Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

7 files changed, 0 insertions, 1776 deletions

diff --git a/qemu/roms/u-boot/include/configs/km/keymile-common.h b/qemu/roms/u-boot/include/configs/km/keymile-common.h
deleted file mode 100644
index 517f46a3a..000000000
--- a/qemu/roms/u-boot/include/configs/km/keymile-common.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_KEYMILE_H
-#define __CONFIG_KEYMILE_H
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DEFAULTENV_VARS
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_SETEXPR
-
-#undef	CONFIG_WATCHDOG		/* disable platform specific watchdog */
-
-#define CONFIG_BOOTDELAY	2 /* autoboot after 2 seconds */
-#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	  */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size  */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		32 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-
-#define CONFIG_HUSH_INIT_VAR
-
-#define CONFIG_SYS_ALT_MEMTEST		/* memory test, takes time */
-
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_LOADS_ECHO
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/* Support the IVM EEprom */
-#define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
-#define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
-#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100
-
-#define	CONFIG_SYS_FLASH_PROTECTION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* UBI Support for all Keymile boards */
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_CONCAT
-
-#define CONFIG_CMD_CRAMFS
-#define CONFIG_CRAMFS_CMDLINE
-
-#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
-#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
-	"actual_bank=0\0"
-#endif
-
-#ifndef CONFIG_KM_DEF_NETDEV
-#define CONFIG_KM_DEF_NETDEV	\
-	"netdev=eth0\0"
-#endif
-
-#ifndef CONFIG_KM_UBI_PARTITION_NAME_BOOT
-#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
-#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */
-
-#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS
-#define CONFIG_KM_UBI_PART_BOOT_OPTS		""
-#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */
-
-#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP
-/* one flash chip only called boot */
-/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
-# define CONFIG_KM_UBI_LINUX_MTD					\
-	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT			\
-	CONFIG_KM_UBI_PART_BOOT_OPTS
-# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
-	"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0"
-#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */
-/* two flash chips called boot and app */
-/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
-/* app:  CONFIG_KM_UBI_PARTITION_NAME_APP */
-# define CONFIG_KM_UBI_LINUX_MTD					\
-	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT			\
-	CONFIG_KM_UBI_PART_BOOT_OPTS " "				\
-	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP
-# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
-	"ubiattach=if test ${boot_bank} -eq 0; then; "			\
-	"ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "; else; "	\
-	"ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0"
-#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */
-
-#ifdef CONFIG_NAND_ECC_BCH
-#define CONFIG_KM_UIMAGE_NAME "ecc_bch_uImage\0"
-#define CONFIG_KM_ECC_MODE    " eccmode=bch"
-#else
-#define CONFIG_KM_UIMAGE_NAME "uImage\0"
-#define CONFIG_KM_ECC_MODE
-#endif
-
-/*
- * boottargets
- * - set 'subbootcmds'
- * - set 'bootcmd' and 'altbootcmd'
- * available targets:
- * - 'release': for a standalone system		kernel/rootfs from flash
- */
-#define CONFIG_KM_DEF_ENV_BOOTTARGETS					\
-	"subbootcmds=ubiattach ubicopy cramfsloadfdt set_fdthigh "	\
-		"cramfsloadkernel flashargs add_default addpanic boot\0"\
-	"develop="							\
-		"tftp 200000 scripts/develop-${arch}.txt && "		\
-		"env import -t 200000 ${filesize} && "			\
-		"run setup_debug_env\0"					\
-	"ramfs="							\
-		"tftp 200000 scripts/ramfs-${arch}.txt && "		\
-		"env import -t 200000 ${filesize} && "			\
-		"run setup_debug_env\0"					\
-	""
-
-/*
- * bootargs
- * - modify 'bootargs'
- *
- * - 'add_default': default bootargs common for all arm/ppc boards
- * - 'addpanic': add kernel panic options
- * - 'flashargs': defaults arguments for flash base boot
- *
- */
-#define CONFIG_KM_DEF_ENV_BOOTARGS					\
-	"add_default="							\
-		"setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off:"				\
-		" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}"	\
-		" mem=${kernelmem} init=${init}"			\
-		CONFIG_KM_ECC_MODE					\
-		" phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\
-		" " CONFIG_KM_UBI_LINUX_MTD " "				\
-		CONFIG_KM_DEF_BOOT_ARGS_CPU				\
-		"\0"							\
-	"addpanic="							\
-		"setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0"	\
-	"flashargs="							\
-		"setenv bootargs "					\
-		"root=mtdblock:rootfs${boot_bank} "			\
-		"rootfstype=squashfs ro\0"				\
-	""
-
-/*
- * flash_boot
- * - commands for booting from flash
- *
- * - 'cramfsloadkernel': copy kernel from a cramfs to ram
- * - 'ubiattach': attach ubi partition
- * - 'ubicopy': copy ubi volume to ram
- *              - volume names: bootfs0, bootfs1, bootfs2, ...
- *
- * processor specific settings
- * - 'cramfsloadfdt': copy fdt from a cramfs to ram
- */
-#define CONFIG_KM_DEF_ENV_FLASH_BOOT					\
-	"cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0"		\
-	"cramfsloadkernel=cramfsload ${load_addr_r} ${uimage}\0"	\
-	"ubicopy=ubi read "__stringify(CONFIG_KM_CRAMFS_ADDR)		\
-			" bootfs${boot_bank}\0"				\
-	"uimage=" CONFIG_KM_UIMAGE_NAME					\
-	CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
-
-/*
- * constants
- * - KM specific constants and commands
- *
- * - 'default': setup default environment
- */
-#define CONFIG_KM_DEF_ENV_CONSTANTS					\
-	"backup_bank=0\0"						\
-	"release=run newenv; reset\0"					\
-	"pnvramsize=" __stringify(CONFIG_KM_PNVRAM) "\0"		\
-	"testbootcmd=setenv boot_bank ${test_bank}; "			\
-		"run ${subbootcmds}; reset\0"				\
-	""
-
-#ifndef CONFIG_KM_DEF_ENV
-#define CONFIG_KM_DEF_ENV	\
-	CONFIG_KM_DEF_ENV_BOOTPARAMS					\
-	CONFIG_KM_DEF_NETDEV						\
-	CONFIG_KM_DEF_ENV_CPU						\
-	CONFIG_KM_DEF_ENV_BOOTTARGETS					\
-	CONFIG_KM_DEF_ENV_BOOTARGS					\
-	CONFIG_KM_DEF_ENV_FLASH_BOOT					\
-	CONFIG_KM_DEF_ENV_CONSTANTS					\
-	"altbootcmd=run bootcmd\0"					\
-	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
-	"bootcmd=km_checkbidhwk &&  "					\
-		"setenv bootcmd \'if km_checktestboot; then; "          \
-				"setenv boot_bank ${test_bank}; else; " \
-				"setenv boot_bank ${actual_bank}; fi;"  \
-			"run ${subbootcmds}; reset\' && "		\
-		"setenv altbootcmd \'setenv boot_bank ${backup_bank}; "	\
-			"run ${subbootcmds}; reset\' && "		\
-		"saveenv && saveenv && boot\0"				\
-	"bootlimit=3\0"							\
-	"cramfsloadfdt="						\
-		"cramfsload ${fdt_addr_r} "				\
-		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
-	"fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0"		\
-	"init=/sbin/init-overlay.sh\0"					\
-	"load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0"		\
-	"load=tftpboot ${load_addr_r} ${u-boot}\0"			\
-	"mtdids=" MTDIDS_DEFAULT "\0"					\
-	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
-	""
-#endif /* CONFIG_KM_DEF_ENV */
-
-#define CONFIG_VERSION_VARIABLE	/* include version env variable */
-
-#endif /* __CONFIG_KEYMILE_H */
diff --git a/qemu/roms/u-boot/include/configs/km/km-powerpc.h b/qemu/roms/u-boot/include/configs/km/km-powerpc.h
deleted file mode 100644
index 763c5bad8..000000000
--- a/qemu/roms/u-boot/include/configs/km/km-powerpc.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_KEYMILE_POWERPC_H
-#define __CONFIG_KEYMILE_POWERPC_H
-
-/* Do boardspecific init for all boards */
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_BOOTCOUNT_LIMIT
-
-#define CONFIG_CMD_DTT
-#define CONFIG_JFFS2_CMDLINE
-
-/* standard km ethernet_present for piggy */
-#define CONFIG_KM_COMMON_ETH_INIT
-
-/* EEprom support 24C08, 24C16, 24C64 */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3  /* 8 Byte write page */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-#define CONFIG_ENV_SIZE		0x04000		/* Size of Environment */
-#define CONFIG_FLASH_CFI_MTD
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000	/* memtest works on */
-
-#define CONFIG_SYS_MEMTEST_END	0x00f00000	/* 1 ... 15 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-
-/* Reserve 4 MB for malloc */
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-
-/******************************************************************************
- * (PRAM usage)
- * ... -------------------------------------------------------
- * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
- * ... |<------------------- pram -------------------------->|
- * ... -------------------------------------------------------
- * @END_OF_RAM:
- * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
- * @CONFIG_KM_PHRAM: address for /var
- * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
- * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
- */
-
-/* size of rootfs in RAM */
-#define CONFIG_KM_ROOTFSSIZE	0x0
-/* pseudo-non volatile RAM [hex] */
-#define CONFIG_KM_PNVRAM	0x80000
-/* physical RAM MTD size [hex] */
-#define CONFIG_KM_PHRAM		0x100000
-/* resereved pram area at the end of memroy [hex] */
-#define CONFIG_KM_RESERVED_PRAM	0x0
-/* enable protected RAM */
-#define CONFIG_PRAM		0
-
-#define CONFIG_KM_CRAMFS_ADDR	0x800000
-#define CONFIG_KM_KERNEL_ADDR	0x400000	/* 3968Kbytes */
-#define CONFIG_KM_FDT_ADDR	0x7E0000	/* 128Kbytes */
-
-/* architecture specific default bootargs */
-#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
-
-#define CONFIG_KM_DEF_ENV_CPU						\
-	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
-	"update="							\
-		"protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
-		"erase " __stringify(BOOTFLASH_START) "  +${filesize} && "\
-		"cp.b ${load_addr_r} " __stringify(BOOTFLASH_START)	\
-		"  ${filesize} && "					\
-		"protect on " __stringify(BOOTFLASH_START) "  +${filesize}\0"\
-	"set_fdthigh=true\0"						\
-	""
-
-#endif /* __CONFIG_KEYMILE_POWERPC_H */
diff --git a/qemu/roms/u-boot/include/configs/km/km8309-common.h b/qemu/roms/u-boot/include/configs/km/km8309-common.h
deleted file mode 100644
index c8df23b53..000000000
--- a/qemu/roms/u-boot/include/configs/km/km8309-common.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (C) 2012 Keymile AG
- *                    Gerlando Falauto <gerlando.falauto@keymile.com>
- *
- * Based on km8321-common.h, see respective copyright notice for credits
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_KM8309_COMMON_H
-#define __CONFIG_KM8309_COMMON_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 family */
-#define CONFIG_QE		1	/* Has QE */
-#define CONFIG_MPC830x		1	/* MPC830x family */
-#define CONFIG_MPC8309		1	/* MPC8309 CPU specific */
-
-#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
-#define CONFIG_CMD_DIAG		1
-
-/* include common defines/options for all 83xx Keymile boards */
-#include "km83xx-common.h"
-
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-/* at end of uboot partition, before env */
-#define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
-
-/*
- * System IO Config
- */
-/* 0x14000180 SICR_1 */
-#define CONFIG_SYS_SICRL (0			\
-		| SICR_1_UART1_UART1RTS		\
-		| SICR_1_I2C_CKSTOP		\
-		| SICR_1_IRQ_A_IRQ		\
-		| SICR_1_IRQ_B_IRQ		\
-		| SICR_1_GPIO_A_GPIO		\
-		| SICR_1_GPIO_B_GPIO		\
-		| SICR_1_GPIO_C_GPIO		\
-		| SICR_1_GPIO_D_GPIO		\
-		| SICR_1_GPIO_E_GPIO		\
-		| SICR_1_GPIO_F_GPIO		\
-		| SICR_1_USB_A_UART2S		\
-		| SICR_1_USB_B_UART2RTS		\
-		| SICR_1_FEC1_FEC1		\
-		| SICR_1_FEC2_FEC2		\
-		)
-
-/* 0x00080400 SICR_2 */
-#define CONFIG_SYS_SICRH (0			\
-		| SICR_2_FEC3_FEC3		\
-		| SICR_2_HDLC1_A_HDLC1		\
-		| SICR_2_ELBC_A_LA		\
-		| SICR_2_ELBC_B_LCLK		\
-		| SICR_2_HDLC2_A_HDLC2		\
-		| SICR_2_USB_D_GPIO		\
-		| SICR_2_PCI_PCI		\
-		| SICR_2_HDLC1_B_HDLC1		\
-		| SICR_2_HDLC1_C_HDLC1		\
-		| SICR_2_HDLC2_B_GPIO		\
-		| SICR_2_HDLC2_C_HDLC2		\
-		| SICR_2_QUIESCE_B		\
-		)
-
-/* GPR_1 */
-#define CONFIG_SYS_GPR1  0x50008060
-
-#define CONFIG_SYS_GP1DIR 0x00000000
-#define CONFIG_SYS_GP1ODR 0x00000000
-#define CONFIG_SYS_GP2DIR 0xFF000000
-#define CONFIG_SYS_GP2ODR 0x00000000
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
-					 SDRAM_CFG_32_BE | \
-					 SDRAM_CFG_SREN | \
-					 SDRAM_CFG_HSE)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
-				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
-					 CSCONFIG_ODT_RD_NEVER | \
-					 CSCONFIG_ODT_WR_ONLY_CURRENT | \
-					 CSCONFIG_ROW_BIT_13 | \
-					 CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE	0x47860242
-#define CONFIG_SYS_DDR_MODE2	0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
-				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
-				 (0 << TIMING_CFG0_WWT_SHIFT) | \
-				 (0 << TIMING_CFG0_RRT_SHIFT) | \
-				 (0 << TIMING_CFG0_WRT_SHIFT) | \
-				 (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
-				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
-				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
-				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
-				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
-				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
-				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
-				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
-				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
-				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
-				 (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-
-#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP	0x80000000
-#define CONFIG_SYS_LCRR_EADC	0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
-
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
-/*
- * MMU Setup
- */
-#define CONFIG_SYS_IBAT7L	(0)
-#define CONFIG_SYS_IBAT7U	(0)
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-#endif /* __CONFIG_KM8309_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/km/km8321-common.h b/qemu/roms/u-boot/include/configs/km/km8321-common.h
deleted file mode 100644
index 149895cb7..000000000
--- a/qemu/roms/u-boot/include/configs/km/km8321-common.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *                    Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- *                    Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- *                    Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * (C) Copyright 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2010
- * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
- *
- * (C) Copyright 2010-2011
- * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_KM8321_COMMON_H
-#define __CONFIG_KM8321_COMMON_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_QE	/* Has QE */
-#define CONFIG_MPC832x	/* MPC832x CPU specific */
-#define CONFIG_KM8321	/* Keymile PBEC8321 board specific */
-
-#define CONFIG_KM_DEF_ARCH	"arch=ppc_8xx\0"
-
-/* include common defines/options for all 83xx Keymile boards */
-#include "km83xx-common.h"
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
-					 SDRAM_CFG_32_BE | \
-					 SDRAM_CFG_SREN | \
-					 SDRAM_CFG_HSE)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
-				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
-					 CSCONFIG_ODT_WR_CFG | \
-					 CSCONFIG_ROW_BIT_13 | \
-					 CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE	0x47860242
-#define CONFIG_SYS_DDR_MODE2	0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
-				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
-				 (0 << TIMING_CFG0_WWT_SHIFT) | \
-				 (0 << TIMING_CFG0_RRT_SHIFT) | \
-				 (0 << TIMING_CFG0_WRT_SHIFT) | \
-				 (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
-				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
-				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
-				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
-				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
-				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
-				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
-				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
-				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
-				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
-				 (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-
-#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP	0x80000000
-#define CONFIG_SYS_LCRR_EADC	0x00010000
-#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
-
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
-/*
- * MMU Setup
- */
-#define CONFIG_SYS_IBAT7L	(0)
-#define CONFIG_SYS_IBAT7U	(0)
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-
-#endif /* __CONFIG_KM8321_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/km/km83xx-common.h b/qemu/roms/u-boot/include/configs/km/km83xx-common.h
deleted file mode 100644
index ae6b6dcf2..000000000
--- a/qemu/roms/u-boot/include/configs/km/km83xx-common.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_KM83XX_H
-#define __CONFIG_KM83XX_H
-
-/* include common defines/options for all Keymile boards */
-#include "keymile-common.h"
-#include "km-powerpc.h"
-
-#ifndef MTDIDS_DEFAULT
-# define MTDIDS_DEFAULT	"nor0=boot"
-#endif /* MTDIDS_DEFAULT */
-
-#ifndef MTDPARTS_DEFAULT
-# define MTDPARTS_DEFAULT	"mtdparts="			\
-	"boot:"							\
-		"768k(u-boot),"					\
-		"128k(env),"					\
-		"128k(envred),"					\
-		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
-#endif /* MTDPARTS_DEFAULT */
-
-#define CONFIG_MISC_INIT_R
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN		66000000
-#define CONFIG_SYS_CLK_FREQ		66000000
-#define CONFIG_83XX_PCICLK		66000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR		0xE0000000
-
-/*
- * Bus Arbitration Configuration Register (ACR)
- */
-#define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
-#define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
-#define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
-#define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
-					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-
-#define CFG_83XX_DDR_USES_CS0
-
-/*
- * Manually set up DDR parameters
- */
-#define CONFIG_DDR_II
-#define CONFIG_SYS_DDR_SIZE		2048 /* MB */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_FLASH_BASE		0xF0000000
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/* Reserve 768 kB for Mon */
-#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus     Machine PortSz  Size  Device
- * ---- ---     ------- ------  -----  ------
- *  0   Local   GPCM    16 bit  256MB FLASH
- *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
- *
- */
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
-#define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
-
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | \
-				BR_PS_16 | /* 16 bit port size */ \
-				BR_MS_GPCM | /* MSEL = GPCM */ \
-				BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
-				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-				OR_GPCM_SCY_5 | \
-				OR_GPCM_TRLX_SET | OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1   /* max num of flash banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-/*
- * PRIO1/PIGGY on the local bus CS1
- */
-/* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_KMBEC_FPGA_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128MB)
-
-#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_KMBEC_FPGA_BASE | \
-				BR_PS_8 | /* 8 bit port size */ \
-				BR_MS_GPCM | /* MSEL = GPCM */ \
-				BR_V)
-#define CONFIG_SYS_OR1_PRELIM	(MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
-				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-				OR_GPCM_SCY_2 | \
-				OR_GPCM_TRLX_SET | OR_GPCM_EAD)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME		"UEC0"
-
-#if !defined(CONFIG_MPC8309)
-#define CONFIG_UEC_ETH1		/* GETH1 */
-#define UEC_VERBOSE_DEBUG	1
-#endif
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
-#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
-#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR	0
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
-#endif
-
-/*
- * Environment
- */
-
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
-					CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
-#define CONFIG_ENV_OFFSET	(CONFIG_SYS_MONITOR_LEN)
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
-						CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#else /* CFG_SYS_RAMBOOT */
-#define CONFIG_SYS_NO_FLASH		/* Flash is not usable now */
-#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE		0x2000
-#endif /* CFG_SYS_RAMBOOT */
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_NUM_I2C_BUSES	4
-#define CONFIG_SYS_I2C_MAX_HOPS		1
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	200000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-#define CONFIG_SYS_I2C_OFFSET		0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED	200000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
-#define CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
-		{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
-		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
-		{1, {I2C_NULL_HOP} } }
-
-#define CONFIG_KM_IVM_BUS		2	/* I2C2 (Mux-Port 1)*/
-
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75		/* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS	{0, 1, 2, 3}	/* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP	70
-#define CONFIG_SYS_DTT_HYSTERESIS	3
-#define CONFIG_SYS_DTT_BUS_NUM		1
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
-#endif
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT		0x000000000
-#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
-					 HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2			HID2_HBE
-
-/*
- * MMU Setup
- */
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
-				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
-					BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
-				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
-					| BATU_VP)
-#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
-
-/* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
-				BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
-				BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
-					BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
-					BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
-				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
-					BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
-
-/*
- * Internal Definitions
- */
-#define BOOTFLASH_START	0xF0000000
-
-#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
-#define CONFIG_KM_DEF_ENV "km-common=empty\0"
-#endif
-
-#ifndef CONFIG_KM_DEF_ARCH
-#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	CONFIG_KM_DEF_ENV						\
-	CONFIG_KM_DEF_ARCH						\
-	"newenv="							\
-		"prot off 0xF00C0000 +0x40000 && "			\
-		"era 0xF00C0000 +0x40000\0"				\
-	"unlock=yes\0"							\
-	""
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#endif
-
-#endif /* __CONFIG_KM83XX_H */
diff --git a/qemu/roms/u-boot/include/configs/km/km_arm.h b/qemu/roms/u-boot/include/configs/km/km_arm.h
deleted file mode 100644
index 6d77680c8..000000000
--- a/qemu/roms/u-boot/include/configs/km/km_arm.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2010-2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * for linking errors see
- * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
- */
-
-#ifndef _CONFIG_KM_ARM_H
-#define _CONFIG_KM_ARM_H
-
-/* We got removed from Linux mach-types.h */
-#define MACH_TYPE_KM_KIRKWOOD          2255
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_MARVELL
-#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
-#define CONFIG_KIRKWOOD			/* SOC Family Name */
-#define CONFIG_KW88F6281		/* SOC Name */
-#define CONFIG_MACH_KM_KIRKWOOD		/* Machine type */
-
-#define CONFIG_MACH_TYPE	MACH_TYPE_KM_KIRKWOOD
-
-#define CONFIG_NAND_ECC_BCH
-#define CONFIG_BCH
-
-/* include common defines/options for all Keymile boards */
-#include "keymile-common.h"
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_SF
-
-/* SPI NOR Flash default params, used by sf commands */
-#define CONFIG_SF_DEFAULT_SPEED		8100000
-#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
-
-#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define CONFIG_ENV_SPI_BUS		0
-#define CONFIG_ENV_SPI_CS		0
-#define CONFIG_ENV_SPI_MAX_HZ		8100000
-#define CONFIG_ENV_SPI_MODE		SPI_MODE_3
-#endif
-
-/* Reserve 4 MB for malloc */
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-
-#include "asm/arch/config.h"
-
-#define CONFIG_SYS_TEXT_BASE	0x07d00000	/* code address before reloc */
-#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
-#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
-#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
-
-/* pseudo-non volatile RAM [hex] */
-#define CONFIG_KM_PNVRAM	0x80000
-/* physical RAM MTD size [hex] */
-#define CONFIG_KM_PHRAM		0x17F000
-
-#define CONFIG_KM_CRAMFS_ADDR	0x2400000
-#define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 3098KBytes */
-#define CONFIG_KM_FDT_ADDR	0x23E0000	/*  128KBytes */
-
-/* architecture specific default bootargs */
-#define CONFIG_KM_DEF_BOOT_ARGS_CPU					\
-		"bootcountaddr=${bootcountaddr} ${mtdparts}"		\
-		" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
-
-#define CONFIG_KM_DEF_ENV_CPU						\
-	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0"		\
-	CONFIG_KM_UPDATE_UBOOT						\
-	"set_fdthigh=setenv fdt_high ${kernelmem}\0"			\
-	""
-
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
-#define CONFIG_MISC_INIT_R
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2		KW_UART1_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_CONS_INDEX	1	/* Console on UART0 */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_BOOTMAPSZ	(8 << 20)	/* Initial Memmap for Linux */
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
-#define CONFIG_INITRD_TAG		/* enable INITRD tag */
-#define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
-
-/*
- * Commands configuration
- */
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_NFS
-
-/*
- * Without NOR FLASH we need this
- */
-#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-
-/*
- * NAND Flash configuration
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-#define BOOTFLASH_START		0x0
-
-/* Kirkwood has two serial IF */
-#if (CONFIG_CONS_INDEX == 2)
-#define CONFIG_KM_CONSOLE_TTY	"ttyS1"
-#else
-#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
-#endif
-
-/*
- * Other required minimal configurations
- */
-#define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
-#define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
-#define CONFIG_ARCH_MISC_INIT		/* call arch_misc_init() */
-#define CONFIG_DISPLAY_CPUINFO		/* Display cpu info */
-#define CONFIG_NR_DRAM_BANKS	4
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
-
-/*
- * Ethernet Driver configuration
- */
-#define CONFIG_NETCONSOLE	/* include NetConsole support   */
-#define CONFIG_MII		/* expose smi ove miiphy interface */
-#define CONFIG_CMD_MII		/* to debug mdio phy config */
-#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
-#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR	0
-#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
-#define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
-
-/*
- * UBI related stuff
- */
-#define CONFIG_SYS_USE_UBI
-
-/*
- * I2C related stuff
- */
-#undef CONFIG_I2C_MVTWSI
-#define CONFIG_SYS_I2C
-#define	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged	*/
-#define CONFIG_SYS_I2C_INIT_BOARD
-
-#define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
-#define CONFIG_SYS_NUM_I2C_BUSES	6
-#define CONFIG_SYS_I2C_MAX_HOPS		1
-#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
-					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
-					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
-					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
-					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
-					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
-				}
-
-#ifndef __ASSEMBLY__
-#include <asm/arch-kirkwood/gpio.h>
-extern void __set_direction(unsigned pin, int high);
-void set_sda(int state);
-void set_scl(int state);
-int get_sda(void);
-int get_scl(void);
-#define KM_KIRKWOOD_SDA_PIN	8
-#define KM_KIRKWOOD_SCL_PIN	9
-#define KM_KIRKWOOD_SOFT_I2C_GPIOS	0x0300
-#define KM_KIRKWOOD_ENV_WP	38
-
-#define I2C_ACTIVE	__set_direction(KM_KIRKWOOD_SDA_PIN, 0)
-#define I2C_TRISTATE	__set_direction(KM_KIRKWOOD_SDA_PIN, 1)
-#define I2C_READ	(kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
-#define I2C_SDA(bit)	kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
-#define I2C_SCL(bit)	kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
-#endif
-
-#define I2C_DELAY	udelay(1)
-#define I2C_SOFT_DECLARATIONS
-
-#define	CONFIG_SYS_I2C_SOFT_SLAVE	0x0
-#define	CONFIG_SYS_I2C_SOFT_SPEED	100000
-
-/* EEprom support 24C128, 24C256 valid for environment eeprom */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6 /* 64 Byte write page */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
-
-/*
- *  Environment variables configurations
- */
-#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define CONFIG_ENV_IS_IN_SPI_FLASH  /* use SPI-Flash for environment vars */
-#define CONFIG_ENV_OFFSET		0xc0000     /* no bracets! */
-#define CONFIG_ENV_SIZE			0x02000     /* Size of Environment */
-#define CONFIG_ENV_SECT_SIZE		0x10000
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
-					CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_TOTAL_SIZE		0x20000     /* no bracets! */
-#else
-#define CONFIG_ENV_IS_IN_EEPROM		/* use EEPROM for environment vars */
-#define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_EEPROM_WREN
-#define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
-#define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
-#define CONFIG_I2C_ENV_EEPROM_BUS	KM_ENV_BUS
-#define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
-#endif
-
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-
-/* SPI bus claim MPP configuration */
-#define CONFIG_SYS_KW_SPI_MPP	0x0
-
-#define FLASH_GPIO_PIN			0x00010000
-#define KM_FLASH_GPIO_PIN	16
-
-#ifndef MTDIDS_DEFAULT
-# define MTDIDS_DEFAULT		"nand0=orion_nand"
-#endif /* MTDIDS_DEFAULT */
-
-#ifndef MTDPARTS_DEFAULT
-# define MTDPARTS_DEFAULT	"mtdparts="			\
-	"orion_nand:"						\
-		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
-#endif /* MTDPARTS_DEFAULT */
-
-#define	CONFIG_KM_UPDATE_UBOOT						\
-	"update="							\
-		"sf probe 0;sf erase 0 +${filesize};"			\
-		"sf write ${load_addr_r} 0 ${filesize};\0"
-
-#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
-#define CONFIG_KM_NEW_ENV						\
-	"newenv=sf probe 0;"						\
-		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
-		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
-#else
-#define CONFIG_KM_NEW_ENV						\
-	"newenv=setenv addr 0x100000 && "				\
-		"i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; "  \
-		"mw.b ${addr} 0 4 && "					\
-		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
-		" ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && "	\
-		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
-		" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
-#endif
-
-#ifndef CONFIG_KM_BOARD_EXTRA_ENV
-#define CONFIG_KM_BOARD_EXTRA_ENV       ""
-#endif
-
-/*
- * Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_KM_BOARD_EXTRA_ENV					\
-	CONFIG_KM_DEF_ENV						\
-	CONFIG_KM_NEW_ENV						\
-	"arch=arm\0"							\
-	""
-
-#if defined(CONFIG_SYS_NO_FLASH)
-#undef	CONFIG_FLASH_CFI_MTD
-#undef	CONFIG_JFFS2_CMDLINE
-#endif
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Do early setups now in board_init_f() */
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/*
- * resereved pram area at the end of memroy [hex]
- * 8Mbytes for switch + 4Kbytes for bootcount
- */
-#define CONFIG_KM_RESERVED_PRAM 0x801000
-/* address for the bootcount (taken from end of RAM) */
-#define BOOTCOUNT_ADDR          (CONFIG_KM_RESERVED_PRAM)
-/* Use generic bootcount RAM driver */
-#define CONFIG_BOOTCOUNT_RAM
-
-/* enable POST tests */
-#define CONFIG_POST	(CONFIG_SYS_POST_MEM_REGIONS)
-#define CONFIG_POST_SKIP_ENV_FLAGS
-#define CONFIG_POST_EXTERNAL_WORD_FUNCS
-#define CONFIG_CMD_DIAG
-
-/* we do the whole PCIe FPGA config stuff here */
-#define	CONFIG_BOARD_LATE_INIT
-
-#endif /* _CONFIG_KM_ARM_H */
diff --git a/qemu/roms/u-boot/include/configs/km/kmp204x-common.h b/qemu/roms/u-boot/include/configs/km/kmp204x-common.h
deleted file mode 100644
index efd96352e..000000000
--- a/qemu/roms/u-boot/include/configs/km/kmp204x-common.h
+++ /dev/null
@@ -1,465 +0,0 @@
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _CONFIG_KMP204X_H
-#define _CONFIG_KMP204X_H
-
-#define CONFIG_PHYS_64BIT
-#define CONFIG_PPC_P2041
-
-#define CONFIG_SYS_TEXT_BASE	0xfff80000
-
-#define CONFIG_KM_DEF_NETDEV	"netdev=eth0\0"
-
-/* an additionnal option is required for UBI as subpage access is
- * supported in u-boot */
-#define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
-
-#define CONFIG_NAND_ECC_BCH
-
-/* common KM defines */
-#include "keymile-common.h"
-
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500			/* BOOKE e500 family */
-#define CONFIG_E500MC			/* BOOKE e500mc family */
-#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
-#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
-#define CONFIG_MP			/* support multiple processors */
-
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
-#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
-#define CONFIG_PCI			/* Enable PCI/PCIE */
-#define CONFIG_PCIE1			/* PCIE controler 1 */
-#define CONFIG_PCIE3			/* PCIE controler 3 */
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_DPAA_RMAN		/* RMan */
-
-#define CONFIG_FSL_LAW			/* Use common FSL init code */
-
-/* Environment in SPI Flash */
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_BUS              0
-#define CONFIG_ENV_SPI_CS               0
-#define CONFIG_ENV_SPI_MAX_HZ           20000000
-#define CONFIG_ENV_SPI_MODE             0
-#define CONFIG_ENV_OFFSET               0x100000	/* 1MB for u-boot */
-#define CONFIG_ENV_SIZE			0x004000	/* 16K env */
-#define CONFIG_ENV_SECT_SIZE            0x010000
-#define CONFIG_ENV_OFFSET_REDUND	0x110000
-#define CONFIG_ENV_TOTAL_SIZE		0x020000
-
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
-#define CONFIG_BTB			/* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
-
-#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS	/* POST memory regions test */
-
-/*
- *  Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
-		CONFIG_RAMBOOT_TEXT_BASE)
-#define CONFIG_SYS_L3_SIZE		(1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
-
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
-#define CONFIG_FSL_DDR_INTERACTIVE
-
-#define CONFIG_SYS_SPD_BUS_NUM	0
-#define SPD_EEPROM_ADDRESS	0x54
-#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
-
-/******************************************************************************
- * (PRAM usage)
- * ... -------------------------------------------------------
- * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
- * ... |<------------------- pram -------------------------->|
- * ... -------------------------------------------------------
- * @END_OF_RAM:
- * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
- * @CONFIG_KM_PHRAM: address for /var
- * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
- * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
- */
-
-/* size of rootfs in RAM */
-#define CONFIG_KM_ROOTFSSIZE	0x0
-/* pseudo-non volatile RAM [hex] */
-#define CONFIG_KM_PNVRAM	0x80000
-/* physical RAM MTD size [hex] */
-#define CONFIG_KM_PHRAM		0x100000
-/* reserved pram area at the end of memory [hex]
- * u-boot reserves some memory for the MP boot page */
-#define CONFIG_KM_RESERVED_PRAM	0x1000
-/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
- * is not valid yet, which is the case for when u-boot copies itself to RAM */
-#define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
-
-#define CONFIG_KM_CRAMFS_ADDR	0x2000000
-#define CONFIG_KM_KERNEL_ADDR	0x1000000	/* max kernel size 15.5Mbytes */
-#define CONFIG_KM_FDT_ADDR	0x1F80000	/* max dtb    size  0.5Mbytes */
-
-/*
- * Local Bus Definitions
- */
-
-/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
-#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_8 | LCRR_EADC_2)
-
-/* Nand Flash */
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE		0xffa00000
-#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
-
-#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
-
-#define CONFIG_BCH
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-			       | BR_PS_8	       /* Port Size = 8 bit */ \
-			       | BR_MS_FCM	       /* MSEL = FCM */ \
-			       | BR_V)		       /* valid */
-
-#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB	      /* length 256K */ \
-			       | OR_FCM_BCTLD	/* LBCTL not ass */	\
-			       | OR_FCM_SCY_1	/* 1 clk wait cycle */	\
-			       | OR_FCM_RST	/* 1 clk read setup */	\
-			       | OR_FCM_PGS	/* Large page size */	\
-			       | OR_FCM_CST)	/* 0.25 command setup */
-
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* QRIO FPGA */
-#define CONFIG_SYS_QRIO_BASE		0xfb000000
-#define CONFIG_SYS_QRIO_BASE_PHYS	0xffb000000ull
-
-#define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
-				| BR_PS_8	/* Port Size 8 bits */ \
-				| BR_DECC_OFF	/* no error corr */ \
-				| BR_MS_GPCM	/* MSEL = GPCM */ \
-				| BR_V)		/* valid */
-
-#define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB	/* length 64K */ \
-				| OR_GPCM_BCTLD /* no LCTL assert */ \
-				| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
-				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
-				| OR_GPCM_TRLX /* relaxed tmgs */ \
-				| OR_GPCM_EAD) /* extra bus clk cycles */
-
-#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
-#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
-
-/* bootcounter in QRIO */
-#define CONFIG_BOOTCOUNT_LIMIT
-#define CONFIG_SYS_BOOTCOUNT_ADDR	(CONFIG_SYS_QRIO_BASE + 0x20)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
-#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-#define CONFIG_LAST_STAGE_INIT
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
-
-#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
-
-/* I2C */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED		100000 /* deblocking */
-#define CONFIG_SYS_NUM_I2C_BUSES	3
-#define CONFIG_SYS_I2C_MAX_HOPS		1
-#define CONFIG_SYS_I2C_FSL		/* Use FSL I2C driver */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
-#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
-					{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
-					{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
-				}
-#ifndef __ASSEMBLY__
-void set_sda(int state);
-void set_scl(int state);
-int get_sda(void);
-int get_scl(void);
-#endif
-
-#define CONFIG_KM_IVM_BUS		1	/* I2C1 (Mux-Port 1)*/
-
-/*
- * eSPI - Enhanced SPI
- */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_BAR	/* 4 byte-addressing */
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED         20000000
-#define CONFIG_SF_DEFAULT_MODE          0
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8010000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-
-/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS	10
-#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
-#define CONFIG_SYS_QMAN_NUM_PORTALS	10
-#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
-#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver
- * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
- * ucode is stored after env, so we got 0x120000.
- */
-#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_FMAN_FW_ADDR	0x120000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
-#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
-#define CONFIG_FMAN_ENET
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP			/* do pci plug-and-play */
-#define CONFIG_E1000
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
-
-/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x11
-#define CONFIG_SYS_TBIPA_VALUE	8
-#define CONFIG_PHYLIB		/* recommended PHY management */
-#define CONFIG_ETHPRIME		"FM1@DTSEC5"
-#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO		/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
-
-/*
- * additionnal command line configuration.
- */
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_ERRATA
-
-/* we don't need flash support */
-#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_FLASH_CFI_MTD
-#undef CONFIG_JFFS2_CMDLINE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-#define __USB_PHY_TYPE	utmi
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
-#define CONFIG_KM_DEF_ENV "km-common=empty\0"
-#endif
-
-#ifndef MTDIDS_DEFAULT
-# define MTDIDS_DEFAULT		"nand0=fsl_elbc_nand"
-#endif /* MTDIDS_DEFAULT */
-
-#ifndef MTDPARTS_DEFAULT
-# define MTDPARTS_DEFAULT	"mtdparts="			\
-	"fsl_elbc_nand:"						\
-		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
-#endif /* MTDPARTS_DEFAULT */
-
-/* architecture specific default bootargs */
-#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
-
-/* FIXME: FDT_ADDR is unspecified */
-#define CONFIG_KM_DEF_ENV_CPU						\
-	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
-	"cramfsloadfdt="						\
-		"cramfsload ${fdt_addr_r} "				\
-		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
-	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
-	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0"		\
-	"update="							\
-		"sf probe 0;sf erase 0 +${filesize};"			\
-		"sf write ${load_addr_r} 0 ${filesize};\0"		\
-	"set_fdthigh=true\0"						\
-	""
-
-#define CONFIG_HW_ENV_SETTINGS						\
-	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"			\
-	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
-	"usb_dr_mode=host\0"
-
-#define CONFIG_KM_NEW_ENV						\
-	"newenv=sf probe 0;"						\
-		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
-		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
-
-/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
-#ifndef CONFIG_KM_DEF_ARCH
-#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_KM_DEF_ENV						\
-	CONFIG_KM_DEF_ARCH						\
-	CONFIG_KM_NEW_ENV						\
-	CONFIG_HW_ENV_SETTINGS						\
-	"EEprom_ivm=pca9547:70:9\0"					\
-	""
-
-#endif /* _CONFIG_KMP204X_H */