diff options
| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/include/configs/P5020DS.h | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/include/configs/P5020DS.h')
| -rw-r--r-- | qemu/roms/u-boot/include/configs/P5020DS.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/include/configs/P5020DS.h b/qemu/roms/u-boot/include/configs/P5020DS.h new file mode 100644 index 000000000..588df809d --- /dev/null +++ b/qemu/roms/u-boot/include/configs/P5020DS.h @@ -0,0 +1,31 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * P5020 DS board configuration file + * Also supports P5010 DS + */ +#define CONFIG_P5020DS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P5020 + +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_MMC +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE3 +#define CONFIG_PCIE4 +#define CONFIG_SYS_FSL_RAID_ENGINE +#define CONFIG_SYS_DPAA_RMAN + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" |