diff options
author | Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
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committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/drivers/twserial | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/drivers/twserial')
-rw-r--r-- | qemu/roms/u-boot/drivers/twserial/Makefile | 8 | ||||
-rw-r--r-- | qemu/roms/u-boot/drivers/twserial/soft_tws.c | 94 |
2 files changed, 102 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/drivers/twserial/Makefile b/qemu/roms/u-boot/drivers/twserial/Makefile new file mode 100644 index 000000000..7cc7c4de8 --- /dev/null +++ b/qemu/roms/u-boot/drivers/twserial/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2009 +# Detlev Zundel, DENX Software Engineering, dzu@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SOFT_TWS) += soft_tws.o diff --git a/qemu/roms/u-boot/drivers/twserial/soft_tws.c b/qemu/roms/u-boot/drivers/twserial/soft_tws.c new file mode 100644 index 000000000..d0bf93d90 --- /dev/null +++ b/qemu/roms/u-boot/drivers/twserial/soft_tws.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2009 + * Detlev Zundel, DENX Software Engineering, dzu@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define TWS_IMPLEMENTATION +#include <common.h> + +/*=====================================================================*/ +/* Public Functions */ +/*=====================================================================*/ + +/*----------------------------------------------------------------------- + * Read bits + */ +int tws_read(uchar *buffer, int len) +{ + int rem = len; + uchar accu, shift; + + debug("tws_read: buffer %p len %d\n", buffer, len); + + /* Configure the data pin for input */ + tws_data_config_output(0); + + /* Disable WR, i.e. setup a read */ + tws_wr(0); + udelay(1); + + /* Rise CE */ + tws_ce(1); + udelay(1); + + for (; rem > 0; ) { + for (shift = 0, accu = 0; + (rem > 0) && (shift < 8); + rem--, shift++) { + tws_clk(1); + udelay(10); + accu |= (tws_data_read() << shift); /* LSB first */ + tws_clk(0); + udelay(10); + } + *buffer++ = accu; + } + + /* Lower CE */ + tws_ce(0); + + return len - rem; +} + + +/*----------------------------------------------------------------------- + * Write bits + */ +int tws_write(uchar *buffer, int len) +{ + int rem = len; + uchar accu, shift; + + debug("tws_write: buffer %p len %d\n", buffer, len); + + /* Configure the data pin for output */ + tws_data_config_output(1); + + /* Enable WR, i.e. setup a write */ + tws_wr(1); + udelay(1); + + /* Rise CE */ + tws_ce(1); + udelay(1); + + for (; rem > 0; ) { + for (shift = 0, accu = *buffer++; + (rem > 0) && (shift < 8); + rem--, shift++) { + tws_data(accu & 0x01); /* LSB first */ + tws_clk(1); + udelay(10); + tws_clk(0); + udelay(10); + accu >>= 1; + } + } + + /* Lower CE */ + tws_ce(0); + + return len - rem; +} |