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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/drivers/sound/wm8994.h
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/drivers/sound/wm8994.h')
-rw-r--r--qemu/roms/u-boot/drivers/sound/wm8994.h69
1 files changed, 69 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/drivers/sound/wm8994.h b/qemu/roms/u-boot/drivers/sound/wm8994.h
new file mode 100644
index 000000000..6d0c7ca27
--- /dev/null
+++ b/qemu/roms/u-boot/drivers/sound/wm8994.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chadrasekar <rcsekar@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __WM8994_H__
+#define __WM8994_H__
+
+/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
+#define WM8994_SYSCLK_MCLK1 1
+#define WM8994_SYSCLK_MCLK2 2
+#define WM8994_SYSCLK_FLL1 3
+#define WM8994_SYSCLK_FLL2 4
+
+/* Avilable audi interface ports in wm8994 codec */
+enum en_audio_interface {
+ WM8994_AIF1 = 1,
+ WM8994_AIF2,
+ WM8994_AIF3
+};
+
+/* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */
+#define WM8994_SYSCLK_OPCLK 5
+
+#define WM8994_FLL1 1
+#define WM8994_FLL2 2
+
+#define WM8994_FLL_SRC_MCLK1 1
+#define WM8994_FLL_SRC_MCLK2 2
+#define WM8994_FLL_SRC_LRCLK 3
+#define WM8994_FLL_SRC_BCLK 4
+
+/* maximum available digital interfac in the dac to configure */
+#define WM8994_MAX_AIF 2
+
+#define WM8994_MAX_INPUT_CLK_FREQ 13500000
+#define WM8994_ID 0x8994
+
+enum wm8994_vmid_mode {
+ WM8994_VMID_NORMAL,
+ WM8994_VMID_FORCE,
+};
+
+/* wm 8994 family devices */
+enum wm8994_type {
+ WM8994 = 0,
+ WM8958 = 1,
+ WM1811 = 2,
+};
+
+/*
+ * intialise wm8994 sound codec device for the given configuration
+ *
+ * @param blob FDT node for codec values
+ * @param aif_id enum value of codec interface port in which
+ * soc i2s is connected
+ * @param sampling_rate Sampling rate ranges between from 8khz to 96khz
+ * @param mclk_freq Master clock frequency.
+ * @param bits_per_sample bits per Sample can be 16 or 24
+ * @param channels Number of channnels, maximum 2
+ *
+ * @returns -1 for error and 0 Success.
+ */
+int wm8994_init(const void *blob, enum en_audio_interface aif_id,
+ int sampling_rate, int mclk_freq,
+ int bits_per_sample, unsigned int channels);
+#endif /*__WM8994_H__ */