summaryrefslogtreecommitdiffstats
path: root/qemu/roms/u-boot/drivers/gpio/mvgpio.h
diff options
context:
space:
mode:
authorRajithaY <rajithax.yerrumsetty@intel.com>2017-04-25 03:31:15 -0700
committerRajitha Yerrumchetty <rajithax.yerrumsetty@intel.com>2017-05-22 06:48:08 +0000
commitbb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch)
treeca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/u-boot/drivers/gpio/mvgpio.h
parenta14b48d18a9ed03ec191cf16b162206998a895ce (diff)
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to kvmfornfv repo and make use of the updated latest qemu for the execution of all testcase Change-Id: I1280af507a857675c7f81d30c95255635667bdd7 Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/drivers/gpio/mvgpio.h')
-rw-r--r--qemu/roms/u-boot/drivers/gpio/mvgpio.h58
1 files changed, 0 insertions, 58 deletions
diff --git a/qemu/roms/u-boot/drivers/gpio/mvgpio.h b/qemu/roms/u-boot/drivers/gpio/mvgpio.h
deleted file mode 100644
index a3f17a0c3..000000000
--- a/qemu/roms/u-boot/drivers/gpio/mvgpio.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2011
- * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
- *
- * (C) Copyright 2010
- * Marvell Semiconductor <www.marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MVGPIO_H__
-#define __MVGPIO_H__
-
-#include <common.h>
-
-#ifdef CONFIG_SHEEVA_88SV331xV5
-/*
- * GPIO Register map for SHEEVA 88SV331xV5
- */
-struct gpio_reg {
- u32 gplr; /* Pin Level Register - 0x0000 */
- u32 pad0[2];
- u32 gpdr; /* Pin Direction Register - 0x000C */
- u32 pad1[2];
- u32 gpsr; /* Pin Output Set Register - 0x0018 */
- u32 pad2[2];
- u32 gpcr; /* Pin Output Clear Register - 0x0024 */
- u32 pad3[2];
- u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */
- u32 pad4[2];
- u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */
- u32 pad5[2];
- u32 gedr; /* Edge Detect Status Register - 0x0048 */
- u32 pad6[2];
- u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */
- u32 pad7[2];
- u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */
- u32 pad8[2];
- u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable
- Register - 0x006C */
- u32 pad9[2];
- u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable
- Register - 0x0078 */
- u32 pad10[2];
- u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable
- Register - 0x0084 */
- u32 pad11[2];
- u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable
- Register - 0x0090 */
- u32 pad12[2];
- u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */
-};
-#else
-#error "CPU core subversion not defined"
-#endif
-
-#endif /* __MVGPIO_H__ */