Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

4 files changed, 265 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/vpac270/Makefile b/qemu/roms/u-boot/board/vpac270/Makefile
new file mode 100644
index 000000000..ad7f7d8d6
--- /dev/null
+++ b/qemu/roms/u-boot/board/vpac270/Makefile
@@ -0,0 +1,13 @@
+#
+# Voipac PXA270 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifndef	CONFIG_SPL_BUILD
+obj-y	:= vpac270.o
+else
+obj-y	:= onenand.o
+endif
diff --git a/qemu/roms/u-boot/board/vpac270/onenand.c b/qemu/roms/u-boot/board/vpac270/onenand.c
new file mode 100644
index 000000000..a749b310c
--- /dev/null
+++ b/qemu/roms/u-boot/board/vpac270/onenand.c
@@ -0,0 +1,46 @@
+/*
+ * Voipac PXA270 OneNAND SPL
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <onenand_uboot.h>
+#include <asm/arch/pxa.h>
+
+void board_init_f(unsigned long unused)
+{
+	extern uint32_t _end;
+	uint32_t tmp;
+
+	asm volatile("mov %0, pc" : "=r"(tmp));
+	tmp >>= 24;
+
+	/* The code runs from OneNAND RAM, copy SPL to SRAM and execute it. */
+	if (tmp == 0) {
+		tmp = (uint32_t)&_end - CONFIG_SPL_TEXT_BASE;
+		onenand_spl_load_image(0, tmp, (void *)CONFIG_SPL_TEXT_BASE);
+		asm volatile("mov pc, %0" : : "r"(CONFIG_SPL_TEXT_BASE));
+	}
+
+	/* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */
+	arch_cpu_init();
+	pxa2xx_dram_init();
+	onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR,
+				CONFIG_SPL_ONENAND_LOAD_SIZE,
+				(void *)CONFIG_SYS_TEXT_BASE);
+	asm volatile("mov pc, %0" : : "r"(CONFIG_SYS_TEXT_BASE));
+
+	for (;;)
+		;
+}
+
+void __attribute__((noreturn)) hang(void)
+{
+	for (;;)
+		;
+}
diff --git a/qemu/roms/u-boot/board/vpac270/u-boot-spl.lds b/qemu/roms/u-boot/board/vpac270/u-boot-spl.lds
new file mode 100644
index 000000000..5dbf94e44
--- /dev/null
+++ b/qemu/roms/u-boot/board/vpac270/u-boot-spl.lds
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = CONFIG_SPL_TEXT_BASE;
+	.text.0	:
+	{
+		arch/arm/cpu/pxa/start.o		(.text*)
+		arch/arm/lib/built-in.o			(.text*)
+		board/vpac270/built-in.o		(.text*)
+		drivers/mtd/onenand/built-in.o		(.text*)
+	}
+
+
+	/* Start of the rest of the SPL */
+	. = CONFIG_SPL_TEXT_BASE + 0x800;
+
+	.text.1	:
+	{
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	__image_copy_end = .;
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	. = ALIGN(0x800);
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		__bss_end = .;
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/qemu/roms/u-boot/board/vpac270/vpac270.c b/qemu/roms/u-boot/board/vpac270/vpac270.c
new file mode 100644
index 000000000..8d777df84
--- /dev/null
+++ b/qemu/roms/u-boot/board/vpac270/vpac270.c
@@ -0,0 +1,126 @@
+/*
+ * Voipac PXA270 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/pxa.h>
+#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* Arch number of vpac270 */
+	gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+#ifndef	CONFIG_ONENAND
+	pxa2xx_dram_init();
+#endif
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#ifdef	CONFIG_RAM_256M
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+}
+
+#ifdef	CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+	pxa_mmc_register(0);
+	return 0;
+}
+#endif
+
+#ifdef	CONFIG_CMD_USB
+int board_usb_init(int index, enum usb_init_type init)
+{
+	writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		;
+
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+	/* Clear any OTG Pin Hold */
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+	/* Set port power control mask bits, only 3 ports. */
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+	/* enable port 2 */
+	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+
+void usb_board_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
+	udelay(10);
+
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+	return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif