Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

6 files changed, 0 insertions, 1507 deletions

diff --git a/qemu/roms/u-boot/board/ti/am335x/Makefile b/qemu/roms/u-boot/board/ti/am335x/Makefile
deleted file mode 100644
index 804ac379d..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Makefile
-#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
-obj-y	:= mux.o
-endif
-
-obj-y	+= board.o
diff --git a/qemu/roms/u-boot/board/ti/am335x/README b/qemu/roms/u-boot/board/ti/am335x/README
deleted file mode 100644
index 947305b58..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/README
+++ /dev/null
@@ -1,205 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'am335x_evm' build, and some of
-the related build targets (am335x_evm_uartN, etc).
-
-Hardware
-========
-
-The binary produced by this board supports, based on parsing of the EEPROM
-documented in TI's reference designs:
-- AM335x GP EVM
-- AM335x EVM SK
-- Beaglebone White
-- Beaglebone Black
-
-Customization
-=============
-
-Given that all of the above boards are reference platforms (and the
-Beaglebone platforms are OSHA), it is likely that this platform code and
-configuration will be used as the basis of a custom platform.  It is
-worth noting that aside from things such as NAND or MMC only being
-required if a custom platform makes use of these blocks, the following
-are required, depending on design:
-
-- GPIO is only required if DDR3 power is controlled in a way similar to
-  EVM SK
-- SPI is only required for SPI flash, or exposing the SPI bus.
-
-The following blocks are required:
-- I2C, to talk with the PMIC and ensure that we do not run afoul of
-  errata 1.0.24.
-
-When removing options as part of customization,
-CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
-needs and to remove no longer relevant options as in some cases we
-define additional text blocks (such as for NAND or DFU strings).  Also
-note that all of the SPL options are grouped together, rather than with
-the IP blocks, so both areas will need their choices updated to reflect
-the custom design.
-
-NAND
-====
-
-The AM335x GP EVM ships with a 256MiB NAND available in most profiles.  In
-this example to program the NAND we assume that an SD card has been
-inserted with the files to write in the first SD slot and that mtdparts
-have been configured correctly for the board. All images are first loaded
-into memory, then written to NAND.
-
-Step-1: Building u-boot for NAND boot
-	Set following CONFIGxx options for NAND device.
-	CONFIG_SYS_NAND_PAGE_SIZE	number of main bytes in NAND page
-	CONFIG_SYS_NAND_OOBSIZE		number of OOB bytes in NAND page
-	CONFIG_SYS_NAND_BLOCK_SIZE	number of bytes in NAND erase-block
-	CONFIG_SYS_NAND_ECCPOS		ECC map for NAND page
-	CONFIG_NAND_OMAP_ECCSCHEME	(refer doc/README.nand)
-
-Step-2: Flashing NAND via MMC/SD
-	# select BOOTSEL to MMC/SD boot and boot from MMC/SD card
-	U-Boot # mmc rescan
-	# erase flash
-	U-Boot # nand erase.chip
-	U-Boot # env default -f -a
-	U-Boot # saveenv
-	# flash MLO. Redundant copies of MLO are kept for failsafe
-	U-Boot # load mmc 0 0x82000000 MLO
-	U-Boot # nand write 0x82000000 0x00000 0x20000
-	U-Boot # nand write 0x82000000 0x20000 0x20000
-	U-Boot # nand write 0x82000000 0x40000 0x20000
-	U-Boot # nand write 0x82000000 0x60000 0x20000
-	# flash u-boot.img
-	U-Boot # load mmc 0 0x82000000 u-boot.img
-	U-Boot # nand write 0x82000000 0x80000 0x60000
-	# flash kernel image
-	U-Boot # load mmc 0 0x82000000 uImage
-	U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize}
-	# flash filesystem image
-	U-Boot # load mmc 0 0x82000000 filesystem.img
-	U-Boot # nand write 0x82000000 ${loadaddress} 0x300000
-
-Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
-	The device should boot from images flashed on NAND device.
-
-NOR
-===
-
-The Beaglebone White can be equiped with a "memory cape" that in turn can
-have a NOR module plugged into it.  In this case it is then possible to
-program and boot from NOR.  Note that due to how U-Boot is architectured we
-must build a specific version of U-Boot that knows we have NOR flash.  This
-build is named 'am335x_evm_nor'.  Further, we have a 'am335x_evm_norboot'
-build that will assume that the environment is on NOR rather than NAND.  In
-the following example we assume that and SD card has been populated with
-MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the
-'u-boot.bin' from a 'am335x_evm_norboot' build.  When booting from NOR, a
-binary must be written to the start of NOR, with no header or similar
-prepended.  In the following example we use a size of 512KiB (0x80000)
-as that is how much space we set aside before the environment, as per
-the config file.
-
-U-Boot # mmc rescan
-U-Boot # load mmc 0 ${loadaddr} u-boot.bin
-U-Boot # protect off 08000000 +80000
-U-Boot # erase 08000000 +80000
-U-Boot # cp.b ${loadaddr} 08000000 ${filesize}
-
-Falcon Mode
-===========
-
-The default build includes "Falcon Mode" (see doc/README.falcon) via NAND,
-eMMC (or raw SD cards) and FAT SD cards.  Our default behavior currently is
-to read a 'c' on the console while in SPL at any point prior to loading the
-OS payload (so as soon as possible) to opt to booting full U-Boot.  Also
-note that while one can program Falcon Mode "in place" great care needs to
-be taken by the user to not 'brick' their setup.  As these are all eval
-boards with multiple boot methods, recovery should not be an issue in this
-worst-case however.
-
-Falcon Mode: eMMC
-=================
-
-The recommended layout in this case is:
-
-MMC BLOCKS      |--------------------------------| LOCATION IN BYTES
-0x0000 - 0x007F : MBR or GPT table               : 0x000000 - 0x020000
-0x0080 - 0x00FF : ARGS or FDT file               : 0x010000 - 0x020000
-0x0100 - 0x01FF : SPL.backup1 (first copy used)  : 0x020000 - 0x040000
-0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000
-0x0300 - 0x06FF : U-Boot                         : 0x060000 - 0x0e0000
-0x0700 - 0x08FF : U-Boot Env + Redundant         : 0x0e0000 - 0x120000
-0x0900 - 0x28FF : Kernel                         : 0x120000 - 0x520000
-
-Note that when we run 'spl export' it will prepare to boot the kernel.
-This includes relocation of the uImage from where we loaded it to the entry
-point defined in the header.  As these locations overlap by default, it
-would leave us with an image that if written to MMC will not boot, so
-instead of using the loadaddr variable we use 0x81000000 in the following
-example.  In this example we are loading from the network, for simplicity,
-and assume a valid partition table already exists and 'mmc dev' has already
-been run to select the correct device.  Also note that if you previously
-had a FAT partition (such as on a Beaglebone Black) it is not enough to
-write garbage into the area, you must delete it from the partition table
-first.
-
-# Ensure we are able to talk with this mmc device
-U-Boot # mmc rescan
-U-Boot # tftp 81000000 am335x/MLO
-# Write to two of the backup locations ROM uses
-U-Boot # mmc write 81000000 100 100
-U-Boot # mmc write 81000000 200 100
-# Write U-Boot to the location set in the config
-U-Boot # tftp 81000000 am335x/u-boot.img
-U-Boot # mmc write 81000000 300 400
-# Load kernel and device tree into memory, perform export
-U-Boot # tftp 81000000 am335x/uImage
-U-Boot # run findfdt
-U-Boot # tftp ${fdtaddr} am335x/${fdtfile}
-U-Boot # run mmcargs
-U-Boot # spl export fdt 81000000 - ${fdtaddr}
-# Write the updated device tree to MMC
-U-Boot # mmc write ${fdtaddr} 80 80
-# Write the uImage to MMC
-U-Boot # mmc write 81000000 900 2000
-
-Falcon Mode: FAT SD cards
-=========================
-
-In this case the additional file is written to the filesystem.  In this
-example we assume that the uImage and device tree to be used are already on
-the FAT filesystem (only the uImage MUST be for this to function
-afterwards) along with a Falcon Mode aware MLO and the FAT partition has
-already been created and marked bootable:
-
-U-Boot # mmc rescan
-# Load kernel and device tree into memory, perform export
-U-Boot # load mmc 0:1 ${loadaddr} uImage
-U-Boot # run findfdt
-U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile}
-U-Boot # run mmcargs
-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
-
-This will print a number of lines and then end with something like:
-   Using Device Tree in place at 80f80000, end 80f85928
-   Using Device Tree in place at 80f80000, end 80f88928
-So then you:
-
-U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928
-
-Falcon Mode: NAND
-=================
-
-In this case the additional data is written to another partition of the
-NAND.  In this example we assume that the uImage and device tree to be are
-already located on the NAND somewhere (such as fileystem or mtd partition)
-along with a Falcon Mode aware MLO written to the correct locations for
-booting and mtdparts have been configured correctly for the board:
-
-U-Boot # nand read ${loadaddr} kernel
-U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
-U-Boot # run nandargs
-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
-U-Boot # nand erase.part u-boot-spl-os
-U-Boot # nand write ${fdtaddr} u-boot-spl-os
diff --git a/qemu/roms/u-boot/board/ti/am335x/board.c b/qemu/roms/u-boot/board/ti/am335x/board.c
deleted file mode 100644
index da780edb8..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/board.c
+++ /dev/null
@@ -1,701 +0,0 @@
-/*
- * board.c
- *
- * Board functions for TI AM335X based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <power/tps65217.h>
-#include <power/tps65910.h>
-#include <environment.h>
-#include <watchdog.h>
-#include <environment.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN		7
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(struct am335x_baseboard_id *header)
-{
-	/* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-		puts("Could not probe the EEPROM; something fundamentally "
-			"wrong on the I2C bus.\n");
-		return -ENODEV;
-	}
-
-	/* read the eeprom using i2c */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
-		     sizeof(struct am335x_baseboard_id))) {
-		puts("Could not read the EEPROM; something fundamentally"
-			" wrong on the I2C bus.\n");
-		return -EIO;
-	}
-
-	if (header->magic != 0xEE3355AA) {
-		/*
-		 * read the eeprom using i2c again,
-		 * but use only a 1 byte address
-		 */
-		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
-			     sizeof(struct am335x_baseboard_id))) {
-			puts("Could not read the EEPROM; something "
-				"fundamentally wrong on the I2C bus.\n");
-			return -EIO;
-		}
-
-		if (header->magic != 0xEE3355AA) {
-			printf("Incorrect magic number (0x%x) in EEPROM\n",
-					header->magic);
-			return -EINVAL;
-		}
-	}
-
-	return 0;
-}
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-static const struct ddr_data ddr2_data = {
-	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
-			  (MT47H128M16RT25E_RD_DQS<<20) |
-			  (MT47H128M16RT25E_RD_DQS<<10) |
-			  (MT47H128M16RT25E_RD_DQS<<0)),
-	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
-			  (MT47H128M16RT25E_WR_DQS<<20) |
-			  (MT47H128M16RT25E_WR_DQS<<10) |
-			  (MT47H128M16RT25E_WR_DQS<<0)),
-	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<20) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<10) |
-			 (MT47H128M16RT25E_PHY_WRLVL<<0)),
-	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<20) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<10) |
-			 (MT47H128M16RT25E_PHY_GATELVL<<0)),
-	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
-			  (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
-	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
-			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
-	.cmd0csratio = MT47H128M16RT25E_RATIO,
-	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
-
-	.cmd1csratio = MT47H128M16RT25E_RATIO,
-	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
-
-	.cmd2csratio = MT47H128M16RT25E_RATIO,
-	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
-};
-
-static const struct emif_regs ddr2_emif_reg_data = {
-	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
-	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
-	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
-	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
-	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
-	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
-};
-
-static const struct ddr_data ddr3_data = {
-	.datardsratio0 = MT41J128MJT125_RD_DQS,
-	.datawdsratio0 = MT41J128MJT125_WR_DQS,
-	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
-	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
-};
-
-static const struct ddr_data ddr3_beagleblack_data = {
-	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
-	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
-	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
-	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct ddr_data ddr3_evm_data = {
-	.datardsratio0 = MT41J512M8RH125_RD_DQS,
-	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
-	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
-	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = MT41J128MJT125_RATIO,
-	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
-
-	.cmd1csratio = MT41J128MJT125_RATIO,
-	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
-
-	.cmd2csratio = MT41J128MJT125_RATIO,
-	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
-};
-
-static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
-	.cmd0csratio = MT41K256M16HA125E_RATIO,
-	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
-	.cmd1csratio = MT41K256M16HA125E_RATIO,
-	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
-	.cmd2csratio = MT41K256M16HA125E_RATIO,
-	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
-	.cmd0csratio = MT41J512M8RH125_RATIO,
-	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
-
-	.cmd1csratio = MT41J512M8RH125_RATIO,
-	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
-
-	.cmd2csratio = MT41J512M8RH125_RATIO,
-	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
-	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
-	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
-	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
-	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
-	.zq_config = MT41J128MJT125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
-				PHY_EN_DYN_PWRDN,
-};
-
-static struct emif_regs ddr3_beagleblack_emif_reg_data = {
-	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
-	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
-	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
-	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
-	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
-	.zq_config = MT41K256M16HA125E_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
-};
-
-static struct emif_regs ddr3_evm_emif_reg_data = {
-	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
-	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
-	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
-	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
-	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
-	.zq_config = MT41J512M8RH125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
-				PHY_EN_DYN_PWRDN,
-};
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
-	/* break into full u-boot on 'c' */
-	if (serial_tstc() && serial_getc() == 'c')
-		return 1;
-
-#ifdef CONFIG_SPL_ENV_SUPPORT
-	env_init();
-	env_relocate_spec();
-	if (getenv_yesno("boot_os") != 1)
-		return 1;
-#endif
-
-	return 0;
-}
-#endif
-
-#define OSC	(V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
-		266, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_evm_sk = {
-		303, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_bone_black = {
-		400, OSC-1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
-	struct am335x_baseboard_id header;
-	int mpu_vdd;
-
-	if (read_eeprom(&header) < 0)
-		puts("Could not get board ID.\n");
-
-	/* Get the frequency */
-	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
-
-	if (board_is_bone(&header) || board_is_bone_lt(&header)) {
-		/* BeagleBone PMIC Code */
-		int usb_cur_lim;
-
-		/*
-		 * Only perform PMIC configurations if board rev > A1
-		 * on Beaglebone White
-		 */
-		if (board_is_bone(&header) && !strncmp(header.version,
-						       "00A1", 4))
-			return;
-
-		if (i2c_probe(TPS65217_CHIP_PM))
-			return;
-
-		/*
-		 * On Beaglebone White we need to ensure we have AC power
-		 * before increasing the frequency.
-		 */
-		if (board_is_bone(&header)) {
-			uchar pmic_status_reg;
-			if (tps65217_reg_read(TPS65217_STATUS,
-					      &pmic_status_reg))
-				return;
-			if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
-				puts("No AC power, disabling frequency switch\n");
-				return;
-			}
-		}
-
-		/*
-		 * Override what we have detected since we know if we have
-		 * a Beaglebone Black it supports 1GHz.
-		 */
-		if (board_is_bone_lt(&header))
-			dpll_mpu_opp100.m = MPUPLL_M_1000;
-
-		/*
-		 * Increase USB current limit to 1300mA or 1800mA and set
-		 * the MPU voltage controller as needed.
-		 */
-		if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
-			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
-			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
-		} else {
-			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
-			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
-		}
-
-		if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
-				       TPS65217_POWER_PATH,
-				       usb_cur_lim,
-				       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
-			puts("tps65217_reg_write failure\n");
-
-		/* Set DCDC3 (CORE) voltage to 1.125V */
-		if (tps65217_voltage_update(TPS65217_DEFDCDC3,
-					    TPS65217_DCDC_VOLT_SEL_1125MV)) {
-			puts("tps65217_voltage_update failure\n");
-			return;
-		}
-
-		/* Set CORE Frequencies to OPP100 */
-		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
-		/* Set DCDC2 (MPU) voltage */
-		if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
-			puts("tps65217_voltage_update failure\n");
-			return;
-		}
-
-		/*
-		 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
-		 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
-		 */
-		if (board_is_bone(&header)) {
-			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
-					       TPS65217_DEFLS1,
-					       TPS65217_LDO_VOLTAGE_OUT_3_3,
-					       TPS65217_LDO_MASK))
-				puts("tps65217_reg_write failure\n");
-		} else {
-			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
-					       TPS65217_DEFLS1,
-					       TPS65217_LDO_VOLTAGE_OUT_1_8,
-					       TPS65217_LDO_MASK))
-				puts("tps65217_reg_write failure\n");
-		}
-
-		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
-				       TPS65217_DEFLS2,
-				       TPS65217_LDO_VOLTAGE_OUT_3_3,
-				       TPS65217_LDO_MASK))
-			puts("tps65217_reg_write failure\n");
-	} else {
-		int sil_rev;
-
-		/*
-		 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
-		 * MPU frequencies we support we use a CORE voltage of
-		 * 1.1375V.  For MPU voltage we need to switch based on
-		 * the frequency we are running at.
-		 */
-		if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
-			return;
-
-		/*
-		 * Depending on MPU clock and PG we will need a different
-		 * VDD to drive at that speed.
-		 */
-		sil_rev = readl(&cdev->deviceid) >> 28;
-		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
-						      dpll_mpu_opp100.m);
-
-		/* Tell the TPS65910 to use i2c */
-		tps65910_set_i2c_control();
-
-		/* First update MPU voltage. */
-		if (tps65910_voltage_update(MPU, mpu_vdd))
-			return;
-
-		/* Second, update the CORE voltage. */
-		if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
-			return;
-
-		/* Set CORE Frequencies to OPP100 */
-		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-	}
-
-	/* Set MPU Frequency to what we detected now that voltages are set */
-	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
-	struct am335x_baseboard_id header;
-
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-	if (read_eeprom(&header) < 0)
-		puts("Could not get board ID.\n");
-
-	if (board_is_evm_sk(&header))
-		return &dpll_ddr_evm_sk;
-	else if (board_is_bone_lt(&header))
-		return &dpll_ddr_bone_black;
-	else if (board_is_evm_15_or_later(&header))
-		return &dpll_ddr_evm_sk;
-	else
-		return &dpll_ddr;
-}
-
-void set_uart_mux_conf(void)
-{
-#ifdef CONFIG_SERIAL1
-	enable_uart0_pin_mux();
-#endif /* CONFIG_SERIAL1 */
-#ifdef CONFIG_SERIAL2
-	enable_uart1_pin_mux();
-#endif /* CONFIG_SERIAL2 */
-#ifdef CONFIG_SERIAL3
-	enable_uart2_pin_mux();
-#endif /* CONFIG_SERIAL3 */
-#ifdef CONFIG_SERIAL4
-	enable_uart3_pin_mux();
-#endif /* CONFIG_SERIAL4 */
-#ifdef CONFIG_SERIAL5
-	enable_uart4_pin_mux();
-#endif /* CONFIG_SERIAL5 */
-#ifdef CONFIG_SERIAL6
-	enable_uart5_pin_mux();
-#endif /* CONFIG_SERIAL6 */
-}
-
-void set_mux_conf_regs(void)
-{
-	__maybe_unused struct am335x_baseboard_id header;
-
-	if (read_eeprom(&header) < 0)
-		puts("Could not get board ID.\n");
-
-	enable_board_pin_mux(&header);
-}
-
-const struct ctrl_ioregs ioregs_evmsk = {
-	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-};
-
-const struct ctrl_ioregs ioregs_bonelt = {
-	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
-	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
-	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
-	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
-	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-const struct ctrl_ioregs ioregs_evm15 = {
-	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
-	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
-	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
-	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
-	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
-};
-
-const struct ctrl_ioregs ioregs = {
-	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-};
-
-void sdram_init(void)
-{
-	__maybe_unused struct am335x_baseboard_id header;
-
-	if (read_eeprom(&header) < 0)
-		puts("Could not get board ID.\n");
-
-	if (board_is_evm_sk(&header)) {
-		/*
-		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
-		 * This is safe enough to do on older revs.
-		 */
-		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
-		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
-	}
-
-	if (board_is_evm_sk(&header))
-		config_ddr(303, &ioregs_evmsk, &ddr3_data,
-			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-	else if (board_is_bone_lt(&header))
-		config_ddr(400, &ioregs_bonelt,
-			   &ddr3_beagleblack_data,
-			   &ddr3_beagleblack_cmd_ctrl_data,
-			   &ddr3_beagleblack_emif_reg_data, 0);
-	else if (board_is_evm_15_or_later(&header))
-		config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
-			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
-	else
-		config_ddr(266, &ioregs, &ddr2_data,
-			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
-}
-#endif
-
-/*
- * Basic board specific setup.  Pinmux has been handled already.
- */
-int board_init(void)
-{
-#if defined(CONFIG_HW_WATCHDOG)
-	hw_watchdog_init();
-#endif
-
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
-	gpmc_init();
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	char safe_string[HDR_NAME_LEN + 1];
-	struct am335x_baseboard_id header;
-
-	if (read_eeprom(&header) < 0)
-		puts("Could not get board ID.\n");
-
-	/* Now set variables based on the header. */
-	strncpy(safe_string, (char *)header.name, sizeof(header.name));
-	safe_string[sizeof(header.name)] = 0;
-	setenv("board_name", safe_string);
-
-	strncpy(safe_string, (char *)header.version, sizeof(header.version));
-	safe_string[sizeof(header.version)] = 0;
-	setenv("board_rev", safe_string);
-#endif
-
-	return 0;
-}
-#endif
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
-	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x208,
-		.sliver_reg_ofs	= 0xd80,
-		.phy_addr	= 0,
-	},
-	{
-		.slave_reg_ofs	= 0x308,
-		.sliver_reg_ofs	= 0xdc0,
-		.phy_addr	= 1,
-	},
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= CPSW_MDIO_BASE,
-	.cpsw_base		= CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
-	.slave_data		= cpsw_slaves,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.bd_ram_ofs		= 0x2000,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-#endif
-
-/*
- * This function will:
- * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
- * in the environment
- * Perform fixups to the PHY present on certain boards.  We only need this
- * function in:
- * - SPL with either CPSW or USB ethernet support
- * - Full U-Boot, with either CPSW or USB ethernet
- * Build in only these cases to avoid warnings about unused variables
- * when we build an SPL that has neither option but full U-Boot will.
- */
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
-		&& defined(CONFIG_SPL_BUILD)) || \
-	((defined(CONFIG_DRIVER_TI_CPSW) || \
-	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
-	 !defined(CONFIG_SPL_BUILD))
-int board_eth_init(bd_t *bis)
-{
-	int rv, n = 0;
-	uint8_t mac_addr[6];
-	uint32_t mac_hi, mac_lo;
-	__maybe_unused struct am335x_baseboard_id header;
-
-	/* try reading mac address from efuse */
-	mac_lo = readl(&cdev->macid0l);
-	mac_hi = readl(&cdev->macid0h);
-	mac_addr[0] = mac_hi & 0xFF;
-	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-	mac_addr[4] = mac_lo & 0xFF;
-	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
-	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-	if (!getenv("ethaddr")) {
-		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
-		if (is_valid_ether_addr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-
-	mac_lo = readl(&cdev->macid1l);
-	mac_hi = readl(&cdev->macid1h);
-	mac_addr[0] = mac_hi & 0xFF;
-	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-	mac_addr[4] = mac_lo & 0xFF;
-	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-	if (!getenv("eth1addr")) {
-		if (is_valid_ether_addr(mac_addr))
-			eth_setenv_enetaddr("eth1addr", mac_addr);
-	}
-
-	if (read_eeprom(&header) < 0)
-		puts("Could not get board ID.\n");
-
-	if (board_is_bone(&header) || board_is_bone_lt(&header) ||
-	    board_is_idk(&header)) {
-		writel(MII_MODE_ENABLE, &cdev->miisel);
-		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
-				PHY_INTERFACE_MODE_MII;
-	} else {
-		writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
-		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
-				PHY_INTERFACE_MODE_RGMII;
-	}
-
-	rv = cpsw_register(&cpsw_data);
-	if (rv < 0)
-		printf("Error %d registering CPSW switch\n", rv);
-	else
-		n += rv;
-#endif
-
-	/*
-	 *
-	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
-	 * operating points.  So we must set the TX clock delay feature
-	 * in the AR8051 PHY.  Since we only support a single ethernet
-	 * device in U-Boot, we only do this for the first instance.
-	 */
-#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
-#define AR8051_PHY_DEBUG_DATA_REG	0x1e
-#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
-#define AR8051_RGMII_TX_CLK_DLY		0x100
-
-	if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
-		const char *devname;
-		devname = miiphy_get_current_dev();
-
-		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
-				AR8051_DEBUG_RGMII_CLK_DLY_REG);
-		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
-				AR8051_RGMII_TX_CLK_DLY);
-	}
-#endif
-#if defined(CONFIG_USB_ETHER) && \
-	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
-	if (is_valid_ether_addr(mac_addr))
-		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
-
-	rv = usb_eth_initialize(bis);
-	if (rv < 0)
-		printf("Error %d registering USB_ETHER\n", rv);
-	else
-		n += rv;
-#endif
-	return n;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/am335x/board.h b/qemu/roms/u-boot/board/ti/am335x/board.h
deleted file mode 100644
index bc700d56f..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/board.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * board.h
- *
- * TI AM335x boards information header
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * TI AM335x parts define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR	3
-#define HDR_ETH_ALEN		6
-#define HDR_NAME_LEN		8
-
-struct am335x_baseboard_id {
-	unsigned int  magic;
-	char name[HDR_NAME_LEN];
-	char version[4];
-	char serial[12];
-	char config[32];
-	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
-static inline int board_is_bone(struct am335x_baseboard_id *header)
-{
-	return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
-}
-
-static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
-{
-	return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
-{
-	return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
-}
-
-static inline int board_is_idk(struct am335x_baseboard_id *header)
-{
-	return !strncmp(header->config, "SKU#02", 6);
-}
-
-static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
-{
-	return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
-{
-	return (board_is_gp_evm(header) &&
-		strncmp("1.5", header->version, 3) <= 0);
-}
-
-/*
- * We have three pin mux functions that must exist.  We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_uart1_pin_mux(void);
-void enable_uart2_pin_mux(void);
-void enable_uart3_pin_mux(void);
-void enable_uart4_pin_mux(void);
-void enable_uart5_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(struct am335x_baseboard_id *header);
-#endif
diff --git a/qemu/roms/u-boot/board/ti/am335x/mux.c b/qemu/roms/u-boot/board/ti/am335x/mux.c
deleted file mode 100644
index b2bfda5ea..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/mux.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
-	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
-	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
-	{-1},
-};
-
-static struct module_pin_mux uart1_pin_mux[] = {
-	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART1_RXD */
-	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},		/* UART1_TXD */
-	{-1},
-};
-
-static struct module_pin_mux uart2_pin_mux[] = {
-	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
-	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
-	{-1},
-};
-
-static struct module_pin_mux uart3_pin_mux[] = {
-	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
-	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
-	{-1},
-};
-
-static struct module_pin_mux uart4_pin_mux[] = {
-	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
-	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
-	{-1},
-};
-
-static struct module_pin_mux uart5_pin_mux[] = {
-	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
-	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
-	{-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
-	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
-	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
-	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
-	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
-	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
-	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
-	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
-	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
-	{-1},
-};
-
-static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
-	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
-	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
-	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
-	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
-	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
-	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
-	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
-	{-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
-	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
-	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
-	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
-	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
-	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
-	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
-	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
-	{-1},
-};
-
-static struct module_pin_mux mmc1_pin_mux[] = {
-	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
-	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
-	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
-	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
-	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
-	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
-	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
-	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_CD */
-	{-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
-	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
-			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
-	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
-			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
-	{-1},
-};
-
-static struct module_pin_mux i2c1_pin_mux[] = {
-	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
-			PULLUDEN | SLEWCTRL)},	/* I2C_DATA */
-	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
-			PULLUDEN | SLEWCTRL)},	/* I2C_SCLK */
-	{-1},
-};
-
-static struct module_pin_mux spi0_pin_mux[] = {
-	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
-	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
-			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
-	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
-	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
-			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
-	{-1},
-};
-
-static struct module_pin_mux gpio0_7_pin_mux[] = {
-	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)},	/* GPIO0_7 */
-	{-1},
-};
-
-static struct module_pin_mux rgmii1_pin_mux[] = {
-	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
-	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
-	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
-	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
-	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
-	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
-	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
-	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
-	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
-	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
-	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
-	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{-1},
-};
-
-static struct module_pin_mux mii1_pin_mux[] = {
-	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
-	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
-	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
-	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
-	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
-	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
-	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
-	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
-	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
-	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
-	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
-	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
-	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{-1},
-};
-
-static struct module_pin_mux nand_pin_mux[] = {
-	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
-	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
-	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
-	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
-	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
-	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
-	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
-	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
-	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
-	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
-	{-1},
-};
-
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
-static struct module_pin_mux bone_norcape_pin_mux[] = {
-	{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */
-	{OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A1 */
-	{OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A2 */
-	{OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A3 */
-	{OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A4 */
-	{OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A5 */
-	{OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A6 */
-	{OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A7 */
-	{OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A8 */
-	{OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A9 */
-	{OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE},       /* NOR_A10 */
-	{OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
-	{OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A12 */
-	{OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A13 */
-	{OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A14 */
-	{OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A15 */
-	{OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A16 */
-	{OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A17 */
-	{OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A18 */
-	{OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A19 */
-	{OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD0 */
-	{OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD1 */
-	{OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD2 */
-	{OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD3 */
-	{OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD4 */
-	{OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD5 */
-	{OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD6 */
-	{OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD7 */
-	{OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD8 */
-	{OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD9 */
-	{OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD10 */
-	{OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD11 */
-	{OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD12 */
-	{OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD13 */
-	{OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD14 */
-	{OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD15 */
-
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE},   /* NOR_CE */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)},    /* NOR_WEN */
-	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
-	{-1},
-};
-#endif
-
-#if defined(CONFIG_NOR_BOOT)
-static struct module_pin_mux norboot_pin_mux[] = {
-	{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
-	{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
-	{-1},
-};
-
-void enable_norboot_pin_mux(void)
-{
-	configure_module_pin_mux(norboot_pin_mux);
-}
-#endif
-
-void enable_uart0_pin_mux(void)
-{
-	configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_uart1_pin_mux(void)
-{
-	configure_module_pin_mux(uart1_pin_mux);
-}
-
-void enable_uart2_pin_mux(void)
-{
-	configure_module_pin_mux(uart2_pin_mux);
-}
-
-void enable_uart3_pin_mux(void)
-{
-	configure_module_pin_mux(uart3_pin_mux);
-}
-
-void enable_uart4_pin_mux(void)
-{
-	configure_module_pin_mux(uart4_pin_mux);
-}
-
-void enable_uart5_pin_mux(void)
-{
-	configure_module_pin_mux(uart5_pin_mux);
-}
-
-void enable_i2c0_pin_mux(void)
-{
-	configure_module_pin_mux(i2c0_pin_mux);
-}
-
-/*
- * The AM335x GP EVM, if daughter card(s) are connected, can have 8
- * different profiles.  These profiles determine what peripherals are
- * valid and need pinmux to be configured.
- */
-#define PROFILE_NONE	0x0
-#define PROFILE_0	(1 << 0)
-#define PROFILE_1	(1 << 1)
-#define PROFILE_2	(1 << 2)
-#define PROFILE_3	(1 << 3)
-#define PROFILE_4	(1 << 4)
-#define PROFILE_5	(1 << 5)
-#define PROFILE_6	(1 << 6)
-#define PROFILE_7	(1 << 7)
-#define PROFILE_MASK	0x7
-#define PROFILE_ALL	0xFF
-
-/* CPLD registers */
-#define I2C_CPLD_ADDR	0x35
-#define CFG_REG		0x10
-
-static unsigned short detect_daughter_board_profile(void)
-{
-	unsigned short val;
-
-	if (i2c_probe(I2C_CPLD_ADDR))
-		return PROFILE_NONE;
-
-	if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
-		return PROFILE_NONE;
-
-	return (1 << (val & PROFILE_MASK));
-}
-
-void enable_board_pin_mux(struct am335x_baseboard_id *header)
-{
-	/* Do board-specific muxes. */
-	if (board_is_bone(header)) {
-		/* Beaglebone pinmux */
-		configure_module_pin_mux(i2c1_pin_mux);
-		configure_module_pin_mux(mii1_pin_mux);
-		configure_module_pin_mux(mmc0_pin_mux);
-#ifndef CONFIG_NOR
-		configure_module_pin_mux(mmc1_pin_mux);
-#endif
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
-		configure_module_pin_mux(bone_norcape_pin_mux);
-#endif
-	} else if (board_is_gp_evm(header)) {
-		/* General Purpose EVM */
-		unsigned short profile = detect_daughter_board_profile();
-		configure_module_pin_mux(rgmii1_pin_mux);
-		configure_module_pin_mux(mmc0_pin_mux);
-		/* In profile #2 i2c1 and spi0 conflict. */
-		if (profile & ~PROFILE_2)
-			configure_module_pin_mux(i2c1_pin_mux);
-		/* Profiles 2 & 3 don't have NAND */
-		if (profile & ~(PROFILE_2 | PROFILE_3))
-			configure_module_pin_mux(nand_pin_mux);
-		else if (profile == PROFILE_2) {
-			configure_module_pin_mux(mmc1_pin_mux);
-			configure_module_pin_mux(spi0_pin_mux);
-		}
-	} else if (board_is_idk(header)) {
-		/*
-		 * Industrial Motor Control (IDK)
-		 * note: IDK console is on UART3 by default.
-		 *       So u-boot mus be build with CONFIG_SERIAL4 and
-		 *       CONFIG_CONS_INDEX=4
-		 */
-		configure_module_pin_mux(mii1_pin_mux);
-		configure_module_pin_mux(mmc0_no_cd_pin_mux);
-	} else if (board_is_evm_sk(header)) {
-		/* Starter Kit EVM */
-		configure_module_pin_mux(i2c1_pin_mux);
-		configure_module_pin_mux(gpio0_7_pin_mux);
-		configure_module_pin_mux(rgmii1_pin_mux);
-		configure_module_pin_mux(mmc0_pin_mux_sk_evm);
-	} else if (board_is_bone_lt(header)) {
-		/* Beaglebone LT pinmux */
-		configure_module_pin_mux(i2c1_pin_mux);
-		configure_module_pin_mux(mii1_pin_mux);
-		configure_module_pin_mux(mmc0_pin_mux);
-		configure_module_pin_mux(mmc1_pin_mux);
-	} else {
-		puts("Unknown board, cannot configure pinmux.");
-		hang();
-	}
-}
diff --git a/qemu/roms/u-boot/board/ti/am335x/u-boot.lds b/qemu/roms/u-boot/board/ti/am335x/u-boot.lds
deleted file mode 100644
index a9e3d34df..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/u-boot.lds
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		*(.__image_copy_start)
-		CPUDIR/start.o (.text*)
-		board/ti/am335x/built-in.o (.text*)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN(4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	.end :
-	{
-		*(.__end)
-	}
-
-	_image_binary_end = .;
-
-	/*
-	 * Deprecated: this MMU section is used by pxa at present but
-	 * should not be used by new boards/CPUs.
-	 */
-	. = ALIGN(4096);
-	.mmutable : {
-		*(.mmutable)
-	}
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	.dynsym _image_binary_end : { *(.dynsym) }
-	.dynbss : { *(.dynbss) }
-	.dynstr : { *(.dynstr*) }
-	.dynamic : { *(.dynamic*) }
-	.hash : { *(.hash*) }
-	.gnu.hash : { *(.gnu.hash) }
-	.plt : { *(.plt*) }
-	.interp : { *(.interp*) }
-	.gnu : { *(.gnu*) }
-	.ARM.exidx : { *(.ARM.exidx*) }
-}