Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

6 files changed, 0 insertions, 1161 deletions

diff --git a/qemu/roms/u-boot/board/technexion/tao3530/Makefile b/qemu/roms/u-boot/board/technexion/tao3530/Makefile
deleted file mode 100644
index 2aff38311..000000000
--- a/qemu/roms/u-boot/board/technexion/tao3530/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= tao3530.o
diff --git a/qemu/roms/u-boot/board/technexion/tao3530/tao3530.c b/qemu/roms/u-boot/board/technexion/tao3530/tao3530.c
deleted file mode 100644
index 44a82406a..000000000
--- a/qemu/roms/u-boot/board/technexion/tao3530/tao3530.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * Maintainer :
- *      Tapani Utriainen <linuxfae@technexion.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-
-#include <usb.h>
-#include <asm/ehci-omap.h>
-
-#include "tao3530.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int tao3530_revision(void)
-{
-	int ret = 0;
-
-	/* char *label argument is unused in gpio_request() */
-	ret = gpio_request(65, "");
-	if (ret) {
-		puts("Error: GPIO 65 not available\n");
-		goto out;
-	}
-	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M4));
-
-	ret = gpio_request(1, "");
-	if (ret) {
-		puts("Error: GPIO 1 not available\n");
-		goto out2;
-	}
-	MUX_VAL(CP(SYS_CLKREQ), (IEN  | PTU | EN | M4));
-
-	ret = gpio_direction_input(65);
-	if (ret) {
-		puts("Error: GPIO 65 not available for input\n");
-		goto out3;
-	}
-
-	ret =  gpio_direction_input(1);
-	if (ret) {
-		puts("Error: GPIO 1 not available for input\n");
-		goto out3;
-	}
-
-	ret = gpio_get_value(65) << 1 | gpio_get_value(1);
-
-out3:
-	MUX_VAL(CP(SYS_CLKREQ), (IEN  | PTU | EN | M0));
-	gpio_free(1);
-out2:
-	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0));
-	gpio_free(65);
-out:
-
-	return ret;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
-#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
-	/*
-	 * Switch baseboard LED to red upon power-on
-	 */
-	MUX_OMAP3_HA();
-
-	/* Request a gpio before using it */
-	gpio_request(111, "");
-	/* Sets the gpio as output and its value to 1, switch LED to red */
-	gpio_direction_output(111, 1);
-#endif
-
-	if (tao3530_revision() < 3) {
-		/* 256MB / Bank */
-		timings->mcfg = MCFG(256 << 20, 14);	/* RAS-width 14 */
-		timings->ctrla = HYNIX_V_ACTIMA_165;
-		timings->ctrlb = HYNIX_V_ACTIMB_165;
-	} else {
-		/* 128MB / Bank */
-		timings->mcfg = MCFG(128 << 20, 13);	/* RAS-width 13 */
-		timings->ctrla = MICRON_V_ACTIMA_165;
-		timings->ctrlb = MICRON_V_ACTIMB_165;
-	}
-
-	timings->mr = MICRON_V_MR_165;
-	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-}
-#endif
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530;
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
-	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
-	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
-
-	twl4030_power_init();
-	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-
-	/* Configure GPIOs to output */
-	/* GPIO23 */
-	writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
-	writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
-		 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
-
-	/* Set GPIOs */
-	writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
-	       &gpio6_base->setdataout);
-	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
-	       GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
-
-	switch (tao3530_revision()) {
-	case 0:
-		puts("TAO-3530 REV Reserve 1\n");
-		break;
-	case 1:
-		puts("TAO-3530 REV Reserve 2\n");
-		break;
-	case 2:
-		puts("TAO-3530 REV Cx\n");
-		break;
-	case 3:
-		puts("TAO-3530 REV Ax/Bx\n");
-		break;
-	default:
-		puts("Unknown board revision\n");
-	}
-
-	dieid_num_r();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_TAO3530();
-#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
-	MUX_OMAP3_HA();
-#endif
-}
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
-	omap_mmc_init(0, 0, 0, -1, -1);
-
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
-/* Call usb_stop() before starting the kernel */
-void show_boot_progress(int val)
-{
-	if (val == BOOTSTAGE_ID_RUN_OS)
-		usb_stop();
-}
-
-static struct omap_usbhs_board_data usbhs_bdata = {
-	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
-	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		  struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
-	return omap_ehci_hcd_stop();
-}
-#endif /* CONFIG_USB_EHCI */
diff --git a/qemu/roms/u-boot/board/technexion/tao3530/tao3530.h b/qemu/roms/u-boot/board/technexion/tao3530/tao3530.h
deleted file mode 100644
index daff10948..000000000
--- a/qemu/roms/u-boot/board/technexion/tao3530/tao3530.h
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
- * (C) Copyright TechNexion 2010
- * Edward Lin <linuxfae@technexion.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _TAO3530_H_
-#define _TAO3530_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
-	"HEAD acoustics OMAP3-HA",
-#else
-	"OMAP3 TAO-3530 board",
-#endif
-	"NAND",
-};
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_TAO3530() \
- /*SDRC*/\
-	MUX_VAL(CP(SDRC_D0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D3),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D4),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D5),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D6),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D7),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D8),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D9),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D10),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D11),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D12),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D13),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D14),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D15),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D16),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D17),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D18),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D19),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D20),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D21),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D22),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D23),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D24),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D25),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D26),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D27),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D28),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D29),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D30),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D31),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_CLK),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS3),	(IEN  | PTD | DIS | M0)) \
- /*GPMC*/\
-	MUX_VAL(CP(GPMC_A1),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A2),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A3),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A4),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A5),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A6),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A7),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A8),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A9),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A10),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D0),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D1),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D2),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D3),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D4),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D5),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D6),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D7),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D8),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D9),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D10),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D11),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D12),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D13),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D14),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D15),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS0),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS1),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS2),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS3),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS4),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS5),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS6),	(IEN  | PTD | EN | M0)) \
-	MUX_VAL(CP(GPMC_NCS7),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_CLK),	(IDIS | PTU | EN | M0)) \
-	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NOE),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NWE),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
-	MUX_VAL(CP(GPMC_NBE1),	(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(GPMC_NWP),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_WAIT0),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_WAIT1),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_WAIT2),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0)) \
- /*DSS*/\
-	MUX_VAL(CP(DSS_PCLK),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_HSYNC),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_VSYNC),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_ACBIAS),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA0),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA1),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA2),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA3),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA4),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA5),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA6),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA7),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA8),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA9),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA10),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA11),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA12),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA13),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA14),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA15),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA16),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA17),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA18),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA19),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA20),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA21),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA22),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA23),	(IDIS | PTD | DIS | M0)) \
- /*CAMERA*/\
-	MUX_VAL(CP(CAM_HS),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_VS),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_XCLKA),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_PCLK),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_FLD),	(IDIS | PTD | DIS | M4)) \
- /* - CAM_RESET*/\
-	MUX_VAL(CP(CAM_D0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D3),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D4),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D5),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D6),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D7),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D8),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D9),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D10),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D11),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_XCLKB),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_WEN),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(CAM_STROBE),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DX0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DY0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DX1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DY1),	(IEN  | PTD | DIS | M0)) \
- /*Audio Interface */\
-	MUX_VAL(CP(MCBSP2_FSX),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP2_CLKX), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP2_DR),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP2_DX),	(IDIS | PTD | DIS | M0)) \
- /*Expansion card */\
-	MUX_VAL(CP(MMC1_CLK),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_CMD),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_DAT0),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_DAT1),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_DAT2),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_DAT3),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_DAT4),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_DAT5),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_DAT6),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_DAT7),	(IEN  | PTU | EN  | M0)) \
- /* MMC2 WLAN */\
-	MUX_VAL(CP(MMC2_CLK),	(IEN  | PTD | DIS  | M0)) \
-	MUX_VAL(CP(MMC2_CMD),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC2_DAT0),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC2_DAT1),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC2_DAT2),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC2_DAT3),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC2_DAT4),	(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC2_DAT5),	(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC2_DAT6),	(IDIS  | PTD | EN  | M4)) \
-	MUX_VAL(CP(MMC2_DAT7),	(IDIS  | PTU | EN  | M4)) \
- /*Bluetooth*/\
-	MUX_VAL(CP(MCBSP3_DX),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP3_DR),	(IEN  | PTD | DIS | M0)) \
- /*LocalBus LAN Reset*/\
-	MUX_VAL(CP(MCBSP3_CLKX), (IEN  | PTD | DIS | M4)) \
- /*LocalBus LAN IRQ*/\
-	MUX_VAL(CP(MCBSP3_FSX),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(UART2_CTS),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(UART2_RTS),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_TX),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_RX),	(IEN  | PTD | DIS | M0)) \
- /*Modem Interface */\
-	MUX_VAL(CP(UART1_TX),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART1_RTS),	(IDIS | PTD | DIS | M0))  \
-	MUX_VAL(CP(UART1_CTS),	(IEN  | PTU | DIS | M0))  \
-	MUX_VAL(CP(UART1_RX),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP4_CLKX), (IEN  | PTD | DIS | M1)) \
-	MUX_VAL(CP(MCBSP4_DR),	(IEN  | PTD | DIS | M1)) \
-	MUX_VAL(CP(MCBSP4_DX),	(IEN  | PTD | DIS | M1)) \
-	MUX_VAL(CP(MCBSP4_FSX),	(IEN  | PTD | DIS | M1)) \
-	MUX_VAL(CP(MCBSP1_CLKR),     (IEN | PTD | DIS | M1)) \
-	MUX_VAL(CP(MCBSP1_FSR),	(IDIS | PTU | EN  | M4)) \
-	MUX_VAL(CP(MCBSP1_DX),	(IEN | PTD | DIS | M1)) \
-	MUX_VAL(CP(MCBSP1_DR),		(IEN | PTD | DIS | M1)) \
-	MUX_VAL(CP(MCBSP_CLKS),	(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_FSX),	(IEN | PTD | EN | M1)) \
-	MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \
- /*Serial Interface*/\
-	MUX_VAL(CP(UART3_CTS_RCTX), (IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART3_RX_IRRX), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_CLK),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_STP),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(HSUSB0_DIR),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_NXT),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA0), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA1), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA2), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA3), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA4), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA5), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA6), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA7), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(I2C1_SCL),	(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(I2C1_SDA),	(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(I2C2_SCL),	(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(I2C2_SDA),	(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(I2C3_SCL),	(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(I2C3_SDA),	(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(I2C4_SCL),	(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(I2C4_SDA),	(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(HDQ_SIO),	(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(MCSPI1_CLK),	(IEN  | PTD | EN | M0)) \
-	MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M0)) \
-	MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) \
-	MUX_VAL(CP(MCSPI1_CS0),	(IEN  | PTD | EN | M0)) \
-	MUX_VAL(CP(MCSPI1_CS1),	(IEN  | PTD | EN | M0)) \
-	MUX_VAL(CP(MCSPI1_CS2),	(IEN  | PTD | EN | M4)) \
- /* USB EHCI (port 2) */\
-	MUX_VAL(CP(MCSPI1_CS3),	(IEN  | PTU | DIS | M3)) \
-	MUX_VAL(CP(MCSPI2_CLK),	(IEN  | PTU | DIS | M3)) \
-	MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \
-	MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \
-	MUX_VAL(CP(MCSPI2_CS0),	(IEN  | PTU | DIS | M3)) \
-	MUX_VAL(CP(MCSPI2_CS1),	(IEN  | PTU | DIS | M3)) \
- /*Control and debug */\
-	MUX_VAL(CP(SYS_32K),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKREQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_NIRQ),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(SYS_BOOT0),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT1),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT2),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT3),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT4),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT5),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT6),	(IDIS | PTD | DIS | M4))  \
-	/* - VIO_1V8*/\
-	MUX_VAL(CP(SYS_OFF_MODE), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKOUT1), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKOUT2), (IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(JTAG_nTRST),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TCK),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TMS),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TDI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_EMU0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_EMU1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) \
-	MUX_VAL(CP(ETK_D0_ES2),	(IEN  | PTU | DIS | M1)) \
-	MUX_VAL(CP(ETK_D1_ES2),	(IEN  | PTU | DIS | M1)) \
-	MUX_VAL(CP(ETK_D2_ES2),	(IEN  | PTU | DIS | M1)) \
-	MUX_VAL(CP(ETK_D3_ES2),	(IEN  | PTU | DIS | M1)) \
-	MUX_VAL(CP(ETK_D4_ES2),	(IEN  | PTU | EN | M4)) \
-	MUX_VAL(CP(ETK_D5_ES2),	(IEN  | PTU | EN | M4)) \
-	MUX_VAL(CP(ETK_D6_ES2),	(IEN  | PTU | EN | M4)) \
-	MUX_VAL(CP(ETK_D7_ES2),	(IEN  | PTU | DIS | M1)) \
-	MUX_VAL(CP(ETK_D8_ES2),	(IEN  | PTU | EN | M4)) \
-	MUX_VAL(CP(ETK_D9_ES2),	(IEN  | PTD | EN | M4)) \
-	MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \
-	MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \
-	MUX_VAL(CP(ETK_D12_ES2), (IEN  | PTU | DIS | M3)) \
-	MUX_VAL(CP(ETK_D13_ES2), (IEN  | PTU | DIS | M3)) \
-	MUX_VAL(CP(ETK_D14_ES2), (IEN|PTU|DIS|M3)) \
-	MUX_VAL(CP(ETK_D15_ES2), (IEN  | PTU | DIS | M3)) \
-	MUX_VAL(CP(D2D_MCAD1),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD2),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD3),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD4),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD5),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD6),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD7),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD8),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD9),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD10),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD11),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD12),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD13),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD14),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD15),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD16),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD17),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD18),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD19),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD20),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD21),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD22),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD23),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD24),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD25),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD26),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD27),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD28),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD29),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD30),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD31),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD32),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD33),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD34),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD35),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD36),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_CLK26MI), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_NRESPWRON), (IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_NRESWARM), (IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_ARM9NIRQ), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SPINT),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_FRINT),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ0), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ1), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ2), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ3), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTRST), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTDI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTDO),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTMS),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTCK),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GRTCK), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MSTDBY),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_SWAKEUP), (IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_IDLEREQ), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_IDLEACK), (IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_MWRITE),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SWRITE),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MREAD),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SREAD),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MBUSFLAG), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SBUSFLAG), (IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_CKE0),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(SDRC_CKE1),	(IDIS | PTU | EN  | M0))
-
-#define MUX_OMAP3_HA() \
-	MUX_VAL(CP(CAM_XCLKB),	(IDIS | PTD | DIS | M4)) /* GPIO_111 */
-
-#endif
diff --git a/qemu/roms/u-boot/board/technexion/twister/Makefile b/qemu/roms/u-boot/board/technexion/twister/Makefile
deleted file mode 100644
index 2a910211f..000000000
--- a/qemu/roms/u-boot/board/technexion/twister/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
-#
-# Based on ti/evm/Makefile
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= twister.o
diff --git a/qemu/roms/u-boot/board/technexion/twister/twister.c b/qemu/roms/u-boot/board/technexion/twister/twister.c
deleted file mode 100644
index 054e7ccde..000000000
--- a/qemu/roms/u-boot/board/technexion/twister/twister.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2009 TechNexion Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <i2c.h>
-#include <asm/gpio.h>
-#ifdef CONFIG_USB_EHCI
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-#include "twister.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Timing definitions for Ethernet Controller */
-static const u32 gpmc_smc911[] = {
-	NET_GPMC_CONFIG1,
-	NET_GPMC_CONFIG2,
-	NET_GPMC_CONFIG3,
-	NET_GPMC_CONFIG4,
-	NET_GPMC_CONFIG5,
-	NET_GPMC_CONFIG6,
-};
-
-static const u32 gpmc_XR16L2751[] = {
-	XR16L2751_GPMC_CONFIG1,
-	XR16L2751_GPMC_CONFIG2,
-	XR16L2751_GPMC_CONFIG3,
-	XR16L2751_GPMC_CONFIG4,
-	XR16L2751_GPMC_CONFIG5,
-	XR16L2751_GPMC_CONFIG6,
-};
-
-#ifdef CONFIG_USB_EHCI
-static struct omap_usbhs_board_data usbhs_bdata = {
-	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
-	return omap_ehci_hcd_stop();
-}
-#endif
-
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	/* Chip select 1  and 3 are used for XR16L2751 UART controller */
-	enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
-		XR16L2751_UART1_BASE, GPMC_SIZE_16M);
-
-	enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
-		XR16L2751_UART2_BASE, GPMC_SIZE_16M);
-
-	gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
-	gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
-
-	return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-int misc_init_r(void)
-{
-	char *eth_addr;
-	struct tam3517_module_info info;
-	int ret;
-
-	dieid_num_r();
-
-	eth_addr = getenv("ethaddr");
-	if (eth_addr)
-		return 0;
-
-	TAM3517_READ_EEPROM(&info, ret);
-	if (!ret)
-		TAM3517_READ_MAC_FROM_EEPROM(&info);
-
-	return 0;
-}
-#endif
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_TWISTER();
-}
-
-int board_eth_init(bd_t *bis)
-{
-	davinci_emac_initialize();
-
-	/* init cs for extern lan */
-	enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
-		CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-	if (smc911x_initialize(0, CONFIG_SMC911X_BASE) <= 0)
-		printf("\nError initializing SMC911x controlleri\n");
-
-	return 0;
-}
-
-#if defined(CONFIG_OMAP_HSMMC) && \
-	!defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * Do board specific preperation before SPL
- * Linux boot
- */
-void spl_board_prepare_for_linux(void)
-{
-	/* init cs for extern lan */
-	enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
-		CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-}
-int spl_start_uboot(void)
-{
-	int val = 0;
-	if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
-		gpio_direction_input(SPL_OS_BOOT_KEY);
-		val = gpio_get_value(SPL_OS_BOOT_KEY);
-		gpio_free(SPL_OS_BOOT_KEY);
-	}
-	return val;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/technexion/twister/twister.h b/qemu/roms/u-boot/board/technexion/twister/twister.h
deleted file mode 100644
index 62fbfdfed..000000000
--- a/qemu/roms/u-boot/board/technexion/twister/twister.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2010 TechNexion Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _TAM3517_H_
-#define _TAM3517_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_DISCRETE,
-	"TAM3517 TWISTER Board",
-	"NAND",
-};
-
-#define XR16L2751_GPMC_CONFIG1	0x00000000
-#define XR16L2751_GPMC_CONFIG2	0x001e1e01
-#define XR16L2751_GPMC_CONFIG3	0x00080300
-#define XR16L2751_GPMC_CONFIG4	0x1c091c09
-#define XR16L2751_GPMC_CONFIG5	0x04181f1f
-#define XR16L2751_GPMC_CONFIG6	0x00000FCF
-
-#define XR16L2751_UART1_BASE	0x21000000
-#define XR16L2751_UART2_BASE	0x23000000
-
-/* GPIO used to select between U-Boot and kernel */
-#define SPL_OS_BOOT_KEY	55
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN	- Pull type selection is active
- * M0	- Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_TWISTER() \
-	/* SDRC */\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
-	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
-	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
-			 /*sdrc_strben_dly0*/\
-	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
-			/*sdrc_strben_dly1*/\
-	/* GPMC */\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS1),		(IEN | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTD | EN  | M2)) /*PWM9*/\
-	MUX_VAL(CP(GPMC_NCS3),		(IEN | PTU | EN | M0)) \
-	MUX_VAL(CP(GPMC_NCS4),		(IEN | PTD | EN | M4)) \
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS6),		(IDIS  | PTD | EN | M3)) /*PWM11*/ \
-	MUX_VAL(CP(GPMC_NCS7),		(IDIS  | PTD | EN | M4)) /*GPIO_58*/ \
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M4)) \
-	/* DSS */\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
-	/* CAMERA */\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
-	/* MMC */\
-	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
-			/* CardDetect */\
-	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
-	\
-	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN | M0)) \
-	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | DIS  | M0)) \
-	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | DIS  | M0)) \
-	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | DIS  | M0)) \
-	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | DIS  | M0)) \
-	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | DIS  | M0)) \
-	MUX_VAL(CP(MMC2_DAT4),		(IDIS  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC2_DAT5),		(IDIS  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC2_DAT6),		(IDIS  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC2_DAT7),		(IDIS  | PTU | EN  | M4)) \
-	/* McBSP */\
-	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
-	\
-	MUX_VAL(CP(MCBSP2_FSX),		(IEN | PTD | EN | M4)) /*GPIO_116*/ \
-	MUX_VAL(CP(MCBSP2_CLKX),	(IEN | PTD | EN | M4)) \
-	MUX_VAL(CP(MCBSP2_DR),		(IEN | PTD | EN | M4)) \
-	MUX_VAL(CP(MCBSP2_DX),		(IEN | PTD | EN | M4)) \
-	\
-	MUX_VAL(CP(MCBSP3_DX),		(IEN | PTU | EN | M4)) \
-	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTU | EN | M4)) \
-	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTU | EN | M4)) \
-	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTU | EN | M4)) \
-	\
-	MUX_VAL(CP(MCBSP4_CLKX),	(IEN | PTD | DIS | M4)) /*GPIO_152*/\
-	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
-	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
-	MUX_VAL(CP(MCBSP4_FSX),		(IEN | PTD | DIS | M4)) /*GPIO_155*/\
-	/* UART */\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART1_RTS),		(IEN | PTU | EN | M4)) \
-	MUX_VAL(CP(UART1_CTS),		(IEN | PTU | EN | M4)) \
-	\
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
-	\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IDIS  | PTD | DIS | M4)) /*GPIO_163*/ \
-	MUX_VAL(CP(UART3_RTS_SD),	(IEN | PTD | DIS | M4)) /*GPIO_164*/\
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
-	/* I2C */\
-	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
-	/* McSPI */\
-	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(MCSPI1_CS1),		(IEN | PTD | EN | M4)) /*GPIO_175*/\
-	MUX_VAL(CP(MCSPI1_CS2),		(IEN | PTD | EN | M4)) /*GPIO_176*/\
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN | PTD | EN | M4)) \
-	\
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M4)) \
-	/* CCDC */\
-	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M1)) \
-	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M1)) \
-	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
-	/* RMII */\
-	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
-	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
-	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
-	/* HECC */\
-	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
-	/* HSUSB */\
-	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
-	/* HDQ */\
-	MUX_VAL(CP(HDQ_SIO),		(IEN | PTD | EN | M4)) \
-	/* Control and debug */\
-	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(SYS_NRESWARM),	(IDIS | PTU | DIS | M4)) \
-			/* - GPIO30 */\
-	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
-	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
-	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
-	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
-	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
-	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
-							 /* - VIO_1V8*/\
-	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
-	\
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
-	/* JTAG */\
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_EMU0),		(IDIS  | PTD | EN | M4)) /*GPIO_11*/ \
-	MUX_VAL(CP(JTAG_EMU1),		(IDIS  | PTD | EN | M4)) /*GPIO_31*/ \
-	/* ETK (ES2 onwards) */\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTD | DIS  | M3)) \
-					/* hsusb1_stp */ \
-	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M3)) \
-					/* hsusb1_clk */\
-	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | EN  | M3)) \
-					/* hsusb1_dir */\
-	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN  | M3)) \
-					/* hsusb1_nxt */\
-	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M4)) \
-	/* Die to Die */\
-	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
-
-#endif