Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

5 files changed, 0 insertions, 393 deletions

diff --git a/qemu/roms/u-boot/board/sbc8641d/Makefile b/qemu/roms/u-boot/board/sbc8641d/Makefile
deleted file mode 100644
index a9b20266b..000000000
--- a/qemu/roms/u-boot/board/sbc8641d/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= sbc8641d.o
-obj-y	+= law.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/qemu/roms/u-boot/board/sbc8641d/README b/qemu/roms/u-boot/board/sbc8641d/README
deleted file mode 100644
index a051466a1..000000000
--- a/qemu/roms/u-boot/board/sbc8641d/README
+++ /dev/null
@@ -1,28 +0,0 @@
-Wind River SBC8641D reference board
-===========================
-
-Created 06/14/2007 Joe Hamman
-Copyright 2007, Embedded Specialties, Inc.
-Copyright 2007 Wind River Systemes, Inc.
------------------------------
-
-1. Building U-Boot
-------------------
-The SBC8641D code is known to build using ELDK 4.1.
-
-    $ make sbc8641d_config
-    Configuring for sbc8641d board...
-
-    $ make
-
-
-2. Switch and Jumper Settings
------------------------------
-All Jumpers & Switches are in their default positions.  Please refer to
-the board documentation for details.  Some settings control CPU voltages
-and settings may change with board revisions.
-
-3. Known limitations
---------------------
-PCI:
-	The PCI command may hang if no boards are present in either slot.
diff --git a/qemu/roms/u-boot/board/sbc8641d/ddr.c b/qemu/roms/u-boot/board/sbc8641d/ddr.c
deleted file mode 100644
index b31ea3432..000000000
--- a/qemu/roms/u-boot/board/sbc8641d/ddr.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/qemu/roms/u-boot/board/sbc8641d/law.c b/qemu/roms/u-boot/board/sbc8641d/law.c
deleted file mode 100644
index c4e736b8a..000000000
--- a/qemu/roms/u-boot/board/sbc8641d/law.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW (Local Access Window) configuration:
- *
- * 0x0000_0000	DDR			256M
- * 0x1000_0000	DDR2			256M
- * 0x8000_0000	PCIE1 MEM		512M
- * 0xa000_0000	PCIE2 MEM		512M
- * 0xc000_0000	RapidIO			512M
- * 0xe200_0000	PCIE1 IO		16M
- * 0xe300_0000	PCIE2 IO		16M
- * 0xf800_0000	CCSRBAR			2M
- * 0xfe00_0000	FLASH (boot bank)	32M
- *
- */
-
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-		 LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
-#endif
-	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/qemu/roms/u-boot/board/sbc8641d/sbc8641d.c b/qemu/roms/u-boot/board/sbc8641d/sbc8641d.c
deleted file mode 100644
index 4906be488..000000000
--- a/qemu/roms/u-boot/board/sbc8641d/sbc8641d.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
- * Copyright 2007 Embedded Specialties, Inc.
- * Joe Hamman joe.hamman@embeddedspecialties.com
- *
- * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-long int fixed_sdram (void);
-
-int board_early_init_f (void)
-{
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("Board: Wind River SBC8641D\n");
-
-	return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
-	long dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = fsl_ddr_sdram();
-#else
-	dram_size = fixed_sdram ();
-#endif
-
-	debug ("    DDR: ");
-	return dram_size;
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
-	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
-	uint *p;
-
-	puts ("SDRAM test phase 1:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	puts ("SDRAM test phase 2:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	puts ("SDRAM test passed.\n");
-	return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-long int fixed_sdram (void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
-	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
-	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
-	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
-	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
-	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
-	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
-	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
-	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
-
-	asm ("sync;isync");
-
-	udelay (500);
-
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
-	asm ("sync; isync");
-
-	udelay (500);
-	ddr = &immap->im_ddr2;
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
-	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
-	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
-	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
-	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
-	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
-	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
-	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
-	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
-	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
-	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
-	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
-	ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
-	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
-	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
-
-	asm ("sync;isync");
-
-	udelay (500);
-
-	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
-	asm ("sync; isync");
-
-	udelay (500);
-#endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif				/* !defined(CONFIG_SPD_EEPROM) */
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif /* CONFIG_PCI */
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup (void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-}
-#endif
-
-void sbc8641d_reset_board (void)
-{
-	puts ("Resetting board....\n");
-}
-
-/*
- * get_board_sys_clk
- *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long get_board_sys_clk (ulong dummy)
-{
-	int i;
-	ulong val = 0;
-
-	i = 5;
-	i &= 0x07;
-
-	switch (i) {
-	case 0:
-		val = 33000000;
-		break;
-	case 1:
-		val = 40000000;
-		break;
-	case 2:
-		val = 50000000;
-		break;
-	case 3:
-		val = 66000000;
-		break;
-	case 4:
-		val = 83000000;
-		break;
-	case 5:
-		val = 100000000;
-		break;
-	case 6:
-		val = 134000000;
-		break;
-	case 7:
-		val = 166000000;
-		break;
-	}
-
-	return val;
-}
-
-void board_reset(void)
-{
-#ifdef CONFIG_SYS_RESET_ADDRESS
-	ulong addr = CONFIG_SYS_RESET_ADDRESS;
-
-	/* flush and disable I/D cache */
-	__asm__ __volatile__ ("mfspr	3, 1008"	::: "r3");
-	__asm__ __volatile__ ("ori	5, 5, 0xcc00"	::: "r5");
-	__asm__ __volatile__ ("ori	4, 3, 0xc00"	::: "r4");
-	__asm__ __volatile__ ("andc	5, 3, 5"	::: "r5");
-	__asm__ __volatile__ ("sync");
-	__asm__ __volatile__ ("mtspr	1008, 4");
-	__asm__ __volatile__ ("isync");
-	__asm__ __volatile__ ("sync");
-	__asm__ __volatile__ ("mtspr	1008, 5");
-	__asm__ __volatile__ ("isync");
-	__asm__ __volatile__ ("sync");
-
-	/*
-	 * SRR0 has system reset vector, SRR1 has default MSR value
-	 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
-	 */
-	__asm__ __volatile__ ("mtspr	26, %0"		:: "r" (addr));
-	__asm__ __volatile__ ("li	4, (1 << 6)"	::: "r4");
-	__asm__ __volatile__ ("mtspr	27, 4");
-	__asm__ __volatile__ ("rfi");
-#endif
-}