Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

4 files changed, 0 insertions, 671 deletions

diff --git a/qemu/roms/u-boot/board/samsung/goni/Makefile b/qemu/roms/u-boot/board/samsung/goni/Makefile
deleted file mode 100644
index 2cdc21d85..000000000
--- a/qemu/roms/u-boot/board/samsung/goni/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= goni.o onenand.o
-obj-y	+= lowlevel_init.o
diff --git a/qemu/roms/u-boot/board/samsung/goni/goni.c b/qemu/roms/u-boot/board/samsung/goni/goni.c
deleted file mode 100644
index 61b9ece03..000000000
--- a/qemu/roms/u-boot/board/samsung/goni/goni.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- *  Copyright (C) 2008-2009 Samsung Electronics
- *  Minkyu Kang <mk7.kang@samsung.com>
- *  Kyungmin Park <kyungmin.park@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc.h>
-#include <power/pmic.h>
-#include <usb/s3c_udc.h>
-#include <asm/arch/cpu.h>
-#include <power/max8998_pmic.h>
-#include <samsung/misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct s5pc110_gpio *s5pc110_gpio;
-
-u32 get_board_rev(void)
-{
-	return 0;
-}
-
-int board_init(void)
-{
-	/* Set Initial global variables */
-	s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE;
-
-	gd->bd->bi_arch_number = MACH_TYPE_GONI;
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	return 0;
-}
-
-int power_init_board(void)
-{
-	int ret;
-
-	/*
-	 * For PMIC the I2C bus is named as I2C5, but it is connected
-	 * to logical I2C adapter 0
-	 */
-	ret = pmic_init(I2C_0);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
-			PHYS_SDRAM_3_SIZE;
-
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	puts("Board:\tGoni\n");
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	int i, ret, ret_sd = 0;
-
-	/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
-	s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
-
-	/*
-	 * MMC0 GPIO
-	 * GPG0[0]	SD_0_CLK
-	 * GPG0[1]	SD_0_CMD
-	 * GPG0[2]	SD_0_CDn	-> Not used
-	 * GPG0[3:6]	SD_0_DATA[0:3]
-	 */
-	for (i = 0; i < 7; i++) {
-		if (i == 2)
-			continue;
-		/* GPG0[0:6] special function 2 */
-		s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
-		/* GPG0[0:6] pull disable */
-		s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
-		/* GPG0[0:6] drv 4x */
-		s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
-	}
-
-	ret = s5p_mmc_init(0, 4);
-	if (ret)
-		error("MMC: Failed to init MMC:0.\n");
-
-	/*
-	 * SD card (T_FLASH) detect and init
-	 * T_FLASH_DETECT: EINT28: GPH3[4] input mode
-	 */
-	s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT);
-	s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP);
-
-	if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) {
-		for (i = 0; i < 7; i++) {
-			if (i == 2)
-				continue;
-
-			/* GPG2[0:6] special function 2 */
-			s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2);
-			/* GPG2[0:6] pull disable */
-			s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE);
-			/* GPG2[0:6] drv 4x */
-			s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X);
-		}
-
-		ret_sd = s5p_mmc_init(2, 4);
-		if (ret_sd)
-			error("MMC: Failed to init SD card (MMC:2).\n");
-	}
-
-	return ret & ret_sd;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-static int s5pc1xx_phy_control(int on)
-{
-	int ret;
-	static int status;
-	struct pmic *p = pmic_get("MAX8998_PMIC");
-	if (!p)
-		return -ENODEV;
-
-	if (pmic_probe(p))
-		return -1;
-
-	if (on && !status) {
-		ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
-				      MAX8998_LDO3, LDO_ON);
-		ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
-				      MAX8998_LDO8, LDO_ON);
-		if (ret) {
-			puts("MAX8998 LDO setting error!\n");
-			return -1;
-		}
-		status = 1;
-	} else if (!on && status) {
-		ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
-				      MAX8998_LDO3, LDO_OFF);
-		ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
-				      MAX8998_LDO8, LDO_OFF);
-		if (ret) {
-			puts("MAX8998 LDO setting error!\n");
-			return -1;
-		}
-		status = 0;
-	}
-	udelay(10000);
-
-	return 0;
-}
-
-struct s3c_plat_otg_data s5pc110_otg_data = {
-	.phy_control = s5pc1xx_phy_control,
-	.regs_phy = S5PC110_PHY_BASE,
-	.regs_otg = S5PC110_OTG_BASE,
-	.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
-};
-#endif
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	set_board_info();
-#endif
-	return 0;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/samsung/goni/lowlevel_init.S b/qemu/roms/u-boot/board/samsung/goni/lowlevel_init.S
deleted file mode 100644
index d52bc09f8..000000000
--- a/qemu/roms/u-boot/board/samsung/goni/lowlevel_init.S
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/power.h>
-
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has S5PC100 GPIO base, 0xE0300000
- * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
- * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
- */
-
-	.globl lowlevel_init
-lowlevel_init:
-	mov	r11, lr
-
-	/* r5 has always zero */
-	mov	r5, #0
-
-	ldr	r7, =S5PC100_GPIO_BASE
-	ldr	r8, =S5PC100_GPIO_BASE
-	/* Read CPU ID */
-	ldr	r2, =S5PC110_PRO_ID
-	ldr	r0, [r2]
-	mov	r1, #0x00010000
-	and	r0, r0, r1
-	cmp	r0, r5
-	beq	100f
-	ldr	r8, =S5PC110_GPIO_BASE
-100:
-	/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
-	cmp	r7, r8
-	beq	skip_check_didle			@ Support C110 only
-
-	ldr	r0, =S5PC110_RST_STAT
-	ldr	r1, [r0]
-	and	r1, r1, #0x000D0000
-	cmp	r1, #(0x1 << 19)			@ DEEPIDLE_WAKEUP
-	beq	didle_wakeup
-	cmp	r7, r8
-
-skip_check_didle:
-	addeq	r0, r8, #0x280				@ S5PC100_GPIO_J4
-	addne	r0, r8, #0x2C0				@ S5PC110_GPIO_J4
-	ldr	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
-	bic	r1, r1, #(0xf << 4)			@ 1 * 4-bit
-	orr	r1, r1, #(0x1 << 4)
-	str	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
-
-	ldr	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
-	bic	r1, r1, #(1 << 1)
-	str	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
-
-	/* Don't setup at s5pc100 */
-	beq	100f
-
-	/*
-	 * Initialize Async Register Setting for EVT1
-	 * Because we are setting EVT1 as the default value of EVT0,
-	 * setting EVT0 as well does not make things worse.
-	 * Thus, for the simplicity, we set for EVT0, too
-	 *
-	 * The "Async Registers" are:
-	 *	0xE0F0_0000
-	 *	0xE1F0_0000
-	 *	0xF180_0000
-	 *	0xF190_0000
-	 *	0xF1A0_0000
-	 *	0xF1B0_0000
-	 *	0xF1C0_0000
-	 *	0xF1D0_0000
-	 *	0xF1E0_0000
-	 *	0xF1F0_0000
-	 *	0xFAF0_0000
-	 */
-	ldr     r0, =0xe0f00000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	ldr     r0, =0xe1f00000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	ldr     r0, =0xf1800000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	ldr     r0, =0xf1900000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	ldr     r0, =0xf1a00000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	ldr     r0, =0xf1b00000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	ldr     r0, =0xf1c00000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	ldr     r0, =0xf1d00000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	ldr     r0, =0xf1e00000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	ldr     r0, =0xf1f00000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	ldr     r0, =0xfaf00000
-	ldr     r1, [r0]
-	bic     r1, r1, #0x1
-	str     r1, [r0]
-
-	/*
-	 * Diable ABB block to reduce sleep current at low temperature
-	 * Note that it's hidden register setup don't modify it
-	 */
-	ldr	r0, =0xE010C300
-	ldr	r1, =0x00800000
-	str	r1, [r0]
-
-100:
-	/* IO retension release */
-	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
-	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
-	ldr	r1, [r0]
-	ldreq	r2, =(1 << 31)				@ IO_RET_REL
-	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
-	orr	r1, r1, r2
-	/* Do not release retention here for S5PC110 */
-	streq	r1, [r0]
-
-	/* Disable Watchdog */
-	ldreq	r0, =S5PC100_WATCHDOG_BASE		@ 0xEA200000
-	ldrne	r0, =S5PC110_WATCHDOG_BASE		@ 0xE2700000
-	str	r5, [r0]
-
-	/* setting SRAM */
-	ldreq	r0, =S5PC100_SROMC_BASE
-	ldrne	r0, =S5PC110_SROMC_BASE
-	ldr	r1, =0x9
-	str	r1, [r0]
-
-	/* S5PC100 has 3 groups of interrupt sources */
-	ldreq	r0, =S5PC100_VIC0_BASE			@ 0xE4000000
-	ldrne	r0, =S5PC110_VIC0_BASE			@ 0xF2000000
-	add	r1, r0, #0x00100000
-	add	r2, r0, #0x00200000
-
-	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
-	mvn	r3, #0x0
-	str	r3, [r0, #0x14]				@ INTENCLEAR
-	str	r3, [r1, #0x14]				@ INTENCLEAR
-	str	r3, [r2, #0x14]				@ INTENCLEAR
-
-	/* Set all interrupts as IRQ */
-	str	r5, [r0, #0xc]				@ INTSELECT
-	str	r5, [r1, #0xc]				@ INTSELECT
-	str	r5, [r2, #0xc]				@ INTSELECT
-
-	/* Pending Interrupt Clear */
-	str	r5, [r0, #0xf00]			@ INTADDRESS
-	str	r5, [r1, #0xf00]			@ INTADDRESS
-	str	r5, [r2, #0xf00]			@ INTADDRESS
-
-	/* for UART */
-	bl	uart_asm_init
-
-	bl	internal_ram_init
-
-	cmp	r7, r8
-	/* Clear wakeup status register */
-	ldreq	r0, =S5PC100_WAKEUP_STAT
-	ldrne	r0, =S5PC110_WAKEUP_STAT
-	ldr	r1, [r0]
-	str	r1, [r0]
-
-	/* IO retension release */
-	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
-	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
-	ldr	r1, [r0]
-	ldreq	r2, =(1 << 31)				@ IO_RET_REL
-	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
-	orr	r1, r1, r2
-	str	r1, [r0]
-
-	b	1f
-
-didle_wakeup:
-	/* Wait when APLL is locked */
-	ldr	r0, =0xE0100100			@ S5PC110_APLL_CON
-lockloop:
-	ldr	r1, [r0]
-	and	r1, r1, #(1 << 29)
-	cmp	r1, #(1 << 29)
-	bne	lockloop
-
-	ldr	r0, =S5PC110_INFORM0
-	ldr	r1, [r0]
-	mov	pc, r1
-	nop
-	nop
-	nop
-	nop
-	nop
-
-1:
-	mov	lr, r11
-	mov	pc, lr
-
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-system_clock_init:
-	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
-
-	/* Check S5PC100 */
-	cmp	r7, r8
-	bne	110f
-100:
-	/* Set Lock Time */
-	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
-	str	r1, [r0, #0x000]		@ S5PC100_APLL_LOCK
-	str	r1, [r0, #0x004]		@ S5PC100_MPLL_LOCK
-	str	r1, [r0, #0x008]		@ S5PC100_EPLL_LOCK
-	str	r1, [r0, #0x00C]		@ S5PC100_HPLL_LOCK
-
-	/* S5P_APLL_CON */
-	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
-	str	r1, [r0, #0x100]
-	/* S5P_MPLL_CON */
-	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
-	str	r1, [r0, #0x104]
-	/* S5P_EPLL_CON */
-	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
-	str	r1, [r0, #0x108]
-	/* S5P_HPLL_CON */
-	ldr	r1, =0x80600603		@ SDIV 3, PDIV 6, MDIV 96
-	str	r1, [r0, #0x10C]
-
-	ldr     r1, [r0, #0x300]
-	ldr     r2, =0x00003fff
-	bic     r1, r1, r2
-	ldr     r2, =0x00011301
-
-	orr	r1, r1, r2
-	str	r1, [r0, #0x300]
-	ldr     r1, [r0, #0x304]
-	ldr     r2, =0x00011110
-	orr     r1, r1, r2
-	str     r1, [r0, #0x304]
-	ldr     r1, =0x00000001
-	str     r1, [r0, #0x308]
-
-	/* Set Source Clock */
-	ldr	r1, =0x00001111			@ A, M, E, HPLL Muxing
-	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
-
-	b	200f
-110:
-	ldr	r0, =0xE010C000			@ S5PC110_PWR_CFG
-
-	/* Set OSC_FREQ value */
-	ldr	r1, =0xf
-	str	r1, [r0, #0x100]		@ S5PC110_OSC_FREQ
-
-	/* Set MTC_STABLE value */
-	ldr	r1, =0xffffffff
-	str	r1, [r0, #0x110]		@ S5PC110_MTC_STABLE
-
-	/* Set CLAMP_STABLE value */
-	ldr	r1, =0x3ff03ff
-	str	r1, [r0, #0x114]		@ S5PC110_CLAMP_STABLE
-
-	ldr	r0, =S5PC110_CLOCK_BASE		@ 0xE0100000
-
-	/* Set Clock divider */
-	ldr	r1, =0x14131330			@ 1:1:4:4, 1:4:5
-	str	r1, [r0, #0x300]
-	ldr	r1, =0x11110111			@ UART[3210]: MMC[3210]
-	str	r1, [r0, #0x310]
-
-	/* Set Lock Time */
-	ldr	r1, =0x2cf			@ Locktime : 30us
-	str	r1, [r0, #0x000]		@ S5PC110_APLL_LOCK
-	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
-	str	r1, [r0, #0x008]		@ S5PC110_MPLL_LOCK
-	str	r1, [r0, #0x010]		@ S5PC110_EPLL_LOCK
-	str	r1, [r0, #0x020]		@ S5PC110_VPLL_LOCK
-
-	/* S5PC110_APLL_CON */
-	ldr	r1, =0x80C80601			@ 800MHz
-	str	r1, [r0, #0x100]
-	/* S5PC110_MPLL_CON */
-	ldr	r1, =0x829B0C01			@ 667MHz
-	str	r1, [r0, #0x108]
-	/* S5PC110_EPLL_CON */
-	ldr	r1, =0x80600602			@  96MHz VSEL 0 P 6 M 96 S 2
-	str	r1, [r0, #0x110]
-	/* S5PC110_VPLL_CON */
-	ldr	r1, =0x806C0603			@  54MHz
-	str	r1, [r0, #0x120]
-
-	/* Set Source Clock */
-	ldr	r1, =0x10001111			@ A, M, E, VPLL Muxing
-	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
-
-	/* OneDRAM(DMC0) clock setting */
-	ldr	r1, =0x01000000			@ ONEDRAM_SEL[25:24] 1 SCLKMPLL
-	str	r1, [r0, #0x218]		@ S5PC110_CLK_SRC6
-	ldr	r1, =0x30000000			@ ONEDRAM_RATIO[31:28] 3 + 1
-	str	r1, [r0, #0x318]		@ S5PC110_CLK_DIV6
-
-	/* XCLKOUT = XUSBXTI 24MHz */
-	add	r2, r0, #0xE000			@ S5PC110_OTHERS
-	ldr     r1, [r2]
-	orr	r1, r1, #(0x3 << 8)		@ CLKOUT[9:8] 3 XUSBXTI
-	str	r1, [r2]
-
-	/* CLK_IP0 */
-	ldr	r1, =0x8fefeeb			@ DMC[1:0] PDMA0[3] IMEM[5]
-	str	r1, [r0, #0x460]		@ S5PC110_CLK_IP0
-
-	/* CLK_IP1 */
-	ldr	r1, =0xe9fdf0f9			@ FIMD[0] USBOTG[16]
-						@ NANDXL[24]
-	str	r1, [r0, #0x464]		@ S5PC110_CLK_IP1
-
-	/* CLK_IP2 */
-	ldr	r1, =0xf75f7fc			@ CORESIGHT[8] MODEM[9]
-						@ HOSTIF[10] HSMMC0[16]
-						@ HSMMC2[18] VIC[27:24]
-	str	r1, [r0, #0x468]		@ S5PC110_CLK_IP2
-
-	/* CLK_IP3 */
-	ldr	r1, =0x8eff038c			@ I2C[8:6]
-						@ SYSTIMER[16] UART0[17]
-						@ UART1[18] UART2[19]
-						@ UART3[20] WDT[22]
-						@ PWM[23] GPIO[26] SYSCON[27]
-	str	r1, [r0, #0x46c]		@ S5PC110_CLK_IP3
-
-	/* CLK_IP4 */
-	ldr	r1, =0xfffffff1			@ CHIP_ID[0] TZPC[8:5]
-	str	r1, [r0, #0x470]		@ S5PC110_CLK_IP3
-
-200:
-	/* wait at least 200us to stablize all clock */
-	mov	r2, #0x10000
-1:	subs	r2, r2, #1
-	bne	1b
-
-	mov	pc, lr
-
-internal_ram_init:
-	ldreq	r0, =0xE3800000
-	ldrne	r0, =0xF1500000
-	ldr	r1, =0x0
-	str	r1, [r0]
-
-	mov	pc, lr
-
-/*
- * uart_asm_init: Initialize UART's pins
- */
-uart_asm_init:
-	/* set GPIO to enable UART0-UART4 */
-	mov	r0, r8
-	ldr	r1, =0x22222222
-	str	r1, [r0, #0x0]			@ S5PC100_GPIO_A0_OFFSET
-	ldr	r1, =0x00002222
-	str	r1, [r0, #0x20]			@ S5PC100_GPIO_A1_OFFSET
-
-	/* Check S5PC100 */
-	cmp	r7, r8
-	bne	110f
-
-	/* UART_SEL GPK0[5] at S5PC100 */
-	add	r0, r8, #0x2A0			@ S5PC100_GPIO_K0_OFFSET
-	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
-	bic	r1, r1, #(0xf << 20)		@ 20 = 5 * 4-bit
-	orr	r1, r1, #(0x1 << 20)		@ Output
-	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
-
-	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
-	bic	r1, r1, #(0x3 << 10)		@ 10 = 5 * 2-bit
-	orr	r1, r1, #(0x2 << 10)		@ Pull-up enabled
-	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
-
-	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
-	orr	r1, r1, #(1 << 5)		@ 5 = 5 * 1-bit
-	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
-
-	b	200f
-110:
-	/*
-	 * Note that the following address
-	 * 0xE020'0360 is reserved address at S5PC100
-	 */
-	/* UART_SEL MP0_5[7] at S5PC110 */
-	add	r0, r8, #0x360			@ S5PC110_GPIO_MP0_5_OFFSET
-	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
-	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
-	orr	r1, r1, #(0x1 << 28)		@ Output
-	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
-
-	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
-	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
-	orr	r1, r1, #(0x2 << 14)		@ Pull-up enabled
-	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
-
-	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
-	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
-	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
-200:
-	mov	pc, lr
diff --git a/qemu/roms/u-boot/board/samsung/goni/onenand.c b/qemu/roms/u-boot/board/samsung/goni/onenand.c
deleted file mode 100644
index b74d8e8ac..000000000
--- a/qemu/roms/u-boot/board/samsung/goni/onenand.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2008-2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/onenand.h>
-#include <linux/mtd/samsung_onenand.h>
-#include <onenand_uboot.h>
-
-void onenand_board_init(struct mtd_info *mtd)
-{
-	struct onenand_chip *this = mtd->priv;
-
-	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
-	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
-	this->chip_probe = s5pc110_chip_probe;
-}