Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

6 files changed, 2692 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/sacsng/Makefile b/qemu/roms/u-boot/board/sacsng/Makefile
new file mode 100644
index 000000000..95e6b8d0c
--- /dev/null
+++ b/qemu/roms/u-boot/board/sacsng/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= sacsng.o flash.o clkinit.o
diff --git a/qemu/roms/u-boot/board/sacsng/clkinit.c b/qemu/roms/u-boot/board/sacsng/clkinit.c
new file mode 100644
index 000000000..2a28037dc
--- /dev/null
+++ b/qemu/roms/u-boot/board/sacsng/clkinit.c
@@ -0,0 +1,1009 @@
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Jon Diekema <diekema@cideas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/cpm_8260.h>
+#include <configs/sacsng.h>
+
+#include "clkinit.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int Daq64xSampling = 0;
+
+
+void Daq_BRG_Reset(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     volatile uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+     *brg_ptr |=  CPM_BRG_RST;
+     *brg_ptr &= ~CPM_BRG_RST;
+}
+
+void Daq_BRG_Disable(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     volatile uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+     *brg_ptr &= ~CPM_BRG_EN;
+}
+
+void Daq_BRG_Enable(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     volatile uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+     *brg_ptr |= CPM_BRG_EN;
+}
+
+uint Daq_BRG_Get_Div16(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     if (*brg_ptr & CPM_BRG_DIV16) {
+	 /* DIV16 active */
+	 return true;
+     }
+     else {
+	 /* DIV16 inactive */
+	 return false;
+     }
+}
+
+void Daq_BRG_Set_Div16(uint brg, uint div16)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     if (div16) {
+	 /* DIV16 active */
+	 *brg_ptr |=  CPM_BRG_DIV16;
+     }
+     else {
+	 /* DIV16 inactive */
+	 *brg_ptr &= ~CPM_BRG_DIV16;
+     }
+}
+
+uint Daq_BRG_Get_Count(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+     uint brg_cnt;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     /* Get the clock divider
+      *
+      * Note: A clock divider of 0 means divide by 1,
+      *       therefore we need to add 1 to the count.
+      */
+     brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
+     brg_cnt++;
+     if (*brg_ptr & CPM_BRG_DIV16) {
+	 brg_cnt *= 16;
+     }
+
+    return (brg_cnt);
+}
+
+void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     /*
+      * Note: A clock divider of 0 means divide by 1,
+      *	 therefore we need to subtract 1 from the count.
+      */
+     if (brg_cnt > 4096) {
+	 /* Prescale = Divide by 16 */
+	 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK)   |
+	     (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
+	 *brg_ptr |= CPM_BRG_DIV16;
+     }
+     else {
+	 /* Prescale = Divide by 1 */
+	 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
+	     ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
+	 *brg_ptr &= ~CPM_BRG_DIV16;
+     }
+}
+
+uint Daq_BRG_Get_ExtClk(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
+}
+
+char* Daq_BRG_Get_ExtClk_Description(uint brg)
+{
+     uint extc;
+
+     extc = Daq_BRG_Get_ExtClk(brg);
+
+     switch (brg + 1) {
+	 case 1:
+	 case 2:
+	 case 5:
+	 case 6: {
+	     switch (extc) {
+		 case 0: {
+		     return ("BRG_INT");
+		 }
+		 case 1: {
+		     return ("CLK3");
+		 }
+		 case 2: {
+		     return ("CLK5");
+		 }
+	     }
+	     return ("??1245??");
+	 }
+	 case 3:
+	 case 4:
+	 case 7:
+	 case 8: {
+	     switch (extc) {
+		 case 0: {
+		     return ("BRG_INT");
+		 }
+		 case 1: {
+		     return ("CLK9");
+		 }
+		 case 2: {
+		     return ("CLK15");
+		 }
+	     }
+	     return ("??3478??");
+	 }
+     }
+     return ("??9876??");
+}
+
+void Daq_BRG_Set_ExtClk(uint brg, uint extc)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
+		((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
+}
+
+uint Daq_BRG_Rate(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+     uint *brg_ptr;
+     uint brg_cnt;
+     uint brg_freq = 0;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     brg_ptr += brg;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg_ptr += (brg - 4);
+     }
+
+    brg_cnt = Daq_BRG_Get_Count(brg);
+
+    switch (Daq_BRG_Get_ExtClk(brg)) {
+	case CPM_BRG_EXTC_CLK3:
+	case CPM_BRG_EXTC_CLK5: {
+	    brg_freq = brg_cnt;
+	    break;
+	}
+	default: {
+	    brg_freq = (uint)BRG_INT_CLK / brg_cnt;
+	}
+    }
+    return (brg_freq);
+}
+
+uint Daq_Get_SampleRate(void)
+{
+     /*
+      * Read the BRG's to return the actual sample rate.
+      */
+     return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
+}
+
+void Daq_Init_Clocks(int sample_rate, int sample_64x)
+{
+    volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
+    uint mclk_divisor; /* MCLK divisor */
+    int  flag;         /* Interrupt state */
+
+    /* Save off the clocking data */
+    Daq64xSampling = sample_64x;
+
+    /*
+     * Limit the sample rate to some sensible values.
+     */
+    if (sample_rate > MAX_64x_SAMPLE_RATE) {
+	sample_rate = MAX_64x_SAMPLE_RATE;
+    }
+    if (sample_rate < MIN_SAMPLE_RATE) {
+	sample_rate = MIN_SAMPLE_RATE;
+    }
+
+    /*
+     * Initialize the MCLK/SCLK/LRCLK baud rate generators.
+     */
+
+    /* Setup MCLK */
+    Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+
+    /* Setup SCLK */
+#   ifdef RUN_SCLK_ON_BRG_INT
+	Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+#   else
+	Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
+#   endif
+
+    /* Setup LRCLK */
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+#   else
+	Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
+#   endif
+
+    /*
+     * Dynamically adjust MCLK based on the new sample rate.
+     */
+
+    /* Compute the divisors */
+    mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
+
+    /*
+     * Disable interrupt and save the current state
+     */
+    flag = disable_interrupts();
+
+    /* Setup MCLK */
+    Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
+
+    /* Setup SCLK */
+#   ifdef RUN_SCLK_ON_BRG_INT
+	Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
+#   else
+	Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
+#   endif
+
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	Daq_BRG_Set_Count(LRCLK_BRG,
+			  mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
+#   else
+	Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
+#   endif
+
+    /*
+     * Restore the Interrupt state
+     */
+     if (flag) {
+	 enable_interrupts();
+     }
+
+    /* Enable the clock drivers */
+    iopa->pdat &= ~SLRCLK_EN_MASK;
+}
+
+void Daq_Stop_Clocks(void)
+
+{
+#ifdef TIGHTEN_UP_BRG_TIMING
+    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+    register uint mclk_brg;       /* MCLK  BRG value */
+    register uint sclk_brg;       /* SCLK  BRG value */
+    register uint lrclk_brg;      /* LRCLK BRG value */
+    unsigned long flag;           /* Interrupt flags */
+#endif
+
+#   ifdef TIGHTEN_UP_BRG_TIMING
+	/*
+	 * Obtain MCLK BRG reset/disabled value
+	 */
+#       if (MCLK_BRG == 0)
+	    mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 1)
+	    mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 2)
+	    mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 3)
+	    mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 4)
+	    mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 5)
+	    mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 6)
+	    mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 7)
+	    mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain SCLK BRG reset/disabled value
+	 */
+#       if (SCLK_BRG == 0)
+	    sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 1)
+	    sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 2)
+	    sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 3)
+	    sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 4)
+	    sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 5)
+	    sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 6)
+	    sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 7)
+	    sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain LRCLK BRG reset/disabled value
+	 */
+#       if (LRCLK_BRG == 0)
+	    lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Disable interrupt and save the current state
+	 */
+	flag = disable_interrupts();
+
+	/*
+	 * Set reset on MCLK BRG
+	 */
+#       if (MCLK_BRG == 0)
+	    *IM_BRGC1 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 1)
+	    *IM_BRGC2 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 2)
+	    *IM_BRGC3 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 3)
+	    *IM_BRGC4 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 4)
+	    *IM_BRGC5 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 5)
+	    *IM_BRGC6 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 6)
+	    *IM_BRGC7 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 7)
+	    *IM_BRGC8 = mclk_brg;
+#       endif
+
+	/*
+	 * Set reset on SCLK BRG
+	 */
+#       if (SCLK_BRG == 0)
+	    *IM_BRGC1 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 1)
+	    *IM_BRGC2 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 2)
+	    *IM_BRGC3 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 3)
+	    *IM_BRGC4 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 4)
+	    *IM_BRGC5 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 5)
+	    *IM_BRGC6 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 6)
+	    *IM_BRGC7 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 7)
+	    *IM_BRGC8 = sclk_brg;
+#       endif
+
+	/*
+	 * Set reset on LRCLK BRG
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = lrclk_brg;
+#       endif
+
+	/*
+	 * Clear reset on MCLK BRG
+	 */
+#       if (MCLK_BRG == 0)
+	    *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 1)
+	    *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 2)
+	    *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 3)
+	    *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 4)
+	    *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 5)
+	    *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 6)
+	    *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 7)
+	    *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+
+	/*
+	 * Clear reset on SCLK BRG
+	 */
+#       if (SCLK_BRG == 0)
+	    *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 1)
+	    *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 2)
+	    *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 3)
+	    *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 4)
+	    *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 5)
+	    *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 6)
+	    *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 7)
+	    *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+
+	/*
+	 * Clear reset on LRCLK BRG
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+
+	/*
+	 * Restore the Interrupt state
+	 */
+	if (flag) {
+	    enable_interrupts();
+	}
+#   else
+	/*
+	 * Reset the clocks
+	 */
+	Daq_BRG_Reset(MCLK_BRG);
+	Daq_BRG_Reset(SCLK_BRG);
+	Daq_BRG_Reset(LRCLK_BRG);
+#   endif
+}
+
+void Daq_Start_Clocks(int sample_rate)
+
+{
+#ifdef TIGHTEN_UP_BRG_TIMING
+    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+    register uint mclk_brg;       /* MCLK  BRG value */
+    register uint sclk_brg;       /* SCLK  BRG value */
+    register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
+    register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
+    uint          lrclk_brg;      /* LRCLK BRG value */
+    unsigned long flags;          /* Interrupt flags */
+    uint          sclk_cnt;       /* SCLK count */
+    uint          delay_cnt;      /* Delay count */
+#endif
+
+#   ifdef TIGHTEN_UP_BRG_TIMING
+	/*
+	 * Obtain the enabled MCLK BRG value
+	 */
+#       if (MCLK_BRG == 0)
+	    mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 1)
+	    mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 2)
+	    mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 3)
+	    mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 4)
+	    mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 5)
+	    mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 6)
+	    mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 7)
+	    mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain the enabled SCLK BRG value
+	 */
+#       if (SCLK_BRG == 0)
+	    sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 1)
+	    sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 2)
+	    sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 3)
+	    sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 4)
+	    sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 5)
+	    sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 6)
+	    sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 7)
+	    sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain the enabled LRCLK BRG value
+	 */
+#       if (LRCLK_BRG == 0)
+	    lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+
+	/* Save off the real LRCLK value */
+	real_lrclk_brg = lrclk_brg;
+
+	/* Obtain the current SCLK count */
+	sclk_cnt  = ((sclk_brg & 0x00001FFE) >> 1) + 1;
+
+	/* Compute the delay as a function of SCLK count */
+	delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
+	if (DaqSampleRate == 43402) {
+	  delay_cnt++;
+	}
+
+	/* Clear out the count */
+	temp_lrclk_brg = sclk_brg & ~0x00001FFE;
+
+	/* Insert the count */
+	temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) &  0x00001FFE;
+
+	/*
+	 * Disable interrupt and save the current state
+	 */
+	flag = disable_interrupts();
+
+	/*
+	 * Enable MCLK BRG
+	 */
+#       if (MCLK_BRG == 0)
+	    *IM_BRGC1 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 1)
+	    *IM_BRGC2 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 2)
+	    *IM_BRGC3 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 3)
+	    *IM_BRGC4 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 4)
+	    *IM_BRGC5 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 5)
+	    *IM_BRGC6 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 6)
+	    *IM_BRGC7 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 7)
+	    *IM_BRGC8 = mclk_brg;
+#       endif
+
+	/*
+	 * Enable SCLK BRG
+	 */
+#       if (SCLK_BRG == 0)
+	    *IM_BRGC1 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 1)
+	    *IM_BRGC2 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 2)
+	    *IM_BRGC3 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 3)
+	    *IM_BRGC4 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 4)
+	    *IM_BRGC5 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 5)
+	    *IM_BRGC6 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 6)
+	    *IM_BRGC7 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 7)
+	    *IM_BRGC8 = sclk_brg;
+#       endif
+
+	/*
+	 * Enable LRCLK BRG (1st time - temporary)
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = temp_lrclk_brg;
+#       endif
+
+	/*
+	 * Enable LRCLK BRG (2nd time - permanent)
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = real_lrclk_brg;
+#       endif
+
+	/*
+	 * Restore the Interrupt state
+	 */
+	if (flag) {
+	    enable_interrupts();
+	}
+#   else
+	/*
+	 * Enable the clocks
+	 */
+	Daq_BRG_Enable(LRCLK_BRG);
+	Daq_BRG_Enable(SCLK_BRG);
+	Daq_BRG_Enable(MCLK_BRG);
+#   endif
+}
+
+void Daq_Display_Clocks(void)
+
+{
+    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+    uint mclk_divisor; /* Detected MCLK divisor */
+    uint sclk_divisor; /* Detected SCLK divisor */
+
+    printf("\nBRG:\n");
+    if (immr->im_brgc4 != 0) {
+	printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  MCLK\n",
+	       immr->im_brgc4,
+	       (uint)&(immr->im_brgc4),
+	       Daq_BRG_Get_Count(3),
+	       Daq_BRG_Get_ExtClk(3),
+	       Daq_BRG_Get_ExtClk_Description(3));
+    }
+    if (immr->im_brgc8 != 0) {
+	printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCLK\n",
+	       immr->im_brgc8,
+	       (uint)&(immr->im_brgc8),
+	       Daq_BRG_Get_Count(7),
+	       Daq_BRG_Get_ExtClk(7),
+	       Daq_BRG_Get_ExtClk_Description(7));
+    }
+    if (immr->im_brgc6 != 0) {
+	printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  LRCLK\n",
+	       immr->im_brgc6,
+	       (uint)&(immr->im_brgc6),
+	       Daq_BRG_Get_Count(5),
+	       Daq_BRG_Get_ExtClk(5),
+	       Daq_BRG_Get_ExtClk_Description(5));
+    }
+    if (immr->im_brgc1 != 0) {
+	printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC1\n",
+	       immr->im_brgc1,
+	       (uint)&(immr->im_brgc1),
+	       Daq_BRG_Get_Count(0),
+	       Daq_BRG_Get_ExtClk(0),
+	       Daq_BRG_Get_ExtClk_Description(0));
+    }
+    if (immr->im_brgc2 != 0) {
+	printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC2\n",
+	       immr->im_brgc2,
+	       (uint)&(immr->im_brgc2),
+	       Daq_BRG_Get_Count(1),
+	       Daq_BRG_Get_ExtClk(1),
+	       Daq_BRG_Get_ExtClk_Description(1));
+    }
+    if (immr->im_brgc3 != 0) {
+	printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCC1\n",
+	       immr->im_brgc3,
+	       (uint)&(immr->im_brgc3),
+	       Daq_BRG_Get_Count(2),
+	       Daq_BRG_Get_ExtClk(2),
+	       Daq_BRG_Get_ExtClk_Description(2));
+    }
+    if (immr->im_brgc5 != 0) {
+	printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
+	       immr->im_brgc5,
+	       (uint)&(immr->im_brgc5),
+	       Daq_BRG_Get_Count(4),
+	       Daq_BRG_Get_ExtClk(4),
+	       Daq_BRG_Get_ExtClk_Description(4));
+    }
+    if (immr->im_brgc7 != 0) {
+	printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
+	       immr->im_brgc7,
+	       (uint)&(immr->im_brgc7),
+	       Daq_BRG_Get_Count(6),
+	       Daq_BRG_Get_ExtClk(6),
+	       Daq_BRG_Get_ExtClk_Description(6));
+    }
+
+#   ifdef RUN_SCLK_ON_BRG_INT
+	mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
+#   else
+	mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
+#   endif
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
+#   else
+	sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
+#   endif
+
+    printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
+    printf("\tMCLK  %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
+	   Daq_BRG_Rate(MCLK_BRG),
+	   mclk_divisor,
+	   mclk_divisor * sclk_divisor);
+#   ifdef RUN_SCLK_ON_BRG_INT
+	printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
+	       Daq_BRG_Rate(SCLK_BRG),
+	       sclk_divisor);
+#   else
+	printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
+	       Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
+	       sclk_divisor);
+#   endif
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	printf("\tLRCLK %8d Hz\n",
+	       Daq_BRG_Rate(LRCLK_BRG));
+#   else
+#       ifdef RUN_SCLK_ON_BRG_INT
+	    printf("\tLRCLK %8d Hz\n",
+		   Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
+#       else
+	    printf("\tLRCLK %8d Hz\n",
+		   Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
+#       endif
+#   endif
+    printf("\n");
+}
diff --git a/qemu/roms/u-boot/board/sacsng/clkinit.h b/qemu/roms/u-boot/board/sacsng/clkinit.h
new file mode 100644
index 000000000..3f759dd48
--- /dev/null
+++ b/qemu/roms/u-boot/board/sacsng/clkinit.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Jon Diekema <diekema@cideas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SLRCLK_EN_MASK  0x00040000 /* PA13 - SLRCLK_EN*     */
+
+#define MIN_SAMPLE_RATE       4000 /* Minimum sample rate */
+#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
+#define MAX_64x_SAMPLE_RATE  86805 /* Maximum  64x sample rate */
+
+#define KHZ          ((uint)1000)
+#define MHZ          ((uint)(1000 * KHZ))
+
+#define MCLK_BRG     3        /* MCLK, Master CLocK for the A/D & D/A   */
+#define SCLK_BRG     7        /* SCLK, Sample CLocK for the A/D & D/A   */
+#define LRCLK_BRG    5        /* LRCLK, L/R CLocK for the A/D & D/A     */
+			      /*   0 == BRG1 (used for SMC1)            */
+			      /*   1 == BRG2 (used for SMC2)            */
+			      /*   2 == BRG3 (used for SCC1)            */
+			      /*   3 == BRG4 (MCLK)                     */
+			      /*   4 == BRG5                            */
+			      /*   5 == BRG6 (LRCLK)                    */
+			      /*   6 == BRG7                            */
+			      /*   7 == BRG8 (SCLK)                     */
+
+#define MCLK_DIVISOR  4       /*  SCLK = MCLK / MCLK_DIVISOR */
+#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
+			      /* LRCLK = SCLK / SCLK_DIVISOR */
+
+#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing      */
+#define RUN_SCLK_ON_BRG_INT      /* Run SCLK on BRG_INT instead of MCLK   */
+				 /* The 8260 (Mask B.3) seems to have     */
+				 /* problems generating SCLK from MCLK    */
+				 /* via CLK9.                             */
+#define RUN_LRCLK_ON_BRG_INT     /* Run LRCLK on BRG_INT instead of SCLK  */
+				 /* The 8260 (Mask B.3) seems to have     */
+				 /* problems generating LRCLK from SCLK   */
+
+#define NUM_LRCLKS_TO_STABILIZE 1  /* Number of LRCLK period (sample)     */
+				   /* to wait for the clock to stabilize  */
+
+#define CPM_CLK      (gd->bd->bi_cpmfreq)
+#define DFBRG        4
+#define BRG_INT_CLK  (CPM_CLK * 2 / DFBRG)
+			      /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
+			      /* BRG = CPM * 2 / 4                */
+			      /* BRG = CPM / 2                    */
+
+#define CPM_BRG_EXTC_MASK	((uint)0x0000C000)
+#define CPM_BRG_EXTC_SHIFT      14
+
+#define CPM_BRG_DIV16_MASK	((uint)0x00000001)
+#define CPM_BRG_DIV16_SHIFT     1
+
+#define CPM_BRG_EXTC_BRGCLK     0
+#define CPM_BRG_EXTC_CLK3       1
+#define CPM_BRG_EXTC_CLK9       CPM_BRG_EXTC_CLK3
+#define CPM_BRG_EXTC_CLK5       2
+#define CPM_BRG_EXTC_CLK15      CPM_BRG_EXTC_CLK5
+
+#define IM_BRGC1 ((uint *)0xf00119f0)
+#define IM_BRGC2 ((uint *)0xf00119f4)
+#define IM_BRGC3 ((uint *)0xf00119f8)
+#define IM_BRGC4 ((uint *)0xf00119fc)
+#define IM_BRGC5 ((uint *)0xf00115f0)
+#define IM_BRGC6 ((uint *)0xf00115f4)
+#define IM_BRGC7 ((uint *)0xf00115f8)
+#define IM_BRGC8 ((uint *)0xf00115fc)
+
+/*
+ * External declarations
+ */
+
+extern int Daq64xSampling;
+
+extern void Daq_BRG_Reset(uint brg);
+extern void Daq_BRG_Run(uint brg);
+
+extern void Daq_BRG_Disable(uint brg);
+extern void Daq_BRG_Enable(uint brg);
+
+extern uint Daq_BRG_Get_Div16(uint brg);
+extern void Daq_BRG_Set_Div16(uint brg, uint div16);
+
+extern uint Daq_BRG_Get_Count(uint brg);
+extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);
+
+extern uint Daq_BRG_Get_ExtClk(uint brg);
+extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
+extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
+
+extern uint Daq_BRG_Rate(uint brg);
+
+extern uint Daq_Get_SampleRate(void);
+
+extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
+extern void Daq_Stop_Clocks(void);
+extern void Daq_Start_Clocks(int sample_rate);
+extern void Daq_Display_Clocks(void);
diff --git a/qemu/roms/u-boot/board/sacsng/flash.c b/qemu/roms/u-boot/board/sacsng/flash.c
new file mode 100644
index 000000000..686fb225d
--- /dev/null
+++ b/qemu/roms/u-boot/board/sacsng/flash.c
@@ -0,0 +1,507 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <configs/sacsng.h>
+
+
+#undef  DEBUG
+
+#ifndef	CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#endif
+#ifndef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+#endif
+
+
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_short *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_short *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_short *)CONFIG_SYS_FLASH1_BASE, &flash_info[1]);
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CONFIG_ENV_ADDR,
+			      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	/*
+	 * We only report the primary flash for U-Boot's use.
+	 */
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_short *addr, flash_info_t *info)
+{
+	short i;
+	ushort value;
+	ulong  base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAAAA;
+	addr[0x02AA] = 0x5555;
+	addr[0x0555] = 0x9090;
+	__asm__ __volatile__(" sync\n ");
+
+	value = addr[0];
+#ifdef DEBUG
+	printf("Flash manufacturer 0x%04X\n", value);
+#endif
+
+	if(value == (ushort)AMD_MANUFACT) {
+		info->flash_id = FLASH_MAN_AMD;
+	} else if (value == (ushort)FUJ_MANUFACT) {
+		info->flash_id = FLASH_MAN_FUJ;
+	} else {
+#ifdef DEBUG
+		printf("Unknown flash manufacturer 0x%04X\n", value);
+#endif
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+#ifdef DEBUG
+	printf("Flash type 0x%04X\n", value);
+#endif
+
+	if(value == (ushort)AMD_ID_LV400T) {
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;	/* => 0.5 MB		*/
+	} else if(value == (ushort)AMD_ID_LV400B) {
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;	/* => 0.5 MB		*/
+	} else if(value == (ushort)AMD_ID_LV800T) {
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;	/* => 1 MB		*/
+	} else if(value == (ushort)AMD_ID_LV800B) {
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;	/* => 1 MB		*/
+	} else if(value == (ushort)AMD_ID_LV160T) {
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;	/* => 2 MB		*/
+	} else if(value == (ushort)AMD_ID_LV160B) {
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;	/* => 2 MB		*/
+	} else if(value == (ushort)AMD_ID_LV320T) {
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;	/* => 4 MB		*/
+	} else if(value == (ushort)AMD_ID_LV320B) {
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;	/* => 4 MB		*/
+	} else {
+#ifdef DEBUG
+		printf("Unknown flash type 0x%04X\n", value);
+		info->size = CONFIG_SYS_FLASH_SIZE;
+#else
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+#endif
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 3) * 0x00010000);
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned short *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned short *)info->start[0];
+
+	}
+
+	addr[0] = 0xF0F0;	/* reset bank */
+	__asm__ __volatile__(" sync\n ");
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAAAA;
+	addr[0x02AA] = 0x5555;
+	addr[0x0555] = 0x8080;
+	addr[0x0555] = 0xAAAA;
+	addr[0x02AA] = 0x5555;
+	__asm__ __volatile__(" sync\n ");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_short*)(info->start[sect]);
+			addr[0] = 0x3030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_short*)(info->start[l_sect]);
+	while ((addr[0] & 0x0080) != 0x0080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			addr[0] = 0xF0F0;	/* reset bank */
+			__asm__ __volatile__(" sync\n ");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_short*)info->start[0];
+	addr[0] = 0xF0F0;	/* reset bank */
+	__asm__ __volatile__(" sync\n ");
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	ulong start;
+	int flag;
+	int j;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((*(vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* The original routine was designed to write 32 bit words to
+	 * 32 bit wide memory.	We have 16 bit wide memory so we do
+	 * two writes.	We write the LSB first at dest+2 and then the
+	 * MSB at dest (lousy big endian).
+	 */
+	dest += 2;
+	for(j = 0; j < 2; j++) {
+		addr[0x0555] = 0xAAAA;
+		addr[0x02AA] = 0x5555;
+		addr[0x0555] = 0xA0A0;
+		__asm__ __volatile__(" sync\n ");
+
+		*((vu_short *)dest) = (ushort)data;
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while (*(vu_short *)dest != (ushort)data) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+		dest -= 2;
+		data >>= 16;
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/qemu/roms/u-boot/board/sacsng/ioconfig.h b/qemu/roms/u-boot/board/sacsng/ioconfig.h
new file mode 100644
index 000000000..ac8f152e1
--- /dev/null
+++ b/qemu/roms/u-boot/board/sacsng/ioconfig.h
@@ -0,0 +1,217 @@
+/*
+ * I/O Port configuration table
+ *
+ * If conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#ifdef SKIP
+#undef SKIP
+#endif
+
+#ifdef CONF
+#undef CONF
+#endif
+
+#ifdef DIN
+#undef DIN
+#endif
+
+#ifdef DOUT
+#undef DOUT
+#endif
+
+#ifdef GPIO
+#undef GPIO
+#endif
+
+#ifdef SPEC
+#undef SPEC
+#endif
+
+#ifdef ACTV
+#undef ACTV
+#endif
+
+#ifdef OPEN
+#undef OPEN
+#endif
+
+#define SKIP 0  /* SKIP over this port */
+#define CONF 1  /* CONFiguration the port */
+
+#define DIN  0  /* PDIRx 0: Direction IN  */
+#define DOUT 1  /* PDIRx 1: Direction OUT */
+
+#define GPIO 0  /* PPARx 0: General Purpose I/O */
+#define SPEC 1  /* PPARx 1: dedicated to a peripheral function, */
+		/*          i.e. the port has a SPECial use. */
+
+#define ACTV 0  /* PODRx 0: ACTiVely driven as an output */
+#define OPEN 1  /* PODRx 1: OPEN-drain driver */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	     conf  ppar  psor  pdir  podr  pdat */
+	/* PA31 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS8*        */
+	/* PA30 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS7*        */
+	/* PA29 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS6*        */
+	/* PA28 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS5*        */
+	/* PA27 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS4*        */
+	/* PA26 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS3*        */
+	/* PA25 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS2*        */
+	/* PA24 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS1*        */
+	/* PA23 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* ODIS_EN*       */
+	/* PA22 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* STLED2_EN*     */
+	/* PA21 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* STLED1_EN*     */
+	/* PA20 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PLED3_EN*      */
+	/* PA19 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PLED2_EN*      */
+	/* PA18 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* PLED1_EN*      */
+	/* PA17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PA16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* DAC_RST*       */
+	/* PA15 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* CH34SDATA_PU   */
+	/* PA14 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* CH12SDATA_PU   */
+	/* PA13 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SLRCLK_EN*     */
+	/* PA12 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4ACDC*    */
+	/* PA11 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4TEDS*    */
+	/* PA10 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4XTDS*    */
+	/* PA9  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3ACDC*    */
+	/* PA8  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3TEDS*    */
+	/* PA7  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3XTDS*    */
+	/* PA6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2ACDC*    */
+	/* PA5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2TEDS*    */
+	/* PA4  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2XTDS*    */
+	/* PA3  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PA2  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_1ACDC*    */
+	/* PA1  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_1TEDS*    */
+	/* PA0  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }  /* MTRX_1XTDS*    */
+    },
+
+    /* Port B configuration */
+    {	/*	     conf  ppar  psor  pdir  podr  pdat */
+	/* PB31 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TX_ER */
+	/* PB30 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RX_DV */
+	/* PB29 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* FCC2 MII_TX_EN */
+	/* PB28 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RX_ER */
+	/* PB27 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_COL   */
+	/* PB26 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_CRS   */
+	/* PB25 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD3  */
+	/* PB24 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD2  */
+	/* PB23 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD1  */
+	/* PB22 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD0  */
+	/* PB21 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD0  */
+	/* PB20 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD1  */
+	/* PB19 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD2  */
+	/* PB18 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD3  */
+	/* PB17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB15 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB14 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RXDC1,   BSDATA_ADC12 */
+	/* PB13 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB12 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RSYNCC1, LRCLK  */
+	/* PB11 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1TXDD1,   RSDATA_DAC12 */
+	/* PB10 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RXDD1,   BSDATA_ADC34 */
+	/* PB9  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB8  */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RSYNCD1, LRCLK  */
+	/* PB7  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* XCITE_SHDN     */
+	/* PB5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* TRIGGER        */
+	/* PB4  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* ARM            */
+	/* PB3  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PB2  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PB1  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PB0  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar  psor  pdir  podr  pdat */
+	/* PC31 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC30 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC29 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK3,  MCLK    */
+	/* PC28 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* TOUT2*         */
+#ifdef QQQ
+	/* PC28 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TOUT2*         */
+#endif
+	/* PC27 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK5,  SCLK    */
+	/* PC26 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC25 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK7,  SCLK    */
+	/* PC24 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC23 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK9,  MCLK    */
+	/* PC22 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC21 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* BRGO6 (LRCLK)  */
+	/* PC20 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC19 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK13, MII_RXCLK  */
+	/* PC18 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK14, MII_TXCLK  */
+	/* PC17 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* BRGO8 (SCLK)   */
+	/* PC16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC15 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* SMC2_TX        */
+	/* PC14 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC13 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC12 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB3      */
+	/* PC11 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC10 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* TDM_STRB4      */
+	/* PC9  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN3      */
+	/* PC8  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN2      */
+	/* PC7  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN1      */
+	/* PC6  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC5  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BTST_IN2*      */
+	/* PC4  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BTST_IN1*      */
+	/* PC3  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* MUSH_STAT      */
+	/* PC2  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* OUTDRV_STAT    */
+	/* PC1  */ { CONF, GPIO,   0,  DOUT, OPEN,   1   }, /* PHY_MDIO       */
+	/* PC0  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PHY_MDC        */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar  psor  pdir  podr  pdat */
+	/* PD31 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* SCC1_RX        */
+	/* PD30 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SCC1_TX        */
+	/* PD29 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD28 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD27 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD26 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD25 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD24 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD23 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD22 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD21 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD20 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SPI_ADC_CS*    */
+	/* PD19 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SPI_DAC_CS*    */
+#if defined(CONFIG_SOFT_SPI)
+	/* PD18 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* SPI_CLK        */
+	/* PD17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* SPI_MOSI       */
+	/* PD16 */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* SPI_MISO       */
+#else
+	/* PD18 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SPI_CLK        */
+	/* PD17 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SPI_MOSI       */
+	/* PD16 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* SPI_MISO       */
+#endif
+#if defined(CONFIG_SYS_I2C_SOFT)
+	/* PD15 */ { CONF, GPIO,   0,  DOUT, OPEN,   1   }, /* I2C_SDA        */
+	/* PD14 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* I2C_SCL        */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ { CONF, SPEC,   1,  DIN,  OPEN,   0   }, /* I2C_SDA        */
+	/* PD14 */ { CONF, SPEC,   1,  DIN,  OPEN,   0   }, /* I2C_SCL        */
+#else /* normal I/O port pins */
+	/* PD15 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* I2C_SDA        */
+	/* PD14 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* I2C_SCL        */
+#endif
+#endif
+	/* PD13 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB1      */
+	/* PD12 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB2      */
+	/* PD11 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD10 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* BRGO4 (MCLK)   */
+	/* PD9  */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* SMC1_TX        */
+	/* PD8  */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* SMC1_RX        */
+	/* PD7  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
+	/* PD6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
+	/* PD5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
+	/* PD4  */ { CONF, SPEC,   1,  DOUT, ACTV,   1   }, /* SMC2_RX        */
+	/* PD3  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PD2  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PD1  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PD0  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }  /* pin doesn't exist */
+    }
+};
diff --git a/qemu/roms/u-boot/board/sacsng/sacsng.c b/qemu/roms/u-boot/board/sacsng/sacsng.c
new file mode 100644
index 000000000..91c4987c9
--- /dev/null
+++ b/qemu/roms/u-boot/board/sacsng/sacsng.c
@@ -0,0 +1,848 @@
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Gerald Van Baren <vanbaren@cideas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/u-boot.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <i2c.h>
+#include <spi.h>
+#include <command.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#include <status_led.h>
+#endif
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+extern void eth_loopback_test(void);
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+#include "clkinit.h"
+#include "ioconfig.h"		/* I/O configuration table */
+
+/*
+ * PBI Page Based Interleaving
+ *   PSDMR_PBI page based interleaving
+ *   0         bank based interleaving
+ * External Address Multiplexing (EAMUX) adds a clock to address cycles
+ *   (this can help with marginal board layouts)
+ *   PSDMR_EAMUX  adds a clock
+ *   0            no extra clock
+ * Buffer Command (BUFCMD) adds a clock to command cycles.
+ *   PSDMR_BUFCMD adds a clock
+ *   0            no extra clock
+ */
+#define CONFIG_PBI		PSDMR_PBI
+#define PESSIMISTIC_SDRAM	0
+#define EAMUX			0	/* EST requires EAMUX */
+#define BUFCMD			0
+
+/*
+ * ADC/DAC Defines:
+ */
+#define INITIAL_SAMPLE_RATE 10016	/* Initial Daq sample rate */
+#define INITIAL_RIGHT_JUST  0	/* Initial DAC right justification */
+#define INITIAL_MCLK_DIVIDE 0	/* Initial MCLK Divide */
+#define INITIAL_SAMPLE_64X  1	/* Initial  64x clocking mode */
+#define INITIAL_SAMPLE_128X 0	/* Initial 128x clocking mode */
+
+/*
+ * ADC Defines:
+ */
+#define I2C_ADC_1_ADDR 0x0E	/* I2C Address of the ADC #1 */
+#define I2C_ADC_2_ADDR 0x0F	/* I2C Address of the ADC #2 */
+
+#define ADC_SDATA1_MASK 0x00020000	/* PA14 - CH12SDATA_PU   */
+#define ADC_SDATA2_MASK 0x00010000	/* PA15 - CH34SDATA_PU   */
+
+#define ADC_VREF_CAP		100	/* VREF capacitor in uF */
+#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP)	/* 10 usec per uF, in usec */
+#define ADC_SDATA_DELAY		100	/* ADC SDATA release delay in usec */
+#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
+					/* Wait at least 4100 LRCLK's */
+
+#define ADC_REG1_FRAME_START    0x80	/* Frame start */
+#define ADC_REG1_GROUND_CAL     0x40	/* Ground calibration enable */
+#define ADC_REG1_ANA_MOD_PDOWN  0x20	/* Analog modulator section in power down */
+#define ADC_REG1_DIG_MOD_PDOWN  0x10	/* Digital modulator section in power down */
+
+#define ADC_REG2_128x           0x80	/* Oversample at 128x */
+#define ADC_REG2_CAL            0x40	/* System calibration enable */
+#define ADC_REG2_CHANGE_SIGN    0x20	/* Change sign enable */
+#define ADC_REG2_LR_DISABLE     0x10	/* Left/Right output disable */
+#define ADC_REG2_HIGH_PASS_DIS  0x08	/* High pass filter disable */
+#define ADC_REG2_SLAVE_MODE     0x04	/* Slave mode */
+#define ADC_REG2_DFS            0x02	/* Digital format select */
+#define ADC_REG2_MUTE           0x01	/* Mute */
+
+#define ADC_REG7_ADDR_ENABLE    0x80	/* Address enable */
+#define ADC_REG7_PEAK_ENABLE    0x40	/* Peak enable */
+#define ADC_REG7_PEAK_UPDATE    0x20	/* Peak update */
+#define ADC_REG7_PEAK_FORMAT    0x10	/* Peak display format */
+#define ADC_REG7_DIG_FILT_PDOWN 0x04	/* Digital filter power down enable */
+#define ADC_REG7_FIR2_IN_EN     0x02	/* External FIR2 input enable */
+#define ADC_REG7_PSYCHO_EN      0x01	/* External pyscho filter input enable */
+
+/*
+ * DAC Defines:
+ */
+
+#define I2C_DAC_ADDR 0x11	/* I2C Address of the DAC */
+
+#define DAC_RST_MASK 0x00008000	/* PA16 - DAC_RST*  */
+#define DAC_RESET_DELAY    100	/* DAC reset delay in usec */
+#define DAC_INITIAL_DELAY 5000	/* DAC initialization delay in usec */
+
+#define DAC_REG1_AMUTE		0x80	/* Auto-mute */
+
+#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4)	/* Fmt 0: Left justified 24 bit  */
+#define DAC_REG1_I2S_24_BIT       (1 << 4)	/* Fmt 1: I2S up to 24 bit       */
+#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4)	/* Fmt 2: Right justified 16 bit */
+#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4)	/* Fmt 3: Right justified 24 bit */
+#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4)	/* Fmt 4: Right justified 20 bit */
+#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4)	/* Fmt 5: Right justified 18 bit */
+
+#define DAC_REG1_DEM_NO           (0 << 2)	/* No      De-emphasis  */
+#define DAC_REG1_DEM_44KHZ        (1 << 2)	/* 44.1KHz De-emphasis  */
+#define DAC_REG1_DEM_48KHZ        (2 << 2)	/* 48KHz   De-emphasis  */
+#define DAC_REG1_DEM_32KHZ        (3 << 2)	/* 32KHz   De-emphasis  */
+
+#define DAC_REG1_SINGLE 0	/*   4- 50KHz sample rate  */
+#define DAC_REG1_DOUBLE 1	/*  50-100KHz sample rate  */
+#define DAC_REG1_QUAD   2	/* 100-200KHz sample rate  */
+#define DAC_REG1_DSD    3	/* Direct Stream Data, DSD */
+
+#define DAC_REG5_INVERT_A   0x80	/* Invert channel A */
+#define DAC_REG5_INVERT_B   0x40	/* Invert channel B */
+#define DAC_REG5_I2C_MODE   0x20	/* Control port (I2C) mode */
+#define DAC_REG5_POWER_DOWN 0x10	/* Power down mode */
+#define DAC_REG5_MUTEC_A_B  0x08	/* Mutec A=B */
+#define DAC_REG5_FREEZE     0x04	/* Freeze */
+#define DAC_REG5_MCLK_DIV   0x02	/* MCLK divide by 2 */
+#define DAC_REG5_RESERVED   0x01	/* Reserved */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+	printf("SACSng\n");
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0;
+	volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
+	uint psdmr = CONFIG_SYS_PSDMR;
+	int i;
+	uint psrt = 14;		/* for no SPD */
+	uint chipselects = 1;	/* for no SPD */
+	uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024;	/* for no SPD */
+	uint or = CONFIG_SYS_OR2_PRELIM;	/* for no SPD */
+
+#ifdef SDRAM_SPD_ADDR
+	uint data_width;
+	uint rows;
+	uint banks;
+	uint cols;
+	uint caslatency;
+	uint width;
+	uint rowst;
+	uint sdam;
+	uint bsma;
+	uint sda10;
+	u_char data;
+	u_char cksum;
+	int j;
+#endif
+
+#ifdef SDRAM_SPD_ADDR
+	/* Keep the compiler from complaining about potentially uninitialized vars */
+	data_width = chipselects = rows = banks = cols = caslatency = psrt =
+		0;
+
+	/*
+	 * Read the SDRAM SPD EEPROM via I2C.
+	 */
+	i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
+	cksum = data;
+	for (j = 1; j < 64; j++) {	/* read only the checksummed bytes */
+		/* note: the I2C address autoincrements when alen == 0 */
+		i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
+		if (j == 5)
+			chipselects = data & 0x0F;
+		else if (j == 6)
+			data_width = data;
+		else if (j == 7)
+			data_width |= data << 8;
+		else if (j == 3)
+			rows = data & 0x0F;
+		else if (j == 4)
+			cols = data & 0x0F;
+		else if (j == 12) {
+			/*
+			 * Refresh rate: this assumes the prescaler is set to
+			 * approximately 1uSec per tick.
+			 */
+			switch (data & 0x7F) {
+			default:
+			case 0:
+				psrt = 14;	/*  15.625uS */
+				break;
+			case 1:
+				psrt = 2;	/*   3.9uS   */
+				break;
+			case 2:
+				psrt = 6;	/*   7.8uS   */
+				break;
+			case 3:
+				psrt = 29;	/*  31.3uS   */
+				break;
+			case 4:
+				psrt = 60;	/*  62.5uS   */
+				break;
+			case 5:
+				psrt = 120;	/* 125uS     */
+				break;
+			}
+		} else if (j == 17)
+			banks = data;
+		else if (j == 18) {
+			caslatency = 3;	/* default CL */
+#if(PESSIMISTIC_SDRAM)
+			if ((data & 0x04) != 0)
+				caslatency = 3;
+			else if ((data & 0x02) != 0)
+				caslatency = 2;
+			else if ((data & 0x01) != 0)
+				caslatency = 1;
+#else
+			if ((data & 0x01) != 0)
+				caslatency = 1;
+			else if ((data & 0x02) != 0)
+				caslatency = 2;
+			else if ((data & 0x04) != 0)
+				caslatency = 3;
+#endif
+			else {
+				printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data);
+			}
+		} else if (j == 63) {
+			if (data != cksum) {
+				printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", data, cksum);
+			}
+		}
+		cksum += data;
+	}
+
+	/* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
+	if (caslatency < 2) {
+		printf("WARNING: CL was %d, forcing to 2\n", caslatency);
+		caslatency = 2;
+	}
+	if (rows > 14) {
+		printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n",
+			rows);
+		rows = 14;
+	}
+	if (cols > 11) {
+		printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n",
+			cols);
+		cols = 11;
+	}
+
+	if ((data_width != 64) && (data_width != 72)) {
+		printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
+			data_width);
+	}
+	width = 3;		/* 2^3 = 8 bytes = 64 bits wide */
+	/*
+	 * Convert banks into log2(banks)
+	 */
+	if (banks == 2)
+		banks = 1;
+	else if (banks == 4)
+		banks = 2;
+	else if (banks == 8)
+		banks = 3;
+
+	sdram_size = 1 << (rows + cols + banks + width);
+
+#if(CONFIG_PBI == 0)		/* bank-based interleaving */
+	rowst = ((32 - 6) - (rows + cols + width)) * 2;
+#else
+	rowst = 32 - (rows + banks + cols + width);
+#endif
+
+	or = ~(sdram_size - 1) |	/* SDAM address mask    */
+		((banks - 1) << 13) |	/* banks per device     */
+		(rowst << 9) |		/* rowst                */
+		((rows - 9) << 6);	/* numr                 */
+
+	memctl->memc_or2 = or;
+
+	/*
+	 * SDAM specifies the number of columns that are multiplexed
+	 * (reference AN2165/D), defined to be (columns - 6) for page
+	 * interleave, (columns - 8) for bank interleave.
+	 *
+	 * BSMA is 14 - max(rows, cols).  The bank select lines come
+	 * into play above the highest "address" line going into the
+	 * the SDRAM.
+	 */
+#if(CONFIG_PBI == 0)		/* bank-based interleaving */
+	sdam = cols - 8;
+	bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+	sda10 = sdam + 2;
+#else
+	sdam = cols - 6;
+	bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+	sda10 = sdam;
+#endif
+#if(PESSIMISTIC_SDRAM)
+	psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK |
+		PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C |
+		PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency |
+		((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */
+		(sdam << 24) | (bsma << 21) | (sda10 << 18);
+#else
+	psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK |
+		PSDMR_PRETOACT_3W |	/* 1 for 7E parts (fast PC-133) */
+		PSDMR_ACTTORW_2W |	/* 1 for 7E parts (fast PC-133) */
+		PSDMR_WRC_1C |	/* 1 clock + 7nSec */
+		EAMUX | BUFCMD) |
+		caslatency | ((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */
+		(sdam << 24) | (bsma << 21) | (sda10 << 18);
+#endif
+#endif
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 * Quote from Micron MT48LC8M16A2 data sheet:
+	 *
+	 *  "...the SDRAM requires a 100uS delay prior to issuing any
+	 *  command other than a COMMAND INHIBIT or NOP.  Starting at some
+	 *  point during this 100uS period and continuing at least through
+	 *  the end of this period, COMMAND INHIBIT or NOP commands should
+	 *  be applied."
+	 *
+	 *  "Once the 100uS delay has been satisfied with at least one COMMAND
+	 *  INHIBIT or NOP command having been applied, a /PRECHARGE command/
+	 *  should be applied.  All banks must then be precharged, thereby
+	 *  placing the device in the all banks idle state."
+	 *
+	 *  "Once in the idle state, /two/ AUTO REFRESH cycles must be
+	 *  performed.  After the AUTO REFRESH cycles are complete, the
+	 *  SDRAM is ready for mode register programming."
+	 *
+	 *  (/emphasis/ mine, gvb)
+	 *
+	 *  The way I interpret this, Micron start up sequence is:
+	 *  1. Issue a PRECHARGE-BANK command (initial precharge)
+	 *  2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
+	 *  3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
+	 *  4. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  --------
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+	 */
+
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = psrt;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+	/*
+	 * Do it a second time for the second set of chips if the DIMM has
+	 * two chip selects (double sided).
+	 */
+	if (chipselects > 1) {
+		ramaddr += sdram_size;
+
+		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
+		memctl->memc_or3 = or;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+		*ramaddr = c;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+		for (i = 0; i < 8; i++)
+			*ramaddr = c;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+		*ramaddr = c;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+		*ramaddr = c;
+	}
+
+	/* return total ram size */
+	return (sdram_size * chipselects);
+}
+
+/*-----------------------------------------------------------------------
+ * Board Control Functions
+ */
+void board_poweroff(void)
+{
+	while (1);		/* hang forever */
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+int misc_init_r(void)
+{
+	/*
+	 * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
+	 */
+	volatile ioport_t *iopa =
+		ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */ );
+	volatile ioport_t *iop =
+		ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
+
+	int reg;		/* I2C register value */
+	char *ep;		/* Environment pointer */
+	char str_buf[12];	/* sprintf output buffer */
+	int sample_rate;	/* ADC/DAC sample rate */
+	int sample_64x;		/* Use  64/4 clocking for the ADC/DAC */
+	int sample_128x;	/* Use 128/4 clocking for the ADC/DAC */
+	int right_just;		/* Is the data to the DAC right justified? */
+	int mclk_divide;	/* MCLK Divide */
+	int quiet;		/* Quiet or minimal output mode */
+
+	quiet = 0;
+
+	if ((ep = getenv("quiet")) != NULL)
+		quiet = simple_strtol(ep, NULL, 10);
+	else
+		setenv("quiet", "0");
+
+	/*
+	 * SACSng custom initialization:
+	 *    Start the ADC and DAC clocks, since the Crystal parts do not
+	 *    work on the I2C bus until the clocks are running.
+	 */
+
+	sample_rate = INITIAL_SAMPLE_RATE;
+	if ((ep = getenv("DaqSampleRate")) != NULL)
+		sample_rate = simple_strtol(ep, NULL, 10);
+
+	sample_64x = INITIAL_SAMPLE_64X;
+	sample_128x = INITIAL_SAMPLE_128X;
+	if ((ep = getenv("Daq64xSampling")) != NULL) {
+		sample_64x = simple_strtol(ep, NULL, 10);
+		if (sample_64x)
+			sample_128x = 0;
+		else
+			sample_128x = 1;
+	} else {
+		if ((ep = getenv("Daq128xSampling")) != NULL) {
+			sample_128x = simple_strtol(ep, NULL, 10);
+			if (sample_128x)
+				sample_64x = 0;
+			else
+				sample_64x = 1;
+		}
+	}
+
+	/*
+	 * Stop the clocks and wait for at least 1 LRCLK period
+	 * to make sure the clocking has really stopped.
+	 */
+	Daq_Stop_Clocks();
+	udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
+
+	/*
+	 * Initialize the clocks with the new rates
+	 */
+	Daq_Init_Clocks(sample_rate, sample_64x);
+	sample_rate = Daq_Get_SampleRate();
+
+	/*
+	 * Start the clocks and wait for at least 1 LRCLK period
+	 * to make sure the clocking has become stable.
+	 */
+	Daq_Start_Clocks(sample_rate);
+	udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
+
+	sprintf(str_buf, "%d", sample_rate);
+	setenv("DaqSampleRate", str_buf);
+
+	if (sample_64x) {
+		setenv("Daq64xSampling", "1");
+		setenv("Daq128xSampling", NULL);
+	} else {
+		setenv("Daq64xSampling", NULL);
+		setenv("Daq128xSampling", "1");
+	}
+
+	/*
+	 * Display the ADC/DAC clocking information
+	 */
+	if (!quiet)
+		Daq_Display_Clocks();
+
+	/*
+	 * Determine the DAC data justification
+	 */
+
+	right_just = INITIAL_RIGHT_JUST;
+	if ((ep = getenv("DaqDACRightJustified")) != NULL)
+		right_just = simple_strtol(ep, NULL, 10);
+
+	sprintf(str_buf, "%d", right_just);
+	setenv("DaqDACRightJustified", str_buf);
+
+	/*
+	 * Determine the DAC MCLK Divide
+	 */
+
+	mclk_divide = INITIAL_MCLK_DIVIDE;
+	if ((ep = getenv("DaqDACMClockDivide")) != NULL)
+		mclk_divide = simple_strtol(ep, NULL, 10);
+
+	sprintf(str_buf, "%d", mclk_divide);
+	setenv("DaqDACMClockDivide", str_buf);
+
+	/*
+	 * Initializing the I2C address in the Crystal A/Ds:
+	 *
+	 * 1) Wait for VREF cap to settle (10uSec per uF)
+	 * 2) Release pullup on SDATA
+	 * 3) Write the I2C address to register 6
+	 * 4) Enable address matching by setting the MSB in register 7
+	 */
+
+	if (!quiet)
+		printf("Initializing the ADC...\n");
+
+	udelay(ADC_INITIAL_DELAY);	/* 10uSec per uF of VREF cap */
+
+	iopa->pdat &= ~ADC_SDATA1_MASK;	/* release SDATA1 */
+	udelay(ADC_SDATA_DELAY);	/* arbitrary settling time */
+
+	i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR);	/* set address */
+	i2c_reg_write(I2C_ADC_1_ADDR, 0x07,	/* turn on ADDREN */
+		      ADC_REG7_ADDR_ENABLE);
+
+	i2c_reg_write(I2C_ADC_1_ADDR, 0x02,	/* 128x, slave mode, !HPEN */
+		      (sample_64x ? 0 : ADC_REG2_128x) |
+		      ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
+
+	reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
+	if (reg != I2C_ADC_1_ADDR) {
+		printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
+			reg, I2C_ADC_1_ADDR);
+	}
+
+	iopa->pdat &= ~ADC_SDATA2_MASK;	/* release SDATA2 */
+	udelay(ADC_SDATA_DELAY);	/* arbitrary settling time */
+
+	/* set address (do not set ADDREN yet) */
+	i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR);
+
+	i2c_reg_write(I2C_ADC_2_ADDR, 0x02,	/* 64x, slave mode, !HPEN */
+		      (sample_64x ? 0 : ADC_REG2_128x) |
+		      ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
+
+	reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
+	if (reg != I2C_ADC_2_ADDR) {
+		printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
+			reg, I2C_ADC_2_ADDR);
+	}
+
+	i2c_reg_write(I2C_ADC_1_ADDR, 0x01,	/* set FSTART and GNDCAL */
+		      ADC_REG1_FRAME_START | ADC_REG1_GROUND_CAL);
+
+	i2c_reg_write(I2C_ADC_1_ADDR, 0x02,	/* Start calibration */
+		      (sample_64x ? 0 : ADC_REG2_128x) |
+		      ADC_REG2_CAL |
+		      ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
+
+	udelay(ADC_CAL_DELAY);	/* a minimum of 4100 LRCLKs */
+	i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00);	/* remove GNDCAL */
+
+	/*
+	 * Now that we have synchronized the ADC's, enable address
+	 * selection on the second ADC as well as the first.
+	 */
+	i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
+
+	/*
+	 * Initialize the Crystal DAC
+	 *
+	 * Two of the config lines are used for I2C so we have to set them
+	 * to the proper initialization state without inadvertantly
+	 * sending an I2C "start" sequence.  When we bring the I2C back to
+	 * the normal state, we send an I2C "stop" sequence.
+	 */
+	if (!quiet)
+		printf("Initializing the DAC...\n");
+
+	/*
+	 * Bring the I2C clock and data lines low for initialization
+	 */
+	I2C_SCL(0);
+	I2C_DELAY;
+	I2C_SDA(0);
+	I2C_ACTIVE;
+	I2C_DELAY;
+
+	/* Reset the DAC */
+	iopa->pdat &= ~DAC_RST_MASK;
+	udelay(DAC_RESET_DELAY);
+
+	/* Release the DAC reset */
+	iopa->pdat |= DAC_RST_MASK;
+	udelay(DAC_INITIAL_DELAY);
+
+	/*
+	 * Cause the DAC to:
+	 *     Enable control port (I2C mode)
+	 *     Going into power down
+	 */
+	i2c_reg_write(I2C_DAC_ADDR, 0x05,
+		      DAC_REG5_I2C_MODE | DAC_REG5_POWER_DOWN);
+
+	/*
+	 * Cause the DAC to:
+	 *     Enable control port (I2C mode)
+	 *     Going into power down
+	 *         . MCLK divide by 1
+	 *         . MCLK divide by 2
+	 */
+	i2c_reg_write(I2C_DAC_ADDR, 0x05,
+		      DAC_REG5_I2C_MODE |
+		      DAC_REG5_POWER_DOWN |
+		      (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
+
+	/*
+	 * Cause the DAC to:
+	 *     Auto-mute disabled
+	 *         . Format 0, left  justified 24 bits
+	 *         . Format 3, right justified 24 bits
+	 *     No de-emphasis
+	 *         . Single speed mode
+	 *         . Double speed mode
+	 */
+	i2c_reg_write(I2C_DAC_ADDR, 0x01,
+		      (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
+		       DAC_REG1_LEFT_JUST_24_BIT) |
+		      DAC_REG1_DEM_NO |
+		      (sample_rate >=
+		       50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
+
+	sprintf(str_buf, "%d",
+		sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
+	setenv("DaqDACFunctionalMode", str_buf);
+
+	/*
+	 * Cause the DAC to:
+	 *     Enable control port (I2C mode)
+	 *     Remove power down
+	 *         . MCLK divide by 1
+	 *         . MCLK divide by 2
+	 */
+	i2c_reg_write(I2C_DAC_ADDR, 0x05,
+		      DAC_REG5_I2C_MODE |
+		      (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
+
+	/*
+	 * Create a I2C stop condition:
+	 *     low->high on data while clock is high.
+	 */
+	I2C_SCL(1);
+	I2C_DELAY;
+	I2C_SDA(1);
+	I2C_DELAY;
+	I2C_TRISTATE;
+
+	if (!quiet)
+		printf("\n");
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+	/*
+	 * Run the Ethernet loopback test
+	 */
+	eth_loopback_test();
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+	/*
+	 * Turn off the RED fail LED now that we are up and running.
+	 */
+	status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+/*
+ * Show boot status: flash the LED if something goes wrong, indicating
+ * that last thing that worked and thus, by implication, what is broken.
+ *
+ * This stores the last OK value in RAM so this will not work properly
+ * before RAM is initialized.  Since it is being used for indicating
+ * boot status (i.e. after RAM is initialized), that is OK.
+ */
+static void flash_code(uchar number, uchar modulo, uchar digits)
+{
+	int j;
+
+	/*
+	 * Recursively do upper digits.
+	 */
+	if (digits > 1)
+		flash_code(number / modulo, modulo, digits - 1);
+
+	number = number % modulo;
+
+	/*
+	 * Zero is indicated by one long flash (dash).
+	 */
+	if (number == 0) {
+		status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+		udelay(1000000);
+		status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+		udelay(200000);
+	} else {
+		/*
+		 * Non-zero is indicated by short flashes, one per count.
+		 */
+		for (j = 0; j < number; j++) {
+			status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+			udelay(100000);
+			status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+			udelay(200000);
+		}
+	}
+	/*
+	 * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
+	 */
+	udelay(700000);
+}
+
+static int last_boot_progress;
+
+void show_boot_progress(int status)
+{
+	int i, j;
+
+	if (status > 0) {
+		last_boot_progress = status;
+	} else {
+		/*
+		 * If a specific failure code is given, flash this code
+		 * else just use the last success code we've seen
+		 */
+		if (status < -1)
+			last_boot_progress = -status;
+
+		/*
+		 * Flash this code 5 times
+		 */
+		for (j = 0; j < 5; j++) {
+			/*
+			 * Houston, we have a problem.
+			 * Blink the last OK status which indicates where things failed.
+			 */
+			status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+			flash_code(last_boot_progress, 5, 3);
+
+			/*
+			 * Delay 5 seconds between repetitions,
+			 * with the fault LED blinking
+			 */
+			for (i = 0; i < 5; i++) {
+				status_led_set(STATUS_LED_RED,
+					       STATUS_LED_OFF);
+				udelay(500000);
+				status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+				udelay(500000);
+			}
+		}
+
+		/*
+		 * Reset the board to retry initialization.
+		 */
+		do_reset(NULL, 0, 0, NULL);
+	}
+}
+#endif /* CONFIG_SHOW_BOOT_PROGRESS */
+
+
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#if defined(CONFIG_CMD_SPI)
+
+#define SPI_ADC_CS_MASK	0x00000800
+#define SPI_DAC_CS_MASK	0x00001000
+
+static const u32 cs_mask[] = {
+	SPI_ADC_CS_MASK,
+	SPI_DAC_CS_MASK,
+};
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	volatile ioport_t *iopd =
+		ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
+
+	iopd->pdat &= ~cs_mask[slave->cs];
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	volatile ioport_t *iopd =
+		ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
+
+	iopd->pdat |= cs_mask[slave->cs];
+}
+
+#endif
+
+#endif /* CONFIG_MISC_INIT_R */