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authorRajithaY <rajithax.yerrumsetty@intel.com>2017-04-25 03:31:15 -0700
committerRajitha Yerrumchetty <rajithax.yerrumsetty@intel.com>2017-05-22 06:48:08 +0000
commitbb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch)
treeca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/u-boot/board/renesas/r2dplus/r2dplus.c
parenta14b48d18a9ed03ec191cf16b162206998a895ce (diff)
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to kvmfornfv repo and make use of the updated latest qemu for the execution of all testcase Change-Id: I1280af507a857675c7f81d30c95255635667bdd7 Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/board/renesas/r2dplus/r2dplus.c')
-rw-r--r--qemu/roms/u-boot/board/renesas/r2dplus/r2dplus.c68
1 files changed, 0 insertions, 68 deletions
diff --git a/qemu/roms/u-boot/board/renesas/r2dplus/r2dplus.c b/qemu/roms/u-boot/board/renesas/r2dplus/r2dplus.c
deleted file mode 100644
index 249c35f3a..000000000
--- a/qemu/roms/u-boot/board/renesas/r2dplus/r2dplus.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2007,2008
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ide.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- puts("BOARD: Renesas Solutions R2D Plus\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
-int board_late_init(void)
-{
- return 0;
-}
-
-#define FPGA_BASE 0xA4000000
-#define FPGA_CFCTL (FPGA_BASE + 0x04)
-#define CFCTL_EN (0x432)
-#define FPGA_CFPOW (FPGA_BASE + 0x06)
-#define CFPOW_ON (0x02)
-#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
-#define CFCDINTCLR_EN (0x01)
-
-void ide_set_reset(int idereset)
-{
- /* if reset = 1 IDE reset will be asserted */
- if (idereset) {
- outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */
- outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
- outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
- }
-}
-
-static struct pci_controller hose;
-void pci_init_board(void)
-{
- pci_sh7751_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}