Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

3 files changed, 134 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/quad100hd/Makefile b/qemu/roms/u-boot/board/quad100hd/Makefile
new file mode 100644
index 000000000..b65e5ad47
--- /dev/null
+++ b/qemu/roms/u-boot/board/quad100hd/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= quad100hd.o nand.o
diff --git a/qemu/roms/u-boot/board/quad100hd/nand.c b/qemu/roms/u-boot/board/quad100hd/nand.c
new file mode 100644
index 000000000..47bbb6b26
--- /dev/null
+++ b/qemu/roms/u-boot/board/quad100hd/nand.c
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#if defined(CONFIG_CMD_NAND)
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
+#include <nand.h>
+
+/*
+ *	hardware specific access to control-lines
+ */
+static void quad100hd_hwcontrol(struct mtd_info *mtd,
+				int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		gpio_write_bit(CONFIG_SYS_NAND_CLE, !!(ctrl & NAND_CLE));
+		gpio_write_bit(CONFIG_SYS_NAND_ALE, !!(ctrl & NAND_ALE));
+		gpio_write_bit(CONFIG_SYS_NAND_CE, !(ctrl & NAND_NCE));
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static int quad100hd_nand_ready(struct mtd_info *mtd)
+{
+	return gpio_read_in_bit(CONFIG_SYS_NAND_RDY);
+}
+
+/*
+ * Main initialization routine
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+	/* Set address of hardware control function */
+	nand->cmd_ctrl = quad100hd_hwcontrol;
+	nand->dev_ready = quad100hd_nand_ready;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	/* 15 us command delay time */
+	nand->chip_delay =  20;
+
+	/* Return happy */
+	return 0;
+}
+#endif /* CONFIG_CMD_NAND */
diff --git a/qemu/roms/u-boot/board/quad100hd/quad100hd.c b/qemu/roms/u-boot/board/quad100hd/quad100hd.c
new file mode 100644
index 000000000..bb14ca705
--- /dev/null
+++ b/qemu/roms/u-boot/board/quad100hd/quad100hd.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * Based in part on board/icecube/icecube.c from PPCBoot
+ * (C) Copyright 2003 Intrinsyc Software
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <environment.h>
+#include <logbuff.h>
+#include <post.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* taken from PPCBoot */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);
+	mtdcr(UIC0PR, 0xFFFF7FFE);	/* set int polarities */
+	mtdcr(UIC0TR, 0x00000000);	/* set int trigger levels */
+	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
+
+	mtdcr(CPC0_SRR, 0x00040000);   /* Hold PCI bridge in reset */
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char buf[64];
+	int i = getenv_f("serial#", buf, sizeof(buf));
+#ifdef DISPLAY_BOARD_INFO
+	sys_info_t sysinfo;
+#endif
+
+	puts("Board: Quad100hd");
+
+	if (i > 0) {
+		puts(", serial# ");
+		puts(buf);
+	}
+	putc('\n');
+
+#ifdef DISPLAY_BOARD_INFO
+	/* taken from ppcboot */
+	get_sys_info(&sysinfo);
+
+	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz);
+	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+	printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv *
+		1000000));
+	printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
+#endif
+
+	return 0;
+}