Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

5 files changed, 1032 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/ppmc7xx/Makefile b/qemu/roms/u-boot/board/ppmc7xx/Makefile
new file mode 100644
index 000000000..f8957f352
--- /dev/null
+++ b/qemu/roms/u-boot/board/ppmc7xx/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= init.o
+obj-y	+= ppmc7xx.o pci.o flash.o
diff --git a/qemu/roms/u-boot/board/ppmc7xx/flash.c b/qemu/roms/u-boot/board/ppmc7xx/flash.c
new file mode 100644
index 000000000..e7242271d
--- /dev/null
+++ b/qemu/roms/u-boot/board/ppmc7xx/flash.c
@@ -0,0 +1,494 @@
+/*
+ * flash.c
+ * -------
+ *
+ * Flash programming routines for the Wind River PPMC 74xx/7xx
+ * based on flash.c from the TQM8260 board.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <74xx_7xx.h>
+
+#define DWORD unsigned long long
+
+/* Local function prototypes */
+static int	write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
+static void	write_via_fpu (volatile DWORD* addr, DWORD* data);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset (void)
+{
+	unsigned long msr;
+	DWORD cmd_reset = 0x00F000F000F000F0LL;
+
+	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
+		msr = get_msr ();
+		set_msr (msr | MSR_FP);
+
+		write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
+
+		set_msr (msr);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+	int i;
+	unsigned long msr;
+	DWORD flashtest;
+	DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+							0x0090009000900090LL };
+
+	/* Enable FPU */
+	msr = get_msr ();
+	set_msr (msr | MSR_FP);
+
+	/* Write auto-select command sequence */
+	write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
+	write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
+	write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
+
+	/* Restore FPU */
+	set_msr (msr);
+
+	/* Read manufacturer ID */
+	flashtest = *(volatile DWORD*)baseaddr;
+	switch ((int)flashtest) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		/* No, faulty or unknown flash */
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);
+	}
+
+	/* Read device ID */
+	flashtest = *(volatile DWORD*)(baseaddr + 8);
+	switch ((long)flashtest) {
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00400000;
+		break;
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;
+		break;
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00800000;
+		break;
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00800000;
+		break;
+	case AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;
+	case AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;
+	case AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;
+	case AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;
+	case AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;
+	default:
+		/* Unknown flash type */
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);
+	}
+
+	if ((long)flashtest == AMD_ID_LV640U) {
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set up sector start adress table (bottom sector type) */
+		info->start[0] = baseaddr + 0x00000000;
+		info->start[1] = baseaddr + 0x00010000;
+		info->start[2] = baseaddr + 0x00018000;
+		info->start[3] = baseaddr + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
+		}
+	} else {
+		/* set up sector start adress table (top sector type) */
+		i = info->sector_count - 1;
+		info->start[i--] = baseaddr + info->size - 0x00010000;
+		info->start[i--] = baseaddr + info->size - 0x00018000;
+		info->start[i--] = baseaddr + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = baseaddr + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) {
+			info->protect[i] = 1;	/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+
+	flash_reset ();
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+	size_b0 = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		printf ("29LV800T (8 M, top sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("29LV800T (8 M, bottom sector)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("29LV160T (16 M, top sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("29LV160B (16 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:
+		printf ("29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:
+		printf ("29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:
+		printf ("29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:
+		printf ("29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AM640U:
+		printf ("29LV640D (64 M, uniform sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned long msr;
+	DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+						   0x0080008000800080LL, 0x00AA00AA00AA00AALL,
+						   0x0055005500550055LL, 0x0030003000300030LL };
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Enable FPU */
+	msr = get_msr();
+	set_msr ( msr | MSR_FP );
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] );
+	udelay (1000);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] );
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* Restore FPU */
+	set_msr (msr);
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
+				!= 0x0080008000800080LL )
+	{
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	flash_reset ();
+
+	printf (" done\n");
+	return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong dp;
+	static unsigned char bb[8];
+	int i, l, rc, cc = cnt;
+
+	dp = (addr & ~7);		/* get lower dword aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - dp) != 0) {
+		for (i = 0; i < 8; i++)
+			bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++;
+		if ((rc = write_dword (info, dp, bb)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		cc -= 8 - l;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cc >= 8) {
+		if ((rc = write_dword (info, dp, src)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		src += 8;
+		cc -= 8;
+	}
+
+	if (cc <= 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	for (i = 0; i < 8; i++) {
+		bb[i] = (i < cc) ? *src++ : *(char*)(dp + i);
+	}
+	return (write_dword (info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
+{
+	ulong start;
+	unsigned long msr;
+	int flag, i;
+	DWORD data;
+	DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+						   0x00A000A000A000A0LL };
+
+	for (data = 0, i = 0; i < 8; i++)
+		data = (data << 8) + *pdata++;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*(DWORD*)dest & data) != data) {
+		return (2);
+	}
+
+	/* Enable FPU */
+	msr = get_msr();
+	set_msr( msr | MSR_FP );
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] );
+	write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] );
+	write_via_fpu ((DWORD*)dest, &data );
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* Restore FPU */
+	set_msr(msr);
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while (*(volatile DWORD*)dest != data ) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_via_fpu (volatile DWORD* addr, DWORD* data)
+{
+	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
+	__asm__ __volatile__ ("eieio");
+}
diff --git a/qemu/roms/u-boot/board/ppmc7xx/init.S b/qemu/roms/u-boot/board/ppmc7xx/init.S
new file mode 100644
index 000000000..99a818ad0
--- /dev/null
+++ b/qemu/roms/u-boot/board/ppmc7xx/init.S
@@ -0,0 +1,336 @@
+/*
+ * init.S
+ * ------
+ *
+ * Wind River PPMC 7xx/74xx init code.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ *
+ * NOTE: The following code was generated automatically by Workbench
+ *       from the ppmc7400_107.reg register file.
+ */
+
+#include <ppc_asm.tmpl>
+
+
+.globl board_asm_init
+board_asm_init:
+
+      lis    r4,0xFEC0
+      ori    r4,r4,0x0000
+      lis    r5,0xFEE0
+      ori    r5,r5,0x0000
+      lis    r3,0x8000          # ADDR_00
+      ori    r3,r3,0x0000
+      stwbrx    r3,0,r4
+      li     r3,0x1057          # VENDOR
+      li    r8, 0x0
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_02
+      ori    r3,r3,0x0002
+      stwbrx    r3,0,r4
+      li     r3,0x0004          # ID
+      li    r8, 0x2
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_04
+      ori    r3,r3,0x0004
+      stwbrx    r3,0,r4
+      li     r3,0x0006          # PCICMD
+      li    r8, 0x0
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_06
+      ori    r3,r3,0x0006
+      stwbrx    r3,0,r4
+      li     r3,0x00A0          # PCISTAT
+      li    r8, 0x2
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_08
+      ori    r3,r3,0x0008
+      stwbrx    r3,0,r4
+      li     r3,0x10            # REVID
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_09
+      ori    r3,r3,0x0009
+      stwbrx    r3,0,r4
+      li     r3,0x00            # PROGIR
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_0A
+      ori    r3,r3,0x000A
+      stwbrx    r3,0,r4
+      li     r3,0x00            # SUBCCODE
+      stb    r3,0x2(r5)
+      lis    r3,0x8000          # ADDR_0B
+      ori    r3,r3,0x000B
+      stwbrx    r3,0,r4
+      li     r3,0x06            # PBCCR
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_0C
+      ori    r3,r3,0x000C
+      stwbrx    r3,0,r4
+      li     r3,0x08            # PCLSR
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_0D
+      ori    r3,r3,0x000D
+      stwbrx    r3,0,r4
+      li     r3,0x00            # PLTR
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_0E
+      ori    r3,r3,0x000E
+      stwbrx    r3,0,r4
+      li     r3,0x00            # HEADTYPE
+      stb    r3,0x2(r5)
+      lis    r3,0x8000          # ADDR_0F
+      ori    r3,r3,0x000F
+      stwbrx    r3,0,r4
+      li     r3,0x00            # BISTCTRL
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_10
+      ori    r3,r3,0x0010
+      stwbrx    r3,0,r4
+      lis    r3,0x0000          # LMBAR
+      ori    r3,r3,0x0008
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_14
+      ori    r3,r3,0x0014
+      stwbrx    r3,0,r4
+      lis    r3,0xF000          # PCSRBAR
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_3C
+      ori    r3,r3,0x003C
+      stwbrx    r3,0,r4
+      li     r3,0x00            # ILR
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_3D
+      ori    r3,r3,0x003D
+      stwbrx    r3,0,r4
+      li     r3,0x01            # INTPIN
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_3E
+      ori    r3,r3,0x003E
+      stwbrx    r3,0,r4
+      li     r3,0x00            # MIN_GNT
+      stb    r3,0x2(r5)
+      lis    r3,0x8000          # ADDR_3F
+      ori    r3,r3,0x003F
+      stwbrx    r3,0,r4
+      li     r3,0x00            # MAX_LAT
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_40
+      ori    r3,r3,0x0040
+      stwbrx    r3,0,r4
+      li     r3,0x00            # BUSNB
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_41
+      ori    r3,r3,0x0041
+      stwbrx    r3,0,r4
+      li     r3,0x00            # SBUSNB
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_46
+      ori    r3,r3,0x0046
+      stwbrx    r3,0,r4
+#      li     r3,0xE080          # PCIARB
+      li     r3,-0x1F80          # PCIARB
+      li    r8, 0x2
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_70
+      ori    r3,r3,0x0070
+      stwbrx    r3,0,r4
+      li     r3,0x0000          # PMCR1
+      li    r8, 0x0
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_72
+      ori    r3,r3,0x0072
+      stwbrx    r3,0,r4
+      li     r3,0xC0            # PMCR2
+      stb    r3,0x2(r5)
+      lis    r3,0x8000          # ADDR_73
+      ori    r3,r3,0x0073
+      stwbrx    r3,0,r4
+      li     r3,0xEF            # ODCR
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_74
+      ori    r3,r3,0x0074
+      stwbrx    r3,0,r4
+      li     r3,0x7D00          # CLKDCR
+      li    r8, 0x0
+      sthbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_76
+      ori    r3,r3,0x0076
+      stwbrx    r3,0,r4
+      li     r3,0x00            # MDCR
+      stb    r3,0x2(r5)
+      lis    r6,0xFCE0
+      ori    r6,r6,0x0000       # r6 is the EUMBAR Base Address
+      lis    r3,0x8000          # ADDR_78
+      ori    r3,r3,0x0078
+      stwbrx    r3,0,r4
+      lis    r3,0xFCE0          # EUMBBAR
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_80
+      ori    r3,r3,0x0080
+      stwbrx    r3,0,r4
+      lis    r3,0xFFFF          # MSADDR1
+      ori    r3,r3,0x4000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_84
+      ori    r3,r3,0x0084
+      stwbrx    r3,0,r4
+      lis    r3,0xFFFF          # MSADDR2
+      ori    r3,r3,0xFFFF
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_88
+      ori    r3,r3,0x0088
+      stwbrx    r3,0,r4
+      lis    r3,0x0303          # EMSADDR1
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_8C
+      ori    r3,r3,0x008C
+      stwbrx    r3,0,r4
+      lis    r3,0x0303          # EMSADDR2
+      ori    r3,r3,0x0303
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_90
+      ori    r3,r3,0x0090
+      stwbrx    r3,0,r4
+      lis    r3,0xFFFF          # EMEADDR1
+      ori    r3,r3,0x7F3F
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_94
+      ori    r3,r3,0x0094
+      stwbrx    r3,0,r4
+      lis    r3,0xFFFF          # EMEADDR2
+      ori    r3,r3,0xFFFF
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_98
+      ori    r3,r3,0x0098
+      stwbrx    r3,0,r4
+      lis    r3,0x0303          # EXTEMEM1
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_9C
+      ori    r3,r3,0x009C
+      stwbrx    r3,0,r4
+      lis    r3,0x0303          # EXTEMEM2
+      ori    r3,r3,0x0303
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_A0
+      ori    r3,r3,0x00A0
+      stwbrx    r3,0,r4
+      li     r3,0x03            # MEMBNKEN
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_A3
+      ori    r3,r3,0x00A3
+      stwbrx    r3,0,r4
+      li     r3,0x00            # MEMPMODE
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_B8
+      ori    r3,r3,0x00B8
+      stwbrx    r3,0,r4
+      li     r3,0x00            # ECCCNT
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_B9
+      ori    r3,r3,0x00B9
+      stwbrx    r3,0,r4
+      li     r3,0x00            # ECCTRG
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_C0
+      ori    r3,r3,0x00C0
+      stwbrx    r3,0,r4
+      li     r3,0xFF            # ERRENR1
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_C1
+      ori    r3,r3,0x00C1
+      stwbrx    r3,0,r4
+      li     r3,0x00            # ERRDR1
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_C3
+      ori    r3,r3,0x00C3
+      stwbrx    r3,0,r4
+      li     r3,0x50            # IPBESR
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_C4
+      ori    r3,r3,0x00C4
+      stwbrx    r3,0,r4
+      li     r3,0xBF            # ERRENR2
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_C5
+      ori    r3,r3,0x00C5
+      stwbrx    r3,0,r4
+      li     r3,0x00            # ERRDR2
+      stb    r3,0x1(r5)
+      lis    r3,0x8000          # ADDR_C7
+      ori    r3,r3,0x00C7
+      stwbrx    r3,0,r4
+      li     r3,0x00            # PCIBESR
+      stb    r3,0x3(r5)
+      lis    r3,0x8000          # ADDR_C8
+      ori    r3,r3,0x00C8
+      stwbrx    r3,0,r4
+      lis    r3,0x0000          # BERRADDR
+      ori    r3,r3,0xE0FE
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_E0
+      ori    r3,r3,0x00E0
+      stwbrx    r3,0,r4
+      li     r3,0xC0            # AMBOR
+      stb    r3,0x0(r5)
+      lis    r3,0x8000          # ADDR_F4
+      ori    r3,r3,0x00F4
+      stwbrx    r3,0,r4
+      lis    r3,0x0000          # MCCR2
+      ori    r3,r3,0x020C
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_F8
+      ori    r3,r3,0x00F8
+      stwbrx    r3,0,r4
+      lis    r3,0x0230          # MCCR3
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_FC
+      ori    r3,r3,0x00FC
+      stwbrx    r3,0,r4
+      lis    r3,0x2532          # MCCR4
+      ori    r3,r3,0x2220
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_F0
+      ori    r3,r3,0x00F0
+      stwbrx    r3,0,r4
+      lis    r3,0xFFC8          # MCCR1
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_A8
+      ori    r3,r3,0x00A8
+      stwbrx    r3,0,r4
+      lis    r3,0xFF14          # PICR1
+      ori    r3,r3,0x1CC8
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+      lis    r3,0x8000          # ADDR_AC
+      ori    r3,r3,0x00AC
+      stwbrx    r3,0,r4
+      lis    r3,0x0000          # PICR2
+      ori    r3,r3,0x0000
+      li    r8, 0x0
+      stwbrx    r3,r8,r5
+
+      blr
diff --git a/qemu/roms/u-boot/board/ppmc7xx/pci.c b/qemu/roms/u-boot/board/ppmc7xx/pci.c
new file mode 100644
index 000000000..d81a41aad
--- /dev/null
+++ b/qemu/roms/u-boot/board/ppmc7xx/pci.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * PCI initialisation for the MPC10x.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc106.h>
+
+#ifdef CONFIG_PCI
+
+struct pci_controller local_hose;
+
+void pci_init_board(void)
+{
+    struct pci_controller* hose = (struct pci_controller *)&local_hose;
+    u16 reg16;
+
+    hose->first_busno = 0;
+    hose->last_busno = 0xff;
+
+    pci_set_region(hose->regions + 0,
+	CONFIG_SYS_PCI_MEMORY_BUS,
+	CONFIG_SYS_PCI_MEMORY_PHYS,
+	CONFIG_SYS_PCI_MEMORY_SIZE,
+	PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+    /* PCI memory space */
+    pci_set_region(hose->regions + 1,
+	CONFIG_SYS_PCI_MEM_BUS,
+	CONFIG_SYS_PCI_MEM_PHYS,
+	CONFIG_SYS_PCI_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* ISA/PCI memory space */
+    pci_set_region(hose->regions + 2,
+	CONFIG_SYS_ISA_MEM_BUS,
+	CONFIG_SYS_ISA_MEM_PHYS,
+	CONFIG_SYS_ISA_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* PCI I/O space */
+    pci_set_region(hose->regions + 3,
+	CONFIG_SYS_PCI_IO_BUS,
+	CONFIG_SYS_PCI_IO_PHYS,
+	CONFIG_SYS_PCI_IO_SIZE,
+	PCI_REGION_IO);
+
+    /* ISA/PCI I/O space */
+    pci_set_region(hose->regions + 4,
+	CONFIG_SYS_ISA_IO_BUS,
+	CONFIG_SYS_ISA_IO_PHYS,
+	CONFIG_SYS_ISA_IO_SIZE,
+	PCI_REGION_IO);
+
+    hose->region_count = 5;
+
+    pci_setup_indirect(hose,
+	MPC106_REG_ADDR,
+	MPC106_REG_DATA);
+
+    pci_register_hose(hose);
+
+    hose->last_busno = pci_hose_scan(hose);
+
+    /* Initialises the MPC10x PCI Configuration regs. */
+    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+    /* Clear non-reserved bits in status register */
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+}
+
+#endif /* CONFIG_PCI */
diff --git a/qemu/roms/u-boot/board/ppmc7xx/ppmc7xx.c b/qemu/roms/u-boot/board/ppmc7xx/ppmc7xx.c
new file mode 100644
index 000000000..432d366a4
--- /dev/null
+++ b/qemu/roms/u-boot/board/ppmc7xx/ppmc7xx.c
@@ -0,0 +1,112 @@
+/*
+ * ppmc7xx.c
+ * ---------
+ *
+ * Main board-specific routines for Wind River PPMC 7xx/74xx board.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+
+
+/* Define some MPC107 (memory controller) registers */
+#define MPC107_EUMB_GCR         0xfce41020
+#define MPC107_EUMB_IACKR       0xfce600a0
+
+
+/* Function prototypes */
+extern void _start(void);
+
+
+/*
+ * initdram()
+ *
+ * This function normally initialises the (S)DRAM of the system. For this board
+ * the SDRAM was already initialised by board_asm_init (see init.S) so we just
+ * return the size of RAM.
+ */
+phys_size_t initdram( int board_type )
+{
+    return CONFIG_SYS_SDRAM_SIZE;
+}
+
+
+/*
+ * after_reloc()
+ *
+ * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
+ * us an opportunity to do some additional setup before the rest of the system
+ * is initialised. We don't need to do anything, so we just call board_init_r()
+ * which should never return.
+ */
+void after_reloc( ulong dest_addr, gd_t* gd )
+{
+	/* Jump to the main U-Boot board init code */
+	board_init_r( gd, dest_addr );
+}
+
+
+/*
+ * checkboard()
+ *
+ * We could do some board level checks here, such as working out what version
+ * it is, but for this board we simply display it's name (on the console).
+ */
+int checkboard( void )
+{
+    puts( "Board: Wind River PPMC 7xx/74xx\n" );
+    return 0;
+}
+
+
+/*
+ * misc_init_r
+ *
+ * Used for other setup which needs to be done late in the bring-up phase.
+ */
+int misc_init_r( void )
+{
+	/* Reset the EPIC and clear pending interrupts */
+	out32r(MPC107_EUMB_GCR, 0xa0000000);
+	while( in32r( MPC107_EUMB_GCR ) & 0x80000000 );
+	out32r( MPC107_EUMB_GCR, 0x20000000 );
+	while( in32r( MPC107_EUMB_IACKR ) != 0xff );
+
+	/* Enable the I-Cache */
+	icache_enable();
+
+	return 0;
+}
+
+
+/*
+ * do_reset()
+ *
+ * Shell command to reset the board.
+ */
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	printf( "Resetting...\n" );
+
+	/* Disabe and invalidate cache */
+	icache_disable();
+	dcache_disable();
+
+	/* Jump to cold reset point (in RAM) */
+	_start();
+
+	/* Should never get here */
+	while(1)
+		;
+
+	return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}