diff options
| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/board/nvidia | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/board/nvidia')
27 files changed, 2231 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/nvidia/beaver/Makefile b/qemu/roms/u-boot/board/nvidia/beaver/Makefile new file mode 100644 index 000000000..1f7c31d64 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/beaver/Makefile @@ -0,0 +1,17 @@ +# +# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +obj-y = ../cardhu/cardhu.o diff --git a/qemu/roms/u-boot/board/nvidia/cardhu/Makefile b/qemu/roms/u-boot/board/nvidia/cardhu/Makefile new file mode 100644 index 000000000..3f9b55f6a --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/cardhu/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := cardhu.o diff --git a/qemu/roms/u-boot/board/nvidia/cardhu/cardhu.c b/qemu/roms/u-boot/board/nvidia/cardhu/cardhu.c new file mode 100644 index 000000000..cc0e5e130 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/cardhu/cardhu.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/gp_padctrl.h> +#include "pinmux-config-cardhu.h" +#include <i2c.h> + +#define PMU_I2C_ADDRESS 0x2D +#define MAX_I2C_RETRY 3 + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(tegra3_pinmux_common, + ARRAY_SIZE(tegra3_pinmux_common)); + + pinmux_config_pingrp_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl)); +} + +#if defined(CONFIG_TEGRA_MMC) +/* + * Do I2C/PMU writes to bring up SD card bus power + * + */ +void board_sdmmc_voltage_init(void) +{ + uchar reg, data_buffer[1]; + int i; + + i2c_set_bus_num(0); /* PMU is on bus 0 */ + + /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */ + data_buffer[0] = 0x65; + reg = 0x32; + + for (i = 0; i < MAX_I2C_RETRY; ++i) { + if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) + udelay(100); + } + + /* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */ + data_buffer[0] = 0x09; + reg = 0x67; + + for (i = 0; i < MAX_I2C_RETRY; ++i) { + if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) + udelay(100); + } +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* + * NOTE: We don't do mmc-specific pin muxes here. + * They were done globally in pinmux_init(). + */ + + /* Bring up the SDIO1 power rail */ + board_sdmmc_voltage_init(); +} +#endif /* MMC */ diff --git a/qemu/roms/u-boot/board/nvidia/cardhu/pinmux-config-cardhu.h b/qemu/roms/u-boot/board/nvidia/cardhu/pinmux-config-cardhu.h new file mode 100644 index 000000000..255e4cd82 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/cardhu/pinmux-config-cardhu.h @@ -0,0 +1,346 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _PINMUX_CONFIG_CARDHU_H_ +#define _PINMUX_CONFIG_CARDHU_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config tegra3_pinmux_common[] = { + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* I2C4 pinmux */ + I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + /* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), + + DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), + LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */ + DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ + DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ + DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), + + /* KBC keys */ + DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), + + /* GPIOs */ + /* SDMMC1 CD gpio */ + DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), + /* SDMMC1 WP gpio */ + LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE), + + /* Touch panel GPIO */ + /* Touch IRQ */ + DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT), + + /* Touch RESET */ + DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT), + + /* Power rails GPIO */ + DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), + + LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), +}; + +static struct pmux_pingrp_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT), +}; + +static struct pmux_drvgrp_config cardhu_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), +}; +#endif /* _PINMUX_CONFIG_CARDHU_H_ */ diff --git a/qemu/roms/u-boot/board/nvidia/common/Makefile b/qemu/roms/u-boot/board/nvidia/common/Makefile new file mode 100644 index 000000000..e3b265157 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/common/Makefile @@ -0,0 +1,4 @@ +# Copyright (c) 2011 The Chromium OS Authors. +# SPDX-License-Identifier: GPL-2.0+ + +include $(src)/common.mk diff --git a/qemu/roms/u-boot/board/nvidia/common/board.c b/qemu/roms/u-boot/board/nvidia/common/board.c new file mode 100644 index 000000000..d01abcee1 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/common/board.c @@ -0,0 +1,255 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ns16550.h> +#include <linux/compiler.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#ifdef CONFIG_LCD +#include <asm/arch/display.h> +#endif +#include <asm/arch/funcmux.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/pmu.h> +#ifdef CONFIG_PWM_TEGRA +#include <asm/arch/pwm.h> +#endif +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/board.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/pmc.h> +#include <asm/arch-tegra/sys_proto.h> +#include <asm/arch-tegra/uart.h> +#include <asm/arch-tegra/warmboot.h> +#ifdef CONFIG_TEGRA_CLOCK_SCALING +#include <asm/arch/emc.h> +#endif +#ifdef CONFIG_USB_EHCI_TEGRA +#include <asm/arch-tegra/usb.h> +#include <usb.h> +#endif +#ifdef CONFIG_TEGRA_MMC +#include <asm/arch-tegra/tegra_mmc.h> +#include <asm/arch-tegra/mmc.h> +#endif +#include <i2c.h> +#include <spi.h> +#include "emc.h" + +DECLARE_GLOBAL_DATA_PTR; + +const struct tegra_sysinfo sysinfo = { + CONFIG_TEGRA_BOARD_STRING +}; + +void __pinmux_init(void) +{ +} + +void pinmux_init(void) __attribute__((weak, alias("__pinmux_init"))); + +void __pin_mux_usb(void) +{ +} + +void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb"))); + +void __pin_mux_spi(void) +{ +} + +void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi"))); + +void __gpio_early_init_uart(void) +{ +} + +void gpio_early_init_uart(void) +__attribute__((weak, alias("__gpio_early_init_uart"))); + +#if defined(CONFIG_TEGRA_NAND) +void __pin_mux_nand(void) +{ + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); +} + +void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand"))); +#endif + +void __pin_mux_display(void) +{ +} + +void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display"))); + +/* + * Routine: power_det_init + * Description: turn off power detects + */ +static void power_det_init(void) +{ +#if defined(CONFIG_TEGRA20) + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + /* turn off power detects */ + writel(0, &pmc->pmc_pwr_det_latch); + writel(0, &pmc->pmc_pwr_det); +#endif +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + __maybe_unused int err; + + /* Do clocks and UART first so that printf() works */ + clock_init(); + clock_verify(); + +#ifdef CONFIG_FDT_SPI + pin_mux_spi(); + spi_init(); +#endif + +#ifdef CONFIG_PWM_TEGRA + if (pwm_init(gd->fdt_blob)) + debug("%s: Failed to init pwm\n", __func__); +#endif +#ifdef CONFIG_LCD + pin_mux_display(); + tegra_lcd_check_next_stage(gd->fdt_blob, 0); +#endif + /* boot param addr */ + gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); + + power_det_init(); + +#ifdef CONFIG_SYS_I2C_TEGRA +#ifndef CONFIG_SYS_I2C_INIT_BOARD +#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards" +#endif + i2c_init_board(); +# ifdef CONFIG_TEGRA_PMU + if (pmu_set_nominal()) + debug("Failed to select nominal voltages\n"); +# ifdef CONFIG_TEGRA_CLOCK_SCALING + err = board_emc_init(); + if (err) + debug("Memory controller init failed: %d\n", err); +# endif +# endif /* CONFIG_TEGRA_PMU */ +#endif /* CONFIG_SYS_I2C_TEGRA */ + +#ifdef CONFIG_USB_EHCI_TEGRA + pin_mux_usb(); + usb_process_devicetree(gd->fdt_blob); +#endif + +#ifdef CONFIG_LCD + tegra_lcd_check_next_stage(gd->fdt_blob, 0); +#endif + +#ifdef CONFIG_TEGRA_NAND + pin_mux_nand(); +#endif + +#ifdef CONFIG_TEGRA_LP0 + /* save Sdram params to PMC 2, 4, and 24 for WB0 */ + warmboot_save_sdram_params(); + + /* prepare the WB code to LP0 location */ + warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +static void __gpio_early_init(void) +{ +} + +void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); + +int board_early_init_f(void) +{ + pinmux_init(); + board_init_uart_f(); + + /* Initialize periph GPIOs */ + gpio_early_init(); + gpio_early_init_uart(); +#ifdef CONFIG_LCD + tegra_lcd_early_init(gd->fdt_blob); +#endif + + return 0; +} +#endif /* EARLY_INIT */ + +int board_late_init(void) +{ +#ifdef CONFIG_LCD + /* Make sure we finish initing the LCD */ + tegra_lcd_check_next_stage(gd->fdt_blob, 1); +#endif + return 0; +} + +#if defined(CONFIG_TEGRA_MMC) +void __pin_mux_mmc(void) +{ +} + +void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc"))); + +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("%s called\n", __func__); + + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + + debug("%s: init MMC\n", __func__); + tegra_mmc_init(); + + return 0; +} + +void pad_init_mmc(struct mmc_host *host) +{ +#if defined(CONFIG_TEGRA30) + enum periph_id id = host->mmc_id; + u32 val; + + debug("%s: sdmmc address = %08x, id = %d\n", __func__, + (unsigned int)host->reg, id); + + /* Set the pad drive strength for SDMMC1 or 3 only */ + if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { + debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", + __func__); + return; + } + + val = readl(&host->reg->sdmemcmppadctl); + val &= 0xFFFFFFF0; + val |= MEMCOMP_PADCTRL_VREF; + writel(val, &host->reg->sdmemcmppadctl); + + val = readl(&host->reg->autocalcfg); + val &= 0xFFFF0000; + val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; + writel(val, &host->reg->autocalcfg); +#endif /* T30 */ +} +#endif /* MMC */ diff --git a/qemu/roms/u-boot/board/nvidia/common/common.mk b/qemu/roms/u-boot/board/nvidia/common/common.mk new file mode 100644 index 000000000..9a9b5298c --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/common/common.mk @@ -0,0 +1,3 @@ +# common options for all tegra boards +obj-y += ../../nvidia/common/board.o +obj-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o diff --git a/qemu/roms/u-boot/board/nvidia/common/emc.c b/qemu/roms/u-boot/board/nvidia/common/emc.c new file mode 100644 index 000000000..8124f8aaf --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/common/emc.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/emc.h> +#include <asm/arch/pmu.h> +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/ap.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* These rates are hard-coded for now, until fdt provides them */ +#define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000) +#define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000) + +int board_emc_init(void) +{ + unsigned rate; + + switch (tegra_get_chip_sku()) { + default: + case TEGRA_SOC_T20: + rate = EMC_SDRAM_RATE_T20; + break; + case TEGRA_SOC_T25: + rate = EMC_SDRAM_RATE_T25; + break; + } + return tegra_set_emc(gd->fdt_blob, rate); +} diff --git a/qemu/roms/u-boot/board/nvidia/common/emc.h b/qemu/roms/u-boot/board/nvidia/common/emc.h new file mode 100644 index 000000000..409523517 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/common/emc.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _NVIDIA_EMC_H_ +#define _NVIDIA_EMC_H_ + +int board_emc_init(void); + +#endif diff --git a/qemu/roms/u-boot/board/nvidia/dalmore/Makefile b/qemu/roms/u-boot/board/nvidia/dalmore/Makefile new file mode 100644 index 000000000..7cdff9c61 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/dalmore/Makefile @@ -0,0 +1,17 @@ +# +# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +obj-y := dalmore.o diff --git a/qemu/roms/u-boot/board/nvidia/dalmore/dalmore.c b/qemu/roms/u-boot/board/nvidia/dalmore/dalmore.c new file mode 100644 index 000000000..f2d05afac --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/dalmore/dalmore.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/gp_padctrl.h> +#include "pinmux-config-dalmore.h" +#include <i2c.h> + +#define BAT_I2C_ADDRESS 0x48 /* TPS65090 charger */ +#define PMU_I2C_ADDRESS 0x58 /* TPS65913 PMU */ + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(tegra114_pinmux_set_nontristate, + ARRAY_SIZE(tegra114_pinmux_set_nontristate)); + + pinmux_config_pingrp_table(tegra114_pinmux_common, + ARRAY_SIZE(tegra114_pinmux_common)); + + pinmux_config_pingrp_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + pinmux_config_drvgrp_table(dalmore_padctrl, + ARRAY_SIZE(dalmore_padctrl)); +} + +#if defined(CONFIG_TEGRA_MMC) +/* + * Do I2C/PMU writes to bring up SD card bus power + * + */ +void board_sdmmc_voltage_init(void) +{ + uchar reg, data_buffer[1]; + int ret; + + ret = i2c_set_bus_num(0);/* PMU is on bus 0 */ + if (ret) + printf("%s: i2c_set_bus_num returned %d\n", __func__, ret); + + /* TPS65913: LDO9_VOLTAGE = 3.3V */ + data_buffer[0] = 0x31; + reg = 0x61; + + ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1); + if (ret) + printf("%s: PMU i2c_write %02X<-%02X returned %d\n", + __func__, reg, data_buffer[0], ret); + + /* TPS65913: LDO9_CTRL = Active */ + data_buffer[0] = 0x01; + reg = 0x60; + + ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1); + if (ret) + printf("%s: PMU i2c_write %02X<-%02X returned %d\n", + __func__, reg, data_buffer[0], ret); + + /* TPS65090: FET6_CTRL = enable output auto discharge, enable FET6 */ + data_buffer[0] = 0x03; + reg = 0x14; + + ret = i2c_write(BAT_I2C_ADDRESS, reg, 1, data_buffer, 1); + if (ret) + printf("%s: BAT i2c_write %02X<-%02X returned %d\n", + __func__, reg, data_buffer[0], ret); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* + * NOTE: We don't do mmc-specific pin muxes here. + * They were done globally in pinmux_init(). + */ + + /* Bring up the SDIO3 power rail */ + board_sdmmc_voltage_init(); +} +#endif /* MMC */ diff --git a/qemu/roms/u-boot/board/nvidia/dalmore/pinmux-config-dalmore.h b/qemu/roms/u-boot/board/nvidia/dalmore/pinmux-config-dalmore.h new file mode 100644 index 000000000..891ac07dd --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _PINMUX_CONFIG_DALMORE_H_ +#define _PINMUX_CONFIG_DALMORE_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define USB_PINMUX CEC_PINMUX + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config tegra114_pinmux_common[] = { + /* EXTPERIPH1 pinmux */ + DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + + /* I2S0 pinmux */ + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + + /* I2S1 pinmux */ + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), + + /* I2S3 pinmux */ + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + + /* CLDVFS pinmux */ + DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, OUTPUT), + + /* I2C3 pinmux */ + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* VI pinmux */ + VI_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + + /* VI_ALT1 pinmux */ + VI_PINMUX(PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + + /* VGP4 pinmux */ + VI_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* UARTD pinmux */ + DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT), + + /* SPI4 pinmux */ + DEFAULT_PINMUX(GMI_AD5_PG5, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6_PG6, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD7_PG7, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS6_N_PI3, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N_PI0, SPI4, NORMAL, NORMAL, INPUT), + + /* PWM1 pinmux */ + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + + /* SOC pinmux */ + DEFAULT_PINMUX(GMI_CS1_N_PJ2, SOC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_OE_N_PI1, SOC, NORMAL, TRISTATE, INPUT), + + /* EXTPERIPH2 pinmux */ + DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT), + + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT), + + /* BLINK pinmux */ + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), + + /* KBC pinmux */ + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT), + + /*Audio Codec*/ + DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT), + + /* UARTA pinmux */ + DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT), + + /* I2CPWR pinmux (I2C5) */ + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* SYSCLK pinmux */ + DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), + + /* RTCK pinmux */ + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), + + /* CLK pinmux */ + DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT), + + /* PWRON pinmux */ + DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT), + + /* CPU pinmux */ + DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT), + + /* PMI pinmux */ + DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT), + + /* RESET_OUT_N pinmux */ + DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT), + + /* EXTPERIPH3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* UARTB pinmux */ + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), + + /* IRDA pinmux */ + DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT), + + /* UARTC pinmux */ + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + + /* OWR pinmux */ + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + + /* CEC pinmux */ + CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* I2C4 pinmux */ + DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + + /* USB pinmux */ + USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* nct */ + DEFAULT_PINMUX(GPIO_X6_AUD_PX6, SPI6, UP, TRISTATE, INPUT), +}; + +static struct pmux_pingrp_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(USB_VBUS_EN1_PN5, RSVD3, DOWN, TRISTATE, OUTPUT), +}; + +/* Initially setting all used GPIO's to non-TRISTATE */ +static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = { + DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X6_AUD_PX6, RSVD3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X1_AUD_PX1, RSVD3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PBB3, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB5, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB6, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PBB7, RSVD3, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(PCC1, RSVD3, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(PCC2, RSVD3, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD10_PH2, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD11_PH3, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD12_PH4, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13_PH5, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CLK_PK1, GMI, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS2_N_PK3, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS3_N_PK4, GMI, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_DQS_P_PJ3, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY_PI5, GMI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(SDMMC1_WP_N_PV3, SPI4, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPDIF_IN_PK6, USB, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT), +}; + +static struct pmux_drvgrp_config dalmore_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE), +}; +#endif /* PINMUX_CONFIG_COMMON_H */ diff --git a/qemu/roms/u-boot/board/nvidia/harmony/Makefile b/qemu/roms/u-boot/board/nvidia/harmony/Makefile new file mode 100644 index 000000000..222b025e9 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/harmony/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := harmony.o diff --git a/qemu/roms/u-boot/board/nvidia/harmony/harmony.c b/qemu/roms/u-boot/board/nvidia/harmony/harmony.c new file mode 100644 index 000000000..c892a2575 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/harmony/harmony.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <lcd.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/tegra.h> +#include <asm/gpio.h> + +#ifdef CONFIG_TEGRA_MMC +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); + funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT); + + /* For power GPIO PI6 */ + pinmux_tristate_disable(PMUX_PINGRP_ATA); + /* For CD GPIO PH2 */ + pinmux_tristate_disable(PMUX_PINGRP_ATD); + + /* For power GPIO PT3 */ + pinmux_tristate_disable(PMUX_PINGRP_DTB); + /* For CD GPIO PI5 */ + pinmux_tristate_disable(PMUX_PINGRP_ATC); +} +#endif + +void pin_mux_usb(void) +{ + funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); + pinmux_tristate_disable(PMUX_PINGRP_CDEV2); + /* USB2 PHY reset GPIO */ + pinmux_tristate_disable(PMUX_PINGRP_UAC); +} + +void pin_mux_display(void) +{ + pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); + pinmux_tristate_disable(PMUX_PINGRP_SDC); +} diff --git a/qemu/roms/u-boot/board/nvidia/jetson-tk1/Makefile b/qemu/roms/u-boot/board/nvidia/jetson-tk1/Makefile new file mode 100644 index 000000000..0f054117c --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/jetson-tk1/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ../venice2/as3722_init.o +obj-y += jetson-tk1.o diff --git a/qemu/roms/u-boot/board/nvidia/jetson-tk1/jetson-tk1.c b/qemu/roms/u-boot/board/nvidia/jetson-tk1/jetson-tk1.c new file mode 100644 index 000000000..f97aafad4 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/jetson-tk1/jetson-tk1.c @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/pinmux.h> +#include "pinmux-config-jetson-tk1.h" + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(jetson_tk1_pingrps, + ARRAY_SIZE(jetson_tk1_pingrps)); + + pinmux_config_drvgrp_table(jetson_tk1_drvgrps, + ARRAY_SIZE(jetson_tk1_drvgrps)); +} diff --git a/qemu/roms/u-boot/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/qemu/roms/u-boot/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h new file mode 100644 index 000000000..1adcae4bd --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_JETSON_TK1_H_ +#define _PINMUX_CONFIG_JETSON_TK1_H_ + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, rcv_sel */ + PINCFG(CLK_32K_OUT_PA0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB0, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB1, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PC7, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG1, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG3, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH2, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH4, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH7, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI6, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK1, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK3, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_OUT_PK5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(ULPI_DATA7_PO0, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA0_PO1, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA1_PO2, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA2_PO3, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA3_PO4, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA6_PO7, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DOUT_PP2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL0_PQ0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL1_PQ1, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL2_PQ2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL5_PQ5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL6_PQ6, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL7_PQ7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW0_PR0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW1_PR1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW2_PR2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW4_PR4, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW5_PR5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW7_PR7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW8_PS0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW11_PS3, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW12_PS4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW13_PS5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW14_PS6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW16_PT0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW17_PT1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU0, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU1, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU5, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU6, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV1, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(GPIO_W2_AUD_PW2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X1_AUD_PX1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X3_AUD_PX3, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X4_AUD_PX4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X5_AUD_PX5, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X6_AUD_PX6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X7_AUD_PX7, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PBB3, VGP3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB7, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC1, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PCC2, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_REQ_PCC5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_REQ_PEE1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PFF2, RSVD2, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), + PINCFG(CLK_32K_IN, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_JETSON_TK1_H */ diff --git a/qemu/roms/u-boot/board/nvidia/seaboard/Makefile b/qemu/roms/u-boot/board/nvidia/seaboard/Makefile new file mode 100644 index 000000000..917141846 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/seaboard/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := seaboard.o diff --git a/qemu/roms/u-boot/board/nvidia/seaboard/seaboard.c b/qemu/roms/u-boot/board/nvidia/seaboard/seaboard.c new file mode 100644 index 000000000..ce2db40f9 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/seaboard/seaboard.c @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/tegra.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include <asm/gpio.h> + +/* TODO: Remove this code when the SPI switch is working */ +#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) +void gpio_early_init_uart(void) +{ + /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ +#ifndef CONFIG_SPL_BUILD + gpio_request(GPIO_PI3, NULL); +#endif + gpio_direction_output(GPIO_PI3, 0); +} +#endif + +#ifdef CONFIG_TEGRA_MMC +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); + funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT); + + /* For power GPIO PI6 */ + pinmux_tristate_disable(PMUX_PINGRP_ATA); + /* For CD GPIO PI5 */ + pinmux_tristate_disable(PMUX_PINGRP_ATC); +} +#endif + +void pin_mux_usb(void) +{ + /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */ + pinmux_tristate_disable(PMUX_PINGRP_SLXK); +} diff --git a/qemu/roms/u-boot/board/nvidia/venice2/Makefile b/qemu/roms/u-boot/board/nvidia/venice2/Makefile new file mode 100644 index 000000000..5fac5ab1f --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/venice2/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2013-2014 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += as3722_init.o +obj-y += venice2.o diff --git a/qemu/roms/u-boot/board/nvidia/venice2/as3722_init.c b/qemu/roms/u-boot/board/nvidia/venice2/as3722_init.c new file mode 100644 index 000000000..960fea7ee --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/venice2/as3722_init.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include "as3722_init.h" + +/* AS3722-PMIC-specific early init code - get CPU rails up, etc */ + +void tegra_i2c_ll_write_addr(uint addr, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(addr, ®->cmd_addr0); + writel(config, ®->cnfg); +} + +void tegra_i2c_ll_write_data(uint data, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(data, ®->cmd_data1); + writel(config, ®->cnfg); +} + +void pmic_enable_cpu_vdd(void) +{ + debug("%s entry\n", __func__); + + /* Don't need to set up VDD_CORE - already done - by OTP */ + + debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); + /* + * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.0V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__); + /* + * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.0V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__); + /* + * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus. + * First set VDD to 1.2V, then enable the VDD regulator. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. + * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); + + debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__); + /* + * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. + * First set it to bypass 3.3V straight thru, then enable the regulator + * + * NOTE: We do this early because doing it later seems to hose the CPU + * power rail/partition startup. Need to debug. + */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. + * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); +} diff --git a/qemu/roms/u-boot/board/nvidia/venice2/as3722_init.h b/qemu/roms/u-boot/board/nvidia/venice2/as3722_init.h new file mode 100644 index 000000000..a7b24039f --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/venice2/as3722_init.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* AS3722-PMIC-specific early init regs */ + +#define AS3722_I2C_ADDR 0x80 + +#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */ +#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */ +#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */ +#define AS3722_SDCONTROL_REG 0x4D + +#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */ +#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */ +#define AS3722_LDCONTROL_REG 0x4E + +#ifdef CONFIG_BOARD_JETSON_TK1 +#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG) +#else +#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG) +#endif +#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG) + +#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG) +#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG) + +#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG) +#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG) + +#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG) +#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG) + +#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG) +#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG) + +#define I2C_SEND_2_BYTES 0x0A02 + +void pmic_enable_cpu_vdd(void); diff --git a/qemu/roms/u-boot/board/nvidia/venice2/pinmux-config-venice2.h b/qemu/roms/u-boot/board/nvidia/venice2/pinmux-config-venice2.h new file mode 100644 index 000000000..2f79ec752 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/venice2/pinmux-config-venice2.h @@ -0,0 +1,339 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_VENICE2_H_ +#define _PINMUX_CONFIG_VENICE2_H_ + +#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ + } + +#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .lock = PMUX_PIN_LOCK_##_lock, \ + .od = PMUX_PIN_OD_##_od, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +#define USB_PINMUX CEC_PINMUX + +#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static struct pmux_pingrp_config tegra124_pinmux_common[] = { + /* EXTPERIPH1 pinmux */ + DEFAULT_PINMUX(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + + /* I2S0 pinmux */ + DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), + + /* I2S1 pinmux */ + DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), + + /* I2S3 pinmux */ + DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), + + /* CLDVFS pinmux */ + DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT), + + /* ULPI pinmux */ + DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT), + + /* EC KBC/SPI */ + DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT), + + /* I2C3 (TPM) pinmux */ + I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* I2C2 pinmux */ + I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* UARTD pinmux (UART4 on Servo board, unused) */ + DEFAULT_PINMUX(PJ7, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PB0, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PB1, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PK7, UARTD, NORMAL, NORMAL, OUTPUT), + + /* SPI4 (Winbond 'boot ROM') */ + DEFAULT_PINMUX(PG5, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PG6, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PG7, SPI4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(PI3, SPI4, NORMAL, NORMAL, INPUT), + + /* Touch IRQ */ + DEFAULT_PINMUX(GPIO_W3_AUD_PW3, RSVD1, NORMAL, NORMAL, INPUT), + + /* PWM1 pinmux */ + DEFAULT_PINMUX(PH1, PWM1, NORMAL, NORMAL, OUTPUT), + + /* SDMMC1 pinmux */ + DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), + + /* SDMMC3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT), + + /* SDMMC4 pinmux */ + DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT), + + /* BLINK pinmux */ + DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), + + /* KBC pinmux */ + DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), + + /* Misc */ + DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT), + + /* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */ + DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT), + + /* I2CPWR pinmux (I2C5) */ + I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* RTCK pinmux */ + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), + + /* CLK pinmux */ + DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT), + + /* PWRON pinmux */ + DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT), + + /* CPU pinmux */ + DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT), + + /* PMI pinmux */ + DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT), + + /* RESET_OUT_N pinmux */ + DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT), + + /* EXTPERIPH3 pinmux */ + DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), + + /* I2C1 pinmux */ + I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* UARTB, GPS */ + DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT), + + /* UARTC (WIFI/BT) */ + DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), + + /* CEC pinmux */ + CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + /* I2C4 (HDMI_DDC) pinmux */ + DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH), + + /* USB pinmux */ + USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + USB_PINMUX(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + /* Unused, marked SNN_ on schematic, TRISTATE 'em */ + DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB3, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB4, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB5, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PH3, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PI7, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PJ2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_X6_AUD_PX6, GMI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(PFF2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(USB_VBUS_EN2_PFF1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL5_PQ5, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW2_PR2, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5_PR5, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW13_PS5, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW14_PS6, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW16_PT0, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_FS_PP0, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SDMMC1_WP_N_PV3, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPDIF_OUT_PK5, RSVD1, NORMAL, TRISTATE, INPUT), +}; + +static struct pmux_pingrp_config unused_pins_lowpower[] = { + DEFAULT_PINMUX(DAP_MCLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT), +}; + +/* Initially setting all used GPIO's to non-TRISTATE */ +static struct pmux_pingrp_config tegra124_pinmux_set_nontristate[] = { + DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT), + + /* EN_VDD_BL */ + DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT), + + /* MODEM */ + DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), + + /* BOOT_SEL0-3 */ + DEFAULT_PINMUX(PG0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PG1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PG2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PG3, GMI, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), + + DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT), + + /* TS_SHDN_L */ + DEFAULT_PINMUX(PK1, GMI, NORMAL, NORMAL, OUTPUT), +}; + +static struct pmux_drvgrp_config venice2_padctrl[] = { + /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE), +}; +#endif /* PINMUX_CONFIG_VENICE2_H */ diff --git a/qemu/roms/u-boot/board/nvidia/venice2/venice2.c b/qemu/roms/u-boot/board/nvidia/venice2/venice2.c new file mode 100644 index 000000000..15082c419 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/venice2/venice2.c @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm-generic/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/gp_padctrl.h> +#include <asm/arch/pinmux.h> +#include "pinmux-config-venice2.h" +#include <i2c.h> + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_config_pingrp_table(tegra124_pinmux_set_nontristate, + ARRAY_SIZE(tegra124_pinmux_set_nontristate)); + + pinmux_config_pingrp_table(tegra124_pinmux_common, + ARRAY_SIZE(tegra124_pinmux_common)); + + pinmux_config_pingrp_table(unused_pins_lowpower, + ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + pinmux_config_drvgrp_table(venice2_padctrl, + ARRAY_SIZE(venice2_padctrl)); +} diff --git a/qemu/roms/u-boot/board/nvidia/ventana/Makefile b/qemu/roms/u-boot/board/nvidia/ventana/Makefile new file mode 100644 index 000000000..f67044f2c --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/ventana/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ../seaboard/seaboard.o diff --git a/qemu/roms/u-boot/board/nvidia/whistler/Makefile b/qemu/roms/u-boot/board/nvidia/whistler/Makefile new file mode 100644 index 000000000..b54c5fd33 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/whistler/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := whistler.o diff --git a/qemu/roms/u-boot/board/nvidia/whistler/whistler.c b/qemu/roms/u-boot/board/nvidia/whistler/whistler.c new file mode 100644 index 000000000..3e9d3d9f1 --- /dev/null +++ b/qemu/roms/u-boot/board/nvidia/whistler/whistler.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/tegra.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/pinmux.h> +#include <asm/gpio.h> +#include <i2c.h> + +#ifdef CONFIG_TEGRA_MMC +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +void pin_mux_mmc(void) +{ + uchar val; + int ret; + + /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ + ret = i2c_set_bus_num(0); + if (ret) + printf("i2c_set_bus_num failed: %d\n", ret); + val = 0x29; + ret = i2c_write(0x3c, 0x46, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret); + val = 0x00; + ret = i2c_write(0x3c, 0x45, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret); + val = 0x1f; + ret = i2c_write(0x3c, 0x44, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); + + funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); +} +#endif + +/* this is a weak define that we are overriding */ +void pin_mux_usb(void) +{ + uchar val; + int ret; + + /* + * This is a hack. This should be represented in DT using the + * vbus-gpio property. However, U-Boot's DT support doesn't + * support any GPIO controller other than the Tegra's yet. + */ + + /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */ + ret = i2c_set_bus_num(0); + if (ret) + printf("i2c_set_bus_num failed: %d\n", ret); + val = 0x03; + ret = i2c_write(0x20, 2, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x20 2 failed: %d\n", ret); + val = 0xfc; + ret = i2c_write(0x20, 6, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x20 6 failed: %d\n", ret); +} |