Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

8 files changed, 4296 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/netta/Makefile b/qemu/roms/u-boot/board/netta/Makefile
new file mode 100644
index 000000000..98bac7ed4
--- /dev/null
+++ b/qemu/roms/u-boot/board/netta/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= netta.o flash.o dsp.o codec.o pcmcia.o
diff --git a/qemu/roms/u-boot/board/netta/codec.c b/qemu/roms/u-boot/board/netta/codec.c
new file mode 100644
index 000000000..e303aa478
--- /dev/null
+++ b/qemu/roms/u-boot/board/netta/codec.c
@@ -0,0 +1,1481 @@
+/*
+ * CODEC
+ */
+
+#include <common.h>
+#include <post.h>
+
+#include "mpc8xx.h"
+
+/***********************************************/
+
+#define MAX_DUSLIC	4
+
+#define NUM_CHANNELS	2
+#define MAX_SLICS	(MAX_DUSLIC * NUM_CHANNELS)
+
+/***********************************************/
+
+#define SOP_READ_CH_0		0xC4  /* Read SOP Register for Channel A  */
+#define SOP_READ_CH_1		0xCC  /* Read SOP Register for Channel B  */
+#define SOP_WRITE_CH_0		0x44  /* Write SOP Register for Channel A */
+#define SOP_WRITE_CH_1		0x4C  /* Write SOP Register for Channel B */
+
+#define COP_READ_CH_0		0xC5
+#define COP_READ_CH_1		0xCD
+#define COP_WRITE_CH_0		0x45
+#define COP_WRITE_CH_1		0x4D
+
+#define POP_READ_CH_0		0xC6
+#define POP_READ_CH_1		0xCE
+#define POP_WRITE_CH_0		0x46
+#define POP_WRITE_CH_1		0x4E
+
+#define RST_CMD_DUSLIC_CHIP	0x40  /* OR 0x48 */
+#define RST_CMD_DUSLIC_CH_A	0x41
+#define RST_CMD_DUSLIC_CH_B	0x49
+
+#define PCM_RESYNC_CMD_CH_A	0x42
+#define PCM_RESYNC_CMD_CH_B	0x4A
+
+#define ACTIVE_HOOK_LEV_4	0
+#define ACTIVE_HOOK_LEV_12	1
+
+#define SLIC_P_NORMAL		0x01
+
+/************************************************/
+
+#define CODSP_WR	0x00
+#define CODSP_RD	0x80
+#define CODSP_OP	0x40
+#define CODSP_ADR(x)	(((unsigned char)(x) & 7) << 3)
+#define CODSP_M(x)	((unsigned char)(x) & 7)
+#define CODSP_CMD(x)	((unsigned char)(x) & 7)
+
+/************************************************/
+
+/* command indication ops */
+#define CODSP_M_SLEEP_PWRDN	7
+#define CODSP_M_PWRDN_HIZ	0
+#define CODSP_M_ANY_ACT		2
+#define CODSP_M_RING		5
+#define CODSP_M_ACT_MET		6
+#define CODSP_M_GND_START	4
+#define CODSP_M_RING_PAUSE	1
+
+/* single byte commands */
+#define CODSP_CMD_SOFT_RESET	CODSP_CMD(0)
+#define CODSP_CMD_RESET_CH	CODSP_CMD(1)
+#define CODSP_CMD_RESYNC	CODSP_CMD(2)
+
+/* two byte commands */
+#define CODSP_CMD_SOP		CODSP_CMD(4)
+#define CODSP_CMD_COP		CODSP_CMD(5)
+#define CODSP_CMD_POP		CODSP_CMD(6)
+
+/************************************************/
+
+/* read as 4-bytes */
+#define CODSP_INTREG_INT_CH	0x80000000
+#define CODSP_INTREG_HOOK	0x40000000
+#define CODSP_INTREG_GNDK	0x20000000
+#define CODSP_INTREG_GNDP	0x10000000
+#define CODSP_INTREG_ICON	0x08000000
+#define CODSP_INTREG_VRTLIM	0x04000000
+#define CODSP_INTREG_OTEMP	0x02000000
+#define CODSP_INTREG_SYNC_FAIL	0x01000000
+#define CODSP_INTREG_LM_THRES	0x00800000
+#define CODSP_INTREG_READY	0x00400000
+#define CODSP_INTREG_RSTAT	0x00200000
+#define CODSP_INTREG_LM_OK	0x00100000
+#define CODSP_INTREG_IO4_DU	0x00080000
+#define CODSP_INTREG_IO3_DU	0x00040000
+#define CODSP_INTREG_IO2_DU	0x00020000
+#define CODSP_INTREG_IO1_DU	0x00010000
+#define CODSP_INTREG_DTMF_OK	0x00008000
+#define CODSP_INTREG_DTMF_KEY4	0x00004000
+#define CODSP_INTREG_DTMF_KEY3	0x00002000
+#define CODSP_INTREG_DTMF_KEY2	0x00001000
+#define CODSP_INTREG_DTMF_KEY1	0x00000800
+#define CODSP_INTREG_DTMF_KEY0	0x00000400
+#define CODSP_INTREG_UTDR_OK	0x00000200
+#define CODSP_INTREG_UTDX_OK	0x00000100
+#define CODSP_INTREG_EDSP_FAIL	0x00000080
+#define CODSP_INTREG_CIS_BOF	0x00000008
+#define CODSP_INTREG_CIS_BUF	0x00000004
+#define CODSP_INTREG_CIS_REQ	0x00000002
+#define CODSP_INTREG_CIS_ACT	0x00000001
+
+/************************************************/
+
+/* ======== SOP REG ADDRESSES =======*/
+
+#define REVISION_ADDR		0x00
+#define PCMC1_ADDR		0x05
+#define XCR_ADDR		0x06
+#define INTREG1_ADDR		0x07
+#define INTREG2_ADDR		0x08
+#define INTREG3_ADDR		0x09
+#define INTREG4_ADDR		0x0A
+#define LMRES1_ADDR		0x0D
+#define MASK_ADDR		0x11
+#define IOCTL3_ADDR		0x14
+#define BCR1_ADDR		0x15
+#define BCR2_ADDR		0x16
+#define BCR3_ADDR		0x17
+#define BCR4_ADDR		0x18
+#define BCR5_ADDR		0x19
+#define DSCR_ADDR		0x1A
+#define LMCR1_ADDR		0x1C
+#define LMCR2_ADDR		0x1D
+#define LMCR3_ADDR		0x1E
+#define OFR1_ADDR		0x1F
+#define PCMR1_ADDR		0x21
+#define PCMX1_ADDR		0x25
+#define TSTR3_ADDR		0x2B
+#define TSTR4_ADDR		0x2C
+#define TSTR5_ADDR		0x2D
+
+/* ========= POP REG ADDRESSES ========*/
+
+#define CIS_DAT_ADDR		0x00
+
+#define LEC_LEN_ADDR		0x3A
+#define LEC_POWR_ADDR		0x3B
+#define LEC_DELP_ADDR		0x3C
+#define LEC_DELQ_ADDR		0x3D
+#define LEC_GAIN_XI_ADDR	0x3E
+#define LEC_GAIN_RI_ADDR	0x3F
+#define LEC_GAIN_XO_ADDR	0x40
+#define LEC_RES_1_ADDR		0x41
+#define LEC_RES_2_ADDR		0x42
+
+#define NLP_POW_LPF_ADDR	0x30
+#define NLP_POW_LPS_ADDR	0x31
+#define NLP_BN_LEV_X_ADDR	0x32
+#define NLP_BN_LEV_R_ADDR	0x33
+#define NLP_BN_INC_ADDR		0x34
+#define NLP_BN_DEC_ADDR		0x35
+#define NLP_BN_MAX_ADDR		0x36
+#define NLP_BN_ADJ_ADDR		0x37
+#define NLP_RE_MIN_ERLL_ADDR	0x38
+#define NLP_RE_EST_ERLL_ADDR	0x39
+#define NLP_SD_LEV_X_ADDR	0x3A
+#define NLP_SD_LEV_R_ADDR	0x3B
+#define NLP_SD_LEV_BN_ADDR	0x3C
+#define NLP_SD_LEV_RE_ADDR	0x3D
+#define NLP_SD_OT_DT_ADDR	0x3E
+#define NLP_ERL_LIN_LP_ADDR	0x3F
+#define NLP_ERL_LEC_LP_ADDR	0x40
+#define NLP_CT_LEV_RE_ADDR	0x41
+#define NLP_CTRL_ADDR		0x42
+
+#define UTD_CF_H_ADDR		0x4B
+#define UTD_CF_L_ADDR		0x4C
+#define UTD_BW_H_ADDR		0x4D
+#define UTD_BW_L_ADDR		0x4E
+#define UTD_NLEV_ADDR		0x4F
+#define UTD_SLEV_H_ADDR		0x50
+#define UTD_SLEV_L_ADDR		0x51
+#define UTD_DELT_ADDR		0x52
+#define UTD_RBRK_ADDR		0x53
+#define UTD_RTIME_ADDR		0x54
+#define UTD_EBRK_ADDR		0x55
+#define UTD_ETIME_ADDR		0x56
+
+#define DTMF_LEV_ADDR		0x30
+#define DTMF_TWI_ADDR		0x31
+#define DTMF_NCF_H_ADDR		0x32
+#define DTMF_NCF_L_ADDR		0x33
+#define DTMF_NBW_H_ADDR		0x34
+#define DTMF_NBW_L_ADDR		0x35
+#define DTMF_GAIN_ADDR		0x36
+#define DTMF_RES1_ADDR		0x37
+#define DTMF_RES2_ADDR		0x38
+#define DTMF_RES3_ADDR		0x39
+
+#define CIS_LEV_H_ADDR		0x43
+#define CIS_LEV_L_ADDR		0x44
+#define CIS_BRS_ADDR		0x45
+#define CIS_SEIZ_H_ADDR		0x46
+#define CIS_SEIZ_L_ADDR		0x47
+#define CIS_MARK_H_ADDR		0x48
+#define CIS_MARK_L_ADDR		0x49
+#define CIS_LEC_MODE_ADDR	0x4A
+
+/*=====================================*/
+
+#define HOOK_LEV_ACT_START_ADDR 0x89
+#define RO1_START_ADDR		0x70
+#define RO2_START_ADDR		0x95
+#define RO3_START_ADDR		0x96
+
+#define TG1_FREQ_START_ADDR	0x38
+#define TG1_GAIN_START_ADDR	0x39
+#define TG1_BANDPASS_START_ADDR 0x3B
+#define TG1_BANDPASS_END_ADDR	0x3D
+
+#define TG2_FREQ_START_ADDR	0x40
+#define TG2_GAIN_START_ADDR	0x41
+#define TG2_BANDPASS_START_ADDR 0x43
+#define TG2_BANDPASS_END_ADDR	0x45
+
+/*====================================*/
+
+#define PCM_HW_B		0x80
+#define PCM_HW_A		0x00
+#define PCM_TIME_SLOT_0		0x00   /*  Byte 0 of PCM Frame (by default is assigned to channel A ) */
+#define PCM_TIME_SLOT_1		0x01   /*  Byte 1 of PCM Frame (by default is assigned to channel B ) */
+#define PCM_TIME_SLOT_4		0x04   /*  Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */
+
+#define	 RX_LEV_ADDR	0x28
+#define	 TX_LEV_ADDR	0x30
+#define	 Ik1_ADDR	0x83
+
+#define	 AR_ROW		3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct	*/
+#define	 AX_ROW		6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct	*/
+#define	 DCF_ROW	0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */
+
+/* Mark the start byte of Duslic parameters that we use with configurator */
+#define	 Ik1_START_BYTE		3
+#define	 RX_LEV_START_BYTE	0
+#define	 TX_LEV_START_BYTE	0
+
+/************************************************/
+
+#define INTREG4_CIS_ACT		(1 << 0)
+
+#define BCR1_SLEEP		0x20
+#define BCR1_REVPOL		0x10
+#define BCR1_ACTR		0x08
+#define BCR1_ACTL		0x04
+#define BCR1_SLIC_MASK		0x03
+
+#define BCR2_HARD_POL_REV	0x40
+#define BCR2_TTX		0x20
+#define BCR2_TTX_12K		0x10
+#define BCR2_HIMAN		0x08
+#define BCR2_PDOT		0x01
+
+#define BCR3_PCMX_EN		(1 << 4)
+
+#define BCR5_DTMF_EN		(1 << 0)
+#define BCR5_DTMF_SRC		(1 << 1)
+#define BCR5_LEC_EN		(1 << 2)
+#define BCR5_LEC_OUT		(1 << 3)
+#define BCR5_CIS_EN		(1 << 4)
+#define BCR5_CIS_AUTO		(1 << 5)
+#define BCR5_UTDX_EN		(1 << 6)
+#define BCR5_UTDR_EN		(1 << 7)
+
+#define DSCR_TG1_EN		(1 << 0)
+#define DSCR_TG2_EN		(1 << 1)
+#define DSCR_PTG		(1 << 2)
+#define DSCR_COR8		(1 << 3)
+#define DSCR_DG_KEY(x)		(((x) & 0x0F) << 4)
+
+#define CIS_LEC_MODE_CIS_V23	(1 << 0)
+#define CIS_LEC_MODE_CIS_FRM	(1 << 1)
+#define CIS_LEC_MODE_NLP_EN	(1 << 2)
+#define CIS_LEC_MODE_UTDR_SUM	(1 << 4)
+#define CIS_LEC_MODE_UTDX_SUM	(1 << 5)
+#define CIS_LEC_MODE_LEC_FREEZE (1 << 6)
+#define CIS_LEC_MODE_LEC_ADAPT	(1 << 7)
+
+#define TSTR4_COR_64		(1 << 5)
+
+#define TSTR3_AC_DLB_8K		(1 << 2)
+#define TSTR3_AC_DLB_32K	(1 << 3)
+#define TSTR3_AC_DLB_4M		(1 << 5)
+
+
+#define LMCR1_TEST_EN		(1 << 7)
+#define LMCR1_LM_EN		(1 << 6)
+#define LMCR1_LM_THM		(1 << 5)
+#define LMCR1_LM_ONCE		(1 << 2)
+#define LMCR1_LM_MASK		(1 << 1)
+
+#define LMCR2_LM_RECT			(1 << 5)
+#define LMCR2_LM_SEL_VDD		0x0D
+#define LMCR2_LM_SEL_IO3		0x0A
+#define LMCR2_LM_SEL_IO4		0x0B
+#define LMCR2_LM_SEL_IO4_MINUS_IO3	0x0F
+
+#define LMCR3_RTR_SEL		(1 << 6)
+
+#define LMCR3_RNG_OFFSET_NONE	0x00
+#define LMCR3_RNG_OFFSET_1	0x01
+#define LMCR3_RNG_OFFSET_2	0x02
+#define LMCR3_RNG_OFFSET_3	0x03
+
+#define TSTR5_DC_HOLD		(1 << 3)
+
+/************************************************/
+
+#define TARGET_ONHOOK_BATH_x100		4600	/* 46.0 Volt */
+#define TARGET_ONHOOK_BATL_x100		2500	/* 25.0 Volt */
+#define TARGET_V_DIVIDER_RATIO_x100	21376L	/* (R1+R2)/R2 = 213.76 */
+#define DIVIDER_RATIO_ACCURx100		(22 * 100)
+#define V_AD_x10000			10834L	/* VAD = 1.0834 */
+#define TARGET_VDDx100			330	/* VDD = 3.3 * 10 */
+#define VDD_MAX_DIFFx100		20	/* VDD Accur = 0.2*100 */
+
+#define RMS_MULTIPLIERx100		111	/* pi/(2xsqrt(2)) = 1.11*/
+#define K_INTDC_RECT_ON			4	/* When Rectifier is ON this value is necessary(2^4) */
+#define K_INTDC_RECT_OFF		2	/* 2^2 */
+#define RNG_FREQ			25
+#define SAMPLING_FREQ			(2000L)
+#define N_SAMPLES			(SAMPLING_FREQ/RNG_FREQ)     /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
+#define HOOK_THRESH_RING_START_ADDR	0x8B
+#define RING_PARAMS_START_ADDR		0x70
+
+#define V_OUT_BATH_MAX_DIFFx100		300	/* 3.0 x100 */
+#define V_OUT_BATL_MAX_DIFFx100		400	/* 4.0 x100 */
+#define MAX_V_RING_MEANx100		50
+#define TARGET_V_RING_RMSx100		2720
+#define V_RMS_RING_MAX_DIFFx100		250
+
+#define LM_OK_SRC_IRG_2			(1 << 4)
+
+/************************************************/
+
+#define PORTB		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define PORTC		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
+#define PORTD		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
+
+#define _PORTD_SET(mask, state) \
+	do { \
+		if (state) \
+			PORTD |= mask; \
+		else \
+			PORTD &= ~mask; \
+	} while (0)
+
+#define _PORTB_SET(mask, state) \
+	do { \
+		if (state) \
+			PORTB |= mask; \
+		else \
+			PORTB &= ~mask; \
+	} while (0)
+
+#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0)
+#define _PORTB_GET(mask) (!!(PORTB & mask))
+
+#define _PORTC_GET(mask) (!!(PORTC & mask))
+
+/* port B */
+#define SPI_RXD		(1 << (31 - 28))
+#define SPI_TXD		(1 << (31 - 29))
+#define SPI_CLK		(1 << (31 - 30))
+
+/* port C */
+#define COM_HOOK1	(1 << (15 - 9))
+#define COM_HOOK2	(1 << (15 - 10))
+
+#ifndef CONFIG_NETTA_SWAPHOOK
+
+#define COM_HOOK3	(1 << (15 - 11))
+#define COM_HOOK4	(1 << (15 - 12))
+
+#else
+
+#define COM_HOOK3	(1 << (15 - 12))
+#define COM_HOOK4	(1 << (15 - 11))
+
+#endif
+
+/* port D */
+#define SPIENC1		(1 << (15 - 9))
+#define SPIENC2		(1 << (15 - 10))
+#define SPIENC3		(1 << (15 - 11))
+#define SPIENC4		(1 << (15 - 14))
+
+#define SPI_DELAY() udelay(1)
+
+static inline unsigned int __SPI_Transfer(unsigned int tx)
+{
+	unsigned int rx;
+	int b;
+
+	rx = 0; b = 8;
+	while (--b >= 0) {
+		_PORTB_SET(SPI_TXD, tx & 0x80);
+		tx <<= 1;
+		_PORTB_TGL(SPI_CLK);
+		SPI_DELAY();
+		rx <<= 1;
+		rx |= _PORTB_GET(SPI_RXD);
+		_PORTB_TGL(SPI_CLK);
+		SPI_DELAY();
+	}
+
+	return rx;
+}
+
+static const char *codsp_dtmf_map = "D1234567890*#ABC";
+
+static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 };
+static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 };
+
+static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen)
+{
+	unsigned int rx;
+	int i;
+
+	/* just some sanity checks */
+	if (cmd == 0 || cmdlen < 0)
+		return -1;
+
+	_PORTD_SET(spienc_mask_tab[duslic_id], 0);
+
+	/* first 2 bytes are without response */
+	i = 2;
+	while (i-- > 0 && cmdlen-- > 0)
+		__SPI_Transfer(*cmd++);
+
+	while (cmdlen-- > 0) {
+		rx = __SPI_Transfer(*cmd++);
+		if (res != 0 && reslen-- > 0)
+			*res++ = (unsigned char)rx;
+	}
+	if (res != 0) {
+		while (reslen-- > 0)
+			*res++ = __SPI_Transfer(0xFF);
+	}
+
+	_PORTD_SET(spienc_mask_tab[duslic_id], 1);
+
+	return 0;
+}
+
+/****************************************************************************/
+
+void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m)
+{
+	unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m);
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+void codsp_reset_chip(int duslic_id)
+{
+	static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET;
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+void codsp_reset_channel(int duslic_id, int channel)
+{
+	unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH;
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+void codsp_resync_channel(int duslic_id, int channel)
+{
+	unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC;
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+/****************************************************************************/
+
+void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+	cmd[2] = val;
+
+	codsp_send(duslic_id, cmd, 3, 0, 0);
+}
+
+void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
+{
+	unsigned char cmd[4];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char)(val >> 8);
+	cmd[3] = (unsigned char)val;
+
+	codsp_send(duslic_id, cmd, 4, 0, 0);
+}
+
+void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)
+{
+	unsigned char cmd[6];
+
+	cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char)(val >> 24);
+	cmd[3] = (unsigned char)(val >> 16);
+	cmd[4] = (unsigned char)(val >> 8);
+	cmd[5] = (unsigned char)val;
+
+	codsp_send(duslic_id, cmd, 6, 0, 0);
+}
+
+unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno)
+{
+	unsigned char cmd[3];
+	unsigned char res[2];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+
+	codsp_send(duslic_id, cmd, 2, res, 2);
+
+	return res[1];
+}
+
+unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[3];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+
+	codsp_send(duslic_id, cmd, 2, res, 3);
+
+	return ((unsigned short)res[1] << 8) | res[2];
+}
+
+unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[5];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+
+	codsp_send(duslic_id, cmd, 2, res, 5);
+
+	return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4];
+}
+
+/****************************************************************************/
+
+void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block)
+{
+	unsigned char cmd[10];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	memcpy(cmd + 2, block, 8);
+	codsp_send(duslic_id, cmd, 10, 0, 0);
+}
+
+void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	cmd[2] = val;
+	codsp_send(duslic_id, cmd, 3, 0, 0);
+}
+
+void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val)
+{
+	unsigned char cmd[4];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	cmd[2] = (unsigned char)(val >> 8);
+	cmd[3] = (unsigned char)val;
+
+	codsp_send(duslic_id, cmd, 4, 0, 0);
+}
+
+void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block)
+{
+	unsigned char cmd[2];
+	unsigned char res[9];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	codsp_send(duslic_id, cmd, 2, res, 9);
+	memcpy(block, res + 1, 8);
+}
+
+unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr)
+{
+	unsigned char cmd[2];
+	unsigned char res[2];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	codsp_send(duslic_id, cmd, 2, res, 2);
+	return res[1];
+}
+
+unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr)
+{
+	unsigned char cmd[2];
+	unsigned char res[3];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+
+	codsp_send(duslic_id, cmd, 2, res, 3);
+
+	return ((unsigned short)res[1] << 8) | res[2];
+}
+
+/****************************************************************************/
+
+#define MAX_POP_BLOCK	50
+
+void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr,
+			    const unsigned char *block, int len)
+{
+	unsigned char cmd[2 + MAX_POP_BLOCK];
+
+	if (len > MAX_POP_BLOCK)	/* truncate */
+		len = MAX_POP_BLOCK;
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = addr;
+	memcpy (cmd + 2, block, len);
+	codsp_send (duslic_id, cmd, 2 + len, 0, 0);
+}
+
+void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno,
+			   unsigned char val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+	cmd[2] = val;
+
+	codsp_send (duslic_id, cmd, 3, 0, 0);
+}
+
+void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno,
+			    unsigned short val)
+{
+	unsigned char cmd[4];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char) (val >> 8);
+	cmd[3] = (unsigned char) val;
+
+	codsp_send (duslic_id, cmd, 4, 0, 0);
+}
+
+void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno,
+			  unsigned int val)
+{
+	unsigned char cmd[6];
+
+	cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char) (val >> 24);
+	cmd[3] = (unsigned char) (val >> 16);
+	cmd[4] = (unsigned char) (val >> 8);
+	cmd[5] = (unsigned char) val;
+
+	codsp_send (duslic_id, cmd, 6, 0, 0);
+}
+
+unsigned char codsp_read_pop_char (int duslic_id, int channel,
+				   unsigned char regno)
+{
+	unsigned char cmd[3];
+	unsigned char res[2];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+
+	codsp_send (duslic_id, cmd, 2, res, 2);
+
+	return res[1];
+}
+
+unsigned short codsp_read_pop_short (int duslic_id, int channel,
+				     unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[3];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+
+	codsp_send (duslic_id, cmd, 2, res, 3);
+
+	return ((unsigned short) res[1] << 8) | res[2];
+}
+
+unsigned int codsp_read_pop_int (int duslic_id, int channel,
+				 unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[5];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+
+	codsp_send (duslic_id, cmd, 2, res, 5);
+
+	return (((unsigned int) res[1] << 24) |
+		((unsigned int) res[2] << 16) |
+		((unsigned int) res[3] <<  8) |
+		res[4] );
+}
+/****************************************************************************/
+
+struct _coeffs {
+	unsigned char addr;
+	unsigned char values[8];
+};
+
+struct _coeffs ac_coeffs[11] = {
+	{ 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
+	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
+	{ 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter	      */
+	{ 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter	      */
+	{ 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter	      */
+	{ 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter	      */
+	{ 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter	      */
+	{ 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter	      */
+	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
+	{ 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
+	{ 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} }  /* 0x10 TH-Filter part 3 */
+};
+
+struct _coeffs ac_coeffs_0dB[11] = {
+	{ 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} },
+	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} },
+	{ 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} },
+	{ 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} },
+	{ 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} },
+	{ 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} },
+	{ 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} },
+	{ 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} },
+	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} },
+	{ 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} },
+	{ 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} }
+};
+
+struct _coeffs dc_coeffs[9] = {
+	{ 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter     */
+	{ 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing	      */
+	{ 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters	      */
+	{ 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels      */
+	{ 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator   */
+	{ 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX	      */
+	{ 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1	      */
+	{ 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2	      */
+	{ 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} }  /* 0x98 Reserved	      */
+};
+
+void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size)
+{
+	int i;
+
+	for (i = 0; i < tab_size; i++)
+	codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);
+}
+
+#define SS_OPEN_CIRCUIT			0
+#define SS_RING_PAUSE			1
+#define SS_ACTIVE			2
+#define SS_ACTIVE_HIGH			3
+#define SS_ACTIVE_RING			4
+#define SS_RINGING			5
+#define SS_ACTIVE_WITH_METERING		6
+#define SS_ONHOOKTRNSM			7
+#define SS_STANDBY			8
+#define SS_MAX				8
+
+static void codsp_set_slic(int duslic_id, int channel, int state)
+{
+	unsigned char v;
+
+	v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR);
+
+	switch (state) {
+
+		case SS_ACTIVE:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL);
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
+			break;
+
+		case SS_ACTIVE_HIGH:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL));
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
+			break;
+
+		case SS_ACTIVE_RING:
+		case SS_ONHOOKTRNSM:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR);
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
+			break;
+
+		case SS_STANDBY:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR));
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN);
+			break;
+
+		case SS_OPEN_CIRCUIT:
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ);
+			break;
+
+		case SS_RINGING:
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING);
+			break;
+
+		case SS_RING_PAUSE:
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE);
+			break;
+	}
+}
+
+const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 };
+const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 };
+
+void retrieve_slic_state(int slic_id)
+{
+	int duslic_id = slic_id >> 1;
+	int channel = slic_id & 1;
+
+	/* Retrieve the state of the SLICs */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
+
+	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
+	udelay(10000);
+
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
+	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);
+
+	/* Program Default Hook Ring thresholds */
+	codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values);
+
+	/* Now program Hook Threshold while Ring and ac RingTrip to max values */
+	codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values);
+
+	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
+
+	udelay(40000);
+}
+
+int wait_level_metering_finish(int duslic_id, int channel)
+{
+	int cnt;
+
+	for (cnt = 0; cnt < 1000 &&
+		(codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { }
+
+	return cnt != 1000;
+}
+
+int measure_on_hook_voltages(int slic_id, long *vdd,
+		long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v)
+{
+	short LM_Result, Offset_Compensation;	/* Signed 16 bit */
+	long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
+	unsigned char err_mask = 0;
+	int duslic_id = slic_id >> 1;
+	int channel = slic_id & 1;
+	int i;
+
+	/* measure VDD */
+	/* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */
+	codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD);
+
+	/* Activate Test Mode ==> To Enable DC Hold !!! */
+	/* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */
+	/* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	udelay(40000);
+
+	/* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD);
+
+	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
+	udelay(10000);
+
+	/* Now Read the LM Result Registers */
+	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+	VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ;	/* VDDx100 */
+
+	*vdd = VDD;
+
+	VDD_diff = VDD - TARGET_VDDx100;
+
+	if (VDD_diff < 0)
+		VDD_diff = -VDD_diff;
+
+	if (VDD_diff > VDD_MAX_DIFFx100)
+		err_mask |= 1;
+
+	Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100;
+
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */
+
+	udelay(40000);
+
+	codsp_write_sop_char(duslic_id, channel,
+		LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	udelay(40000);
+
+	/* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
+
+	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
+	udelay(10000);
+
+	/* Now Read the LM Result Registers */
+	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+	V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ;  /* Vin x 10000*/
+
+	V_out = (V_in * Divider_Ratio) / 10000L ;	/* Vout x100 */
+
+	*v_oh_H = V_out;
+
+	Vout_diff = V_out - TARGET_ONHOOK_BATH_x100;
+
+	if (Vout_diff < 0)
+		Vout_diff = -Vout_diff;
+
+	if (Vout_diff > V_OUT_BATH_MAX_DIFFx100)
+		err_mask |= 2;
+
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */
+
+	udelay(40000);
+
+	/* Now Read the LM Result Registers */
+	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+
+	V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ;  /* Vin x 10000*/
+
+	V_out = (V_in * Divider_Ratio) / 10000L ;	/* Vout x100 */
+
+	*v_oh_L = V_out;
+
+	Vout_diff = V_out - TARGET_ONHOOK_BATL_x100;
+
+	if (Vout_diff < 0)
+		Vout_diff = -Vout_diff;
+
+	if (Vout_diff > V_OUT_BATL_MAX_DIFFx100)
+		err_mask |= 4;
+
+	/* perform ring tests */
+
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	udelay(40000);
+
+	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE);
+
+	/* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/
+	codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz);
+
+	/* By Default RO1 is selected when ringing RNG-OFFSET = 00 */
+
+	/* Now program Hook Threshold while Ring and ac RingTrip to max values */
+	for(i = 0; i < sizeof(Max_HookRingTh); i++)
+		codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]);
+
+	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
+
+	codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
+
+	/* select source for the levelmeter to be IO4-IO3 */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
+
+	udelay(40000);
+
+	/* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */
+	codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF);
+
+	udelay(10000);
+
+	/* Enable LevelMeter to Integrate only once (Rectifier Disabled) */
+	codsp_write_sop_char(duslic_id, channel,
+			LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+	udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
+
+	if (wait_level_metering_finish(duslic_id, channel)) {
+
+		udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */
+
+		/* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */
+		Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+		Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES);
+
+		/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+		codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
+
+		/* Now programm Integrator Offset Registers !!! */
+		codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
+
+		codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */
+
+		udelay(40000);
+
+		/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
+		codsp_write_sop_char(duslic_id, channel,
+				LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+		udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
+
+		/* Poll the LM_OK bit to see when Integration Result is Ready */
+		if (wait_level_metering_finish(duslic_id, channel)) {
+
+			udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */
+
+			/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
+			/*				    ==>After that Result Regs will be updated every 500us !!!) */
+			LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+			V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ;  /* Vin x 10000*/
+
+			V_out = (V_in * Divider_Ratio) / 10000L ;	/* Vout x100 */
+
+			if (V_out < 0)
+				V_out= -V_out;
+
+			if (V_out > MAX_V_RING_MEANx100)
+				err_mask |= 8;
+
+			*ring_mean_v = V_out;
+		} else {
+			err_mask |= 8;
+			*ring_mean_v = 0;
+		}
+	} else {
+		err_mask |= 8;
+		*ring_mean_v = 0;
+	}
+
+	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
+		LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
+	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
+
+	codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
+
+	/* Now Enable Rectifier */
+	/* select source for the levelmeter to be IO4-IO3 */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR,
+		LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT);
+
+	/* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */
+	codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON);
+
+	udelay(40000);
+
+	/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
+			LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+	udelay(40000);
+
+	/* Poll the LM_OK bit to see when Integration Result is Ready */
+	if (wait_level_metering_finish(duslic_id, channel)) {
+
+		udelay(10000);
+
+		/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
+		/*				    ==>After that Result Regs will be updated every 500us !!!) */
+		Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+		Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES);
+
+		/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+		codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
+
+		/* Now programm Integrator Offset Registers !!! */
+		codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
+
+		/* Be sure that a Ring is generated !!!! */
+		codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */
+
+		udelay(40000);
+
+		/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
+		codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
+				LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+		udelay(40000);
+
+		/* Poll the LM_OK bit to see when Integration Result is Ready */
+		if (wait_level_metering_finish(duslic_id, channel)) {
+
+			udelay(10000);
+
+			/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
+			/*				    ==>After that Result Regs will be updated every 500us !!!) */
+			LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+			V_in = (-1) *  ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ;  /* Vin x 10000*/
+
+			V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ;	/* Vout_RMS x100 */
+			if (V_out < 0)
+				V_out = -V_out;
+
+			Vout_diff = (V_out - TARGET_V_RING_RMSx100);
+
+			if (Vout_diff < 0)
+				Vout_diff = -Vout_diff;
+
+			if (Vout_diff > V_RMS_RING_MAX_DIFFx100)
+				err_mask |= 16;
+
+			*ring_rms_v = V_out;
+		} else {
+			err_mask |= 16;
+			*ring_rms_v = 0;
+		}
+	} else {
+		err_mask |= 16;
+		*ring_rms_v = 0;
+	}
+	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	retrieve_slic_state(slic_id);
+
+	return(err_mask);
+}
+
+int test_dtmf(int slic_id)
+{
+	unsigned char code;
+	unsigned char b;
+	unsigned int intreg;
+	int duslic_id = slic_id >> 1;
+	int channel = slic_id & 1;
+
+	for (code = 0; code < 16; code++) {
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+			(b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
+		udelay(80000);
+
+		intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR);
+		if ((intreg & CODSP_INTREG_INT_CH) == 0)
+			break;
+
+		if ((intreg & CODSP_INTREG_DTMF_OK) == 0 ||
+				codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code])
+			break;
+
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+				b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
+
+		udelay(80000);
+
+		intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */
+	}
+
+	if (code != 16) {
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+				b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
+		return(1);
+	}
+
+	return(0);
+}
+
+void data_up_persist_time(int duslic_id, int channel, int time_ms)
+{
+	unsigned char b;
+
+	b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR);
+	b = (b & 0x0F) | ((time_ms & 0x0F) << 4);
+	codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b);
+}
+
+static void program_dtmf_params(int duslic_id, int channel)
+{
+	unsigned char b;
+
+	codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10);
+	codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB);
+	codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91);
+	codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00);
+	codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00);
+	codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00);
+
+	b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR);
+	codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN);
+}
+
+static void codsp_channel_full_reset(int duslic_id, int channel)
+{
+
+	program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs));
+	program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs));
+
+	/* program basic configuration registers */
+	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01);
+	codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41);
+	codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43);
+	codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00);
+	codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00);
+
+	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04);		/* PG */
+
+	program_dtmf_params(duslic_id, channel);
+
+	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);	/* RingTRip_SEL */
+
+	data_up_persist_time(duslic_id, channel, 4);
+
+	codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF);     /* All interrupts masked */
+
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
+}
+
+static int codsp_chip_full_reset(int duslic_id)
+{
+	int i, cnt;
+	int intreg[NUM_CHANNELS];
+	unsigned char pcm_resync;
+	unsigned char revision;
+
+	codsp_reset_chip(duslic_id);
+
+	udelay(2000);
+
+	for (i = 0; i < NUM_CHANNELS; i++)
+		intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR);
+
+	udelay(1500);
+
+	if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) {
+		printf("_HOOK(%d) stayed low\n", duslic_id);
+		return -1;
+	}
+
+	for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) {
+		if (intreg[i] & CODSP_INTREG_SYNC_FAIL)
+			pcm_resync |= 1 << i;
+	}
+
+	for (cnt = 0; cnt < 5 && pcm_resync; cnt++) {
+		for (i = 0; i < NUM_CHANNELS; i++)
+			codsp_resync_channel(duslic_id, i);
+
+		udelay(2000);
+
+		pcm_resync = 0;
+
+		for (i = 0; i < NUM_CHANNELS; i++) {
+			if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL)
+				pcm_resync |= 1 << i;
+		}
+	}
+
+	if (cnt == 5) {
+		printf("PCM_Resync(%u) not completed\n", duslic_id);
+		return -2;
+	}
+
+	revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR);
+	printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F);
+
+	codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80);	/* EDSP_EN */
+
+	for (i = 0; i < NUM_CHANNELS; i++) {
+		codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01);
+		codsp_channel_full_reset(duslic_id, i);
+	}
+
+	return 0;
+}
+
+int slic_self_test(int duslic_mask)
+{
+	int slic;
+	int i;
+	int r;
+	long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v;
+	const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" };
+	int error = 0;
+
+	for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */
+		if (duslic_mask & (1 << (slic >> 1))) {
+			r = measure_on_hook_voltages(slic, &vdd,
+				&v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);
+
+			printf("SLIC %u measured voltages (x100):\n\t"
+				    "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
+				    slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
+
+			if (r != 0)
+				error |= 1 << slic;
+
+			for (i = 0; i < 5; i++)
+				if (r & (1 << i))
+					printf("\t%s out of range\n", err_txt[i]);
+		}
+	}
+
+	for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */
+		if (duslic_mask & (1 << (slic >> 1))) {
+			printf("SLIC %u VOICE PATH...CHECKING", slic);
+			printf("\rSLIC %u VOICE PATH...%s\n", slic,
+				(r = test_dtmf(slic)) != 0 ? "FAILED  " : "PASSED  ");
+
+			if (r != 0)
+				error |= 1 << slic;
+		}
+	}
+
+	return(error);
+}
+
+#if defined(CONFIG_NETTA_ISDN)
+
+#define SPIENS1		(1 << (31 - 15))
+#define SPIENS2		(1 << (31 - 19))
+
+static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 };
+int s_initialized = 0;
+
+static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value)
+{
+	unsigned int rx, v;
+
+	_PORTB_SET(spiens_mask_tab[s_id], 0);
+
+	rx = __SPI_Transfer(address);
+
+	switch (address & 0xF0) {
+	case 0x60:	/* write byte register */
+	case 0x70:
+		rx = __SPI_Transfer(value);
+		break;
+
+	case 0xE0:	/* read R6 register */
+		v = __SPI_Transfer(0);
+
+		rx = (rx << 8) | v;
+
+		break;
+
+	case 0xF0:	/* read byte register */
+		rx = __SPI_Transfer(0);
+
+		break;
+	}
+
+	_PORTB_SET(spiens_mask_tab[s_id], 1);
+
+	return rx;
+}
+
+static void s_write_BR(int s_id, unsigned int regno, unsigned int val)
+{
+	unsigned int address;
+
+	address = 0x70 | (regno & 15);
+	val &= 0xff;
+
+	(void)s_transfer_internal(s_id, address, val);
+}
+
+static void s_write_OR(int s_id, unsigned int regno, unsigned int val)
+{
+	unsigned int address;
+
+	address = 0x70 | (regno & 15);
+	val &= 0xff;
+
+	(void)s_transfer_internal(s_id, address, val);
+}
+
+static void s_write_NR(int s_id, unsigned int regno, unsigned int val)
+{
+	unsigned int address;
+
+	address = (regno & 7) << 4;
+	val &= 0xf;
+
+	(void)s_transfer_internal(s_id, address | val, 0x00);
+}
+
+#define BR7_IFR			0x08	/* IDL2 free run */
+#define BR7_ICSLSB		0x04	/* IDL2 clock speed LSB */
+
+#define BR15_OVRL_REG_EN	0x80
+#define OR7_D3VR		0x80	/* disable 3V regulator */
+
+#define OR8_TEME		0x10	/* TE mode enable */
+#define OR8_MME			0x08	/* master mode enable */
+
+void s_initialize(void)
+{
+	int s_id;
+
+	for (s_id = 0; s_id < 2; s_id++) {
+		s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB);
+		s_write_BR(s_id, 15, BR15_OVRL_REG_EN);
+		s_write_OR(s_id, 8, OR8_TEME | OR8_MME);
+		s_write_OR(s_id, 7, OR7_D3VR);
+		s_write_OR(s_id, 6, 0);
+		s_write_BR(s_id, 15, 0);
+		s_write_NR(s_id, 3, 0);
+	}
+}
+
+#endif
+
+int board_post_codec(int flags)
+{
+	int j;
+	int r;
+	int duslic_mask;
+
+	printf("board_post_dsp\n");
+
+#if defined(CONFIG_NETTA_ISDN)
+	if (s_initialized == 0) {
+		s_initialize();
+		s_initialized = 1;
+
+		printf("s_initialized\n");
+
+		udelay(20000);
+	}
+#endif
+	duslic_mask = 0;
+
+	for (j = 0; j < MAX_DUSLIC; j++) {
+		if (codsp_chip_full_reset(j) < 0)
+			printf("Error initializing DuSLIC#%d\n", j);
+		else
+			duslic_mask |= 1 << j;
+	}
+
+	if (duslic_mask != 0) {
+		printf("Testing SLICs...\n");
+
+		r = slic_self_test(duslic_mask);
+		for (j = 0; j < MAX_SLICS; j++) {
+			if (duslic_mask & (1 << (j >> 1)))
+				printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK");
+		}
+	}
+	printf("DuSLIC self test finished\n");
+
+	return 0;	/* return -1 on error */
+}
diff --git a/qemu/roms/u-boot/board/netta/dsp.c b/qemu/roms/u-boot/board/netta/dsp.c
new file mode 100644
index 000000000..cd576476e
--- /dev/null
+++ b/qemu/roms/u-boot/board/netta/dsp.c
@@ -0,0 +1,1208 @@
+/*
+ * Intracom TI6711/TI6412 DSP
+ */
+
+#include <common.h>
+#include <post.h>
+
+#include "mpc8xx.h"
+
+struct ram_range {
+	u32 start;
+	u32 size;
+};
+
+#if defined(CONFIG_NETTA_6412)
+
+static const struct ram_range int_ram[] = {
+	{ 0x00000000U, 0x00040000U },
+};
+
+static const struct ram_range ext_ram[] = {
+	{ 0x80000000U, 0x00100000U },
+};
+
+static const struct ram_range ranges[] = {
+	{ 0x00000000U, 0x00040000U },
+	{ 0x80000000U, 0x00100000U },
+};
+
+static inline u16 bit_invert(u16 d)
+{
+	register u8 i;
+	register u16 r;
+	register u16 bit;
+
+	r = 0;
+	for (i = 0; i < 16; i++) {
+		bit = d & (1 << i);
+		if (bit != 0)
+			r |= 1 << (15 - i);
+	}
+	return r;
+}
+
+#else
+
+static const struct ram_range int_ram[] = {
+	{ 0x00000000U, 0x00010000U },
+};
+
+static const struct ram_range ext_ram[] = {
+	{ 0x80000000U, 0x00100000U },
+};
+
+static const struct ram_range ranges[] = {
+	{ 0x00000000U, 0x00010000U },
+	{ 0x80000000U, 0x00100000U },
+};
+
+#endif
+
+/*******************************************************************************************************/
+
+static inline int addr_in_int_ram(u32 addr)
+{
+	int i;
+
+	for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++)
+		if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size)
+			return 1;
+
+	return 0;
+}
+
+static inline int addr_in_ext_ram(u32 addr)
+{
+	int i;
+
+	for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++)
+		if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size)
+			return 1;
+
+	return 0;
+}
+
+/*******************************************************************************************************/
+
+#define DSP_HPIC	0x0
+#define DSP_HPIA	0x4
+#define DSP_HPID1	0x8
+#define DSP_HPID2	0xC
+
+static u32 dummy_delay;
+static volatile u32 *ti6711_delay = &dummy_delay;
+
+static inline void dsp_go_slow(void)
+{
+	volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
+#if defined(CONFIG_NETTA_6412)
+	memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX;
+#else
+	memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX;
+#endif
+	memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX;
+
+	ti6711_delay = (u32 *)DUMMY_BASE;
+}
+
+static inline void dsp_go_fast(void)
+{
+	volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
+#if defined(CONFIG_NETTA_6412)
+	memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
+#else
+	memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK;
+#endif
+	memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
+
+	ti6711_delay = &dummy_delay;
+}
+
+/*******************************************************************************************************/
+
+static inline void dsp_delay(void)
+{
+	/* perform ti6711_delay chip select read to have a small delay */
+	(void) *(volatile u32 *)ti6711_delay;
+}
+
+static inline u16 dsp_read_hpic(void)
+{
+#if defined(CONFIG_NETTA_6412)
+	return bit_invert(*((volatile u16 *)DSP_BASE));
+#else
+	return *((volatile u16 *)DSP_BASE);
+#endif
+}
+
+static inline void dsp_write_hpic(u16 val)
+{
+#if defined(CONFIG_NETTA_6412)
+	*((volatile u16 *)DSP_BASE) = bit_invert(val);
+#else
+	*((volatile u16 *)DSP_BASE) = val;
+#endif
+}
+
+static inline void dsp_reset(void)
+{
+#if defined(CONFIG_NETTA_6412)
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
+	udelay(500);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 15));
+	udelay(500);
+#else
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
+	udelay(250);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 7));
+	udelay(250);
+#endif
+}
+
+static inline u32 dsp_read_hpic_word(u32 addr)
+{
+	u32 val;
+	volatile u16 *p;
+#if defined(CONFIG_NETTA_6412)
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+
+	val = ((u32) bit_invert(p[0]) << 16);
+	/* dsp_delay(); */
+
+	val |= bit_invert(p[1]);
+	/* dsp_delay(); */
+#else
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+
+	val = ((u32) p[0] << 16);
+	dsp_delay();
+
+	val |= p[1];
+	dsp_delay();
+#endif
+	return val;
+}
+
+static inline u16 dsp_read_hpic_hi_hword(u32 addr)
+{
+#if defined(CONFIG_NETTA_6412)
+	return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr));
+#else
+	return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+#endif
+}
+
+static inline u16 dsp_read_hpic_lo_hword(u32 addr)
+{
+#if defined(CONFIG_NETTA_6412)
+	return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2));
+#else
+	return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2);
+#endif
+}
+
+static inline void dsp_wait_hrdy(void)
+{
+	int i;
+
+	i = 0;
+#if defined(CONFIG_NETTA_6412)
+	while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
+#else
+	while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
+#endif
+		dsp_delay();
+		i++;
+	}
+}
+
+static inline void dsp_write_hpic_word(u32 addr, u32 val)
+{
+	volatile u16 *p;
+#if defined(CONFIG_NETTA_6412)
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+	p[0] = bit_invert((u16)(val >> 16));
+	/* dsp_delay(); */
+
+	p[1] = bit_invert((u16)val);
+	/* dsp_delay(); */
+#else
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+	p[0] = (u16)(val >> 16);
+	dsp_delay();
+
+	p[1] = (u16)val;
+	dsp_delay();
+#endif
+}
+
+static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h)
+{
+#if defined(CONFIG_NETTA_6412)
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h);
+#else
+
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h;
+#endif
+}
+
+static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l)
+{
+#if defined(CONFIG_NETTA_6412)
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l);
+#else
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l;
+#endif
+}
+
+/********************************************************************/
+
+static inline void c62_write_word(u32 addr, u32 val)
+{
+	dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+
+	dsp_wait_hrdy();
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16));
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+
+	/* dsp_wait_hrdy();
+	dsp_delay(); */
+#endif
+	dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+}
+
+static u32 c62_read_word(u32 addr)
+{
+	u32 val;
+
+	dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+
+	/* FETCH */
+#if defined(CONFIG_NETTA_6412)
+	dsp_write_hpic_word(DSP_HPIC, 0x00100010);
+#else
+	dsp_write_hpic(0x10);
+	dsp_delay();
+#endif
+	dsp_wait_hrdy();
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16;
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+
+	/* dsp_wait_hrdy();
+	dsp_delay(); */
+#endif
+	val |= dsp_read_hpic_lo_hword(DSP_HPID2);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	return val;
+}
+
+static inline void c62_read(u32 addr, u32 *buffer, int numdata)
+{
+	int i;
+
+	if (numdata <= 0)
+		return;
+
+	for (i = 0; i < numdata; i++) {
+		*buffer++ = c62_read_word(addr);
+		addr += 4;
+	}
+}
+
+static inline u32 c62_checksum(u32 addr, int numdata)
+{
+	int i;
+	u32 chksum;
+
+	chksum = 0;
+	for (i = 0; i < numdata; i++) {
+		chksum += c62_read_word(addr);
+		addr += 4;
+	}
+
+	return chksum;
+}
+
+static inline void c62_write(u32 addr, const u32 *buffer, int numdata)
+{
+	int i;
+
+	if (numdata <= 0)
+		return;
+
+	for (i = 0; i < numdata; i++) {
+		c62_write_word(addr, *buffer++);
+		addr += 4;
+	}
+}
+
+static inline int c62_write_word_validated(u32 addr, u32 val)
+{
+	c62_write_word(addr, val);
+	return c62_read_word(addr) == val ? 0 : -1;
+}
+
+static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata)
+{
+	int i, r;
+
+	if (numdata <= 0)
+		return 0;
+
+	for (i = 0; i < numdata; i++) {
+		r = c62_write_word_validated(addr, *buffer++);
+		if (r < 0)
+			return r;
+		addr += 4;
+	}
+	return 0;
+}
+
+#if defined(CONFIG_NETTA_6412)
+
+#define DRAM_REGS_BASE	0x1800000
+
+#define GBLCTL	DRAM_REGS_BASE
+#define CECTL1	(DRAM_REGS_BASE + 0x4)
+#define CECTL0	(DRAM_REGS_BASE + 0x8)
+#define CECTL2	(DRAM_REGS_BASE + 0x10)
+#define CECTL3	(DRAM_REGS_BASE + 0x14)
+#define SDCTL	(DRAM_REGS_BASE + 0x18)
+#define SDTIM	(DRAM_REGS_BASE + 0x1C)
+#define SDEXT	(DRAM_REGS_BASE + 0x20)
+#define SESEC1	(DRAM_REGS_BASE + 0x44)
+#define SESEC0	(DRAM_REGS_BASE + 0x48)
+#define SESEC2	(DRAM_REGS_BASE + 0x50)
+#define SESEC3	(DRAM_REGS_BASE + 0x54)
+
+#define MAR128	0x1848200
+#define MAR129	0x1848204
+
+void dsp_dram_initialize(void)
+{
+	c62_write_word(GBLCTL, 0x120E4);
+	c62_write_word(CECTL1, 0x18);
+	c62_write_word(CECTL0, 0xD0);
+	c62_write_word(CECTL2, 0x18);
+	c62_write_word(CECTL3, 0x18);
+	c62_write_word(SDCTL, 0x47115000);
+	c62_write_word(SDTIM, 1536);
+	c62_write_word(SDEXT, 0x534A9);
+#if 0
+	c62_write_word(SESEC1, 0);
+	c62_write_word(SESEC0, 0);
+	c62_write_word(SESEC2, 0);
+	c62_write_word(SESEC3, 0);
+#endif
+	c62_write_word(MAR128, 1);
+	c62_write_word(MAR129, 0);
+}
+
+#endif
+
+static inline void dsp_init_hpic(void)
+{
+	int i;
+	volatile u16 *p;
+#if defined(CONFIG_NETTA_6412)
+	dsp_go_fast();
+#else
+	dsp_go_slow();
+#endif
+	i = 0;
+#if defined(CONFIG_NETTA_6412)
+	while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
+#else
+	while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
+#endif
+		dsp_delay();
+		i++;
+	}
+
+	if (i == 1000)
+		printf("HRDY stuck\n");
+
+	dsp_delay();
+
+	/* write control register */
+	p = (volatile u16 *)DSP_BASE;
+	p[0] = 0x0000;
+	dsp_delay();
+	p[1] = 0x0000;
+	dsp_delay();
+
+#if !defined(CONFIG_NETTA_6412)
+	dsp_go_fast();
+#endif
+}
+
+/***********************************************************************************************************/
+
+#if !defined(CONFIG_NETTA_6412)
+
+static const u8 bootstrap_rbin[5084] = {
+	0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00,
+	0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a,
+	0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x03, 0x62,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x30, 0x28,
+	0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x90, 0x00, 0x20, 0x90,
+	0x01, 0x04, 0x2a, 0x58, 0x00, 0x00, 0x60, 0x00, 0xa0, 0x00, 0x0a, 0x10,
+	0x00, 0x00, 0x80, 0x00, 0x02, 0x00, 0x00, 0xfa, 0x02, 0x00, 0xc0, 0x6a,
+	0x02, 0x90, 0x02, 0xe6, 0x03, 0x00, 0x08, 0x2a, 0x00, 0x00, 0x40, 0x00,
+	0x02, 0x94, 0xcd, 0xfa, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x00, 0xf8,
+	0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00,
+	0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74, 0x0f, 0xff, 0xfa, 0x90,
+	0x00, 0x00, 0x80, 0x00, 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb,
+	0x01, 0x80, 0x00, 0xf8, 0x01, 0x90, 0x02, 0xf4, 0x02, 0x60, 0x80, 0x2a,
+	0x02, 0x00, 0xdb, 0xeb, 0x02, 0x00, 0x04, 0x28, 0x02, 0x10, 0x02, 0xf4,
+	0x02, 0x00, 0x22, 0x66, 0x02, 0x60, 0x88, 0x28, 0x02, 0x00, 0xdb, 0xe8,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76, 0x02, 0x80, 0x42, 0x66,
+	0x02, 0x60, 0x8a, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0xc2, 0x66, 0x02, 0x60, 0x92, 0x28,
+	0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76,
+	0x02, 0x80, 0x62, 0x66, 0x02, 0x60, 0x8c, 0x2a, 0x02, 0x00, 0xdb, 0xea,
+	0x00, 0x00, 0x20, 0x00, 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x82, 0x66,
+	0x02, 0x60, 0x8e, 0x28, 0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00,
+	0x02, 0x10, 0x02, 0x76, 0x00, 0x00, 0xa2, 0x64, 0x02, 0x60, 0x90, 0x2a,
+	0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00, 0x00, 0x10, 0x02, 0xf4,
+	0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x01, 0x90, 0x02, 0xf4,
+	0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb, 0x00, 0x00, 0x00, 0xa8,
+	0x00, 0x10, 0x02, 0xf4, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x19, 0x2a, 0x2a,
+	0x02, 0x84, 0x20, 0xfb, 0x02, 0x00, 0x00, 0x6a, 0x02, 0x90, 0x02, 0xf6,
+	0x02, 0x98, 0xe0, 0x2a, 0x02, 0x19, 0x2c, 0x2a, 0x02, 0x00, 0x00, 0x6b,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x29, 0x02, 0x80, 0x00, 0x6a,
+	0x03, 0x94, 0x10, 0x59, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x12, 0xaa,
+	0x00, 0x80, 0x00, 0xa8, 0x04, 0x08, 0x00, 0x28, 0x04, 0x00, 0x00, 0x68,
+	0x20, 0x03, 0xe0, 0x5b, 0x90, 0x14, 0x02, 0x64, 0x20, 0x00, 0x00, 0x12,
+	0x93, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x00, 0x00, 0x03, 0x20, 0x02, 0x65,
+	0x02, 0x19, 0x2a, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x79,
+	0x01, 0xa0, 0x36, 0x65, 0x02, 0x00, 0x00, 0x68, 0x80, 0x87, 0xe0, 0x59,
+	0x90, 0x14, 0x02, 0x75, 0x02, 0x90, 0x01, 0xa0, 0x00, 0x14, 0x02, 0x64,
+	0x00, 0x00, 0x40, 0x00, 0x03, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x60, 0x78,
+	0x00, 0x14, 0x02, 0x74, 0x00, 0x19, 0x2a, 0x28, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x18, 0xe0, 0x29, 0x00, 0x00, 0x02, 0x66, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x00, 0x40, 0x00, 0x31, 0x80, 0x80, 0x59, 0x32, 0x19, 0x2e, 0x2a,
+	0x32, 0x00, 0x00, 0x6a, 0x31, 0x90, 0x02, 0xf4, 0x30, 0x02, 0x9d, 0x41,
+	0x32, 0x19, 0x30, 0x2a, 0x32, 0x00, 0x00, 0x6a, 0x30, 0x10, 0x02, 0xf4,
+	0x30, 0x00, 0x09, 0x12, 0x00, 0x00, 0x80, 0x00, 0x02, 0x80, 0x00, 0xfa,
+	0x02, 0x80, 0xc0, 0x6a, 0x03, 0x14, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a,
+	0x00, 0x00, 0x40, 0x00, 0x02, 0x18, 0x8d, 0xfa, 0x02, 0x14, 0x02, 0xf6,
+	0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64,
+	0x00, 0x00, 0x60, 0x00, 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74,
+	0x0f, 0xff, 0xf9, 0x90, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static int load_bootstrap(void)
+{
+	const u8 *s = bootstrap_rbin;
+	u32 l = sizeof(bootstrap_rbin);
+	const u8 *data, *hdr, *h;
+	u32 chksum, chksum2;
+	int i, j, rangenr;
+	u32 start, length;
+
+	if (l < 12) {
+		printf("bootstrap image corrupted. (too short header)\n");
+		return -1;
+	}
+
+	chksum  = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] <<  8) |  (u32)s[ 7];
+	rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] <<  8) |  (u32)s[11];
+	s += 12; l -= 12;
+
+	hdr = s;
+	s += 8 * rangenr; l -= 8 * rangenr;
+	data = s;
+
+	/* validate bootstrap image */
+	h = hdr; s = data; chksum2 = 0;
+	for (i = 0; i < rangenr; i++) {
+		start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
+		length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
+		h += 8;
+
+		/* too short */
+		if (l < length) {
+			printf("bootstrap image corrupted. (too short data)\n");
+			return -1;
+		}
+		l -= length;
+
+		j = (int)length / 4;
+		while (j-- > 0) {
+			chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] <<  8) |  (u32)s[3];
+			s += 4;
+		}
+	}
+
+	/* checksum must match */
+	if (chksum != chksum2) {
+		printf("bootstrap image corrupted. (checksum error)\n");
+		return -1;
+	}
+
+	/* nothing must be left */
+	if (l != 0) {
+		printf("bootstrap image corrupted. (garbage at the end)\n");
+		return -1;
+	}
+
+	/* write the image */
+	h = hdr;
+	s = data;
+	for (i = 0; i < rangenr; i++) {
+		start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
+		length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
+		h += 8;
+		c62_write(start, (u32 *)s, length / 4);
+		s += length;
+	}
+
+	/* and now validate checksum */
+	h = hdr;
+	s = data;
+	chksum2 = 0;
+	for (i = 0; i < rangenr; i++) {
+		start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
+		length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
+		h += 8;
+		chksum2 += c62_checksum(start, length / 4);
+		s += length;
+	}
+
+	/* checksum must match */
+	if (chksum != chksum2) {
+		printf("bootstrap in DSP memory is corrupted\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+struct host_init {
+	u32 master_mode;
+	struct {
+		u8 port_id;
+		u8 slot_id;
+	} ch_serial_map[32];
+	u32 clk_divider[2];
+	/* pll */
+	u32 initmode;
+	u32 pllm;
+	u32 div[4];
+	u32 oscdiv1;
+	u32 unused[10];
+};
+
+const struct host_init hi_default = {
+	.master_mode	=
+#if !defined(CONFIG_NETTA_ISDN)
+		-1,
+#else
+		0,
+#endif
+
+	.ch_serial_map	= {
+		[ 0]	= { .port_id = 2, .slot_id = 16 },
+		[ 1]	= { .port_id = 2, .slot_id = 17 },
+		[ 2]	= { .port_id = 2, .slot_id = 18 },
+		[ 3]	= { .port_id = 2, .slot_id = 19 },
+		[ 4]	= { .port_id = 2, .slot_id = 20 },
+		[ 5]	= { .port_id = 2, .slot_id = 21 },
+		[ 6]	= { .port_id = 2, .slot_id = 22 },
+		[ 7]	= { .port_id = 2, .slot_id = 23 },
+		[ 8]	= { .port_id = 2, .slot_id = 24 },
+		[ 9]	= { .port_id = 2, .slot_id = 25 },
+		[10]	= { .port_id = 2, .slot_id = 26 },
+		[11]	= { .port_id = 2, .slot_id = 27 },
+		[12]	= { .port_id = 2, .slot_id = 28 },
+		[13]	= { .port_id = 2, .slot_id = 29 },
+		[14]	= { .port_id = 2, .slot_id = 30 },
+		[15]	= { .port_id = 2, .slot_id = 31 },
+	},
+
+	/*
+	   dsp_clk(xin, pllm)         = xin * pllm
+	   serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1)
+	 */
+
+	.clk_divider	= {
+		[0]	= 47,		/* must be 2048Hz */
+		[1]	= 47,
+	},
+
+	.initmode	= 1,
+	.pllm		=
+#if !defined(CONFIG_NETTA_ISDN)
+	8,		/* for =~ 25MHz 8 */
+#else
+	4,
+#endif
+	.div		= {
+		[0]	= 0x8000,
+		[1]	= 0x8000,	/* for =~ 25MHz 0x8000 */
+		[2]	= 0x8001,	/* for =~ 25MHz 0x8001 */
+		[3]	= 0x8001,	/* for =~ 25MHz 0x8001 */
+	},
+
+	.oscdiv1	= 0,
+};
+
+static void hi_write(const struct host_init *hi)
+{
+	u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)];
+	u32 *s;
+	u32 chksum;
+	int i;
+
+	memset(hi_buf, 0, sizeof(hi_buf));
+
+	s = hi_buf;
+	s++;
+	*s++ = hi->master_mode;
+	for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++)
+		*s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) |
+				((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id;
+
+	for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++)
+		*s++ = hi->clk_divider[i];
+
+	*s++ = hi->initmode;
+	*s++ = hi->pllm;
+	for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++)
+		*s++ = hi->div[i];
+	*s++ = hi->oscdiv1;
+
+	chksum = 0;
+	for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++)
+		chksum += hi_buf[i];
+	hi_buf[0] = -chksum;
+
+	c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0]));
+}
+
+static void run_bootstrap(void)
+{
+	dsp_go_slow();
+
+	hi_write(&hi_default);
+
+	/* signal interrupt */
+	dsp_write_hpic(0x0002);
+	dsp_delay();
+
+	dsp_go_fast();
+}
+
+#endif
+
+/***********************************************************************************************************/
+
+int board_post_dsp(int flags)
+{
+	u32 ramS, ramE;
+	u32 data, data2;
+	int i, j, k;
+#if !defined(CONFIG_NETTA_6412)
+	int r;
+#endif
+	dsp_reset();
+	dsp_init_hpic();
+#if !defined(CONFIG_NETTA_6412)
+	dsp_go_slow();
+#endif
+	data = 0x11223344;
+	dsp_write_hpic_word(DSP_HPIA, data);
+	data2 = dsp_read_hpic_word(DSP_HPIA);
+	if (data2 !=   0x11223344) {
+		printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
+		goto err;
+	}
+
+	data = 0xFFEEDDCC;
+	dsp_write_hpic_word(DSP_HPIA, data);
+	data2 = dsp_read_hpic_word(DSP_HPIA);
+	if (data2 != 0xFFEEDDCC) {
+		printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
+		goto err;
+	}
+#if defined(CONFIG_NETTA_6412)
+	dsp_dram_initialize();
+#else
+	r = load_bootstrap();
+	if (r < 0) {
+		printf("BOOTSTRAP: ** ERROR ** failed to load\n");
+		goto err;
+	}
+
+	run_bootstrap();
+
+	dsp_go_fast();
+#endif
+	printf("    ");
+
+	/* test RAMs */
+	for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) {
+
+		ramS = ranges[k].start;
+		ramE = ranges[k].start + ranges[k].size;
+
+		for (j = 0; j < 3; j++) {
+
+			printf("\b\b\b\bR%d.%d", k, j);
+
+			for (i = ramS; i < ramE; i += 4) {
+
+				data = 0;
+				switch (j) {
+					case 0: data = 0xAA55AA55; break;
+					case 1: data = 0x55AA55AA; break;
+					case 2: data = (u32)i;     break;
+				}
+
+				c62_write_word(i, data);
+				data2 = c62_read_word(i);
+				if (data != data2) {
+					printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2);
+					goto err;
+				}
+			}
+		}
+	}
+
+	printf("\b\b\b\b    \b\b\b\bOK\n");
+#if !defined(CONFIG_NETTA_6412)
+	/* XXX assume that this works */
+	load_bootstrap();
+	run_bootstrap();
+	dsp_go_fast();
+#endif
+	return 0;
+
+err:
+	return -1;
+}
+
+int board_dsp_reset(void)
+{
+#if !defined(CONFIG_NETTA_6412)
+	int r;
+#endif
+	dsp_reset();
+	dsp_init_hpic();
+#if defined(CONFIG_NETTA_6412)
+	dsp_dram_initialize();
+#else
+	dsp_go_slow();
+	r = load_bootstrap();
+	if (r < 0)
+		return r;
+
+	run_bootstrap();
+	dsp_go_fast();
+#endif
+	return 0;
+}
diff --git a/qemu/roms/u-boot/board/netta/flash.c b/qemu/roms/u-boot/board/netta/flash.c
new file mode 100644
index 000000000..d6902a693
--- /dev/null
+++ b/qemu/roms/u-boot/board/netta/flash.c
@@ -0,0 +1,492 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR,
+			CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CONFIG_ENV_ADDR_REDUND,
+			CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/qemu/roms/u-boot/board/netta/netta.c b/qemu/roms/u-boot/board/netta/netta.c
new file mode 100644
index 000000000..2c9c6bf6b
--- /dev/null
+++ b/qemu/roms/u-boot/board/netta/netta.c
@@ -0,0 +1,558 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+		unsigned char  reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Intracom NETTA"
+#if defined(CONFIG_NETTA_ISDN)
+			" with ISDN support"
+#endif
+#if defined(CONFIG_NETTA_6412)
+			" (DSP:TI6412)"
+#else
+			" (DSP:TI6711)"
+#endif
+			"\n"
+			);
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define A10_AAAA	0x00000000
+#define A10_AAA0	0x00200000
+#define A10_AAA1	0x00300000
+#define A10_000A	0x00800000
+#define A10_0000	0x00A00000
+#define A10_0001	0x00B00000
+#define A10_111A	0x00C00000
+#define A10_1110	0x00E00000
+#define A10_1111	0x00F00000
+
+#define RAS_0000	0x00000000
+#define RAS_0001	0x00040000
+#define RAS_1110	0x00080000
+#define RAS_1111	0x000C0000
+
+#define CAS_0000	0x00000000
+#define CAS_0001	0x00010000
+#define CAS_1110	0x00020000
+#define CAS_1111	0x00030000
+
+#define WE_0000		0x00000000
+#define WE_0001		0x00004000
+#define WE_1110		0x00008000
+#define WE_1111		0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+/* #define CAS_LATENCY	3 */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 8 */
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+
+	memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mbmr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+	{
+		u32 d1, d2;
+
+		d1 = 0xAA55AA55;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+
+		d1 = 0x55AA55AA;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+#if 0
+	printf("check 0\n");
+	check_ram(( 0 << 20), (2 << 20));
+	printf("check 16\n");
+	check_ram((16 << 20), (2 << 20));
+	printf("check 32\n");
+	check_ram((32 << 20), (2 << 20));
+	printf("check 48\n");
+	check_ram((48 << 20), (2 << 20));
+#endif
+
+	if (size == 0) {
+		printf("SIZE is zero: LOOP on 0\n");
+		for (;;) {
+			*(volatile u32 *)0 = 0;
+			(void)*(volatile u32 *)0;
+		}
+	}
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r(void)
+{
+	return(0);
+}
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
+		if (v == 0xFFFF)
+			continue;
+		fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
+		udelay(10000);
+		fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
+				BMCR_RESET | BMCR_ANENABLE);
+		udelay(10000);
+	}
+}
+
+extern int board_dsp_reset(void);
+
+int last_stage_init(void)
+{
+	int r;
+
+	reset_phys();
+	r = board_dsp_reset();
+	if (r < 0)
+		printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	(_BWR(3) | _BWR(7, 9) | _BW(11))
+#define PA_GP_OUTMASK	(_BW(6) | _BW(10) | _BWR(12, 15))
+#define PA_SP_MASK	(_BWR(0, 2) | _BWR(4, 5))
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(13) | _BWR(14, 15))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	(_B(28) | _B(31))
+#define PB_GP_OUTMASK	(_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
+#define PB_SP_MASK	(_BR(22, 25))
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
+#define PB_SP_DIRVAL	0
+
+#define PC_GP_INMASK	(_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
+#define PC_GP_OUTMASK	(_BW(6) | _BW(12))
+#define PC_SP_MASK	(_BW(4) | _BW(8))
+#define PC_SOVAL	0
+#define PC_INTVAL	_BW(7)
+#define PC_GP_OUTVAL	(_BW(6) | _BW(12))
+#define PC_SP_DIRVAL	0
+
+#define PD_GP_INMASK	0
+#define PD_GP_OUTMASK	_BWR(3, 15)
+#define PD_SP_MASK	0
+
+#if defined(CONFIG_NETTA_6412)
+
+#define PD_GP_OUTVAL	(_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
+
+#else
+
+#define PD_GP_OUTVAL	(_BWR(5, 7) | _BW(9) | _BW(11))
+
+#endif
+
+#define PD_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* CS1: NAND chip select */
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#if !defined(CONFIG_NETTA_6412)
+	/* CS2: DSP */
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
+	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+#else
+	/* CS6: DSP */
+	memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
+	memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+#endif
+	/* CS4: External register chip select */
+	memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
+	memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
+
+	/* CS5: dummy for accurate delay */
+	memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
+	memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	ioport->iop_pddat	= PD_GP_OUTVAL;
+	ioport->iop_pddir	= PD_GP_OUTMASK | PD_SP_DIRVAL;
+	ioport->iop_pdpar	= PD_SP_MASK;
+
+	/* ioport->iop_pddat |=  (1 << (15 - 6)) | (1 << (15 - 7)); */
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_PCMCIA)
+
+int pcmcia_init(void)
+{
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif
diff --git a/qemu/roms/u-boot/board/netta/pcmcia.c b/qemu/roms/u-boot/board/netta/pcmcia.c
new file mode 100644
index 000000000..3fa1925f4
--- /dev/null
+++ b/qemu/roms/u-boot/board/netta/pcmcia.c
@@ -0,0 +1,346 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#undef	CONFIG_PCMCIA
+
+#if defined(CONFIG_CMD_PCMCIA)
+#define	CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define	CONFIG_PCMCIA
+#endif
+
+#ifdef	CONFIG_PCMCIA
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+#define PCMCIA_BOARD_MSG "NETTA"
+
+static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) };
+
+static void cfg_vppd(int no)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
+		return;
+
+	mask = vppd_masks[no];
+
+	immap->im_ioport.iop_papar &= ~mask;
+	immap->im_ioport.iop_paodr &= ~mask;
+	immap->im_ioport.iop_padir |=  mask;
+}
+
+static void set_vppd(int no, int what)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
+		return;
+
+	mask = vppd_masks[no];
+
+	if (what)
+		immap->im_ioport.iop_padat |= mask;
+	else
+		immap->im_ioport.iop_padat &= ~mask;
+}
+
+static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) };
+
+static void cfg_vccd(int no)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
+		return;
+
+	mask = vccd_masks[no];
+
+	immap->im_ioport.iop_papar &= ~mask;
+	immap->im_ioport.iop_paodr &= ~mask;
+	immap->im_ioport.iop_padir |=  mask;
+}
+
+static void set_vccd(int no, int what)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
+		return;
+
+	mask = vccd_masks[no];
+
+	if (what)
+		immap->im_ioport.iop_padat |= mask;
+	else
+		immap->im_ioport.iop_padat &= ~mask;
+}
+
+static const unsigned short oc_mask = _BW(8);
+
+static void cfg_oc(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask = oc_mask;
+
+	immap->im_ioport.iop_pcdir &= ~mask;
+	immap->im_ioport.iop_pcso  &= ~mask;
+	immap->im_ioport.iop_pcint &= ~mask;
+	immap->im_ioport.iop_pcpar &= ~mask;
+}
+
+static int get_oc(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask = oc_mask;
+	int what;
+
+	what = !!(immap->im_ioport.iop_pcdat & mask);;
+	return what;
+}
+
+static const unsigned short shdn_mask = _BW(12);
+
+static void cfg_shdn(void)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	mask = shdn_mask;
+
+	immap->im_ioport.iop_papar &= ~mask;
+	immap->im_ioport.iop_paodr &= ~mask;
+	immap->im_ioport.iop_padir |=  mask;
+}
+
+static void set_shdn(int what)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	unsigned short mask;
+
+	mask = shdn_mask;
+
+	if (what)
+		immap->im_ioport.iop_padat |= mask;
+	else
+		immap->im_ioport.iop_padat &= ~mask;
+}
+
+static void cfg_ports (void)
+{
+	cfg_vppd(0); cfg_vppd(1);	/* VPPD0,VPPD1 VAVPP => Hi-Z */
+	cfg_vccd(0); cfg_vccd(1);	/* 3V and 5V off */
+	cfg_shdn();
+	cfg_oc();
+
+	/*
+	 * Configure Port A for TPS2211 PC-Card Power-Interface Switch
+	 *
+	 * Switch off all voltages, assert shutdown
+	 */
+	set_vppd(0, 1); set_vppd(1, 1);
+	set_vccd(0, 0); set_vccd(1, 0);
+	set_shdn(1);
+
+	udelay(100000);
+}
+
+int pcmcia_hardware_enable(int slot)
+{
+	volatile pcmconf8xx_t	*pcmp;
+	uint reg, pipr, mask;
+	int i;
+
+	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	udelay(10000);
+
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+
+	/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
+	cfg_ports ();
+
+	/* clear interrupt state, and disable interrupts */
+	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
+	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+	/*
+	 * Disable interrupts, DMA, and PCMCIA buffers
+	 * (isolate the interface) and assert RESET signal
+	 */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(500);
+
+	/*
+	* Make sure there is a card in the slot, then configure the interface.
+	*/
+	udelay(10000);
+	debug ("[%d] %s: PIPR(%p)=0x%x\n",
+	       __LINE__,__FUNCTION__,
+	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
+		printf ("   No Card found\n");
+		return (1);
+	}
+
+	/*
+	 * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
+	 */
+	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+	pipr = pcmp->pcmc_pipr;
+	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+	       pipr,
+	       (reg&PCMCIA_VS1(slot))?"n":"ff",
+	       (reg&PCMCIA_VS2(slot))?"n":"ff");
+
+	if ((pipr & mask) == mask) {
+		set_vppd(0, 1); set_vppd(1, 1);		/* VAVPP => Hi-Z */
+		set_vccd(0, 0); set_vccd(1, 1);		/* 5V on, 3V off */
+		puts (" 5.0V card found: ");
+	} else {
+		set_vppd(0, 1); set_vppd(1, 1);		/* VAVPP => Hi-Z */
+		set_vccd(0, 1); set_vccd(1, 0);		/* 5V off, 3V on */
+		puts (" 3.3V card found: ");
+	}
+
+	/*  Wait 500 ms; use this to check for over-current */
+	for (i=0; i<5000; ++i) {
+		if (!get_oc()) {
+			printf ("   *** Overcurrent - Safety shutdown ***\n");
+			set_vccd(0, 0); set_vccd(1, 0);		/* VAVPP => Hi-Z */
+			return (1);
+		}
+		udelay (100);
+	}
+
+	debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	udelay(250000);	/* some cards need >150 ms to come up :-( */
+
+	debug ("# hardware_enable done\n");
+
+	return (0);
+}
+
+
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+	u_long reg;
+
+	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+	/* Configure PCMCIA General Control Register */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = 0;
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+
+	/* All voltages off / Hi-Z */
+	set_vppd(0, 1); set_vppd(1, 1);
+	set_vccd(0, 1); set_vccd(1, 1);
+
+	udelay(10000);
+
+	return (0);
+}
+#endif
+
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+	volatile pcmconf8xx_t	*pcmp;
+	u_long reg;
+
+	debug ("voltage_set: "
+			PCMCIA_BOARD_MSG
+			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	/*
+	 * Disable PCMCIA buffers (isolate the interface)
+	 * and assert RESET signal
+	 */
+	debug ("Disable PCMCIA buffers and assert RESET\n");
+	reg  = PCMCIA_PGCRX(_slot_);
+	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	/*
+	 * Configure Port C pins for
+	 * 5 Volts Enable and 3 Volts enable,
+	 * Turn all power pins to Hi-Z
+	 */
+	debug ("PCMCIA power OFF\n");
+	cfg_ports ();	/* Enables switch, but all in Hi-Z */
+
+	set_vppd(0, 1); set_vppd(1, 1);
+
+	switch(vcc) {
+	case  0:
+		break;	/* Switch off		*/
+
+	case 33:
+		set_vccd(0, 1); set_vccd(1, 0);
+		break;
+
+	case 50:
+		set_vccd(0, 0); set_vccd(1, 1);
+		break;
+
+	default:
+		goto done;
+	}
+
+	/* Checking supported voltages */
+
+	debug ("PIPR: 0x%x --> %s\n",
+	       pcmp->pcmc_pipr,
+	       (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+done:
+			debug ("Enable PCMCIA buffers and stop RESET\n");
+	reg  =  PCMCIA_PGCRX(_slot_);
+	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
+	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
+	PCMCIA_PGCRX(_slot_) = reg;
+	udelay(500);
+
+	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
+	       slot+'A');
+	return (0);
+}
+
+#endif	/* CONFIG_PCMCIA */
diff --git a/qemu/roms/u-boot/board/netta/u-boot.lds b/qemu/roms/u-boot/board/netta/u-boot.lds
new file mode 100644
index 000000000..0dff5a402
--- /dev/null
+++ b/qemu/roms/u-boot/board/netta/u-boot.lds
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .text	:
+  {
+    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}
diff --git a/qemu/roms/u-boot/board/netta/u-boot.lds.debug b/qemu/roms/u-boot/board/netta/u-boot.lds.debug
new file mode 100644
index 000000000..a198cf952
--- /dev/null
+++ b/qemu/roms/u-boot/board/netta/u-boot.lds.debug
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    arch/powerpc/cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib/vsprintf.o	(.text)
+    lib/crc32.o		(.text)
+
+    . = env_offset;
+    common/env_embedded.o(.text)
+
+    *(.text)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}