Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

43 files changed, 0 insertions, 3878 deletions

diff --git a/qemu/roms/u-boot/board/matrix_vision/common/Makefile b/qemu/roms/u-boot/board/matrix_vision/common/Makefile
deleted file mode 100644
index 699da1ca2..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/common/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= mv_common.o
diff --git a/qemu/roms/u-boot/board/matrix_vision/common/mv_common.c b/qemu/roms/u-boot/board/matrix_vision/common/mv_common.c
deleted file mode 100644
index 70133b511..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/common/mv_common.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <environment.h>
-#include <fpga.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_ENV_IS_NOWHERE
-static char* entries_to_keep[] = {
-	"serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
-	"fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
-	"static_ipaddr", "static_netmask", "static_gateway",
-	"syslog", "watchdog", "netboot", "evo8serialnumber" };
-
-#define MV_MAX_ENV_ENTRY_LENGTH	64
-#define MV_KEEP_ENTRIES		ARRAY_SIZE(entries_to_keep)
-
-void mv_reset_environment(void)
-{
-	int i;
-	char *s[MV_KEEP_ENTRIES];
-	char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH];
-
-	printf("\n*** RESET ENVIRONMENT ***\n");
-
-	memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH);
-	for (i = 0; i < MV_KEEP_ENTRIES; i++) {
-		s[i] = getenv(entries_to_keep[i]);
-		if (s[i]) {
-			printf("save '%s' : %s\n", entries_to_keep[i], s[i]);
-			strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH);
-		}
-	}
-
-	gd->env_valid = 0;
-	env_relocate();
-
-	for (i = 0; i < MV_KEEP_ENTRIES; i++) {
-		if (s[i]) {
-			printf("restore '%s' : %s\n", entries_to_keep[i], s[i]);
-			setenv(entries_to_keep[i], s[i]);
-		}
-	}
-
-	saveenv();
-}
-#endif
-
-int mv_load_fpga(void)
-{
-	int result;
-	size_t data_size = 0;
-	void *fpga_data = NULL;
-	char *datastr = getenv("fpgadata");
-	char *sizestr = getenv("fpgadatasize");
-
-	if (getenv("skip_fpga")) {
-		printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
-		return -1;
-	}
-	printf("loading FPGA\n");
-
-	if (datastr)
-		fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
-	if (sizestr)
-		data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
-	if (!data_size) {
-		printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
-		return -1;
-	}
-
-	result = fpga_load(0, fpga_data, data_size);
-	if (!result)
-		bootstage_mark(BOOTSTAGE_ID_START);
-
-	return result;
-}
-
-u8 *dhcp_vendorex_prep(u8 *e)
-{
-	char *ptr;
-
-	/* DHCP vendor-class-identifier = 60 */
-	if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
-		*e++ = 60;
-		*e++ = strlen(ptr);
-		while (*ptr)
-			*e++ = *ptr++;
-	}
-	/* DHCP_CLIENT_IDENTIFIER = 61 */
-	if ((ptr = getenv("dhcp_client_id"))) {
-		*e++ = 61;
-		*e++ = strlen(ptr);
-		while (*ptr)
-			*e++ = *ptr++;
-	}
-
-	return e;
-}
-
-u8 *dhcp_vendorex_proc(u8 *popt)
-{
-	return NULL;
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/common/mv_common.h b/qemu/roms/u-boot/board/matrix_vision/common/mv_common.h
deleted file mode 100644
index 369394356..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/common/mv_common.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright 2008 Matrix Vision GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-extern int mv_load_fpga(void);
-extern void mv_reset_environment(void);
diff --git a/qemu/roms/u-boot/board/matrix_vision/mergerbox/Makefile b/qemu/roms/u-boot/board/matrix_vision/mergerbox/Makefile
deleted file mode 100644
index 11a7fd2c7..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mergerbox/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mergerbox.o pci.o fpga.o sm107.o
diff --git a/qemu/roms/u-boot/board/matrix_vision/mergerbox/README b/qemu/roms/u-boot/board/matrix_vision/mergerbox/README
deleted file mode 100644
index 1994b65be..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mergerbox/README
+++ /dev/null
@@ -1,59 +0,0 @@
-Matrix Vision MergerBox
------------------------
-
-1.	Board Description
-
-	The MergerBox is a 120x160mm single board computing platform
-	for 3D Full-HD digital video processing.
-
-	Power Supply is 10-32VDC.
-
-2	System Components
-
-2.1	CPU
-	Freescale MPC8377 CPU running at 800MHz core and 333MHz csb.
-	256 MByte DDR-II memory @ 333MHz data rate.
-	64 MByte Nor Flash on local bus.
-	1 GByte Nand Flash on FCM.
-	1 Vitesse VSC8601 RGMII ethernet Phys.
-	1 USB host controller over ULPI I/F with 4-Port hub.
-	2 serial ports. Console running on ttyS0 @ 115200 8N1.
-	1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt.
-	2 PCIe x1 busses on local mPCIe and cutom expansion connector.
-	2 SATA host ports.
-	System configuration (HRCW) is taken from I2C EEPROM.
-
-2.2	Graphics
-	SM107 emebedded video controller driving a 5" 800x480 TFT panel.
-	Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory.
-
-2.3	FPGA
-	Altera Cyclone-IV EP4C115 with several PCI DMA engines.
-	Connects to 7x Gennum 3G-SDI transceivers as video interconnect
-	as well as a HDMI v1.4 compliant output for 3D monitoring.
-	Utilizes two more DDR-II controllers providing 256MB memory.
-
-2.4	I2C
-	Bus1:
-		AD7418 @ 0x50 for voltage/temp. monitoring.
-		SX8650 @ 0x90 touch controller for HMI.
-		EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
-	Bus2:
-		mPCIe SMBus
-		SiI9022A @ 0x72/0xC0 HDMI transmitter.
-		TCA6416A @ 0x40 + 0x42 16-Bit I/O expander.
-		LMH1983 @ 0xCA video PLL.
-		DS1338C @ 0xD0 real-time clock with embedded crystal.
-		9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock.
-
-3	Flash layout.
-
-	reset vector is 0x00000100, i.e. low boot.
-
-	00000000	u-boot binary.
-	00100000	FPGA raw bit file.
-	00300000	FIT image holding kernel, dtb and rescue squashfs.
-	03d00000	u-boot environment.
-	03e00000	splash image
-
-	mtd partitions are propagated to linux kernel via device tree blob.
diff --git a/qemu/roms/u-boot/board/matrix_vision/mergerbox/fpga.c b/qemu/roms/u-boot/board/matrix_vision/mergerbox/fpga.c
deleted file mode 100644
index 57552c1ae..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mergerbox/fpga.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2011
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include "mergerbox.h"
-#include "fpga.h"
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
-	fpga_null_fn,
-	fpga_config_fn,
-	fpga_status_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_null_fn,
-	fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
-	Altera_CYC2,
-	passive_serial,
-	Altera_EP2C20_SIZE,
-	(void *) &altera_fns,
-	NULL,
-	0
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mergerbox_init_fpga(void)
-{
-	debug("Initialize FPGA interface\n");
-	fpga_init();
-	fpga_add(fpga_altera, &cyclone2);
-
-	return 1;
-}
-
-int fpga_null_fn(int cookie)
-{
-	return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
-	u32 dvo = gpio->dat;
-
-	dvo &= ~FPGA_CONFIG;
-	gpio->dat = dvo;
-	udelay(5);
-	dvo |= FPGA_CONFIG;
-	gpio->dat = dvo;
-
-	return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
-	int result = 0;
-
-	udelay(10);
-	debug("CONF_DONE check ... ");
-	if (gpio->dat & FPGA_CONF_DONE) {
-		debug("high\n");
-		result = 1;
-	} else
-		debug("low\n");
-
-	return result;
-}
-
-int fpga_status_fn(int cookie)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
-	int result = 0;
-
-	debug("STATUS check ... ");
-	if (gpio->dat & FPGA_STATUS) {
-		debug("high\n");
-		result = 1;
-	} else
-		debug("low\n");
-
-	return result;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
-	u32 dvo = gpio->dat;
-
-	debug("CLOCK %s\n", assert_clk ? "high" : "low");
-	if (assert_clk)
-		dvo |= FPGA_CCLK;
-	else
-		dvo &= ~FPGA_CCLK;
-
-	if (flush)
-		gpio->dat = dvo;
-
-	return assert_clk;
-}
-
-static inline int _write_fpga(u8 val, int dump)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
-	int i;
-	u32 dvo = gpio->dat;
-
-	if (dump)
-		debug("  %02x -> ", val);
-	for (i = 0; i < 8; i++) {
-		dvo &= ~FPGA_CCLK;
-		gpio->dat = dvo;
-		dvo &= ~FPGA_DIN;
-		if (dump)
-			debug("%d ", val&1);
-		if (val & 1)
-			dvo |= FPGA_DIN;
-		gpio->dat = dvo;
-		dvo |= FPGA_CCLK;
-		gpio->dat = dvo;
-		val >>= 1;
-	}
-	if (dump)
-		debug("\n");
-
-	return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
-	unsigned char *data = (unsigned char *) buf;
-	int i;
-
-	debug("fpga_wr: buf %p / size %d\n", buf, len);
-	for (i = 0; i < len; i++)
-		_write_fpga(data[i], 0);
-	debug("\n");
-
-	return FPGA_SUCCESS;
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/mergerbox/fpga.h b/qemu/roms/u-boot/board/matrix_vision/mergerbox/fpga.h
deleted file mode 100644
index dbe9bff25..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mergerbox/fpga.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-extern int mergerbox_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
diff --git a/qemu/roms/u-boot/board/matrix_vision/mergerbox/mergerbox.c b/qemu/roms/u-boot/board/matrix_vision/mergerbox/mergerbox.c
deleted file mode 100644
index 5c891d128..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mergerbox/mergerbox.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <spi.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include <fdt_support.h>
-#include <spd_sdram.h>
-#include "mergerbox.h"
-#include "fpga.h"
-#include "../common/mv_common.h"
-
-static void setup_serdes(void)
-{
-	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
-		FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
-		FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram(void)
-{
-	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
-	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
-	uint *p;
-
-	printf("Testing DRAM from 0x%08x to 0x%08x\n",
-		CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
-
-	printf("DRAM test phase 1:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf("DRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	printf("DRAM test phase 2:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf("DRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	printf("DRAM test passed.\n");
-	return 0;
-}
-#endif
-
-phys_size_t initdram(int board_type)
-{
-	u32 msize;
-
-	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
-
-	/* Enable PCI_CLK[0:1] */
-	clk->occr |= 0xc0000000;
-	udelay(2000);
-
-#if defined(CONFIG_SPD_EEPROM)
-	msize = spd_sdram();
-#else
-	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize_log2;
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	msize_log2 = __ilog2(msize);
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-
-	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-	udelay(50000);
-
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-	udelay(1000);
-
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	udelay(1000);
-
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	__asm__ __volatile__("sync");
-	udelay(1000);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-	udelay(2000);
-#endif
-	setup_serdes();
-
-	return msize << 20;
-}
-
-int checkboard(void)
-{
-	puts("Board: Matrix Vision MergerBox\n");
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u16 dim;
-	int result;
-	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1];
-	unsigned char mac[6], mac_verify[6];
-	char *s = getenv("reset_env");
-
-	for (dim = 10; dim < 180; dim += 5) {
-		mergerbox_tft_dim(dim);
-		udelay(100000);
-	}
-
-	if (s)
-		mv_reset_environment();
-
-	i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac));
-
-	/* check if Matrix Vision prefix present and export to env */
-	if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) {
-		printf("valid MAC found in eeprom: %pM\n", mac);
-		eth_setenv_enetaddr("ethaddr", mac);
-	} else {
-		printf("no valid MAC found in eeprom.\n");
-
-		/* no: check the env */
-		if (!eth_getenv_enetaddr("ethaddr", mac)) {
-			printf("no valid MAC found in env either.\n");
-			/* TODO: ask for valid MAC */
-		} else {
-			printf("valid MAC found in env: %pM\n", mac);
-			printf("updating MAC in eeprom.\n");
-
-			do {
-				result = test_and_clear_bit(20, &gpio->dat);
-				if (result)
-					printf("unprotect EEPROM failed !\n");
-				udelay(20000);
-			} while(result);
-
-			i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6);
-			udelay(20000);
-
-			do {
-				result = test_and_set_bit(20, &gpio->dat);
-				if (result)
-					printf("protect EEPROM failed !\n");
-				udelay(20000);
-			} while(result);
-
-			printf("verify MAC %pM ... ", mac);
-			i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6);
-
-			if (!strncmp((char *)mac, (char *)mac_verify, 6))
-				printf("ok.\n");
-			else
-				/* TODO: retry or do something useful */
-				printf("FAILED (got %pM) !\n", mac_verify);
-		}
-	}
-
-	return 0;
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-	iopd->dat &= ~TFT_SPI_CPLD_CS;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-	iopd->dat |= TFT_SPI_CPLD_CS;
-}
-
-/* control backlight pwm (display brightness).
- * allow values 0-250 with 0 = turn off and 250 = max brightness
- */
-void mergerbox_tft_dim(u16 value)
-{
-	struct spi_slave *slave;
-	u16 din;
-	u16 dout = 0;
-
-	if (value > 0 && value < 250)
-		dout = 0x4000 | value;
-
-	slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH);
-	spi_claim_bus(slave);
-	spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END);
-	spi_release_bus(slave);
-	spi_free_slave(slave);
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
-	ft_pci_setup(blob, bd);
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/mergerbox/mergerbox.h b/qemu/roms/u-boot/board/matrix_vision/mergerbox/mergerbox.h
deleted file mode 100644
index 53eab28f3..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mergerbox/mergerbox.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MERGERBOX_H__
-#define __MERGERBOX_H__
-
-#define MV_GPIO
-
-/*
- * GPIO Bank 1
- */
-#define	TFT_SPI_EN	(0x80000000>>0)
-#define	FPGA_CONFIG	(0x80000000>>1)
-#define	FPGA_STATUS	(0x80000000>>2)
-#define	FPGA_CONF_DONE	(0x80000000>>3)
-#define	FPGA_DIN	(0x80000000>>4)
-#define	FPGA_CCLK	(0x80000000>>5)
-#define	MAN_RST		(0x80000000>>6)
-#define	FPGA_SYS_RST	(0x80000000>>7)
-#define	WD_WDI		(0x80000000>>8)
-#define	TFT_RST		(0x80000000>>9)
-#define	HISCON_GPIO1	(0x80000000>>10)
-#define	HISCON_GPIO2	(0x80000000>>11)
-#define	B2B_GPIO2	(0x80000000>>12)
-#define	CCU_GPIN	(0x80000000>>13)
-#define	CCU_GPOUT	(0x80000000>>14)
-#define	TFT_GPIO0	(0x80000000>>15)
-#define	TFT_GPIO1	(0x80000000>>16)
-#define	TFT_GPIO2	(0x80000000>>17)
-#define	TFT_GPIO3	(0x80000000>>18)
-#define	B2B_GPIO0	(0x80000000>>19)
-#define	B2B_GPIO1	(0x80000000>>20)
-#define	TFT_SPI_CPLD_CS	(0x80000000>>21)
-#define	TFT_SPI_CS	(0x80000000>>22)
-#define	CCU_PWR_EN	(0x80000000>>23)
-#define	B2B_GPIO3	(0x80000000>>24)
-#define	CCU_PWR_STAT	(0x80000000>>25)
-
-#define MV_GPIO1_DAT	(FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS)
-#define MV_GPIO1_OUT	(TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \
-			 TFT_SPI_CPLD_CS)
-#define MV_GPIO1_ODE	(FPGA_CONFIG|MAN_RST)
-
-/*
- * GPIO Bank 2
- */
-#define	SPI_FLASH_WP	(0x80000000>>10)
-#define	SYS_EEPROM_WP	(0x80000000>>11)
-#define	SPI_FLASH_CS	(0x80000000>>22)
-
-#define MV_GPIO2_DAT	(SYS_EEPROM_WP|SPI_FLASH_CS)
-#define MV_GPIO2_OUT	(SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS)
-#define MV_GPIO2_ODE	0
-
-void mergerbox_tft_dim(u16 value);
-
-#endif
diff --git a/qemu/roms/u-boot/board/matrix_vision/mergerbox/pci.c b/qemu/roms/u-boot/board/matrix_vision/mergerbox/pci.c
deleted file mode 100644
index 480f3ed38..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mergerbox/pci.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include "mergerbox.h"
-#include "fpga.h"
-#include "../common/mv_common.h"
-
-static struct pci_region pci_regions[] = {
-	{
-		.bus_start = CONFIG_SYS_PCI_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCI_MEM_PHYS,
-		.size = CONFIG_SYS_PCI_MEM_SIZE,
-		.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		.bus_start = CONFIG_SYS_PCI_MMIO_BASE,
-		.phys_start = CONFIG_SYS_PCI_MMIO_PHYS,
-		.size = CONFIG_SYS_PCI_MMIO_SIZE,
-		.flags = PCI_REGION_MEM
-	},
-	{
-		.bus_start = CONFIG_SYS_PCI_IO_BASE,
-		.phys_start = CONFIG_SYS_PCI_IO_PHYS,
-		.size = CONFIG_SYS_PCI_IO_SIZE,
-		.flags = PCI_REGION_IO
-	}
-};
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static struct pci_region pcie_regions_1[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
-		.size = CONFIG_SYS_PCIE2_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	volatile sysconf83xx_t *sysconf = &immr->sysconf;
-	volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *reg[] = { pci_regions };
-	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-
-	volatile gpio83xx_t *gpio;
-	gpio = (gpio83xx_t *)&immr->gpio[0];
-
-	gpio->dat = MV_GPIO1_DAT;
-	gpio->odr = MV_GPIO1_ODE;
-	gpio->dir = MV_GPIO1_OUT;
-
-	gpio = (gpio83xx_t *)&immr->gpio[1];
-
-	gpio->dat = MV_GPIO2_DAT;
-	gpio->odr = MV_GPIO2_ODE;
-	gpio->dir = MV_GPIO2_OUT;
-
-	printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
-		immr->sysconf.sicrl);
-
-	/* Enable PCI_CLK[0:1] */
-	clk->occr |= 0xc0000000;
-	udelay(2000);
-
-	mergerbox_init_fpga();
-	mv_load_fpga();
-
-	mergerbox_tft_dim(0);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	udelay(2000);
-
-	mpc83xx_pci_init(1, reg);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	out_be32(&sysconf->pecr2, 0xE0008000);
-	udelay(2000);
-
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(2, pcie_reg);
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/mergerbox/sm107.c b/qemu/roms/u-boot/board/matrix_vision/mergerbox/sm107.c
deleted file mode 100644
index d24f92626..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mergerbox/sm107.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <netdev.h>
-#include <sm501.h>
-#include <pci.h>
-#include "../common/mv_common.h"
-
-#ifdef CONFIG_VIDEO
-static const SMI_REGS init_regs_800x480[] = {
-	/* set endianess to little endian */
-	{0x0005c, 0x00000000},
-	/* PCI drive 12mA */
-	{0x00004, 0x42401001},
-	/* current clock */
-	{0x0003c, 0x310a1818},
-	/* clocks for pm0... */
-	{0x00040, 0x0002184f},
-	{0x00044, 0x2a1a0a01},
-	/* GPIO */
-	{0x10008, 0x00000000},
-	{0x1000C, 0x00000000},
-	/* panel control regs */
-	{0x80000, 0x0f017106},
-	{0x80004, 0x0},
-	{0x80008, 0x0},
-	{0x8000C, 0x00000000},
-	{0x80010, 0x0c800c80},
-	/* width 0x320 */
-	{0x80014, 0x03200000},
-	/* height 0x1e0 */
-	{0x80018, 0x01E00000},
-	{0x8001C, 0x0},
-	{0x80020, 0x01df031f},
-	{0x80024, 0x041f031f},
-	{0x80028, 0x00800347},
-	{0x8002C, 0x020c01df},
-	{0x80030, 0x000201e9},
-	{0x80200, 0x00000000},
-	/* ZV[0:7] */
-	{0x00008, 0x00ff0000},
-	/* 24-Bit TFT */
-	{0x0000c, 0x3f000000},
-	{0, 0}
-};
-
-/*
- * Returns SM107 register base address. First thing called in the driver.
- */
-unsigned int board_video_init(void)
-{
-	pci_dev_t devbusfn;
-	u32 addr;
-
-	devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
-	if (devbusfn != -1) {
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1,
-			(u32 *)&addr);
-		return addr & 0xfffffffe;
-	}
-
-	return 0;
-}
-
-/*
- * Called after initializing the SM501 and before clearing the screen.
- */
-void board_validate_screen(unsigned int base)
-{
-}
-
-/*
- * Returns SM107 framebuffer address
- */
-unsigned int board_video_get_fb(void)
-{
-	pci_dev_t devbusfn;
-	u32 addr;
-
-	devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
-	if (devbusfn != -1) {
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
-			(u32 *)&addr);
-		addr &= 0xfffffffe;
-#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
-		addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
-#endif
-		return addr;
-	}
-
-	printf("board_video_get_fb(): FAILED\n");
-
-	return 0;
-}
-
-/*
- * Return a pointer to the initialization sequence.
- */
-const SMI_REGS *board_get_regs(void)
-{
-	return init_regs_800x480;
-}
-
-int board_get_width(void)
-{
-	return 800;
-}
-
-int board_get_height(void)
-{
-	return 480;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/Makefile b/qemu/roms/u-boot/board/matrix_vision/mvbc_p/Makefile
deleted file mode 100644
index 4c1994156..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004-2008
-# Matrix-Vision GmbH, info@matrix-vision.de
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mvbc_p.o fpga.o
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/README.mvbc_p b/qemu/roms/u-boot/board/matrix_vision/mvbc_p/README.mvbc_p
deleted file mode 100644
index a69113755..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/README.mvbc_p
+++ /dev/null
@@ -1,73 +0,0 @@
-Matrix Vision mvBlueCOUGAR-P (mvBC-P)
--------------------------------------
-
-1.	Board Description
-
-	The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera
-	with main focus on GigEVision protocol in combination with local image
-	preprocessing.
-
-	Power Supply is either VDC 48V or Pover over Ethernet (PoE).
-
-2	System Components
-
-2.1	CPU
-	Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
-	64MB SDRAM @ 133MHz.
-	8 MByte Nor Flash on local bus.
-	1 serial ports. Console running on ttyS0 @ 115200 8N1.
-
-2.2	PCI
-	PCI clock fixed at 66MHz. Arbitration inside FPGA.
-	Intel GD82541ER network MAC/PHY and FPGA connected.
-
-2.3	FPGA
-	Altera Cyclone-II EP2C8 with PCI DMA engine.
-	Connects to Matrix Vision specific CCD/CMOS sensor interface.
-	Utilizes 64MB Nand Flash.
-
-2.3.1	I/O @ FPGA
-	2 Outputs : photo coupler
-	2 Inputs  : photo coupler
-
-2.4	I2C
-	LM75 @ 0x90 for temperature monitoring.
-	EEPROM @ 0xA0 for vendor specifics.
-	image sensor interface (slave addresses depend on sensor)
-
-3	Flash layout.
-
-	reset vector is 0x00000100, i.e. "LOWBOOT".
-
-	FF800000	u-boot
-	FF840000	u-boot script image
-	FF850000	redundant u-boot script image
-	FF860000	FPGA raw bit file
-	FF8A0000	tbd.
-	FF900000	root FS
-	FFC00000	kernel
-	FFFC0000	device tree blob
-	FFFD0000	redundant device tree blob
-	FFFE0000	environment
-	FFFF0000	redundant environment
-
-	mtd partitions are propagated to linux kernel via device tree blob.
-
-4	Booting
-
-	On startup the bootscript @ FF840000 is executed. This script can be
-	exchanged easily. Default boot mode is "boot from flash", i.e. system
-	works stand-alone.
-
-	This behaviour depends on some environment variables :
-
-	"netboot" : yes ->try dhcp/bootp and boot from network.
-	A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
-	DHCP server configuration, e.g. to provide different images to
-	different devices.
-
-	During netboot the system tries to get 3 image files:
-	1. Kernel - name + data is given during BOOTP.
-	2. Initrd - name is stored in "initrd_name"
-	3. device tree blob - name is stored in "dtb_name"
-	Fallback files are the flash versions.
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/fpga.c b/qemu/roms/u-boot/board/matrix_vision/mvbc_p/fpga.c
deleted file mode 100644
index b88f43f3e..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/fpga.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include "fpga.h"
-#include "mvbc_p.h"
-
-#ifdef FPGA_DEBUG
-#define fpga_debug(fmt, args...)	printf("%s: "fmt, __func__, ##args)
-#else
-#define fpga_debug(fmt, args...)
-#endif
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
-	fpga_null_fn,
-	fpga_config_fn,
-	fpga_status_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_null_fn,
-	fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
-	Altera_CYC2,
-	passive_serial,
-	Altera_EP2C8_SIZE,
-	(void *) &altera_fns,
-	NULL,
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mvbc_p_init_fpga(void)
-{
-	fpga_debug("Initialize FPGA interface\n");
-	fpga_init();
-	fpga_add(fpga_altera, &cyclone2);
-	fpga_config_fn(0, 1, 0);
-	udelay(60);
-
-	return 1;
-}
-
-int fpga_null_fn(int cookie)
-{
-	return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-	u32 dvo = gpio->simple_dvo;
-
-	fpga_debug("SET config : %s\n", assert ? "low" : "high");
-	if (assert)
-		dvo |= FPGA_CONFIG;
-	else
-		dvo &= ~FPGA_CONFIG;
-
-	if (flush)
-		gpio->simple_dvo = dvo;
-
-	return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-	int result = 0;
-
-	udelay(10);
-	fpga_debug("CONF_DONE check ... ");
-	if (gpio->simple_ival & FPGA_CONF_DONE) {
-		fpga_debug("high\n");
-		result = 1;
-	} else
-		fpga_debug("low\n");
-
-	return result;
-}
-
-int fpga_status_fn(int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-	int result = 0;
-
-	fpga_debug("STATUS check ... ");
-	if (gpio->sint_ival & FPGA_STATUS) {
-		fpga_debug("high\n");
-		result = 1;
-	} else
-		fpga_debug("low\n");
-
-	return result;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-	u32 dvo = gpio->simple_dvo;
-
-	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
-	if (assert_clk)
-		dvo |= FPGA_CCLK;
-	else
-		dvo &= ~FPGA_CCLK;
-
-	if (flush)
-		gpio->simple_dvo = dvo;
-
-	return assert_clk;
-}
-
-static inline int _write_fpga(u8 val)
-{
-	int i;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-	u32 dvo = gpio->simple_dvo;
-
-	for (i=0; i<8; i++) {
-		dvo &= ~FPGA_CCLK;
-		gpio->simple_dvo = dvo;
-		dvo &= ~FPGA_DIN;
-		if (val & 1)
-			dvo |= FPGA_DIN;
-		gpio->simple_dvo = dvo;
-		dvo |= FPGA_CCLK;
-		gpio->simple_dvo = dvo;
-		val >>= 1;
-	}
-
-	return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
-	unsigned char *data = (unsigned char *) buf;
-	int i;
-
-	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
-	for (i = 0; i < len; i++)
-		_write_fpga(data[i]);
-	fpga_debug("\n");
-
-	return FPGA_SUCCESS;
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/fpga.h b/qemu/roms/u-boot/board/matrix_vision/mvbc_p/fpga.h
deleted file mode 100644
index 96d34654c..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/fpga.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-extern int mvbc_p_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/mvbc_p.c b/qemu/roms/u-boot/board/matrix_vision/mvbc_p/mvbc_p.c
deleted file mode 100644
index 8faebeeeb..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/mvbc_p.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2005-2007
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <malloc.h>
-#include <pci.h>
-#include <i2c.h>
-#include <fpga.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include "fpga.h"
-#include "mvbc_p.h"
-#include "../common/mv_common.h"
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_start (int hi_addr)
-{
-	long hi_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
-
-	/* precharge all banks */
-	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
-
-	/* precharge all banks */
-	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
-
-	/* auto refresh */
-	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
-
-	/* set mode register */
-	out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
-}
-
-phys_addr_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-	ulong test1,
-	      test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
-
-	/* setup config registers */
-	out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	if (dramsize > 0)
-		out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1);
-	else
-		out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
-
-	return dramsize;
-}
-
-void mvbc_init_gpio(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	printf("Ports : 0x%08x\n", gpio->port_config);
-	printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
-
-	out_be32(&gpio->simple_ddr, SIMPLE_DDR);
-	out_be32(&gpio->simple_dvo, SIMPLE_DVO);
-	out_be32(&gpio->simple_ode, SIMPLE_ODE);
-	out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
-
-	out_8(&gpio->sint_ode, SINT_ODE);
-	out_8(&gpio->sint_ddr, SINT_DDR);
-	out_8(&gpio->sint_dvo, SINT_DVO);
-	out_8(&gpio->sint_inten, SINT_INTEN);
-	out_be16(&gpio->sint_itype, SINT_ITYPE);
-	out_8(&gpio->sint_gpioe, SINT_GPIOEN);
-
-	out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
-	out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
-	out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
-	out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
-
-	printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
-	printf("sint_gpioe  : 0x%08x\n", gpio->sint_gpioe);
-}
-
-int misc_init_r(void)
-{
-	char *s = getenv("reset_env");
-
-	if (!s) {
-		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
-			return 0;
-		udelay(50000);
-		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
-			return 0;
-		udelay(50000);
-		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
-			return 0;
-	}
-	printf(" === FACTORY RESET ===\n");
-	mv_reset_environment();
-	saveenv();
-
-	return -1;
-}
-
-int checkboard(void)
-{
-	mvbc_init_gpio();
-	printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
-
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
-}
-
-void flash_afterinit(ulong size)
-{
-	out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
-		size));
-	out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
-		size));
-	out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
-		size));
-	out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
-		size));
-}
-
-void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char line = 0xff;
-	char *s = getenv("pci_latency");
-	u32 base;
-	u8 val = 0;
-
-	if (s)
-		val = simple_strtoul(s, NULL, 16);
-
-	if (PCI_BUS(dev) == 0) {
-		switch (PCI_DEV (dev)) {
-		case 0xa: /* FPGA */
-			line = 3;
-			pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
-			printf("found FPGA - enable arbitration\n");
-			writel(0x03, (u32*)(base + 0x80c0));
-			writel(0xf0, (u32*)(base + 0x8080));
-			if (val)
-				pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
-			break;
-		case 0xb: /* LAN */
-			line = 2;
-			if (val)
-				pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
-			break;
-		case 0x1a:
-			break;
-		default:
-			printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
-			break;
-		}
-		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
-	}
-}
-
-struct pci_controller hose = {
-	fixup_irq:pci_mvbc_fixup_irq
-};
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	mvbc_p_init_fpga();
-	mv_load_fpga();
-	pci_mpc5xxx_init(&hose);
-}
-
-void show_boot_progress(int val)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	switch(val) {
-	case BOOTSTAGE_ID_START: /* FPGA ok */
-		setbits_be32(&gpio->simple_dvo, LED_G0);
-		break;
-	case BOOTSTAGE_ID_NET_ETH_INIT:
-		setbits_be32(&gpio->simple_dvo, LED_G1);
-		break;
-	case BOOTSTAGE_ID_COPY_RAMDISK:
-		setbits_be32(&gpio->simple_dvo, LED_Y);
-		break;
-	case BOOTSTAGE_ID_RUN_OS:
-		setbits_be32(&gpio->simple_dvo, LED_R);
-		break;
-	default:
-		break;
-	}
-
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in FEC comes first */
-	return pci_eth_init(bis);
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/mvbc_p.h b/qemu/roms/u-boot/board/matrix_vision/mvbc_p/mvbc_p.h
deleted file mode 100644
index be1542b77..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/mvbc_p.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef __MVBC_H__
-#define __MVBC_H__
-
-#define LED_G0          MPC5XXX_GPIO_SIMPLE_PSC2_0
-#define LED_G1          MPC5XXX_GPIO_SIMPLE_PSC2_1
-#define LED_Y           MPC5XXX_GPIO_SIMPLE_PSC2_2
-#define LED_R           MPC5XXX_GPIO_SIMPLE_PSC2_3
-#define ARB_X_EN        MPC5XXX_GPIO_WKUP_PSC2_4
-
-#define FPGA_DIN        MPC5XXX_GPIO_SIMPLE_PSC3_0
-#define FPGA_CCLK       MPC5XXX_GPIO_SIMPLE_PSC3_1
-#define FPGA_CONF_DONE  MPC5XXX_GPIO_SIMPLE_PSC3_2
-#define FPGA_CONFIG     MPC5XXX_GPIO_SIMPLE_PSC3_3
-#define FPGA_STATUS     MPC5XXX_GPIO_SINT_PSC3_4
-
-#define MAN_RST         MPC5XXX_GPIO_WKUP_PSC6_0
-#define WD_TS           MPC5XXX_GPIO_WKUP_PSC6_1
-#define WD_WDI          MPC5XXX_GPIO_SIMPLE_PSC6_2
-#define COP_PRESENT     MPC5XXX_GPIO_SIMPLE_PSC6_3
-#define FACT_RST        MPC5XXX_GPIO_WKUP_6
-#define FLASH_RBY       MPC5XXX_GPIO_WKUP_7
-
-#define SIMPLE_DDR      (LED_G0 | LED_G1 | LED_Y | LED_R | \
-			 FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
-#define SIMPLE_DVO      (FPGA_CONFIG)
-#define SIMPLE_ODE      (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R)
-#define SIMPLE_GPIOEN   (LED_G0 | LED_G1 | LED_Y | LED_R | \
-			 FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
-			 WD_WDI | COP_PRESENT)
-
-#define SINT_ODE        0
-#define SINT_DDR        0
-#define SINT_DVO        0
-#define SINT_INTEN      0
-#define SINT_ITYPE      0
-#define SINT_GPIOEN     (FPGA_STATUS)
-
-#define WKUP_ODE        (MAN_RST)
-#define WKUP_DIR        (ARB_X_EN|MAN_RST|WD_TS)
-#define WKUP_DO         (ARB_X_EN|MAN_RST|WD_TS)
-#define WKUP_EN         (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
-
-#endif
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/qemu/roms/u-boot/board/matrix_vision/mvbc_p/mvbc_p_autoscript
deleted file mode 100644
index 9b21f30ec..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvbc_p/mvbc_p_autoscript
+++ /dev/null
@@ -1,48 +0,0 @@
-echo
-echo "==== running autoscript ===="
-echo
-setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
-setenv ramkernel setenv kernel_boot \${loadaddr}
-setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
-setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
-setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb
-setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
-setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
-setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
-setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
-if test ${console} = yes;
-then
-setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8
-else
-setenv addcons setenv bootargs \${bootargs} console=tty0
-fi
-setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1
-setenv set_static_ip setenv ipaddr \${static_ipaddr}
-setenv set_static_nm setenv netmask \${static_netmask}
-setenv set_static_gw setenv gatewayip \${static_gateway}
-setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
-setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
-if test ${oprofile} = yes;
-then
-setenv addprofile setenv bootargs \${bootargs} profile=\${profile}
-fi
-if test ${autoscript_boot} != no;
-then
-  if test ${netboot} = yes;
-  then
-    bootp
-    if test $? = 0;
-    then
-      echo "=== bootp succeeded -> netboot ==="
-      run set_ip
-      run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb
-    else
-      echo "=== netboot failed ==="
-    fi
-  fi
-  run set_static_ip set_static_nm set_static_gw set_ip
-  echo "=== bootfromflash ==="
-  run cpdtb rundtb bootfromflash
-else
-  echo "=== boot stopped with autoscript_boot no ==="
-fi
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/.gitignore b/qemu/roms/u-boot/board/matrix_vision/mvblm7/.gitignore
deleted file mode 100644
index 469f1bc4c..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblm7/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-bootscript.img
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/Makefile b/qemu/roms/u-boot/board/matrix_vision/mvblm7/Makefile
deleted file mode 100644
index 9ed2837a7..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblm7/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (C) Freescale Semiconductor, Inc. 2006.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mvblm7.o pci.o fpga.o
-
-extra-y := bootscript.img
-
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-        $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
-MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script
-
-$(obj)/bootscript.img: $(src)/bootscript
-	$(call cmd,mkimage)
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/README.mvblm7 b/qemu/roms/u-boot/board/matrix_vision/mvblm7/README.mvblm7
deleted file mode 100644
index a0686f7fa..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblm7/README.mvblm7
+++ /dev/null
@@ -1,84 +0,0 @@
-Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
--------------------------------------
-
-1.	Board Description
-
-	The mvBL-M7 is a 120x120mm single board computing platform
-	with strong focus on stereo image processing applications.
-
-	Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
-	on any port (requires add-on board).
-
-2	System Components
-
-2.1	CPU
-	Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
-	512MByte DDR-II memory @ 133MHz.
-	8 MByte Nor Flash on local bus.
-	2 Vitesse VSC8601 RGMII ethernet Phys.
-	1 USB host controller over ULPI I/F.
-	2 serial ports. Console running on ttyS0 @ 115200 8N1.
-	1 SD-Card slot connected to SPI.
-	System configuration (HRCW) is taken from I2C EEPROM.
-
-2.2	PCI
-	A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
-
-2.3	FPGA
-	Altera Cyclone-II EP2C20/35 with PCI DMA engines.
-	Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
-	Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.
-
-2.3.1	I/O @ FPGA
-	2x8 Outputs : Infineon High-Side Switches to Main Supply.
-	2x8 Inputs  : Programmable input threshold + trigger capabilities
-	2 dedicated flash interfaces for illuminator boards.
-	Cross trigger for chaining several boards.
-
-2.4	I2C
-	Bus1:
-		MAX5381 DAC @ 0x60 for 1st digital input threshold.
-		LM75 @ 0x90 for temperature monitoring.
-		EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
-		1st image sensor interface (slave addresses depend on sensor)
-	Bus2:
-		MAX5381 DAC @ 0x60 for 2nd digital input threshold.
-		2nd image sensor interface (slave addresses depend on sensor)
-
-3	Flash layout.
-
-	reset vector is 0xFFF00100, i.e. "HIGHBOOT".
-
-	FF800000	environment
-	FF802000	redundant environment
-	FF804000	u-boot script image
-	FF806000	redundant u-boot script image
-	FF808000	device tree blob
-	FF80A000	redundant device tree blob
-	FF80C000	tbd.
-	FF80E000	tbd.
-	FF810000	kernel
-	FFC00000	root FS
-	FFF00000	u-boot
-	FFF80000	FPGA raw bit file
-
-	mtd partitions are propagated to linux kernel via device tree blob.
-
-4	Booting
-
-	On startup the bootscript @ FF804000 is executed. This script can be
-	exchanged easily. Default boot mode is "boot from flash", i.e. system
-	works stand-alone.
-
-	This behaviour depends on some environment variables :
-
-	"netboot" : yes ->try dhcp/bootp and boot from network.
-	A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
-	DHCP server configuration, e.g. to provide different images to
-	different devices.
-
-	During netboot the system tries to get 3 image files:
-	1. Kernel - name + data is given during BOOTP.
-	2. Initrd - name is stored in "initrd_name"
-	3. device tree blob - name is stored in "dtb_name"
-	Fallback files are the flash versions.
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/bootscript b/qemu/roms/u-boot/board/matrix_vision/mvblm7/bootscript
deleted file mode 100644
index dc385fde7..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblm7/bootscript
+++ /dev/null
@@ -1,43 +0,0 @@
-echo
-echo "==== running autoscript ===="
-echo
-setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
-setenv ramkernel setenv kernel_boot \${loadaddr}
-setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
-setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
-setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb
-setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
-setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
-setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
-setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
-if test ${console} = yes;
-then
-setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8
-else
-setenv addcons setenv bootargs \${bootargs} console=tty0
-fi
-setenv set_static_ip setenv ipaddr \${static_ipaddr}
-setenv set_static_nm setenv netmask \${static_netmask}
-setenv set_static_gw setenv gatewayip \${static_gateway}
-setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
-setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
-if test ${autoscript_boot} != no;
-then
-  if test ${netboot} = yes;
-  then
-    bootp
-    if test $? = 0;
-    then
-      echo "=== bootp succeeded -> netboot ==="
-      run set_ip
-      run getdtb rundtb bootfromnet ramparam addcons bootdtb
-    else
-      echo "=== netboot failed ==="
-    fi
-  fi
-  run set_static_ip set_static_nm set_static_gw set_ip
-  echo "=== bootfromflash ==="
-  run cpdtb rundtb bootfromflash
-else
-  echo "=== boot stopped with autoscript_boot no ==="
-fi
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.c b/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.c
deleted file mode 100644
index c0c5bedb2..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include "fpga.h"
-#include "mvblm7.h"
-
-#ifdef FPGA_DEBUG
-#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
-#else
-#define fpga_debug(fmt, args...)
-#endif
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
-	fpga_null_fn,
-	fpga_config_fn,
-	fpga_status_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_null_fn,
-	fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
-	Altera_CYC2,
-	passive_serial,
-	Altera_EP2C20_SIZE,
-	(void *) &altera_fns,
-	NULL,
-	0
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mvblm7_init_fpga(void)
-{
-	fpga_debug("Initialize FPGA interface\n");
-	fpga_init();
-	fpga_add(fpga_altera, &cyclone2);
-	fpga_config_fn(0, 1, 0);
-	udelay(60);
-
-	return 1;
-}
-
-int fpga_null_fn(int cookie)
-{
-	return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-	u32 dvo = gpio->dat;
-
-	fpga_debug("SET config : %s\n", assert ? "low" : "high");
-	if (assert)
-		dvo |= FPGA_CONFIG;
-	else
-		dvo &= ~FPGA_CONFIG;
-
-	if (flush)
-		gpio->dat = dvo;
-
-	return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-	int result = 0;
-
-	udelay(10);
-	fpga_debug("CONF_DONE check ... ");
-	if (gpio->dat & FPGA_CONF_DONE)  {
-		fpga_debug("high\n");
-		result = 1;
-	} else
-		fpga_debug("low\n");
-
-	return result;
-}
-
-int fpga_status_fn(int cookie)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-	int result = 0;
-
-	fpga_debug("STATUS check ... ");
-	if (gpio->dat & FPGA_STATUS)  {
-		fpga_debug("high\n");
-		result = 1;
-	} else
-		fpga_debug("low\n");
-
-	return result;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-	u32 dvo = gpio->dat;
-
-	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
-	if (assert_clk)
-		dvo |= FPGA_CCLK;
-	else
-		dvo &= ~FPGA_CCLK;
-
-	if (flush)
-		gpio->dat = dvo;
-
-	return assert_clk;
-}
-
-static inline int _write_fpga(u8 val, int dump)
-{
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-	int i;
-	u32 dvo = gpio->dat;
-
-	if (dump)
-		fpga_debug("  %02x -> ", val);
-	for (i = 0; i < 8; i++) {
-		dvo &= ~FPGA_CCLK;
-		gpio->dat = dvo;
-		dvo &= ~FPGA_DIN;
-		if (dump)
-			fpga_debug("%d ", val&1);
-		if (val & 1)
-			dvo |= FPGA_DIN;
-		gpio->dat = dvo;
-		dvo |= FPGA_CCLK;
-		gpio->dat = dvo;
-		val >>= 1;
-	}
-	if (dump)
-		fpga_debug("\n");
-
-	return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
-	unsigned char *data = (unsigned char *) buf;
-	int i;
-
-	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
-	for (i = 0; i < len; i++)
-		_write_fpga(data[i], 0);
-	fpga_debug("\n");
-
-	return FPGA_SUCCESS;
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.h b/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.h
deleted file mode 100644
index b480c09b2..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblm7/fpga.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-extern int mvblm7_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.c b/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.c
deleted file mode 100644
index f3c16a3e9..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <pci.h>
-#include <spi.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-#include "../common/mv_common.h"
-#include "mvblm7.h"
-
-int fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = 0;
-	u32 ddr_size;
-	u32 ddr_size_log2;
-	char *s = getenv("ddr_size");
-
-	msize = CONFIG_SYS_DDR_SIZE;
-	if (s) {
-		u32 env_ddr_size = simple_strtoul(s, NULL, 10);
-		if (env_ddr_size == 512)
-			msize = 512;
-	}
-
-	for (ddr_size = msize << 20, ddr_size_log2 = 0;
-	     (ddr_size > 1);
-	     ddr_size = ddr_size >> 1, ddr_size_log2++) {
-		if (ddr_size & 1)
-			return -1;
-	}
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
-		LAWAR_SIZE);
-
-	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-
-	asm("sync;isync");
-	udelay(600);
-
-	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
-	asm("sync;isync");
-	udelay(500);
-
-	return msize;
-}
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = 0;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
-
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-	msize = fixed_sdram();
-
-	/* return total bus RAM size(bytes) */
-	return msize * 1024 * 1024;
-}
-
-int misc_init_r(void)
-{
-	char *s = getenv("reset_env");
-
-	if (s) {
-		mv_reset_environment();
-	}
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: Matrix Vision mvBlueLYNX-M7\n");
-
-	return 0;
-}
-
-#ifdef CONFIG_HARD_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-	iopd->dat &= ~MVBLM7_MMC_CS;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-	iopd->dat |= ~MVBLM7_MMC_CS;
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-}
-
-#endif
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.h b/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.h
deleted file mode 100644
index de9fec7fb..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblm7/mvblm7.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __MVBC_H__
-#define __MVBC_H__
-
-#define MV_GPIO
-
-#define FPGA_CONFIG     0x80000000
-#define FPGA_CCLK       0x40000000
-#define FPGA_DIN        0x20000000
-#define FPGA_STATUS     0x10000000
-#define FPGA_CONF_DONE  0x08000000
-
-#define WD_WDI          0x00400000
-#define WD_TS           0x00200000
-#define MAN_RST         0x00100000
-
-#define MV_GPIO_DAT	(WD_TS)
-#define MV_GPIO_OUT	(FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS)
-#define MV_GPIO_ODE	(FPGA_CONFIG|MAN_RST)
-
-#endif
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblm7/pci.c b/qemu/roms/u-boot/board/matrix_vision/mvblm7/pci.c
deleted file mode 100644
index f14837ad4..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblm7/pci.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#include <pci.h>
-#include <mpc83xx.h>
-#include <fpga.h>
-#include "mvblm7.h"
-#include "fpga.h"
-#include "../common/mv_common.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-void pci_init_board(void)
-{
-	int i;
-	volatile immap_t *immr;
-	volatile pcictrl83xx_t *pci_ctrl;
-	volatile gpio83xx_t *gpio;
-	volatile clk83xx_t *clk;
-	volatile law83xx_t *pci_law;
-	struct pci_region *reg[] = { pci_regions };
-
-	immr = (immap_t *) CONFIG_SYS_IMMR;
-	clk = (clk83xx_t *) &immr->clk;
-	pci_ctrl = immr->pci_ctrl;
-	pci_law = immr->sysconf.pcilaw;
-	gpio  = (volatile gpio83xx_t *)&immr->gpio[0];
-
-	gpio->dat = MV_GPIO_DAT;
-	gpio->odr = MV_GPIO_ODE;
-	gpio->dir = MV_GPIO_OUT;
-
-	printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
-		immr->sysconf.sicrl);
-
-	mvblm7_init_fpga();
-	mv_load_fpga();
-
-	gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
-
-	/* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
-	clk->occr = 0xc0000000;
-
-	pci_ctrl[0].gcr = 0;
-	udelay(2000);
-	pci_ctrl[0].gcr = 1;
-
-	for (i = 0; i < 1000; ++i)
-		udelay(1000);
-
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblx/Makefile b/qemu/roms/u-boot/board/matrix_vision/mvblx/Makefile
deleted file mode 100644
index c056ebaf7..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblx/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mvblx.o fpga.o
-obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
-
-ccflags-y += -Werror
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblx/config.mk b/qemu/roms/u-boot/board/matrix_vision/mvblx/config.mk
deleted file mode 100644
index de13072da..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblx/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
-#
-# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblx/fpga.c b/qemu/roms/u-boot/board/matrix_vision/mvblx/fpga.c
deleted file mode 100644
index 7f9b24550..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblx/fpga.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2011
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include <asm/gpio.h>
-#include <linux/byteorder/generic.h>
-#include "fpga.h"
-
-#ifdef FPGA_DEBUG
-#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
-#else
-#define fpga_debug(fmt, args...)
-#endif
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
-	fpga_null_fn,   /* Altera_pre_fn */
-	fpga_config_fn,
-	fpga_status_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_null_fn,
-	fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
-	Altera_CYC2,
-	fast_passive_parallel,
-	Altera_EP3C5_SIZE,
-	(void *) &altera_fns,
-	NULL,
-	0
-};
-
-#define GPIO_RESET		43
-#define GPIO_DCLK		65
-#define GPIO_nSTATUS	157
-#define GPIO_CONF_DONE	158
-#define GPIO_nCONFIG	159
-#define GPIO_DATA0		54
-#define GPIO_DATA1		55
-#define GPIO_DATA2		56
-#define GPIO_DATA3		57
-#define GPIO_DATA4		58
-#define GPIO_DATA5		60
-#define GPIO_DATA6		61
-#define GPIO_DATA7		62
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* return FPGA_SUCCESS on success, else FPGA_FAIL
- */
-int mvblx_init_fpga(void)
-{
-	fpga_debug("Initializing FPGA interface\n");
-	fpga_init();
-	fpga_add(fpga_altera, &cyclone2);
-
-	if (gpio_request(GPIO_DCLK, "dclk") ||
-			gpio_request(GPIO_nSTATUS, "nStatus") ||
-#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
-			gpio_request(GPIO_CONF_DONE, "conf_done") ||
-#endif
-			gpio_request(GPIO_nCONFIG, "nConfig") ||
-			gpio_request(GPIO_DATA0, "data0") ||
-			gpio_request(GPIO_DATA1, "data1") ||
-			gpio_request(GPIO_DATA2, "data2") ||
-			gpio_request(GPIO_DATA3, "data3") ||
-			gpio_request(GPIO_DATA4, "data4") ||
-			gpio_request(GPIO_DATA5, "data5") ||
-			gpio_request(GPIO_DATA6, "data6") ||
-			gpio_request(GPIO_DATA7, "data7")) {
-		printf("%s: error requesting GPIOs.", __func__);
-		return FPGA_FAIL;
-	}
-
-	/* set up outputs */
-	gpio_direction_output(GPIO_DCLK,  0);
-	gpio_direction_output(GPIO_nCONFIG, 0);
-	gpio_direction_output(GPIO_DATA0, 0);
-	gpio_direction_output(GPIO_DATA1, 0);
-	gpio_direction_output(GPIO_DATA2, 0);
-	gpio_direction_output(GPIO_DATA3, 0);
-	gpio_direction_output(GPIO_DATA4, 0);
-	gpio_direction_output(GPIO_DATA5, 0);
-	gpio_direction_output(GPIO_DATA6, 0);
-	gpio_direction_output(GPIO_DATA7, 0);
-
-	/* NB omap_free_gpio() resets to an input, so we can't
-	 * free ie. nCONFIG, or else the FPGA would reset
-	 * Q: presumably gpio_free() has the same effect?
-	 */
-
-	/* set up inputs */
-	gpio_direction_input(GPIO_nSTATUS);
-#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
-	gpio_direction_input(GPIO_CONF_DONE);
-#endif
-
-	fpga_config_fn(0, 1, 0);
-	udelay(60);
-
-	return FPGA_SUCCESS;
-}
-
-int fpga_null_fn(int cookie)
-{
-	return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
-	fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
-	if (flush) {
-		gpio_set_value(GPIO_nCONFIG, !assert);
-		udelay(1);
-		gpio_set_value(GPIO_nCONFIG, assert);
-	}
-
-	return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
-	int result = 0;
-
-	/* since revA of BLX, we will not get this signal. */
-	udelay(10);
-#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
-	fpga_debug("not waiting for CONF_DONE.");
-	result = 1;
-#else
-	fpga_debug("CONF_DONE check ... ");
-	if (gpio_get_value(GPIO_CONF_DONE))  {
-		fpga_debug("high\n");
-		result = 1;
-	} else
-		fpga_debug("low\n");
-	gpio_free(GPIO_CONF_DONE);
-#endif
-
-	return result;
-}
-
-int fpga_status_fn(int cookie)
-{
-	int result = 0;
-	fpga_debug("STATUS check ... ");
-
-	result = gpio_get_value(GPIO_nSTATUS);
-
-	if (result < 0)
-		fpga_debug("error\n");
-	else if (result > 0)
-		fpga_debug("high\n");
-	else
-		fpga_debug("low\n");
-
-	return result;
-}
-
-static inline int _write_fpga(u8 byte)
-{
-	gpio_set_value(GPIO_DATA0, byte & 0x01);
-	gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
-	gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
-	gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
-	gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
-	gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
-	gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
-	gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
-
-	/* clock */
-	gpio_set_value(GPIO_DCLK, 1);
-	udelay(1);
-	gpio_set_value(GPIO_DCLK, 0);
-	udelay(1);
-
-	return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
-	unsigned char *data = (unsigned char *) buf;
-	int i;
-	int headerlen = len - cyclone2.size;
-
-	if (headerlen < 0)
-		return FPGA_FAIL;
-	else if (headerlen == sizeof(uint32_t)) {
-		const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */
-		char fpgavers_str[fpgavers_len];
-		snprintf(fpgavers_str, fpgavers_len, "0x%08x",
-				be32_to_cpup((uint32_t*)data));
-		setenv("fpgavers", fpgavers_str);
-	}
-
-	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
-	for (i = headerlen; i < len; i++)
-		_write_fpga(data[i]);
-	fpga_debug("-%s\n", __func__);
-
-	return FPGA_SUCCESS;
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblx/fpga.h b/qemu/roms/u-boot/board/matrix_vision/mvblx/fpga.h
deleted file mode 100644
index 411b039c0..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblx/fpga.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-extern int mvblx_init_fpga(void);
-
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblx/mvblx.c b/qemu/roms/u-boot/board/matrix_vision/mvblx/mvblx.c
deleted file mode 100644
index a69359fa1..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblx/mvblx.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * MATRIX VISION GmbH mvBlueLYNX-X
- *
- * Derived from Beagle and Overo
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Sunil Kumar <sunilsaini05@gmail.com>
- *	Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
-#include <asm/mach-types.h>
-#include "mvblx.h"
-#include "fpga.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET)
-static void setup_net_chip(void);
-#endif /* CONFIG_CMD_NET */
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init();	/* in SRAM or SDRAM, finish GPMC */
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
-	printf("mvBlueLYNX-X\n");
-	if (get_cpu_family() == CPU_OMAP36XX)
-		setenv("mpurate", "1000");
-	else
-		setenv("mpurate", "600");
-
-	twl4030_power_init();
-
-#if defined(CONFIG_CMD_NET)
-	setup_net_chip();
-#endif /* CONFIG_CMD_NET */
-
-	mvblx_init_fpga();
-
-	mac_read_from_eeprom();
-
-	dieid_num_r();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_MVBLX();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	omap_mmc_init(0, 0, 0, -1, -1);
-	omap_mmc_init(1, 0, 0, -1, -1);
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_CMD_NET)
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- *		Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
-	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
-	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
-	/* Configure GPMC registers */
-	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
-	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
-	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
-	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
-	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
-	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
-	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
-
-	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
-	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
-	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
-	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
-		&ctrl_base->gpmc_nadv_ale);
-
-	/* Make GPIO 139 as output pin */
-	writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
-
-	/* Now send a pulse on the GPIO pin */
-	writel(GPIO11, &gpio5_base->setdataout);
-	udelay(1);
-	writel(GPIO11, &gpio5_base->cleardataout);
-	udelay(1);
-	writel(GPIO11, &gpio5_base->setdataout);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-	return rc;
-}
-
-int overwrite_console(void)
-{
-	/* return true if console should be overwritten */
-	return 0;
-}
-
-#endif /* CONFIG_CMD_NET */
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblx/mvblx.h b/qemu/roms/u-boot/board/matrix_vision/mvblx/mvblx.h
deleted file mode 100644
index 6c1c752e4..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblx/mvblx.h
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _MVBLX_H_
-#define _MVBLX_H_
-
-#include <asm/arch/sys_proto.h>
-
-const omap3_sysinfo sysinfo = {
-	DDR_DISCRETE,
-	"OMAP3 mvBlueLYNX-X camera",
-	"no NAND",
-};
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_MVBLX() \
- /*SDRC*/\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M4)) /*GPIO_41*/\
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M4)) /*GPIO_42*/\
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M4)) /*GPIO_43*/\
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
-	MUX_VAL(CP(GPMC_NCS3),		(IEN  | PTU | EN  | M4)) /*GPIO54*/\
-	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M4)) /*GPIO55*/\
-	MUX_VAL(CP(GPMC_NCS5),		(IEN  | PTU | EN  | M4)) /*GPIO56*/\
-	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTU | EN  | M4)) /*GPIO57*/\
-	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M4)) /*GPIO58*/\
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IEN  | PTU | EN  | M4)) /*GPIO60*/\
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M4)) /*GPIO61*/\
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTU | EN  | M4)) /*GPIO62*/\
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IDIS  | PTU | EN  | M4)) /*GPIO65*/\
- /*DSS*/\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
- /*CAMERA*/\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
-	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
-	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
-	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
-	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
-	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
-	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
- /*Audio Interface */\
-	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
-	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
-	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
-	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /*Expansion card 1*/\
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
-	MUX_VAL(CP(MMC1_DAT4),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
-	MUX_VAL(CP(MMC1_DAT5),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
-	MUX_VAL(CP(MMC1_DAT6),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
-	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | DIS  | M7)) /*GPIO_129 disabled*/\
- /*Expansion card 2 */\
-	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | DIS  | M0)) /*MMC2_CLK*/\
-	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | DIS  | M0)) /*MMC2_CMD*/\
-	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT0*/\
-	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT1*/\
-	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT2*/\
-	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT3*/\
-	MUX_VAL(CP(MMC2_DAT4),		(IDIS  | PTU | DIS  | M4)) /*GPIO_136*/\
-	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
-	MUX_VAL(CP(MMC2_DAT6),		(IDIS  | PTU | DIS  | M4)) /*GPIO_138*/\
-	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
- /*Bluetooth*/\
-	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
-	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
-	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
-	MUX_VAL(CP(MCBSP3_FSX),		(IDIS | PTD | DIS | M1)) /*UART2_RX*/\
- /*Modem Interface */\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
-	MUX_VAL(CP(UART1_CTS),		(IEN | PTU | EN | M4)) /*GPIO_150*/ \
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
-	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
-	MUX_VAL(CP(MCBSP1_FSR),		(IEN | PTU | EN  | M4)) /*GPIO_157*/\
-	MUX_VAL(CP(MCBSP1_DX),		(IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
-	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
-	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
-	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
-	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
- /*Serial Interface*/\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
-	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
-	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
-	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
-	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
-	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
-	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
-	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
-	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
-	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
-	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
-	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
-	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
-	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
-	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
-	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
-	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
-	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
-	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
-	MUX_VAL(CP(MCSPI1_CLK),		(IDIS  | PTU | DIS  | M4)) /*GPIO_171*/\
-	MUX_VAL(CP(MCSPI1_SIMO),	(IDIS  | PTU | DIS  | M4)) /*GPIO_172*/\
-	MUX_VAL(CP(MCSPI1_SOMI),	(IDIS  | PTU | DIS  | M4)) /*GPIO_173*/\
-	MUX_VAL(CP(MCSPI1_CS0),		(IDIS  | PTD | DIS  | M4)) /*GPIO_174*/\
-	MUX_VAL(CP(MCSPI1_CS3),		(IDIS  | PTU | DIS | M4)) /*GPIO_177*/\
- /* USB EHCI (port 2) not used */\
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI2_CLK*/\
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI2_SIMO*/\
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI2_SOMI*/\
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS0*/\
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS1*/\
- /*Control and debug */\
-	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
-	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
-	MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
-	MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M0)) /*GPIO_4*/\
-	MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
-	MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
-	MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
-	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
-	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS  | PTD | DIS | M4)) /*GPIO_10*/\
-	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTD | DIS  | M0)) /*SYS_CLKOUT2*/\
- /* USB EHCI (port 1) */\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
-	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
-	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
-	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
-	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
-	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
-	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
-	MUX_VAL(CP(ETK_D10_ES2),	(IEN | PTU | EN | M4)) /*GPIO_24*/\
-	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M4)) /*GPIO_25*/\
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_26*/\
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_27*/\
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_28*/\
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_29*/\
- /*Die to Die */\
-	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
-	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
-	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
-	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
-	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
-	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
-	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
-	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
-	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
-	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
-	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
-	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
-	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
-	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
-	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
-	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
-	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
-	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
-	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
-	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
-	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
-	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
-	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
-	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
-	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
-	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
-	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
-	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
-	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
-	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
-	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
-	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
-	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
-	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
-	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
-	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
-	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
-	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
-	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
-	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
-	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
-	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
-	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
-	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
-	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
-	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
-	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
-	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
-	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
-	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
-	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
-	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
-	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
-	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
-	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
-	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
-	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
-	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
-	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
-	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
-	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
-	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
-	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
-	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
-	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
-
-#endif
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvblx/sys_eeprom.c b/qemu/roms/u-boot/board/matrix_vision/mvblx/sys_eeprom.c
deleted file mode 100644
index 1a2ac8d6c..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvblx/sys_eeprom.c
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
- * York Sun (yorksun@freescale.com)
- * Haiying Wang (haiying.wang@freescale.com)
- * Timur Tabi (timur@freescale.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-
-/* #define DEBUG */
-
-/*
- * static eeprom: EEPROM layout
- */
-static struct __attribute__ ((__packed__)) eeprom {
-	u8 id[16];		/* 0x01 - 0x0F Type e.g. 100wG-5111 */
-	u8 sn[10];		/* 0x10 - 0x19 Serial Number */
-	u8 date[6];		/* 0x1A - 0x1F Build Date */
-	u8 mac[6];		/* 0x20 - 0x25 MAC address  */
-	u8 reserved[10];/* 0x26 - 0x2f reserved */
-	u32 crc;        /* x+1         CRC32 checksum */
-} e;
-
-/* Set to 1 if we've read EEPROM into memory */
-static int has_been_read;
-
-/**
- * show_eeprom - display the contents of the EEPROM
- */
-static void show_eeprom(void)
-{
-	unsigned int crc;
-	char safe_string[16];
-
-#ifdef DEBUG
-	int i;
-#endif
-	u8 *p;
-
-	/* ID */
-	strncpy(safe_string, (char *)e.id, sizeof(e.id));
-	safe_string[sizeof(e.id)-1] = 0;
-	printf("ID: mvBlueLYNX-X%s\n", safe_string);
-
-	/* Serial number */
-	strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
-	safe_string[sizeof(e.sn)-1] = 0;
-	printf("SN: %s\n", safe_string);
-
-	/* Build date, BCD date values, as YYMMDDhhmmss */
-	printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
-		e.date[0], e.date[1], e.date[2],
-		e.date[3] & 0x7F, e.date[4], e.date[5],
-		e.date[3] & 0x80 ? "PM" : "");
-
-	/* Show MAC address  */
-	p = e.mac;
-	printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
-		p[0], p[1], p[2], p[3],	p[4], p[5]);
-
-	crc = crc32(0, (void *)&e, sizeof(e) - 4);
-
-	if (crc == be32_to_cpu(e.crc))
-		printf("CRC: %08x\n", be32_to_cpu(e.crc));
-	else
-		printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
-
-#ifdef DEBUG
-	printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
-	for (i = 0; i < sizeof(e); i++) {
-		if ((i % 16) == 0)
-			printf("%02X: ", i);
-		printf("%02X ", ((u8 *)&e)[i]);
-		if (((i % 16) == 15) || (i == sizeof(e) - 1))
-			printf("\n");
-	}
-#endif
-}
-
-/**
- * read_eeprom - read the EEPROM into memory
- */
-static int read_eeprom(void)
-{
-	int ret;
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	unsigned int bus;
-#endif
-
-	if (has_been_read)
-		return 0;
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	bus = i2c_get_bus_num();
-	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
-
-	ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
-		(uchar *)&e, sizeof(e));
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	i2c_set_bus_num(bus);
-#endif
-
-#ifdef DEBUG
-	show_eeprom();
-#endif
-
-	has_been_read = (ret == 0) ? 1 : 0;
-
-	return ret;
-}
-
-/**
- *  update_crc - update the CRC
- *
- *  This function should be called after each update to the EEPROM structure,
- *  to make sure the CRC is always correct.
- */
-static void update_crc(void)
-{
-	u32 crc;
-
-	crc = crc32(0, (void *)&e, sizeof(e) - 4);
-	e.crc = cpu_to_be32(crc);
-}
-
-/**
- * prog_eeprom - write the EEPROM from memory
- */
-static int prog_eeprom(void)
-{
-	int ret = 0;
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	unsigned int bus;
-#endif
-
-	update_crc();
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	bus = i2c_get_bus_num();
-	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
-
-	ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
-		(uchar *)&e, sizeof(e));
-
-	if (!ret) {
-		/* Verify the write by reading back the EEPROM and comparing */
-		struct eeprom e2;
-#ifdef DEBUG
-		printf("%s verifying...\n", __func__);
-#endif
-		ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
-			(uchar *)&e2, sizeof(e2));
-
-		if (!ret && memcmp(&e, &e2, sizeof(e)))
-			ret = -1;
-	}
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	i2c_set_bus_num(bus);
-#endif
-
-	if (ret) {
-		printf("Programming failed.\n");
-		has_been_read = 0;
-		return -1;
-	}
-
-	printf("Programming passed.\n");
-	return 0;
-}
-
-/**
- * h2i - converts hex character into a number
- *
- * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
- * the integer equivalent.
- */
-static inline u8 h2i(char p)
-{
-	if ((p >= '0') && (p <= '9'))
-		return p - '0';
-
-	if ((p >= 'A') && (p <= 'F'))
-		return (p - 'A') + 10;
-
-	if ((p >= 'a') && (p <= 'f'))
-		return (p - 'a') + 10;
-
-	return 0;
-}
-
-/**
- * set_date - stores the build date into the EEPROM
- *
- * This function takes a pointer to a string in the format "YYMMDDhhmmss"
- * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
- * and stores it in the build date field of the EEPROM local copy.
- */
-static void set_date(const char *string)
-{
-	unsigned int i;
-
-	if (strlen(string) != 12) {
-		printf("Usage: mac date YYMMDDhhmmss\n");
-		return;
-	}
-
-	for (i = 0; i < 6; i++)
-		e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
-
-	update_crc();
-}
-
-/**
- * set_mac_address - stores a MAC address into the EEPROM
- *
- * This function takes a pointer to MAC address string
- * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
- * stores it in the MAC address field in the EEPROM local copy.
- */
-static void set_mac_address(const char *string)
-{
-	char *p = (char *) string;
-	unsigned int i;
-
-	for (i = 0; *p && (i < 6); i++) {
-		e.mac[i] = simple_strtoul(p, &p, 16);
-		if (*p == ':')
-			p++;
-	}
-
-	update_crc();
-}
-
-int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	char cmd;
-
-	if (argc == 1) {
-		show_eeprom();
-		return 0;
-	}
-
-	cmd = argv[1][0];
-
-	if (cmd == 'r') {
-#ifdef DEBUG
-		printf("%s read\n", __func__);
-#endif
-		read_eeprom();
-		return 0;
-	}
-
-	if (argc == 2) {
-		switch (cmd) {
-		case 's':	/* save */
-#ifdef DEBUG
-			printf("%s save\n", __func__);
-#endif
-			prog_eeprom();
-			break;
-		default:
-			return cmd_usage(cmdtp);
-		}
-
-		return 0;
-	}
-
-	/* We know we have at least one parameter  */
-
-	switch (cmd) {
-	case 'n':	/* serial number */
-#ifdef DEBUG
-		printf("%s serial number\n", __func__);
-#endif
-		memset(e.sn, 0, sizeof(e.sn));
-		strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
-		update_crc();
-		break;
-	case 'd':	/* date BCD format YYMMDDhhmmss */
-		set_date(argv[2]);
-		break;
-	case 'e':	/* errata */
-		printf("mac errata not implemented\n");
-		break;
-	case 'i':	/* id */
-		memset(e.id, 0, sizeof(e.id));
-		strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
-		update_crc();
-		break;
-	case 'p':	/* ports */
-		printf("mac ports not implemented (always 1 port)\n");
-		break;
-	case '0' ... '9':
-		/* we only have "mac 0" but any digit can be used here */
-		set_mac_address(argv[2]);
-		break;
-	case 'h':	/* help */
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	return 0;
-}
-
-static inline int is_portrait(void)
-{
-	int i;
-	unsigned int orient_index = 0; /* idx of char which determines orientation */
-
-	for (i = sizeof(e.id)/sizeof(*e.id) - 1; i>=0; i--) {
-		if (e.id[i] == '-') {
-			orient_index = i+1;
-			break;
-		}
-	}
-
-	return (orient_index &&
-			(e.id[orient_index] >= '5') && (e.id[orient_index] <= '8'));
-}
-
-int mac_read_from_eeprom(void)
-{
-	u32 crc, crc_offset = offsetof(struct eeprom, crc);
-	u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
-#define FILENAME_LANDSCAPE "mvBlueLynx_X.rbf"
-#define FILENAME_PORTRAIT "mvBlueLynx_X_sensor_cd.rbf"
-
-	if (read_eeprom()) {
-		printf("EEPROM Read failed.\n");
-		return -1;
-	}
-
-	crc = crc32(0, (void *)&e, crc_offset);
-	crcp = (void *)&e + crc_offset;
-	if (crc != be32_to_cpu(*crcp)) {
-		printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
-			be32_to_cpu(e.crc));
-		return -1;
-	}
-
-	if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
-		memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
-		char ethaddr[9];
-
-		sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
-			e.mac[0],
-			e.mac[1],
-			e.mac[2],
-			e.mac[3],
-			e.mac[4],
-			e.mac[5]);
-		/* Only initialize environment variables that are blank
-		 * (i.e. have not yet been set)
-		 */
-		if (!getenv("ethaddr"))
-			setenv("ethaddr", ethaddr);
-	}
-
-	if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) &&
-		memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
-		char serial_num[12];
-
-		strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
-		/* Only initialize environment variables that are blank
-		 * (i.e. have not yet been set)
-		 */
-		if (!getenv("serial#"))
-			setenv("serial#", serial_num);
-	}
-
-	/* decide which fpga file to load depending on orientation */
-	if (is_portrait())
-		setenv("fpgafilename", FILENAME_PORTRAIT);
-	else
-		setenv("fpgafilename", FILENAME_LANDSCAPE);
-
-	/* TODO should I calculate CRC here? */
-	return 0;
-}
-
-#ifdef CONFIG_SERIAL_TAG
-void get_board_serial(struct tag_serialnr *serialnr)
-{
-	char *serial = getenv("serial#");
-
-	if (serial && (strlen(serial) > 3)) {
-		/* use the numerical part of the serial number LXnnnnnn */
-		serialnr->high = 0;
-		serialnr->low = simple_strtoul(serial + 2, NULL, 10);
-	} else {
-		serialnr->high = 0;
-		serialnr->low = 0;
-	}
-}
-#endif
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvsmr/.gitignore b/qemu/roms/u-boot/board/matrix_vision/mvsmr/.gitignore
deleted file mode 100644
index 469f1bc4c..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvsmr/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-bootscript.img
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvsmr/Makefile b/qemu/roms/u-boot/board/matrix_vision/mvsmr/Makefile
deleted file mode 100644
index a9c794e21..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvsmr/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004-2008
-# Matrix-Vision GmbH, info@matrix-vision.de
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mvsmr.o fpga.o
-
-extra-y := bootscript.img
-
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-        $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
-MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script
-
-$(obj)/bootscript.img: $(src)/bootscript
-	$(call cmd,mkimage)
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvsmr/README.mvsmr b/qemu/roms/u-boot/board/matrix_vision/mvsmr/README.mvsmr
deleted file mode 100644
index 8e34cb783..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvsmr/README.mvsmr
+++ /dev/null
@@ -1,55 +0,0 @@
-Matrix Vision mvSMR
--------------------
-
-1.	Board Description
-
-	The mvSMR is a 75x130mm single image processing board used
-	in automation. Power Supply is 24VDC.
-
-2	System Components
-
-2.1	CPU
-	Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
-	64MB DDR-I @ 133MHz.
-	8 MByte Nor Flash on local bus.
-	2 serial ports. Console running on ttyS0 @ 115200 8N1.
-
-2.2	PCI
-	PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
-
-2.3	FPGA
-	Xilinx Spartan-3 XC3S200 with PCI DMA engine.
-	Connects to Matrix Vision specific CCD/CMOS sensor interface.
-
-2.4	I2C
-	EEPROM @ 0xA0 for vendor specifics.
-	image sensor interface (slave addresses depend on sensor)
-
-3	Flash layout.
-
-	reset vector is 0x00000100, i.e. "LOWBOOT".
-
-	FF800000	u-boot
-	FF806000	u-boot script image
-	FF808000	u-boot environment
-	FF840000	FPGA raw bit file
-	FF880000	root FS
-	FFF00000	kernel
-
-4	Booting
-
-	On startup the bootscript @ FF806000 is executed. This script can be
-	exchanged easily. Default boot mode is "boot from flash", i.e. system
-	works stand-alone.
-
-	This behaviour depends on some environment variables :
-
-	"netboot" : yes ->try dhcp/bootp and boot from network.
-	A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
-	DHCP server configuration, e.g. to provide different images to
-	different devices.
-
-	During netboot the system tries to get 3 image files:
-	1. Kernel - name + data is given during BOOTP.
-	2. Initrd - name is stored in "initrd_name"
-	Fallback files are the flash versions.
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvsmr/bootscript b/qemu/roms/u-boot/board/matrix_vision/mvsmr/bootscript
deleted file mode 100644
index 02c802c8c..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvsmr/bootscript
+++ /dev/null
@@ -1,42 +0,0 @@
-echo
-echo "==== running autoscript ===="
-echo
-setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
-setenv ramkernel 'setenv kernel_boot ${loadaddr}'
-setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
-setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
-setenv bootfromflash run flashkernel cpird addcons boot24
-setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
-if test ${console} = yes;
-then
-setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
-else
-setenv addcons 'setenv bootargs ${bootargs} console=tty0'
-fi
-setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
-setenv set_static_nm 'setenv netmask ${static_netmask}'
-setenv set_static_gw 'setenv gatewayip ${static_gateway}'
-setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
-if test ${servicemode} != yes;
-then
-  echo "=== forced flash mode ==="
-  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
-fi
-if test ${autoscript_boot} != no;
-then
-  if test ${netboot} = yes;
-  then
-    bootp
-    if test $? = 0;
-    then
-      echo "=== bootp succeeded -> netboot ==="
-      run set_ip bootfromnet addcons boot24
-    else
-      echo "=== netboot failed ==="
-    fi
-  fi
-  echo "=== bootfromflash ==="
-  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
-else
-  echo "=== boot stopped with autoscript_boot no ==="
-fi
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvsmr/fpga.c b/qemu/roms/u-boot/board/matrix_vision/mvsmr/fpga.c
deleted file mode 100644
index 518992578..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvsmr/fpga.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2010
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <spartan3.h>
-#include <command.h>
-#include <asm/io.h>
-#include "fpga.h"
-#include "mvsmr.h"
-
-xilinx_spartan3_slave_serial_fns fpga_fns = {
-	fpga_pre_config_fn,
-	fpga_pgm_fn,
-	fpga_clk_fn,
-	fpga_init_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	0
-};
-
-xilinx_desc spartan3 = {
-	xilinx_spartan2,
-	slave_serial,
-	XILINX_XC3S200_SIZE,
-	(void *) &fpga_fns,
-	0,
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mvsmr_init_fpga(void)
-{
-	fpga_init();
-	fpga_add(fpga_xilinx, &spartan3);
-
-	return 1;
-}
-
-int fpga_init_fn(int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
-		return 0;
-
-	return 1;
-}
-
-int fpga_done_fn(int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	int result = 0;
-
-	udelay(10);
-	if (in_be32(&gpio->simple_ival) & FPGA_DONE)
-		result = 1;
-
-	return result;
-}
-
-int fpga_pgm_fn(int assert, int flush, int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (!assert)
-		setbits_8(&gpio->sint_dvo, FPGA_STATUS);
-	else
-		clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
-
-	return assert;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (assert_clk)
-		setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
-	else
-		clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
-
-	return assert_clk;
-}
-
-int fpga_wr_fn(int assert_write, int flush, int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (assert_write)
-		setbits_be32(&gpio->simple_dvo, FPGA_DIN);
-	else
-		clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
-
-	return assert_write;
-}
-
-int fpga_pre_config_fn(int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	setbits_8(&gpio->sint_dvo, FPGA_STATUS);
-
-	return 0;
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvsmr/fpga.h b/qemu/roms/u-boot/board/matrix_vision/mvsmr/fpga.h
deleted file mode 100644
index 7ef878bd4..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvsmr/fpga.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-extern int mvsmr_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_init_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_pre_config_fn(int cookie);
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvsmr/mvsmr.c b/qemu/roms/u-boot/board/matrix_vision/mvsmr/mvsmr.c
deleted file mode 100644
index 2c513897f..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvsmr/mvsmr.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2005-2010
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <malloc.h>
-#include <pci.h>
-#include <i2c.h>
-#include <fpga.h>
-#include <environment.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include "fpga.h"
-#include "mvsmr.h"
-#include "../common/mv_common.h"
-
-#define SDRAM_DDR	1
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x715f0f00
-#define SDRAM_CONFIG1	0xd3722930
-#define SDRAM_CONFIG2	0x46770000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_start(int hi_addr)
-{
-	long hi_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
-		hi_bit);
-
-	/* precharge all banks */
-	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
-		hi_bit);
-
-	/* set mode register: extended mode */
-	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
-
-	/* precharge all banks */
-	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
-		hi_bit);
-
-	/* auto refresh */
-	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
-		hi_bit);
-
-	/* set mode register */
-	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
-}
-
-phys_addr_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-	ulong test1,
-	      test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
-
-	/* setup config registers */
-	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	if (dramsize > 0)
-		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1);
-	else
-		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
-
-	return dramsize;
-}
-
-void mvsmr_init_gpio(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	printf("Ports : 0x%08x\n", gpio->port_config);
-	printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
-
-	out_be32(&gpio->simple_ddr, SIMPLE_DDR);
-	out_be32(&gpio->simple_dvo, SIMPLE_DVO);
-	out_be32(&gpio->simple_ode, SIMPLE_ODE);
-	out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
-
-	out_8(&gpio->sint_ode, SINT_ODE);
-	out_8(&gpio->sint_ddr, SINT_DDR);
-	out_8(&gpio->sint_dvo, SINT_DVO);
-	out_8(&gpio->sint_inten, SINT_INTEN);
-	out_be16(&gpio->sint_itype, SINT_ITYPE);
-	out_8(&gpio->sint_gpioe, SINT_GPIOEN);
-
-	out_8(&wu_gpio->ode, WKUP_ODE);
-	out_8(&wu_gpio->ddr, WKUP_DIR);
-	out_8(&wu_gpio->dvo, WKUP_DO);
-	out_8(&wu_gpio->enable, WKUP_EN);
-
-	out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
-	out_be32(&timers->gpt1.emsr, 0x00000234);
-	out_be32(&timers->gpt2.emsr, 0x00000234);
-	out_be32(&timers->gpt3.emsr, 0x00000234);
-	out_be32(&timers->gpt4.emsr, 0x00000234);
-	out_be32(&timers->gpt5.emsr, 0x00000234);
-	out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
-	out_be32(&timers->gpt7.emsr, 0x00000024);
-}
-
-int misc_init_r(void)
-{
-	char *s = getenv("reset_env");
-
-	if (s) {
-		printf(" === FACTORY RESET ===\n");
-		mv_reset_environment();
-		saveenv();
-	}
-
-	return -1;
-}
-
-void mvsmr_get_dbg_present(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
-
-	if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
-		setenv("dbg_present", "no\0");
-		setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
-	} else {
-		setenv("dbg_present", "yes\0");
-		setenv("bootstopkey", "s\0");
-		setbits_8(&psc->command, PSC_RX_ENABLE);
-	}
-}
-
-void mvsmr_get_service_mode(void)
-{
-	struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-
-	if (in_8(&wu_gpio->ival) & SERVICE_MODE)
-		setenv("servicemode", "no\0");
-	else
-		setenv("servicemode", "yes\0");
-}
-
-int mvsmr_get_mac(void)
-{
-	unsigned char mac[6];
-	struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-
-	if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
-		setenv("lan_present", "no\0");
-		return -1;
-	} else
-		setenv("lan_present", "yes\0");
-
-	i2c_read(0x50, 0, 1, mac, 6);
-
-	eth_setenv_enetaddr("ethaddr", mac);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	mvsmr_init_gpio();
-	printf("Board: Matrix Vision mvSMR\n");
-
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
-}
-
-void flash_afterinit(ulong size)
-{
-	out_be32((u32 *)MPC5XXX_BOOTCS_START,
-		START_REG(CONFIG_SYS_BOOTCS_START | size));
-	out_be32((u32 *)MPC5XXX_CS0_START,
-		START_REG(CONFIG_SYS_BOOTCS_START | size));
-	out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
-		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
-	out_be32((u32 *)MPC5XXX_CS0_STOP,
-		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
-}
-
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	mvsmr_get_dbg_present();
-	mvsmr_get_service_mode();
-	mvsmr_init_fpga();
-	mv_load_fpga();
-	pci_mpc5xxx_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	if (!mvsmr_get_mac())
-		return cpu_eth_init(bis);
-
-	return pci_eth_init(bis);
-}
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvsmr/mvsmr.h b/qemu/roms/u-boot/board/matrix_vision/mvsmr/mvsmr.h
deleted file mode 100644
index b8320f1e6..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvsmr/mvsmr.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#include <pci.h>
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-#define FPGA_DIN	MPC5XXX_GPIO_SIMPLE_PSC3_0
-#define FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_1
-#define FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_2
-#define FPGA_CONFIG	MPC5XXX_GPIO_SIMPLE_PSC3_3
-#define FPGA_STATUS	MPC5XXX_GPIO_SINT_PSC3_4
-#define S_FPGA_DIN	MPC5XXX_GPIO_SINT_PSC3_5
-#define S_FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_6
-#define S_FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_7
-#define S_FPGA_CONFIG	MPC5XXX_GPIO_SINT_PSC3_8
-#define S_FPGA_STATUS	MPC5XXX_GPIO_WKUP_PSC3_9
-
-#define MAN_RST		MPC5XXX_GPIO_WKUP_PSC6_0
-#define WD_TS		MPC5XXX_GPIO_WKUP_PSC6_1
-#define WD_WDI		MPC5XXX_GPIO_SIMPLE_PSC6_2
-#define COP_PRESENT	MPC5XXX_GPIO_SIMPLE_PSC6_3
-#define SERVICE_MODE	MPC5XXX_GPIO_WKUP_6
-#define FLASH_RBY	MPC5XXX_GPIO_WKUP_7
-#define UART_EN1	MPC5XXX_GPIO_WKUP_PSC1_4
-#define LAN_PRSNT	MPC5XXX_GPIO_WKUP_PSC2_4
-
-#define SIMPLE_DDR	(FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
-			 S_FPGA_CCLK)
-#define SIMPLE_DVO	(FPGA_CONFIG)
-#define SIMPLE_ODE	(FPGA_CONFIG)
-#define SIMPLE_GPIOEN	(FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
-			 S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
-
-#define SINT_ODE	0x1
-#define SINT_DDR	0x3
-#define SINT_DVO	0x1
-#define SINT_INTEN	0
-#define SINT_ITYPE	0
-#define SINT_GPIOEN	(FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
-
-#define WKUP_ODE	(MAN_RST | S_FPGA_STATUS)
-#define WKUP_DIR	(MAN_RST | WD_TS | S_FPGA_STATUS)
-#define WKUP_DO		(MAN_RST | WD_TS | S_FPGA_STATUS)
-#define WKUP_EN		(MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
-			 FLASH_RBY | UART_EN1 | LAN_PRSNT)
diff --git a/qemu/roms/u-boot/board/matrix_vision/mvsmr/u-boot.lds b/qemu/roms/u-boot/board/matrix_vision/mvsmr/u-boot.lds
deleted file mode 100644
index e885b7c16..000000000
--- a/qemu/roms/u-boot/board/matrix_vision/mvsmr/u-boot.lds
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2010
- * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within  */
-    /* the first two sectors (=8KB) of our S29GL flash chip */
-    arch/powerpc/cpu/mpc5xxx/start.o	(.text*)
-    arch/powerpc/cpu/mpc5xxx/traps.o	(.text*)
-    board/matrix_vision/common/built-in.o	(.text*)
-
-    /* This is only needed to force failure if size of above code will ever */
-    /* increase and grow into reserved space. */
-    . = ALIGN(0x2000);	/* location counter has to be 0x4000 now */
-    . += 0x4000;	/* ->0x8000, i.e. move to env_offset */
-
-    . = env_offset;	/* ld error as soon as above ALIGN misplaces lc */
-    common/env_embedded.o        (.ppcenv)
-
-    *(.text*)
-    . = ALIGN(16);
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}