Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

16 files changed, 0 insertions, 1558 deletions

diff --git a/qemu/roms/u-boot/board/logicpd/am3517evm/Makefile b/qemu/roms/u-boot/board/logicpd/am3517evm/Makefile
deleted file mode 100644
index 73b11dfbf..000000000
--- a/qemu/roms/u-boot/board/logicpd/am3517evm/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Author: Vaibhav Hiremath <hvaibhav@ti.com>
-#
-# Based on ti/evm/Makefile
-#
-# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= am3517evm.o
diff --git a/qemu/roms/u-boot/board/logicpd/am3517evm/am3517evm.c b/qemu/roms/u-boot/board/logicpd/am3517evm/am3517evm.c
deleted file mode 100644
index 24be6eabf..000000000
--- a/qemu/roms/u-boot/board/logicpd/am3517evm/am3517evm.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * am3517evm.c - board file for TI's AM3517 family of devices.
- *
- * Author: Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Based on ti/evm/evm.c
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/omap_musb.h>
-#include <asm/arch/am35x_def.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/musb.h>
-#include <asm/mach-types.h>
-#include <asm/errno.h>
-#include <asm/gpio.h>
-#include <linux/usb/ch9.h>
-#include <linux/usb/gadget.h>
-#include <linux/usb/musb.h>
-#include <i2c.h>
-#include <netdev.h>
-#include "am3517evm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define AM3517_IP_SW_RESET	0x48002598
-#define CPGMACSS_SW_RST		(1 << 1)
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-#ifdef CONFIG_USB_MUSB_AM35X
-static struct musb_hdrc_config musb_config = {
-	.multipoint     = 1,
-	.dyn_fifo       = 1,
-	.num_eps        = 16,
-	.ram_bits       = 12,
-};
-
-static struct omap_musb_board_data musb_board_data = {
-	.set_phy_power		= am35x_musb_phy_power,
-	.clear_irq		= am35x_musb_clear_irq,
-	.reset			= am35x_musb_reset,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_MUSB_HOST)
-	.mode           = MUSB_HOST,
-#elif defined(CONFIG_MUSB_GADGET)
-	.mode		= MUSB_PERIPHERAL,
-#else
-#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
-#endif
-	.config         = &musb_config,
-	.power          = 250,
-	.platform_ops	= &am35x_ops,
-	.board_data	= &musb_board_data,
-};
-
-static void am3517_evm_musb_init(void)
-{
-	/*
-	 * Set up USB clock/mode in the DEVCONF2 register.
-	 * USB2.0 PHY reference clock is 13 MHz
-	 */
-	clrsetbits_le32(&am35x_scm_general_regs->devconf2,
-			CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
-			CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
-			CONF2_VBDTCTEN | CONF2_DATPOL);
-
-	musb_register(&musb_plat, &musb_board_data,
-			(void *)AM35XX_IPSS_USBOTGSS_BASE);
-}
-#else
-#define am3517_evm_musb_init() do {} while (0)
-#endif
-
-/*
- * Routine: misc_init_r
- * Description: Init i2c, ethernet, etc... (done here so udelay works)
- */
-int misc_init_r(void)
-{
-	volatile unsigned int ctr;
-	u32 reset;
-
-#ifdef CONFIG_SYS_I2C_OMAP34XX
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
-
-	dieid_num_r();
-
-	am3517_evm_musb_init();
-
-	/* activate PHY reset */
-	gpio_direction_output(30, 0);
-	gpio_set_value(30, 0);
-
-	ctr  = 0;
-	do {
-		udelay(1000);
-		ctr++;
-	} while (ctr < 300);
-
-	/* deactivate PHY reset */
-	gpio_set_value(30, 1);
-
-	/* allow the PHY to stabilize and settle down */
-	ctr = 0;
-	do {
-		udelay(1000);
-		ctr++;
-	} while (ctr < 300);
-
-	/* ensure that the module is out of reset */
-	reset = readl(AM3517_IP_SW_RESET);
-	reset &= (~CPGMACSS_SW_RST);
-	writel(reset,AM3517_IP_SW_RESET);
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_AM3517EVM();
-}
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)
-int board_eth_init(bd_t *bis)
-{
-	int rv, n = 0;
-
-	rv = cpu_eth_init(bis);
-	if (rv > 0)
-		n += rv;
-
-	rv = usb_eth_initialize(bis);
-	if (rv > 0)
-		n += rv;
-
-	return n;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/logicpd/am3517evm/am3517evm.h b/qemu/roms/u-boot/board/logicpd/am3517evm/am3517evm.h
deleted file mode 100644
index d407d66ae..000000000
--- a/qemu/roms/u-boot/board/logicpd/am3517evm/am3517evm.h
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
- * am3517evm.h - Header file for the AM3517 EVM.
- *
- * Author: Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Based on ti/evm/evm.h
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _AM3517EVM_H_
-#define _AM3517EVM_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_DISCRETE,
-	"AM3517EVM Board",
-	"NAND",
-};
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_AM3517EVM() \
-	/* SDRC */\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
-	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
-	/*sdrc_strben_dly0*/\
-	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
-	 /*sdrc_strben_dly1*/\
-	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
-	/* GPMC */\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
-							 /* - ETH_nRESET*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) \
-	/* DSS */\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
-	/* CAMERA */\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-							 /* - CAM_RESET*/\
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
-	/* MMC */\
-	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
-	/* WriteProtect */\
-	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*CardDetect*/\
-	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
-	\
-	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | DIS | M0)) \
-	/* McBSP */\
-	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
-	\
-	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) \
-	\
-	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) \
-	\
-	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
-							 /* - LCD_INI*/\
-	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
-							 /* - LCD_ENVDD */\
-	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
-							 /* - LCD_QVGA/nVGA */\
-	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
-							 /* - LCD_RESB */\
-	/* UART */\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) \
-	\
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
-	\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
-	/* I2C */\
-	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
-	/* McSPI */\
-	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
-	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
-							 /* - LAN_INTR*/\
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) \
-	\
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M4)) \
-	/* CCDC */\
-	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M1)) \
-	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M1)) \
-	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
-	/* RMII */\
-	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
-	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
-	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
-	/* HECC */\
-	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
-	/* HSUSB */\
-	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
-	/* HDQ */\
-	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) \
-	/* Control and debug */\
-	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
-	/*SYS_nRESWARM */\
-	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | EN | M4)) \
-							/* - GPIO30 */\
-	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
-							 /* - PEN_IRQ */\
-	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
-	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
-	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
-	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
-	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
-							 /* - VIO_1V8*/\
-	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
-	\
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
-	/* JTAG */\
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) \
-	/* ETK (ES2 onwards) */\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) \
-	/* Die to Die */\
-	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
-
-#endif
diff --git a/qemu/roms/u-boot/board/logicpd/imx27lite/Makefile b/qemu/roms/u-boot/board/logicpd/imx27lite/Makefile
deleted file mode 100644
index 50a3da62e..000000000
--- a/qemu/roms/u-boot/board/logicpd/imx27lite/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= imx27lite.o
-obj-y	+= lowlevel_init.o
diff --git a/qemu/roms/u-boot/board/logicpd/imx27lite/imx27lite.c b/qemu/roms/u-boot/board/logicpd/imx27lite/imx27lite.c
deleted file mode 100644
index 07b07a07f..000000000
--- a/qemu/roms/u-boot/board/logicpd/imx27lite/imx27lite.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2007 Sascha Hauer, Pengutronix
- * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-#if defined(CONFIG_SYS_NAND_LARGEPAGE)
-	struct system_control_regs *sc_regs =
-		(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
-#endif
-
-	gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-#ifdef CONFIG_MXC_UART
-	mx27_uart1_init_pins();
-#endif
-#ifdef CONFIG_FEC_MXC
-	mx27_fec_init_pins();
-	imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
-	gpio_set_value(GPIO_PORTC | 31, 1);
-#endif
-#ifdef CONFIG_MXC_MMC
-#if defined(CONFIG_MAGNESIUM)
-	mx27_sd1_init_pins();
-#else
-	mx27_sd2_init_pins();
-#endif
-#endif
-
-#if defined(CONFIG_SYS_NAND_LARGEPAGE)
-	/*
-	 * set in FMCR NF_FMS Bit(5) to 1
-	 * (NAND Flash with 2 Kbyte page size)
-	 */
-	writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr);
-#endif
-	return 0;
-}
-
-int dram_init(void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				PHYS_SDRAM_1_SIZE);
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-			PHYS_SDRAM_1_SIZE);
-#if CONFIG_NR_DRAM_BANKS > 1
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
-			PHYS_SDRAM_2_SIZE);
-#endif
-}
-
-int checkboard(void)
-{
-	puts("Board: ");
-	puts(CONFIG_BOARDNAME);
-	return 0;
-}
diff --git a/qemu/roms/u-boot/board/logicpd/imx27lite/lowlevel_init.S b/qemu/roms/u-boot/board/logicpd/imx27lite/lowlevel_init.S
deleted file mode 100644
index c286d0dfe..000000000
--- a/qemu/roms/u-boot/board/logicpd/imx27lite/lowlevel_init.S
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
- * Applications Processor Reference Manual, Rev. 0.2".
- *
- * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#include <config.h>
-#include <version.h>
-#include <asm/macro.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-
-SOC_ESDCTL_BASE_W:	.word	IMX_ESD_BASE
-SOC_SI_ID_REG_W:	.word	IMX_SYSTEM_CTL_BASE
-SDRAM_ESDCFG_T1_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(0)
-SDRAM_ESDCFG_T2_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(3)
-SDRAM_PRECHARGE_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
-				 ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_AUTOREF_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
-				 ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_LOADMODE_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
-				 ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_NORMAL_CMD_W:	.word	SDRAM_ESDCTL_REGISTER_VAL
-
-.macro init_aipi
-	/*
-	 * setup AIPI1 and AIPI2
-	 */
-	write32 AIPI1_PSR0, AIPI1_PSR0_VAL
-	write32 AIPI1_PSR1, AIPI1_PSR1_VAL
-	write32 AIPI2_PSR0, AIPI2_PSR0_VAL
-	write32 AIPI2_PSR1, AIPI2_PSR1_VAL
-
-.endm /* init_aipi */
-
-.macro init_clock
-	ldr r0, =CSCR
-	/* disable MPLL/SPLL first */
-	ldr r1, [r0]
-	bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
-	str r1, [r0]
-
-	write32 MPCTL0, MPCTL0_VAL
-	write32 SPCTL0, SPCTL0_VAL
-
-	write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
-
-	/*
-	 * add some delay here
-	 */
-	wait_timer 0x1000
-
-	/* peripheral clock divider */
-	write32 PCDR0, PCDR0_VAL
-	write32 PCDR1, PCDR1_VAL
-
-	/* Configure PCCR0 and PCCR1 */
-	write32 PCCR0, PCCR0_VAL
-	write32 PCCR1, PCCR1_VAL
-
-.endm /* init_clock */
-
-.macro sdram_init
-	ldr r0, SOC_ESDCTL_BASE_W
-	mov r2, #PHYS_SDRAM_1
-
-	/* Do initial reset */
-	mov r1, #ESDMISC_MDDR_DL_RST
-	str r1, [r0, #ESDMISC_ROF]
-
-	/* Hold for more than 200ns */
-	wait_timer 0x10000
-
-	/* Activate LPDDR iface */
-	mov r1, #ESDMISC_MDDREN
-	str r1, [r0, #ESDMISC_ROF]
-
-	/* Check The chip version TO1 or TO2 */
-	ldr r1, SOC_SI_ID_REG_W
-	ldr r1, [r1]
-	ands r1, r1, #0xF0000000
-	/* add Latency on CAS only for TO2 */
-	ldreq r1, SDRAM_ESDCFG_T2_W
-	ldrne r1, SDRAM_ESDCFG_T1_W
-	str r1, [r0, #ESDCFG0_ROF]
-
-	/* Run initialization sequence */
-	ldr r1, SDRAM_PRECHARGE_CMD_W
-	str r1, [r0, #ESDCTL0_ROF]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-
-	ldr r1, SDRAM_AUTOREF_CMD_W
-	str r1, [r0, #ESDCTL0_ROF]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-
-	ldr r1, SDRAM_LOADMODE_CMD_W
-	str r1, [r0, #ESDCTL0_ROF]
-	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
-	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
-	ldrb r1, [r3]
-
-	ldr r1, SDRAM_NORMAL_CMD_W
-	str r1, [r0, #ESDCTL0_ROF]
-
-#if (CONFIG_NR_DRAM_BANKS > 1)
-	/* 2nd sdram */
-	mov r2, #PHYS_SDRAM_2
-
-	/* Check The chip version TO1 or TO2 */
-	ldr r1, SOC_SI_ID_REG_W
-	ldr r1, [r1]
-	ands r1, r1, #0xF0000000
-	/* add Latency on CAS only for TO2 */
-	ldreq r1, SDRAM_ESDCFG_T2_W
-	ldrne r1, SDRAM_ESDCFG_T1_W
-	str r1, [r0, #ESDCFG1_ROF]
-
-	/* Run initialization sequence */
-	ldr r1, SDRAM_PRECHARGE_CMD_W
-	str r1, [r0, #ESDCTL1_ROF]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-
-	ldr r1, SDRAM_AUTOREF_CMD_W
-	str r1, [r0, #ESDCTL1_ROF]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-	ldr r1, [r2, #SDRAM_ALL_VAL]
-
-	ldr r1, SDRAM_LOADMODE_CMD_W
-	str r1, [r0, #ESDCTL1_ROF]
-	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
-	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
-	ldrb r1, [r3]
-
-	ldr r1, SDRAM_NORMAL_CMD_W
-	str r1, [r0, #ESDCTL1_ROF]
-#endif  /* CONFIG_NR_DRAM_BANKS > 1 */
-
-.endm /* sdram_init */
-
-.globl	lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-	init_aipi
-
-	init_clock
-
-	sdram_init
-
-	mov	pc,r10
diff --git a/qemu/roms/u-boot/board/logicpd/imx31_litekit/Makefile b/qemu/roms/u-boot/board/logicpd/imx31_litekit/Makefile
deleted file mode 100644
index 3fd71c8de..000000000
--- a/qemu/roms/u-boot/board/logicpd/imx31_litekit/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= imx31_litekit.o
-obj-y	+= lowlevel_init.o
diff --git a/qemu/roms/u-boot/board/logicpd/imx31_litekit/imx31_litekit.c b/qemu/roms/u-boot/board/logicpd/imx31_litekit/imx31_litekit.c
deleted file mode 100644
index 386e10632..000000000
--- a/qemu/roms/u-boot/board/logicpd/imx31_litekit/imx31_litekit.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
-				PHYS_SDRAM_1_SIZE);
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	/* CS0: Nor Flash */
-	static const struct mxc_weimcs cs0 = {
-		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
-		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 15, 0,  0,  3),
-		/*    oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
-		CSCR_L(10,  0,   3,   3,  0,  1,  5,  0,  0,  0,   0,   1),
-		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
-		CSCR_A(0,   0,  2,  2,  0,  0,  2,  0,  0,  0,  0,  0,   0,  0)
-	};
-
-	/* CS4: Network Controller */
-	static const struct mxc_weimcs cs4 = {
-		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
-		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 28, 1,  7,  6),
-		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
-		CSCR_L(4,  4,   4,  10,  4,  0,  5,  4,  0,  0,   0,   1),
-		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
-		CSCR_A(4,   4,  4,  4,  0,  1,  4,  3,  0,  0,  0,  0,   1,  0)
-	};
-
-	mxc_setup_weimcs(0, &cs0);
-	mxc_setup_weimcs(4, &cs4);
-
-	/* setup pins for UART1 */
-	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
-	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
-	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
-	/* SPI2 */
-	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
-	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
-	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
-	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
-	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
-	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
-	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
-
-	/* start SPI2 clock */
-	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	printf("Board: i.MX31 Litekit\n");
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-	return rc;
-}
diff --git a/qemu/roms/u-boot/board/logicpd/imx31_litekit/lowlevel_init.S b/qemu/roms/u-boot/board/logicpd/imx31_litekit/lowlevel_init.S
deleted file mode 100644
index 7c456bc4a..000000000
--- a/qemu/roms/u-boot/board/logicpd/imx31_litekit/lowlevel_init.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
-	ldr r2, =\reg
-	ldr r3, =\val
-	str r3, [r2]
-.endm
-
-.macro REG8 reg, val
-	ldr r2, =\reg
-	ldr r3, =\val
-	strb r3, [r2]
-.endm
-
-.macro DELAY loops
-	ldr r2, =\loops
-1:
-	subs	r2, r2, #1
-	nop
-	bcs 1b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
-	REG	IPU_CONF, IPU_CONF_DI_EN
-	REG	CCM_CCMR, 0x074B0BF5
-
-	DELAY 0x40000
-
-	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE
-	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
-
-	REG	CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
-
-	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
-	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
-
-	REG	0x43FAC26C, 0 /* SDCLK */
-	REG	0x43FAC270, 0 /* CAS */
-	REG	0x43FAC274, 0 /* RAS */
-	REG	0x43FAC27C, 0x1000 /* CS2 (CSD0) */
-	REG	0x43FAC284, 0 /* DQM3 */
-	REG	0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
-	REG	0x43FAC28C, 0
-	REG	0x43FAC290, 0
-	REG	0x43FAC294, 0
-	REG	0x43FAC298, 0
-	REG	0x43FAC29C, 0
-	REG	0x43FAC2A0, 0
-	REG	0x43FAC2A4, 0
-	REG	0x43FAC2A8, 0
-	REG	0x43FAC2AC, 0
-	REG	0x43FAC2B0, 0
-	REG	0x43FAC2B4, 0
-	REG	0x43FAC2B8, 0
-	REG	0x43FAC2BC, 0
-	REG	0x43FAC2C0, 0
-	REG	0x43FAC2C4, 0
-	REG	0x43FAC2C8, 0
-	REG	0x43FAC2CC, 0
-	REG	0x43FAC2D0, 0
-	REG	0x43FAC2D4, 0
-	REG	0x43FAC2D8, 0
-	REG	0x43FAC2DC, 0
-	REG	0xB8001010, 0x00000004
-	REG	0xB8001004, 0x006ac73a
-	REG	0xB8001000, 0x92100000
-	REG	0x80000f00, 0x12344321
-	REG	0xB8001000, 0xa2100000
-	REG	0x80000000, 0x12344321
-	REG	0x80000000, 0x12344321
-	REG	0xB8001000, 0xb2100000
-	REG8	0x80000033, 0xda
-	REG8	0x81000000, 0xff
-	REG	0xB8001000, 0x82226080
-	REG	0x80000000, 0xDEADBEEF
-	REG	0xB8001010, 0x0000000c
-
-	mov	pc, lr
diff --git a/qemu/roms/u-boot/board/logicpd/omap3som/Makefile b/qemu/roms/u-boot/board/logicpd/omap3som/Makefile
deleted file mode 100644
index 87b86ad25..000000000
--- a/qemu/roms/u-boot/board/logicpd/omap3som/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= omap3logic.o
diff --git a/qemu/roms/u-boot/board/logicpd/omap3som/omap3logic.c b/qemu/roms/u-boot/board/logicpd/omap3som/omap3logic.c
deleted file mode 100644
index 075fe949a..000000000
--- a/qemu/roms/u-boot/board/logicpd/omap3som/omap3logic.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * (C) Copyright 2011
- * Logic Product Development <www.logicpd.com>
- *
- * Author :
- *	Peter Barada <peter.barada@logicpd.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <flash.h>
-#include <nand.h>
-#include <i2c.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include "omap3logic.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * two dimensional array of strucures containining board name and Linux
- * machine IDs; row it selected based on CPU column is slected based
- * on hsusb0_data5 pin having a pulldown resistor
- */
-static struct board_id {
-	char *name;
-	int machine_id;
-} boards[2][2] = {
-	{
-		{
-			.name		= "OMAP35xx SOM LV",
-			.machine_id	= MACH_TYPE_OMAP3530_LV_SOM,
-		},
-		{
-			.name		= "OMAP35xx Torpedo",
-			.machine_id	= MACH_TYPE_OMAP3_TORPEDO,
-		},
-	},
-	{
-		{
-			.name		= "DM37xx SOM LV",
-			.machine_id	= MACH_TYPE_DM3730_SOM_LV,
-		},
-		{
-			.name		= "DM37xx Torpedo",
-			.machine_id	= MACH_TYPE_DM3730_TORPEDO,
-		},
-	},
-};
-
-/*
- * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
- */
-#define BOARD_ID_GPIO	189 /* hsusb0_data5 pin */
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	struct board_id *board;
-	unsigned int val;
-
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	/*
-	 * To identify between a SOM LV and Torpedo module,
-	 * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
-	 * Drive the pin (and let it soak), then read it back.
-	 * If the pin is still high its a Torpedo.  If low its a SOM LV
-	 */
-
-	/* Mux hsusb0_data5 as a GPIO */
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M4));
-
-	if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
-
-		/*
-		 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
-		 * will drain the voltage.
-		 */
-		gpio_direction_output(BOARD_ID_GPIO, 0);
-		gpio_set_value(BOARD_ID_GPIO, 1);
-
-		/* Let it soak for a bit */
-		sdelay(0x100);
-
-		/*
-		 * Read state of BOARD_ID_GPIO as an input and if its set.
-		 * If so the board is a Torpedo
-		 */
-		gpio_direction_input(BOARD_ID_GPIO);
-		val = gpio_get_value(BOARD_ID_GPIO);
-		gpio_free(BOARD_ID_GPIO);
-
-		board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
-		printf("Board: %s\n", board->name);
-
-		/* Set the machine_id passed to Linux */
-		gd->bd->bi_arch_number = board->machine_id;
-	}
-
-	/* restore hsusb0_data5 pin as hsusb0_data5 */
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0));
-
-	return 0;
-}
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#ifdef CONFIG_SMC911X
-/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
-static const u32 gpmc_lan92xx_config[] = {
-	NET_LAN92XX_GPMC_CONFIG1,
-	NET_LAN92XX_GPMC_CONFIG2,
-	NET_LAN92XX_GPMC_CONFIG3,
-	NET_LAN92XX_GPMC_CONFIG4,
-	NET_LAN92XX_GPMC_CONFIG5,
-	NET_LAN92XX_GPMC_CONFIG6,
-};
-
-int board_eth_init(bd_t *bis)
-{
-	enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
-			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	/*GPMC*/
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | DIS | M4));
-	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0));
-
-	/*Expansion card  */
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0));
-
-	/* Serial Console */
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0));
-	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0));
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0));
-
-	/* I2C */
-	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0));
-
-	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0));
-
-	/*Control and debug */
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0));
-	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0));
-	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0));
-}
diff --git a/qemu/roms/u-boot/board/logicpd/omap3som/omap3logic.h b/qemu/roms/u-boot/board/logicpd/omap3som/omap3logic.h
deleted file mode 100644
index 3a3ef6e2d..000000000
--- a/qemu/roms/u-boot/board/logicpd/omap3som/omap3logic.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2011
- * Logic Product Development <www.logicpd.com>
- *
- * Author:
- * Peter Barada <peter.barada@logicpd.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _OMAP3LOGIC_H_
-#define _OMAP3LOGIC_H_
-
-/*
- * OMAP3 GPMC register settings for CS1 LAN922x
- */
-#define NET_LAN92XX_GPMC_CONFIG1	0x00001000
-#define NET_LAN92XX_GPMC_CONFIG2	0x00080801
-#define NET_LAN92XX_GPMC_CONFIG3	0x00000000
-#define NET_LAN92XX_GPMC_CONFIG4	0x08010801
-#define NET_LAN92XX_GPMC_CONFIG5	0x00080a0a
-#define NET_LAN92XX_GPMC_CONFIG6	0x03000280
-
-
-const omap3_sysinfo sysinfo = {
-	DDR_DISCRETE,
-	"Logic DM37x/OMAP35x reference board",
-	"NAND",
-};
-
-
-#endif
diff --git a/qemu/roms/u-boot/board/logicpd/zoom1/Makefile b/qemu/roms/u-boot/board/logicpd/zoom1/Makefile
deleted file mode 100644
index 7da0da031..000000000
--- a/qemu/roms/u-boot/board/logicpd/zoom1/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= zoom1.o
diff --git a/qemu/roms/u-boot/board/logicpd/zoom1/config.mk b/qemu/roms/u-boot/board/logicpd/zoom1/config.mk
deleted file mode 100644
index c7ebfd9e6..000000000
--- a/qemu/roms/u-boot/board/logicpd/zoom1/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2006-2008
-# Texas Instruments, <www.ti.com>
-#
-# Zoom MDK uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
diff --git a/qemu/roms/u-boot/board/logicpd/zoom1/zoom1.c b/qemu/roms/u-boot/board/logicpd/zoom1/zoom1.c
deleted file mode 100644
index 461a85272..000000000
--- a/qemu/roms/u-boot/board/logicpd/zoom1/zoom1.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Nishanth Menon <nm@ti.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- *	Sunil Kumar <sunilsaini05@gmail.com>
- *	Shashi Ranjan <shashiranjanmca05@gmail.com>
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "zoom1.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* gpmc_cfg is initialized by gpmc_init and we use it here */
-extern struct gpmc *gpmc_cfg;
-
-/* GPMC definitions for Ethenet Controller LAN9211 */
-static const u32 gpmc_lab_enet[] = {
-	ZOOM1_ENET_GPMC_CONF1,
-	ZOOM1_ENET_GPMC_CONF2,
-	ZOOM1_ENET_GPMC_CONF3,
-	ZOOM1_ENET_GPMC_CONF4,
-	ZOOM1_ENET_GPMC_CONF5,
-	ZOOM1_ENET_GPMC_CONF6,
-	/*CONF7- computed as params */
-};
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* CS1 is Ethernet LAN9211 */
-	enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
-			      DEBUG_BASE, GPMC_SIZE_16M);
-	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure zoom board specific configurations
- */
-int misc_init_r(void)
-{
-	twl4030_power_init();
-	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-	dieid_num_r();
-
-	/*
-	 * Board Reset
-	 * The board is reset by holding the red button on the
-	 * top right front face for eight seconds.
-	 */
-	twl4030_power_reset_init();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	/* platform specific muxes */
-	MUX_ZOOM1_MDK();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-
-#ifdef CONFIG_SMC911X
-#define STR_ENV_ETHADDR	"ethaddr"
-
-	struct eth_device *dev;
-	uchar eth_addr[6];
-
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
-		dev = eth_get_dev_by_index(0);
-		if (dev) {
-			eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
-		} else {
-			printf("zoom1: Couldn't get eth device\n");
-			rc = -1;
-		}
-	}
-#endif
-
-	return rc;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/logicpd/zoom1/zoom1.h b/qemu/roms/u-boot/board/logicpd/zoom1/zoom1.h
deleted file mode 100644
index 3a943dfc0..000000000
--- a/qemu/roms/u-boot/board/logicpd/zoom1/zoom1.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments
- * Nishanth Menon <nm@ti.com>
- *
- * Derived from: board/omap3/beagle/beagle.h
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _BOARD_ZOOM1_H_
-#define _BOARD_ZOOM1_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-	"OMAP3 Zoom MDK Rev 1",
-	"NAND",
-};
-
-#define ZOOM1_ENET_GPMC_CONF1  0x00611000
-#define ZOOM1_ENET_GPMC_CONF2  0x001F1F01
-#define ZOOM1_ENET_GPMC_CONF3  0x00080803
-#define ZOOM1_ENET_GPMC_CONF4  0x1D091D09
-#define ZOOM1_ENET_GPMC_CONF5  0x041D1F1F
-#define ZOOM1_ENET_GPMC_CONF6  0x1D0904C4
-
-/*
- * IEN	- Input Enable
- * IDIS	- Input Disable
- * PTD	- Pull type Down
- * PTU	- Pull type Up
- * DIS	- Pull type selection is inactive
- * EN	- Pull type selection is active
- * M0	- Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_ZOOM1_MDK() \
- /*SDRC*/\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
-	MUX_VAL(CP(GPMC_NCS3),		(IEN  | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\
-	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\
-	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M7)) /*GPMC_nCS6*/\
-	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
-	MUX_VAL(CP(GPMC_NWP),		(IDIS | PTU | DIS | M0)) /*GPMC_nWP*/\
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTD | EN  | M0)) /*GPMC_WAIT0*/\
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/
-
-#endif /* _BOARD_ZOOM_H_ */