Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

4 files changed, 0 insertions, 278 deletions

diff --git a/qemu/roms/u-boot/board/iomega/iconnect/Makefile b/qemu/roms/u-boot/board/iomega/iconnect/Makefile
deleted file mode 100644
index 65e357ac9..000000000
--- a/qemu/roms/u-boot/board/iomega/iconnect/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= iconnect.o
diff --git a/qemu/roms/u-boot/board/iomega/iconnect/iconnect.c b/qemu/roms/u-boot/board/iomega/iconnect/iconnect.c
deleted file mode 100644
index c3443bdc8..000000000
--- a/qemu/roms/u-boot/board/iomega/iconnect/iconnect.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (C) 2009-2012
- * Wojciech Dubowik <wojciech.dubowik@neratec.com>
- * Luka Perkov <luka@openwrt.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
-#include <asm/arch/mpp.h>
-#include "iconnect.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/*
-	 * default gpio configuration
-	 * There are maximum 64 gpios controlled through 2 sets of registers
-	 * the below configuration configures mainly initial LED status
-	 */
-	kw_config_gpio(ICONNECT_OE_VAL_LOW,
-			ICONNECT_OE_VAL_HIGH,
-			ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
-
-	/* Multi-Purpose Pins Functionality configuration */
-	static const u32 kwmpp_config[] = {
-		MPP0_NF_IO2,
-		MPP1_NF_IO3,
-		MPP2_NF_IO4,
-		MPP3_NF_IO5,
-		MPP4_NF_IO6,
-		MPP5_NF_IO7,
-		MPP6_SYSRST_OUTn,	/* Reset signal */
-		MPP7_GPO,
-		MPP8_TW_SDA,		/* I2C */
-		MPP9_TW_SCK,		/* I2C */
-		MPP10_UART0_TXD,
-		MPP11_UART0_RXD,
-		MPP12_GPO,		/* Reset button */
-		MPP13_SD_CMD,
-		MPP14_SD_D0,
-		MPP15_SD_D1,
-		MPP16_SD_D2,
-		MPP17_SD_D3,
-		MPP18_NF_IO0,
-		MPP19_NF_IO1,
-		MPP20_GE1_0,
-		MPP21_GE1_1,
-		MPP22_GE1_2,
-		MPP23_GE1_3,
-		MPP24_GE1_4,
-		MPP25_GE1_5,
-		MPP26_GE1_6,
-		MPP27_GE1_7,
-		MPP28_GPIO,
-		MPP29_GPIO,
-		MPP30_GE1_10,
-		MPP31_GE1_11,
-		MPP32_GE1_12,
-		MPP33_GE1_13,
-		MPP34_GE1_14,
-		MPP35_GPIO,		/* OTB button */
-		MPP36_AUDIO_SPDIFI,
-		MPP37_AUDIO_SPDIFO,
-		MPP38_GPIO,
-		MPP39_TDM_SPI_CS0,
-		MPP40_TDM_SPI_SCK,
-		MPP41_GPIO,		/* LED brightness */
-		MPP42_GPIO,		/* LED power (blue) */
-		MPP43_GPIO,		/* LED power (red) */
-		MPP44_GPIO,		/* LED USB 1 */
-		MPP45_GPIO,		/* LED USB 2 */
-		MPP46_GPIO,		/* LED USB 3 */
-		MPP47_GPIO,		/* LED USB 4 */
-		MPP48_GPIO,		/* LED OTB */
-		MPP49_GPIO,
-		0
-	};
-	kirkwood_mpp_conf(kwmpp_config, NULL);
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
-
-	return 0;
-}
diff --git a/qemu/roms/u-boot/board/iomega/iconnect/iconnect.h b/qemu/roms/u-boot/board/iomega/iconnect/iconnect.h
deleted file mode 100644
index 6107a9963..000000000
--- a/qemu/roms/u-boot/board/iomega/iconnect/iconnect.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (C) 2009-2012
- * Wojciech Dubowik <wojciech.dubowik@neratec.com>
- * Luka Perkov <luka@openwrt.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ICONNECT_H
-#define __ICONNECT_H
-
-#define ICONNECT_OE_LOW			(~(1 << 7))
-#define ICONNECT_OE_HIGH		(~(1 << 10))
-#define ICONNECT_OE_VAL_LOW		(0)
-#define ICONNECT_OE_VAL_HIGH		(1 << 10)
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG		10
-#define MV88E1116_CPRSP_CR3_REG		21
-#define MV88E1116_MAC_CTRL_REG		21
-#define MV88E1116_PGADR_REG		22
-#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
-
-#endif /* __ICONNECT_H */
diff --git a/qemu/roms/u-boot/board/iomega/iconnect/kwbimage.cfg b/qemu/roms/u-boot/board/iomega/iconnect/kwbimage.cfg
deleted file mode 100644
index 3c63a03d3..000000000
--- a/qemu/roms/u-boot/board/iomega/iconnect/kwbimage.cfg
+++ /dev/null
@@ -1,151 +0,0 @@
-#
-# (C) Copyright 2009-2012
-# Wojciech Dubowik <wojciech.dubowik@neratec.com>
-# Luka Perkov <luka@openwrt.org>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM	nand
-NAND_ECC_MODE	default
-NAND_PAGE_SIZE	0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xffd100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xffd01400 0x43000c30	# DDR Configuration register
-# bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
-# bit23-14: 0x0,
-# bit24:    0x1,   enable exit self refresh mode on DDR access
-# bit25:    0x1,   required
-# bit29-26: 0x0,
-# bit31-30: 0x1,
-
-DATA 0xffd01404 0x37543000	# DDR Controller Control Low
-# bit4:     0x0, addr/cmd in smame cycle
-# bit5:     0x0, clk is driven during self refresh, we don't care for APX
-# bit6:     0x0, use recommended falling edge of clk for addr/cmd
-# bit14:    0x0, input buffer always powered up
-# bit18:    0x1, cpu lock transaction enabled
-# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 0x3, required
-# bit31:    0x0, no additional STARTBURST delay
-
-DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
-# bit3-0:   TRAS lsbs
-# bit7-4:   TRCD
-# bit11-8:  TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20:    TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xffd0140c 0x00000a33	# DDR Timing (High)
-# bit6-0:   TRFC
-# bit8-7:   TR2R
-# bit10-9:  TR2W
-# bit12-11: TW2W
-# bit31-13: 0x0, required
-
-DATA 0xffd01410 0x000000cc	# DDR Address Control
-# bit1-0:   00,  Cs0width (x8)
-# bit3-2:   11,  Cs0size (1Gb)
-# bit5-4:   00,  Cs1width (x8)
-# bit7-6:   11,  Cs1size (1Gb)
-# bit9-8:   00,  Cs2width (nonexistent)
-# bit11-10: 00,  Cs2size (nonexistent)
-# bit13-12: 00,  Cs3width (nonexistent)
-# bit15-14: 00,  Cs3size (nonexistent)
-# bit16:    0,   Cs0AddrSel
-# bit17:    0,   Cs1AddrSel
-# bit18:    0,   Cs2AddrSel
-# bit19:    0,   Cs3AddrSel
-# bit31-20: 0x0, required
-
-DATA 0xffd01414 0x00000000	# DDR Open Pages Control
-# bit0:    0,   OpenPage enabled
-# bit31-1: 0x0, required
-
-DATA 0xffd01418 0x00000000	# DDR Operation
-# bit3-0:   0x0, DDR cmd
-# bit31-4:  0x0, required
-
-DATA 0xffd0141c 0x00000c52	# DDR Mode
-# bit2-0:   0x2, BurstLen=2 required
-# bit3:     0x0, BurstType=0 required
-# bit6-4:   0x4, CL=5
-# bit7:     0x0, TestMode=0 normal
-# bit8:     0x0, DLL reset=0 normal
-# bit11-9:  0x6, auto-precharge write recovery ????????????
-# bit12:    0x0, PD must be zero
-# bit31-13: 0x0, required
-
-DATA 0xffd01420 0x00000040	# DDR Extended Mode
-# bit0:     0,   DDR DLL enabled
-# bit1:     0,   DDR drive strenght normal
-# bit2:     0,   DDR ODT control lsd (disabled)
-# bit5-3:   0x0, required
-# bit6:     1,   DDR ODT control msb, (disabled)
-# bit9-7:   0x0, required
-# bit10:    0,   differential DQS enabled
-# bit11:    0,   required
-# bit12:    0,   DDR output buffer enabled
-# bit31-13: 0x0, required
-
-DATA 0xffd01424 0x0000f17f	# DDR Controller Control High
-# bit2-0:   0x7, required
-# bit3:     0x1, MBUS Burst Chop disabled
-# bit6-4:   0x7, required
-# bit7:     0x0,
-# bit8:     0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9:     0x0, no half clock cycle addition to dataout
-# bit10:    0x0, 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11:    0x0, 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 0xf, required
-# bit31-16: 0x0, required
-
-DATA 0xffd01428 0x00085520	# DDR2 ODT Read Timing (default values)
-DATA 0xffd0147c 0x00008552	# DDR2 ODT Write Timing (default values)
-
-DATA 0xffd01500 0x00000000	# CS[0]n Base address to 0x0
-DATA 0xffd01504 0x0ffffff1	# CS[0]n Size
-# bit0:     0x1,     Window enabled
-# bit1:     0x0,     Write Protect disabled
-# bit3-2:   0x0,     CS0 hit selected
-# bit23-4:  0xfffff, required
-# bit31-24: 0x0f,    Size (i.e. 256MB)
-
-DATA 0xffd01508 0x00000000	# CS[1]n Base address to 256Mb
-DATA 0xffd0150c 0x00000000	# CS[1]n Size, window disabled
-
-DATA 0xffd01514 0x00000000	# CS[2]n Size, window disabled
-DATA 0xffd0151c 0x00000000	# CS[3]n Size, window disabled
-
-DATA 0xffd01494 0x00030000	# DDR ODT Control (Low)
-# bit3-0:     ODT0Rd, MODT[0] asserted during read from DRAM CS1
-# bit7-4:     ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
-# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xffd01498 0x00000000	# DDR ODT Control (High)
-# bit1-0:  0x0, ODT0 controlled by ODT Control (low) register above
-# bit3-2:  0x1, ODT1 active NEVER!
-# bit31-4: 0x0, required
-
-DATA 0xffd0149c 0x0000e803	# CPU ODT Control
-DATA 0xffd01480 0x00000001	# DDR Initialization Control
-# bit0: 0x1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0