Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

9 files changed, 901 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/gdsys/common/Makefile b/qemu/roms/u-boot/board/gdsys/common/Makefile
new file mode 100644
index 000000000..fb841e0b8
--- /dev/null
+++ b/qemu/roms/u-boot/board/gdsys/common/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
+obj-$(CONFIG_IO) += miiphybb.o
+obj-$(CONFIG_IO64) += miiphybb.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o
+obj-$(CONFIG_DLVISION_10G) += osd.o
+obj-$(CONFIG_CONTROLCENTERD) += dp501.o
diff --git a/qemu/roms/u-boot/board/gdsys/common/dp501.c b/qemu/roms/u-boot/board/gdsys/common/dp501.c
new file mode 100644
index 000000000..52f3ea167
--- /dev/null
+++ b/qemu/roms/u-boot/board/gdsys/common/dp501.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+
+static void dp501_setbits(u8 addr, u8 reg, u8 mask)
+{
+	u8 val;
+
+	val = i2c_reg_read(addr, reg);
+	setbits_8(&val, mask);
+	i2c_reg_write(addr, reg, val);
+}
+
+static void dp501_clrbits(u8 addr, u8 reg, u8 mask)
+{
+	u8 val;
+
+	val = i2c_reg_read(addr, reg);
+	clrbits_8(&val, mask);
+	i2c_reg_write(addr, reg, val);
+}
+
+static int dp501_detect_cable_adapter(u8 addr)
+{
+	u8 val = i2c_reg_read(addr, 0x00);
+
+	return !(val & 0x04);
+}
+
+static void dp501_link_training(u8 addr)
+{
+	u8 val;
+
+	val = i2c_reg_read(addr, 0x51);
+	i2c_reg_write(addr, 0x5d, val); /* set link_bw */
+	val = i2c_reg_read(addr, 0x52);
+	i2c_reg_write(addr, 0x5e, val); /* set lane_cnt */
+	val = i2c_reg_read(addr, 0x53);
+	i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
+
+	i2c_reg_write(addr, 0x5f, 0x0d); /* start training */
+}
+
+void dp501_powerup(u8 addr)
+{
+	dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
+	i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
+	dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
+	dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
+	i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
+	dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
+	dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+	i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
+	i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
+
+	if (dp501_detect_cable_adapter(addr)) {
+		printf("DVI/HDMI cable adapter detected\n");
+		i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */
+		dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
+	} else {
+		printf("no DVI/HDMI cable adapter detected\n");
+		i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
+		i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
+		i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
+		i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
+		i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
+		i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
+		dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
+		i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
+		i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
+		i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
+		dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
+
+		dp501_link_training(addr);
+	}
+}
+
+void dp501_powerdown(u8 addr)
+{
+	dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
+}
diff --git a/qemu/roms/u-boot/board/gdsys/common/dp501.h b/qemu/roms/u-boot/board/gdsys/common/dp501.h
new file mode 100644
index 000000000..8dc3215dc
--- /dev/null
+++ b/qemu/roms/u-boot/board/gdsys/common/dp501.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DP501_H_
+#define _DP501_H_
+
+void dp501_powerup(u8 addr);
+void dp501_powerdown(u8 addr);
+
+#endif
diff --git a/qemu/roms/u-boot/board/gdsys/common/fpga.c b/qemu/roms/u-boot/board/gdsys/common/fpga.c
new file mode 100644
index 000000000..e10c105fe
--- /dev/null
+++ b/qemu/roms/u-boot/board/gdsys/common/fpga.c
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <gdsys_fpga.h>
+
+#include <asm/io.h>
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+	out_le16(reg, data);
+
+	return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+	*data = in_le16(reg);
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/board/gdsys/common/mclink.c b/qemu/roms/u-boot/board/gdsys/common/mclink.c
new file mode 100644
index 000000000..9f230c9a9
--- /dev/null
+++ b/qemu/roms/u-boot/board/gdsys/common/mclink.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+
+#include <gdsys_fpga.h>
+
+enum {
+	MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7,
+	MCINT_TX_ERROR_EV = 1 << 9,
+	MCINT_TX_BUFFER_FREE = 1 << 10,
+	MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11,
+	MCINT_RX_ERROR_EV = 1 << 13,
+	MCINT_RX_CONTENT_AVAILABLE = 1 << 14,
+	MCINT_RX_PACKET_RECEIVED_EV = 1 << 15,
+};
+
+int mclink_probe(void)
+{
+	unsigned int k;
+	int slaves = 0;
+
+	for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) {
+		int timeout = 0;
+		unsigned int ctr = 0;
+		u16 mc_status;
+
+		FPGA_GET_REG(k, mc_status, &mc_status);
+
+		if (!(mc_status & (1 << 15)))
+			break;
+
+		FPGA_SET_REG(k, mc_control, 0x8000);
+
+		FPGA_GET_REG(k, mc_status, &mc_status);
+		while (!(mc_status & (1 << 14))) {
+			udelay(100);
+			if (ctr++ > 500) {
+				timeout = 1;
+				break;
+			}
+			FPGA_GET_REG(k, mc_status, &mc_status);
+		}
+		if (timeout)
+			break;
+
+		printf("waited %d us for mclink %d to come up\n", ctr * 100, k);
+
+		slaves++;
+	}
+
+	return slaves;
+}
+
+int mclink_send(u8 slave, u16 addr, u16 data)
+{
+	unsigned int ctr = 0;
+	u16 int_status;
+	u16 rx_cmd_status;
+	u16 rx_cmd;
+
+	/* reset interrupt status */
+	FPGA_GET_REG(0, mc_int, &int_status);
+	FPGA_SET_REG(0, mc_int, int_status);
+
+	/* send */
+	FPGA_SET_REG(0, mc_tx_address, addr);
+	FPGA_SET_REG(0, mc_tx_data, data);
+	FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14);
+	FPGA_SET_REG(0, mc_control, 0x8001);
+
+	/* wait for reply */
+	FPGA_GET_REG(0, mc_int, &int_status);
+	while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) {
+		udelay(100);
+		if (ctr++ > 3)
+			return -ETIMEDOUT;
+		FPGA_GET_REG(0, mc_int, &int_status);
+	}
+
+	FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
+	rx_cmd = (rx_cmd_status >> 12) & 0x03;
+	if (rx_cmd != 0)
+		printf("mclink_send: received cmd %d, expected %d\n", rx_cmd,
+		       0);
+
+	return 0;
+}
+
+int mclink_receive(u8 slave, u16 addr, u16 *data)
+{
+	u16 rx_cmd_status;
+	u16 rx_cmd;
+	u16 int_status;
+	unsigned int ctr = 0;
+
+	/* send read request */
+	FPGA_SET_REG(0, mc_tx_address, addr);
+	FPGA_SET_REG(0, mc_tx_cmd,
+		     ((slave & 0x03) << 14) | (1 << 12) | (1 << 0));
+	FPGA_SET_REG(0, mc_control, 0x8001);
+
+
+	/* wait for reply */
+	FPGA_GET_REG(0, mc_int, &int_status);
+	while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) {
+		udelay(100);
+		if (ctr++ > 3)
+			return -ETIMEDOUT;
+		FPGA_GET_REG(0, mc_int, &int_status);
+	}
+
+	/* check reply */
+	FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
+	if ((rx_cmd_status >> 14) != slave) {
+		printf("mclink_receive: reply from slave %d, expected %d\n",
+		       rx_cmd_status >> 14, slave);
+		return -EINVAL;
+	}
+
+	rx_cmd = (rx_cmd_status >> 12) & 0x03;
+	if (rx_cmd != 1) {
+		printf("mclink_send: received cmd %d, expected %d\n",
+		       rx_cmd, 1);
+		return -EIO;
+	}
+
+	FPGA_GET_REG(0, mc_rx_data, data);
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/board/gdsys/common/mclink.h b/qemu/roms/u-boot/board/gdsys/common/mclink.h
new file mode 100644
index 000000000..febd46a70
--- /dev/null
+++ b/qemu/roms/u-boot/board/gdsys/common/mclink.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MCLINK_H_
+#define _MCLINK_H_
+
+int mclink_probe(void);
+int mclink_send(u8 slave, u16 addr, u16 data);
+int mclink_receive(u8 slave, u16 addr, u16 *data);
+
+#endif
diff --git a/qemu/roms/u-boot/board/gdsys/common/miiphybb.c b/qemu/roms/u-boot/board/gdsys/common/miiphybb.c
new file mode 100644
index 000000000..310562902
--- /dev/null
+++ b/qemu/roms/u-boot/board/gdsys/common/miiphybb.c
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include <asm/io.h>
+
+struct io_bb_pinset {
+	int mdio;
+	int mdc;
+};
+
+static int io_bb_mii_init(struct bb_miiphy_bus *bus)
+{
+	return 0;
+}
+
+static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+	struct io_bb_pinset *pins = bus->priv;
+
+	out_be32((void *)GPIO0_TCR,
+		in_be32((void *)GPIO0_TCR) | pins->mdio);
+
+	return 0;
+}
+
+static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+	struct io_bb_pinset *pins = bus->priv;
+
+	out_be32((void *)GPIO0_TCR,
+		in_be32((void *)GPIO0_TCR) & ~pins->mdio);
+
+	return 0;
+}
+
+static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+	struct io_bb_pinset *pins = bus->priv;
+
+	if (v)
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) | pins->mdio);
+	else
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) & ~pins->mdio);
+
+	return 0;
+}
+
+static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+	struct io_bb_pinset *pins = bus->priv;
+
+	*v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
+
+	return 0;
+}
+
+static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+	struct io_bb_pinset *pins = bus->priv;
+
+	if (v)
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) | pins->mdc);
+	else
+		out_be32((void *)GPIO0_OR,
+			in_be32((void *)GPIO0_OR) & ~pins->mdc);
+
+	return 0;
+}
+
+static int io_bb_delay(struct bb_miiphy_bus *bus)
+{
+	udelay(1);
+
+	return 0;
+}
+
+struct io_bb_pinset io_bb_pinsets[] = {
+	{
+		.mdio = CONFIG_SYS_MDIO_PIN,
+		.mdc = CONFIG_SYS_MDC_PIN,
+	},
+#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
+	{
+		.mdio = CONFIG_SYS_MDIO1_PIN,
+		.mdc = CONFIG_SYS_MDC1_PIN,
+	},
+#endif
+};
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+	{
+		.name = CONFIG_SYS_GBIT_MII_BUSNAME,
+		.init = io_bb_mii_init,
+		.mdio_active = io_bb_mdio_active,
+		.mdio_tristate = io_bb_mdio_tristate,
+		.set_mdio = io_bb_set_mdio,
+		.get_mdio = io_bb_get_mdio,
+		.set_mdc = io_bb_set_mdc,
+		.delay = io_bb_delay,
+		.priv = &io_bb_pinsets[0],
+	},
+#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
+	{
+		.name = CONFIG_SYS_GBIT_MII1_BUSNAME,
+		.init = io_bb_mii_init,
+		.mdio_active = io_bb_mdio_active,
+		.mdio_tristate = io_bb_mdio_tristate,
+		.set_mdio = io_bb_set_mdio,
+		.get_mdio = io_bb_get_mdio,
+		.set_mdc = io_bb_set_mdc,
+		.delay = io_bb_delay,
+		.priv = &io_bb_pinsets[1],
+	},
+#endif
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+			  sizeof(bb_miiphy_buses[0]);
diff --git a/qemu/roms/u-boot/board/gdsys/common/osd.c b/qemu/roms/u-boot/board/gdsys/common/osd.c
new file mode 100644
index 000000000..c49cd9a61
--- /dev/null
+++ b/qemu/roms/u-boot/board/gdsys/common/osd.c
@@ -0,0 +1,449 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <malloc.h>
+
+#include <gdsys_fpga.h>
+
+#define CH7301_I2C_ADDR 0x75
+
+#define ICS8N3QV01_I2C_ADDR 0x6E
+#define ICS8N3QV01_FREF 114285000
+#define ICS8N3QV01_FREF_LL 114285000LL
+#define ICS8N3QV01_F_DEFAULT_0 156250000LL
+#define ICS8N3QV01_F_DEFAULT_1 125000000LL
+#define ICS8N3QV01_F_DEFAULT_2 100000000LL
+#define ICS8N3QV01_F_DEFAULT_3  25175000LL
+
+#define SIL1178_MASTER_I2C_ADDRESS 0x38
+#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+
+#define PIXCLK_640_480_60 25180000
+
+enum {
+	CH7301_CM = 0x1c,		/* Clock Mode Register */
+	CH7301_IC = 0x1d,		/* Input Clock Register */
+	CH7301_GPIO = 0x1e,		/* GPIO Control Register */
+	CH7301_IDF = 0x1f,		/* Input Data Format Register */
+	CH7301_CD = 0x20,		/* Connection Detect Register */
+	CH7301_DC = 0x21,		/* DAC Control Register */
+	CH7301_HPD = 0x23,		/* Hot Plug Detection Register */
+	CH7301_TCTL = 0x31,		/* DVI Control Input Register */
+	CH7301_TPCP = 0x33,		/* DVI PLL Charge Pump Ctrl Register */
+	CH7301_TPD = 0x34,		/* DVI PLL Divide Register */
+	CH7301_TPVT = 0x35,		/* DVI PLL Supply Control Register */
+	CH7301_TPF = 0x36,		/* DVI PLL Filter Register */
+	CH7301_TCT = 0x37,		/* DVI Clock Test Register */
+	CH7301_TSTP = 0x48,		/* Test Pattern Register */
+	CH7301_PM = 0x49,		/* Power Management register */
+	CH7301_VID = 0x4a,		/* Version ID Register */
+	CH7301_DID = 0x4b,		/* Device ID Register */
+	CH7301_DSP = 0x56,		/* DVI Sync polarity Register */
+};
+
+unsigned int base_width;
+unsigned int base_height;
+size_t bufsize;
+u16 *buf;
+
+unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
+
+#ifdef CONFIG_SYS_CH7301
+int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+#endif
+
+#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
+static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
+{
+	u16 val;
+
+	do {
+		FPGA_GET_REG(screen, extended_interrupt, &val);
+	} while (val & (1 << 12));
+
+	FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8));
+	FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1));
+}
+
+static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
+{
+	unsigned int ctr = 0;
+	u16 val;
+
+	do {
+		FPGA_GET_REG(screen, extended_interrupt, &val);
+	} while (val & (1 << 12));
+
+	FPGA_SET_REG(screen, extended_interrupt, 1 << 14);
+	FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg);
+	FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1));
+
+	FPGA_GET_REG(screen, extended_interrupt, &val);
+	while (!(val & (1 << 14))) {
+		udelay(100000);
+		if (ctr++ > 5) {
+			printf("iic receive timeout\n");
+			break;
+		}
+		FPGA_GET_REG(screen, extended_interrupt, &val);
+	}
+
+	FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val);
+	return val >> 8;
+}
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
+static void mpc92469ac_calc_parameters(unsigned int fout,
+	unsigned int *post_div, unsigned int *feedback_div)
+{
+	unsigned int n = *post_div;
+	unsigned int m = *feedback_div;
+	unsigned int a;
+	unsigned int b = 14745600 / 16;
+
+	if (fout < 50169600)
+		n = 8;
+	else if (fout < 100339199)
+		n = 4;
+	else if (fout < 200678399)
+		n = 2;
+	else
+		n = 1;
+
+	a = fout * n + (b / 2); /* add b/2 for proper rounding */
+
+	m = a / b;
+
+	*post_div = n;
+	*feedback_div = m;
+}
+
+static void mpc92469ac_set(unsigned screen, unsigned int fout)
+{
+	unsigned int n;
+	unsigned int m;
+	unsigned int bitval = 0;
+	mpc92469ac_calc_parameters(fout, &n, &m);
+
+	switch (n) {
+	case 1:
+		bitval = 0x00;
+		break;
+	case 2:
+		bitval = 0x01;
+		break;
+	case 4:
+		bitval = 0x02;
+		break;
+	case 8:
+		bitval = 0x03;
+		break;
+	}
+
+	FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
+}
+#endif
+
+#ifdef CONFIG_SYS_ICS8N3QV01
+
+static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
+{
+	unsigned long long n;
+	unsigned long long mint;
+	unsigned long long mfrac;
+	u8 reg_a, reg_b, reg_c, reg_d, reg_f;
+	unsigned long long fout_calc;
+
+	if (index > 3)
+		return 0;
+
+	reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index);
+	reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index);
+	reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index);
+	reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index);
+	reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index);
+
+	mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
+	mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
+		| (reg_d >> 7);
+	n = reg_d & 0x7f;
+
+	fout_calc = (mint * ICS8N3QV01_FREF_LL
+		     + mfrac * ICS8N3QV01_FREF_LL / 262144LL
+		     + ICS8N3QV01_FREF_LL / 524288LL
+		     + n / 2)
+		    / n
+		    * 1000000
+		    / (1000000 - 100);
+
+	return fout_calc;
+}
+
+
+static void ics8n3qv01_calc_parameters(unsigned int fout,
+	unsigned int *_mint, unsigned int *_mfrac,
+	unsigned int *_n)
+{
+	unsigned int n;
+	unsigned int foutiic;
+	unsigned int fvcoiic;
+	unsigned int mint;
+	unsigned long long mfrac;
+
+	n = (2215000000U + fout / 2) / fout;
+	if ((n & 1) && (n > 5))
+		n -= 1;
+
+	foutiic = fout - (fout / 10000);
+	fvcoiic = foutiic * n;
+
+	mint = fvcoiic / 114285000;
+	if ((mint < 17) || (mint > 63))
+		printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
+
+	mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
+		/ 114285000LL;
+
+	*_mint = mint;
+	*_mfrac = mfrac;
+	*_n = n;
+}
+
+static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+{
+	unsigned int n;
+	unsigned int mint;
+	unsigned int mfrac;
+	unsigned int fout_calc;
+	unsigned long long fout_prog;
+	long long off_ppm;
+	u8 reg0, reg4, reg8, reg12, reg18, reg20;
+
+	fout_calc = ics8n3qv01_get_fout_calc(screen, 1);
+	off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
+		  / ICS8N3QV01_F_DEFAULT_1;
+	printf("       PLL is off by %lld ppm\n", off_ppm);
+	fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
+		    / ICS8N3QV01_F_DEFAULT_1;
+	ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
+
+	reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+	reg0 |= (mint & 0x1f) << 1;
+	reg0 |= (mfrac >> 17) & 0x01;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
+
+	reg4 = mfrac >> 9;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
+
+	reg8 = mfrac >> 1;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
+
+	reg12 = mfrac << 7;
+	reg12 |= n & 0x7f;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
+
+	reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+	reg18 |= 0x20;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
+
+	reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+	reg20 |= mint & (1 << 5);
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
+}
+#endif
+
+static int osd_write_videomem(unsigned screen, unsigned offset,
+	u16 *data, size_t charcount)
+{
+	unsigned int k;
+
+	for (k = 0; k < charcount; ++k) {
+		if (offset + k >= bufsize)
+			return -1;
+		FPGA_SET_REG(screen, videomem[offset + k], data[k]);
+	}
+
+	return charcount;
+}
+
+static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned screen;
+
+	for (screen = 0; screen <= max_osd_screen; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned charcount;
+		unsigned len;
+		u8 color;
+		unsigned int k;
+		char *text;
+		int res;
+
+		if (argc < 5) {
+			cmd_usage(cmdtp);
+			return 1;
+		}
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		color = simple_strtoul(argv[3], NULL, 16);
+		text = argv[4];
+		charcount = strlen(text);
+		len = (charcount > bufsize) ? bufsize : charcount;
+
+		for (k = 0; k < len; ++k)
+			buf[k] = (text[k] << 8) | color;
+
+		res = osd_write_videomem(screen, y * base_width + x, buf, len);
+		if (res < 0)
+			return res;
+	}
+
+	return 0;
+}
+
+int osd_probe(unsigned screen)
+{
+	u16 version;
+	u16 features;
+	u8 value;
+#ifdef CONFIG_SYS_CH7301
+	int old_bus = i2c_get_bus_num();
+#endif
+
+	FPGA_GET_REG(0, osd.version, &version);
+	FPGA_GET_REG(0, osd.features, &features);
+
+	base_width = ((features & 0x3f00) >> 8) + 1;
+	base_height = (features & 0x001f) + 1;
+	bufsize = base_width * base_height;
+	buf = malloc(sizeof(u16) * bufsize);
+	if (!buf)
+		return -1;
+
+	printf("OSD%d:  Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+		screen, version/100, version%100, base_width, base_height);
+
+#ifdef CONFIG_SYS_CH7301
+	i2c_set_bus_num(ch7301_i2c[screen]);
+	value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+	if (value != 0x17) {
+		printf("       Probing CH7301 failed, DID %02x\n", value);
+		i2c_set_bus_num(old_bus);
+		return -1;
+	}
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+	i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+	i2c_set_bus_num(old_bus);
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
+	mpc92469ac_set(screen, PIXCLK_640_480_60);
+#endif
+
+#ifdef CONFIG_SYS_ICS8N3QV01
+	ics8n3qv01_set(screen, PIXCLK_640_480_60);
+#endif
+
+#ifdef CONFIG_SYS_SIL1178
+	value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+	if (value != 0x06) {
+		printf("       Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
+		return -1;
+	}
+	/* magic initialization sequence adapted from datasheet */
+	fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+#endif
+
+	FPGA_SET_REG(screen, videocontrol, 0x0002);
+	FPGA_SET_REG(screen, osd.control, 0x0049);
+
+	FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
+	FPGA_SET_REG(screen, osd.x_pos, 0x007f);
+	FPGA_SET_REG(screen, osd.y_pos, 0x005f);
+
+	if (screen > max_osd_screen)
+		max_osd_screen = screen;
+
+	return 0;
+}
+
+int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned screen;
+
+	for (screen = 0; screen <= max_osd_screen; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned k;
+		u16 buffer[base_width];
+		char *rp;
+		u16 *wp = buffer;
+		unsigned count = (argc > 4) ?
+			simple_strtoul(argv[4], NULL, 16) : 1;
+
+		if ((argc < 4) || (strlen(argv[3]) % 4)) {
+			cmd_usage(cmdtp);
+			return 1;
+		}
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		rp = argv[3];
+
+
+		while (*rp) {
+			char substr[5];
+
+			memcpy(substr, rp, 4);
+			substr[4] = 0;
+			*wp = simple_strtoul(substr, NULL, 16);
+
+			rp += 4;
+			wp++;
+			if (wp - buffer > base_width)
+				break;
+		}
+
+		for (k = 0; k < count; ++k) {
+			unsigned offset =
+				y * base_width + x + k * (wp - buffer);
+			osd_write_videomem(screen, offset, buffer,
+				wp - buffer);
+		}
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	osdw, 5, 0, osd_write,
+	"write 16-bit hex encoded buffer to osd memory",
+	"pos_x pos_y buffer count\n"
+);
+
+U_BOOT_CMD(
+	osdp, 5, 0, osd_print,
+	"write ASCII buffer to osd memory",
+	"pos_x pos_y color text\n"
+);
diff --git a/qemu/roms/u-boot/board/gdsys/common/osd.h b/qemu/roms/u-boot/board/gdsys/common/osd.h
new file mode 100644
index 000000000..440b276a0
--- /dev/null
+++ b/qemu/roms/u-boot/board/gdsys/common/osd.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _OSD_H_
+#define _OSD_H_
+
+int osd_probe(unsigned screen);
+
+#endif