Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

16 files changed, 0 insertions, 1186 deletions

diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/Makefile b/qemu/roms/u-boot/board/freescale/t104xrdb/Makefile
deleted file mode 100644
index 6cd304cce..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y	+= t104xrdb.o
-obj-y	+= cpld.o
-obj-y	+= eth.o
-obj-$(CONFIG_PCI)	+= pci.o
-endif
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/README b/qemu/roms/u-boot/board/freescale/t104xrdb/README
deleted file mode 100644
index cdbe1fafd..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/README
+++ /dev/null
@@ -1,273 +0,0 @@
-Overview
---------
-The T1040RDB is a Freescale reference board that hosts the T1040 SoC
-(and variants). Variants inclued T1042 presonality of T1040, in which
-case T1040RDB can also be called T1042RDB.
-
-The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
-(a personality of T1040 SoC). The board is similar to T1040RDB but is
-designed specially with low power features targeted for Printing Image Market.
-
-T1040 SoC Overview
-------------------
-The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
-processor cores with high-performance data path acceleration architecture
-and network peripheral interfaces required for networking & telecommunications.
-
-The T1040/T1042 SoC includes the following function and features:
-
- - Four e5500 cores, each with a private 256 KB L2 cache
- - 256 KB shared L3 CoreNet platform cache (CPC)
- - Interconnect CoreNet platform
- - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration
- for the following functions:
-    -  Packet parsing, classification, and distribution
-    -  Queue management for scheduling, packet sequencing, and congestion
-       management
-    -  Cryptography Acceleration (SEC 5.0)
-    - RegEx Pattern Matching Acceleration (PME 2.2)
-    - IEEE Std 1588 support
-    - Hardware buffer management for buffer allocation and deallocation
- - Ethernet interfaces
-    - Integrated 8-port Gigabit Ethernet switch (T1040 only)
-    - Four 1 Gbps Ethernet controllers
- - Two RGMII interfaces or one RGMII and one MII interfaces
- - High speed peripheral interfaces
-   - Four PCI Express 2.0 controllers running at up to 5 GHz
-   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
-   - Upto two QSGMII interface
-   - Upto six SGMII interface supporting 1000 Mbps
-   - One SGMII interface supporting upto 2500 Mbps
- - Additional peripheral interfaces
-   - Two USB 2.0 controllers with integrated PHY
-   - SD/eSDHC/eMMC
-   - eSPI controller
-   - Four I2C controllers
-   - Four UARTs
-   - Four GPIO controllers
-   - Integrated flash controller (IFC)
-   - LCD and HDMI interface (DIU) with 12 bit dual data rate
-   - TDM interface
- - Multicore programmable interrupt controller (PIC)
- - Two 8-channel DMA engines
- - Single source clocking implementation
- - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-
-T1040 SoC Personalities
--------------------------
-
-T1022 Personality:
-T1022 is a reduced personality of T1040 with less core/clusters.
-
-T1042 Personality:
-T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
-Ethernet switch. Rest of the blocks are same as T1040
-
-
-T1040RDB board Overview
--------------------------
- - SERDES Connections, 8 lanes information:
-	1: None
-	2: SGMII
-	3: QSGMII
-	4: QSGMII
-	5: PCIe1 x1 slot
-	6: mini PCIe connector
-	7: mini PCIe connector
-	8: SATA connector
- - DDR Controller
-     - Supports rates of up to 1600 MHz data-rate
-     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- - IFC/Local Bus
-     - NAND flash: 1GB 8-bit NAND flash
-     - NOR: 128MB 16-bit NOR Flash
- - Ethernet
-     - Two on-board RGMII 10/100/1G ethernet ports.
- - CPLD
- - Clocks
-     - System and DDR clock (SYSCLK, “DDRCLK”)
-     - SERDES clocks
- - Power Supplies
- - USB
-     - Supports two USB 2.0 ports with integrated PHYs
-     - Two type A ports with 5V@1.5A per port.
- - SDHC
-     - SDHC/SDXC connector
- - SPI
-    -  On-board 64MB SPI flash
- - Other IO
-    - Two Serial ports
-    - Four I2C ports
-
-T1042RDB_PI board Overview
--------------------------
- - SERDES Connections, 8 lanes information:
-	1, 2, 3, 4 : PCIe x4 slot
-	5: mini PCIe connector
-	6: mini PCIe connector
-	7: NA
-	8: SATA connector
- - DDR Controller
-     - Supports rates of up to 1600 MHz data-rate
-     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- - IFC/Local Bus
-     - NAND flash: 1GB 8-bit NAND flash
-     - NOR: 128MB 16-bit NOR Flash
- - Ethernet
-     - Two on-board RGMII 10/100/1G ethernet ports.
- - CPLD
- - Clocks
-     - System and DDR clock (SYSCLK, “DDRCLK”)
-     - SERDES clocks
- - Video
-     - DIU supports video at up to 1280x1024x32bpp
- - Power Supplies
- - USB
-     - Supports two USB 2.0 ports with integrated PHYs
-     - Two type A ports with 5V@1.5A per port.
- - SDHC
-     - SDHC/SDXC connector
- - SPI
-    -  On-board 64MB SPI flash
- - Other IO
-    - Two Serial ports
-    - Four I2C ports
-
-Memory map
------------
-The addresses in brackets are physical addresses.
-
-Start Address  End Address      Description                     Size
-0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - CPLD                      4KB
-0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash                64KB
-0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR                         16MB
-0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space         64KB
-0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space	        64KB
-0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space         64KB
-0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space	        64KB
-0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
-0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
-0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash                 128MB
-0xF_0000_0000  0xF_003F_FFFF    DCSR                            4MB
-0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 4 Mem Space         256MB
-0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space         256MB
-0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space         256MB
-0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space         256MB
-0x0_0000_0000  0x0_ffff_ffff    DDR                             2GB
-
-
-NOR Flash memory Map
----------------------
- Start          End             Definition                       Size
-0xEFF40000      0xEFFFFFFF      u-boot (current bank)            768KB
-0xEFF20000      0xEFF3FFFF      u-boot env (current bank)        128KB
-0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)        128KB
-0xED300000      0xEFEFFFFF      rootfs (alt bank)                44MB
-0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank)  1MB
-0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)          7MB + 875KB
-0xEC000000      0xEC01FFFF      RCW (alt bank)                   128KB
-0xEBF40000      0xEBFFFFFF      u-boot (alt bank)                768KB
-0xEBF20000      0xEBF3FFFF      u-boot env (alt bank)            128KB
-0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)            128KB
-0xE9300000      0xEBEFFFFF      rootfs (current bank)            44MB
-0xE8800000      0xE88FFFFF      Hardware device tree (cur bank)  11MB + 512KB
-0xE8020000      0xE86FFFFF      Linux.uImage (current bank)      7MB + 875KB
-0xE8000000      0xE801FFFF      RCW (current bank)               128KB
-
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to the board
-
-1. U-boot environment variable hwconfig
-   The default hwconfig is:
-	hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
-					dr_mode=host,phy_type=utmi
-   Note: For USB gadget set "dr_mode=peripheral"
-
-2. FMAN Ucode versions
-   fsl_fman_ucode_t1040.bin
-
-3. Switching to alternate bank
-   Commands for switching to alternate bank.
-
-	1. To change from vbank0 to vbank4
-		=> qixis_reset altbank (it will boot using vbank4)
-
-	2.To change from vbank4 to vbank0
-		=> qixis reset (it will boot using vbank0)
-
-NAND boot with 2 Stage boot loader
-----------------------------------
-PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
-SPL further initialise DDR using SPD and environment variables and copy
-u-boot(768 KB) from flash to DDR.
-Finally SPL transer control to u-boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
- Run time view of SPL framework during  boot :-
- -----------------------------------------------
- Area        | Address                         |
------------------------------------------------
- Secure boot | 0xFFFC0000 (32KB)               |
- headers     |                                 |
- -----------------------------------------------
- GD, BD      | 0xFFFC8000 (4KB)                |
- -----------------------------------------------
- ENV         | 0xFFFC9000 (8KB)                |
- -----------------------------------------------
- HEAP        | 0xFFFCB000 (30KB)               |
- -----------------------------------------------
- STACK       | 0xFFFD8000 (22KB)               |
- -----------------------------------------------
- U-boot SPL  | 0xFFFD8000 (160KB)              |
- -----------------------------------------------
-
-NAND Flash memory Map on T104xRDB
-------------------------------------------
- Start		 End		Definition			Size
-0x000000	0x0FFFFF	u-boot                          1MB
-0x180000	0x19FFFF	u-boot env                      128KB
-0x280000	0x29FFFF	FMAN Ucode                      128KB
-0x380000	0x39FFFF	QE Firmware                     128KB
-
-SD Card memory Map on T104xRDB
-------------------------------------------
- Block		#blocks		Definition			Size
-0x008		2048		u-boot                          1MB
-0x800		0024		u-boot env                      8KB
-0x820		0256		FMAN Ucode                      128KB
-0x920		0256		QE Firmware                     128KB
-
-SPI Flash memory Map on T104xRDB
-------------------------------------------
- Start		 End		Definition			Size
-0x000000	0x0FFFFF	u-boot                          1MB
-0x100000	0x101FFF	u-boot env                      8KB
-0x110000	0x12FFFF	FMAN Ucode                      128KB
-0x130000	0x14FFFF	QE Firmware                     128KB
-
-Please note QE Firmware is only valid for T1040RDB
-
-
-Switch Settings: (ON is 0, OFF is 1)
-===============
-NAND boot SW setting:
-SW1: 10001000
-SW2: 00111001
-SW3: 11110001
-
-SPI boot SW setting:
-SW1: 00100010
-SW2: 10111001
-SW3: 11100001
-
-SD boot SW setting:
-SW1: 00100000
-SW2: 00111001
-SW3: 11100001
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/cpld.c b/qemu/roms/u-boot/board/freescale/t104xrdb/cpld.c
deleted file mode 100644
index df0e348d4..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/cpld.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/**
- * Copyright 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * This file provides support for the board-specific CPLD used on some Freescale
- * reference boards.
- *
- * The following macros need to be defined:
- *
- * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
-	return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
-	out_8(p + reg, value);
-}
-
-/**
- * Set the boot bank to the alternate bank
- */
-void cpld_set_altbank(void)
-{
-	u8 reg = CPLD_READ(flash_ctl_status);
-
-	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
-
-	CPLD_WRITE(flash_ctl_status, reg);
-	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
-}
-
-/**
- * Set the boot bank to the default bank
- */
-void cpld_set_defbank(void)
-{
-	u8 reg = CPLD_READ(flash_ctl_status);
-
-	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
-
-	CPLD_WRITE(flash_ctl_status, reg);
-	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
-}
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
-	printf("cpld_ver	 = 0x%02x\n", CPLD_READ(cpld_ver));
-	printf("cpld_ver_sub	 = 0x%02x\n", CPLD_READ(cpld_ver_sub));
-	printf("hw_ver		 = 0x%02x\n", CPLD_READ(hw_ver));
-	printf("sw_ver		 = 0x%02x\n", CPLD_READ(sw_ver));
-	printf("reset_ctl1	 = 0x%02x\n", CPLD_READ(reset_ctl1));
-	printf("reset_ctl2	 = 0x%02x\n", CPLD_READ(reset_ctl2));
-	printf("int_status	 = 0x%02x\n", CPLD_READ(int_status));
-	printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
-	printf("fan_ctl_status	 = 0x%02x\n", CPLD_READ(fan_ctl_status));
-	printf("led_ctl_status	 = 0x%02x\n", CPLD_READ(led_ctl_status));
-	printf("sfp_ctl_status	 = 0x%02x\n", CPLD_READ(sfp_ctl_status));
-	printf("misc_ctl_status	 = 0x%02x\n", CPLD_READ(misc_ctl_status));
-	printf("boot_override	 = 0x%02x\n", CPLD_READ(boot_override));
-	printf("boot_config1	 = 0x%02x\n", CPLD_READ(boot_config1));
-	printf("boot_config2	 = 0x%02x\n", CPLD_READ(boot_config2));
-	putc('\n');
-}
-#endif
-
-int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int rc = 0;
-
-	if (argc <= 1)
-		return cmd_usage(cmdtp);
-
-	if (strcmp(argv[1], "reset") == 0) {
-		if (strcmp(argv[2], "altbank") == 0)
-			cpld_set_altbank();
-		else
-			cpld_set_defbank();
-#ifdef DEBUG
-	} else if (strcmp(argv[1], "dump") == 0) {
-		cpld_dump_regs();
-#endif
-	} else
-		rc = cmd_usage(cmdtp);
-
-	return rc;
-}
-
-U_BOOT_CMD(
-	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
-	"Reset the board or alternate bank",
-	"reset - hard reset to default bank\n"
-	"cpld reset altbank - reset to alternate bank\n"
-#ifdef DEBUG
-	"cpld dump - display the CPLD registers\n"
-#endif
-	);
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/cpld.h b/qemu/roms/u-boot/board/freescale/t104xrdb/cpld.h
deleted file mode 100644
index 0da9a0159..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/cpld.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/**
- * Copyright 2013 Freescale Semiconductor
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/*
- * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
- */
-struct cpld_data {
-	u8 cpld_ver;		/* 0x00 - CPLD Major Revision Register */
-	u8 cpld_ver_sub;	/* 0x01 - CPLD Minor Revision Register */
-	u8 hw_ver;		/* 0x02 - Hardware Revision Register */
-	u8 sw_ver;		/* 0x03 - Software Revision register */
-	u8 res0[12];		/* 0x04 - 0x0F - not used */
-	u8 reset_ctl1;		/* 0x10 - Reset control Register1 */
-	u8 reset_ctl2;		/* 0x11 - Reset control Register2 */
-	u8 int_status;		/* 0x12 - Interrupt status Register */
-	u8 flash_ctl_status;	/* 0x13 - Flash control and status register */
-	u8 fan_ctl_status;	/* 0x14 - Fan control and status register  */
-	u8 led_ctl_status;	/* 0x15 - LED control and status register */
-	u8 sfp_ctl_status;	/* 0x16 - SFP control and status register  */
-	u8 misc_ctl_status;	/* 0x17 - Miscellanies ctrl & status register*/
-	u8 boot_override;	/* 0x18 - Boot override register */
-	u8 boot_config1;	/* 0x19 - Boot config override register*/
-	u8 boot_config2;	/* 0x1A - Boot config override register*/
-} cpld_data_t;
-
-
-/* Pointer to the CPLD register set */
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value)\
-		cpld_write(offsetof(struct cpld_data, reg), value)
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/ddr.c b/qemu/roms/u-boot/board/freescale/t104xrdb/ddr.c
deleted file mode 100644
index 34c9224ad..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/ddr.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-		unsigned int controller_number,
-		unsigned int dimm_number)
-{
-	const char dimm_model[] = "RAW timing DDR";
-
-	if ((controller_number == 0) && (dimm_number == 0)) {
-		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-	}
-
-	return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num > 1) {
-		printf("Not supported controller number %d\n", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	pbsp = udimms[0];
-
-	/* Get clk_adjust according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks &&
-		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found\n");
-		printf("for data rate %lu MT/s\n", ddr_freq);
-		printf("Trying to use the highest speed (%u) parameters\n",
-		       pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-found:
-	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
-		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
-		"wrlvl_ctrl_3 0x%x\n",
-		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
-		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
-		pbsp->wrlvl_ctl_3);
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * rtt and rtt_wr override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 75 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
-}
-
-phys_size_t initdram(int board_type)
-{
-	phys_size_t dram_size;
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
-	puts("Initializing....using SPD\n");
-
-	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-#else
-	dram_size =  fsl_ddr_sdram_size();
-#endif
-	return dram_size;
-}
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/ddr.h b/qemu/roms/u-boot/board/freescale/t104xrdb/ddr.h
deleted file mode 100644
index 09b30b9aa..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/ddr.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-dimm_params_t ddr_raw_timing = {
-	.n_ranks = 2,
-	.rank_density = 2147483648u,
-	.capacity = 4294967296u,
-	.primary_sdram_width = 64,
-	.ec_sdram_width = 8,
-	.registered_dimm = 0,
-	.mirrored_dimm = 0,
-	.n_row_addr = 15,
-	.n_col_addr = 10,
-	.n_banks_per_sdram_device = 8,
-	.edc_config = 2,	/* ECC */
-	.burst_lengths_bitmask = 0x0c,
-	.tckmin_x_ps = 1071,
-	.caslat_x = 0xfe << 4,	/* 5,6,7,8,9,10,11 */
-	.taa_ps = 13125,
-	.twr_ps = 15000,
-	.trcd_ps = 13125,
-	.trrd_ps = 6000,
-	.trp_ps = 13125,
-	.tras_ps = 34000,
-	.trc_ps = 48125,
-	.trfc_ps = 260000,
-	.twtr_ps = 7500,
-	.trtp_ps = 7500,
-	.refresh_rate_ps = 7800000,
-	.tfaw_ps = 35000,
-};
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 rank_gb;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl
-	 * ranks| mhz| GB  |adjst| start |   ctl2
-	 */
-	{2,  833,  4, 4,     6, 0x06060607, 0x08080807},
-	{2,  833,  0, 4,     6, 0x06060607, 0x08080807},
-	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{1,  833,  4, 4,     6, 0x06060607, 0x08080807},
-	{1,  833,  0, 4,     6, 0x06060607, 0x08080807},
-	{1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{}
-};
-
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-#endif
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/eth.c b/qemu/roms/u-boot/board/freescale/t104xrdb/eth.c
deleted file mode 100644
index 63e5f900d..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/eth.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/immap_85xx.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <asm/fsl_dtsec.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	struct memac_mdio_info memac_mdio_info;
-	unsigned int i;
-	int phy_addr = 0;
-	printf("Initializing Fman\n");
-
-	memac_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the real 1G MDIO bus */
-	fm_memac_mdio_init(bis, &memac_mdio_info);
-
-	/*
-	 * Program on board RGMII, SGMII PHY addresses.
-	 */
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		int idx = i - FM1_DTSEC1;
-
-		switch (fm_info_get_enet_if(i)) {
-#ifdef CONFIG_T1040RDB
-		case PHY_INTERFACE_MODE_SGMII:
-			/* T1040RDB only supports SGMII on DTSEC3 */
-			fm_info_set_phy_address(FM1_DTSEC3,
-						CONFIG_SYS_SGMII1_PHY_ADDR);
-			break;
-#endif
-		case PHY_INTERFACE_MODE_RGMII:
-			if (FM1_DTSEC4 == i)
-				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
-			if (FM1_DTSEC5 == i)
-				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
-			fm_info_set_phy_address(i, phy_addr);
-			break;
-		case PHY_INTERFACE_MODE_QSGMII:
-			fm_info_set_phy_address(i, 0);
-			break;
-		case PHY_INTERFACE_MODE_NONE:
-			fm_info_set_phy_address(i, 0);
-			break;
-		default:
-			printf("Fman1: DTSEC%u set to unknown interface %i\n",
-			       idx + 1, fm_info_get_enet_if(i));
-			fm_info_set_phy_address(i, 0);
-			break;
-		}
-		fm_info_set_mdio(i,
-				 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-	}
-
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/law.c b/qemu/roms/u-boot/board/freescale/t104xrdb/law.c
deleted file mode 100644
index 2362d4324..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/law.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SYS_NO_FLASH
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/pci.c b/qemu/roms/u-boot/board/freescale/t104xrdb/pci.c
deleted file mode 100644
index c53e3b76a..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/spl.c b/qemu/roms/u-boot/board/freescale/t104xrdb/spl.c
deleted file mode 100644
index c628c95f2..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/spl.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
-	return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	return CONFIG_DDR_CLK_FREQ;
-}
-
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK	0xFF800000
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio, sys_clk, uart_clk;
-#ifdef CONFIG_SPL_NAND_BOOT
-	u32 porsr1, pinctl;
-#endif
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#ifdef CONFIG_SPL_NAND_BOOT
-	/*
-	 * There is T1040 SoC issue where NOR, FPGA are inaccessible during
-	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
-	 * This workaround changes RCW source to make all signals enabled.
-	 */
-	porsr1 = in_be32(&gur->porsr1);
-	pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
-	out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
-#endif
-
-	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
-	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
-	/* Update GD pointer */
-	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
-	/* compiler optimization barrier needed for GCC >= 3.4 */
-	__asm__ __volatile__("" : : : "memory");
-
-	console_init_f();
-
-	/* initialize selected port with appropriate baud rate */
-	sys_clk = get_board_sys_clk();
-	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	uart_clk = sys_clk * plat_ratio / 2;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     uart_clk / 16 / CONFIG_BAUDRATE);
-
-	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	bd_t *bd;
-
-	bd = (bd_t *)(gd + sizeof(gd_t));
-	memset(bd, 0, sizeof(bd_t));
-	gd->bd = bd;
-	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
-	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
-
-	probecpu();
-	get_clocks();
-	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
-			CONFIG_SPL_RELOC_MALLOC_SIZE);
-
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_initialize(bd);
-#endif
-
-	/* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
-	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			    (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			   (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
-	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			   (uchar *)CONFIG_ENV_ADDR);
-#endif
-	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
-	gd->env_valid = 1;
-
-	i2c_init_all();
-
-	puts("\n\n");
-
-	gd->ram_size = initdram(0);
-
-#ifdef CONFIG_SPL_MMC_BOOT
-	mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
-	spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
-	nand_boot();
-#endif
-}
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/t1040_rcw.cfg b/qemu/roms/u-boot/board/freescale/t104xrdb/t1040_rcw.cfg
deleted file mode 100644
index 3300c184a..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/t1040_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-66000002 80000002 e8106000 01000000
-00000000 00000000 00000000 00032810
-00000000 0342500f 00000000 00000000
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/t1042_rcw.cfg b/qemu/roms/u-boot/board/freescale/t104xrdb/t1042_rcw.cfg
deleted file mode 100644
index a3ea8ada5..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/t1042_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0c18000e 0e000000 00000000 00000000
-06000002 00400002 e8106000 01000000
-00000000 00000000 00000000 00030810
-00000000 01fe0a06 00000000 00000000
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/t104x_pbi.cfg b/qemu/roms/u-boot/board/freescale/t104xrdb/t104x_pbi.cfg
deleted file mode 100644
index 7b9e9b05f..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/t104x_pbi.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1
-09000cd0 00000000
-09000cd4 fffc0000
-09000cd8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-091380c0 000FFFFF
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/t104xrdb.c b/qemu/roms/u-boot/board/freescale/t104xrdb/t104xrdb.c
deleted file mode 100644
index fb5b84940..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/t104xrdb.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <asm/mpc85xx_gpio.h>
-
-#include "t104xrdb.h"
-#include "cpld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	struct cpu_type *cpu = gd->arch.cpu;
-	u8 sw;
-
-	printf("Board: %sRDB\n", cpu->name);
-	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
-	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
-
-	sw = CPLD_READ(flash_ctl_status);
-	sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
-
-	if (sw <= 7)
-		printf("vBank: %d\n", sw);
-	else
-		printf("Unsupported Bank=%x\n", sw);
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_SYS_FLASH_BASE
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* invalidate existing TLB entry for flash */
-	disable_tlb(flash_esel);
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
-	set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
-	setup_portals();
-#endif
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = getenv_bootm_low();
-	size = getenv_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-	fdt_fixup_fman_ethernet(blob);
-#endif
-}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-	/* Disable MCKE isolation */
-	gpio_set_value(2, 0);
-	udelay(1);
-}
-#endif
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/t104xrdb.h b/qemu/roms/u-boot/board/freescale/t104xrdb/t104xrdb.h
deleted file mode 100644
index e7cc0c7b5..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/t104xrdb.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __T104x_RDB_H__
-#define __T104x_RDB_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/qemu/roms/u-boot/board/freescale/t104xrdb/tlb.c b/qemu/roms/u-boot/board/freescale/t104xrdb/tlb.c
deleted file mode 100644
index 95c15aa59..000000000
--- a/qemu/roms/u-boot/board/freescale/t104xrdb/tlb.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-	/*
-	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
-	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_256K, 1),
-#else
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/* *I*G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 5, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 7, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
-	/*
-	 * *I*G - NAND
-	 * entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so we use entry 16 for nand.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 11, BOOKE_PAGESZ_256K, 1),
-#endif
-
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 12, BOOKE_PAGESZ_1G, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 13, BOOKE_PAGESZ_1G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);