diff options
| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/board/freescale/p1023rds/bcsr.h | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/board/freescale/p1023rds/bcsr.h')
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1023rds/bcsr.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/freescale/p1023rds/bcsr.h b/qemu/roms/u-boot/board/freescale/p1023rds/bcsr.h new file mode 100644 index 000000000..a9deb72f7 --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/p1023rds/bcsr.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * Authors: Chunhe Lan <b25806@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BCSR_H_ +#define __BCSR_H_ + +#include <common.h> + +/* + * BCSR Bit definitions + * BCSR 15 * + 0 device insertion oriention + 1 stack processor present + 2 power supply shut down/normal operation + 3 I2C bus0 drive enable + 4 reserved + 5:7 I2C bus0 select + 5 - I2C_BUS_0_SS0 + 6 - I2C_BUS_0_SS1 + 7 - I2C_BUS_0_SS2 +*/ + +/* BCSR register base address is 0xFX000020 */ +#define BCSR_BASE_REG_OFFSET 0x20 +#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET) + +#define BCSR15_DEV_INS_ORI 0x80 +#define BCSR15_STACK_PRO_PRE 0x40 +#define BCSR15_POWER_SUPPLY 0x20 +#define BCSR15_I2C_BUS0_EN 0x10 +#define BCSR15_I2C_BUS0_SEG0 0x00 +#define BCSR15_I2C_BUS0_SEG1 0x04 +#define BCSR15_I2C_BUS0_SEG2 0x02 +#define BCSR15_I2C_BUS0_SEG3 0x06 +#define BCSR15_I2C_BUS0_SEG4 0x01 +#define BCSR15_I2C_BUS0_SEG5 0x05 +#define BCSR15_I2C_BUS0_SEG6 0x03 +#define BCSR15_I2C_BUS0_SEG7 0x07 +#define BCSR15_I2C_BUS0_SEG_CLR 0x07 +#define BCSR19_SGMII_SEL_L 0x01 + +/*BCSR Utils functions*/ +void fixup_i2c_bus0_sel_seg0(void); +#endif /* __BCSR_H_ */ |