Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

5 files changed, 0 insertions, 589 deletions

diff --git a/qemu/roms/u-boot/board/freescale/mpc8641hpcn/Makefile b/qemu/roms/u-boot/board/freescale/mpc8641hpcn/Makefile
deleted file mode 100644
index 86c70bcb9..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc8641hpcn/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= mpc8641hpcn.o
-obj-y	+= law.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/qemu/roms/u-boot/board/freescale/mpc8641hpcn/README b/qemu/roms/u-boot/board/freescale/mpc8641hpcn/README
deleted file mode 100644
index d8fe0a4a1..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc8641hpcn/README
+++ /dev/null
@@ -1,186 +0,0 @@
-Freescale MPC8641HPCN board
-===========================
-
-Created 05/24/2006 Haiying Wang
--------------------------------
-
-1. Building U-Boot
-------------------
-The 86xx HPCN code base is known to compile using:
-    Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
-
-    $ make MPC8641HPCN_config
-    Configuring for MPC8641HPCN board...
-
-    $ make
-
-
-2. Switch and Jumper Setting
-----------------------------
-Jumpers:
-	J14 Pins 1-2 (near plcc32 socket)
-
-Switches:
-	SW1(1-5) = 01100	CONFIG_SYS_COREPLL	= 01000 :: CORE =   2:1
-						  01100 :: CORE = 2.5:1
-						  10000 :: CORE =   3:1
-						  11100 :: CORE = 3.5:1
-						  10100 :: CORE =   4:1
-						  01110 :: CORE = 4.5:1
-	SW1(6-8) = 001		CONFIG_SYS_SYSCLK	= 000	:: SYSCLK = 33MHz
-						  001	:: SYSCLK = 40MHz
-
-	SW2(1-4) = 1100		CONFIG_SYS_CCBPLL	= 0010	:: 2X
-						  0100	:: 4X
-						  0110	:: 6X
-						  1000	:: 8X
-						  1010	:: 10X
-						  1100	:: 12X
-						  1110	:: 14X
-						  0000	:: 16X
-	SW2(5-8) = 1110		CONFIG_SYS_BOOTLOC	= 1110	:: boot 16-bit localbus
-
-	SW3(1-7) = 0011000	CONFIG_SYS_VID		= 0011000 :: VCORE = 1.2V
-						  0100000 :: VCORE = 1.11V
-	SW3(8)	 = 0		VCC_PLAT	= 0	:: VCC_PLAT = 1.2V
-						  1	:: VCC_PLAT = 1.0V
-
-	SW4(1-2) = 11		CONFIG_SYS_HOSTMODE	= 11	:: both prots host/root
-	SW4(3-4) = 11		CONFIG_SYS_BOOTSEQ	= 11	:: no boot seq
-	SW4(5-8) = 0011		CONFIG_SYS_IOPORT	= 0011	:: both PEX
-
-	SW5(1)	 = 1		CONFIG_SYS_FLASHMAP	= 1	:: boot from flash
-						  0	:: boot from PromJet
-	SW5(2)	 = 1		CONFIG_SYS_FLASHBANK	= 1	:: swap upper/lower
-							 halves (virtual banks)
-						  0	:: normal
-	SW5(3)	 = 0		CONFIG_SYS_FLASHWP	= 0	:: not protected
-	SW5(4)	 = 0		CONFIG_SYS_PORTDIV	= 1	:: 2:1 for PD4
-							   1:1 for PD6
-	SW5(5-6) = 11		CONFIG_SYS_PIXISOPT	= 11	:: s/w determined
-	SW5(7-8) = 11		CONFIG_SYS_LADOPT	= 11	:: s/w determined
-
-	SW6(1)	 = 1		CONFIG_SYS_CPUBOOT	= 1	:: no boot holdoff
-	SW6(2)	 = 1		CONFIG_SYS_BOOTADDR	= 1	:: no traslation
-	SW6(3-5) = 000		CONFIG_SYS_REFCLKSEL	= 000	:: 100MHZ
-	SW6(6)	 = 1		CONFIG_SYS_SERROM_ADDR= 1	::
-	SW6(7)	 = 1		CONFIG_SYS_MEMDEBUG	= 1	::
-	SW6(8)	 = 1		CONFIG_SYS_DDRDEBUG	= 1	::
-
-	SW8(1)	 = 1		ACZ_SYNC	= 1	:: 48MHz on TP49
-	SW8(2)	 = 1		ACB_SYNC	= 1	:: THRMTRIP disabled
-	SW8(3)	 = 1		ACZ_SDOUT	= 1	:: p4 mode
-	SW8(4)	 = 1		ACB_SDOUT	= 1	:: PATA freq. = 133MHz
-	SW8(5)	 = 0		SUSLED		= 0	:: SouthBridge Mode
-	SW8(6)	 = 0		SPREAD		= 0	:: REFCLK SSCG Disabled
-	SW8(7)	 = 1		ACPWR		= 1	:: non-battery
-	SW8(8)	 = 0		CONFIG_SYS_IDWP	= 0	:: write enable
-
-
-3. Flash U-Boot
----------------
-The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
-It is possible to use either half to boot using u-boot.  Switch 5 bit 2
-is used for this purpose.
-
-0xEF800000 to 0xEFBFFFFF - 4MB
-0xEFC00000 to 0xEFFFFFFF - 4MB
-When this bit is 0, U-Boot is at 0xEFF00000.
-When this bit is 1, U-Boot is at 0xEFB00000.
-
-Use the above mentioned flash commands to program the other half, and
-use switch 5, bit 2 to alternate between the halves.  Note: The booting
-version of U-Boot will always be at 0xEFF00000.
-
-To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
-
-	tftp 1000000 u-boot.bin
-	protect off all
-	erase eff00000 +$filesize
-	cp.b 1000000 eff00000 $filesize
-
-or use tftpflash command:
-	run tftpflash
-
-To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
-
-	tftp 1000000 u-boot.bin
-	erase efb00000 +$filesize
-	cp.b 1000000 efb00000 $filesize
-
-
-4. Memory Map
--------------
-NOTE:  RIO and PCI are mutually exclusive, so they share an address
-
-For 32-bit u-boot, devices are mapped so that the virtual address ==
-the physical address, and the map looks liks this:
-
-	Memory Range			Device		Size
-	------------			------		----
-	0x0000_0000	0x7fff_ffff	DDR		2G
-	0x8000_0000	0x9fff_ffff	RIO MEM		512M
-	0x8000_0000	0x9fff_ffff	PCI1/PEX1 MEM	512M
-	0xa000_0000	0xbfff_ffff	PCI2/PEX2 MEM	512M
-	0xffe0_0000	0xffef_ffff	CCSR		1M
-	0xffdf_0000	0xffdf_7fff	PIXIS		8K
-	0xffdf_8000	0xffdf_ffff	CF		8K
-	0xf840_0000	0xf840_3fff	Stack space	32K
-	0xffc0_0000	0xffc0_ffff	PCI1/PEX1 IO	64K
-	0xffc1_0000	0xffc1_ffff	PCI2/PEX2 IO	64K
-	0xef80_0000	0xefff_ffff	Flash		8M
-
-For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
-However, the physical map is altered to reside in 36-bit space, as follows.
-Addresses are no longer mapped with VA == PA.  All accesses from
-software use the VA; the PA is only used for setting up windows
-and mappings. Note that with the exception of PCI MEM and RIO, the low
- 32 bits are the same as the VA above; only the top 4 bits vary:
-
-	Memory Range			Device		Size
-	------------			------		----
-	0x0_0000_0000	0x0_7fff_ffff	DDR		2G
-	0xc_0000_0000	0xc_1fff_ffff	RIO MEM		512M
-	0xc_0000_0000	0xc_1fff_ffff	PCI1/PEX1 MEM	512M
-	0xc_2000_0000	0xc_3fff_ffff	PCI2/PEX2 MEM	512M
-	0xf_ffe0_0000	0xf_ffef_ffff	CCSR		1M
-	0xf_ffdf_0000	0xf_ffdf_7fff	PIXIS		8K
-	0xf_ffdf_8000	0xf_ffdf_ffff	CF		8K
-	0x0_f840_0000	0xf_f840_3fff	Stack space	32K
-	0xf_ffc0_0000	0xf_ffc0_ffff	PCI1/PEX1 IO	64K
-	0xf_ffc1_0000	0xf_ffc1_ffff	PCI2/PEX2 IO	64K
-	0xf_ef80_0000	0xf_efff_ffff	Flash		8M
-
-5. pixis_reset command
---------------------
-A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
-using the FPGA sequencer.  When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
-	pixis_reset
-	pixis_reset altbank
-	pixis_reset altbank wd
-	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
-	/* reset to current bank, like "reset" command */
-	pixis_reset
-
-	/* reset board but use the to alternate flash bank */
-	pixis_reset altbank
-
-	/* reset board, use alternate flash bank with watchdog timer enabled*/
-	pixis_reset altbank wd
-
-	/* reset board to alternate bank with frequency changed.
-	 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
-	 */
-	pixis-reset altbank cf 40 2.5 10
-
-Valid clock choices are in the 8641 Reference Manuals.
diff --git a/qemu/roms/u-boot/board/freescale/mpc8641hpcn/ddr.c b/qemu/roms/u-boot/board/freescale/mpc8641hpcn/ddr.c
deleted file mode 100644
index 7cd039565..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc8641hpcn/ddr.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2008,2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;
-	u32 cpo;
-	u32 write_data_delay;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-const struct board_specific_parameters dimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| cpo|wrdata|2T
-	 * ranks| mhz|adjst|    | delay|
-	 */
-	{4,  333,    7,   7,     3},
-	{4,  549,    7,   9,     3},
-	{4,  650,    7,  10,     4},
-	{2,  333,    7,   7,     3},
-	{2,  549,    7,   9,     3},
-	{2,  650,    7,  10,     4},
-	{1,  333,    7,   7,     3},
-	{1,  549,    7,   9,     3},
-	{1,  650,    7,  10,     4},
-	{}
-};
-
-/*
- * The two slots have slightly different timing. The center values are good
- * for both slots. We use identical speed tables for them. In future use, if
- * DIMMs have fewer center values that require two separated tables, copy the
- * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
- */
-const struct board_specific_parameters *dimms[] = {
-	dimm0,
-	dimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-			dimm_params_t *pdimm,
-			unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	unsigned int i;
-	ulong ddr_freq;
-
-	if (ctrl_num > 1) {
-		printf("Wrong parameter for controller number %d", ctrl_num);
-		return;
-	}
-	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
-		if (pdimm[i].n_ranks)
-			break;
-	}
-	if (i >= CONFIG_DIMM_SLOTS_PER_CTLR)    /* no DIMM */
-		return;
-
-	pbsp = dimms[ctrl_num];
-
-	/* Get clk_adjust, cpo, write_data_delay, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm[i].n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s!\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-
-found:
-	/* 2T timing enable */
-	popts->twot_en = 1;
-}
diff --git a/qemu/roms/u-boot/board/freescale/mpc8641hpcn/law.c b/qemu/roms/u-boot/board/freescale/mpc8641hpcn/law.c
deleted file mode 100644
index 6d25c76cc..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc8641hpcn/law.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000     0x9fff_ffff     PCIE1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCIE2 MEM                512M
- * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000     0x9fff_ffff     RapidIO                 512M
- * endif
- * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
- * 0xffc0_0000     0xffc0_ffff     PCIE1 IO                 64K
- * 0xffc1_0000     0xffc1_ffff     PCIE2 IO                 64K
- * 0xffe0_0000     0xffef_ffff     CCSRBAR                 1M
- * 0xffdf_0000     0xffe0_0000     PIXIS, CF               64K
- * 0xef80_0000     0xefff_ffff     FLASH (boot bank)       8M
- *
- * Notes:
- *    CCSRBAR doesn't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
-#endif
-	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/qemu/roms/u-boot/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/qemu/roms/u-boot/board/freescale/mpc8641hpcn/mpc8641hpcn.c
deleted file mode 100644
index a58b5f9cd..000000000
--- a/qemu/roms/u-boot/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-
-phys_size_t fixed_sdram(void);
-
-int checkboard(void)
-{
-	u8 vboot;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
-		in_8(pixis_base + PIXIS_PVER));
-
-	vboot = in_8(pixis_base + PIXIS_VBOOT);
-	if (vboot & PIXIS_VBOOT_FMAP)
-		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
-	else
-		puts ("Promjet\n");
-
-	return 0;
-}
-
-phys_size_t
-initdram(int board_type)
-{
-	phys_size_t dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = fsl_ddr_sdram();
-#else
-	dram_size = fixed_sdram();
-#endif
-
-	setup_ddr_bat(dram_size);
-
-	debug("    DDR: ");
-	return dram_size;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t
-fixed_sdram(void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
-	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
-	ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
-	ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
-
-#if defined (CONFIG_DDR_ECC)
-	ddr->err_disable = 0x0000008D;
-	ddr->err_sbe = 0x00ff0000;
-#endif
-	asm("sync;isync");
-
-	udelay(500);
-
-#if defined (CONFIG_DDR_ECC)
-	/* Enable ECC checking */
-	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
-#else
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-#endif
-	asm("sync; isync");
-
-	udelay(500);
-#endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif	/* !defined(CONFIG_SPD_EEPROM) */
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCIE1
-		/*
-		 * Activate ULI1575 legacy chip by performing a fake
-		 * memory access.  Needed to make ULI RTC work.
-		 */
-		in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
-				       + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
-#endif /* CONFIG_PCIE1 */
-}
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
-	int off;
-	u64 *tmp;
-	u32 *addrcells;
-
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-	/*
-	 * Warn if it looks like the device tree doesn't match u-boot.
-	 * This is just an estimation, based on the location of CCSR,
-	 * which is defined by the "reg" property in the soc node.
-	 */
-	off = fdt_path_offset(blob, "/soc8641");
-	addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
-	tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
-
-	if (tmp) {
-		u64 addr;
-		if (addrcells && (*addrcells == 1))
-			addr = *(u32 *)tmp;
-		else
-			addr = *tmp;
-
-		if (addr != CONFIG_SYS_CCSRBAR_PHYS)
-			printf("WARNING: The CCSRBAR address in your .dts "
-			       "does not match the address of the CCSR "
-			       "in u-boot.  This means your .dts might "
-			       "be old.\n");
-	}
-}
-#endif
-
-
-/*
- * get_board_sys_clk
- *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
-	u8 i, go_bit, rd_clks;
-	ulong val = 0;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	go_bit = in_8(pixis_base + PIXIS_VCTL);
-	go_bit &= 0x01;
-
-	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
-	rd_clks &= 0x1C;
-
-	/*
-	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
-	 * should we be using the AUX register. Remember, we also set the
-	 * GO bit to boot from the alternate bank on the on-board flash
-	 */
-
-	if (go_bit) {
-		if (rd_clks == 0x1c)
-			i = in_8(pixis_base + PIXIS_AUX);
-		else
-			i = in_8(pixis_base + PIXIS_SPD);
-	} else {
-		i = in_8(pixis_base + PIXIS_SPD);
-	}
-
-	i &= 0x07;
-
-	switch (i) {
-	case 0:
-		val = 33000000;
-		break;
-	case 1:
-		val = 40000000;
-		break;
-	case 2:
-		val = 50000000;
-		break;
-	case 3:
-		val = 66000000;
-		break;
-	case 4:
-		val = 83000000;
-		break;
-	case 5:
-		val = 100000000;
-		break;
-	case 6:
-		val = 134000000;
-		break;
-	case 7:
-		val = 166000000;
-		break;
-	}
-
-	return val;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	/* Initialize TSECs */
-	cpu_eth_init(bis);
-	return pci_eth_init(bis);
-}
-
-void board_reset(void)
-{
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	out_8(pixis_base + PIXIS_RST, 0);
-
-	while (1)
-		;
-}