diff options
| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/board/freescale/mpc8569mds/bcsr.c | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/board/freescale/mpc8569mds/bcsr.c')
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/mpc8569mds/bcsr.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/freescale/mpc8569mds/bcsr.c b/qemu/roms/u-boot/board/freescale/mpc8569mds/bcsr.c new file mode 100644 index 000000000..178d9f873 --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/mpc8569mds/bcsr.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +#include "bcsr.h" + +void enable_8569mds_flash_write(void) +{ + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); +} + +void disable_8569mds_flash_write(void) +{ + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); +} + +void enable_8569mds_qe_uec(void) +{ +#if defined(CONFIG_SYS_UCC_RGMII_MODE) + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), + BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), + BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), + BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), + BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); +#elif defined(CONFIG_SYS_UCC_RMII_MODE) + /* Set UCC1-4 working at RMII mode */ + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), + BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), + BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), + BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), + BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN); +#endif +} + +void disable_8569mds_brd_eeprom_write_protect(void) +{ + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT); +} |