Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

3 files changed, 202 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/freescale/m5235evb/Makefile b/qemu/roms/u-boot/board/freescale/m5235evb/Makefile
new file mode 100644
index 000000000..e77d9d95b
--- /dev/null
+++ b/qemu/roms/u-boot/board/freescale/m5235evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= m5235evb.o
diff --git a/qemu/roms/u-boot/board/freescale/m5235evb/m5235evb.c b/qemu/roms/u-boot/board/freescale/m5235evb/m5235evb.c
new file mode 100644
index 000000000..68c1631f8
--- /dev/null
+++ b/qemu/roms/u-boot/board/freescale/m5235evb/m5235evb.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M5235 EVB\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+	u32 dramsize, i, dramclk;
+
+	/*
+	 * When booting from external Flash, the port-size is less than
+	 * the port-size of SDRAM.  In this case it is necessary to enable
+	 * Data[15:0] on Port Address/Data.
+	 */
+	out_8(&gpio->par_ad,
+		GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
+		GPIO_PAR_AD_DATAL);
+
+	/* Initialize PAR to enable SDRAM signals */
+	out_8(&gpio->par_sdram,
+		GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
+		GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
+		GPIO_PAR_SDRAM_SDCS(3));
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
+		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
+
+		/* Initialize DRAM Control Register: DCR */
+		out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
+			SDRAMC_DCR_RTIM_6CLKS |
+			SDRAMC_DCR_RC((15 * dramclk) >> 4));
+
+		/* Initialize DACR0 */
+		out_be32(&sdram->dacr0,
+			SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+			SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
+			SDRAMC_DARCn_PS_32);
+		asm("nop");
+
+		/* Initialize DMR0 */
+		out_be32(&sdram->dmr0,
+			((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
+		asm("nop");
+
+		/* Set IP (bit 3) in DACR */
+		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
+
+		/* Wait 30ns to allow banks to precharge */
+		for (i = 0; i < 5; i++) {
+			asm("nop");
+		}
+
+		/* Write to this block to initiate precharge */
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+
+		/*  Set RE (bit 15) in DACR */
+		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
+
+		/* Wait for at least 8 auto refresh cycles to occur */
+		for (i = 0; i < 0x2000; i++) {
+			asm("nop");
+		}
+
+		/* Finish the configuration by issuing the MRS. */
+		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
+		asm("nop");
+
+		/* Write to the SDRAM Mode Register */
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+	}
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/qemu/roms/u-boot/board/freescale/m5235evb/u-boot.lds b/qemu/roms/u-boot/board/freescale/m5235evb/u-boot.lds
new file mode 100644
index 000000000..ccfb5d6b1
--- /dev/null
+++ b/qemu/roms/u-boot/board/freescale/m5235evb/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+  .text      :
+  {
+    arch/m68k/cpu/mcf523x/start.o		(.text*)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o      (.text)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    KEEP(*(.got))
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)      :
+  {
+   _sbss = .;
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}