Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

3 files changed, 174 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/faraday/a320evb/Makefile b/qemu/roms/u-boot/board/faraday/a320evb/Makefile
new file mode 100644
index 000000000..518ce3fcb
--- /dev/null
+++ b/qemu/roms/u-boot/board/faraday/a320evb/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= a320evb.o
+obj-y	+= lowlevel_init.o
diff --git a/qemu/roms/u-boot/board/faraday/a320evb/a320evb.c b/qemu/roms/u-boot/board/faraday/a320evb/a320evb.c
new file mode 100644
index 000000000..c42635b70
--- /dev/null
+++ b/qemu/roms/u-boot/board/faraday/a320evb/a320evb.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_1;
+	unsigned long expected_size = PHYS_SDRAM_1_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else
+		return 0;
+}
diff --git a/qemu/roms/u-boot/board/faraday/a320evb/lowlevel_init.S b/qemu/roms/u-boot/board/faraday/a320evb/lowlevel_init.S
new file mode 100644
index 000000000..d366260a8
--- /dev/null
+++ b/qemu/roms/u-boot/board/faraday/a320evb/lowlevel_init.S
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/macro.h>
+#include <faraday/ftsdmc020.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define TP0_A		(CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
+#define TP1_A		(CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
+#define CR_A		(CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
+#define B0_BSR_A	(CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
+#define ACR_A		(CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
+
+#define TP0_D		CONFIG_SYS_FTSDMC020_TP0
+#define TP1_D		CONFIG_SYS_FTSDMC020_TP1
+#define CR_D1		FTSDMC020_CR_IPREC
+#define CR_D2		FTSDMC020_CR_ISMR
+#define CR_D3		FTSDMC020_CR_IREF
+
+#define B0_BSR_D	(CONFIG_SYS_FTSDMC020_BANK0_BSR | \
+			FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
+#define ACR_D		FTSDMC020_ACR_TOC(0x18)
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro	wait_sdram
+	ldr	r0, =CONFIG_FTSDMC020_BASE
+1:
+	ldr	r1, [r0, #FTSDMC020_OFFSET_CR]
+	cmp	r1, #0
+	bne	1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+	mov	r11, lr
+
+	led	0x0
+
+	bl	init_sdmc
+
+	led	0x1
+
+	/* everything is fine now */
+	mov	lr, r11
+	mov	pc, lr
+
+/*
+ * memory initialization
+ */
+init_sdmc:
+	led	0x10
+
+	/* set SDRAM register */
+
+	write32	TP0_A, TP0_D
+	led	0x11
+
+	write32	TP1_A, TP1_D
+	led	0x12
+
+	/* set to precharge */
+	write32	CR_A, CR_D1
+	led	0x13
+
+	wait_sdram
+	led	0x14
+
+	/* set mode register */
+	write32	CR_A, CR_D2
+	led	0x15
+
+	wait_sdram
+	led	0x16
+
+	/* set to refresh */
+	write32	CR_A, CR_D3
+	led	0x17
+
+	wait_sdram
+	led	0x18
+
+	write32	B0_BSR_A, B0_BSR_D
+	led	0x19
+
+	write32	ACR_A, ACR_D
+	led	0x1a
+
+	mov	pc, lr