Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

6 files changed, 472 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/exmeritus/hww1u1a/Makefile b/qemu/roms/u-boot/board/exmeritus/hww1u1a/Makefile
new file mode 100644
index 000000000..d0cd87828
--- /dev/null
+++ b/qemu/roms/u-boot/board/exmeritus/hww1u1a/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= hww1u1a.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-$(CONFIG_DDR_SPD) += ddr.o
diff --git a/qemu/roms/u-boot/board/exmeritus/hww1u1a/ddr.c b/qemu/roms/u-boot/board/exmeritus/hww1u1a/ddr.c
new file mode 100644
index 000000000..e1f6865f4
--- /dev/null
+++ b/qemu/roms/u-boot/board/exmeritus/hww1u1a/ddr.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2009-2010 eXMeritus, A Boeing Company
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * We only support one DIMM, so according to the P2020 docs we should
+	 * set the options as follows:
+	 */
+	popts->cs_local_opts[0].odt_rd_cfg = 0;
+	popts->cs_local_opts[0].odt_wr_cfg = 4;
+	popts->cs_local_opts[1].odt_rd_cfg = 0;
+	popts->cs_local_opts[1].odt_wr_cfg = 0;
+	popts->half_strength_driver_enable = 0;
+
+	/* Manually configured for our static clock rate */
+	popts->clk_adjust = 4;
+	popts->cpo_override = 4;
+	popts->write_data_delay = 2;
+	popts->twot_en = 0;
+}
diff --git a/qemu/roms/u-boot/board/exmeritus/hww1u1a/gpios.h b/qemu/roms/u-boot/board/exmeritus/hww1u1a/gpios.h
new file mode 100644
index 000000000..499880f1a
--- /dev/null
+++ b/qemu/roms/u-boot/board/exmeritus/hww1u1a/gpios.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2010 eXMeritus, A Boeing Company
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/mpc85xx_gpio.h>
+
+/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */
+#define GPIO_CPU_ID		(1UL << (31 -  8))
+#define GPIO_BLUE_LED		(1UL << (31 -  9))
+#define GPIO_DIMM_RESET		(1UL << (31 - 10))
+#define GPIO_USB_RESET		(1UL << (31 - 11))
+#define GPIO_UNUSED_12		(1UL << (31 - 12))
+#define GPIO_GETH0_RESET	(1UL << (31 - 13))
+#define GPIO_RS422_RE		(1UL << (31 - 14))
+#define GPIO_RS422_DE		(1UL << (31 - 15))
+#define IRQ_I2CINT		(1UL << (31 - 20))
+#define IRQ_FANINT		(1UL << (31 - 21))
+#define IRQ_DIMM_EVENT		(1UL << (31 - 22))
+
+#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET)
+
+/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
+#define GPIO_CPUA_UNUSED_0	(1UL << (31 -  0))
+#define GPIO_CPUA_CPU_READY	(1UL << (31 -  1))
+#define GPIO_CPUA_DEBUG_LED2	(1UL << (31 -  2))
+#define GPIO_CPUA_DEBUG_LED1	(1UL << (31 -  3))
+#define GPIO_CPUA_TDIS2B	(1UL << (31 -  4)) /* MAC 2 TX B */
+#define GPIO_CPUA_TDIS2A	(1UL << (31 -  5)) /* MAC 2 TX A */
+#define GPIO_CPUA_TDIS1B	(1UL << (31 -  6)) /* MAC 1 TX B */
+#define GPIO_CPUA_TDIS1A	(1UL << (31 -  7)) /* MAC 1 TX A */
+#define IRQ_CPUA_UNUSED_0	(1UL << (31 - 16))
+#define IRQ_CPUA_UNUSED_1	(1UL << (31 - 17))
+#define IRQ_CPUA_UNUSED_2	(1UL << (31 - 18))
+#define IRQ_CPUA_UNUSED_3	(1UL << (31 - 19))
+
+/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
+#define GPIO_CPUB_RMUX_SEL1B	(1UL << (31 -  0))
+#define GPIO_CPUB_RMUX_SEL0B	(1UL << (31 -  1))
+#define GPIO_CPUB_RMUX_SEL1A	(1UL << (31 -  2))
+#define GPIO_CPUB_RMUX_SEL0A	(1UL << (31 -  3))
+#define GPIO_CPUB_UNUSED_4	(1UL << (31 -  4))
+#define GPIO_CPUB_CPU_READY	(1UL << (31 -  5))
+#define GPIO_CPUB_DEBUG_LED2	(1UL << (31 -  6))
+#define GPIO_CPUB_DEBUG_LED1	(1UL << (31 -  7))
+#define IRQ_CPUB_SD_1A		(1UL << (31 - 16))
+#define IRQ_CPUB_SD_2B		(1UL << (31 - 17))
+#define IRQ_CPUB_SD_2A		(1UL << (31 - 18))
+#define IRQ_CPUB_SD_1B		(1UL << (31 - 19))
+
+/* If it isn't CPU A then it's CPU B */
+static inline unsigned int hww1u1a_is_cpu_a(void)
+{
+	return !mpc85xx_gpio_get(GPIO_CPU_ID);
+}
diff --git a/qemu/roms/u-boot/board/exmeritus/hww1u1a/hww1u1a.c b/qemu/roms/u-boot/board/exmeritus/hww1u1a/hww1u1a.c
new file mode 100644
index 000000000..97b84b322
--- /dev/null
+++ b/qemu/roms/u-boot/board/exmeritus/hww1u1a/hww1u1a.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright 2009-2011 eXMeritus, A Boeing Company
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <linux/ctype.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <pca953x.h>
+
+#include "gpios.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	unsigned int gpio_high = 0;
+	unsigned int gpio_low  = 0;
+	unsigned int gpio_in   = 0;
+	unsigned int i;
+	struct ccsr_ddr __iomem *ddr;
+
+	puts("Board: HWW-1U-1A ");
+
+	/*
+	 * First just figure out which CPU we're on, then use that to
+	 * configure the lists of other GPIOs to be programmed.
+	 */
+	mpc85xx_gpio_set_in(GPIO_CPU_ID);
+	if (hww1u1a_is_cpu_a()) {
+		puts("CPU A\n");
+
+		/* We want to turn on some LEDs */
+		gpio_high |= GPIO_CPUA_CPU_READY;
+		gpio_low  |= GPIO_CPUA_DEBUG_LED1;
+		gpio_low  |= GPIO_CPUA_DEBUG_LED2;
+
+		/* Disable the unused transmitters */
+		gpio_low  |= GPIO_CPUA_TDIS1A;
+		gpio_high |= GPIO_CPUA_TDIS1B;
+		gpio_low  |= GPIO_CPUA_TDIS2A;
+		gpio_high |= GPIO_CPUA_TDIS2B;
+	} else {
+		puts("CPU B\n");
+
+		/* We want to turn on some LEDs */
+		gpio_high |= GPIO_CPUB_CPU_READY;
+		gpio_low  |= GPIO_CPUB_DEBUG_LED1;
+		gpio_low  |= GPIO_CPUB_DEBUG_LED2;
+
+		/* Enable the appropriate receivers */
+		gpio_high |= GPIO_CPUB_RMUX_SEL0A;
+		gpio_high |= GPIO_CPUB_RMUX_SEL0B;
+		gpio_low  |= GPIO_CPUB_RMUX_SEL1A;
+		gpio_low  |= GPIO_CPUB_RMUX_SEL1B;
+	}
+
+	/* These GPIOs are common */
+	gpio_in   |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT;
+	gpio_low  |= GPIO_RS422_RE;
+	gpio_high |= GPIO_RS422_DE;
+
+	/* Ok, now go ahead and program all of those in one go */
+	mpc85xx_gpio_set(gpio_high|gpio_low|gpio_in,
+			 gpio_high|gpio_low,
+			 gpio_high);
+
+	/*
+	 * If things have been taken out of reset early (for example, by one
+	 * of the BDI3000 debuggers), then we need to put them back in reset
+	 * and delay a while before we continue.
+	 */
+	if (mpc85xx_gpio_get(GPIO_RESETS)) {
+		ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+
+		puts("Debugger detected... extra device reset enabled!\n");
+
+		/* Put stuff into reset and disable the DDR controller */
+		mpc85xx_gpio_set_low(GPIO_RESETS);
+		out_be32(&ddr->sdram_cfg, 0x00000000);
+
+		puts("    Waiting 1 sec for reset...");
+		for (i = 0; i < 10; i++) {
+			udelay(100000);
+			puts(".");
+		}
+		puts("\n");
+	}
+
+	/* Now bring everything back out of reset again */
+	mpc85xx_gpio_set_high(GPIO_RESETS);
+	return 0;
+}
+
+/*
+ * This little shell function just returns whether or not it's CPU A.
+ * It can be used to select the right device-tree when booting, etc.
+ */
+int do_hww1u1a_test_cpu_a(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	if (argc > 1)
+		cmd_usage(cmdtp);
+
+	if (hww1u1a_is_cpu_a())
+		return 0;
+	else
+		return 1;
+}
+U_BOOT_CMD(
+	test_cpu_a, 1, 0, do_hww1u1a_test_cpu_a,
+	"Test if this is CPU A (versus B) on the eXMeritus HWW-1U-1A board",
+	""
+);
+
+/* Create a prompt-like string: "uboot@HOSTNAME% " */
+#define PROMPT_PREFIX "uboot@exm"
+#define PROMPT_SUFFIX "% "
+
+/* This function returns a PS1 prompt based on the serial number */
+static char *hww1u1a_prompt;
+const char *hww1u1a_get_ps1(void)
+{
+	unsigned long len, i, j;
+	const char *serialnr;
+
+	/* If our prompt was already set, just use that */
+	if (hww1u1a_prompt)
+		return hww1u1a_prompt;
+
+	/* Use our serial number if present, otherwise a default */
+	serialnr = getenv("serial#");
+	if (!serialnr || !serialnr[0])
+		serialnr = "999999-X";
+
+	/*
+	 * We will turn the serial number into a hostname by:
+	 *   (A) Delete all non-alphanumerics.
+	 *   (B) Lowercase all letters.
+	 *   (C) Prefix "exm".
+	 *   (D) Suffix "a" for CPU A and "b" for CPU B.
+	 */
+	for (i = 0, len = 0; serialnr[i]; i++) {
+		if (isalnum(serialnr[i]))
+			len++;
+	}
+
+	len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX) + 1; /* Includes NUL */
+	hww1u1a_prompt = malloc(len);
+	if (!hww1u1a_prompt)
+		return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX;
+
+	/* Now actually fill it in */
+	i = 0;
+
+	/* Handle the prefix */
+	for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++)
+		hww1u1a_prompt[i++] = PROMPT_PREFIX[j];
+
+	/* Now the serial# part of the hostname */
+	for (j = 0; serialnr[j]; j++)
+		if (isalnum(serialnr[j]))
+			hww1u1a_prompt[i++] = tolower(serialnr[j]);
+
+	/* Now the CPU id ("a" or "b") */
+	hww1u1a_prompt[i++] = hww1u1a_is_cpu_a() ? 'a' : 'b';
+
+	/* Finally the suffix */
+	for (j = 0; j < sizeof(PROMPT_SUFFIX); j++)
+		hww1u1a_prompt[i++] = PROMPT_SUFFIX[j];
+
+	/* This should all have added up, but just in case */
+	hww1u1a_prompt[len - 1] = '\0';
+
+	/* Now we're done */
+	return hww1u1a_prompt;
+}
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap bootflash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for FLASH */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct tsec_info_struct tsec_info[4];
+	struct fsl_pq_mdio_info mdio_info;
+
+	SET_STD_TSEC_INFO(tsec_info[0], 1);
+	SET_STD_TSEC_INFO(tsec_info[1], 2);
+	SET_STD_TSEC_INFO(tsec_info[2], 3);
+
+	if (hww1u1a_is_cpu_a())
+		tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA;
+	else
+		tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB;
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, 3);
+	return pci_eth_init(bis);
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	FT_FSL_PCI_SETUP;
+}
diff --git a/qemu/roms/u-boot/board/exmeritus/hww1u1a/law.c b/qemu/roms/u-boot/board/exmeritus/hww1u1a/law.c
new file mode 100644
index 000000000..c7dc58d59
--- /dev/null
+++ b/qemu/roms/u-boot/board/exmeritus/hww1u1a/law.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/qemu/roms/u-boot/board/exmeritus/hww1u1a/tlb.c b/qemu/roms/u-boot/board/exmeritus/hww1u1a/tlb.c
new file mode 100644
index 000000000..7f5a36f1e
--- /dev/null
+++ b/qemu/roms/u-boot/board/exmeritus/hww1u1a/tlb.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2009-2010 eXMeritus, A Boeing Company
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  0 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  0 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  4 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  4 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  8 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  8 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      + 12 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Boot page */
+	SET_TLB_ENTRY(1,	CONFIG_BPTR_VIRT_ADDR,
+				CONFIG_BPTR_VIRT_ADDR,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_CCSRBAR,
+				CONFIG_SYS_CCSRBAR_PHYS,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/*
+	 * W**G* - FLASH (Will be *I*G* after relocation to RAM)
+	 *
+	 * This maps both SPI FLASH chips (128MByte per chip)
+	 */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_FLASH_BASE,
+				CONFIG_SYS_FLASH_BASE_PHYS,
+				MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+				0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * *I*G* - PCI memory
+	 *
+	 * We have 1.5GB total PCI-E memory space to map and we want to use
+	 * the minimum possible number of TLB entries.  Since Book-E TLB
+	 * entries are sized in powers of 4, we use 1GB + 256MB + 256MB.
+	 */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT,
+				CONFIG_SYS_PCIE3_MEM_PHYS,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 3, BOOKE_PAGESZ_1G, 1),
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+				CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 4, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+				CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * *I*G* - PCI I/O
+	 *
+	 * This one entry covers all 3 64k PCI-E I/O windows
+	 */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_IO_VIRT,
+				CONFIG_SYS_PCIE3_IO_PHYS,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 6, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);