Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

4 files changed, 2798 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/esd/plu405/Makefile b/qemu/roms/u-boot/board/esd/plu405/Makefile
new file mode 100644
index 000000000..6ffae677b
--- /dev/null
+++ b/qemu/roms/u-boot/board/esd/plu405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= plu405.o flash.o \
+	../common/misc.o \
+	../common/esd405ep_nand.o \
diff --git a/qemu/roms/u-boot/board/esd/plu405/flash.c b/qemu/roms/u-boot/board/esd/plu405/flash.c
new file mode 100644
index 000000000..23e81642e
--- /dev/null
+++ b/qemu/roms/u-boot/board/esd/plu405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	pbcr = mfdcr(EBC0_CFGDATA);
+	mtdcr(EBC0_CFGADDR, PB0CR);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(EBC0_CFGDATA, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CONFIG_SYS_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/qemu/roms/u-boot/board/esd/plu405/fpgadata.c b/qemu/roms/u-boot/board/esd/plu405/fpgadata.c
new file mode 100644
index 000000000..485b9a209
--- /dev/null
+++ b/qemu/roms/u-boot/board/esd/plu405/fpgadata.c
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+0xb7, 0x57, 0xd1, 0xf3, 0xa9, 0x10, 0xee, 0xea,
+0xe8, 0xc9, 0x6f, 0xd5, 0xe6, 0x61, 0x1a, 0x30,
+0x17, 0x7e, 0xdb, 0x06, 0xfb, 0xe0, 0x77, 0x11,
+0x1f, 0x58, 0x73, 0x97, 0x70, 0x1a, 0x81, 0xbf,
+0xa1, 0xe5, 0x1f, 0x5f, 0x97, 0x79, 0x3d, 0xff,
+0xd4, 0x81, 0xc5, 0x15, 0x5f, 0xc1, 0xe0, 0xc9,
+0x03, 0x8b, 0xd7, 0xc6, 0x6f, 0x59, 0x77, 0x62,
+0xcf, 0x53, 0xcd, 0xff, 0x54, 0x11, 0xcf, 0xac,
+0x3b, 0x89, 0xc1, 0x1f, 0xd0, 0xf3, 0x59, 0x76,
+0xef, 0xcd, 0x97, 0xff, 0xe3, 0xc5, 0xf3, 0xef,
+0x5f, 0x5c, 0x89, 0xc1, 0x33, 0xe7, 0x3f, 0xb8,
+0xb8, 0xec, 0xd2, 0xc6, 0x33, 0x0f, 0x5d, 0x3e,
+0xfb, 0xf1, 0xc5, 0x65, 0xf7, 0x6c, 0xbc, 0x8c,
+0xc1, 0xc7, 0xe0, 0x0a, 0x3e, 0x2b, 0xfe, 0xb6,
+0x62, 0x61, 0x66, 0x6d, 0x7e, 0xcf, 0xb6, 0x05,
+0x17, 0xab, 0x7f, 0xd2, 0x79, 0x39, 0xff, 0xeb,
+0x6d, 0x2b, 0xfe, 0x7e, 0xed, 0xbd, 0xaf, 0xad,
+0xcd, 0x3f, 0xf2, 0xf1, 0xca, 0xcb, 0x6b, 0x17,
+0xbd, 0xb6, 0xf6, 0xfc, 0x23, 0x67, 0xe9, 0xf1,
+0x2b, 0xef, 0xb9, 0xf9, 0xcc, 0x43, 0xcf, 0x9c,
+0x7d, 0x9f, 0x4c, 0xc3, 0x9e, 0xd8, 0xd9, 0x0f,
+0xd0, 0xf8, 0x9b, 0xcf, 0x58, 0x33, 0xa4, 0xc7,
+0x37, 0xcd, 0xef, 0x3a, 0xb3, 0xe7, 0xc6, 0xb3,
+0x0f, 0xdc, 0xb6, 0x0c, 0xff, 0xc7, 0x43, 0x67,
+0xdf, 0x7f, 0x1b, 0x81, 0xb7, 0xea, 0x9e, 0x19,
+0x78, 0xff, 0x62, 0x53, 0xca, 0x02, 0xef, 0x7d,
+0xcf, 0x37, 0xa1, 0xbe, 0x5e, 0x7d, 0x9f, 0xba,
+0x48, 0xbd, 0x6f, 0xb4, 0x11, 0x01, 0x70, 0xa3,
+0x5c, 0x71, 0x54, 0xec, 0xd5, 0xe7, 0xaa, 0x8b,
+0xea, 0x2d, 0x80, 0xbe, 0x9a, 0x5b, 0x41, 0xcb,
+0x53, 0x1e, 0xdc, 0x01, 0x10, 0x09, 0xac, 0x05,
+0xe3, 0x83, 0x98, 0x0d, 0x6e, 0xb2, 0xf8, 0x21,
+0x38, 0xed, 0x23, 0x8a, 0xf4, 0x78, 0x87, 0x1f,
+0x5e, 0x05, 0xfa, 0x73, 0x18, 0xcc, 0x56, 0xe4,
+0x9d, 0x2e, 0x3f, 0xf4, 0x00, 0xf4, 0x4d, 0xc8,
+0x26, 0x69, 0xb9, 0x20, 0x7f, 0x53, 0x69, 0x40,
+0x3e, 0xca, 0xaa, 0xbb, 0x84, 0x04, 0xec, 0x8c,
+0xc3, 0x89, 0x6d, 0xed, 0xc2, 0xdc, 0x81, 0xaf,
+0x69, 0x35, 0xc7, 0x64, 0xbc, 0x31, 0xbe, 0x76,
+0x53, 0xcd, 0x84, 0x0d, 0xb4, 0x1a, 0xd3, 0x7f,
+0x7f, 0x55, 0x29, 0x43, 0xfc, 0x70, 0x10, 0xb1,
+0x2e, 0xef, 0xfe, 0x0a, 0x06, 0x7d, 0xe4, 0x2f,
+0x92, 0x4f, 0x15, 0xa2, 0x85, 0x88, 0x1f, 0x1a,
+0x00, 0x3d, 0x56, 0x82, 0x02, 0x11, 0x1b, 0x1c,
+0x96, 0x9b, 0xd1, 0x95, 0x4c, 0xaf, 0xba, 0x0f,
+0x33, 0x46, 0x98, 0x31, 0x7c, 0xef, 0x68, 0x5f,
+0x91, 0xd7, 0x0d, 0xce, 0x7e, 0x6c, 0xf5, 0x11,
+0x75, 0xc9, 0xc0, 0xb7, 0x72, 0xb5, 0x23, 0xab,
+0x1e, 0xab, 0xb9, 0x46, 0xee, 0x32, 0x6f, 0xb1,
+0xc1, 0x3a, 0xfb, 0x0a, 0x35, 0x7b, 0xb3, 0x0a,
+0xd4, 0x81, 0xfa, 0x89, 0xd8, 0xc3, 0x60, 0x12,
+0x4a, 0xa0, 0x1e, 0x71, 0x1f, 0xfb, 0xb4, 0x31,
+0x63, 0x36, 0xa8, 0xc7, 0x40, 0x27, 0xff, 0x01,
+0xbd, 0xaa, 0xaa, 0x2a, 0x7a, 0x97, 0xed, 0x06,
+0xf8, 0x29, 0xc2, 0x6f, 0xa2, 0x82, 0x0a, 0x56,
+0xa1, 0x7f, 0xc8, 0x59, 0x61, 0xb6, 0x6a, 0xbd,
+0x34, 0xeb, 0x82, 0xe7, 0xbe, 0x46, 0xf7, 0xb7,
+0x5f, 0x57, 0x35, 0xd9, 0xff, 0xa6, 0x2a, 0xfb,
+0x5f, 0x39, 0xe9, 0xf1, 0xb2, 0x61, 0x2b, 0x49,
+0xac, 0xe8, 0x53, 0x48, 0xe3, 0x23, 0xfd, 0x69,
+0x08, 0xc3, 0x16, 0x31, 0x71, 0xbe, 0xaa, 0x81,
+0xde, 0x78, 0x55, 0xd0, 0x45, 0x03, 0x0c, 0x83,
+0xff, 0x6d, 0xdf, 0x7c, 0x5e, 0xa4, 0xb8, 0x82,
+0x38, 0x5e, 0x6f, 0xe6, 0xed, 0xa4, 0xc5, 0xd9,
+0xa5, 0x7b, 0x33, 0x0b, 0xad, 0x2c, 0x32, 0xa3,
+0xab, 0x1e, 0xbc, 0xf4, 0x2c, 0x0a, 0x8a, 0x07,
+0x9f, 0xbb, 0x33, 0xeb, 0xac, 0xb0, 0xda, 0x44,
+0x54, 0x08, 0x39, 0xb4, 0xc1, 0x8b, 0xb7, 0xec,
+0xcd, 0x4b, 0xe2, 0x9b, 0xcd, 0x45, 0xc4, 0xc3,
+0xa2, 0x22, 0x0a, 0x82, 0x7b, 0xd0, 0xdc, 0x84,
+0xfc, 0x09, 0x33, 0x0b, 0x19, 0x48, 0x4e, 0x42,
+0x62, 0x6e, 0x21, 0x1b, 0xc8, 0xc5, 0xbb, 0x10,
+0x72, 0x90, 0xb5, 0xea, 0xbd, 0xfe, 0xf1, 0x7a,
+0xc7, 0x08, 0x7a, 0x88, 0x20, 0xf5, 0xbd, 0xec,
+0x97, 0xda, 0x37, 0x4d, 0x75, 0xbf, 0x9a, 0xea,
+0x4f, 0xf5, 0xcc, 0x1c, 0xa2, 0x9e, 0x65, 0xcd,
+0x2e, 0x32, 0x61, 0x66, 0x4c, 0x64, 0x2d, 0x4f,
+0x5f, 0x75, 0x17, 0x2c, 0x1f, 0xf6, 0x88, 0x0f,
+0x0d, 0x28, 0xfa, 0x9b, 0x68, 0x6e, 0x67, 0xc6,
+0xf2, 0x61, 0x7e, 0xbf, 0xa0, 0x33, 0x1f, 0xe7,
+0xc3, 0xf9, 0xd4, 0xa8, 0x3c, 0xa2, 0xf2, 0xf5,
+0x15, 0xb0, 0xd8, 0x89, 0xd8, 0x96, 0x9b, 0xf9,
+0x41, 0x39, 0x32, 0x28, 0xe5, 0x63, 0xf8, 0xad,
+0x0e, 0x6b, 0xd6, 0x78, 0x01, 0x9a, 0xe1, 0x57,
+0xa9, 0xb1, 0x11, 0x5d, 0xe4, 0x23, 0xc6, 0xf9,
+0x70, 0xdc, 0x14, 0xf5, 0x10, 0x8b, 0xb7, 0x1e,
+0x1f, 0x4f, 0xb3, 0x74, 0x7c, 0x27, 0x1f, 0x85,
+0x1b, 0xd9, 0x80, 0x2e, 0xa2, 0x7f, 0x6a, 0x02,
+0x34, 0xb8, 0x5f, 0x64, 0xe6, 0xd2, 0xc8, 0x42,
+0x9e, 0x4f, 0x4f, 0x11, 0x0d, 0xce, 0x26, 0x9f,
+0x85, 0xa2, 0x06, 0xab, 0x86, 0x0f, 0x05, 0x45,
+0xca, 0xa6, 0x28, 0x9f, 0x1e, 0x7d, 0xa5, 0x44,
+0x67, 0xf3, 0x86, 0xc6, 0x7a, 0x41, 0x3e, 0x14,
+0xf4, 0x95, 0x3b, 0x6b, 0xb4, 0x31, 0xe0, 0xe4,
+0x73, 0x09, 0x69, 0x50, 0x27, 0xad, 0x18, 0x2e,
+0x21, 0x28, 0xbe, 0x30, 0x58, 0x98, 0xf3, 0x61,
+0x66, 0x54, 0x71, 0x7f, 0x17, 0x4b, 0x72, 0xb5,
+0x3f, 0x9b, 0x9c, 0x09, 0x83, 0xd1, 0x7f, 0x1b,
+0xe7, 0xfa, 0x23, 0x76, 0xae, 0xea, 0x47, 0xc9,
+0x61, 0x4b, 0x83, 0x64, 0x76, 0x8d, 0xf0, 0x44,
+0x66, 0x8d, 0xa9, 0xa4, 0x91, 0x62, 0x7d, 0x8c,
+0x7c, 0xd8, 0x36, 0x58, 0x28, 0x46, 0xa9, 0x99,
+0x19, 0x89, 0xd5, 0xfe, 0x6d, 0x34, 0x17, 0x33,
+0x62, 0x9c, 0xd9, 0x74, 0xea, 0x67, 0x1a, 0xc7,
+0x4c, 0xe4, 0x43, 0x25, 0xd7, 0x45, 0xa2, 0x97,
+0xed, 0x58, 0x3a, 0x87, 0xdb, 0x34, 0xdd, 0xc3,
+0x08, 0xf5, 0x1f, 0xdf, 0xed, 0x3f, 0x0a, 0xcb,
+0xf5, 0x8a, 0x0e, 0x93, 0xda, 0x03, 0xf8, 0x01,
+0xcd, 0xde, 0xa4, 0x16, 0x0a, 0xe4, 0x43, 0xed,
+0x65, 0x26, 0x24, 0x53, 0xac, 0x87, 0x6e, 0x22,
+0xaf, 0xb7, 0xa6, 0xbc, 0xc5, 0x35, 0xd8, 0x90,
+0xc7, 0xc5, 0x3e, 0x1c, 0xd5, 0x82, 0x2d, 0x79,
+0x1d, 0xcd, 0x19, 0xc7, 0x38, 0xf5, 0x2c, 0xbe,
+0x40, 0x1a, 0xf4, 0xa2, 0x0a, 0xce, 0x0b, 0x58,
+0x2d, 0x7b, 0xb0, 0x5a, 0xb0, 0xed, 0x5c, 0x25,
+0x2c, 0xec, 0x89, 0x3b, 0x19, 0x28, 0x3a, 0xf9,
+0x60, 0xfd, 0x34, 0x4d, 0x91, 0xc0, 0x2d, 0xa2,
+0xc1, 0x8d, 0xa5, 0x12, 0x1f, 0xa6, 0xc6, 0xad,
+0x9f, 0x05, 0xa9, 0x86, 0x8d, 0x66, 0xd7, 0xf3,
+0x2b, 0x32, 0xee, 0xfb, 0x68, 0x82, 0x8a, 0x54,
+0xda, 0x6f, 0x76, 0x8c, 0xe9, 0x1b, 0x03, 0xce,
+0xf5, 0xc1, 0xf7, 0xcb, 0xa0, 0x11, 0x4d, 0x78,
+0xf0, 0x4b, 0x13, 0x06, 0x8d, 0x1f, 0x45, 0x5d,
+0x2c, 0x42, 0xac, 0x31, 0x82, 0xa6, 0x19, 0x0f,
+0x8c, 0x51, 0xce, 0xf5, 0xf1, 0xa8, 0xff, 0x10,
+0x1f, 0x82, 0xc2, 0x69, 0x14, 0x70, 0x3e, 0xf5,
+0xe4, 0x82, 0xb0, 0xa0, 0xa8, 0xc6, 0xf8, 0x10,
+0xf3, 0xd9, 0x3f, 0x4d, 0x7c, 0x88, 0xcd, 0x60,
+0x3f, 0x32, 0xd9, 0x7c, 0x0b, 0xf9, 0x10, 0x52,
+0x3e, 0xcc, 0x41, 0xd1, 0xc9, 0x47, 0xec, 0xe8,
+0x3f, 0xa5, 0xb6, 0x93, 0x1b, 0xe7, 0xfa, 0xa8,
+0xca, 0x55, 0x78, 0x08, 0x35, 0xfa, 0xe2, 0x40,
+0x32, 0xf1, 0x30, 0x6b, 0x3b, 0x1e, 0x99, 0xf5,
+0xbc, 0x23, 0x39, 0xf9, 0x24, 0xb8, 0x4d, 0x53,
+0xb8, 0x4d, 0x9a, 0xf6, 0x0b, 0x37, 0x4e, 0xfb,
+0x5b, 0x70, 0x5c, 0xdc, 0xc2, 0x48, 0xbc, 0x95,
+0xfe, 0xcb, 0xe9, 0x3f, 0x31, 0x9e, 0xe0, 0x09,
+0x35, 0xf5, 0x4d, 0xf5, 0x91, 0x7e, 0xba, 0x11,
+0xa9, 0xba, 0x5f, 0x95, 0x30, 0x84, 0x48, 0x79,
+0x64, 0x7e, 0x82, 0x34, 0xe2, 0xd4, 0x33, 0xbe,
+0x53, 0x8f, 0xa9, 0xc9, 0xb8, 0x1a, 0xcb, 0xfb,
+0xd0, 0x3e, 0x3d, 0xa9, 0xaa, 0x0d, 0x5c, 0xd6,
+0x06, 0x2f, 0x46, 0xf3, 0x02, 0xda, 0xaa, 0x4e,
+0x66, 0xd3, 0xc9, 0x67, 0x51, 0x5e, 0x19, 0x86,
+0xd1, 0x52, 0x08, 0xdf, 0xcb, 0x64, 0x80, 0xa6,
+0x1e, 0xa0, 0x19, 0x1a, 0x73, 0x37, 0x33, 0x6e,
+0xff, 0x51, 0xc4, 0x87, 0x83, 0x0a, 0x3d, 0xa7,
+0xdc, 0xf9, 0xd4, 0xd0, 0x89, 0x14, 0xd7, 0xa7,
+0xd7, 0x49, 0xf6, 0x84, 0xb5, 0x25, 0xa1, 0x75,
+0xe7, 0x6b, 0x1f, 0x41, 0xb1, 0x15, 0xdc, 0xcc,
+0xb0, 0xf0, 0x81, 0x1c, 0xe3, 0x43, 0xec, 0x3f,
+0x9d, 0x8b, 0xc1, 0x8c, 0xec, 0x9e, 0xf6, 0xfd,
+0x4e, 0xec, 0x37, 0x64, 0x57, 0x04, 0xca, 0x1a,
+0x08, 0x3a, 0x32, 0x0e, 0x6c, 0xc4, 0xa9, 0x1f,
+0x2a, 0xc0, 0xfc, 0xb9, 0x83, 0xbf, 0x36, 0x81,
+0x25, 0x09, 0xb6, 0x36, 0x45, 0x6e, 0x8a, 0x7a,
+0x00, 0x69, 0xb1, 0x50, 0x95, 0xf9, 0xb0, 0x9f,
+0x19, 0x1b, 0x71, 0xeb, 0x67, 0xa5, 0x7a, 0x41,
+0xdd, 0x7b, 0xde, 0x3a, 0xaa, 0x57, 0x2a, 0x55,
+0xf5, 0xdb, 0xf3, 0x83, 0x47, 0x27, 0x57, 0xc4,
+0x05, 0x34, 0xc7, 0xd0, 0x54, 0x53, 0xe3, 0xe4,
+0x23, 0x90, 0x07, 0x90, 0x0f, 0xf1, 0xa6, 0xff,
+0xf3, 0x1c, 0xdd, 0xfd, 0x2f, 0x37, 0x0b, 0x0c,
+0x78, 0x2b, 0x0f, 0x1c, 0xc9, 0xf8, 0x70, 0xf7,
+0xd9, 0xb3, 0xc4, 0x87, 0xcf, 0xae, 0x1d, 0x31,
+0x7c, 0xf8, 0xc4, 0xf0, 0xe1, 0xef, 0x64, 0x96,
+0x9d, 0xe5, 0x70, 0x2a, 0xe3, 0xc3, 0x93, 0x37,
+0xce, 0x13, 0x1f, 0x6e, 0xbf, 0x3e, 0x65, 0xc0,
+0xec, 0x95, 0xe5, 0xc3, 0x5f, 0xb7, 0x5f, 0x6d,
+0x97, 0x78, 0xec, 0x7d, 0x65, 0xb0, 0xf0, 0xe5,
+0x3a, 0x1e, 0xf6, 0xdf, 0x14, 0x14, 0xe7, 0x1e,
+0x2f, 0x93, 0x31, 0x7c, 0x68, 0x22, 0xdf, 0xba,
+0xeb, 0x0d, 0x16, 0xfe, 0xf3, 0x37, 0xa5, 0x91,
+0x81, 0xe2, 0x0d, 0x63, 0x2c, 0x1f, 0x52, 0xa4,
+0xc4, 0xab, 0x27, 0x33, 0x3e, 0x3c, 0xb0, 0xef,
+0xdc, 0x9f, 0x77, 0xda, 0xb4, 0xfe, 0xbb, 0x73,
+0xa3, 0xcf, 0xe9, 0x85, 0x39, 0x6a, 0x7e, 0x78,
+0xf6, 0x11, 0x8e, 0x58, 0xf8, 0xb6, 0xc6, 0xbf,
+0x8b, 0xf5, 0x0f, 0x3f, 0x0a, 0x8b, 0xc5, 0x62,
+0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0xfa, 0xd4,
+0x65, 0x66, 0x07, 0xc9, 0xb3, 0x03, 0x8b, 0xc5,
+0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x7a,
+0xb7, 0xcc, 0xec, 0x50, 0xe3, 0xd9, 0x81, 0xc5,
+0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62,
+0xbd, 0x5b, 0x66, 0x76, 0xf0, 0xcc, 0xec, 0xf0,
+0xb1, 0x53, 0x61, 0xb1, 0x58, 0x2c, 0x16, 0x8b,
+0xc5, 0x62, 0xb1, 0x58, 0xff, 0xa3, 0x22, 0xfa,
+0x7d, 0x1c, 0x3c, 0xfb, 0x23, 0x02, 0x4d, 0xbf,
+0x5a, 0xa9, 0x46, 0xa0, 0xde, 0xfb, 0xf3, 0x84,
+0xf4, 0xb5, 0x13, 0x11, 0x6c, 0x88, 0xe2, 0x98,
+0x7f, 0x7d, 0xb9, 0x73, 0xdd, 0x1b, 0x3b, 0x1c,
+0x29, 0xc2, 0xf0, 0x33, 0x01, 0x00,
diff --git a/qemu/roms/u-boot/board/esd/plu405/plu405.c b/qemu/roms/u-boot/board/esd/plu405/plu405.c
new file mode 100644
index 000000000..03bf9c8fe
--- /dev/null
+++ b/qemu/roms/u-boot/board/esd/plu405/plu405.c
@@ -0,0 +1,345 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <sja1000.h>
+
+#undef FPGA_DEBUG
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+	struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+
+	/* dominant */
+	out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+	out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+	out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+	      OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+	out_8(&ctrl->cr, 0x00);
+
+	/* delay */
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
+	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
+	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to
+	 * 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	unsigned char *dst;
+	unsigned char fctr;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+		   (uchar *)fpgadata, &len) != 0) {
+		printf("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low "
+			       "after asserting PROGRAM*)\n");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high "
+			       "after deasserting PROGRAM*)\n");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high "
+			       "after programming FPGA)\n");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+	udelay(10);
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+	udelay(1000);
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) &
+		 ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+
+	/*
+	 * Setup EEPROM write protection
+	 */
+	out_be32((void*)GPIO0_OR,
+		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+	out_be32((void*)GPIO0_TCR,
+		 in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	out_8((void *)DUART0_BA + 4, 0x08);
+	out_8((void *)DUART1_BA + 4, 0x08);
+
+	/*
+	 * Enable auto RS485 mode in 2nd external uart
+	 */
+	out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
+	fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
+	fctr |= 0x08;                       /* enable RS485 mode */
+	out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
+	out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
+
+	/*
+	 * Init magnetic couplers
+	 */
+	if (!getenv("noinitcoupler")) {
+		init_coupler(CAN0_BA);
+		init_coupler(CAN1_BA);
+	}
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char str[64];
+	int i = getenv_f("serial#", str, sizeof(str));
+
+	puts("Board: ");
+
+	if (i == -1)
+		puts("### No HW ID - assuming PLU405");
+	else
+		puts(str);
+
+	putc('\n');
+	return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
+void ide_set_reset(int on)
+{
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		out_be16((void *)FPGA_CTRL,
+			 in_be16((void *)FPGA_CTRL) &
+			 ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		out_be16((void *)FPGA_CTRL,
+			 in_be16((void *)FPGA_CTRL) |
+			 CONFIG_SYS_FPGA_CTRL_CF_RESET);
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *	       <state> -1: deliver current state
+ *			0: disable write
+ *			1: enable write
+ *  Returns:	       -1: wrong device address
+ *			0: dis-/en- able done
+ *		      0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO0. */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) &
+				 ~CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO0. */
+			out_be32((void*)GPIO0_OR,
+				 in_be32((void*)GPIO0_OR) |
+				 CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = ((in_be32((void*)GPIO0_OR) &
+				       CONFIG_SYS_EEPROM_WP) == 0);
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts("Query of write access state failed.\n");
+		} else {
+			printf("Write access for device 0x%0x is %sabled.\n",
+			       CONFIG_SYS_I2C_EEPROM_ADDR,
+			       state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if (argv[1][0] == '0') {
+			/* Disable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+						    0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+						    1);
+		}
+		if (state < 0)
+			puts("Setup of write access state failed.\n");
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	"Enable / disable / query EEPROM write access",
+	""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */