Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

5 files changed, 838 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/ep8260/Makefile b/qemu/roms/u-boot/board/ep8260/Makefile
new file mode 100644
index 000000000..dd08b74bf
--- /dev/null
+++ b/qemu/roms/u-boot/board/ep8260/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= ep8260.o flash.o mii_phy.o
diff --git a/qemu/roms/u-boot/board/ep8260/ep8260.c b/qemu/roms/u-boot/board/ep8260/ep8260.c
new file mode 100644
index 000000000..3697d24fd
--- /dev/null
+++ b/qemu/roms/u-boot/board/ep8260/ep8260.c
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "ep8260.h"
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA30 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA29 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA28 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA27 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA26 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA21 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA20 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA19 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA18 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA17 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA16 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA15 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA14 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB30 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB29 */ {   0,   1,   1,   1,   0,   0   }, /*  */
+	/* PB28 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB27 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB26 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB25 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB24 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB23 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB22 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB21 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB20 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB19 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB18 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /*  */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC19 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC18 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CLK15 */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CLK16 */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /*  */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /*  */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /*  */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Setup CS4 to enable the Board Control/Status registers.
+ * Otherwise the smcs won't work.
+*/
+int board_early_init_f (void)
+{
+	volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+	regs->bcsr1 = 0x62;	/* to enable terminal on SMC1 */
+	regs->bcsr2 = 0x30;	/* enable NVRAM and writing FLASH */
+	return 0;
+}
+
+void reset_phy (void)
+{
+	volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
+
+	regs->bcsr4 = 0xC0;
+}
+
+/*
+ * Check Board Identity:
+ * I don' know, how the next board revisions will be coded.
+ * Thats why its a static interpretation ...
+*/
+
+int checkboard (void)
+{
+	volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
+	uint major = 0, minor = 0;
+
+	switch (regs->bcsr0) {
+	case 0x02:
+		major = 1;
+		break;
+	case 0x03:
+		major = 1;
+		minor = 1;
+		break;
+	case 0x06:
+		major = 1;
+		minor = 3;
+		break;
+	default:
+		break;
+	}
+	printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
+		major, minor);
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+
+phys_size_t initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0;
+	volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE) + 0x110;
+
+/*
+	ulong psdmr = CONFIG_SYS_PSDMR;
+#ifdef CONFIG_SYS_LSDRAM
+	ulong lsdmr = CONFIG_SYS_LSDMR;
+#endif
+*/
+	long size = CONFIG_SYS_SDRAM0_SIZE;
+	int i;
+
+
+/*
+* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+*
+* "At system reset, initialization software must set up the
+*  programmable parameters in the memory controller banks registers
+*  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+*  system software should execute the following initialization sequence
+*  for each SDRAM device.
+*
+*  1. Issue a PRECHARGE-ALL-BANKS command
+*  2. Issue eight CBR REFRESH commands
+*  3. Issue a MODE-SET command to initialize the mode register
+*
+*  The initial commands are executed by setting P/LSDMR[OP] and
+*  accessing the SDRAM with a single-byte transaction."
+*
+* The appropriate BRx/ORx registers have already been set when we
+* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
+*/
+
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+#ifndef CONFIG_SYS_RAMBOOT
+#ifdef CONFIG_SYS_LSDRAM
+	size += CONFIG_SYS_SDRAM1_SIZE;
+	ramaddr = (uchar *) (CONFIG_SYS_SDRAM1_BASE) + 0x8c;
+	memctl->memc_lsrt = CONFIG_SYS_LSRT;
+
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+#endif /* CONFIG_SYS_LSDRAM */
+#endif /* CONFIG_SYS_RAMBOOT */
+	return (size * 1024 * 1024);
+}
diff --git a/qemu/roms/u-boot/board/ep8260/ep8260.h b/qemu/roms/u-boot/board/ep8260/ep8260.h
new file mode 100644
index 000000000..3032b1424
--- /dev/null
+++ b/qemu/roms/u-boot/board/ep8260/ep8260.h
@@ -0,0 +1,24 @@
+#ifndef __EP8260_H__
+#define __EP8260_H__
+
+typedef struct tt_ep_regs {
+	volatile unsigned char bcsr0;
+	volatile unsigned char bcsr1;
+	volatile unsigned char bcsr2;
+	volatile unsigned char bcsr3;
+	volatile unsigned char bcsr4;
+	volatile unsigned char bcsr5;
+	volatile unsigned char bcsr6;
+	volatile unsigned char bcsr7;
+	volatile unsigned char bcsr8;
+	volatile unsigned char bcsr9;
+	volatile unsigned char bcsr10;
+	volatile unsigned char bcsr11;
+	volatile unsigned char bcsr12;
+	volatile unsigned char bcsr13;
+	volatile unsigned char bcsr14;
+	volatile unsigned char bcsr15;
+} t_ep_regs;
+typedef t_ep_regs *tp_ep_regs;
+
+#endif
diff --git a/qemu/roms/u-boot/board/ep8260/flash.c b/qemu/roms/u-boot/board/ep8260/flash.c
new file mode 100644
index 000000000..44f63ee38
--- /dev/null
+++ b/qemu/roms/u-boot/board/ep8260/flash.c
@@ -0,0 +1,395 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * Flash Routines for AMD device AM29DL323DB on the EP8260 board.
+ *
+ * This file is based on board/tqm8260/flash.c.
+ *--------------------------------------------------------------------
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define V_ULONG(a)	(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)	(*(volatile unsigned char *)( a ))
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset(void)
+{
+	if( flash_info[0].flash_id != FLASH_UNKNOWN ) {
+		V_ULONG( flash_info[0].start[0] ) = 0x00F000F0;
+		V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size( ulong baseaddr, flash_info_t *info )
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	/* Write auto select command sequence and test FLASH answer */
+	V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055;
+	V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090;
+	V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055;
+	V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090;
+
+	flashtest_h = V_ULONG(baseaddr);		/* manufacturer ID	   */
+	flashtest_l = V_ULONG(baseaddr + 4);
+
+	if ((int)flashtest_h == AMD_MANUFACT) {
+		info->flash_id = FLASH_MAN_AMD;
+	} else {
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash	   */
+	}
+
+	flashtest_h = V_ULONG(baseaddr + 8);	        /* device ID		   */
+	flashtest_l = V_ULONG(baseaddr + 12);
+	if (flashtest_h != flashtest_l) {
+		info->flash_id = FLASH_UNKNOWN;
+		return(0);
+	}
+
+	switch((int)flashtest_h) {
+	case AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x01000000;	 /* 4 * 4 MB = 16 MB	*/
+		break;
+	case AMD_ID_LV640U:	/* AMDLV640 and AMDLV641 have same ID */
+		info->flash_id += FLASH_AMLV640U;
+		info->sector_count = 128;
+		info->size = 0x02000000;	/* 4 * 8 MB = 32 MB	*/
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return(0);				/* no or unknown flash	   */
+	}
+
+	if(flashtest_h == AMD_ID_LV640U) {
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+	} else {
+		/* set up sector start adress table (bottom sector type) */
+		for (i = 0; i < 8; i++) {
+			info->start[i] = baseaddr + (i * 0x00008000);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
+		}
+	}
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) ||
+		    (V_ULONG( info->start[i] + 20 ) & 0x00010001)) {
+			info->protect[i] = 1;		/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+
+	flash_reset();
+	return(info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0>>20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef  CONFIG_ENV_SIZE
+#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+# endif
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_ENV_ADDR,
+		      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+		      &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case FLASH_MAN_AMD:	    printf ("AMD ");		    break;
+	default:		    printf ("Unknown Vendor ");	    break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDL323B:	printf ("29DL323B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMLV640U:	printf ("29LV640U (64 M, uniform sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+			);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080;
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+	udelay (1000);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			V_ULONG( info->start[sect] ) = 0x00300030;
+			V_ULONG( info->start[sect] + 4 ) = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 ||
+	       (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080)
+	{
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+ DONE:
+	/* reset to read mode */
+	flash_reset ();
+
+	printf (" done\n");
+	return 0;
+}
+
+static int write_dword (flash_info_t *, ulong, unsigned char *);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong dp;
+	static unsigned char bb[8];
+	int i, l, rc, cc = cnt;
+
+	dp = (addr & ~7);	/* get lower dword aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - dp) != 0) {
+		for (i = 0; i < 8; i++)
+			bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++;
+		if ((rc = write_dword(info, dp, bb)) != 0)
+		{
+			return (rc);
+		}
+		dp += 8;
+		cc -= 8 - l;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cc >= 8) {
+		if ((rc = write_dword(info, dp, src)) != 0) {
+			return (rc);
+		}
+		dp  += 8;
+		src += 8;
+		cc -= 8;
+	}
+
+	if (cc <= 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	for (i = 0; i < 8; i++) {
+		bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i);
+	}
+	return (write_dword(info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata)
+{
+	ulong start;
+	ulong cl = 0, ch =0;
+	int flag, i;
+
+	for (ch=0, i=0; i < 4; i++)
+		ch = (ch << 8) + *pdata++;	/* high word	*/
+	for (cl=0, i=0; i < 4; i++)
+		cl = (cl << 8) + *pdata++;	/* low word	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & ch)	!= ch
+	    ||(*((vu_long *)(dest + 4)) & cl)	!= cl)
+	{
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0;
+	V_ULONG( dest ) = ch;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0;
+	V_ULONG( dest + 4 ) = cl;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) ||
+	       ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/qemu/roms/u-boot/board/ep8260/mii_phy.c b/qemu/roms/u-boot/board/ep8260/mii_phy.c
new file mode 100644
index 000000000..c7aa2755f
--- /dev/null
+++ b/qemu/roms/u-boot/board/ep8260/mii_phy.c
@@ -0,0 +1,107 @@
+#include <common.h>
+#include <mii_phy.h>
+#include "ep8260.h"
+
+#define MII_MDIO	0x01
+#define MII_MDCK	0x02
+#define MII_MDIR	0x04
+
+void
+mii_discover_phy(void)
+{
+    int known;
+    unsigned short phy_reg;
+    unsigned long phy_id;
+
+    known = 0;
+    printf("Discovering phy @ 0: ");
+    phy_id = mii_phy_read(2) << 16;
+    phy_id |= mii_phy_read(3);
+    if ((phy_id & 0xFFFFFC00) == 0x00137800) {
+	printf("Level One ");
+	if ((phy_id & 0x000003F0) == 0xE0) {
+	    printf("LXT971A Revision %d\n", (int)(phy_id & 0xF));
+	    known = 1;
+	}
+	else printf("unknown type\n");
+    }
+    else printf("unknown OUI = 0x%08lX\n", phy_id);
+
+    phy_reg = mii_phy_read(1);
+    if (!(phy_reg & 0x0004)) printf("Link is down\n");
+    if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n");
+    if (phy_reg & 0x0002) printf("Jabber condition detected\n");
+    if (phy_reg & 0x0010) printf("Remote fault condition detected \n");
+
+    if (known) {
+	phy_reg = mii_phy_read(17);
+	if (phy_reg & 0x0400)
+	    printf("Phy operating at %d MBit/s in %s-duplex mode\n",
+		phy_reg & 0x4000 ? 100 : 10,
+		phy_reg & 0x0200 ? "full" : "half");
+	else
+	    printf("bad link!!\n");
+/*
+left  off: no link, green 100MBit, yellow 10MBit
+right off: no activity, green full-duplex, yellow half-duplex
+*/
+	mii_phy_write(20, 0x0452);
+    }
+}
+
+unsigned short
+mii_phy_read(unsigned short reg)
+{
+    int i;
+    unsigned short tmp, val = 0, adr = 0;
+    t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE;
+
+    tmp = 0x6002 | (adr << 7) | (reg << 2);
+    regs->bcsr4 = 0xC3;
+    for (i = 0; i < 64; i++) {
+	regs->bcsr4 ^= MII_MDCK;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	tmp <<= 1;
+    }
+    regs->bcsr4 |= MII_MDIR;
+    for (i = 0; i < 16; i++) {
+	val <<= 1;
+	regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK);
+	if (regs->bcsr4 & MII_MDIO) val |= 1;
+	regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK);
+    }
+    return val;
+}
+
+void
+mii_phy_write(unsigned short reg, unsigned short val)
+{
+    int i;
+    unsigned short tmp, adr = 0;
+    t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE;
+
+    tmp = 0x5002 | (adr << 7) | (reg << 2);
+    regs->bcsr4 = 0xC3;
+    for (i = 0; i < 64; i++) {
+	regs->bcsr4 ^= MII_MDCK;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	tmp <<= 1;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (val & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	val <<= 1;
+    }
+}