diff options
| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/board/cogent/serial.h | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/board/cogent/serial.h')
| -rw-r--r-- | qemu/roms/u-boot/board/cogent/serial.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/cogent/serial.h b/qemu/roms/u-boot/board/cogent/serial.h new file mode 100644 index 000000000..89962d887 --- /dev/null +++ b/qemu/roms/u-boot/board/cogent/serial.h @@ -0,0 +1,15 @@ +/* Line Status Register bits */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +#define CLKRATE 3686400 /* cogent motherboard serial clk = 3.6864MHz */ +#define DEFDIV 1 /* default to 230400 bps */ + +#define br_to_div(br) (CLKRATE / (16 * (br))) +#define div_to_br(div) (CLKRATE / (16 * (div))) |