Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

5 files changed, 742 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/board/astro/mcf5373l/Makefile b/qemu/roms/u-boot/board/astro/mcf5373l/Makefile
new file mode 100644
index 000000000..005d03697
--- /dev/null
+++ b/qemu/roms/u-boot/board/astro/mcf5373l/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= mcf5373l.o fpga.o
diff --git a/qemu/roms/u-boot/board/astro/mcf5373l/astro.h b/qemu/roms/u-boot/board/astro/mcf5373l/astro.h
new file mode 100644
index 000000000..b55a6f785
--- /dev/null
+++ b/qemu/roms/u-boot/board/astro/mcf5373l/astro.h
@@ -0,0 +1,44 @@
+#ifndef __ASTRO_H__
+#define __ASTRO_H__
+
+/* in mcf5373l.c */
+int rs_serial_init(int port, int baud);
+void astro_put_char(char ch);
+int astro_is_char(void);
+int astro_get_char(void);
+
+/* in fpga.c */
+int astro5373l_altera_load(void);
+int astro5373l_xilinx_load(void);
+
+/* data structures used for communication (update.c) */
+typedef struct card_id {
+	char card_type;
+	char hardware_version;
+	char software_version;
+	char software_subversion;	/* " ","a".."z" */
+	char fpga_version_altera;
+	char fpga_version_xilinx;
+} card_id_t;
+
+typedef struct {
+	unsigned char mode;
+	unsigned char deviation;
+	unsigned short freq;
+} __attribute__ ((packed)) output_params_t;
+
+typedef struct {
+	unsigned short satfreq;
+	unsigned char satdatallg;
+	unsigned short symbolrate;
+	unsigned char viterbirate;
+	unsigned char symbolrate_l;
+	output_params_t output_params;
+	unsigned char reserve;
+	unsigned char card_error;
+	unsigned short dummy_ts_id;
+	unsigned char dummy_pat_ver;
+	unsigned char dummy_sdt_ver;
+} __attribute__ ((packed)) parameters_t;
+
+#endif /* __ASTRO_H__ */
diff --git a/qemu/roms/u-boot/board/astro/mcf5373l/fpga.c b/qemu/roms/u-boot/board/astro/mcf5373l/fpga.c
new file mode 100644
index 000000000..1d044d96a
--- /dev/null
+++ b/qemu/roms/u-boot/board/astro/mcf5373l/fpga.c
@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
+ * w.wegner@astro-kom.de
+ *
+ * based on the files by
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ * and
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
+
+#include <common.h>
+#include <watchdog.h>
+#include <altera.h>
+#include <ACEX1K.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int altera_pre_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char tmp_char;
+	unsigned short tmp_short;
+
+	/* first, set the required pins to GPIO function */
+	/* PAR_T0IN -> GPIO */
+	tmp_char = readb(&gpiop->par_timer);
+	tmp_char &= 0xfc;
+	writeb(tmp_char, &gpiop->par_timer);
+	/* all QSPI pins -> GPIO */
+	writew(0x0000, &gpiop->par_qspi);
+	/* U0RTS, U0CTS -> GPIO */
+	tmp_short = __raw_readw(&gpiop->par_uart);
+	tmp_short &= 0xfff3;
+	__raw_writew(tmp_short, &gpiop->par_uart);
+	/* all PWM pins -> GPIO */
+	writeb(0x00, &gpiop->par_pwm);
+	/* next, set data direction registers */
+	writeb(0x01, &gpiop->pddr_timer);
+	writeb(0x25, &gpiop->pddr_qspi);
+	writeb(0x0c, &gpiop->pddr_uart);
+	writeb(0x04, &gpiop->pddr_pwm);
+
+	/* ensure other SPI peripherals are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x38, &gpiop->ppd_qspi);
+
+	/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
+	writeb(0xFB, &gpiop->pclrr_uart);
+	/* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
+	writeb(0xFE, &gpiop->pclrr_timer);
+	writeb(0xDF, &gpiop->pclrr_qspi);
+	return FPGA_SUCCESS;
+}
+
+/* Set the state of CONFIG Pin */
+int altera_config_fn(int assert_config, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_config)
+		writeb(0x04, &gpiop->ppd_uart);
+	else
+		writeb(0xFB, &gpiop->pclrr_uart);
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of STATUS Pin */
+int altera_status_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (readb(&gpiop->ppd_pwm) & 0x08)
+		return FPGA_FAIL;
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of CONF_DONE Pin */
+int altera_done_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (readb(&gpiop->ppd_pwm) & 0x20)
+		return FPGA_FAIL;
+	return FPGA_SUCCESS;
+}
+
+/*
+ * writes the complete buffer to the FPGA
+ * writing the complete buffer in one function is much faster,
+ * then calling it for every bit
+ */
+int altera_write_fn(void *buf, size_t len, int flush, int cookie)
+{
+	size_t bytecount = 0;
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char *data = (unsigned char *)buf;
+	unsigned char val = 0;
+	int i;
+	int len_40 = len / 40;
+
+	while (bytecount < len) {
+		val = data[bytecount++];
+		i = 8;
+		do {
+			writeb(0xFB, &gpiop->pclrr_qspi);
+			if (val & 0x01)
+				writeb(0x01, &gpiop->ppd_qspi);
+			else
+				writeb(0xFE, &gpiop->pclrr_qspi);
+			writeb(0x04, &gpiop->ppd_qspi);
+			val >>= 1;
+			i--;
+		} while (i > 0);
+
+		if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+			WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+			putc('.');	/* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+			if (ctrlc())
+				return FPGA_FAIL;
+#endif
+		}
+	}
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming is aborted */
+int altera_abort_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	writeb(0x20, &gpiop->ppd_qspi);
+	writeb(0x08, &gpiop->ppd_uart);
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming was succesful */
+int altera_post_fn(int cookie)
+{
+	return altera_abort_fn(cookie);
+}
+
+/*
+ * Note that these are pointers to code that is in Flash. They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	altera_pre_fn,
+	altera_config_fn,
+	altera_status_fn,
+	altera_done_fn,
+	altera_write_fn,
+	altera_abort_fn,
+	altera_post_fn
+};
+
+Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
+	{Altera_CYC2,
+	 passive_serial,
+	 85903,
+	 (void *)&altera_fns,
+	 NULL,
+	 0}
+};
+
+/* Initialize the fpga.  Return 1 on success, 0 on failure. */
+int astro5373l_altera_load(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		/*
+		 * I did not yet manage to get relocation work properly,
+		 * so set stuff here instead of static initialisation:
+		 */
+		altera_fns.pre = altera_pre_fn;
+		altera_fns.config = altera_config_fn;
+		altera_fns.status = altera_status_fn;
+		altera_fns.done = altera_done_fn;
+		altera_fns.write = altera_write_fn;
+		altera_fns.abort = altera_abort_fn;
+		altera_fns.post = altera_post_fn;
+		altera_fpga[i].iface_fns = (void *)&altera_fns;
+		fpga_add(fpga_altera, &altera_fpga[i]);
+	}
+	return 1;
+}
+
+/* Set the FPGA's PROG_B line to the specified level */
+int xilinx_pgm_config_fn(int assert, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert)
+		writeb(0xFB, &gpiop->pclrr_uart);
+	else
+		writeb(0x04, &gpiop->ppd_uart);
+	return assert;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int xilinx_init_config_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
+}
+
+/* Test the state of the active-high FPGA DONE pin */
+int xilinx_done_config_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
+}
+
+/* Abort an FPGA operation */
+int xilinx_abort_config_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	/* ensure all SPI peripherals and FPGAs are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x01, &gpiop->ppd_timer);
+	writeb(0x38, &gpiop->ppd_qspi);
+	return FPGA_FAIL;
+}
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int xilinx_pre_config_fn(int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char tmp_char;
+	unsigned short tmp_short;
+
+	/* first, set the required pins to GPIO function */
+	/* PAR_T0IN -> GPIO */
+	tmp_char = readb(&gpiop->par_timer);
+	tmp_char &= 0xfc;
+	writeb(tmp_char, &gpiop->par_timer);
+	/* all QSPI pins -> GPIO */
+	writew(0x0000, &gpiop->par_qspi);
+	/* U0RTS, U0CTS -> GPIO */
+	tmp_short = __raw_readw(&gpiop->par_uart);
+	tmp_short &= 0xfff3;
+	__raw_writew(tmp_short, &gpiop->par_uart);
+	/* all PWM pins -> GPIO */
+	writeb(0x00, &gpiop->par_pwm);
+	/* next, set data direction registers */
+	writeb(0x01, &gpiop->pddr_timer);
+	writeb(0x25, &gpiop->pddr_qspi);
+	writeb(0x0c, &gpiop->pddr_uart);
+	writeb(0x04, &gpiop->pddr_pwm);
+
+	/* ensure other SPI peripherals are deselected */
+	writeb(0x08, &gpiop->ppd_uart);
+	writeb(0x38, &gpiop->ppd_qspi);
+	writeb(0x01, &gpiop->ppd_timer);
+
+	/* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
+	writeb(0xFB, &gpiop->pclrr_uart);
+	/* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
+	writeb(0xF7, &gpiop->pclrr_uart);
+	writeb(0xDF, &gpiop->pclrr_qspi);
+	return 0;
+}
+
+/*
+ * FPGA post configuration function. Should perform a test if FPGA is running.
+ */
+int xilinx_post_config_fn(int cookie)
+{
+	int rc = 0;
+
+	/*
+	 * no test yet
+	 */
+	return rc;
+}
+
+int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_clk)
+		writeb(0x04, &gpiop->ppd_qspi);
+	else
+		writeb(0xFB, &gpiop->pclrr_qspi);
+	return assert_clk;
+}
+
+int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
+{
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+	if (assert_write)
+		writeb(0x01, &gpiop->ppd_qspi);
+	else
+		writeb(0xFE, &gpiop->pclrr_qspi);
+	return assert_write;
+}
+
+int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
+{
+	size_t bytecount = 0;
+	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+	unsigned char *data = (unsigned char *)buf;
+	unsigned char val = 0;
+	int i;
+	int len_40 = len / 40;
+
+	for (bytecount = 0; bytecount < len; bytecount++) {
+		val = *(data++);
+		for (i = 8; i > 0; i--) {
+			writeb(0xFB, &gpiop->pclrr_qspi);
+			if (val & 0x80)
+				writeb(0x01, &gpiop->ppd_qspi);
+			else
+				writeb(0xFE, &gpiop->pclrr_qspi);
+			writeb(0x04, &gpiop->ppd_qspi);
+			val <<= 1;
+		}
+		if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+			WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+			putc('.');	/* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+			if (ctrlc())
+				return FPGA_FAIL;
+#endif
+		}
+	}
+	return FPGA_SUCCESS;
+}
+
+/*
+ * Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+xilinx_spartan3_slave_serial_fns xilinx_fns = {
+	xilinx_pre_config_fn,
+	xilinx_pgm_config_fn,
+	xilinx_clk_config_fn,
+	xilinx_init_config_fn,
+	xilinx_done_config_fn,
+	xilinx_wr_config_fn,
+	0,
+	xilinx_fastwr_config_fn
+};
+
+xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+	{xilinx_spartan3,
+	 slave_serial,
+	 XILINX_XC3S4000_SIZE,
+	 (void *)&xilinx_fns,
+	 0,
+	 &spartan3_op}
+};
+
+/* Initialize the fpga.  Return 1 on success, 0 on failure. */
+int astro5373l_xilinx_load(void)
+{
+	int i;
+
+	fpga_init();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		/*
+		 * I did not yet manage to get relocation work properly,
+		 * so set stuff here instead of static initialisation:
+		 */
+		xilinx_fns.pre = xilinx_pre_config_fn;
+		xilinx_fns.pgm = xilinx_pgm_config_fn;
+		xilinx_fns.clk = xilinx_clk_config_fn;
+		xilinx_fns.init = xilinx_init_config_fn;
+		xilinx_fns.done = xilinx_done_config_fn;
+		xilinx_fns.wr = xilinx_wr_config_fn;
+		xilinx_fns.bwr = xilinx_fastwr_config_fn;
+		xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
+		fpga_add(fpga_xilinx, &xilinx_fpga[i]);
+	}
+	return 1;
+}
diff --git a/qemu/roms/u-boot/board/astro/mcf5373l/mcf5373l.c b/qemu/roms/u-boot/board/astro/mcf5373l/mcf5373l.c
new file mode 100644
index 000000000..daba32c9d
--- /dev/null
+++ b/qemu/roms/u-boot/board/astro/mcf5373l/mcf5373l.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/m5329.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+
+/* needed for astro bus: */
+#include <asm/uart.h>
+#include "astro.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+extern void uart_port_conf(void);
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("ASTRO MCF5373L (Urmel) Board\n");
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+	sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
+
+	/*
+	 * GPIO configuration for bus should be set correctly from reset,
+	 * so we do not care! First, set up address space: at this point,
+	 * we should be running from internal SRAM;
+	 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
+	 * and do not care where it is
+	 */
+	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
+			&sdp->cs0);
+	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
+			&sdp->cs1);
+	/*
+	 * I am not sure from the data sheet, but it seems burst length
+	 * has to be 8 for the 16 bit data bus we use;
+	 * so these values are for BL = 8
+	 */
+	__raw_writel(0x33211530, &sdp->cfg1);
+	__raw_writel(0x56570000, &sdp->cfg2);
+	/* send PrechargeALL, REF and IREF remain cleared! */
+	__raw_writel(0xE1462C02, &sdp->ctrl);
+	udelay(1);
+	/* refresh SDRAM twice */
+	__raw_writel(0xE1462C04, &sdp->ctrl);
+	udelay(1);
+	__raw_writel(0xE1462C04, &sdp->ctrl);
+	/* init MR  */
+	__raw_writel(0x008D0000, &sdp->mode);
+	/* initialize EMR */
+	__raw_writel(0x80010000, &sdp->mode);
+	/* wait until DLL is locked */
+	udelay(1);
+	/*
+	 * enable automatic refresh, lock mode register,
+	 * clear iref and ipall
+	 */
+	__raw_writel(0x71462C00, &sdp->ctrl);
+	/* Dummy write to start SDRAM */
+	writel(0, CONFIG_SYS_SDRAM_BASE);
+#endif
+
+	/*
+	 * for get_ram_size() to work, both CS areas have to be
+	 * configured, i.e. CS1 has to be explicitely disabled, else
+	 * probing for memory will cause the SDRAM bus to hang!
+	 * (Do not rely on the SDCS register(s) being set to 0x00000000
+	 * during reset as stated in the data sheet.)
+	 */
+	return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE,
+				0x80000000 - CONFIG_SYS_SDRAM_BASE);
+}
+
+#define UART_BASE MMAP_UART0
+int rs_serial_init(int port, int baud)
+{
+	uart_t *uart;
+	u32 counter;
+
+	switch (port) {
+	case 0:
+		uart = (uart_t *)(MMAP_UART0);
+		break;
+	case 1:
+		uart = (uart_t *)(MMAP_UART1);
+		break;
+	case 2:
+		uart = (uart_t *)(MMAP_UART2);
+		break;
+	default:
+		uart = (uart_t *)(MMAP_UART0);
+	}
+
+	uart_port_conf();
+
+	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
+	writeb(UART_UCR_RESET_RX, &uart->ucr);
+	writeb(UART_UCR_RESET_TX, &uart->ucr);
+	writeb(UART_UCR_RESET_ERROR, &uart->ucr);
+	writeb(UART_UCR_RESET_MR, &uart->ucr);
+	__asm__ ("nop");
+
+	writeb(0, &uart->uimr);
+
+	/* write to CSR: RX/TX baud rate from timers */
+	writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
+
+	writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
+	writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
+
+	/* Setting up BaudRate */
+	counter = (u32) (gd->bus_clk / (baud));
+	counter >>= 5;
+
+	/* write to CTUR: divide counter upper byte */
+	writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
+	/* write to CTLR: divide counter lower byte */
+	writeb((u8) (counter & 0x00ff), &uart->ubg2);
+
+	writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
+
+	return 0;
+}
+
+void astro_put_char(char ch)
+{
+	uart_t *uart;
+	unsigned long timer;
+
+	uart = (uart_t *)(MMAP_UART0);
+	/*
+	 * Wait for last character to go. Timeout of 6ms should
+	 * be enough for our lowest baud rate of 2400.
+	 */
+	timer = get_timer(0);
+	while (get_timer(timer) < 6) {
+		if (readb(&uart->usr) & UART_USR_TXRDY)
+			break;
+	}
+	writeb(ch, &uart->utb);
+
+	return;
+}
+
+int astro_is_char(void)
+{
+	uart_t *uart;
+
+	uart = (uart_t *)(MMAP_UART0);
+	return readb(&uart->usr) & UART_USR_RXRDY;
+}
+
+int astro_get_char(void)
+{
+	uart_t *uart;
+
+	uart = (uart_t *)(MMAP_UART0);
+	while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
+	return readb(&uart->urb);
+}
+
+int misc_init_r(void)
+{
+	int retval = 0;
+
+	puts("Configure Xilinx FPGA...");
+	retval = astro5373l_xilinx_load();
+	if (!retval) {
+		puts("failed!\n");
+		return retval;
+	}
+	puts("done\n");
+
+	puts("Configure Altera FPGA...");
+	retval = astro5373l_altera_load();
+	if (!retval) {
+		puts("failed!\n");
+		return retval;
+	}
+	puts("done\n");
+
+	return retval;
+}
diff --git a/qemu/roms/u-boot/board/astro/mcf5373l/u-boot.lds b/qemu/roms/u-boot/board/astro/mcf5373l/u-boot.lds
new file mode 100644
index 000000000..8ef0620ee
--- /dev/null
+++ b/qemu/roms/u-boot/board/astro/mcf5373l/u-boot.lds
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    arch/m68k/cpu/mcf532x/start.o		(.text*)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text*)
+
+    *(.text*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    KEEP(*(.got))
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss*)
+   *(.bss*)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}