Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

4 files changed, 0 insertions, 171 deletions

diff --git a/qemu/roms/u-boot/board/amcc/bluestone/Makefile b/qemu/roms/u-boot/board/amcc/bluestone/Makefile
deleted file mode 100644
index 07320ce42..000000000
--- a/qemu/roms/u-boot/board/amcc/bluestone/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (c) 2010, Applied Micro Circuits Corporation
-# Author: Tirumala R Marri <tmarri@apm.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bluestone.o
-extra-y	+= init.o
diff --git a/qemu/roms/u-boot/board/amcc/bluestone/bluestone.c b/qemu/roms/u-boot/board/amcc/bluestone/bluestone.c
deleted file mode 100644
index 6520f75c6..000000000
--- a/qemu/roms/u-boot/board/amcc/bluestone/bluestone.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Bluestone board support
- *
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/apm821xx.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx-gpio.h>
-
-int board_early_init_f(void)
-{
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all */
-	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC3ER, 0x00000000);	/* disable all */
-	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-
-	/*
-	 * Configure PFC (Pin Function Control) registers
-	 * UART0: 2 pins
-	 */
-	mtsdr(SDR0_PFC1, 0x0000000);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts("Board: Bluestone Evaluation Board");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 sdr0_srst1 = 0;
-
-	/* Setup PLB4-AHB bridge based on the system address map */
-	mtdcr(AHB_TOP, 0x8000004B);
-	mtdcr(AHB_BOT, 0x8000004B);
-
-	/*
-	 * The AHB Bridge core is held in reset after power-on or reset
-	 * so enable it now
-	 */
-	mfsdr(SDR0_SRST1, sdr0_srst1);
-	sdr0_srst1 &= ~SDR0_SRST1_AHB;
-	mtsdr(SDR0_SRST1, sdr0_srst1);
-
-	return 0;
-}
diff --git a/qemu/roms/u-boot/board/amcc/bluestone/config.mk b/qemu/roms/u-boot/board/amcc/bluestone/config.mk
deleted file mode 100644
index a947e82af..000000000
--- a/qemu/roms/u-boot/board/amcc/bluestone/config.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (c) 2010, Applied Micro Circuits Corporation
-# Author: Tirumala R Marri <tmarri@apm.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# Applied Micro APM821XX Evaluation board.
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/qemu/roms/u-boot/board/amcc/bluestone/init.S b/qemu/roms/u-boot/board/amcc/bluestone/init.S
deleted file mode 100644
index cf22ca634..000000000
--- a/qemu/roms/u-boot/board/amcc/bluestone/init.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/* TLB 0 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
-	4, AC_RWX | SA_G)
-
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
-			0, AC_RWX | SA_G)
-
-	/* TLB-entry for OCM */
-	tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4,
-			AC_RWX | SA_I)
-
-	/* TLB-entry for Local Configuration registers => peripherals */
-	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K,
-			CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG)
-	tlbtab_end