Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

6 files changed, 986 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/arch/nds32/lib/Makefile b/qemu/roms/u-boot/arch/nds32/lib/Makefile
new file mode 100644
index 000000000..6ea96db95
--- /dev/null
+++ b/qemu/roms/u-boot/arch/nds32/lib/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += board.o
+obj-y += cache.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-y += interrupts.o
diff --git a/qemu/roms/u-boot/arch/nds32/lib/asm-offsets.c b/qemu/roms/u-boot/arch/nds32/lib/asm-offsets.c
new file mode 100644
index 000000000..39e3480bd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/nds32/lib/asm-offsets.c
@@ -0,0 +1,82 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+	/*
+	 * TODO : Check if each entry in this file is really necessary.
+	 *   - struct ftahbc02s
+	 *   - struct ftsdmc021
+	 *   - struct andes_pcu
+	 *   - struct dwcddr21mctl
+	 * are used only for generating asm-offsets.h.
+	 * It means their offset addresses are referenced only from assembly
+	 * code. Is it better to define the macros directly in headers?
+	 */
+
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_4,	ftahbc02s, s_bsr[4]);
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTPMU010
+	OFFSET(FTPMU010_PDLLCR0,	ftpmu010, PDLLCR0);
+#endif
+	BLANK();
+#ifdef CONFIG_FTSDMC021
+	OFFSET(FTSDMC021_TP1,		ftsdmc021, tp1);
+	OFFSET(FTSDMC021_TP2,		ftsdmc021, tp2);
+	OFFSET(FTSDMC021_CR1,		ftsdmc021, cr1);
+	OFFSET(FTSDMC021_CR2,		ftsdmc021, cr2);
+	OFFSET(FTSDMC021_BANK0_BSR,	ftsdmc021, bank0_bsr);
+	OFFSET(FTSDMC021_BANK1_BSR,	ftsdmc021, bank1_bsr);
+	OFFSET(FTSDMC021_BANK2_BSR,	ftsdmc021, bank2_bsr);
+	OFFSET(FTSDMC021_BANK3_BSR,	ftsdmc021, bank3_bsr);
+#endif
+	BLANK();
+#ifdef CONFIG_ANDES_PCU
+	OFFSET(ANDES_PCU_PCS4,		andes_pcu, pcs4.parm);	/* 0x104 */
+#endif
+	BLANK();
+#ifdef CONFIG_DWCDDR21MCTL
+	OFFSET(DWCDDR21MCTL_CCR,	dwcddr21mctl, ccr);	/* 0x04 */
+	OFFSET(DWCDDR21MCTL_DCR,	dwcddr21mctl, dcr);	/* 0x04 */
+	OFFSET(DWCDDR21MCTL_IOCR,	dwcddr21mctl, iocr);	/* 0x08 */
+	OFFSET(DWCDDR21MCTL_CSR,	dwcddr21mctl, csr);	/* 0x0c */
+	OFFSET(DWCDDR21MCTL_DRR,	dwcddr21mctl, drr);	/* 0x10 */
+	OFFSET(DWCDDR21MCTL_DLLCR0,	dwcddr21mctl, dllcr[0]); /* 0x24 */
+	OFFSET(DWCDDR21MCTL_DLLCR1,	dwcddr21mctl, dllcr[1]); /* 0x28 */
+	OFFSET(DWCDDR21MCTL_DLLCR2,	dwcddr21mctl, dllcr[2]); /* 0x2c */
+	OFFSET(DWCDDR21MCTL_DLLCR3,	dwcddr21mctl, dllcr[3]); /* 0x30 */
+	OFFSET(DWCDDR21MCTL_DLLCR4,	dwcddr21mctl, dllcr[4]); /* 0x34 */
+	OFFSET(DWCDDR21MCTL_DLLCR5,	dwcddr21mctl, dllcr[5]); /* 0x38 */
+	OFFSET(DWCDDR21MCTL_DLLCR6,	dwcddr21mctl, dllcr[6]); /* 0x3c */
+	OFFSET(DWCDDR21MCTL_DLLCR7,	dwcddr21mctl, dllcr[7]); /* 0x40 */
+	OFFSET(DWCDDR21MCTL_DLLCR8,	dwcddr21mctl, dllcr[8]); /* 0x44 */
+	OFFSET(DWCDDR21MCTL_DLLCR9,	dwcddr21mctl, dllcr[9]); /* 0x48 */
+	OFFSET(DWCDDR21MCTL_RSLR0,	dwcddr21mctl, rslr[0]);	/* 0x4c */
+	OFFSET(DWCDDR21MCTL_RDGR0,	dwcddr21mctl, rdgr[0]);	/* 0x5c */
+	OFFSET(DWCDDR21MCTL_DTAR,	dwcddr21mctl, dtar);	/* 0xa4 */
+	OFFSET(DWCDDR21MCTL_MR,		dwcddr21mctl, mr);	/* 0x1f0 */
+#endif
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/nds32/lib/board.c b/qemu/roms/u-boot/arch/nds32/lib/board.c
new file mode 100644
index 000000000..4c06a4866
--- /dev/null
+++ b/qemu/roms/u-boot/arch/nds32/lib/board.c
@@ -0,0 +1,398 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SYS_I2C)
+#include <i2c.h>
+#endif
+
+ulong monitor_flash_len;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
+	return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+	puts("Flash: ");
+	print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__	/* AG101: internal definition in toolchain */
+	ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+	ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+	ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif	/* __NDS32_N1213_43U1H__ */
+#endif
+	return 0;
+}
+#endif
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+void __dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size =  gd->ram_size;
+}
+void dram_init_banksize(void)
+	__attribute__((weak, alias("__dram_init_banksize")));
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	pmu_init,
+#endif
+#endif
+	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+	display_dram_config,
+	NULL,
+};
+
+void board_init_f(ulong bootflag)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	gd_t *id;
+	ulong addr, addr_sp;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
+
+	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+
+	gd->mon_len = (unsigned int)(&__bss_end) - (unsigned int)(&_start);
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	debug("monitor len: %08lX\n", gd->mon_len);
+	/*
+	 * Ram is setup, size stored in gd !!
+	 */
+	debug("ramsize: %08lX\n", gd->ram_size);
+
+	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
+
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+	gd->fb_base = CONFIG_FB_ADDR;
+#else
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
+	/*
+	 * reserve memory for U-Boot code, data & bss
+	 * round down to next 4 kB limit
+	 */
+	addr -= gd->mon_len;
+	addr &= ~(4096 - 1);
+
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+
+	/*
+	 * reserve memory for malloc() arena
+	 */
+	addr_sp = addr - TOTAL_MALLOC_LEN;
+	debug("Reserving %dk for malloc() at: %08lx\n",
+			TOTAL_MALLOC_LEN >> 10, addr_sp);
+	/*
+	 * (permanently) allocate a Board Info struct
+	 * and a permanent copy of the "global" data
+	 */
+	addr_sp -= GENERATED_BD_INFO_SIZE;
+	bd = (bd_t *) addr_sp;
+	gd->bd = bd;
+	memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+			GENERATED_BD_INFO_SIZE, addr_sp);
+
+	addr_sp -= GENERATED_GBL_DATA_SIZE;
+	id = (gd_t *) addr_sp;
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			GENERATED_GBL_DATA_SIZE, addr_sp);
+
+	/* setup stackpointer for exeptions */
+	gd->irq_sp = addr_sp;
+#ifdef CONFIG_USE_IRQ
+	addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
+#endif
+	/* leave 3 words for abort-stack    */
+	addr_sp -= 12;
+
+	/* 8-byte alignment for ABI compliance */
+	addr_sp &= ~0x07;
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
+
+	/* Ram isn't board specific, so move it to board code ... */
+	dram_init_banksize();
+	display_dram_config();	/* and display it */
+
+	gd->relocaddr = addr;
+	gd->start_addr_sp = addr_sp;
+
+	gd->reloc_off = addr - _TEXT_BASE;
+
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	memcpy(id, (void *)gd, GENERATED_GBL_DATA_SIZE);
+
+	relocate_code(addr_sp, id, addr);
+
+	/* NOTREACHED - relocate_code() does not return */
+}
+
+/*
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	bd_t *bd;
+	ulong malloc_start;
+
+	gd = id;
+	bd = gd->bd;
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	monitor_flash_len = (ulong)&_end - (ulong)&_start;
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
+
+	board_init();	/* Setup chipselects */
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+	/*
+	 * We have to relocate the command table manually
+	 */
+	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+			ll_entry_count(cmd_tbl_t, cmd));
+#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
+
+	serial_initialize();
+
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+	mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+
+#ifndef CONFIG_SYS_NO_FLASH
+	/* configure available FLASH banks */
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	gd->bd->bi_flashsize = flash_init();
+	gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+	if (gd->bd->bi_flashsize)
+			display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#if defined(CONFIG_CMD_IDE)
+	puts("IDE:   ");
+	ide_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+#if defined(CONFIG_SYS_I2C_ADAPTERS)
+	i2c_reloc_fixup();
+#endif
+
+	/* initialize environment */
+	env_relocate();
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	puts("PCI:   ");
+	nds32_pci_init();
+#endif
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+#if defined(CONFIG_USE_IRQ)
+	/* set up exceptions */
+	interrupt_init();
+	/* enable exceptions */
+	enable_interrupts();
+#endif
+
+	/* Initialize from environment */
+	load_addr = getenv_ulong("loadaddr", 16, load_addr);
+
+#ifdef CONFIG_BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#if defined(CONFIG_CMD_NET)
+	puts("Net:   ");
+
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
diff --git a/qemu/roms/u-boot/arch/nds32/lib/bootm.c b/qemu/roms/u-boot/arch/nds32/lib/bootm.c
new file mode 100644
index 000000000..8b0b28fd9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/nds32/lib/bootm.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	bd_t	*bd = gd->bd;
+	char	*s;
+	int	machid = bd->bi_arch_number;
+	void	(*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+	char *commandline = getenv("bootargs");
+#endif
+
+	/*
+	 * allow the PREP bootm subcommand, it is required for bootm to work
+	 */
+	if (flag & BOOTM_STATE_OS_PREP)
+		return 0;
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	theKernel = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		machid = simple_strtoul(s, NULL, 16);
+		printf("Using machid 0x%x from environment\n", machid);
+	}
+
+	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+	debug("## Transferring control to Linux (at address %08lx) ...\n",
+	       (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+	setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+	setup_serial_tag(&params);
+#endif
+#ifdef CONFIG_REVISION_TAG
+	setup_revision_tag(&params);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+	setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+	setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+	if (images->rd_start && images->rd_end)
+		setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+	setup_end_tag(bd);
+#endif
+
+	/* we assume that the kernel is in place */
+	printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+	{
+		extern void udc_disconnect(void);
+		udc_disconnect();
+	}
+#endif
+
+	cleanup_before_linux();
+
+	theKernel(0, machid, bd->bi_boot_params);
+	/* does not return */
+
+	return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+	defined(CONFIG_CMDLINE_TAG) || \
+	defined(CONFIG_INITRD_TAG) || \
+	defined(CONFIG_SERIAL_TAG) || \
+	defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size(tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size(tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next(params);
+	}
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++)
+		;
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+	strcpy(params->u.cmdline.cmdline, p)
+		;
+
+	params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size(tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+	void get_board_serial(struct tag_serialnr *serialnr);
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size(tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high = serialnr.high;
+	params = tag_next(params);
+	*tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+	u32 get_board_rev(void);
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size(tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next(params);
+}
+#endif  /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/qemu/roms/u-boot/arch/nds32/lib/cache.c b/qemu/roms/u-boot/arch/nds32/lib/cache.c
new file mode 100644
index 000000000..866dc1a98
--- /dev/null
+++ b/qemu/roms/u-boot/arch/nds32/lib/cache.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2012 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		asm volatile (
+			"\n\tcctl %0, L1D_VA_WB"
+			"\n\tcctl %0, L1D_VA_INVAL"
+			:
+			: "r" (start)
+		);
+		start += line_size;
+	}
+}
+
+void invalidate_icache_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		asm volatile (
+			"\n\tcctl %0, L1I_VA_INVAL"
+			:
+			: "r"(start)
+		);
+		start += line_size;
+	}
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+	while (end > start) {
+		asm volatile (
+			"\n\tcctl %0, L1D_VA_INVAL"
+			:
+			: "r"(start)
+		);
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	flush_dcache_range(addr, addr + size);
+	invalidate_icache_range(addr, addr + size);
+}
+
+void icache_enable(void)
+{
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	return ret;
+}
+
+void dcache_enable(void)
+{
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	return ret;
+}
diff --git a/qemu/roms/u-boot/arch/nds32/lib/interrupts.c b/qemu/roms/u-boot/arch/nds32/lib/interrupts.c
new file mode 100644
index 000000000..d86cc2341
--- /dev/null
+++ b/qemu/roms/u-boot/arch/nds32/lib/interrupts.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+static int int_flag;
+
+int irq_flags;		/* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $psw\n\t"
+		"andi	%0, %0, 0x1\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+	return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return true if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+	int gie_ori_status;
+
+	gie_ori_status = GIE_STATUS();
+
+	local_irq_save(int_flag);
+
+	return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+	printf("\n");
+	printf("pc : [<%08lx>]	sp: [<%08lx>]\n"
+		"lp : %08lx  gp : %08lx  fp : %08lx\n",
+		regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+	printf("D1H: %08lx  D1L: %08lx  D0H: %08lx  D0L: %08lx\n",
+		regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+	printf("r27: %08lx  r26: %08lx  r25: %08lx  r24: %08lx\n",
+		regs->p1, regs->p0, regs->r[25], regs->r[24]);
+	printf("r23: %08lx  r22: %08lx  r21: %08lx  r20: %08lx\n",
+		regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+	printf("r19: %08lx  r18: %08lx  r17: %08lx  r16: %08lx\n",
+		regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+	printf("r15: %08lx  r14: %08lx  r13: %08lx  r12: %08lx\n",
+		regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+	printf("r11: %08lx  r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+	printf("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+	printf("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+	printf("  Interrupts %s  Mode %s\n",
+		interrupts_enabled(regs) ? "on" : "off",
+		processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+	const char *interruption_type[] = {
+		"Reset",
+		"TLB Fill",
+		"TLB Not Present",
+		"TLB Misc",
+		"VLPT Miss",
+		"Cache Parity Error",
+		"Debug",
+		"General Exception",
+		"External Interrupt"
+	};
+
+	printf("%s\n", interruption_type[EVIC_num]);
+	show_regs(pt_regs);
+	bad_mode();
+}