Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to kvmfornfv repo and make use of the updated latest qemu for the execution of all testcase Change-Id: I1280af507a857675c7f81d30c95255635667bdd7 Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
author: RajithaY <rajithax.yerrumsetty@intel.com> 2017-04-25 03:31:15 -0700
committer: Rajitha Yerrumchetty <rajithax.yerrumsetty@intel.com> 2017-05-22 06:48:08 +0000
commit: bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch)
tree: ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/u-boot/arch/mips
parent: a14b48d18a9ed03ec191cf16b162206998a895ce (diff)
61 files changed, 0 insertions, 11944 deletions
diff --git a/qemu/roms/u-boot/arch/mips/config.mk b/qemu/roms/u-boot/arch/mips/config.mk
deleted file mode 100644
index f4a234adb..000000000
--- a/qemu/roms/u-boot/arch/mips/config.mk
+++ /dev/null
@@ -1,58 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := mips_4KC-
-endif
-
-# Handle special prefix in ELDK 4.0 toolchain
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS := -EL
-endif
-
-ifdef CONFIG_SYS_LITTLE_ENDIAN
-ENDIANNESS := -EL
-endif
-
-ifdef CONFIG_SYS_BIG_ENDIAN
-ENDIANNESS := -EB
-endif
-
-# Default to EB if no endianess is configured
-ENDIANNESS ?= -EB
-
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
-
-__HAVE_ARCH_GENERIC_BOARD := y
-
-#
-# From Linux arch/mips/Makefile
-#
-# GCC uses -G 0 -mabicalls -fpic as default.  We don't want PIC in the kernel
-# code since it only slows down the whole thing.  At some point we might make
-# use of global pointer optimizations but their use of $28 conflicts with
-# the current pointer optimization.
-#
-# The DECStation requires an ECOFF kernel for remote booting, other MIPS
-# machines may also.  Since BFD is incredibly buggy with respect to
-# crossformat linking we rely on the elf2ecoff tool for format conversion.
-#
-# cflags-y			+= -G 0 -mno-abicalls -fno-pic -pipe
-# cflags-y			+= -msoft-float
-# LDFLAGS_vmlinux		+= -G 0 -static -n -nostdlib
-# MODFLAGS			+= -mlong-calls
-#
-# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
-# to RAM. $28 is always used as gp.
-#
-PLATFORM_CPPFLAGS		+= -G 0 -mabicalls -fpic $(ENDIANNESS)
-PLATFORM_CPPFLAGS		+= -msoft-float
-PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib $(ENDIANNESS)
-PLATFORM_RELFLAGS		+= -ffunction-sections -fdata-sections
-LDFLAGS_FINAL			+= --gc-sections -pie
-OBJCOPYFLAGS			+= -j .text -j .rodata -j .data -j .got
-OBJCOPYFLAGS			+= -j .u_boot_list -j .rel.dyn
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/Makefile b/qemu/roms/u-boot/arch/mips/cpu/mips32/Makefile
deleted file mode 100644
index e0e6309c6..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y	= start.o
-obj-y	= cache.o
-obj-y	+= cpu.o interrupts.o time.o
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/Makefile b/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/Makefile
deleted file mode 100644
index c5643e713..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2011
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_eth.c b/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
deleted file mode 100644
index 4770f563a..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/* Only eth0 supported for now
- *
- * (C) Copyright 2003
- * Thomas.Lange@corelatus.se
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <config.h>
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-#error "PHY not supported yet"
-/* We just assume that we are running 100FD for now */
-/* We all use switches, right? ;-) */
-#endif
-
-/* I assume ethernet behaves like au1000 */
-
-#ifdef CONFIG_SOC_AU1000
-/* Base address differ between cpu:s */
-#define ETH0_BASE AU1000_ETH0_BASE
-#define MAC0_ENABLE AU1000_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1100
-#define ETH0_BASE AU1100_ETH0_BASE
-#define MAC0_ENABLE AU1100_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1500
-#define ETH0_BASE AU1500_ETH0_BASE
-#define MAC0_ENABLE AU1500_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1550
-#define ETH0_BASE AU1550_ETH0_BASE
-#define MAC0_ENABLE AU1550_MAC0_ENABLE
-#else
-#error "No valid cpu set"
-#endif
-#endif
-#endif
-#endif
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/au1x00.h>
-
-#if defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH  1520
-#define PKT_MAXBUF_SIZE		1518
-
-static char txbuf[DBUF_LENGTH];
-
-static int next_tx;
-static int next_rx;
-
-/* 4 rx and 4 tx fifos */
-#define NO_OF_FIFOS 4
-
-typedef struct{
-	u32 status;
-	u32 addr;
-	u32 len; /* Only used for tx */
-	u32 not_used;
-} mac_fifo_t;
-
-mac_fifo_t mac_fifo[NO_OF_FIFOS];
-
-#define MAX_WAIT 1000
-
-#if defined(CONFIG_CMD_MII)
-int  au1x00_miiphy_read(const char *devname, unsigned char addr,
-		unsigned char reg, unsigned short * value)
-{
-	volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
-	volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
-	u32 mii_control;
-	unsigned int timedout = 20;
-
-	while (*mii_control_reg & MAC_MII_BUSY) {
-		udelay(1000);
-		if (--timedout == 0) {
-			printf("au1x00_eth: miiphy_read busy timeout!!\n");
-			return -1;
-		}
-	}
-
-	mii_control = MAC_SET_MII_SELECT_REG(reg) |
-		MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
-
-	*mii_control_reg = mii_control;
-
-	timedout = 20;
-	while (*mii_control_reg & MAC_MII_BUSY) {
-		udelay(1000);
-		if (--timedout == 0) {
-			printf("au1x00_eth: miiphy_read busy timeout!!\n");
-			return -1;
-		}
-	}
-	*value = *mii_data_reg;
-	return 0;
-}
-
-int  au1x00_miiphy_write(const char *devname, unsigned char addr,
-		unsigned char reg, unsigned short value)
-{
-	volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
-	volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
-	u32 mii_control;
-	unsigned int timedout = 20;
-
-	while (*mii_control_reg & MAC_MII_BUSY) {
-		udelay(1000);
-		if (--timedout == 0) {
-			printf("au1x00_eth: miiphy_write busy timeout!!\n");
-			return -1;
-		}
-	}
-
-	mii_control = MAC_SET_MII_SELECT_REG(reg) |
-		MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
-
-	*mii_data_reg = value;
-	*mii_control_reg = mii_control;
-	return 0;
-}
-#endif
-
-static int au1x00_send(struct eth_device *dev, void *packet, int length)
-{
-	volatile mac_fifo_t *fifo_tx =
-		(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
-	int i;
-	int res;
-
-	/* tx fifo should always be idle */
-	fifo_tx[next_tx].len = length;
-	fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
-	au_sync();
-
-	udelay(1);
-	i=0;
-	while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
-		if(i>MAX_WAIT){
-			printf("TX timeout\n");
-			break;
-		}
-		udelay(1);
-		i++;
-	}
-
-	/* Clear done bit */
-	fifo_tx[next_tx].addr = 0;
-	fifo_tx[next_tx].len = 0;
-	au_sync();
-
-	res = fifo_tx[next_tx].status;
-
-	next_tx++;
-	if(next_tx>=NO_OF_FIFOS){
-		next_tx=0;
-	}
-	return(res);
-}
-
-static int au1x00_recv(struct eth_device* dev){
-	volatile mac_fifo_t *fifo_rx =
-		(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
-
-	int length;
-	u32 status;
-
-	for(;;){
-		if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
-			/* Nothing has been received */
-			return(-1);
-		}
-
-		status = fifo_rx[next_rx].status;
-
-		length = status&0x3FFF;
-
-		if(status&RX_ERROR){
-			printf("Rx error 0x%x\n", status);
-		}
-		else{
-			/* Pass the packet up to the protocol layers. */
-			NetReceive(NetRxPackets[next_rx], length - 4);
-		}
-
-		fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
-
-		next_rx++;
-		if(next_rx>=NO_OF_FIFOS){
-			next_rx=0;
-		}
-	} /* for */
-
-	return(0); /* Does anyone use this? */
-}
-
-static int au1x00_init(struct eth_device* dev, bd_t * bd){
-
-	volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
-	volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
-	volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
-	volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
-	volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
-	volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
-	volatile mac_fifo_t *fifo_tx =
-		(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
-	volatile mac_fifo_t *fifo_rx =
-		(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
-	int i;
-
-	next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
-	next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
-
-	/* We have to enable clocks before releasing reset */
-	*macen = MAC_EN_CLOCK_ENABLE;
-	udelay(10);
-
-	/* Enable MAC0 */
-	/* We have to release reset before accessing registers */
-	*macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
-		MAC_EN_RESET1|MAC_EN_RESET2;
-	udelay(10);
-
-	for(i=0;i<NO_OF_FIFOS;i++){
-		fifo_tx[i].len = 0;
-		fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
-		fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
-	}
-
-	/* Put mac addr in little endian */
-#define ea eth_get_dev()->enetaddr
-	*mac_addr_high	=	(ea[5] <<  8) | (ea[4]	    ) ;
-	*mac_addr_low	=	(ea[3] << 24) | (ea[2] << 16) |
-		(ea[1] <<  8) | (ea[0]	    ) ;
-#undef ea
-	*mac_mcast_low = 0;
-	*mac_mcast_high = 0;
-
-	/* Make sure the MAC buffer is in the correct endian mode */
-#ifdef __LITTLE_ENDIAN
-	*mac_ctrl = MAC_FULL_DUPLEX;
-	udelay(1);
-	*mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
-#else
-	*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
-	udelay(1);
-	*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
-#endif
-
-	return(1);
-}
-
-static void au1x00_halt(struct eth_device* dev){
-	volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
-
-	/* Put MAC0 in reset */
-	*macen = 0;
-}
-
-int au1x00_enet_initialize(bd_t *bis){
-	struct eth_device* dev;
-
-	if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
-		puts ("malloc failed\n");
-		return -1;
-	}
-
-	memset(dev, 0, sizeof *dev);
-
-	sprintf(dev->name, "Au1X00 ethernet");
-	dev->iobase = 0;
-	dev->priv   = 0;
-	dev->init   = au1x00_init;
-	dev->halt   = au1x00_halt;
-	dev->send   = au1x00_send;
-	dev->recv   = au1x00_recv;
-
-	eth_register(dev);
-
-#if defined(CONFIG_CMD_MII)
-	miiphy_register(dev->name,
-		au1x00_miiphy_read, au1x00_miiphy_write);
-#endif
-
-	return 1;
-}
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_ide.c b/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_ide.c
deleted file mode 100644
index ba0b35df5..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_ide.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2000-2011
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ide.h>
-
-/* AU1X00 swaps data in big-endian mode, enforce little-endian function */
-void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
-	ide_input_data(dev, sect_buf, words);
-}
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_serial.c b/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_serial.c
deleted file mode 100644
index 046350826..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_serial.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * AU1X00 UART support
- *
- * Hardcoded to UART 0 for now
- * Speed and options also hardcoded to 115200 8N1
- *
- *  Copyright (c) 2003	Thomas.Lange@corelatus.se
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/au1x00.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-/******************************************************************************
-*
-* serial_init - initialize a channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-static int au1x00_serial_init(void)
-{
-	volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
-	volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
-
-	/* Enable clocks first */
-	*uart_enable = UART_EN_CE;
-
-	/* Then release reset */
-	/* Must release reset before setting other regs */
-	*uart_enable = UART_EN_CE|UART_EN_E;
-
-	/* Activate fifos, reset tx and rx */
-	/* Set tx trigger level to 12 */
-	*uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
-		UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
-
-	serial_setbrg();
-
-	return 0;
-}
-
-
-static void au1x00_serial_setbrg(void)
-{
-	volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
-	volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
-	volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
-	int sd;
-	int divisorx2;
-
-	/* sd is system clock divisor			*/
-	/* see section 10.4.5 in au1550 datasheet	*/
-	sd = (*sys_powerctrl & 0x03) + 2;
-
-	/* calulate 2x baudrate and round */
-	divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
-
-	if (divisorx2 & 0x01)
-		divisorx2 = divisorx2 + 1;
-
-	*uart_clk = divisorx2 / 2;
-
-	/* Set parity, stop bits and word length to 8N1 */
-	*uart_lcr = UART_LCR_WLEN8;
-}
-
-static void au1x00_serial_putc(const char c)
-{
-	volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
-	volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
-
-	if (c == '\n')
-		au1x00_serial_putc('\r');
-
-	/* Wait for fifo to shift out some bytes */
-	while((*uart_lsr&UART_LSR_THRE)==0);
-
-	*uart_tx = (u32)c;
-}
-
-static int au1x00_serial_getc(void)
-{
-	volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
-	char c;
-
-	while (!serial_tstc());
-
-	c = (*uart_rx&0xFF);
-	return c;
-}
-
-static int au1x00_serial_tstc(void)
-{
-	volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
-
-	if(*uart_lsr&UART_LSR_DR){
-		/* Data in rfifo */
-		return(1);
-	}
-	return 0;
-}
-
-static struct serial_device au1x00_serial_drv = {
-	.name	= "au1x00_serial",
-	.start	= au1x00_serial_init,
-	.stop	= NULL,
-	.setbrg	= au1x00_serial_setbrg,
-	.putc	= au1x00_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= au1x00_serial_getc,
-	.tstc	= au1x00_serial_tstc,
-};
-
-void au1x00_serial_initialize(void)
-{
-	serial_register(&au1x00_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &au1x00_serial_drv;
-}
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c
deleted file mode 100644
index a3dac7079..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c
+++ /dev/null
@@ -1,1611 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
- *
- * (C) Copyright 2003
- * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- * Note: Part of this code has been derived from linux
- *
- */
-/*
- * IMPORTANT NOTES
- * 1 - this driver is intended for use with USB Mass Storage Devices
- *     (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
- */
-
-#include <config.h>
-
-#ifdef CONFIG_USB_OHCI
-
-/* #include <pci.h> no PCI on the AU1x00 */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/au1x00.h>
-#include <usb.h>
-#include "au1x00_usb_ohci.h"
-
-#define OHCI_USE_NPS		/* force NoPowerSwitching mode */
-#define OHCI_VERBOSE_DEBUG	/* not always helpful */
-#define OHCI_FILL_TRACE
-
-#define USBH_ENABLE_BE (1<<0)
-#define USBH_ENABLE_C  (1<<1)
-#define USBH_ENABLE_E  (1<<2)
-#define USBH_ENABLE_CE (1<<3)
-#define USBH_ENABLE_RD (1<<4)
-
-#ifdef __LITTLE_ENDIAN
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
-#else
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
-#endif
-
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define OHCI_CONTROL_INIT \
-	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-
-#undef readl
-#undef writel
-
-#define readl(a)     au_readl((long)(a))
-#define writel(v,a)  au_writel((v),(int)(a))
-
-#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-
-#define DEBUG
-#ifdef DEBUG
-#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
-#else
-#define dbg(format, arg...) do {} while(0)
-#endif /* DEBUG */
-#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
-#define SHOW_INFO
-#ifdef SHOW_INFO
-#define info(format, arg...) printf("INFO: " format "\n", ## arg)
-#else
-#define info(format, arg...) do {} while(0)
-#endif
-
-#define m16_swap(x) swap_16(x)
-#define m32_swap(x) swap_32(x)
-
-/* global ohci_t */
-static ohci_t gohci;
-/* this must be aligned to a 256 byte boundary */
-struct ohci_hcca ghcca[1];
-/* a pointer to the aligned storage */
-struct ohci_hcca *phcca;
-/* this allocates EDs for all possible endpoints */
-struct ohci_device ohci_dev;
-/* urb_priv */
-urb_priv_t urb_priv;
-/* RHSC flag */
-int got_rhsc;
-/* device which was disconnected */
-struct usb_device *devgone;
-
-/*-------------------------------------------------------------------------*/
-
-/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
- * The erratum (#4) description is incorrect.  AMD's workaround waits
- * till some bits (mostly reserved) are clear; ok for all revs.
- */
-#define OHCI_QUIRK_AMD756 0xabcd
-#define read_roothub(hc, register, mask) ({ \
-	u32 temp = readl (&hc->regs->roothub.register); \
-	if (hc->flags & OHCI_QUIRK_AMD756) \
-		while (temp & mask) \
-			temp = readl (&hc->regs->roothub.register); \
-	temp; })
-
-static u32 roothub_a (struct ohci *hc)
-	{ return read_roothub (hc, a, 0xfc0fe000); }
-static inline u32 roothub_b (struct ohci *hc)
-	{ return readl (&hc->regs->roothub.b); }
-static inline u32 roothub_status (struct ohci *hc)
-	{ return readl (&hc->regs->roothub.status); }
-static u32 roothub_portstatus (struct ohci *hc, int i)
-	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
-
-
-/* forward declaration */
-static int hc_interrupt (void);
-static void
-td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
-	int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
-
-/*-------------------------------------------------------------------------*
- * URB support functions
- *-------------------------------------------------------------------------*/
-
-/* free HCD-private data associated with this URB */
-
-static void urb_free_priv (urb_priv_t * urb)
-{
-	int		i;
-	int		last;
-	struct td	* td;
-
-	last = urb->length - 1;
-	if (last >= 0) {
-		for (i = 0; i <= last; i++) {
-			td = urb->td[i];
-			if (td) {
-				td->usb_dev = NULL;
-				urb->td[i] = NULL;
-			}
-		}
-	}
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-static int sohci_get_current_frame_number (struct usb_device * dev);
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header */
-
-static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
-	int transfer_len, struct devrequest * setup, char * str, int small)
-{
-	urb_priv_t * purb = &urb_priv;
-
-	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
-			str,
-			sohci_get_current_frame_number (dev),
-			usb_pipedevice (pipe),
-			usb_pipeendpoint (pipe),
-			usb_pipeout (pipe)? 'O': 'I',
-			usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
-				(usb_pipecontrol (pipe)? "CTRL": "BULK"),
-			purb->actual_length,
-			transfer_len, dev->status);
-#ifdef	OHCI_VERBOSE_DEBUG
-	if (!small) {
-		int i, len;
-
-		if (usb_pipecontrol (pipe)) {
-			printf (__FILE__ ": cmd(8):");
-			for (i = 0; i < 8 ; i++)
-				printf (" %02x", ((__u8 *) setup) [i]);
-			printf ("\n");
-		}
-		if (transfer_len > 0 && buffer) {
-			printf (__FILE__ ": data(%d/%d):",
-				purb->actual_length,
-				transfer_len);
-			len = usb_pipeout (pipe)?
-					transfer_len: purb->actual_length;
-			for (i = 0; i < 16 && i < len; i++)
-				printf (" %02x", ((__u8 *) buffer) [i]);
-			printf ("%s\n", i < len? "...": "");
-		}
-	}
-#endif
-}
-
-/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
-void ep_print_int_eds (ohci_t *ohci, char * str) {
-	int i, j;
-	 __u32 * ed_p;
-	for (i= 0; i < 32; i++) {
-		j = 5;
-		ed_p = &(ohci->hcca->int_table [i]);
-		if (*ed_p == 0)
-		    continue;
-		printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
-		while (*ed_p != 0 && j--) {
-			ed_t *ed = (ed_t *)m32_swap(ed_p);
-			printf (" ed: %4x;", ed->hwINFO);
-			ed_p = &ed->hwNextED;
-		}
-		printf ("\n");
-	}
-}
-
-static void ohci_dump_intr_mask (char *label, __u32 mask)
-{
-	dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
-		label,
-		mask,
-		(mask & OHCI_INTR_MIE) ? " MIE" : "",
-		(mask & OHCI_INTR_OC) ? " OC" : "",
-		(mask & OHCI_INTR_RHSC) ? " RHSC" : "",
-		(mask & OHCI_INTR_FNO) ? " FNO" : "",
-		(mask & OHCI_INTR_UE) ? " UE" : "",
-		(mask & OHCI_INTR_RD) ? " RD" : "",
-		(mask & OHCI_INTR_SF) ? " SF" : "",
-		(mask & OHCI_INTR_WDH) ? " WDH" : "",
-		(mask & OHCI_INTR_SO) ? " SO" : ""
-		);
-}
-
-static void maybe_print_eds (char *label, __u32 value)
-{
-	ed_t *edp = (ed_t *)value;
-
-	if (value) {
-		dbg ("%s %08x", label, value);
-		dbg ("%08x", edp->hwINFO);
-		dbg ("%08x", edp->hwTailP);
-		dbg ("%08x", edp->hwHeadP);
-		dbg ("%08x", edp->hwNextED);
-	}
-}
-
-static char * hcfs2string (int state)
-{
-	switch (state) {
-		case OHCI_USB_RESET:	return "reset";
-		case OHCI_USB_RESUME:	return "resume";
-		case OHCI_USB_OPER:	return "operational";
-		case OHCI_USB_SUSPEND:	return "suspend";
-	}
-	return "?";
-}
-
-/* dump control and status registers */
-static void ohci_dump_status (ohci_t *controller)
-{
-	struct ohci_regs	*regs = controller->regs;
-	__u32			temp;
-
-	temp = readl (&regs->revision) & 0xff;
-	if (temp != 0x10)
-		dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
-	temp = readl (&regs->control);
-	dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
-		(temp & OHCI_CTRL_RWE) ? " RWE" : "",
-		(temp & OHCI_CTRL_RWC) ? " RWC" : "",
-		(temp & OHCI_CTRL_IR) ? " IR" : "",
-		hcfs2string (temp & OHCI_CTRL_HCFS),
-		(temp & OHCI_CTRL_BLE) ? " BLE" : "",
-		(temp & OHCI_CTRL_CLE) ? " CLE" : "",
-		(temp & OHCI_CTRL_IE) ? " IE" : "",
-		(temp & OHCI_CTRL_PLE) ? " PLE" : "",
-		temp & OHCI_CTRL_CBSR
-		);
-
-	temp = readl (&regs->cmdstatus);
-	dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
-		(temp & OHCI_SOC) >> 16,
-		(temp & OHCI_OCR) ? " OCR" : "",
-		(temp & OHCI_BLF) ? " BLF" : "",
-		(temp & OHCI_CLF) ? " CLF" : "",
-		(temp & OHCI_HCR) ? " HCR" : ""
-		);
-
-	ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
-	ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
-
-	maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
-
-	maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
-	maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
-
-	maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
-	maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
-
-	maybe_print_eds ("donehead", readl (&regs->donehead));
-}
-
-static void ohci_dump_roothub (ohci_t *controller, int verbose)
-{
-	__u32			temp, ndp, i;
-
-	temp = roothub_a (controller);
-	ndp = (temp & RH_A_NDP);
-
-	if (verbose) {
-		dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
-			((temp & RH_A_POTPGT) >> 24) & 0xff,
-			(temp & RH_A_NOCP) ? " NOCP" : "",
-			(temp & RH_A_OCPM) ? " OCPM" : "",
-			(temp & RH_A_DT) ? " DT" : "",
-			(temp & RH_A_NPS) ? " NPS" : "",
-			(temp & RH_A_PSM) ? " PSM" : "",
-			ndp
-			);
-		temp = roothub_b (controller);
-		dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
-			temp,
-			(temp & RH_B_PPCM) >> 16,
-			(temp & RH_B_DR)
-			);
-		temp = roothub_status (controller);
-		dbg ("roothub.status: %08x%s%s%s%s%s%s",
-			temp,
-			(temp & RH_HS_CRWE) ? " CRWE" : "",
-			(temp & RH_HS_OCIC) ? " OCIC" : "",
-			(temp & RH_HS_LPSC) ? " LPSC" : "",
-			(temp & RH_HS_DRWE) ? " DRWE" : "",
-			(temp & RH_HS_OCI) ? " OCI" : "",
-			(temp & RH_HS_LPS) ? " LPS" : ""
-			);
-	}
-
-	for (i = 0; i < ndp; i++) {
-		temp = roothub_portstatus (controller, i);
-		dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
-			i,
-			temp,
-			(temp & RH_PS_PRSC) ? " PRSC" : "",
-			(temp & RH_PS_OCIC) ? " OCIC" : "",
-			(temp & RH_PS_PSSC) ? " PSSC" : "",
-			(temp & RH_PS_PESC) ? " PESC" : "",
-			(temp & RH_PS_CSC) ? " CSC" : "",
-
-			(temp & RH_PS_LSDA) ? " LSDA" : "",
-			(temp & RH_PS_PPS) ? " PPS" : "",
-			(temp & RH_PS_PRS) ? " PRS" : "",
-			(temp & RH_PS_POCI) ? " POCI" : "",
-			(temp & RH_PS_PSS) ? " PSS" : "",
-
-			(temp & RH_PS_PES) ? " PES" : "",
-			(temp & RH_PS_CCS) ? " CCS" : ""
-			);
-	}
-}
-
-static void ohci_dump (ohci_t *controller, int verbose)
-{
-	dbg ("OHCI controller usb-%s state", controller->slot_name);
-
-	/* dumps some of the state we know about */
-	ohci_dump_status (controller);
-	if (verbose)
-		ep_print_int_eds (controller, "hcca");
-	dbg ("hcca frame #%04x", controller->hcca->frame_no);
-	ohci_dump_roothub (controller, 1);
-}
-
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*
- * Interface functions (URB)
- *-------------------------------------------------------------------------*/
-
-/* get a transfer request */
-
-int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len, struct devrequest *setup, int interval)
-{
-	ohci_t *ohci;
-	ed_t * ed;
-	urb_priv_t *purb_priv;
-	int i, size = 0;
-
-	ohci = &gohci;
-
-	/* when controller's hung, permit only roothub cleanup attempts
-	 * such as powering down ports */
-	if (ohci->disabled) {
-		err("sohci_submit_job: EPIPE");
-		return -1;
-	}
-
-	/* every endpoint has a ed, locate and fill it */
-	if (!(ed = ep_add_ed (dev, pipe))) {
-		err("sohci_submit_job: ENOMEM");
-		return -1;
-	}
-
-	/* for the private part of the URB we need the number of TDs (size) */
-	switch (usb_pipetype (pipe)) {
-		case PIPE_BULK: /* one TD for every 4096 Byte */
-			size = (transfer_len - 1) / 4096 + 1;
-			break;
-		case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
-			size = (transfer_len == 0)? 2:
-						(transfer_len - 1) / 4096 + 3;
-			break;
-	}
-
-	if (size >= (N_URB_TD - 1)) {
-		err("need %d TDs, only have %d", size, N_URB_TD);
-		return -1;
-	}
-	purb_priv = &urb_priv;
-	purb_priv->pipe = pipe;
-
-	/* fill the private part of the URB */
-	purb_priv->length = size;
-	purb_priv->ed = ed;
-	purb_priv->actual_length = 0;
-
-	/* allocate the TDs */
-	/* note that td[0] was allocated in ep_add_ed */
-	for (i = 0; i < size; i++) {
-		purb_priv->td[i] = td_alloc (dev);
-		if (!purb_priv->td[i]) {
-			purb_priv->length = i;
-			urb_free_priv (purb_priv);
-			err("sohci_submit_job: ENOMEM");
-			return -1;
-		}
-	}
-
-	if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
-		urb_free_priv (purb_priv);
-		err("sohci_submit_job: EINVAL");
-		return -1;
-	}
-
-	/* link the ed into a chain if is not already */
-	if (ed->state != ED_OPER)
-		ep_link (ohci, ed);
-
-	/* fill the TDs and link it to the ed */
-	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
-
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-/* tell us the current USB frame number */
-
-static int sohci_get_current_frame_number (struct usb_device *usb_dev)
-{
-	ohci_t *ohci = &gohci;
-
-	return m16_swap (ohci->hcca->frame_no);
-}
-#endif
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-/* link an ed into one of the HC chains */
-
-static int ep_link (ohci_t *ohci, ed_t *edi)
-{
-	volatile ed_t *ed = edi;
-
-	ed->state = ED_OPER;
-
-	switch (ed->type) {
-	case PIPE_CONTROL:
-		ed->hwNextED = 0;
-		if (ohci->ed_controltail == NULL) {
-			writel ((long)ed, &ohci->regs->ed_controlhead);
-		} else {
-			ohci->ed_controltail->hwNextED = m32_swap (ed);
-		}
-		ed->ed_prev = ohci->ed_controltail;
-		if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
-			!ohci->ed_rm_list[1] && !ohci->sleeping) {
-			ohci->hc_control |= OHCI_CTRL_CLE;
-			writel (ohci->hc_control, &ohci->regs->control);
-		}
-		ohci->ed_controltail = edi;
-		break;
-
-	case PIPE_BULK:
-		ed->hwNextED = 0;
-		if (ohci->ed_bulktail == NULL) {
-			writel ((long)ed, &ohci->regs->ed_bulkhead);
-		} else {
-			ohci->ed_bulktail->hwNextED = m32_swap (ed);
-		}
-		ed->ed_prev = ohci->ed_bulktail;
-		if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
-			!ohci->ed_rm_list[1] && !ohci->sleeping) {
-			ohci->hc_control |= OHCI_CTRL_BLE;
-			writel (ohci->hc_control, &ohci->regs->control);
-		}
-		ohci->ed_bulktail = edi;
-		break;
-	}
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* unlink an ed from one of the HC chains.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed */
-
-static int ep_unlink (ohci_t *ohci, ed_t *ed)
-{
-	ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
-
-	switch (ed->type) {
-	case PIPE_CONTROL:
-		if (ed->ed_prev == NULL) {
-			if (!ed->hwNextED) {
-				ohci->hc_control &= ~OHCI_CTRL_CLE;
-				writel (ohci->hc_control, &ohci->regs->control);
-			}
-			writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
-		} else {
-			ed->ed_prev->hwNextED = ed->hwNextED;
-		}
-		if (ohci->ed_controltail == ed) {
-			ohci->ed_controltail = ed->ed_prev;
-		} else {
-			((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
-		}
-		break;
-
-	case PIPE_BULK:
-		if (ed->ed_prev == NULL) {
-			if (!ed->hwNextED) {
-				ohci->hc_control &= ~OHCI_CTRL_BLE;
-				writel (ohci->hc_control, &ohci->regs->control);
-			}
-			writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
-		} else {
-			ed->ed_prev->hwNextED = ed->hwNextED;
-		}
-		if (ohci->ed_bulktail == ed) {
-			ohci->ed_bulktail = ed->ed_prev;
-		} else {
-			((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
-		}
-		break;
-	}
-	ed->state = ED_UNLINK;
-	return 0;
-}
-
-
-/*-------------------------------------------------------------------------*/
-
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
- * but the USB stack is a little bit stateless	so we do it at every transaction
- * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
- * in all other cases the state is left unchanged
- * the ed info fields are setted anyway even though most of them should not change */
-
-static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
-{
-	td_t *td;
-	ed_t *ed_ret;
-	volatile ed_t *ed;
-
-	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
-			(usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
-
-	if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
-		err("ep_add_ed: pending delete");
-		/* pending delete request */
-		return NULL;
-	}
-
-	if (ed->state == ED_NEW) {
-		ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
-		/* dummy td; end of td list for ed */
-		td = td_alloc (usb_dev);
-		ed->hwTailP = m32_swap (td);
-		ed->hwHeadP = ed->hwTailP;
-		ed->state = ED_UNLINK;
-		ed->type = usb_pipetype (pipe);
-		ohci_dev.ed_cnt++;
-	}
-
-	ed->hwINFO = m32_swap (usb_pipedevice (pipe)
-			| usb_pipeendpoint (pipe) << 7
-			| (usb_pipeisoc (pipe)? 0x8000: 0)
-			| (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
-			| (usb_dev->speed == USB_SPEED_LOW) << 13
-			| usb_maxpacket (usb_dev, pipe) << 16);
-
-	return ed_ret;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void td_fill (ohci_t *ohci, unsigned int info,
-	void *data, int len,
-	struct usb_device *dev, int index, urb_priv_t *urb_priv)
-{
-	volatile td_t  *td, *td_pt;
-#ifdef OHCI_FILL_TRACE
-	int i;
-#endif
-
-	if (index > urb_priv->length) {
-		err("index > length");
-		return;
-	}
-	/* use this td as the next dummy */
-	td_pt = urb_priv->td [index];
-	td_pt->hwNextTD = 0;
-
-	/* fill the old dummy TD */
-	td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
-
-	td->ed = urb_priv->ed;
-	td->next_dl_td = NULL;
-	td->index = index;
-	td->data = (__u32)data;
-#ifdef OHCI_FILL_TRACE
-	if (1 || (usb_pipebulk(urb_priv->pipe) &&
-				usb_pipeout(urb_priv->pipe))) {
-		for (i = 0; i < len; i++)
-		printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
-	}
-#endif
-	if (!len)
-		data = 0;
-
-	td->hwINFO = m32_swap (info);
-	td->hwCBP = m32_swap (data);
-	if (data)
-		td->hwBE = m32_swap (data + len - 1);
-	else
-		td->hwBE = 0;
-	td->hwNextTD = m32_swap (td_pt);
-	td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
-
-	/* append to queue */
-	td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* prepare all TDs of a transfer */
-
-#define kseg_to_phys(x)	  ((void *)((__u32)(x) - 0x80000000))
-
-static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
-	int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
-{
-	ohci_t *ohci = &gohci;
-	int data_len = transfer_len;
-	void *data;
-	int cnt = 0;
-	__u32 info = 0;
-	unsigned int toggle = 0;
-
-	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
-	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
-		toggle = TD_T_TOGGLE;
-	} else {
-		toggle = TD_T_DATA0;
-		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
-	}
-	urb->td_cnt = 0;
-	if (data_len)
-		data = kseg_to_phys(buffer);
-	else
-		data = 0;
-
-	switch (usb_pipetype (pipe)) {
-	case PIPE_BULK:
-		info = usb_pipeout (pipe)?
-			TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
-		while(data_len > 4096) {
-			td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
-			data += 4096; data_len -= 4096; cnt++;
-		}
-		info = usb_pipeout (pipe)?
-			TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
-		td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
-		cnt++;
-
-		if (!ohci->sleeping)
-			writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
-		break;
-
-	case PIPE_CONTROL:
-		info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
-		td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
-		if (data_len > 0) {
-			info = usb_pipeout (pipe)?
-				TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
-			/* NOTE:  mishandles transfers >8K, some >4K */
-			td_fill (ohci, info, data, data_len, dev, cnt++, urb);
-		}
-		info = usb_pipeout (pipe)?
-			TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
-		td_fill (ohci, info, data, 0, dev, cnt++, urb);
-		if (!ohci->sleeping)
-			writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
-		break;
-	}
-	if (urb->length != cnt)
-		dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-
-/* calculate the transfer length and update the urb */
-
-static void dl_transfer_length(td_t * td)
-{
-	__u32 tdINFO, tdBE, tdCBP;
-	urb_priv_t *lurb_priv = &urb_priv;
-
-	tdINFO = m32_swap (td->hwINFO);
-	tdBE   = m32_swap (td->hwBE);
-	tdCBP  = m32_swap (td->hwCBP);
-
-
-	if (!(usb_pipecontrol(lurb_priv->pipe) &&
-	    ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
-		if (tdBE != 0) {
-			if (td->hwCBP == 0)
-				lurb_priv->actual_length += tdBE - td->data + 1;
-			else
-				lurb_priv->actual_length += tdCBP - td->data;
-		}
-	}
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* replies to the request have to be on a FIFO basis so
- * we reverse the reversed done-list */
-
-static td_t * dl_reverse_done_list (ohci_t *ohci)
-{
-	__u32 td_list_hc;
-	td_t *td_rev = NULL;
-	td_t *td_list = NULL;
-	urb_priv_t *lurb_priv = NULL;
-
-	td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
-	ohci->hcca->done_head = 0;
-
-	while (td_list_hc) {
-		td_list = (td_t *)td_list_hc;
-
-		if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
-			lurb_priv = &urb_priv;
-			dbg(" USB-error/status: %x : %p",
-					TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
-			if (td_list->ed->hwHeadP & m32_swap (0x1)) {
-				if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
-					td_list->ed->hwHeadP =
-						(lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
-									(td_list->ed->hwHeadP & m32_swap (0x2));
-					lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
-				} else
-					td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
-			}
-		}
-
-		td_list->next_dl_td = td_rev;
-		td_rev = td_list;
-		td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
-	}
-	return td_list;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* td done list */
-static int dl_done_list (ohci_t *ohci, td_t *td_list)
-{
-	td_t *td_list_next = NULL;
-	ed_t *ed;
-	int cc = 0;
-	int stat = 0;
-	/* urb_t *urb; */
-	urb_priv_t *lurb_priv;
-	__u32 tdINFO, edHeadP, edTailP;
-
-	while (td_list) {
-		td_list_next = td_list->next_dl_td;
-
-		lurb_priv = &urb_priv;
-		tdINFO = m32_swap (td_list->hwINFO);
-
-		ed = td_list->ed;
-
-		dl_transfer_length(td_list);
-
-		/* error code of transfer */
-		cc = TD_CC_GET (tdINFO);
-		if (cc != 0) {
-			dbg("ConditionCode %#x", cc);
-			stat = cc_to_error[cc];
-		}
-
-		if (ed->state != ED_NEW) {
-			edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
-			edTailP = m32_swap (ed->hwTailP);
-
-			/* unlink eds if they are not busy */
-			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
-				ep_unlink (ohci, ed);
-		}
-
-		td_list = td_list_next;
-	}
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*
- * Virtual Root Hub
- *-------------------------------------------------------------------------*/
-
-#include <usbroothubdes.h>
-
-/* Hub class-specific descriptor is constructed dynamically */
-
-
-/*-------------------------------------------------------------------------*/
-
-#define OK(x)			len = (x); break
-#ifdef DEBUG
-#define WR_RH_STAT(x)		{info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
-#define WR_RH_PORTSTAT(x)	{info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
-#else
-#define WR_RH_STAT(x)		writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x)	writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
-#endif
-#define RD_RH_STAT		roothub_status(&gohci)
-#define RD_RH_PORTSTAT		roothub_portstatus(&gohci,wIndex-1)
-
-/* request to virtual root hub */
-
-int rh_check_port_status(ohci_t *controller)
-{
-	__u32 temp, ndp, i;
-	int res;
-
-	res = -1;
-	temp = roothub_a (controller);
-	ndp = (temp & RH_A_NDP);
-	for (i = 0; i < ndp; i++) {
-		temp = roothub_portstatus (controller, i);
-		/* check for a device disconnect */
-		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
-			(RH_PS_PESC | RH_PS_CSC)) &&
-			((temp & RH_PS_CCS) == 0)) {
-			res = i;
-			break;
-		}
-	}
-	return res;
-}
-
-static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
-		void *buffer, int transfer_len, struct devrequest *cmd)
-{
-	void * data = buffer;
-	int leni = transfer_len;
-	int len = 0;
-	int stat = 0;
-	__u32 datab[4];
-	__u8 *data_buf = (__u8 *)datab;
-	__u16 bmRType_bReq;
-	__u16 wValue;
-	__u16 wIndex;
-	__u16 wLength;
-
-#ifdef DEBUG
-urb_priv.actual_length = 0;
-pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-	if (usb_pipeint(pipe)) {
-		info("Root-Hub submit IRQ: NOT implemented");
-		return 0;
-	}
-
-	bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
-	wValue	      = m16_swap (cmd->value);
-	wIndex	      = m16_swap (cmd->index);
-	wLength	      = m16_swap (cmd->length);
-
-	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
-		dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
-
-	switch (bmRType_bReq) {
-	/* Request Destination:
-	   without flags: Device,
-	   RH_INTERFACE: interface,
-	   RH_ENDPOINT: endpoint,
-	   RH_CLASS means HUB here,
-	   RH_OTHER | RH_CLASS	almost ever means HUB_PORT here
-	*/
-
-	case RH_GET_STATUS:
-			*(__u16 *) data_buf = m16_swap (1); OK (2);
-	case RH_GET_STATUS | RH_INTERFACE:
-			*(__u16 *) data_buf = m16_swap (0); OK (2);
-	case RH_GET_STATUS | RH_ENDPOINT:
-			*(__u16 *) data_buf = m16_swap (0); OK (2);
-	case RH_GET_STATUS | RH_CLASS:
-			*(__u32 *) data_buf = m32_swap (
-				RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
-			OK (4);
-	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-			*(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
-
-	case RH_CLEAR_FEATURE | RH_ENDPOINT:
-		switch (wValue) {
-			case (RH_ENDPOINT_STALL): OK (0);
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_CLASS:
-		switch (wValue) {
-			case RH_C_HUB_LOCAL_POWER:
-				OK(0);
-			case (RH_C_HUB_OVER_CURRENT):
-					WR_RH_STAT(RH_HS_OCIC); OK (0);
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
-		switch (wValue) {
-			case (RH_PORT_ENABLE):
-					WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
-			case (RH_PORT_SUSPEND):
-					WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
-			case (RH_PORT_POWER):
-					WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
-			case (RH_C_PORT_CONNECTION):
-					WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
-			case (RH_C_PORT_ENABLE):
-					WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
-			case (RH_C_PORT_SUSPEND):
-					WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
-			case (RH_C_PORT_OVER_CURRENT):
-					WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
-			case (RH_C_PORT_RESET):
-					WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
-		}
-		break;
-
-	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
-		switch (wValue) {
-			case (RH_PORT_SUSPEND):
-					WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
-			case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
-					if (RD_RH_PORTSTAT & RH_PS_CCS)
-					    WR_RH_PORTSTAT (RH_PS_PRS);
-					OK (0);
-			case (RH_PORT_POWER):
-					WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
-			case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
-					if (RD_RH_PORTSTAT & RH_PS_CCS)
-					    WR_RH_PORTSTAT (RH_PS_PES );
-					OK (0);
-		}
-		break;
-
-	case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
-
-	case RH_GET_DESCRIPTOR:
-		switch ((wValue & 0xff00) >> 8) {
-			case (0x01): /* device descriptor */
-				len = min_t(unsigned int,
-					  leni,
-					  min_t(unsigned int,
-					      sizeof (root_hub_dev_des),
-					      wLength));
-				data_buf = root_hub_dev_des; OK(len);
-			case (0x02): /* configuration descriptor */
-				len = min_t(unsigned int,
-					  leni,
-					  min_t(unsigned int,
-					      sizeof (root_hub_config_des),
-					      wLength));
-				data_buf = root_hub_config_des; OK(len);
-			case (0x03): /* string descriptors */
-				if(wValue==0x0300) {
-					len = min_t(unsigned int,
-						  leni,
-						  min_t(unsigned int,
-						      sizeof (root_hub_str_index0),
-						      wLength));
-					data_buf = root_hub_str_index0;
-					OK(len);
-				}
-				if(wValue==0x0301) {
-					len = min_t(unsigned int,
-						  leni,
-						  min_t(unsigned int,
-						      sizeof (root_hub_str_index1),
-						      wLength));
-					data_buf = root_hub_str_index1;
-					OK(len);
-			}
-			default:
-				stat = USB_ST_STALLED;
-		}
-		break;
-
-	case RH_GET_DESCRIPTOR | RH_CLASS:
-	    {
-		    __u32 temp = roothub_a (&gohci);
-
-		    data_buf [0] = 9;		/* min length; */
-		    data_buf [1] = 0x29;
-		    data_buf [2] = temp & RH_A_NDP;
-		    data_buf [3] = 0;
-		    if (temp & RH_A_PSM)	/* per-port power switching? */
-			data_buf [3] |= 0x1;
-		    if (temp & RH_A_NOCP)	/* no overcurrent reporting? */
-			data_buf [3] |= 0x10;
-		    else if (temp & RH_A_OCPM)	/* per-port overcurrent reporting? */
-			data_buf [3] |= 0x8;
-
-		    /* corresponds to data_buf[4-7] */
-		    datab [1] = 0;
-		    data_buf [5] = (temp & RH_A_POTPGT) >> 24;
-		    temp = roothub_b (&gohci);
-		    data_buf [7] = temp & RH_B_DR;
-		    if (data_buf [2] < 7) {
-			data_buf [8] = 0xff;
-		    } else {
-			data_buf [0] += 2;
-			data_buf [8] = (temp & RH_B_DR) >> 8;
-			data_buf [10] = data_buf [9] = 0xff;
-		    }
-
-		    len = min_t(unsigned int, leni,
-			      min_t(unsigned int, data_buf [0], wLength));
-		    OK (len);
-		}
-
-	case RH_GET_CONFIGURATION:	*(__u8 *) data_buf = 0x01; OK (1);
-
-	case RH_SET_CONFIGURATION:	WR_RH_STAT (0x10000); OK (0);
-
-	default:
-		dbg ("unsupported root hub command");
-		stat = USB_ST_STALLED;
-	}
-
-#ifdef	DEBUG
-	ohci_dump_roothub (&gohci, 1);
-#else
-	mdelay(1);
-#endif
-
-	len = min_t(int, len, leni);
-	if (data != data_buf)
-	    memcpy (data, data_buf, len);
-	dev->act_len = len;
-	dev->status = stat;
-
-#ifdef DEBUG
-	if (transfer_len)
-		urb_priv.actual_length = transfer_len;
-	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
-#else
-	mdelay(1);
-#endif
-
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* common code for handling submit messages - used for all but root hub */
-/* accesses. */
-int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len, struct devrequest *setup, int interval)
-{
-	int stat = 0;
-	int maxsize = usb_maxpacket(dev, pipe);
-	int timeout;
-
-	/* device pulled? Shortcut the action. */
-	if (devgone == dev) {
-		dev->status = USB_ST_CRC_ERR;
-		return 0;
-	}
-
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-	if (!maxsize) {
-		err("submit_common_message: pipesize for pipe %lx is zero",
-			pipe);
-		return -1;
-	}
-
-	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
-		err("sohci_submit_job failed");
-		return -1;
-	}
-
-	mdelay(10);
-	/* ohci_dump_status(&gohci); */
-
-	/* allow more time for a BULK device to react - some are slow */
-#define BULK_TO	 5000	/* timeout in milliseconds */
-	if (usb_pipebulk(pipe))
-		timeout = BULK_TO;
-	else
-		timeout = 100;
-
-	timeout *= 4;
-	/* wait for it to complete */
-	for (;;) {
-		/* check whether the controller is done */
-		stat = hc_interrupt();
-		if (stat < 0) {
-			stat = USB_ST_CRC_ERR;
-			break;
-		}
-		if (stat >= 0 && stat != 0xff) {
-			/* 0xff is returned for an SF-interrupt */
-			break;
-		}
-		if (--timeout) {
-			udelay(250); /* mdelay(1); */
-		} else {
-			err("CTL:TIMEOUT ");
-			stat = USB_ST_CRC_ERR;
-			break;
-		}
-	}
-	/* we got an Root Hub Status Change interrupt */
-	if (got_rhsc) {
-#ifdef DEBUG
-		ohci_dump_roothub (&gohci, 1);
-#endif
-		got_rhsc = 0;
-		/* abuse timeout */
-		timeout = rh_check_port_status(&gohci);
-		if (timeout >= 0) {
-#if 0 /* this does nothing useful, but leave it here in case that changes */
-			/* the called routine adds 1 to the passed value */
-			usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
-#endif
-			/*
-			 * XXX
-			 * This is potentially dangerous because it assumes
-			 * that only one device is ever plugged in!
-			 */
-			devgone = dev;
-		}
-	}
-
-	dev->status = stat;
-	dev->act_len = transfer_len;
-
-#ifdef DEBUG
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-
-	/* free TDs in urb_priv */
-	urb_free_priv (&urb_priv);
-	return 0;
-}
-
-/* submit routines called from usb.c */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len)
-{
-	info("submit_bulk_msg");
-	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len, struct devrequest *setup)
-{
-	int maxsize = usb_maxpacket(dev, pipe);
-
-	info("submit_control_msg");
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-	if (!maxsize) {
-		err("submit_control_message: pipesize for pipe %lx is zero",
-			pipe);
-		return -1;
-	}
-	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
-		gohci.rh.dev = dev;
-		/* root hub - redirect */
-		return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
-			setup);
-	}
-
-	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
-}
-
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len, int interval)
-{
-	info("submit_int_msg");
-	return -1;
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-/* reset the HC and BUS */
-
-static int hc_reset (ohci_t *ohci)
-{
-	int timeout = 30;
-	int smm_timeout = 50; /* 0,5 sec */
-
-	if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
-		writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
-		info("USB HC TakeOver from SMM");
-		while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
-			mdelay (10);
-			if (--smm_timeout == 0) {
-				err("USB HC TakeOver failed!");
-				return -1;
-			}
-		}
-	}
-
-	/* Disable HC interrupts */
-	writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
-
-	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
-		ohci->slot_name,
-		readl (&ohci->regs->control));
-
-	/* Reset USB (needed by some controllers) */
-	writel (0, &ohci->regs->control);
-
-	/* HC Reset requires max 10 us delay */
-	writel (OHCI_HCR,  &ohci->regs->cmdstatus);
-	while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
-		if (--timeout == 0) {
-			err("USB HC reset timed out!");
-			return -1;
-		}
-		udelay (1);
-	}
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * enable interrupts
- * connect the virtual root hub */
-
-static int hc_start (ohci_t * ohci)
-{
-	__u32 mask;
-	unsigned int fminterval;
-
-	ohci->disabled = 1;
-
-	/* Tell the controller where the control and bulk lists are
-	 * The lists are empty now. */
-
-	writel (0, &ohci->regs->ed_controlhead);
-	writel (0, &ohci->regs->ed_bulkhead);
-
-	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
-
-	fminterval = 0x2edf;
-	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
-	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
-	writel (fminterval, &ohci->regs->fminterval);
-	writel (0x628, &ohci->regs->lsthresh);
-
-	/* start controller operations */
-	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
-	ohci->disabled = 0;
-	writel (ohci->hc_control, &ohci->regs->control);
-
-	/* disable all interrupts */
-	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
-			OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
-			OHCI_INTR_OC | OHCI_INTR_MIE);
-	writel (mask, &ohci->regs->intrdisable);
-	/* clear all interrupts */
-	mask &= ~OHCI_INTR_MIE;
-	writel (mask, &ohci->regs->intrstatus);
-	/* Choose the interrupts we care about now  - but w/o MIE */
-	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
-	writel (mask, &ohci->regs->intrenable);
-
-#ifdef	OHCI_USE_NPS
-	/* required for AMD-756 and some Mac platforms */
-	writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
-		&ohci->regs->roothub.a);
-	writel (RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif	/* OHCI_USE_NPS */
-
-	/* POTPGT delay is bits 24-31, in 2 ms units. */
-	mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
-
-	/* connect the virtual root hub */
-	ohci->rh.devnum = 0;
-
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static int
-hc_interrupt (void)
-{
-	ohci_t *ohci = &gohci;
-	struct ohci_regs *regs = ohci->regs;
-	int ints;
-	int stat = -1;
-
-	if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
-		ints =	OHCI_INTR_WDH;
-	} else {
-		ints = readl (&regs->intrstatus);
-	}
-
-	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
-
-	if (ints & OHCI_INTR_RHSC) {
-		got_rhsc = 1;
-	}
-
-	if (ints & OHCI_INTR_UE) {
-		ohci->disabled++;
-		err ("OHCI Unrecoverable Error, controller usb-%s disabled",
-			ohci->slot_name);
-		/* e.g. due to PCI Master/Target Abort */
-
-#ifdef	DEBUG
-		ohci_dump (ohci, 1);
-#else
-	mdelay(1);
-#endif
-		/* FIXME: be optimistic, hope that bug won't repeat often. */
-		/* Make some non-interrupt context restart the controller. */
-		/* Count and limit the retries though; either hardware or */
-		/* software errors can go forever... */
-		hc_reset (ohci);
-		return -1;
-	}
-
-	if (ints & OHCI_INTR_WDH) {
-		mdelay(1);
-		writel (OHCI_INTR_WDH, &regs->intrdisable);
-		stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
-		writel (OHCI_INTR_WDH, &regs->intrenable);
-	}
-
-	if (ints & OHCI_INTR_SO) {
-		dbg("USB Schedule overrun\n");
-		writel (OHCI_INTR_SO, &regs->intrenable);
-		stat = -1;
-	}
-
-	/* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
-	if (ints & OHCI_INTR_SF) {
-		unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
-		mdelay(1);
-		writel (OHCI_INTR_SF, &regs->intrdisable);
-		if (ohci->ed_rm_list[frame] != NULL)
-			writel (OHCI_INTR_SF, &regs->intrenable);
-		stat = 0xff;
-	}
-
-	writel (ints, &regs->intrstatus);
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------------*/
-
-/* De-allocate all resources.. */
-
-static void hc_release_ohci (ohci_t *ohci)
-{
-	dbg ("USB HC release ohci usb-%s", ohci->slot_name);
-
-	if (!ohci->disabled)
-		hc_reset (ohci);
-}
-
-/*-------------------------------------------------------------------------*/
-
-#define __read_32bit_c0_register(source, sel)				\
-({ int __res;								\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mfc0\t%0, " #source "\n\t"			\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mfc0\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0\n\t"				\
-			: "=r" (__res));				\
-	__res;								\
-})
-
-#define read_c0_prid()		__read_32bit_c0_register($15, 0)
-
-/*
- * low level initalisation routine, called from usb.c
- */
-static char ohci_inited = 0;
-
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
-	u32 pin_func;
-	u32 sys_freqctrl, sys_clksrc;
-	u32 prid = read_c0_prid();
-
-	dbg("in usb_lowlevel_init\n");
-
-	/* zero and disable FREQ2 */
-	sys_freqctrl = au_readl(SYS_FREQCTRL0);
-	sys_freqctrl &= ~0xFFF00000;
-	au_writel(sys_freqctrl, SYS_FREQCTRL0);
-
-	/* zero and disable USBH/USBD clocks */
-	sys_clksrc = au_readl(SYS_CLKSRC);
-	sys_clksrc &= ~0x00007FE0;
-	au_writel(sys_clksrc, SYS_CLKSRC);
-
-	sys_freqctrl = au_readl(SYS_FREQCTRL0);
-	sys_freqctrl &= ~0xFFF00000;
-
-	sys_clksrc = au_readl(SYS_CLKSRC);
-	sys_clksrc &= ~0x00007FE0;
-
-	switch (prid & 0x000000FF) {
-	case 0x00: /* DA */
-	case 0x01: /* HA */
-	case 0x02: /* HB */
-		/* CPU core freq to 48MHz to slow it way down... */
-		au_writel(4, SYS_CPUPLL);
-
-		/*
-		 * Setup 48MHz FREQ2 from CPUPLL for USB Host
-		 */
-		/* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
-		sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
-		au_writel(sys_freqctrl, SYS_FREQCTRL0);
-
-		/* CPU core freq to 384MHz */
-		au_writel(0x20, SYS_CPUPLL);
-
-		printf("Au1000: 48MHz OHCI workaround enabled\n");
-		break;
-
-	default:  /* HC and newer */
-		/* FREQ2 = aux/2 = 48 MHz */
-		sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
-		au_writel(sys_freqctrl, SYS_FREQCTRL0);
-		break;
-	}
-
-	/*
-	 * Route 48MHz FREQ2 into USB Host and/or Device
-	 */
-	sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
-	au_writel(sys_clksrc, SYS_CLKSRC);
-
-	/* configure pins GPIO[14:9] as GPIO */
-	pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
-
-	au_writel(pin_func, SYS_PINFUNC);
-	au_writel(0x2800, SYS_TRIOUTCLR);
-	au_writel(0x0030, SYS_OUTPUTCLR);
-
-	dbg("OHCI board setup complete\n");
-
-	/* enable host controller */
-	au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
-	udelay(1000);
-	au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
-	udelay(1000);
-
-	/* wait for reset complete (read register twice; see au1500 errata) */
-	while (au_readl(USB_HOST_CONFIG),
-	       !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
-		udelay(1000);
-
-	dbg("OHCI clock running\n");
-
-	memset (&gohci, 0, sizeof (ohci_t));
-	memset (&urb_priv, 0, sizeof (urb_priv_t));
-
-	/* align the storage */
-	if ((__u32)&ghcca[0] & 0xff) {
-		err("HCCA not aligned!!");
-		return -1;
-	}
-	phcca = &ghcca[0];
-	info("aligned ghcca %p", phcca);
-	memset(&ohci_dev, 0, sizeof(struct ohci_device));
-	if ((__u32)&ohci_dev.ed[0] & 0x7) {
-		err("EDs not aligned!!");
-		return -1;
-	}
-	memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
-	if ((__u32)gtd & 0x7) {
-		err("TDs not aligned!!");
-		return -1;
-	}
-	ptd = gtd;
-	gohci.hcca = phcca;
-	memset (phcca, 0, sizeof (struct ohci_hcca));
-
-	gohci.disabled = 1;
-	gohci.sleeping = 0;
-	gohci.irq = -1;
-	gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
-
-	gohci.flags = 0;
-	gohci.slot_name = "au1x00";
-
-	dbg("OHCI revision: 0x%08x\n"
-	       "  RH: a: 0x%08x b: 0x%08x\n",
-	       readl(&gohci.regs->revision),
-	       readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
-
-	if (hc_reset (&gohci) < 0)
-		goto errout;
-
-	/* FIXME this is a second HC reset; why?? */
-	writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
-	mdelay (10);
-
-	if (hc_start (&gohci) < 0)
-		goto errout;
-
-#ifdef	DEBUG
-	ohci_dump (&gohci, 1);
-#else
-	mdelay(1);
-#endif
-	ohci_inited = 1;
-	return 0;
-
-  errout:
-	err("OHCI initialization error\n");
-	hc_release_ohci (&gohci);
-	/* Initialization failed */
-	au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
-	return -1;
-}
-
-int usb_lowlevel_stop(int index)
-{
-	/* this gets called really early - before the controller has */
-	/* even been initialized! */
-	if (!ohci_inited)
-		return 0;
-	/* TODO release any interrupts, etc. */
-	/* call hc_release_ohci() here ? */
-	hc_reset (&gohci);
-	/* may not want to do this */
-	/* Disable clock */
-	au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
-	return 0;
-}
-
-#endif /* CONFIG_USB_OHCI */
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h b/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h
deleted file mode 100644
index bb9f35109..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h
+++ /dev/null
@@ -1,416 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB.
- *
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
- *
- * usb-ohci.h
- */
-
-
-static int cc_to_error[16] = {
-
-/* mapping of the OHCI CC status to error codes */
-	/* No  Error  */	0,
-	/* CRC Error  */	USB_ST_CRC_ERR,
-	/* Bit Stuff  */	USB_ST_BIT_ERR,
-	/* Data Togg  */	USB_ST_CRC_ERR,
-	/* Stall      */	USB_ST_STALLED,
-	/* DevNotResp */	-1,
-	/* PIDCheck   */	USB_ST_BIT_ERR,
-	/* UnExpPID   */	USB_ST_BIT_ERR,
-	/* DataOver   */	USB_ST_BUF_ERR,
-	/* DataUnder  */	USB_ST_BUF_ERR,
-	/* reservd    */	-1,
-	/* reservd    */	-1,
-	/* BufferOver */	USB_ST_BUF_ERR,
-	/* BuffUnder  */	USB_ST_BUF_ERR,
-	/* Not Access */	-1,
-	/* Not Access */	-1
-};
-
-/* ED States */
-
-#define ED_NEW		0x00
-#define ED_UNLINK	0x01
-#define ED_OPER		0x02
-#define ED_DEL		0x04
-#define ED_URB_DEL	0x08
-
-/* usb_ohci_ed */
-struct ed {
-	__u32 hwINFO;
-	__u32 hwTailP;
-	__u32 hwHeadP;
-	__u32 hwNextED;
-
-	struct ed *ed_prev;
-	__u8 int_period;
-	__u8 int_branch;
-	__u8 int_load;
-	__u8 int_interval;
-	__u8 state;
-	__u8 type;
-	__u16 last_iso;
-	struct ed *ed_rm_list;
-
-	struct usb_device *usb_dev;
-	__u32 unused[3];
-} __attribute__((aligned(16)));
-typedef struct ed ed_t;
-
-
-/* TD info field */
-#define TD_CC			0xf0000000
-#define TD_CC_GET(td_p)		((td_p >>28) & 0x0f)
-#define TD_CC_SET(td_p, cc)	(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
-#define TD_EC			0x0C000000
-#define TD_T			0x03000000
-#define TD_T_DATA0		0x02000000
-#define TD_T_DATA1		0x03000000
-#define TD_T_TOGGLE		0x00000000
-#define TD_R			0x00040000
-#define TD_DI			0x00E00000
-#define TD_DI_SET(X)		(((X) & 0x07)<< 21)
-#define TD_DP			0x00180000
-#define TD_DP_SETUP		0x00000000
-#define TD_DP_IN		0x00100000
-#define TD_DP_OUT		0x00080000
-
-#define TD_ISO			0x00010000
-#define TD_DEL			0x00020000
-
-/* CC Codes */
-#define TD_CC_NOERROR		0x00
-#define TD_CC_CRC		0x01
-#define TD_CC_BITSTUFFING	0x02
-#define TD_CC_DATATOGGLEM	0x03
-#define TD_CC_STALL		0x04
-#define TD_DEVNOTRESP		0x05
-#define TD_PIDCHECKFAIL		0x06
-#define TD_UNEXPECTEDPID	0x07
-#define TD_DATAOVERRUN		0x08
-#define TD_DATAUNDERRUN		0x09
-#define TD_BUFFEROVERRUN	0x0C
-#define TD_BUFFERUNDERRUN	0x0D
-#define TD_NOTACCESSED		0x0F
-
-
-#define MAXPSW 1
-
-struct td {
-	__u32 hwINFO;
-	__u32 hwCBP;		/* Current Buffer Pointer */
-	__u32 hwNextTD;		/* Next TD Pointer */
-	__u32 hwBE;		/* Memory Buffer End Pointer */
-
-	__u16 hwPSW[MAXPSW];
-	__u8 unused;
-	__u8 index;
-	struct ed *ed;
-	struct td *next_dl_td;
-	struct usb_device *usb_dev;
-	int transfer_len;
-	__u32 data;
-
-	__u32 unused2[2];
-} __attribute__((aligned(32)));
-typedef struct td td_t;
-
-#define OHCI_ED_SKIP	(1 << 14)
-
-/*
- * The HCCA (Host Controller Communications Area) is a 256 byte
- * structure defined in the OHCI spec. that the host controller is
- * told the base address of.  It must be 256-byte aligned.
- */
-
-#define NUM_INTS 32	/* part of the OHCI standard */
-struct ohci_hcca {
-	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
-	__u16	frame_no;		/* current frame number */
-	__u16	pad1;			/* set to 0 on each frame_no change */
-	__u32	done_head;		/* info returned for an interrupt */
-	u8		reserved_for_hc[116];
-} __attribute__((aligned(256)));
-
-
-/*
- * Maximum number of root hub ports.
- */
-#define MAX_ROOT_PORTS	15	/* maximum OHCI root hub ports */
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O
- * region.  This is Memory Mapped I/O.	You must use the readl() and
- * writel() macros defined in asm/io.h to access these!!
- */
-struct ohci_regs {
-	/* control and status registers */
-	__u32	revision;
-	__u32	control;
-	__u32	cmdstatus;
-	__u32	intrstatus;
-	__u32	intrenable;
-	__u32	intrdisable;
-	/* memory pointers */
-	__u32	hcca;
-	__u32	ed_periodcurrent;
-	__u32	ed_controlhead;
-	__u32	ed_controlcurrent;
-	__u32	ed_bulkhead;
-	__u32	ed_bulkcurrent;
-	__u32	donehead;
-	/* frame counters */
-	__u32	fminterval;
-	__u32	fmremaining;
-	__u32	fmnumber;
-	__u32	periodicstart;
-	__u32	lsthresh;
-	/* Root hub ports */
-	struct	ohci_roothub_regs {
-		__u32	a;
-		__u32	b;
-		__u32	status;
-		__u32	portstatus[MAX_ROOT_PORTS];
-	} roothub;
-} __attribute__((aligned(32)));
-
-
-/* OHCI CONTROL AND STATUS REGISTER MASKS */
-
-/*
- * HcControl (control) register masks
- */
-#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
-#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
-#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
-#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
-#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
-#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
-#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
-#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
-#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
-
-/* pre-shifted values for HCFS */
-#	define OHCI_USB_RESET	(0 << 6)
-#	define OHCI_USB_RESUME	(1 << 6)
-#	define OHCI_USB_OPER	(2 << 6)
-#	define OHCI_USB_SUSPEND	(3 << 6)
-
-/*
- * HcCommandStatus (cmdstatus) register masks
- */
-#define OHCI_HCR	(1 << 0)	/* host controller reset */
-#define OHCI_CLF	(1 << 1)	/* control list filled */
-#define OHCI_BLF	(1 << 2)	/* bulk list filled */
-#define OHCI_OCR	(1 << 3)	/* ownership change request */
-#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
-
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
-#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
-#define OHCI_INTR_SF	(1 << 2)	/* start frame */
-#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
-#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
-#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
-#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
-#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
-#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
-
-
-/* Virtual Root HUB */
-struct virt_root_hub {
-	int devnum; /* Address of Root Hub endpoint */
-	void *dev;  /* was urb */
-	void *int_addr;
-	int send;
-	int interval;
-};
-
-/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
-
-/* destination of request */
-#define RH_INTERFACE		0x01
-#define RH_ENDPOINT		0x02
-#define RH_OTHER		0x03
-
-#define RH_CLASS		0x20
-#define RH_VENDOR		0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS		0x0080
-#define RH_CLEAR_FEATURE	0x0100
-#define RH_SET_FEATURE		0x0300
-#define RH_SET_ADDRESS		0x0500
-#define RH_GET_DESCRIPTOR	0x0680
-#define RH_SET_DESCRIPTOR	0x0700
-#define RH_GET_CONFIGURATION	0x0880
-#define RH_SET_CONFIGURATION	0x0900
-#define RH_GET_STATE		0x0280
-#define RH_GET_INTERFACE	0x0A80
-#define RH_SET_INTERFACE	0x0B00
-#define RH_SYNC_FRAME		0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP		0x2000
-
-
-/* Hub port features */
-#define RH_PORT_CONNECTION	0x00
-#define RH_PORT_ENABLE		0x01
-#define RH_PORT_SUSPEND		0x02
-#define RH_PORT_OVER_CURRENT	0x03
-#define RH_PORT_RESET		0x04
-#define RH_PORT_POWER		0x08
-#define RH_PORT_LOW_SPEED	0x09
-
-#define RH_C_PORT_CONNECTION	0x10
-#define RH_C_PORT_ENABLE	0x11
-#define RH_C_PORT_SUSPEND	0x12
-#define RH_C_PORT_OVER_CURRENT	0x13
-#define RH_C_PORT_RESET		0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER	0x00
-#define RH_C_HUB_OVER_CURRENT	0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL	0x01
-
-#define RH_ACK			0x01
-#define RH_REQ_ERR		-1
-#define RH_NACK			0x00
-
-
-/* OHCI ROOT HUB REGISTER MASKS */
-
-/* roothub.portstatus [i] bits */
-#define RH_PS_CCS		0x00000001	/* current connect status */
-#define RH_PS_PES		0x00000002	/* port enable status*/
-#define RH_PS_PSS		0x00000004	/* port suspend status */
-#define RH_PS_POCI		0x00000008	/* port over current indicator */
-#define RH_PS_PRS		0x00000010	/* port reset status */
-#define RH_PS_PPS		0x00000100	/* port power status */
-#define RH_PS_LSDA		0x00000200	/* low speed device attached */
-#define RH_PS_CSC		0x00010000	/* connect status change */
-#define RH_PS_PESC		0x00020000	/* port enable status change */
-#define RH_PS_PSSC		0x00040000	/* port suspend status change */
-#define RH_PS_OCIC		0x00080000	/* over current indicator change */
-#define RH_PS_PRSC		0x00100000	/* port reset status change */
-
-/* roothub.status bits */
-#define RH_HS_LPS		0x00000001	/* local power status */
-#define RH_HS_OCI		0x00000002	/* over current indicator */
-#define RH_HS_DRWE		0x00008000	/* device remote wakeup enable */
-#define RH_HS_LPSC		0x00010000	/* local power status change */
-#define RH_HS_OCIC		0x00020000	/* over current indicator change */
-#define RH_HS_CRWE		0x80000000	/* clear remote wakeup enable */
-
-/* roothub.b masks */
-#define RH_B_DR			0x0000ffff	/* device removable flags */
-#define RH_B_PPCM		0xffff0000	/* port power control mask */
-
-/* roothub.a masks */
-#define	RH_A_NDP		(0xff << 0)	/* number of downstream ports */
-#define	RH_A_PSM		(1 << 8)	/* power switching mode */
-#define	RH_A_NPS		(1 << 9)	/* no power switching */
-#define	RH_A_DT			(1 << 10)	/* device type (mbz) */
-#define	RH_A_OCPM		(1 << 11)	/* over current protection mode */
-#define	RH_A_NOCP		(1 << 12)	/* no over current protection */
-#define	RH_A_POTPGT		(0xff << 24)	/* power on to power good time */
-
-/* urb */
-#define N_URB_TD 48
-typedef struct
-{
-	ed_t *ed;
-	__u16 length;		/* number of tds associated with this request */
-	__u16 td_cnt;		/* number of tds already serviced */
-	int   state;
-	unsigned long pipe;
-	int actual_length;
-	td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
-} urb_priv_t;
-#define URB_DEL 1
-
-/*
- * This is the full ohci controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-
-typedef struct ohci {
-	struct ohci_hcca *hcca;		/* hcca */
-	/*dma_addr_t hcca_dma;*/
-
-	int irq;
-	int disabled;			/* e.g. got a UE, we're hung */
-	int sleeping;
-	unsigned long flags;		/* for HC bugs */
-
-	struct ohci_regs *regs;		/* OHCI controller's memory */
-
-	ed_t *ed_rm_list[2];		/* lists of all endpoints to be removed */
-	ed_t *ed_bulktail;		/* last endpoint of bulk list */
-	ed_t *ed_controltail;		/* last endpoint of control list */
-	int intrstatus;
-	__u32 hc_control;		/* copy of the hc control reg */
-	struct usb_device *dev[32];
-	struct virt_root_hub rh;
-
-	const char	*slot_name;
-} ohci_t;
-
-#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
-
-struct ohci_device {
-	ed_t	ed[NUM_EDS];
-	int ed_cnt;
-};
-
-/* hcd */
-/* endpoint */
-static int ep_link(ohci_t * ohci, ed_t * ed);
-static int ep_unlink(ohci_t * ohci, ed_t * ed);
-static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
-
-/*-------------------------------------------------------------------------*/
-
-/* we need more TDs than EDs */
-#define NUM_TD 64
-
-/* +1 so we can align the storage */
-td_t gtd[NUM_TD+1];
-/* pointers to aligned storage */
-td_t *ptd;
-
-/* TDs ... */
-static inline struct td *
-td_alloc (struct usb_device *usb_dev)
-{
-	int i;
-	struct td	*td;
-
-	td = NULL;
-	for (i = 0; i < NUM_TD; i++) {
-		if (ptd[i].usb_dev == NULL) {
-			td = &ptd[i];
-			td->usb_dev = usb_dev;
-			break;
-		}
-	}
-	return td;
-}
-
-static inline void
-ed_free (struct ed *ed)
-{
-	ed->usb_dev = NULL;
-}
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/config.mk b/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/config.mk
deleted file mode 100644
index 5c89129d8..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/au1x00/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2011
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mtune=4kc
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/cache.S b/qemu/roms/u-boot/arch/mips/cpu/mips32/cache.S
deleted file mode 100644
index 22bd844ea..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/cache.S
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- *  Cache-handling routined for MIPS CPUs
- *
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/asm.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
-#ifndef CONFIG_SYS_MIPS_CACHE_MODE
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-#endif
-
-#define RA		t9
-
-#define INDEX_BASE	CKSEG0
-
-	.macro	cache_op op addr
-	.set	push
-	.set	noreorder
-	.set	mips3
-	cache	\op, 0(\addr)
-	.set	pop
-	.endm
-
-	.macro	f_fill64 dst, offset, val
-	LONG_S	\val, (\offset +  0 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  1 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  2 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  3 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  4 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  5 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  6 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  7 * LONGSIZE)(\dst)
-#if LONGSIZE == 4
-	LONG_S	\val, (\offset +  8 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  9 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 10 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 11 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 12 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 13 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 14 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 15 * LONGSIZE)(\dst)
-#endif
-	.endm
-
-/*
- * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
- */
-LEAF(mips_init_icache)
-	blez		a1, 9f
-	mtc0		zero, CP0_TAGLO
-	/* clear tag to invalidate */
-	PTR_LI		t0, INDEX_BASE
-	PTR_ADDU	t1, t0, a1
-1:	cache_op	INDEX_STORE_TAG_I t0
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 1b
-	/* fill once, so data field parity is correct */
-	PTR_LI		t0, INDEX_BASE
-2:	cache_op	FILL t0
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 2b
-	/* invalidate again - prudent but not strictly neccessary */
-	PTR_LI		t0, INDEX_BASE
-1:	cache_op	INDEX_STORE_TAG_I t0
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 1b
-9:	jr		ra
-	END(mips_init_icache)
-
-/*
- * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
- */
-LEAF(mips_init_dcache)
-	blez		a1, 9f
-	mtc0		zero, CP0_TAGLO
-	/* clear all tags */
-	PTR_LI		t0, INDEX_BASE
-	PTR_ADDU	t1, t0, a1
-1:	cache_op	INDEX_STORE_TAG_D t0
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 1b
-	/* load from each line (in cached space) */
-	PTR_LI		t0, INDEX_BASE
-2:	LONG_L		zero, 0(t0)
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 2b
-	/* clear all tags */
-	PTR_LI		t0, INDEX_BASE
-1:	cache_op	INDEX_STORE_TAG_D t0
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 1b
-9:	jr		ra
-	END(mips_init_dcache)
-
-/*
- * mips_cache_reset - low level initialisation of the primary caches
- *
- * This routine initialises the primary caches to ensure that they have good
- * parity.  It must be called by the ROM before any cached locations are used
- * to prevent the possibility of data with bad parity being written to memory.
- *
- * To initialise the instruction cache it is essential that a source of data
- * with good parity is available. This routine will initialise an area of
- * memory starting at location zero to be used as a source of parity.
- *
- * RETURNS: N/A
- *
- */
-NESTED(mips_cache_reset, 0, ra)
-	move	RA, ra
-
-#if !defined(CONFIG_SYS_ICACHE_SIZE) || !defined(CONFIG_SYS_DCACHE_SIZE) || \
-    !defined(CONFIG_SYS_CACHELINE_SIZE)
-	/* read Config1 for use below */
-	mfc0	t5, CP0_CONFIG, 1
-#endif
-
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-	li	t7, CONFIG_SYS_CACHELINE_SIZE
-	li	t8, CONFIG_SYS_CACHELINE_SIZE
-#else
-	/* Detect I-cache line size. */
-	srl	t8, t5, MIPS_CONF1_IL_SHIFT
-	andi	t8, t8, (MIPS_CONF1_IL >> MIPS_CONF1_IL_SHIFT)
-	beqz	t8, 1f
-	li	t6, 2
-	sllv	t8, t6, t8
-
-1:	/* Detect D-cache line size. */
-	srl	t7, t5, MIPS_CONF1_DL_SHIFT
-	andi	t7, t7, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
-	beqz	t7, 1f
-	li	t6, 2
-	sllv	t7, t6, t7
-1:
-#endif
-
-#ifdef CONFIG_SYS_ICACHE_SIZE
-	li	t2, CONFIG_SYS_ICACHE_SIZE
-#else
-	/* Detect I-cache size. */
-	srl	t6, t5, MIPS_CONF1_IS_SHIFT
-	andi	t6, t6, (MIPS_CONF1_IS >> MIPS_CONF1_IS_SHIFT)
-	li	t4, 32
-	xori	t2, t6, 0x7
-	beqz	t2, 1f
-	addi	t6, t6, 1
-	sllv	t4, t4, t6
-1:	/* At this point t4 == I-cache sets. */
-	mul	t2, t4, t8
-	srl	t6, t5, MIPS_CONF1_IA_SHIFT
-	andi	t6, t6, (MIPS_CONF1_IA >> MIPS_CONF1_IA_SHIFT)
-	addi	t6, t6, 1
-	/* At this point t6 == I-cache ways. */
-	mul	t2, t2, t6
-#endif
-
-#ifdef CONFIG_SYS_DCACHE_SIZE
-	li	t3, CONFIG_SYS_DCACHE_SIZE
-#else
-	/* Detect D-cache size. */
-	srl	t6, t5, MIPS_CONF1_DS_SHIFT
-	andi	t6, t6, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
-	li	t4, 32
-	xori	t3, t6, 0x7
-	beqz	t3, 1f
-	addi	t6, t6, 1
-	sllv	t4, t4, t6
-1:	/* At this point t4 == I-cache sets. */
-	mul	t3, t4, t7
-	srl	t6, t5, MIPS_CONF1_DA_SHIFT
-	andi	t6, t6, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
-	addi	t6, t6, 1
-	/* At this point t6 == I-cache ways. */
-	mul	t3, t3, t6
-#endif
-
-	/* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
-#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
-	li	v0, CONFIG_SYS_ICACHE_SIZE
-#else
-	li	v0, CONFIG_SYS_DCACHE_SIZE
-#endif
-#else
-	move	v0, t2
-	sltu	t1, t2, t3
-	movn	v0, t3, t1
-#endif
-	/*
-	 * Now clear that much memory starting from zero.
-	 */
-	PTR_LI		a0, CKSEG1
-	PTR_ADDU	a1, a0, v0
-2:	PTR_ADDIU	a0, 64
-	f_fill64	a0, -64, zero
-	bne		a0, a1, 2b
-
-	/*
-	 * The caches are probably in an indeterminate state,
-	 * so we force good parity into them by doing an
-	 * invalidate, load/fill, invalidate for each line.
-	 */
-
-	/*
-	 * Assume bottom of RAM will generate good parity for the cache.
-	 */
-
-	/*
-	 * Initialize the I-cache first,
-	 */
-	move	a1, t2
-	move	a2, t8
-	PTR_LA	v1, mips_init_icache
-	jalr	v1
-
-	/*
-	 * then initialize D-cache.
-	 */
-	move	a1, t3
-	move	a2, t7
-	PTR_LA	v1, mips_init_dcache
-	jalr	v1
-
-	jr	RA
-	END(mips_cache_reset)
-
-/*
- * dcache_status - get cache status
- *
- * RETURNS: 0 - cache disabled; 1 - cache enabled
- *
- */
-LEAF(dcache_status)
-	mfc0	t0, CP0_CONFIG
-	li	t1, CONF_CM_UNCACHED
-	andi	t0, t0, CONF_CM_CMASK
-	move	v0, zero
-	beq	t0, t1, 2f
-	li	v0, 1
-2:	jr	ra
-	END(dcache_status)
-
-/*
- * dcache_disable - disable cache
- *
- * RETURNS: N/A
- *
- */
-LEAF(dcache_disable)
-	mfc0	t0, CP0_CONFIG
-	li	t1, -8
-	and	t0, t0, t1
-	ori	t0, t0, CONF_CM_UNCACHED
-	mtc0	t0, CP0_CONFIG
-	jr	ra
-	END(dcache_disable)
-
-/*
- * dcache_enable - enable cache
- *
- * RETURNS: N/A
- *
- */
-LEAF(dcache_enable)
-	mfc0	t0, CP0_CONFIG
-	ori	t0, CONF_CM_CMASK
-	xori	t0, CONF_CM_CMASK
-	ori	t0, CONFIG_SYS_MIPS_CACHE_MODE
-	mtc0	t0, CP0_CONFIG
-	jr	ra
-	END(dcache_enable)
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/config.mk b/qemu/roms/u-boot/arch/mips/cpu/mips32/config.mk
deleted file mode 100644
index 332cd62c7..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/config.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# Default optimization level for MIPS32
-#
-# Note: Toolchains with binutils prior to v2.16
-# are no longer supported by U-Boot MIPS tree!
-#
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2
-PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS  += -m elf32btsmip
-else
-PLATFORM_LDFLAGS  += -m elf32ltsmip
-endif
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
-			       -T $(srctree)/examples/standalone/mips.lds
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/cpu.c b/qemu/roms/u-boot/arch/mips/cpu/mips32/cpu.c
deleted file mode 100644
index 278865b6f..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/cpu.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mipsregs.h>
-#include <asm/cacheops.h>
-#include <asm/reboot.h>
-
-#define cache_op(op,addr)						\
-	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noreorder				\n"	\
-	"	.set	mips3\n\t				\n"	\
-	"	cache	%0, %1					\n"	\
-	"	.set	pop					\n"	\
-	:								\
-	: "i" (op), "R" (*(unsigned char *)(addr)))
-
-void __attribute__((weak)) _machine_restart(void)
-{
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	_machine_restart();
-
-	fprintf(stderr, "*** reset failed ***\n");
-	return 0;
-}
-
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-
-static inline unsigned long icache_line_size(void)
-{
-	return CONFIG_SYS_CACHELINE_SIZE;
-}
-
-static inline unsigned long dcache_line_size(void)
-{
-	return CONFIG_SYS_CACHELINE_SIZE;
-}
-
-#else /* !CONFIG_SYS_CACHELINE_SIZE */
-
-static inline unsigned long icache_line_size(void)
-{
-	unsigned long conf1, il;
-	conf1 = read_c0_config1();
-	il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
-	if (!il)
-		return 0;
-	return 2 << il;
-}
-
-static inline unsigned long dcache_line_size(void)
-{
-	unsigned long conf1, dl;
-	conf1 = read_c0_config1();
-	dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
-	if (!dl)
-		return 0;
-	return 2 << dl;
-}
-
-#endif /* !CONFIG_SYS_CACHELINE_SIZE */
-
-void flush_cache(ulong start_addr, ulong size)
-{
-	unsigned long ilsize = icache_line_size();
-	unsigned long dlsize = dcache_line_size();
-	unsigned long addr, aend;
-
-	/* aend will be miscalculated when size is zero, so we return here */
-	if (size == 0)
-		return;
-
-	addr = start_addr & ~(dlsize - 1);
-	aend = (start_addr + size - 1) & ~(dlsize - 1);
-
-	if (ilsize == dlsize) {
-		/* flush I-cache & D-cache simultaneously */
-		while (1) {
-			cache_op(HIT_WRITEBACK_INV_D, addr);
-			cache_op(HIT_INVALIDATE_I, addr);
-			if (addr == aend)
-				break;
-			addr += dlsize;
-		}
-		return;
-	}
-
-	/* flush D-cache */
-	while (1) {
-		cache_op(HIT_WRITEBACK_INV_D, addr);
-		if (addr == aend)
-			break;
-		addr += dlsize;
-	}
-
-	/* flush I-cache */
-	addr = start_addr & ~(ilsize - 1);
-	aend = (start_addr + size - 1) & ~(ilsize - 1);
-	while (1) {
-		cache_op(HIT_INVALIDATE_I, addr);
-		if (addr == aend)
-			break;
-		addr += ilsize;
-	}
-}
-
-void flush_dcache_range(ulong start_addr, ulong stop)
-{
-	unsigned long lsize = dcache_line_size();
-	unsigned long addr = start_addr & ~(lsize - 1);
-	unsigned long aend = (stop - 1) & ~(lsize - 1);
-
-	while (1) {
-		cache_op(HIT_WRITEBACK_INV_D, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
-}
-
-void invalidate_dcache_range(ulong start_addr, ulong stop)
-{
-	unsigned long lsize = dcache_line_size();
-	unsigned long addr = start_addr & ~(lsize - 1);
-	unsigned long aend = (stop - 1) & ~(lsize - 1);
-
-	while (1) {
-		cache_op(HIT_INVALIDATE_D, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
-}
-
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
-	write_c0_entrylo0(low0);
-	write_c0_pagemask(pagemask);
-	write_c0_entrylo1(low1);
-	write_c0_entryhi(hi);
-	write_c0_index(index);
-	tlb_write_indexed();
-}
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SOC_AU1X00
-	au1x00_enet_initialize(bis);
-#endif
-	return 0;
-}
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/interrupts.c b/qemu/roms/u-boot/arch/mips/cpu/mips32/interrupts.c
deleted file mode 100644
index 275fcf569..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/interrupts.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-int interrupt_init(void)
-{
-	return 0;
-}
-
-void enable_interrupts(void)
-{
-}
-
-int disable_interrupts(void)
-{
-	return 0;
-}
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/start.S b/qemu/roms/u-boot/arch/mips/cpu/mips32/start.S
deleted file mode 100644
index 68e59b596..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/start.S
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- *  Startup Code for MIPS32 CPU-core
- *
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-
-#ifndef CONFIG_SYS_MIPS_CACHE_MODE
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-#endif
-
-	/*
-	 * For the moment disable interrupts, mark the kernel mode and
-	 * set ST0_KX so that the CPU does not spit fire when using
-	 * 64-bit addresses.
-	 */
-	.macro	setup_c0_status set clr
-	.set	push
-	mfc0	t0, CP0_STATUS
-	or	t0, ST0_CU0 | \set | 0x1f | \clr
-	xor	t0, 0x1f | \clr
-	mtc0	t0, CP0_STATUS
-	.set	noreorder
-	sll	zero, 3				# ehb
-	.set	pop
-	.endm
-
-	.set noreorder
-
-	.globl _start
-	.text
-_start:
-	/* U-boot entry point */
-	b	reset
-	 nop
-
-	.org 0x10
-#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
-	/*
-	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
-	 * access external NOR flashes. If the board boots from NOR flash the
-	 * internal BootROM does a blind read at address 0xB0000010 to read the
-	 * initial configuration for that EBU in order to access the flash
-	 * device with correct parameters. This config option is board-specific.
-	 */
-	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
-	.word 0x0
-#elif defined(CONFIG_MALTA)
-	/*
-	 * Linux expects the Board ID here.
-	 */
-	.word 0x00000420	# 0x420 (Malta Board with CoreLV)
-	.word 0x00000000
-#endif
-
-	.org 0x200
-	/* TLB refill, 32 bit task */
-1:	b	1b
-	 nop
-
-	.org 0x280
-	/* XTLB refill, 64 bit task */
-1:	b	1b
-	 nop
-
-	.org 0x300
-	/* Cache error exception */
-1:	b	1b
-	 nop
-
-	.org 0x380
-	/* General exception */
-1:	b	1b
-	 nop
-
-	.org 0x400
-	/* Catch interrupt exceptions */
-1:	b	1b
-	 nop
-
-	.org 0x480
-	/* EJTAG debug exception */
-1:	b	1b
-	 nop
-
-	.align 4
-reset:
-
-	/* Clear watch registers */
-	mtc0	zero, CP0_WATCHLO
-	mtc0	zero, CP0_WATCHHI
-
-	/* WP(Watch Pending), SW0/1 should be cleared */
-	mtc0	zero, CP0_CAUSE
-
-	setup_c0_status 0 0
-
-	/* Init Timer */
-	mtc0	zero, CP0_COUNT
-	mtc0	zero, CP0_COMPARE
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	/* CONFIG0 register */
-	li	t0, CONF_CM_UNCACHED
-	mtc0	t0, CP0_CONFIG
-#endif
-
-	/* Initialize $gp */
-	bal	1f
-	 nop
-	.word	_gp
-1:
-	lw	gp, 0(ra)
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	/* Initialize any external memory */
-	la	t9, lowlevel_init
-	jalr	t9
-	 nop
-
-	/* Initialize caches... */
-	la	t9, mips_cache_reset
-	jalr	t9
-	 nop
-
-	/* ... and enable them */
-	li	t0, CONFIG_SYS_MIPS_CACHE_MODE
-	mtc0	t0, CP0_CONFIG
-#endif
-
-	/* Set up temporary stack */
-	li	sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-
-	la	t9, board_init_f
-	jr	t9
-	 nop
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * a0 = addr_sp
- * a1 = gd
- * a2 = destination address
- */
-	.globl	relocate_code
-	.ent	relocate_code
-relocate_code:
-	move	sp, a0			# set new stack pointer
-
-	move	s0, a1			# save gd in s0
-	move	s2, a2			# save destination address in s2
-
-	li	t0, CONFIG_SYS_MONITOR_BASE
-	sub	s1, s2, t0		# s1 <-- relocation offset
-
-	la	t3, in_ram
-	lw	t2, -12(t3)		# t2 <-- __image_copy_end
-	move	t1, a2
-
-	add	gp, s1			# adjust gp
-
-	/*
-	 * t0 = source address
-	 * t1 = target address
-	 * t2 = source end address
-	 */
-1:
-	lw	t3, 0(t0)
-	sw	t3, 0(t1)
-	addu	t0, 4
-	blt	t0, t2, 1b
-	 addu	t1, 4
-
-	/* If caches were enabled, we would have to flush them here. */
-	sub	a1, t1, s2		# a1 <-- size
-	la	t9, flush_cache
-	jalr	t9
-	 move	a0, s2			# a0 <-- destination address
-
-	/* Jump to where we've relocated ourselves */
-	addi	t0, s2, in_ram - _start
-	jr	t0
-	 nop
-
-	.word	__rel_dyn_end
-	.word	__rel_dyn_start
-	.word	__image_copy_end
-	.word	_GLOBAL_OFFSET_TABLE_
-	.word	num_got_entries
-
-in_ram:
-	/*
-	 * Now we want to update GOT.
-	 *
-	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
-	 * generated by GNU ld. Skip these reserved entries from relocation.
-	 */
-	lw	t3, -4(t0)		# t3 <-- num_got_entries
-	lw	t8, -8(t0)		# t8 <-- _GLOBAL_OFFSET_TABLE_
-	add	t8, s1			# t8 now holds relocated _G_O_T_
-	addi	t8, t8, 8		# skipping first two entries
-	li	t2, 2
-1:
-	lw	t1, 0(t8)
-	beqz	t1, 2f
-	 add	t1, s1
-	sw	t1, 0(t8)
-2:
-	addi	t2, 1
-	blt	t2, t3, 1b
-	 addi	t8, 4
-
-	/* Update dynamic relocations */
-	lw	t1, -16(t0)		# t1 <-- __rel_dyn_start
-	lw	t2, -20(t0)		# t2 <-- __rel_dyn_end
-
-	b	2f			# skip first reserved entry
-	 addi	t1, 8
-
-1:
-	lw	t8, -4(t1)		# t8 <-- relocation info
-
-	li	t3, 3
-	bne	t8, t3, 2f		# skip non R_MIPS_REL32 entries
-	 nop
-
-	lw	t3, -8(t1)		# t3 <-- location to fix up in FLASH
-
-	lw	t8, 0(t3)		# t8 <-- original pointer
-	add	t8, s1			# t8 <-- adjusted pointer
-
-	add	t3, s1			# t3 <-- location to fix up in RAM
-	sw	t8, 0(t3)
-
-2:
-	blt	t1, t2, 1b
-	 addi	t1, 8			# each rel.dyn entry is 8 bytes
-
-	/*
-	 * Clear BSS
-	 *
-	 * GOT is now relocated. Thus __bss_start and __bss_end can be
-	 * accessed directly via $gp.
-	 */
-	la	t1, __bss_start		# t1 <-- __bss_start
-	la	t2, __bss_end		# t2 <-- __bss_end
-
-1:
-	sw	zero, 0(t1)
-	blt	t1, t2, 1b
-	 addi	t1, 4
-
-	move	a0, s0			# a0 <-- gd
-	la	t9, board_init_r
-	jr	t9
-	 move	a1, s2
-
-	.end	relocate_code
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips32/time.c b/qemu/roms/u-boot/arch/mips/cpu/mips32/time.c
deleted file mode 100644
index 386f45a1b..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips32/time.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mipsregs.h>
-
-static unsigned long timestamp;
-
-/* how many counter cycles in a jiffy */
-#define CYCLES_PER_JIFFY	\
-	(CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
-
-/*
- * timer without interrupts
- */
-
-int timer_init(void)
-{
-	/* Set up the timer for the first expiration. */
-	write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
-
-	return 0;
-}
-
-ulong get_timer(ulong base)
-{
-	unsigned int count;
-	unsigned int expirelo = read_c0_compare();
-
-	/* Check to see if we have missed any timestamps. */
-	count = read_c0_count();
-	while ((count - expirelo) < 0x7fffffff) {
-		expirelo += CYCLES_PER_JIFFY;
-		timestamp++;
-	}
-	write_c0_compare(expirelo);
-
-	return timestamp - base;
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned int tmo;
-
-	tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
-	while ((tmo - read_c0_count()) < 0x7fffffff)
-		/*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips64/Makefile b/qemu/roms/u-boot/arch/mips/cpu/mips64/Makefile
deleted file mode 100644
index 899c319c9..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips64/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y	= start.o
-obj-y	= cpu.o interrupts.o time.o cache.o
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips64/cache.S b/qemu/roms/u-boot/arch/mips/cpu/mips64/cache.S
deleted file mode 100644
index 36d868818..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips64/cache.S
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- *  Cache-handling routined for MIPS CPUs
- *
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/asm.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
-#define RA		t9
-
-/*
- * 16kB is the maximum size of instruction and data caches on MIPS 4K,
- * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
- *
- * Note that the above size is the maximum size of primary cache. U-Boot
- * doesn't have L2 cache support for now.
- */
-#define MIPS_MAX_CACHE_SIZE	0x10000
-
-#define INDEX_BASE	CKSEG0
-
-	.macro	cache_op op addr
-	.set	push
-	.set	noreorder
-	.set	mips3
-	cache	\op, 0(\addr)
-	.set	pop
-	.endm
-
-	.macro	f_fill64 dst, offset, val
-	LONG_S	\val, (\offset +  0 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  1 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  2 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  3 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  4 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  5 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  6 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  7 * LONGSIZE)(\dst)
-#if LONGSIZE == 4
-	LONG_S	\val, (\offset +  8 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset +  9 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 10 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 11 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 12 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 13 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 14 * LONGSIZE)(\dst)
-	LONG_S	\val, (\offset + 15 * LONGSIZE)(\dst)
-#endif
-	.endm
-
-/*
- * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
- */
-LEAF(mips_init_icache)
-	blez		a1, 9f
-	mtc0		zero, CP0_TAGLO
-	/* clear tag to invalidate */
-	PTR_LI		t0, INDEX_BASE
-	PTR_ADDU	t1, t0, a1
-1:	cache_op	INDEX_STORE_TAG_I t0
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 1b
-	/* fill once, so data field parity is correct */
-	PTR_LI		t0, INDEX_BASE
-2:	cache_op	FILL t0
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 2b
-	/* invalidate again - prudent but not strictly neccessary */
-	PTR_LI		t0, INDEX_BASE
-1:	cache_op	INDEX_STORE_TAG_I t0
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 1b
-9:	jr		ra
-	END(mips_init_icache)
-
-/*
- * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
- */
-LEAF(mips_init_dcache)
-	blez		a1, 9f
-	mtc0		zero, CP0_TAGLO
-	/* clear all tags */
-	PTR_LI		t0, INDEX_BASE
-	PTR_ADDU	t1, t0, a1
-1:	cache_op	INDEX_STORE_TAG_D t0
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 1b
-	/* load from each line (in cached space) */
-	PTR_LI		t0, INDEX_BASE
-2:	LONG_L		zero, 0(t0)
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 2b
-	/* clear all tags */
-	PTR_LI		t0, INDEX_BASE
-1:	cache_op	INDEX_STORE_TAG_D t0
-	PTR_ADDU	t0, a2
-	bne		t0, t1, 1b
-9:	jr		ra
-	END(mips_init_dcache)
-
-/*
- * mips_cache_reset - low level initialisation of the primary caches
- *
- * This routine initialises the primary caches to ensure that they have good
- * parity.  It must be called by the ROM before any cached locations are used
- * to prevent the possibility of data with bad parity being written to memory.
- *
- * To initialise the instruction cache it is essential that a source of data
- * with good parity is available. This routine will initialise an area of
- * memory starting at location zero to be used as a source of parity.
- *
- * RETURNS: N/A
- *
- */
-NESTED(mips_cache_reset, 0, ra)
-	move	RA, ra
-	li	t2, CONFIG_SYS_ICACHE_SIZE
-	li	t3, CONFIG_SYS_DCACHE_SIZE
-	li	t8, CONFIG_SYS_CACHELINE_SIZE
-
-	li	v0, MIPS_MAX_CACHE_SIZE
-
-	/*
-	 * Now clear that much memory starting from zero.
-	 */
-	PTR_LI		a0, CKSEG1
-	PTR_ADDU	a1, a0, v0
-2:	PTR_ADDIU	a0, 64
-	f_fill64	a0, -64, zero
-	bne		a0, a1, 2b
-
-	/*
-	 * The caches are probably in an indeterminate state,
-	 * so we force good parity into them by doing an
-	 * invalidate, load/fill, invalidate for each line.
-	 */
-
-	/*
-	 * Assume bottom of RAM will generate good parity for the cache.
-	 */
-
-	/*
-	 * Initialize the I-cache first,
-	 */
-	move	a1, t2
-	move	a2, t8
-	PTR_LA	v1, mips_init_icache
-	jalr	v1
-
-	/*
-	 * then initialize D-cache.
-	 */
-	move	a1, t3
-	move	a2, t8
-	PTR_LA	v1, mips_init_dcache
-	jalr	v1
-
-	jr	RA
-	END(mips_cache_reset)
-
-/*
- * dcache_status - get cache status
- *
- * RETURNS: 0 - cache disabled; 1 - cache enabled
- *
- */
-LEAF(dcache_status)
-	mfc0	t0, CP0_CONFIG
-	li	t1, CONF_CM_UNCACHED
-	andi	t0, t0, CONF_CM_CMASK
-	move	v0, zero
-	beq	t0, t1, 2f
-	li	v0, 1
-2:	jr	ra
-	END(dcache_status)
-
-/*
- * dcache_disable - disable cache
- *
- * RETURNS: N/A
- *
- */
-LEAF(dcache_disable)
-	mfc0	t0, CP0_CONFIG
-	li	t1, -8
-	and	t0, t0, t1
-	ori	t0, t0, CONF_CM_UNCACHED
-	mtc0	t0, CP0_CONFIG
-	jr	ra
-	END(dcache_disable)
-
-/*
- * dcache_enable - enable cache
- *
- * RETURNS: N/A
- *
- */
-LEAF(dcache_enable)
-	mfc0	t0, CP0_CONFIG
-	ori	t0, CONF_CM_CMASK
-	xori	t0, CONF_CM_CMASK
-	ori	t0, CONF_CM_CACHABLE_NONCOHERENT
-	mtc0	t0, CP0_CONFIG
-	jr	ra
-	END(dcache_enable)
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips64/config.mk b/qemu/roms/u-boot/arch/mips/cpu/mips64/config.mk
deleted file mode 100644
index c55eb7f2e..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips64/config.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# Default optimization level for MIPS64
-#
-# Note: Toolchains with binutils prior to v2.16
-# are no longer supported by U-Boot MIPS tree!
-#
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64
-PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS  += -m elf64btsmip
-else
-PLATFORM_LDFLAGS  += -m elf64ltsmip
-endif
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \
-			       -T $(srctree)/examples/standalone/mips64.lds
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips64/cpu.c b/qemu/roms/u-boot/arch/mips/cpu/mips64/cpu.c
deleted file mode 100644
index 9f45cfca5..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips64/cpu.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mipsregs.h>
-#include <asm/cacheops.h>
-#include <asm/reboot.h>
-
-#define cache_op(op, addr)						\
-	__asm__ __volatile__(						\
-	"	.set	push\n"						\
-	"	.set	noreorder\n"					\
-	"	.set	mips64\n"					\
-	"	cache	%0, %1\n"					\
-	"	.set	pop\n"						\
-	:								\
-	: "i" (op), "R" (*(unsigned char *)(addr)))
-
-void __attribute__((weak)) _machine_restart(void)
-{
-	fprintf(stderr, "*** reset failed ***\n");
-
-	while (1)
-		/* NOP */;
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	_machine_restart();
-
-	return 0;
-}
-
-void flush_cache(ulong start_addr, ulong size)
-{
-	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-	unsigned long addr = start_addr & ~(lsize - 1);
-	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
-
-	/* aend will be miscalculated when size is zero, so we return here */
-	if (size == 0)
-		return;
-
-	while (1) {
-		cache_op(HIT_WRITEBACK_INV_D, addr);
-		cache_op(HIT_INVALIDATE_I, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
-}
-
-void flush_dcache_range(ulong start_addr, ulong stop)
-{
-	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-	unsigned long addr = start_addr & ~(lsize - 1);
-	unsigned long aend = (stop - 1) & ~(lsize - 1);
-
-	while (1) {
-		cache_op(HIT_WRITEBACK_INV_D, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
-}
-
-void invalidate_dcache_range(ulong start_addr, ulong stop)
-{
-	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-	unsigned long addr = start_addr & ~(lsize - 1);
-	unsigned long aend = (stop - 1) & ~(lsize - 1);
-
-	while (1) {
-		cache_op(HIT_INVALIDATE_D, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
-}
-
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
-	write_c0_entrylo0(low0);
-	write_c0_pagemask(pagemask);
-	write_c0_entrylo1(low1);
-	write_c0_entryhi(hi);
-	write_c0_index(index);
-	tlb_write_indexed();
-}
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips64/interrupts.c b/qemu/roms/u-boot/arch/mips/cpu/mips64/interrupts.c
deleted file mode 100644
index 275fcf569..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips64/interrupts.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-int interrupt_init(void)
-{
-	return 0;
-}
-
-void enable_interrupts(void)
-{
-}
-
-int disable_interrupts(void)
-{
-	return 0;
-}
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips64/start.S b/qemu/roms/u-boot/arch/mips/cpu/mips64/start.S
deleted file mode 100644
index 92954e1c9..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips64/start.S
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- *  Startup Code for MIPS64 CPU-core
- *
- *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-
-#ifndef CONFIG_SYS_MIPS_CACHE_MODE
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-#endif
-
-#ifdef CONFIG_SYS_LITTLE_ENDIAN
-#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
-	(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
-#else
-#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
-	((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
-#endif
-
-	/*
-	 * For the moment disable interrupts, mark the kernel mode and
-	 * set ST0_KX so that the CPU does not spit fire when using
-	 * 64-bit addresses.
-	 */
-	.macro	setup_c0_status set clr
-	.set	push
-	mfc0	t0, CP0_STATUS
-	or	t0, ST0_CU0 | \set | 0x1f | \clr
-	xor	t0, 0x1f | \clr
-	mtc0	t0, CP0_STATUS
-	.set	noreorder
-	sll	zero, 3				# ehb
-	.set	pop
-	.endm
-
-	.set noreorder
-
-	.globl _start
-	.text
-_start:
-	/* U-boot entry point */
-	b	reset
-	 nop
-
-	.org 0x200
-	/* TLB refill, 32 bit task */
-1:	b	1b
-	 nop
-
-	.org 0x280
-	/* XTLB refill, 64 bit task */
-1:	b	1b
-	 nop
-
-	.org 0x300
-	/* Cache error exception */
-1:	b	1b
-	 nop
-
-	.org 0x380
-	/* General exception */
-1:	b	1b
-	 nop
-
-	.org 0x400
-	/* Catch interrupt exceptions */
-1:	b	1b
-	 nop
-
-	.org 0x480
-	/* EJTAG debug exception */
-1:	b	1b
-	 nop
-
-	.align 4
-reset:
-
-	/* Clear watch registers */
-	dmtc0	zero, CP0_WATCHLO
-	dmtc0	zero, CP0_WATCHHI
-
-	/* WP(Watch Pending), SW0/1 should be cleared */
-	mtc0	zero, CP0_CAUSE
-
-	setup_c0_status ST0_KX 0
-
-	/* Init Timer */
-	mtc0	zero, CP0_COUNT
-	mtc0	zero, CP0_COMPARE
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	/* CONFIG0 register */
-	dli	t0, CONF_CM_UNCACHED
-	mtc0	t0, CP0_CONFIG
-#endif
-
-	/*
-	 * Initialize $gp, force 8 byte alignment of bal instruction to forbid
-	 * the compiler to put nop's between bal and _gp. This is required to
-	 * keep _gp and ra aligned to 8 byte.
-	 */
-	.align	3
-	bal	1f
-	 nop
-	.dword	_gp
-1:
-	ld	gp, 0(ra)
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	/* Initialize any external memory */
-	dla	t9, lowlevel_init
-	jalr	t9
-	 nop
-
-	/* Initialize caches... */
-	dla	t9, mips_cache_reset
-	jalr	t9
-	 nop
-
-	/* ... and enable them */
-	dli	t0, CONFIG_SYS_MIPS_CACHE_MODE
-	mtc0	t0, CP0_CONFIG
-#endif
-
-	/* Set up temporary stack */
-	dli	sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-
-	dla	t9, board_init_f
-	jr	t9
-	 nop
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * a0 = addr_sp
- * a1 = gd
- * a2 = destination address
- */
-	.globl	relocate_code
-	.ent	relocate_code
-relocate_code:
-	move	sp, a0			# set new stack pointer
-
-	move	s0, a1			# save gd in s0
-	move	s2, a2			# save destination address in s2
-
-	dli	t0, CONFIG_SYS_MONITOR_BASE
-	dsub	s1, s2, t0		# s1 <-- relocation offset
-
-	dla	t3, in_ram
-	ld	t2, -24(t3)		# t2 <-- __image_copy_end
-	move	t1, a2
-
-	dadd	gp, s1			# adjust gp
-
-	/*
-	 * t0 = source address
-	 * t1 = target address
-	 * t2 = source end address
-	 */
-1:
-	lw	t3, 0(t0)
-	sw	t3, 0(t1)
-	daddu	t0, 4
-	blt	t0, t2, 1b
-	 daddu	t1, 4
-
-	/* If caches were enabled, we would have to flush them here. */
-	dsub	a1, t1, s2		# a1 <-- size
-	dla	t9, flush_cache
-	jalr	t9
-	 move	a0, s2			# a0 <-- destination address
-
-	/* Jump to where we've relocated ourselves */
-	daddi	t0, s2, in_ram - _start
-	jr	t0
-	 nop
-
-	.dword	__rel_dyn_end
-	.dword	__rel_dyn_start
-	.dword	__image_copy_end
-	.dword	_GLOBAL_OFFSET_TABLE_
-	.dword	num_got_entries
-
-in_ram:
-	/*
-	 * Now we want to update GOT.
-	 *
-	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
-	 * generated by GNU ld. Skip these reserved entries from relocation.
-	 */
-	ld	t3, -8(t0)		# t3 <-- num_got_entries
-	ld	t8, -16(t0)		# t8 <-- _GLOBAL_OFFSET_TABLE_
-	dadd	t8, s1			# t8 now holds relocated _G_O_T_
-	daddi	t8, t8, 16		# skipping first two entries
-	dli	t2, 2
-1:
-	ld	t1, 0(t8)
-	beqz	t1, 2f
-	 dadd	t1, s1
-	sd	t1, 0(t8)
-2:
-	daddi	t2, 1
-	blt	t2, t3, 1b
-	 daddi	t8, 8
-
-	/* Update dynamic relocations */
-	ld	t1, -32(t0)		# t1 <-- __rel_dyn_start
-	ld	t2, -40(t0)		# t2 <-- __rel_dyn_end
-
-	b	2f			# skip first reserved entry
-	 daddi	t1, 16
-
-1:
-	lw	t8, -4(t1)		# t8 <-- relocation info
-
-	dli	t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
-	bne	t8, t3, 2f		# skip non R_MIPS_REL32 entries
-	 nop
-
-	ld	t3, -16(t1)		# t3 <-- location to fix up in FLASH
-
-	ld	t8, 0(t3)		# t8 <-- original pointer
-	dadd	t8, s1			# t8 <-- adjusted pointer
-
-	dadd	t3, s1			# t3 <-- location to fix up in RAM
-	sd	t8, 0(t3)
-
-2:
-	blt	t1, t2, 1b
-	 daddi	t1, 16			# each rel.dyn entry is 16 bytes
-
-	/*
-	 * Clear BSS
-	 *
-	 * GOT is now relocated. Thus __bss_start and __bss_end can be
-	 * accessed directly via $gp.
-	 */
-	dla	t1, __bss_start		# t1 <-- __bss_start
-	dla	t2, __bss_end		# t2 <-- __bss_end
-
-1:
-	sd	zero, 0(t1)
-	blt	t1, t2, 1b
-	 daddi	t1, 8
-
-	move	a0, s0			# a0 <-- gd
-	dla	t9, board_init_r
-	jr	t9
-	 move	a1, s2
-
-	.end	relocate_code
diff --git a/qemu/roms/u-boot/arch/mips/cpu/mips64/time.c b/qemu/roms/u-boot/arch/mips/cpu/mips64/time.c
deleted file mode 100644
index 0497acf4a..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/mips64/time.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mipsregs.h>
-
-static unsigned long timestamp;
-
-/* how many counter cycles in a jiffy */
-#define CYCLES_PER_JIFFY	 \
-	(CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
-
-/*
- * timer without interrupts
- */
-
-int timer_init(void)
-{
-	/* Set up the timer for the first expiration. */
-	write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
-
-	return 0;
-}
-
-ulong get_timer(ulong base)
-{
-	unsigned int count;
-	unsigned int expirelo = read_c0_compare();
-
-	/* Check to see if we have missed any timestamps. */
-	count = read_c0_count();
-	while ((count - expirelo) < 0x7fffffff) {
-		expirelo += CYCLES_PER_JIFFY;
-		timestamp++;
-	}
-	write_c0_compare(expirelo);
-
-	return timestamp - base;
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned int tmo;
-
-	tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
-	while ((tmo - read_c0_count()) < 0x7fffffff)
-		/*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On MIPS it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On MIPS it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/qemu/roms/u-boot/arch/mips/cpu/u-boot.lds b/qemu/roms/u-boot/arch/mips/cpu/u-boot.lds
deleted file mode 100644
index e504ea754..000000000
--- a/qemu/roms/u-boot/arch/mips/cpu/u-boot.lds
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#if defined(CONFIG_64BIT)
-#define PTR_COUNT_SHIFT	3
-#else
-#define PTR_COUNT_SHIFT	2
-#endif
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text : {
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : {
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-
-	. = .;
-	_gp = ALIGN(16) + 0x7ff0;
-
-	.got : {
-		*(.got)
-	}
-
-	num_got_entries = SIZEOF(.got) >> PTR_COUNT_SHIFT;
-
-	. = ALIGN(4);
-	.sdata : {
-		*(.sdata*)
-	}
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN(4);
-	__image_copy_end = .;
-	__init_end = .;
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel.dyn)
-		__rel_dyn_end = .;
-	}
-
-	_end = .;
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.sbss.*)
-		*(.bss.*)
-		*(COMMON)
-		. = ALIGN(4);
-		__bss_end = .;
-	}
-
-	.dynsym _end : {
-		*(.dynsym)
-	}
-
-	.dynbss : {
-		*(.dynbss)
-	}
-
-	.dynstr : {
-		*(.dynstr)
-	}
-
-	.dynamic : {
-		*(.dynamic)
-	}
-
-	.plt : {
-		*(.plt)
-	}
-
-	.interp : {
-		*(.interp)
-	}
-
-	.gnu : {
-		*(.gnu*)
-	}
-
-	.MIPS.stubs : {
-		*(.MIPS.stubs)
-	}
-
-	.hash : {
-		*(.hash)
-	}
-}
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/addrspace.h b/qemu/roms/u-boot/arch/mips/include/asm/addrspace.h
deleted file mode 100644
index b768bb508..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/addrspace.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 99 Ralf Baechle
- * Copyright (C) 2000, 2002  Maciej W. Rozycki
- * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
- */
-#ifndef _ASM_ADDRSPACE_H
-#define _ASM_ADDRSPACE_H
-
-/*
- *  Configure language
- */
-#ifdef __ASSEMBLY__
-#define _ATYPE_
-#define _ATYPE32_
-#define _ATYPE64_
-#define _CONST64_(x)	x
-#else
-#define _ATYPE_		__PTRDIFF_TYPE__
-#define _ATYPE32_	int
-#define _ATYPE64_	__s64
-#ifdef CONFIG_64BIT
-#define _CONST64_(x)	x ## L
-#else
-#define _CONST64_(x)	x ## LL
-#endif
-#endif
-
-/*
- *  32-bit MIPS address spaces
- */
-#ifdef __ASSEMBLY__
-#define _ACAST32_
-#define _ACAST64_
-#else
-#define _ACAST32_		(_ATYPE_)(_ATYPE32_)	/* widen if necessary */
-#define _ACAST64_		(_ATYPE64_)		/* do _not_ narrow */
-#endif
-
-/*
- * Returns the kernel segment base of a given address
- */
-#define KSEGX(a)		((_ACAST32_ (a)) & 0xe0000000)
-
-/*
- * Returns the physical address of a CKSEGx / XKPHYS address
- */
-#define CPHYSADDR(a)		((_ACAST32_(a)) & 0x1fffffff)
-#define XPHYSADDR(a)		((_ACAST64_(a)) &			\
-				 _CONST64_(0x000000ffffffffff))
-
-#ifdef CONFIG_64BIT
-
-/*
- * Memory segments (64bit kernel mode addresses)
- * The compatibility segments use the full 64-bit sign extended value.  Note
- * the R8000 doesn't have them so don't reference these in generic MIPS code.
- */
-#define XKUSEG			_CONST64_(0x0000000000000000)
-#define XKSSEG			_CONST64_(0x4000000000000000)
-#define XKPHYS			_CONST64_(0x8000000000000000)
-#define XKSEG			_CONST64_(0xc000000000000000)
-#define CKSEG0			_CONST64_(0xffffffff80000000)
-#define CKSEG1			_CONST64_(0xffffffffa0000000)
-#define CKSSEG			_CONST64_(0xffffffffc0000000)
-#define CKSEG3			_CONST64_(0xffffffffe0000000)
-
-#define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
-#define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
-#define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
-#define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
-
-#else
-
-#define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
-#define CKSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
-#define CKSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
-#define CKSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
-
-/*
- * Map an address to a certain kernel segment
- */
-#define KSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
-#define KSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
-#define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
-#define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
-
-/*
- * Memory segments (32bit kernel mode addresses)
- * These are the traditional names used in the 32-bit universe.
- */
-#define KUSEG			0x00000000
-#define KSEG0			0x80000000
-#define KSEG1			0xa0000000
-#define KSEG2			0xc0000000
-#define KSEG3			0xe0000000
-
-#define CKUSEG			0x00000000
-#define CKSEG0			0x80000000
-#define CKSEG1			0xa0000000
-#define CKSEG2			0xc0000000
-#define CKSEG3			0xe0000000
-
-#endif
-
-/*
- * Cache modes for XKPHYS address conversion macros
- */
-#define K_CALG_COH_EXCL1_NOL2	0
-#define K_CALG_COH_SHRL1_NOL2	1
-#define K_CALG_UNCACHED		2
-#define K_CALG_NONCOHERENT	3
-#define K_CALG_COH_EXCL		4
-#define K_CALG_COH_SHAREABLE	5
-#define K_CALG_NOTUSED		6
-#define K_CALG_UNCACHED_ACCEL	7
-
-/*
- * 64-bit address conversions
- */
-#define PHYS_TO_XKSEG_UNCACHED(p)	PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
-#define PHYS_TO_XKSEG_CACHED(p)		PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
-#define XKPHYS_TO_PHYS(p)		((p) & TO_PHYS_MASK)
-#define PHYS_TO_XKPHYS(cm, a)		(_CONST64_(0x8000000000000000) | \
-					 (_CONST64_(cm) << 59) | (a))
-
-/*
- * Returns the uncached address of a sdram address
- */
-#ifndef __ASSEMBLY__
-#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
-/* We use a 36 bit physical address map here and
-   cannot access physical memory directly from core */
-#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
-#else	/* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
-#endif	/* CONFIG_SOC_AU1X00 */
-#endif	/* __ASSEMBLY__ */
-
-/*
- * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
- * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
- * R8000 implements most with its 48-bit physical address space.
- */
-#define TO_PHYS_MASK	_CONST64_(0x07ffffffffffffff)	/* 2^^59 - 1 */
-
-#ifndef CONFIG_CPU_R8000
-
-/*
- * The R8000 doesn't have the 32-bit compat spaces so we don't define them
- * in order to catch bugs in the source code.
- */
-
-#define COMPAT_K1BASE32		_CONST64_(0xffffffffa0000000)
-#define PHYS_TO_COMPATK1(x)	((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
-
-#endif
-
-#define KDM_TO_PHYS(x)		(_ACAST64_ (x) & TO_PHYS_MASK)
-#define PHYS_TO_K0(x)		(_ACAST64_ (x) | CAC_BASE)
-
-#endif /* _ASM_ADDRSPACE_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/asm.h b/qemu/roms/u-boot/arch/mips/include/asm/asm.h
deleted file mode 100644
index 933ccb1b7..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/asm.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
- * Copyright (C) 1999 by Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- * Copyright (C) 2002  Maciej W. Rozycki
- *
- * Some useful macros for MIPS assembler code
- *
- * Some of the routines below contain useless nops that will be optimized
- * away by gas in -O mode. These nops are however required to fill delay
- * slots in noreorder mode.
- */
-#ifndef __ASM_ASM_H
-#define __ASM_ASM_H
-
-#include <asm/sgidefs.h>
-
-#ifndef CAT
-#ifdef __STDC__
-#define __CAT(str1, str2) str1##str2
-#else
-#define __CAT(str1, str2) str1/**/str2
-#endif
-#define CAT(str1, str2) __CAT(str1, str2)
-#endif
-
-/*
- * PIC specific declarations
- * Not used for the kernel but here seems to be the right place.
- */
-#ifdef __PIC__
-#define CPRESTORE(register)                             \
-		.cprestore register
-#define CPADD(register)                                 \
-		.cpadd	register
-#define CPLOAD(register)                                \
-		.cpload	register
-#else
-#define CPRESTORE(register)
-#define CPADD(register)
-#define CPLOAD(register)
-#endif
-
-/*
- * LEAF - declare leaf routine
- */
-#define	LEAF(symbol)                                    \
-		.globl	symbol;                         \
-		.align	2;                              \
-		.type	symbol, @function;              \
-		.ent	symbol, 0;                      \
-symbol:		.frame	sp, 0, ra
-
-/*
- * NESTED - declare nested routine entry point
- */
-#define	NESTED(symbol, framesize, rpc)                  \
-		.globl	symbol;                         \
-		.align	2;                              \
-		.type	symbol, @function;              \
-		.ent	symbol, 0;                       \
-symbol:		.frame	sp, framesize, rpc
-
-/*
- * END - mark end of function
- */
-#define	END(function)                                   \
-		.end	function;		        \
-		.size	function, .-function
-
-/*
- * EXPORT - export definition of symbol
- */
-#define EXPORT(symbol)					\
-		.globl	symbol;                         \
-symbol:
-
-/*
- * FEXPORT - export definition of a function symbol
- */
-#define FEXPORT(symbol)					\
-		.globl	symbol;				\
-		.type	symbol, @function;		\
-symbol:
-
-/*
- * ABS - export absolute symbol
- */
-#define	ABS(symbol,value)                               \
-		.globl	symbol;                         \
-symbol		=	value
-
-#define	PANIC(msg)                                      \
-		.set	push;				\
-		.set	reorder;                        \
-		PTR_LA	a0, 8f;                          \
-		jal	panic;                          \
-9:		b	9b;                             \
-		.set	pop;				\
-		TEXT(msg)
-
-/*
- * Print formatted string
- */
-#ifdef CONFIG_PRINTK
-#define PRINT(string)                                   \
-		.set	push;				\
-		.set	reorder;                        \
-		PTR_LA	a0, 8f;                          \
-		jal	printk;                         \
-		.set	pop;				\
-		TEXT(string)
-#else
-#define PRINT(string)
-#endif
-
-#define	TEXT(msg)                                       \
-		.pushsection .data;			\
-8:		.asciiz	msg;                            \
-		.popsection;
-
-/*
- * Build text tables
- */
-#define TTABLE(string)                                  \
-		.pushsection .text;			\
-		.word	1f;                             \
-		.popsection				\
-		.pushsection .data;			\
-1:		.asciiz	string;                         \
-		.popsection
-
-/*
- * MIPS IV pref instruction.
- * Use with .set noreorder only!
- *
- * MIPS IV implementations are free to treat this as a nop.  The R5000
- * is one of them.  So we should have an option not to use this instruction.
- */
-#ifdef CONFIG_CPU_HAS_PREFETCH
-
-#define PREF(hint,addr)                                 \
-		.set	push;				\
-		.set	mips4;				\
-		pref	hint, addr;			\
-		.set	pop
-
-#define PREFX(hint,addr)                                \
-		.set	push;				\
-		.set	mips4;				\
-		prefx	hint, addr;			\
-		.set	pop
-
-#else /* !CONFIG_CPU_HAS_PREFETCH */
-
-#define PREF(hint, addr)
-#define PREFX(hint, addr)
-
-#endif /* !CONFIG_CPU_HAS_PREFETCH */
-
-/*
- * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
- */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
-#define MOVN(rd, rs, rt)                                \
-		.set	push;				\
-		.set	reorder;			\
-		beqz	rt, 9f;                         \
-		move	rd, rs;                         \
-		.set	pop;				\
-9:
-#define MOVZ(rd, rs, rt)                                \
-		.set	push;				\
-		.set	reorder;			\
-		bnez	rt, 9f;                         \
-		move	rd, rs;                         \
-		.set	pop;				\
-9:
-#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
-#define MOVN(rd, rs, rt)                                \
-		.set	push;				\
-		.set	noreorder;			\
-		bnezl	rt, 9f;                         \
-		 move	rd, rs;                         \
-		.set	pop;				\
-9:
-#define MOVZ(rd, rs, rt)                                \
-		.set	push;				\
-		.set	noreorder;			\
-		beqzl	rt, 9f;                         \
-		 move	rd, rs;                         \
-		.set	pop;				\
-9:
-#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-#define MOVN(rd, rs, rt)                                \
-		movn	rd, rs, rt
-#define MOVZ(rd, rs, rt)                                \
-		movz	rd, rs, rt
-#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
-
-/*
- * Stack alignment
- */
-#if (_MIPS_SIM == _MIPS_SIM_ABI32)
-#define ALSZ	7
-#define ALMASK	~7
-#endif
-#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-#define ALSZ	15
-#define ALMASK	~15
-#endif
-
-/*
- * Macros to handle different pointer/register sizes for 32/64-bit code
- */
-
-/*
- * Size of a register
- */
-#ifdef __mips64
-#define SZREG	8
-#else
-#define SZREG	4
-#endif
-
-/*
- * Use the following macros in assemblercode to load/store registers,
- * pointers etc.
- */
-#if (_MIPS_SIM == _MIPS_SIM_ABI32)
-#define REG_S		sw
-#define REG_L		lw
-#define REG_SUBU	subu
-#define REG_ADDU	addu
-#endif
-#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-#define REG_S		sd
-#define REG_L		ld
-#define REG_SUBU	dsubu
-#define REG_ADDU	daddu
-#endif
-
-/*
- * How to add/sub/load/store/shift C int variables.
- */
-#if (_MIPS_SZINT == 32)
-#define INT_ADD		add
-#define INT_ADDU	addu
-#define INT_ADDI	addi
-#define INT_ADDIU	addiu
-#define INT_SUB		sub
-#define INT_SUBU	subu
-#define INT_L		lw
-#define INT_S		sw
-#define INT_SLL		sll
-#define INT_SLLV	sllv
-#define INT_SRL		srl
-#define INT_SRLV	srlv
-#define INT_SRA		sra
-#define INT_SRAV	srav
-#endif
-
-#if (_MIPS_SZINT == 64)
-#define INT_ADD		dadd
-#define INT_ADDU	daddu
-#define INT_ADDI	daddi
-#define INT_ADDIU	daddiu
-#define INT_SUB		dsub
-#define INT_SUBU	dsubu
-#define INT_L		ld
-#define INT_S		sd
-#define INT_SLL		dsll
-#define INT_SLLV	dsllv
-#define INT_SRL		dsrl
-#define INT_SRLV	dsrlv
-#define INT_SRA		dsra
-#define INT_SRAV	dsrav
-#endif
-
-/*
- * How to add/sub/load/store/shift C long variables.
- */
-#if (_MIPS_SZLONG == 32)
-#define LONG_ADD	add
-#define LONG_ADDU	addu
-#define LONG_ADDI	addi
-#define LONG_ADDIU	addiu
-#define LONG_SUB	sub
-#define LONG_SUBU	subu
-#define LONG_L		lw
-#define LONG_S		sw
-#define LONG_SLL	sll
-#define LONG_SLLV	sllv
-#define LONG_SRL	srl
-#define LONG_SRLV	srlv
-#define LONG_SRA	sra
-#define LONG_SRAV	srav
-
-#define LONG		.word
-#define LONGSIZE	4
-#define LONGMASK	3
-#define LONGLOG		2
-#endif
-
-#if (_MIPS_SZLONG == 64)
-#define LONG_ADD	dadd
-#define LONG_ADDU	daddu
-#define LONG_ADDI	daddi
-#define LONG_ADDIU	daddiu
-#define LONG_SUB	dsub
-#define LONG_SUBU	dsubu
-#define LONG_L		ld
-#define LONG_S		sd
-#define LONG_SLL	dsll
-#define LONG_SLLV	dsllv
-#define LONG_SRL	dsrl
-#define LONG_SRLV	dsrlv
-#define LONG_SRA	dsra
-#define LONG_SRAV	dsrav
-
-#define LONG		.dword
-#define LONGSIZE	8
-#define LONGMASK	7
-#define LONGLOG		3
-#endif
-
-/*
- * How to add/sub/load/store/shift pointers.
- */
-#if (_MIPS_SZPTR == 32)
-#define PTR_ADD		add
-#define PTR_ADDU	addu
-#define PTR_ADDI	addi
-#define PTR_ADDIU	addiu
-#define PTR_SUB		sub
-#define PTR_SUBU	subu
-#define PTR_L		lw
-#define PTR_S		sw
-#define PTR_LA		la
-#define PTR_LI		li
-#define PTR_SLL		sll
-#define PTR_SLLV	sllv
-#define PTR_SRL		srl
-#define PTR_SRLV	srlv
-#define PTR_SRA		sra
-#define PTR_SRAV	srav
-
-#define PTR_SCALESHIFT	2
-
-#define PTR		.word
-#define PTRSIZE		4
-#define PTRLOG		2
-#endif
-
-#if (_MIPS_SZPTR == 64)
-#define PTR_ADD		dadd
-#define PTR_ADDU	daddu
-#define PTR_ADDI	daddi
-#define PTR_ADDIU	daddiu
-#define PTR_SUB		dsub
-#define PTR_SUBU	dsubu
-#define PTR_L		ld
-#define PTR_S		sd
-#define PTR_LA		dla
-#define PTR_LI		dli
-#define PTR_SLL		dsll
-#define PTR_SLLV	dsllv
-#define PTR_SRL		dsrl
-#define PTR_SRLV	dsrlv
-#define PTR_SRA		dsra
-#define PTR_SRAV	dsrav
-
-#define PTR_SCALESHIFT	3
-
-#define PTR		.dword
-#define PTRSIZE		8
-#define PTRLOG		3
-#endif
-
-/*
- * Some cp0 registers were extended to 64bit for MIPS III.
- */
-#if (_MIPS_SIM == _MIPS_SIM_ABI32)
-#define MFC0		mfc0
-#define MTC0		mtc0
-#endif
-#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-#define MFC0		dmfc0
-#define MTC0		dmtc0
-#endif
-
-#define SSNOP		sll zero, zero, 1
-
-#ifdef CONFIG_SGI_IP28
-/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
-#include <asm/cacheops.h>
-#define R10KCBARRIER(addr)  cache   CACHE_BARRIER, addr;
-#else
-#define R10KCBARRIER(addr)
-#endif
-
-#endif /* __ASM_ASM_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/au1x00.h b/qemu/roms/u-boot/arch/mips/include/asm/au1x00.h
deleted file mode 100644
index f76c4c316..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/au1x00.h
+++ /dev/null
@@ -1,1072 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *	Include file for Alchemy Semiconductor's Au1k CPU.
- *
- * Copyright 2000,2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *	   ppopov@mvista.com or source@mvista.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
- /*
-  * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
-  */
-
-#ifndef _AU1X00_H_
-#define _AU1X00_H_
-
-#ifndef __ASSEMBLY__
-/* cpu pipeline flush */
-void static inline au_sync(void)
-{
-	__asm__ volatile ("sync");
-}
-
-void static inline au_sync_udelay(int us)
-{
-	__asm__ volatile ("sync");
-	udelay(us);
-}
-
-void static inline au_writeb(u8 val, int reg)
-{
-	*(volatile u8 *)(reg) = val;
-}
-
-void static inline au_writew(u16 val, int reg)
-{
-	*(volatile u16 *)(reg) = val;
-}
-
-void static inline au_writel(u32 val, int reg)
-{
-	*(volatile u32 *)(reg) = val;
-}
-
-static inline u8 au_readb(unsigned long port)
-{
-	return (*(volatile u8 *)port);
-}
-
-static inline u16 au_readw(unsigned long port)
-{
-	return (*(volatile u16 *)port);
-}
-
-static inline u32 au_readl(unsigned long port)
-{
-	return (*(volatile u32 *)port);
-}
-
-/* These next three functions should be a generic part of the MIPS
- * kernel (with the 'au_' removed from the name) and selected for
- * processors that support the instructions.
- * Taken from PPC tree.  -- Dan
- */
-/* Return the bit position of the most significant 1 bit in a word */
-static __inline__ int __ilog2(unsigned int x)
-{
-	int lz;
-
-	asm volatile (
-		".set\tnoreorder\n\t"
-		".set\tnoat\n\t"
-		".set\tmips32\n\t"
-		"clz\t%0,%1\n\t"
-		".set\tmips0\n\t"
-		".set\tat\n\t"
-		".set\treorder"
-		: "=r" (lz)
-		: "r" (x));
-
-	return 31 - lz;
-}
-
-static __inline__ int au_ffz(unsigned int x)
-{
-	if ((x = ~x) == 0)
-		return 32;
-	return __ilog2(x & -x);
-}
-
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static __inline__ int au_ffs(int x)
-{
-	return __ilog2(x & -x) + 1;
-}
-
-#define gpio_set(Value)      outl(Value, SYS_OUTPUTSET)
-#define gpio_clear(Value)    outl(Value, SYS_OUTPUTCLR)
-#define gpio_read()          inl(SYS_PINSTATERD)
-#define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR)
-
-#endif /* !ASSEMBLY */
-
-#ifdef CONFIG_PM
-/* no CP0 timer irq */
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
-#else
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
-#endif
-
-#define CP0_IWATCHLO		$18,1
-#define CP0_DEBUG		$23
-
-/* SDRAM Controller */
-#ifdef CONFIG_SOC_AU1550
-
-#define MEM_SDMODE0                0xB4000800
-#define MEM_SDMODE1                0xB4000808
-#define MEM_SDMODE2                0xB4000810
-
-#define MEM_SDADDR0                0xB4000820
-#define MEM_SDADDR1                0xB4000828
-#define MEM_SDADDR2                0xB4000830
-
-#define MEM_SDCONFIGA              0xB4000840
-#define MEM_SDCONFIGB              0xB4000848
-#define MEM_SDPRECMD               0xB40008c0
-#define MEM_SDAUTOREF              0xB40008c8
-
-#define MEM_SDWRMD0                0xB4000880
-#define MEM_SDWRMD1                0xB4000888
-#define MEM_SDWRMD2                0xB4000890
-
-#else /* CONFIG_SOC_AU1550 */
-
-#define MEM_SDMODE0                0xB4000000
-#define MEM_SDMODE1                0xB4000004
-#define MEM_SDMODE2                0xB4000008
-
-#define MEM_SDADDR0                0xB400000C
-#define MEM_SDADDR1                0xB4000010
-#define MEM_SDADDR2                0xB4000014
-
-#define MEM_SDREFCFG               0xB4000018
-#define MEM_SDPRECMD               0xB400001C
-#define MEM_SDAUTOREF              0xB4000020
-
-#define MEM_SDWRMD0                0xB4000024
-#define MEM_SDWRMD1                0xB4000028
-#define MEM_SDWRMD2                0xB400002C
-
-#endif /* CONFIG_SOC_AU1550 */
-
-#define MEM_SDSLEEP                0xB4000030
-#define MEM_SDSMCKE                0xB4000034
-
-/* Static Bus Controller */
-#define MEM_STCFG0                 0xB4001000
-#define MEM_STTIME0                0xB4001004
-#define MEM_STADDR0                0xB4001008
-
-#define MEM_STCFG1                 0xB4001010
-#define MEM_STTIME1                0xB4001014
-#define MEM_STADDR1                0xB4001018
-
-#define MEM_STCFG2                 0xB4001020
-#define MEM_STTIME2                0xB4001024
-#define MEM_STADDR2                0xB4001028
-
-#define MEM_STCFG3                 0xB4001030
-#define MEM_STTIME3                0xB4001034
-#define MEM_STADDR3                0xB4001038
-
-/* Interrupt Controller 0 */
-#define IC0_CFG0RD                 0xB0400040
-#define IC0_CFG0SET                0xB0400040
-#define IC0_CFG0CLR                0xB0400044
-
-#define IC0_CFG1RD                 0xB0400048
-#define IC0_CFG1SET                0xB0400048
-#define IC0_CFG1CLR                0xB040004C
-
-#define IC0_CFG2RD                 0xB0400050
-#define IC0_CFG2SET                0xB0400050
-#define IC0_CFG2CLR                0xB0400054
-
-#define IC0_REQ0INT                0xB0400054
-#define IC0_SRCRD                  0xB0400058
-#define IC0_SRCSET                 0xB0400058
-#define IC0_SRCCLR                 0xB040005C
-#define IC0_REQ1INT                0xB040005C
-
-#define IC0_ASSIGNRD               0xB0400060
-#define IC0_ASSIGNSET              0xB0400060
-#define IC0_ASSIGNCLR              0xB0400064
-
-#define IC0_WAKERD                 0xB0400068
-#define IC0_WAKESET                0xB0400068
-#define IC0_WAKECLR                0xB040006C
-
-#define IC0_MASKRD                 0xB0400070
-#define IC0_MASKSET                0xB0400070
-#define IC0_MASKCLR                0xB0400074
-
-#define IC0_RISINGRD               0xB0400078
-#define IC0_RISINGCLR              0xB0400078
-#define IC0_FALLINGRD              0xB040007C
-#define IC0_FALLINGCLR             0xB040007C
-
-#define IC0_TESTBIT                0xB0400080
-
-/* Interrupt Controller 1 */
-#define IC1_CFG0RD                 0xB1800040
-#define IC1_CFG0SET                0xB1800040
-#define IC1_CFG0CLR                0xB1800044
-
-#define IC1_CFG1RD                 0xB1800048
-#define IC1_CFG1SET                0xB1800048
-#define IC1_CFG1CLR                0xB180004C
-
-#define IC1_CFG2RD                 0xB1800050
-#define IC1_CFG2SET                0xB1800050
-#define IC1_CFG2CLR                0xB1800054
-
-#define IC1_REQ0INT                0xB1800054
-#define IC1_SRCRD                  0xB1800058
-#define IC1_SRCSET                 0xB1800058
-#define IC1_SRCCLR                 0xB180005C
-#define IC1_REQ1INT                0xB180005C
-
-#define IC1_ASSIGNRD               0xB1800060
-#define IC1_ASSIGNSET              0xB1800060
-#define IC1_ASSIGNCLR              0xB1800064
-
-#define IC1_WAKERD                 0xB1800068
-#define IC1_WAKESET                0xB1800068
-#define IC1_WAKECLR                0xB180006C
-
-#define IC1_MASKRD                 0xB1800070
-#define IC1_MASKSET                0xB1800070
-#define IC1_MASKCLR                0xB1800074
-
-#define IC1_RISINGRD               0xB1800078
-#define IC1_RISINGCLR              0xB1800078
-#define IC1_FALLINGRD              0xB180007C
-#define IC1_FALLINGCLR             0xB180007C
-
-#define IC1_TESTBIT                0xB1800080
-
-/* Interrupt Configuration Modes */
-#define INTC_INT_DISABLED                0
-#define INTC_INT_RISE_EDGE             0x1
-#define INTC_INT_FALL_EDGE             0x2
-#define INTC_INT_RISE_AND_FALL_EDGE    0x3
-#define INTC_INT_HIGH_LEVEL            0x5
-#define INTC_INT_LOW_LEVEL             0x6
-#define INTC_INT_HIGH_AND_LOW_LEVEL    0x7
-
-/* Interrupt Numbers */
-#define AU1X00_UART0_INT          0
-#define AU1000_UART1_INT          1 /* au1000 */
-#define AU1000_UART2_INT          2 /* au1000 */
-
-#define AU1500_PCI_INTA           1 /* au1500 */
-#define AU1500_PCI_INTB           2 /* au1500 */
-
-#define AU1X00_UART3_INT          3
-
-#define AU1000_SSI0_INT           4 /* au1000 */
-#define AU1000_SSI1_INT           5 /* au1000 */
-
-#define AU1500_PCI_INTC           4 /* au1500 */
-#define AU1500_PCI_INTD           5 /* au1500 */
-
-#define AU1X00_DMA_INT_BASE       6
-#define AU1X00_TOY_INT            14
-#define AU1X00_TOY_MATCH0_INT     15
-#define AU1X00_TOY_MATCH1_INT     16
-#define AU1X00_TOY_MATCH2_INT     17
-#define AU1X00_RTC_INT            18
-#define AU1X00_RTC_MATCH0_INT     19
-#define AU1X00_RTC_MATCH1_INT     20
-#define AU1X00_RTC_MATCH2_INT     21
-#define AU1000_IRDA_TX_INT        22 /* au1000 */
-#define AU1000_IRDA_RX_INT        23 /* au1000 */
-#define AU1X00_USB_DEV_REQ_INT    24
-#define AU1X00_USB_DEV_SUS_INT    25
-#define AU1X00_USB_HOST_INT       26
-#define AU1X00_ACSYNC_INT         27
-#define AU1X00_MAC0_DMA_INT       28
-#define AU1X00_MAC1_DMA_INT       29
-#define AU1X00_ETH0_IRQ           AU1X00_MAC0_DMA_INT
-#define AU1X00_ETH1_IRQ           AU1X00_MAC1_DMA_INT
-#define AU1000_I2S_UO_INT         30 /* au1000 */
-#define AU1X00_AC97C_INT          31
-#define AU1X00_LAST_INTC0_INT     AU1X00_AC97C_INT
-#define AU1X00_GPIO_0             32
-#define AU1X00_GPIO_1             33
-#define AU1X00_GPIO_2             34
-#define AU1X00_GPIO_3             35
-#define AU1X00_GPIO_4             36
-#define AU1X00_GPIO_5             37
-#define AU1X00_GPIO_6             38
-#define AU1X00_GPIO_7             39
-#define AU1X00_GPIO_8             40
-#define AU1X00_GPIO_9             41
-#define AU1X00_GPIO_10            42
-#define AU1X00_GPIO_11            43
-#define AU1X00_GPIO_12            44
-#define AU1X00_GPIO_13            45
-#define AU1X00_GPIO_14            46
-#define AU1X00_GPIO_15            47
-
-/* Au1000 only */
-#define AU1000_GPIO_16            48
-#define AU1000_GPIO_17            49
-#define AU1000_GPIO_18            50
-#define AU1000_GPIO_19            51
-#define AU1000_GPIO_20            52
-#define AU1000_GPIO_21            53
-#define AU1000_GPIO_22            54
-#define AU1000_GPIO_23            55
-#define AU1000_GPIO_24            56
-#define AU1000_GPIO_25            57
-#define AU1000_GPIO_26            58
-#define AU1000_GPIO_27            59
-#define AU1000_GPIO_28            60
-#define AU1000_GPIO_29            61
-#define AU1000_GPIO_30            62
-#define AU1000_GPIO_31            63
-
-/* Au1500 only */
-#define AU1500_GPIO_200           48
-#define AU1500_GPIO_201           49
-#define AU1500_GPIO_202           50
-#define AU1500_GPIO_203           51
-#define AU1500_GPIO_20            52
-#define AU1500_GPIO_204           53
-#define AU1500_GPIO_205           54
-#define AU1500_GPIO_23            55
-#define AU1500_GPIO_24            56
-#define AU1500_GPIO_25            57
-#define AU1500_GPIO_26            58
-#define AU1500_GPIO_27            59
-#define AU1500_GPIO_28            60
-#define AU1500_GPIO_206           61
-#define AU1500_GPIO_207           62
-#define AU1500_GPIO_208_215       63
-
-#define AU1X00_MAX_INTR           63
-
-#define AU1100_SD		2
-#define	AU1100_GPIO_208_215	29
-/* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */
-
-/* Programmable Counters 0 and 1 */
-#define SYS_BASE                   0xB1900000
-#define SYS_COUNTER_CNTRL          (SYS_BASE + 0x14)
-#define SYS_CNTRL_E1S            (1<<23)
-#define SYS_CNTRL_T1S            (1<<20)
-#define SYS_CNTRL_M21            (1<<19)
-#define SYS_CNTRL_M11            (1<<18)
-#define SYS_CNTRL_M01            (1<<17)
-#define SYS_CNTRL_C1S            (1<<16)
-#define SYS_CNTRL_BP             (1<<14)
-#define SYS_CNTRL_EN1            (1<<13)
-#define SYS_CNTRL_BT1            (1<<12)
-#define SYS_CNTRL_EN0            (1<<11)
-#define SYS_CNTRL_BT0            (1<<10)
-#define SYS_CNTRL_E0             (1<<8)
-#define SYS_CNTRL_E0S            (1<<7)
-#define SYS_CNTRL_32S            (1<<5)
-#define SYS_CNTRL_T0S            (1<<4)
-#define SYS_CNTRL_M20            (1<<3)
-#define SYS_CNTRL_M10            (1<<2)
-#define SYS_CNTRL_M00            (1<<1)
-#define SYS_CNTRL_C0S            (1<<0)
-
-/* Programmable Counter 0 Registers */
-#define SYS_TOYTRIM                 (SYS_BASE + 0)
-#define SYS_TOYWRITE                (SYS_BASE + 4)
-#define SYS_TOYMATCH0               (SYS_BASE + 8)
-#define SYS_TOYMATCH1               (SYS_BASE + 0xC)
-#define SYS_TOYMATCH2               (SYS_BASE + 0x10)
-#define SYS_TOYREAD                 (SYS_BASE + 0x40)
-
-/* Programmable Counter 1 Registers */
-#define SYS_RTCTRIM                 (SYS_BASE + 0x44)
-#define SYS_RTCWRITE                (SYS_BASE + 0x48)
-#define SYS_RTCMATCH0               (SYS_BASE + 0x4C)
-#define SYS_RTCMATCH1               (SYS_BASE + 0x50)
-#define SYS_RTCMATCH2               (SYS_BASE + 0x54)
-#define SYS_RTCREAD                 (SYS_BASE + 0x58)
-
-/* I2S Controller */
-#define I2S_DATA                    0xB1000000
-#define I2S_DATA_MASK        (0xffffff)
-#define I2S_CONFIG                0xB1000004
-#define I2S_CONFIG_XU        (1<<25)
-#define I2S_CONFIG_XO        (1<<24)
-#define I2S_CONFIG_RU        (1<<23)
-#define I2S_CONFIG_RO        (1<<22)
-#define I2S_CONFIG_TR        (1<<21)
-#define I2S_CONFIG_TE        (1<<20)
-#define I2S_CONFIG_TF        (1<<19)
-#define I2S_CONFIG_RR        (1<<18)
-#define I2S_CONFIG_RE        (1<<17)
-#define I2S_CONFIG_RF        (1<<16)
-#define I2S_CONFIG_PD        (1<<11)
-#define I2S_CONFIG_LB        (1<<10)
-#define I2S_CONFIG_IC        (1<<9)
-#define I2S_CONFIG_FM_BIT    7
-#define I2S_CONFIG_FM_MASK     (0x3 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_FM_I2S    (0x0 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_FM_LJ     (0x1 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_FM_RJ     (0x2 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_TN        (1<<6)
-#define I2S_CONFIG_RN        (1<<5)
-#define I2S_CONFIG_SZ_BIT    0
-#define I2S_CONFIG_SZ_MASK     (0x1F << I2S_CONFIG_SZ_BIT)
-
-#define I2S_CONTROL                0xB1000008
-#define I2S_CONTROL_D         (1<<1)
-#define I2S_CONTROL_CE        (1<<0)
-
-/* USB Host Controller */
-/* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */
-#define USB_OHCI_BASE             0x10100000
-#define USB_OHCI_LEN              0x00100000
-#define USB_HOST_CONFIG           0xB017fffc
-
-/* USB Device Controller */
-#define USBD_EP0RD                0xB0200000
-#define USBD_EP0WR                0xB0200004
-#define USBD_EP2WR                0xB0200008
-#define USBD_EP3WR                0xB020000C
-#define USBD_EP4RD                0xB0200010
-#define USBD_EP5RD                0xB0200014
-#define USBD_INTEN                0xB0200018
-#define USBD_INTSTAT              0xB020001C
-#define USBDEV_INT_SOF       (1<<12)
-#define USBDEV_INT_HF_BIT    6
-#define USBDEV_INT_HF_MASK   (0x3f << USBDEV_INT_HF_BIT)
-#define USBDEV_INT_CMPLT_BIT  0
-#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
-#define USBD_CONFIG               0xB0200020
-#define USBD_EP0CS                0xB0200024
-#define USBD_EP2CS                0xB0200028
-#define USBD_EP3CS                0xB020002C
-#define USBD_EP4CS                0xB0200030
-#define USBD_EP5CS                0xB0200034
-#define USBDEV_CS_SU         (1<<14)
-#define USBDEV_CS_NAK        (1<<13)
-#define USBDEV_CS_ACK        (1<<12)
-#define USBDEV_CS_BUSY       (1<<11)
-#define USBDEV_CS_TSIZE_BIT  1
-#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
-#define USBDEV_CS_STALL      (1<<0)
-#define USBD_EP0RDSTAT            0xB0200040
-#define USBD_EP0WRSTAT            0xB0200044
-#define USBD_EP2WRSTAT            0xB0200048
-#define USBD_EP3WRSTAT            0xB020004C
-#define USBD_EP4RDSTAT            0xB0200050
-#define USBD_EP5RDSTAT            0xB0200054
-#define USBDEV_FSTAT_FLUSH     (1<<6)
-#define USBDEV_FSTAT_UF        (1<<5)
-#define USBDEV_FSTAT_OF        (1<<4)
-#define USBDEV_FSTAT_FCNT_BIT  0
-#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
-#define USBD_ENABLE               0xB0200058
-#define USBDEV_ENABLE (1<<1)
-#define USBDEV_CE     (1<<0)
-
-/* Ethernet Controllers  */
-#define AU1000_ETH0_BASE          0xB0500000
-#define AU1000_ETH1_BASE          0xB0510000
-#define AU1500_ETH0_BASE	  0xB1500000
-#define AU1500_ETH1_BASE	  0xB1510000
-#define AU1100_ETH0_BASE	  0xB0500000
-#define AU1550_ETH0_BASE	  0xB0500000
-#define AU1550_ETH1_BASE	  0xB0510000
-
-/* 4 byte offsets from AU1000_ETH_BASE */
-#define MAC_CONTROL                     0x0
-#define MAC_RX_ENABLE               (1<<2)
-#define MAC_TX_ENABLE               (1<<3)
-#define MAC_DEF_CHECK               (1<<5)
-#define MAC_SET_BL(X)       (((X)&0x3)<<6)
-#define MAC_AUTO_PAD                (1<<8)
-#define MAC_DISABLE_RETRY          (1<<10)
-#define MAC_DISABLE_BCAST          (1<<11)
-#define MAC_LATE_COL               (1<<12)
-#define MAC_HASH_MODE              (1<<13)
-#define MAC_HASH_ONLY              (1<<15)
-#define MAC_PASS_ALL               (1<<16)
-#define MAC_INVERSE_FILTER         (1<<17)
-#define MAC_PROMISCUOUS            (1<<18)
-#define MAC_PASS_ALL_MULTI         (1<<19)
-#define MAC_FULL_DUPLEX            (1<<20)
-#define MAC_NORMAL_MODE                 0
-#define MAC_INT_LOOPBACK           (1<<21)
-#define MAC_EXT_LOOPBACK           (1<<22)
-#define MAC_DISABLE_RX_OWN         (1<<23)
-#define MAC_BIG_ENDIAN             (1<<30)
-#define MAC_RX_ALL                 (1<<31)
-#define MAC_ADDRESS_HIGH                0x4
-#define MAC_ADDRESS_LOW                 0x8
-#define MAC_MCAST_HIGH                  0xC
-#define MAC_MCAST_LOW                  0x10
-#define MAC_MII_CNTRL                  0x14
-#define MAC_MII_BUSY                (1<<0)
-#define MAC_MII_READ                     0
-#define MAC_MII_WRITE               (1<<1)
-#define MAC_SET_MII_SELECT_REG(X)   (((X)&0x1f)<<6)
-#define MAC_SET_MII_SELECT_PHY(X)   (((X)&0x1f)<<11)
-#define MAC_MII_DATA                   0x18
-#define MAC_FLOW_CNTRL                 0x1C
-#define MAC_FLOW_CNTRL_BUSY         (1<<0)
-#define MAC_FLOW_CNTRL_ENABLE       (1<<1)
-#define MAC_PASS_CONTROL            (1<<2)
-#define MAC_SET_PAUSE(X)        (((X)&0xffff)<<16)
-#define MAC_VLAN1_TAG                  0x20
-#define MAC_VLAN2_TAG                  0x24
-
-/* Ethernet Controller Enable */
-#define AU1000_MAC0_ENABLE       0xB0520000
-#define AU1000_MAC1_ENABLE       0xB0520004
-#define AU1500_MAC0_ENABLE       0xB1520000
-#define AU1500_MAC1_ENABLE       0xB1520004
-#define AU1100_MAC0_ENABLE       0xB0520000
-#define AU1550_MAC0_ENABLE       0xB0520000
-#define AU1550_MAC1_ENABLE       0xB0520004
-
-#define MAC_EN_CLOCK_ENABLE         (1<<0)
-#define MAC_EN_RESET0               (1<<1)
-#define MAC_EN_TOSS                 (0<<2)
-#define MAC_EN_CACHEABLE            (1<<3)
-#define MAC_EN_RESET1               (1<<4)
-#define MAC_EN_RESET2               (1<<5)
-#define MAC_DMA_RESET               (1<<6)
-
-/* Ethernet Controller DMA Channels */
-
-#define MAC0_TX_DMA_ADDR         0xB4004000
-#define MAC1_TX_DMA_ADDR         0xB4004200
-/* offsets from MAC_TX_RING_ADDR address */
-#define MAC_TX_BUFF0_STATUS             0x0
-#define TX_FRAME_ABORTED            (1<<0)
-#define TX_JAB_TIMEOUT              (1<<1)
-#define TX_NO_CARRIER               (1<<2)
-#define TX_LOSS_CARRIER             (1<<3)
-#define TX_EXC_DEF                  (1<<4)
-#define TX_LATE_COLL_ABORT          (1<<5)
-#define TX_EXC_COLL                 (1<<6)
-#define TX_UNDERRUN                 (1<<7)
-#define TX_DEFERRED                 (1<<8)
-#define TX_LATE_COLL                (1<<9)
-#define TX_COLL_CNT_MASK         (0xF<<10)
-#define TX_PKT_RETRY               (1<<31)
-#define MAC_TX_BUFF0_ADDR                0x4
-#define TX_DMA_ENABLE               (1<<0)
-#define TX_T_DONE                   (1<<1)
-#define TX_GET_DMA_BUFFER(X)    (((X)>>2)&0x3)
-#define MAC_TX_BUFF0_LEN                 0x8
-#define MAC_TX_BUFF1_STATUS             0x10
-#define MAC_TX_BUFF1_ADDR               0x14
-#define MAC_TX_BUFF1_LEN                0x18
-#define MAC_TX_BUFF2_STATUS             0x20
-#define MAC_TX_BUFF2_ADDR               0x24
-#define MAC_TX_BUFF2_LEN                0x28
-#define MAC_TX_BUFF3_STATUS             0x30
-#define MAC_TX_BUFF3_ADDR               0x34
-#define MAC_TX_BUFF3_LEN                0x38
-
-#define MAC0_RX_DMA_ADDR         0xB4004100
-#define MAC1_RX_DMA_ADDR         0xB4004300
-/* offsets from MAC_RX_RING_ADDR */
-#define MAC_RX_BUFF0_STATUS              0x0
-#define RX_FRAME_LEN_MASK           0x3fff
-#define RX_WDOG_TIMER              (1<<14)
-#define RX_RUNT                    (1<<15)
-#define RX_OVERLEN                 (1<<16)
-#define RX_COLL                    (1<<17)
-#define RX_ETHER                   (1<<18)
-#define RX_MII_ERROR               (1<<19)
-#define RX_DRIBBLING               (1<<20)
-#define RX_CRC_ERROR               (1<<21)
-#define RX_VLAN1                   (1<<22)
-#define RX_VLAN2                   (1<<23)
-#define RX_LEN_ERROR               (1<<24)
-#define RX_CNTRL_FRAME             (1<<25)
-#define RX_U_CNTRL_FRAME           (1<<26)
-#define RX_MCAST_FRAME             (1<<27)
-#define RX_BCAST_FRAME             (1<<28)
-#define RX_FILTER_FAIL             (1<<29)
-#define RX_PACKET_FILTER           (1<<30)
-#define RX_MISSED_FRAME            (1<<31)
-
-#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
-		    RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
-		    RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
-#define MAC_RX_BUFF0_ADDR                0x4
-#define RX_DMA_ENABLE               (1<<0)
-#define RX_T_DONE                   (1<<1)
-#define RX_GET_DMA_BUFFER(X)    (((X)>>2)&0x3)
-#define RX_SET_BUFF_ADDR(X)     ((X)&0xffffffc0)
-#define MAC_RX_BUFF1_STATUS              0x10
-#define MAC_RX_BUFF1_ADDR                0x14
-#define MAC_RX_BUFF2_STATUS              0x20
-#define MAC_RX_BUFF2_ADDR                0x24
-#define MAC_RX_BUFF3_STATUS              0x30
-#define MAC_RX_BUFF3_ADDR                0x34
-
-
-/* UARTS 0-3 */
-#define UART0_ADDR                0xB1100000
-#define UART1_ADDR                0xB1200000
-#define UART2_ADDR                0xB1300000
-#define UART3_ADDR                0xB1400000
-#define UART_BASE                 UART0_ADDR
-#define UART_DEBUG_BASE           UART2_ADDR
-
-#define UART_RX		0	/* Receive buffer */
-#define UART_TX		4	/* Transmit buffer */
-#define UART_IER	8	/* Interrupt Enable Register */
-#define UART_IIR	0xC	/* Interrupt ID Register */
-#define UART_FCR	0x10	/* FIFO Control Register */
-#define UART_LCR	0x14	/* Line Control Register */
-#define UART_MCR	0x18	/* Modem Control Register */
-#define UART_LSR	0x1C	/* Line Status Register */
-#define UART_MSR	0x20	/* Modem Status Register */
-#define UART_CLK	0x28	/* Baud Rate Clock Divider */
-#define UART_ENABLE	0x100	/* Uart enable */
-
-#define UART_EN_CE      1       /* Clock enable */
-#define UART_EN_E       2       /* Enable */
-
-#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
-#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK	0xF0 /* Mask for the FIFO trigger range */
-#define UART_FCR_R_TRIGGER_1	0x00 /* Mask for receive trigger set at 1 */
-#define UART_FCR_R_TRIGGER_4	0x40 /* Mask for receive trigger set at 4 */
-#define UART_FCR_R_TRIGGER_8	0x80 /* Mask for receive trigger set at 8 */
-#define UART_FCR_R_TRIGGER_14   0xA0 /* Mask for receive trigger set at 14 */
-#define UART_FCR_T_TRIGGER_0	0x00 /* Mask for transmit trigger set at 0 */
-#define UART_FCR_T_TRIGGER_4	0x10 /* Mask for transmit trigger set at 4 */
-#define UART_FCR_T_TRIGGER_8    0x20 /* Mask for transmit trigger set at 8 */
-#define UART_FCR_T_TRIGGER_12	0x30 /* Mask for transmit trigger set at 12 */
-
-/*
- * These are the definitions for the Line Control Register
- */
-#define UART_LCR_SBC	0x40	/* Set break control */
-#define UART_LCR_SPAR	0x20	/* Stick parity (?) */
-#define UART_LCR_EPAR	0x10	/* Even parity select */
-#define UART_LCR_PARITY	0x08	/* Parity Enable */
-#define UART_LCR_STOP	0x04	/* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5  0x00	/* Wordlength: 5 bits */
-#define UART_LCR_WLEN6  0x01	/* Wordlength: 6 bits */
-#define UART_LCR_WLEN7  0x02	/* Wordlength: 7 bits */
-#define UART_LCR_WLEN8  0x03	/* Wordlength: 8 bits */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_TEMT	0x40	/* Transmitter empty */
-#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
-#define UART_LSR_BI	0x10	/* Break interrupt indicator */
-#define UART_LSR_FE	0x08	/* Frame error indicator */
-#define UART_LSR_PE	0x04	/* Parity error indicator */
-#define UART_LSR_OE	0x02	/* Overrun error indicator */
-#define UART_LSR_DR	0x01	/* Receiver data ready */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
-#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
-#define UART_IIR_MSI	0x00	/* Modem status interrupt */
-#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
-#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
-#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
-#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
-#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
-#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
-#define UART_MCR_OUT2	0x08	/* Out2 complement */
-#define UART_MCR_OUT1	0x04	/* Out1 complement */
-#define UART_MCR_RTS	0x02	/* RTS complement */
-#define UART_MCR_DTR	0x01	/* DTR complement */
-
-/*
- * These are the definitions for the Modem Status Register
- */
-#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
-#define UART_MSR_RI	0x40	/* Ring Indicator */
-#define UART_MSR_DSR	0x20	/* Data Set Ready */
-#define UART_MSR_CTS	0x10	/* Clear to Send */
-#define UART_MSR_DDCD	0x08	/* Delta DCD */
-#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
-#define UART_MSR_DDSR	0x02	/* Delta DSR */
-#define UART_MSR_DCTS	0x01	/* Delta CTS */
-#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */
-
-
-/* SSIO */
-#define SSI0_STATUS                0xB1600000
-#define SSI_STATUS_BF              (1<<4)
-#define SSI_STATUS_OF              (1<<3)
-#define SSI_STATUS_UF              (1<<2)
-#define SSI_STATUS_D               (1<<1)
-#define SSI_STATUS_B               (1<<0)
-#define SSI0_INT                   0xB1600004
-#define SSI_INT_OI                 (1<<3)
-#define SSI_INT_UI                 (1<<2)
-#define SSI_INT_DI                 (1<<1)
-#define SSI0_INT_ENABLE            0xB1600008
-#define SSI_INTE_OIE               (1<<3)
-#define SSI_INTE_UIE               (1<<2)
-#define SSI_INTE_DIE               (1<<1)
-#define SSI0_CONFIG                0xB1600020
-#define SSI_CONFIG_AO              (1<<24)
-#define SSI_CONFIG_DO              (1<<23)
-#define SSI_CONFIG_ALEN_BIT        20
-#define SSI_CONFIG_ALEN_MASK       (0x7<<20)
-#define SSI_CONFIG_DLEN_BIT        16
-#define SSI_CONFIG_DLEN_MASK       (0x7<<16)
-#define SSI_CONFIG_DD              (1<<11)
-#define SSI_CONFIG_AD              (1<<10)
-#define SSI_CONFIG_BM_BIT          8
-#define SSI_CONFIG_BM_MASK         (0x3<<8)
-#define SSI_CONFIG_CE              (1<<7)
-#define SSI_CONFIG_DP              (1<<6)
-#define SSI_CONFIG_DL              (1<<5)
-#define SSI_CONFIG_EP              (1<<4)
-#define SSI0_ADATA                 0xB1600024
-#define SSI_AD_D                   (1<<24)
-#define SSI_AD_ADDR_BIT            16
-#define SSI_AD_ADDR_MASK           (0xff<<16)
-#define SSI_AD_DATA_BIT            0
-#define SSI_AD_DATA_MASK           (0xfff<<0)
-#define SSI0_CLKDIV                0xB1600028
-#define SSI0_CONTROL               0xB1600100
-#define SSI_CONTROL_CD             (1<<1)
-#define SSI_CONTROL_E              (1<<0)
-
-/* SSI1 */
-#define SSI1_STATUS                0xB1680000
-#define SSI1_INT                   0xB1680004
-#define SSI1_INT_ENABLE            0xB1680008
-#define SSI1_CONFIG                0xB1680020
-#define SSI1_ADATA                 0xB1680024
-#define SSI1_CLKDIV                0xB1680028
-#define SSI1_ENABLE                0xB1680100
-
-/*
- * Register content definitions
- */
-#define SSI_STATUS_BF				(1<<4)
-#define SSI_STATUS_OF				(1<<3)
-#define SSI_STATUS_UF				(1<<2)
-#define SSI_STATUS_D				(1<<1)
-#define SSI_STATUS_B				(1<<0)
-
-/* SSI_INT */
-#define SSI_INT_OI					(1<<3)
-#define SSI_INT_UI					(1<<2)
-#define SSI_INT_DI					(1<<1)
-
-/* SSI_INTEN */
-#define SSI_INTEN_OIE				(1<<3)
-#define SSI_INTEN_UIE				(1<<2)
-#define SSI_INTEN_DIE				(1<<1)
-
-#define SSI_CONFIG_AO				(1<<24)
-#define SSI_CONFIG_DO				(1<<23)
-#define SSI_CONFIG_ALEN				(7<<20)
-#define SSI_CONFIG_DLEN				(15<<16)
-#define SSI_CONFIG_DD				(1<<11)
-#define SSI_CONFIG_AD				(1<<10)
-#define SSI_CONFIG_BM				(3<<8)
-#define SSI_CONFIG_CE				(1<<7)
-#define SSI_CONFIG_DP				(1<<6)
-#define SSI_CONFIG_DL				(1<<5)
-#define SSI_CONFIG_EP				(1<<4)
-#define SSI_CONFIG_ALEN_N(N)		((N-1)<<20)
-#define SSI_CONFIG_DLEN_N(N)		((N-1)<<16)
-#define SSI_CONFIG_BM_HI			(0<<8)
-#define SSI_CONFIG_BM_LO			(1<<8)
-#define SSI_CONFIG_BM_CY			(2<<8)
-
-#define SSI_ADATA_D					(1<<24)
-#define SSI_ADATA_ADDR				(0xFF<<16)
-#define SSI_ADATA_DATA				(0x0FFF)
-#define SSI_ADATA_ADDR_N(N)			(N<<16)
-
-#define SSI_ENABLE_CD				(1<<1)
-#define SSI_ENABLE_E				(1<<0)
-
-
-/* IrDA Controller */
-#define IRDA_BASE                 0xB0300000
-#define IR_RING_PTR_STATUS        (IRDA_BASE+0x00)
-#define IR_RING_BASE_ADDR_H       (IRDA_BASE+0x04)
-#define IR_RING_BASE_ADDR_L       (IRDA_BASE+0x08)
-#define IR_RING_SIZE              (IRDA_BASE+0x0C)
-#define IR_RING_PROMPT            (IRDA_BASE+0x10)
-#define IR_RING_ADDR_CMPR         (IRDA_BASE+0x14)
-#define IR_INT_CLEAR              (IRDA_BASE+0x18)
-#define IR_CONFIG_1               (IRDA_BASE+0x20)
-#define IR_RX_INVERT_LED        (1<<0)
-#define IR_TX_INVERT_LED        (1<<1)
-#define IR_ST                   (1<<2)
-#define IR_SF                   (1<<3)
-#define IR_SIR                  (1<<4)
-#define IR_MIR                  (1<<5)
-#define IR_FIR                  (1<<6)
-#define IR_16CRC                (1<<7)
-#define IR_TD                   (1<<8)
-#define IR_RX_ALL               (1<<9)
-#define IR_DMA_ENABLE           (1<<10)
-#define IR_RX_ENABLE            (1<<11)
-#define IR_TX_ENABLE            (1<<12)
-#define IR_LOOPBACK             (1<<14)
-#define IR_SIR_MODE	          (IR_SIR | IR_DMA_ENABLE | \
-				   IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
-#define IR_SIR_FLAGS              (IRDA_BASE+0x24)
-#define IR_ENABLE                 (IRDA_BASE+0x28)
-#define IR_RX_STATUS            (1<<9)
-#define IR_TX_STATUS            (1<<10)
-#define IR_READ_PHY_CONFIG        (IRDA_BASE+0x2C)
-#define IR_WRITE_PHY_CONFIG       (IRDA_BASE+0x30)
-#define IR_MAX_PKT_LEN            (IRDA_BASE+0x34)
-#define IR_RX_BYTE_CNT            (IRDA_BASE+0x38)
-#define IR_CONFIG_2               (IRDA_BASE+0x3C)
-#define IR_MODE_INV             (1<<0)
-#define IR_ONE_PIN              (1<<1)
-#define IR_INTERFACE_CONFIG       (IRDA_BASE+0x40)
-
-/* GPIO */
-#define SYS_PINFUNC               0xB190002C
-#define SYS_PF_USB			(1<<15)	/* 2nd USB device/host */
-#define SYS_PF_U3			(1<<14)	/* GPIO23/U3TXD */
-#define SYS_PF_U2			(1<<13) /* GPIO22/U2TXD */
-#define SYS_PF_U1			(1<<12) /* GPIO21/U1TXD */
-#define SYS_PF_SRC			(1<<11)	/* GPIO6/SROMCKE */
-#define SYS_PF_CK5			(1<<10)	/* GPIO3/CLK5 */
-#define SYS_PF_CK4			(1<<9)	/* GPIO2/CLK4 */
-#define SYS_PF_IRF			(1<<8)	/* GPIO15/IRFIRSEL */
-#define SYS_PF_UR3			(1<<7)	/* GPIO[14:9]/UART3 */
-#define SYS_PF_I2D			(1<<6)	/* GPIO8/I2SDI */
-#define SYS_PF_I2S			(1<<5)	/* I2S/GPIO[29:31] */
-#define SYS_PF_NI2			(1<<4)	/* NI2/GPIO[24:28] */
-#define SYS_PF_U0			(1<<3)	/* U0TXD/GPIO20 */
-#define SYS_PF_RD			(1<<2)	/* IRTXD/GPIO19 */
-#define SYS_PF_A97			(1<<1)	/* AC97/SSL1 */
-#define SYS_PF_S0			(1<<0)	/* SSI_0/GPIO[16:18] */
-#define SYS_TRIOUTRD              0xB1900100
-#define SYS_TRIOUTCLR             0xB1900100
-#define SYS_OUTPUTRD              0xB1900108
-#define SYS_OUTPUTSET             0xB1900108
-#define SYS_OUTPUTCLR             0xB190010C
-#define SYS_PINSTATERD            0xB1900110
-#define SYS_PININPUTEN            0xB1900110
-
-/* GPIO2, Au1500 only */
-#define GPIO2_BASE                0xB1700000
-#define GPIO2_DIR                 (GPIO2_BASE + 0)
-#define GPIO2_DATA_EN             (GPIO2_BASE + 8)
-#define GPIO2_PIN_STATE           (GPIO2_BASE + 0xC)
-#define GPIO2_INT_ENABLE          (GPIO2_BASE + 0x10)
-#define GPIO2_ENABLE              (GPIO2_BASE + 0x14)
-
-/* Power Management */
-#define SYS_SCRATCH0              0xB1900018
-#define SYS_SCRATCH1              0xB190001C
-#define SYS_WAKEMSK               0xB1900034
-#define SYS_ENDIAN                0xB1900038
-#define SYS_POWERCTRL             0xB190003C
-#define SYS_WAKESRC               0xB190005C
-#define SYS_SLPPWR                0xB1900078
-#define SYS_SLEEP                 0xB190007C
-
-/* Clock Controller */
-#define SYS_FREQCTRL0             0xB1900020
-#define SYS_FC_FRDIV2_BIT         22
-#define SYS_FC_FRDIV2_MASK        (0xff << FQC2_FRDIV2_BIT)
-#define SYS_FC_FE2                (1<<21)
-#define SYS_FC_FS2                (1<<20)
-#define SYS_FC_FRDIV1_BIT         12
-#define SYS_FC_FRDIV1_MASK        (0xff << FQC2_FRDIV1_BIT)
-#define SYS_FC_FE1                (1<<11)
-#define SYS_FC_FS1                (1<<10)
-#define SYS_FC_FRDIV0_BIT         2
-#define SYS_FC_FRDIV0_MASK        (0xff << FQC2_FRDIV0_BIT)
-#define SYS_FC_FE0                (1<<1)
-#define SYS_FC_FS0                (1<<0)
-#define SYS_FREQCTRL1             0xB1900024
-#define SYS_FC_FRDIV5_BIT         22
-#define SYS_FC_FRDIV5_MASK        (0xff << FQC2_FRDIV5_BIT)
-#define SYS_FC_FE5                (1<<21)
-#define SYS_FC_FS5                (1<<20)
-#define SYS_FC_FRDIV4_BIT         12
-#define SYS_FC_FRDIV4_MASK        (0xff << FQC2_FRDIV4_BIT)
-#define SYS_FC_FE4                (1<<11)
-#define SYS_FC_FS4                (1<<10)
-#define SYS_FC_FRDIV3_BIT         2
-#define SYS_FC_FRDIV3_MASK        (0xff << FQC2_FRDIV3_BIT)
-#define SYS_FC_FE3                (1<<1)
-#define SYS_FC_FS3                (1<<0)
-#define SYS_CLKSRC                0xB1900028
-#define SYS_CS_ME1_BIT            27
-#define SYS_CS_ME1_MASK           (0x7<<CSC_ME1_BIT)
-#define SYS_CS_DE1                (1<<26)
-#define SYS_CS_CE1                (1<<25)
-#define SYS_CS_ME0_BIT            22
-#define SYS_CS_ME0_MASK           (0x7<<CSC_ME0_BIT)
-#define SYS_CS_DE0                (1<<21)
-#define SYS_CS_CE0                (1<<20)
-#define SYS_CS_MI2_BIT            17
-#define SYS_CS_MI2_MASK           (0x7<<CSC_MI2_BIT)
-#define SYS_CS_DI2                (1<<16)
-#define SYS_CS_CI2                (1<<15)
-#define SYS_CS_MUH_BIT            12
-#define SYS_CS_MUH_MASK           (0x7<<CSC_MUH_BIT)
-#define SYS_CS_DUH                (1<<11)
-#define SYS_CS_CUH                (1<<10)
-#define SYS_CS_MUD_BIT            7
-#define SYS_CS_MUD_MASK           (0x7<<CSC_MUD_BIT)
-#define SYS_CS_DUD                (1<<6)
-#define SYS_CS_CUD                (1<<5)
-#define SYS_CS_MIR_BIT            2
-#define SYS_CS_MIR_MASK           (0x7<<CSC_MIR_BIT)
-#define SYS_CS_DIR                (1<<1)
-#define SYS_CS_CIR                (1<<0)
-
-#define SYS_CS_MUX_AUX            0x1
-#define SYS_CS_MUX_FQ0            0x2
-#define SYS_CS_MUX_FQ1            0x3
-#define SYS_CS_MUX_FQ2            0x4
-#define SYS_CS_MUX_FQ3            0x5
-#define SYS_CS_MUX_FQ4            0x6
-#define SYS_CS_MUX_FQ5            0x7
-#define SYS_CPUPLL                0xB1900060
-#define SYS_AUXPLL                0xB1900064
-
-/* AC97 Controller */
-#define AC97C_CONFIG              0xB0000000
-#define AC97C_RECV_SLOTS_BIT  13
-#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
-#define AC97C_XMIT_SLOTS_BIT  3
-#define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
-#define AC97C_SG              (1<<2)
-#define AC97C_SYNC            (1<<1)
-#define AC97C_RESET           (1<<0)
-#define AC97C_STATUS              0xB0000004
-#define AC97C_XU              (1<<11)
-#define AC97C_XO              (1<<10)
-#define AC97C_RU              (1<<9)
-#define AC97C_RO              (1<<8)
-#define AC97C_READY           (1<<7)
-#define AC97C_CP              (1<<6)
-#define AC97C_TR              (1<<5)
-#define AC97C_TE              (1<<4)
-#define AC97C_TF              (1<<3)
-#define AC97C_RR              (1<<2)
-#define AC97C_RE              (1<<1)
-#define AC97C_RF              (1<<0)
-#define AC97C_DATA                0xB0000008
-#define AC97C_CMD                 0xB000000C
-#define AC97C_WD_BIT          16
-#define AC97C_READ            (1<<7)
-#define AC97C_INDEX_MASK      0x7f
-#define AC97C_CNTRL               0xB0000010
-#define AC97C_RS              (1<<1)
-#define AC97C_CE              (1<<0)
-
-#define DB1000_BCSR_ADDR 0xAE000000
-#define DB1550_BCSR_ADDR 0xAF000000
-
-#ifdef CONFIG_DBAU1550
-#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR
-#else
-#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR
-#endif
-
-#ifdef CONFIG_SOC_AU1500
-/* Au1500 PCI Controller */
-#define Au1500_CFG_BASE           0xB4005000 /* virtual, kseg0 addr */
-#define Au1500_PCI_CMEM           (Au1500_CFG_BASE + 0)
-#define Au1500_PCI_CFG            (Au1500_CFG_BASE + 4)
-#define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
-#define Au1500_PCI_B2BMASK_CCH    (Au1500_CFG_BASE + 8)
-#define Au1500_PCI_B2B0_VID       (Au1500_CFG_BASE + 0xC)
-#define Au1500_PCI_B2B1_ID        (Au1500_CFG_BASE + 0x10)
-#define Au1500_PCI_MWMASK_DEV     (Au1500_CFG_BASE + 0x14)
-#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
-#define Au1500_PCI_ERR_ADDR       (Au1500_CFG_BASE + 0x1C)
-#define Au1500_PCI_SPEC_INTACK    (Au1500_CFG_BASE + 0x20)
-#define Au1500_PCI_ID             (Au1500_CFG_BASE + 0x100)
-#define Au1500_PCI_STATCMD        (Au1500_CFG_BASE + 0x104)
-#define Au1500_PCI_CLASSREV       (Au1500_CFG_BASE + 0x108)
-#define Au1500_PCI_HDRTYPE        (Au1500_CFG_BASE + 0x10C)
-#define Au1500_PCI_MBAR           (Au1500_CFG_BASE + 0x110)
-
-#define Au1500_PCI_HDR            0xB4005100 /* virtual, kseg0 addr */
-
-/* All of our structures, like pci resource, have 32 bit members.
- * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
- * hard to store 0x4 0000 0000 in a 32 bit type.  We require a small patch
- * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
- * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
- * addresses.  For PCI IO, it's simpler because we get to do the ioremap
- * ourselves and then adjust the device's resources.
- */
-#define Au1500_EXT_CFG            0x600000000
-#define Au1500_EXT_CFG_TYPE1      0x680000000
-#define Au1500_PCI_IO_START       0x500000000
-#define Au1500_PCI_IO_END         0x5000FFFFF
-#define Au1500_PCI_MEM_START      0x440000000
-#define Au1500_PCI_MEM_END        0x443FFFFFF
-
-#define PCI_IO_START    (Au1500_PCI_IO_START + 0x300)
-#define PCI_IO_END      (Au1500_PCI_IO_END)
-#define PCI_MEM_START   (Au1500_PCI_MEM_START)
-#define PCI_MEM_END     (Au1500_PCI_MEM_END)
-#define PCI_FIRST_DEVFN (0<<3)
-#define PCI_LAST_DEVFN  (19<<3)
-
-#endif
-
-#if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000))
-/* no PCI bus controller */
-#define PCI_IO_START    0
-#define PCI_IO_END      0
-#define PCI_MEM_START   0
-#define PCI_MEM_END     0
-#define PCI_FIRST_DEVFN 0
-#define PCI_LAST_DEVFN  0
-#endif
-#define AU1X_SOCK0_IO        0xF00000000
-#define AU1X_SOCK0_PHYS_ATTR 0xF40000000
-#define AU1X_SOCK0_PHYS_MEM  0xF80000000
-
-/* pcmcia socket 1 needs external glue logic so the memory map
- * differs from board to board.
- */
-
-/* Only for db board, not older pb */
-#define AU1X_SOCK1_IO        0xF04000000
-#define AU1X_SOCK1_PHYS_ATTR 0xF44000000
-#define AU1X_SOCK1_PHYS_MEM  0xF84000000
-
-#endif
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/bitops.h b/qemu/roms/u-boot/arch/mips/include/asm/bitops.h
deleted file mode 100644
index b5c2a6367..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/bitops.h
+++ /dev/null
@@ -1,901 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1994 - 1997, 1999, 2000  Ralf Baechle (ralf@gnu.org)
- * Copyright (c) 2000  Silicon Graphics, Inc.
- */
-#ifndef _ASM_BITOPS_H
-#define _ASM_BITOPS_H
-
-#include <linux/types.h>
-#include <asm/byteorder.h>		/* sigh ... */
-
-#ifdef __KERNEL__
-
-#include <asm/sgidefs.h>
-#include <asm/system.h>
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit()	barrier()
-#define smp_mb__after_clear_bit()	barrier()
-
-/*
- * Only disable interrupt for kernel mode stuff to keep usermode stuff
- * that dares to use kernel include files alive.
- */
-#define __bi_flags unsigned long flags
-#define __bi_cli() __cli()
-#define __bi_save_flags(x) __save_flags(x)
-#define __bi_save_and_cli(x) __save_and_cli(x)
-#define __bi_restore_flags(x) __restore_flags(x)
-#else
-#define __bi_flags
-#define __bi_cli()
-#define __bi_save_flags(x)
-#define __bi_save_and_cli(x)
-#define __bi_restore_flags(x)
-#endif /* __KERNEL__ */
-
-#ifdef CONFIG_CPU_HAS_LLSC
-
-#include <asm/mipsregs.h>
-
-/*
- * These functions for MIPS ISA > 1 are interrupt and SMP proof and
- * interrupt friendly
- */
-
-/*
- * set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered.  See __set_bit()
- * if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static __inline__ void
-set_bit(int nr, volatile void *addr)
-{
-	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
-	unsigned long temp;
-
-	__asm__ __volatile__(
-		"1:\tll\t%0, %1\t\t# set_bit\n\t"
-		"or\t%0, %2\n\t"
-		"sc\t%0, %1\n\t"
-		"beqz\t%0, 1b"
-		: "=&r" (temp), "=m" (*m)
-		: "ir" (1UL << (nr & 0x1f)), "m" (*m));
-}
-
-/*
- * __set_bit - Set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * Unlike set_bit(), this function is non-atomic and may be reordered.
- * If it's called on the same region of memory simultaneously, the effect
- * may be that only one operation succeeds.
- */
-static __inline__ void __set_bit(int nr, volatile void * addr)
-{
-	unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
-
-	*m |= 1UL << (nr & 31);
-}
-#define PLATFORM__SET_BIT
-
-/*
- * clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and may not be reordered.  However, it does
- * not contain a memory barrier, so if it is used for locking purposes,
- * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
- * in order to ensure changes are visible on other processors.
- */
-static __inline__ void
-clear_bit(int nr, volatile void *addr)
-{
-	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
-	unsigned long temp;
-
-	__asm__ __volatile__(
-		"1:\tll\t%0, %1\t\t# clear_bit\n\t"
-		"and\t%0, %2\n\t"
-		"sc\t%0, %1\n\t"
-		"beqz\t%0, 1b\n\t"
-		: "=&r" (temp), "=m" (*m)
-		: "ir" (~(1UL << (nr & 0x1f))), "m" (*m));
-}
-
-/*
- * change_bit - Toggle a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * change_bit() is atomic and may not be reordered.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static __inline__ void
-change_bit(int nr, volatile void *addr)
-{
-	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
-	unsigned long temp;
-
-	__asm__ __volatile__(
-		"1:\tll\t%0, %1\t\t# change_bit\n\t"
-		"xor\t%0, %2\n\t"
-		"sc\t%0, %1\n\t"
-		"beqz\t%0, 1b"
-		: "=&r" (temp), "=m" (*m)
-		: "ir" (1UL << (nr & 0x1f)), "m" (*m));
-}
-
-/*
- * __change_bit - Toggle a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * Unlike change_bit(), this function is non-atomic and may be reordered.
- * If it's called on the same region of memory simultaneously, the effect
- * may be that only one operation succeeds.
- */
-static __inline__ void __change_bit(int nr, volatile void * addr)
-{
-	unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
-
-	*m ^= 1UL << (nr & 31);
-}
-
-/*
- * test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int
-test_and_set_bit(int nr, volatile void *addr)
-{
-	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
-	unsigned long temp, res;
-
-	__asm__ __volatile__(
-		".set\tnoreorder\t\t# test_and_set_bit\n"
-		"1:\tll\t%0, %1\n\t"
-		"or\t%2, %0, %3\n\t"
-		"sc\t%2, %1\n\t"
-		"beqz\t%2, 1b\n\t"
-		" and\t%2, %0, %3\n\t"
-		".set\treorder"
-		: "=&r" (temp), "=m" (*m), "=&r" (res)
-		: "r" (1UL << (nr & 0x1f)), "m" (*m)
-		: "memory");
-
-	return res != 0;
-}
-
-/*
- * __test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
-{
-	int mask, retval;
-	volatile int *a = addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a |= mask;
-
-	return retval;
-}
-
-/*
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int
-test_and_clear_bit(int nr, volatile void *addr)
-{
-	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
-	unsigned long temp, res;
-
-	__asm__ __volatile__(
-		".set\tnoreorder\t\t# test_and_clear_bit\n"
-		"1:\tll\t%0, %1\n\t"
-		"or\t%2, %0, %3\n\t"
-		"xor\t%2, %3\n\t"
-		"sc\t%2, %1\n\t"
-		"beqz\t%2, 1b\n\t"
-		" and\t%2, %0, %3\n\t"
-		".set\treorder"
-		: "=&r" (temp), "=m" (*m), "=&r" (res)
-		: "r" (1UL << (nr & 0x1f)), "m" (*m)
-		: "memory");
-
-	return res != 0;
-}
-
-/*
- * __test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
-{
-	int	mask, retval;
-	volatile int	*a = addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a &= ~mask;
-
-	return retval;
-}
-
-/*
- * test_and_change_bit - Change a bit and return its new value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int
-test_and_change_bit(int nr, volatile void *addr)
-{
-	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
-	unsigned long temp, res;
-
-	__asm__ __volatile__(
-		".set\tnoreorder\t\t# test_and_change_bit\n"
-		"1:\tll\t%0, %1\n\t"
-		"xor\t%2, %0, %3\n\t"
-		"sc\t%2, %1\n\t"
-		"beqz\t%2, 1b\n\t"
-		" and\t%2, %0, %3\n\t"
-		".set\treorder"
-		: "=&r" (temp), "=m" (*m), "=&r" (res)
-		: "r" (1UL << (nr & 0x1f)), "m" (*m)
-		: "memory");
-
-	return res != 0;
-}
-
-/*
- * __test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
-{
-	int	mask, retval;
-	volatile int	*a = addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a ^= mask;
-
-	return retval;
-}
-
-#else /* MIPS I */
-
-/*
- * set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered.  See __set_bit()
- * if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static __inline__ void set_bit(int nr, volatile void * addr)
-{
-	int	mask;
-	volatile int	*a = addr;
-	__bi_flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	__bi_save_and_cli(flags);
-	*a |= mask;
-	__bi_restore_flags(flags);
-}
-
-/*
- * __set_bit - Set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * Unlike set_bit(), this function is non-atomic and may be reordered.
- * If it's called on the same region of memory simultaneously, the effect
- * may be that only one operation succeeds.
- */
-static __inline__ void __set_bit(int nr, volatile void * addr)
-{
-	int	mask;
-	volatile int	*a = addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	*a |= mask;
-}
-
-/*
- * clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and may not be reordered.  However, it does
- * not contain a memory barrier, so if it is used for locking purposes,
- * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
- * in order to ensure changes are visible on other processors.
- */
-static __inline__ void clear_bit(int nr, volatile void * addr)
-{
-	int	mask;
-	volatile int	*a = addr;
-	__bi_flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	__bi_save_and_cli(flags);
-	*a &= ~mask;
-	__bi_restore_flags(flags);
-}
-
-/*
- * change_bit - Toggle a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * change_bit() is atomic and may not be reordered.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static __inline__ void change_bit(int nr, volatile void * addr)
-{
-	int	mask;
-	volatile int	*a = addr;
-	__bi_flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	__bi_save_and_cli(flags);
-	*a ^= mask;
-	__bi_restore_flags(flags);
-}
-
-/*
- * __change_bit - Toggle a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * Unlike change_bit(), this function is non-atomic and may be reordered.
- * If it's called on the same region of memory simultaneously, the effect
- * may be that only one operation succeeds.
- */
-static __inline__ void __change_bit(int nr, volatile void * addr)
-{
-	unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
-
-	*m ^= 1UL << (nr & 31);
-}
-
-/*
- * test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int test_and_set_bit(int nr, volatile void * addr)
-{
-	int	mask, retval;
-	volatile int	*a = addr;
-	__bi_flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	__bi_save_and_cli(flags);
-	retval = (mask & *a) != 0;
-	*a |= mask;
-	__bi_restore_flags(flags);
-
-	return retval;
-}
-
-/*
- * __test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
-{
-	int	mask, retval;
-	volatile int	*a = addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a |= mask;
-
-	return retval;
-}
-
-/*
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
-{
-	int	mask, retval;
-	volatile int	*a = addr;
-	__bi_flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	__bi_save_and_cli(flags);
-	retval = (mask & *a) != 0;
-	*a &= ~mask;
-	__bi_restore_flags(flags);
-
-	return retval;
-}
-
-/*
- * __test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
-{
-	int	mask, retval;
-	volatile int	*a = addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a &= ~mask;
-
-	return retval;
-}
-
-/*
- * test_and_change_bit - Change a bit and return its new value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int test_and_change_bit(int nr, volatile void * addr)
-{
-	int	mask, retval;
-	volatile int	*a = addr;
-	__bi_flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	__bi_save_and_cli(flags);
-	retval = (mask & *a) != 0;
-	*a ^= mask;
-	__bi_restore_flags(flags);
-
-	return retval;
-}
-
-/*
- * __test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
-{
-	int	mask, retval;
-	volatile int	*a = addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a ^= mask;
-
-	return retval;
-}
-
-#undef __bi_flags
-#undef __bi_cli
-#undef __bi_save_flags
-#undef __bi_restore_flags
-
-#endif /* MIPS I */
-
-/*
- * test_bit - Determine whether a bit is set
- * @nr: bit number to test
- * @addr: Address to start counting from
- */
-static __inline__ int test_bit(int nr, const volatile void *addr)
-{
-	return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0;
-}
-
-#ifndef __MIPSEB__
-
-/* Little endian versions. */
-
-/*
- * find_first_zero_bit - find the first zero bit in a memory region
- * @addr: The address to start the search at
- * @size: The maximum size to search
- *
- * Returns the bit-number of the first zero bit, not the number of the byte
- * containing a bit.
- */
-static __inline__ int find_first_zero_bit (void *addr, unsigned size)
-{
-	unsigned long dummy;
-	int res;
-
-	if (!size)
-		return 0;
-
-	__asm__ (".set\tnoreorder\n\t"
-		".set\tnoat\n"
-		"1:\tsubu\t$1,%6,%0\n\t"
-		"blez\t$1,2f\n\t"
-		"lw\t$1,(%5)\n\t"
-		"addiu\t%5,4\n\t"
-#if (_MIPS_ISA == _MIPS_ISA_MIPS2 ) || (_MIPS_ISA == _MIPS_ISA_MIPS3 ) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5 ) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-		"beql\t%1,$1,1b\n\t"
-		"addiu\t%0,32\n\t"
-#else
-		"addiu\t%0,32\n\t"
-		"beq\t%1,$1,1b\n\t"
-		"nop\n\t"
-		"subu\t%0,32\n\t"
-#endif
-#ifdef __MIPSEB__
-#error "Fix this for big endian"
-#endif /* __MIPSEB__ */
-		"li\t%1,1\n"
-		"1:\tand\t%2,$1,%1\n\t"
-		"beqz\t%2,2f\n\t"
-		"sll\t%1,%1,1\n\t"
-		"bnez\t%1,1b\n\t"
-		"add\t%0,%0,1\n\t"
-		".set\tat\n\t"
-		".set\treorder\n"
-		"2:"
-		: "=r" (res), "=r" (dummy), "=r" (addr)
-		: "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff),
-		  "2" (addr), "r" (size)
-		: "$1");
-
-	return res;
-}
-
-/*
- * find_next_zero_bit - find the first zero bit in a memory region
- * @addr: The address to base the search on
- * @offset: The bitnumber to start searching at
- * @size: The maximum size to search
- */
-static __inline__ int find_next_zero_bit (void * addr, int size, int offset)
-{
-	unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
-	int set = 0, bit = offset & 31, res;
-	unsigned long dummy;
-
-	if (bit) {
-		/*
-		 * Look for zero in first byte
-		 */
-#ifdef __MIPSEB__
-#error "Fix this for big endian byte order"
-#endif
-		__asm__(".set\tnoreorder\n\t"
-			".set\tnoat\n"
-			"1:\tand\t$1,%4,%1\n\t"
-			"beqz\t$1,1f\n\t"
-			"sll\t%1,%1,1\n\t"
-			"bnez\t%1,1b\n\t"
-			"addiu\t%0,1\n\t"
-			".set\tat\n\t"
-			".set\treorder\n"
-			"1:"
-			: "=r" (set), "=r" (dummy)
-			: "0" (0), "1" (1 << bit), "r" (*p)
-			: "$1");
-		if (set < (32 - bit))
-			return set + offset;
-		set = 32 - bit;
-		p++;
-	}
-	/*
-	 * No zero yet, search remaining full bytes for a zero
-	 */
-	res = find_first_zero_bit(p, size - 32 * (p - (unsigned int *) addr));
-	return offset + set + res;
-}
-
-#endif /* !(__MIPSEB__) */
-
-/*
- * ffz - find first zero in word.
- * @word: The word to search
- *
- * Undefined if no zero exists, so code should check against ~0UL first.
- */
-static __inline__ unsigned long ffz(unsigned long word)
-{
-	unsigned int	__res;
-	unsigned int	mask = 1;
-
-	__asm__ (
-		".set\tnoreorder\n\t"
-		".set\tnoat\n\t"
-		"move\t%0,$0\n"
-		"1:\tand\t$1,%2,%1\n\t"
-		"beqz\t$1,2f\n\t"
-		"sll\t%1,1\n\t"
-		"bnez\t%1,1b\n\t"
-		"addiu\t%0,1\n\t"
-		".set\tat\n\t"
-		".set\treorder\n"
-		"2:\n\t"
-		: "=&r" (__res), "=r" (mask)
-		: "r" (word), "1" (mask)
-		: "$1");
-
-	return __res;
-}
-
-#ifdef __KERNEL__
-
-/*
- * hweightN - returns the hamming weight of a N-bit word
- * @x: the word to weigh
- *
- * The Hamming Weight of a number is the total number of bits set in it.
- */
-
-#define hweight32(x) generic_hweight32(x)
-#define hweight16(x) generic_hweight16(x)
-#define hweight8(x) generic_hweight8(x)
-
-#endif /* __KERNEL__ */
-
-#ifdef __MIPSEB__
-/*
- * find_next_zero_bit - find the first zero bit in a memory region
- * @addr: The address to base the search on
- * @offset: The bitnumber to start searching at
- * @size: The maximum size to search
- */
-static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
-{
-	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
-	unsigned long result = offset & ~31UL;
-	unsigned long tmp;
-
-	if (offset >= size)
-		return size;
-	size -= result;
-	offset &= 31UL;
-	if (offset) {
-		tmp = *(p++);
-		tmp |= ~0UL >> (32-offset);
-		if (size < 32)
-			goto found_first;
-		if (~tmp)
-			goto found_middle;
-		size -= 32;
-		result += 32;
-	}
-	while (size & ~31UL) {
-		if (~(tmp = *(p++)))
-			goto found_middle;
-		result += 32;
-		size -= 32;
-	}
-	if (!size)
-		return result;
-	tmp = *p;
-
-found_first:
-	tmp |= ~0UL << size;
-found_middle:
-	return result + ffz(tmp);
-}
-
-/* Linus sez that gcc can optimize the following correctly, we'll see if this
- * holds on the Sparc as it does for the ALPHA.
- */
-
-#if 0 /* Fool kernel-doc since it doesn't do macros yet */
-/*
- * find_first_zero_bit - find the first zero bit in a memory region
- * @addr: The address to start the search at
- * @size: The maximum size to search
- *
- * Returns the bit-number of the first zero bit, not the number of the byte
- * containing a bit.
- */
-static int find_first_zero_bit (void *addr, unsigned size);
-#endif
-
-#define find_first_zero_bit(addr, size) \
-	find_next_zero_bit((addr), (size), 0)
-
-#endif /* (__MIPSEB__) */
-
-/* Now for the ext2 filesystem bit operations and helper routines. */
-
-#ifdef __MIPSEB__
-static __inline__ int ext2_set_bit(int nr, void * addr)
-{
-	int		mask, retval, flags;
-	unsigned char	*ADDR = (unsigned char *) addr;
-
-	ADDR += nr >> 3;
-	mask = 1 << (nr & 0x07);
-	save_and_cli(flags);
-	retval = (mask & *ADDR) != 0;
-	*ADDR |= mask;
-	restore_flags(flags);
-	return retval;
-}
-
-static __inline__ int ext2_clear_bit(int nr, void * addr)
-{
-	int		mask, retval, flags;
-	unsigned char	*ADDR = (unsigned char *) addr;
-
-	ADDR += nr >> 3;
-	mask = 1 << (nr & 0x07);
-	save_and_cli(flags);
-	retval = (mask & *ADDR) != 0;
-	*ADDR &= ~mask;
-	restore_flags(flags);
-	return retval;
-}
-
-static __inline__ int ext2_test_bit(int nr, const void * addr)
-{
-	int			mask;
-	const unsigned char	*ADDR = (const unsigned char *) addr;
-
-	ADDR += nr >> 3;
-	mask = 1 << (nr & 0x07);
-	return ((mask & *ADDR) != 0);
-}
-
-#define ext2_find_first_zero_bit(addr, size) \
-	ext2_find_next_zero_bit((addr), (size), 0)
-
-static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
-{
-	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
-	unsigned long result = offset & ~31UL;
-	unsigned long tmp;
-
-	if (offset >= size)
-		return size;
-	size -= result;
-	offset &= 31UL;
-	if(offset) {
-		/* We hold the little endian value in tmp, but then the
-		 * shift is illegal. So we could keep a big endian value
-		 * in tmp, like this:
-		 *
-		 * tmp = __swab32(*(p++));
-		 * tmp |= ~0UL >> (32-offset);
-		 *
-		 * but this would decrease preformance, so we change the
-		 * shift:
-		 */
-		tmp = *(p++);
-		tmp |= __swab32(~0UL >> (32-offset));
-		if(size < 32)
-			goto found_first;
-		if(~tmp)
-			goto found_middle;
-		size -= 32;
-		result += 32;
-	}
-	while(size & ~31UL) {
-		if(~(tmp = *(p++)))
-			goto found_middle;
-		result += 32;
-		size -= 32;
-	}
-	if(!size)
-		return result;
-	tmp = *p;
-
-found_first:
-	/* tmp is little endian, so we would have to swab the shift,
-	 * see above. But then we have to swab tmp below for ffz, so
-	 * we might as well do this here.
-	 */
-	return result + ffz(__swab32(tmp) | (~0UL << size));
-found_middle:
-	return result + ffz(__swab32(tmp));
-}
-#else /* !(__MIPSEB__) */
-
-/* Native ext2 byte ordering, just collapse using defines. */
-#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr))
-#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr))
-#define ext2_test_bit(nr, addr) test_bit((nr), (addr))
-#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size))
-#define ext2_find_next_zero_bit(addr, size, offset) \
-		find_next_zero_bit((addr), (size), (offset))
-
-#endif /* !(__MIPSEB__) */
-
-/*
- * Bitmap functions for the minix filesystem.
- * FIXME: These assume that Minix uses the native byte/bitorder.
- * This limits the Minix filesystem's value for data exchange very much.
- */
-#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
-#define minix_set_bit(nr,addr) set_bit(nr,addr)
-#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
-#define minix_test_bit(nr,addr) test_bit(nr,addr)
-#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
-
-#endif /* _ASM_BITOPS_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/byteorder.h b/qemu/roms/u-boot/arch/mips/include/asm/byteorder.h
deleted file mode 100644
index b5e685feb..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/byteorder.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 99, 2003 by Ralf Baechle
- */
-#ifndef _ASM_BYTEORDER_H
-#define _ASM_BYTEORDER_H
-
-#include <asm/types.h>
-
-#ifdef __GNUC__
-
-#ifdef CONFIG_CPU_MIPSR2
-
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
-{
-	__asm__(
-	"	wsbh	%0, %1			\n"
-	: "=r" (x)
-	: "r" (x));
-
-	return x;
-}
-#define __arch__swab16(x)	___arch__swab16(x)
-
-static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
-{
-	__asm__(
-	"	wsbh	%0, %1			\n"
-	"	rotr	%0, %0, 16		\n"
-	: "=r" (x)
-	: "r" (x));
-
-	return x;
-}
-#define __arch__swab32(x)	___arch__swab32(x)
-
-#ifdef CONFIG_CPU_MIPS64_R2
-
-static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
-{
-	__asm__(
-	"	dsbh	%0, %1			\n"
-	"	dshd	%0, %0			\n"
-	"	drotr	%0, %0, 32		\n"
-	: "=r" (x)
-	: "r" (x));
-
-	return x;
-}
-
-#define __arch__swab64(x)	___arch__swab64(x)
-
-#endif /* CONFIG_CPU_MIPS64_R2 */
-
-#endif /* CONFIG_CPU_MIPSR2 */
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#endif /* __GNUC__ */
-
-#if defined(__MIPSEB__)
-#  include <linux/byteorder/big_endian.h>
-#elif defined(__MIPSEL__)
-#  include <linux/byteorder/little_endian.h>
-#else
-#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
-#endif
-
-#endif /* _ASM_BYTEORDER_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/cache.h b/qemu/roms/u-boot/arch/mips/include/asm/cache.h
deleted file mode 100644
index 0dfb54ef4..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/cache.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MIPS_CACHE_H__
-#define __MIPS_CACHE_H__
-
-/*
- * The maximum L1 data cache line size on MIPS seems to be 128 bytes.  We use
- * that as a default for aligning DMA buffers unless the board config has
- * specified another cache line size.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN	128
-#endif
-
-#endif /* __MIPS_CACHE_H__ */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/cachectl.h b/qemu/roms/u-boot/arch/mips/include/asm/cachectl.h
deleted file mode 100644
index f3ce72186..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/cachectl.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
- */
-#ifndef	_ASM_CACHECTL
-#define	_ASM_CACHECTL
-
-/*
- * Options for cacheflush system call
- */
-#define	ICACHE	(1<<0)		/* flush instruction cache        */
-#define	DCACHE	(1<<1)		/* writeback and flush data cache */
-#define	BCACHE	(ICACHE|DCACHE)	/* flush both caches              */
-
-/*
- * Caching modes for the cachectl(2) call
- *
- * cachectl(2) is currently not supported and returns ENOSYS.
- */
-#define CACHEABLE	0	/* make pages cacheable */
-#define UNCACHEABLE	1	/* make pages uncacheable */
-
-#endif	/* _ASM_CACHECTL */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/cacheops.h b/qemu/roms/u-boot/arch/mips/include/asm/cacheops.h
deleted file mode 100644
index 6464250d8..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/cacheops.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Cache operations for the cache instruction.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
- * (C) Copyright 1999 Silicon Graphics, Inc.
- */
-#ifndef	__ASM_CACHEOPS_H
-#define	__ASM_CACHEOPS_H
-
-/*
- * Cache Operations available on all MIPS processors with R4000-style caches
- */
-#define INDEX_INVALIDATE_I      0x00
-#define INDEX_WRITEBACK_INV_D   0x01
-#define INDEX_LOAD_TAG_I	0x04
-#define INDEX_LOAD_TAG_D	0x05
-#define INDEX_STORE_TAG_I	0x08
-#define INDEX_STORE_TAG_D	0x09
-#if defined(CONFIG_CPU_LOONGSON2)
-#define HIT_INVALIDATE_I	0x00
-#else
-#define HIT_INVALIDATE_I	0x10
-#endif
-#define HIT_INVALIDATE_D	0x11
-#define HIT_WRITEBACK_INV_D	0x15
-
-/*
- * R4000-specific cacheops
- */
-#define CREATE_DIRTY_EXCL_D	0x0d
-#define FILL			0x14
-#define HIT_WRITEBACK_I		0x18
-#define HIT_WRITEBACK_D		0x19
-
-/*
- * R4000SC and R4400SC-specific cacheops
- */
-#define INDEX_INVALIDATE_SI     0x02
-#define INDEX_WRITEBACK_INV_SD  0x03
-#define INDEX_LOAD_TAG_SI	0x06
-#define INDEX_LOAD_TAG_SD	0x07
-#define INDEX_STORE_TAG_SI	0x0A
-#define INDEX_STORE_TAG_SD	0x0B
-#define CREATE_DIRTY_EXCL_SD	0x0f
-#define HIT_INVALIDATE_SI	0x12
-#define HIT_INVALIDATE_SD	0x13
-#define HIT_WRITEBACK_INV_SD	0x17
-#define HIT_WRITEBACK_SD	0x1b
-#define HIT_SET_VIRTUAL_SI	0x1e
-#define HIT_SET_VIRTUAL_SD	0x1f
-
-/*
- * R5000-specific cacheops
- */
-#define R5K_PAGE_INVALIDATE_S	0x17
-
-/*
- * RM7000-specific cacheops
- */
-#define PAGE_INVALIDATE_T	0x16
-
-/*
- * R10000-specific cacheops
- *
- * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
- * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
- */
-#define INDEX_WRITEBACK_INV_S	0x03
-#define INDEX_LOAD_TAG_S	0x07
-#define INDEX_STORE_TAG_S	0x0B
-#define HIT_INVALIDATE_S	0x13
-#define CACHE_BARRIER		0x14
-#define HIT_WRITEBACK_INV_S	0x17
-#define INDEX_LOAD_DATA_I	0x18
-#define INDEX_LOAD_DATA_D	0x19
-#define INDEX_LOAD_DATA_S	0x1b
-#define INDEX_STORE_DATA_I	0x1c
-#define INDEX_STORE_DATA_D	0x1d
-#define INDEX_STORE_DATA_S	0x1f
-
-#endif	/* __ASM_CACHEOPS_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/config.h b/qemu/roms/u-boot/arch/mips/include/asm/config.h
deleted file mode 100644
index 1c8a42bd2..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/config.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_CONFIG_H_
-#define _ASM_CONFIG_H_
-
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-
-#define CONFIG_LMB
-#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-
-#endif
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/errno.h b/qemu/roms/u-boot/arch/mips/include/asm/errno.h
deleted file mode 100644
index 4c82b503d..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/errno.h>
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/global_data.h b/qemu/roms/u-boot/arch/mips/include/asm/global_data.h
deleted file mode 100644
index 2d9a0c9e7..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/global_data.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * (C) Copyright 2002-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef	__ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-#include <asm/regdef.h>
-
-/* Architecture-specific global data */
-struct arch_global_data {
-#ifdef CONFIG_JZSOC
-	/* There are other clocks in the jz4740 */
-	unsigned long per_clk;	/* Peripheral bus clock */
-	unsigned long dev_clk;	/* Device clock */
-	unsigned long sys_clk;
-	unsigned long tbl;
-	unsigned long lastinc;
-#endif
-};
-
-#include <asm-generic/global_data.h>
-
-#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("k0")
-
-#endif /* __ASM_GBL_DATA_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/io.h b/qemu/roms/u-boot/arch/mips/include/asm/io.h
deleted file mode 100644
index 3fa37f5dd..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/io.h
+++ /dev/null
@@ -1,507 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995 Waldorf GmbH
- * Copyright (C) 1994 - 2000 Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 FSMLabs, Inc.
- */
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
-
-#if 0
-#include <linux/pagemap.h>
-#endif
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-
-/*
- * Slowdown I/O port space accesses for antique hardware.
- */
-#undef CONF_SLOWDOWN_IO
-
-/*
- * Sane hardware offers swapping of I/O space accesses in hardware; less
- * sane hardware forces software to fiddle with this ...
- */
-#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
-
-#define __ioswab8(x) (x)
-#define __ioswab16(x) swab16(x)
-#define __ioswab32(x) swab32(x)
-
-#else
-
-#define __ioswab8(x) (x)
-#define __ioswab16(x) (x)
-#define __ioswab32(x) (x)
-
-#endif
-
-/*
- * This file contains the definitions for the MIPS counterpart of the
- * x86 in/out instructions. This heap of macros and C results in much
- * better code than the approach of doing it in plain C.  The macros
- * result in code that is to fast for certain hardware.  On the other
- * side the performance of the string functions should be improved for
- * sake of certain devices like EIDE disks that do highspeed polled I/O.
- *
- *   Ralf
- *
- * This file contains the definitions for the x86 IO instructions
- * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
- *
- * This file is not meant to be obfuscating: it's just complicated
- * to (a) handle it all in a way that makes gcc able to optimize it
- * as well as possible and (b) trying to avoid writing the same thing
- * over and over again with slight variations and possibly making a
- * mistake somewhere.
- */
-
-/*
- * On MIPS I/O ports are memory mapped, so we access them using normal
- * load/store instructions. mips_io_port_base is the virtual address to
- * which all ports are being mapped.  For sake of efficiency some code
- * assumes that this is an address that can be loaded with a single lui
- * instruction, so the lower 16 bits must be zero.  Should be true on
- * on any sane architecture; generic code does not use this assumption.
- */
-extern const unsigned long mips_io_port_base;
-
-/*
- * Gcc will generate code to load the value of mips_io_port_base after each
- * function call which may be fairly wasteful in some cases.  So we don't
- * play quite by the book.  We tell gcc mips_io_port_base is a long variable
- * which solves the code generation issue.  Now we need to violate the
- * aliasing rules a little to make initialization possible and finally we
- * will need the barrier() to fight side effects of the aliasing chat.
- * This trickery will eventually collapse under gcc's optimizer.  Oh well.
- */
-static inline void set_io_port_base(unsigned long base)
-{
-	* (unsigned long *) &mips_io_port_base = base;
-}
-
-/*
- * Thanks to James van Artsdalen for a better timing-fix than
- * the two short jumps: using outb's to a nonexistent port seems
- * to guarantee better timings even on fast machines.
- *
- * On the other hand, I'd like to be sure of a non-existent port:
- * I feel a bit unsafe about using 0x80 (should be safe, though)
- *
- *		Linus
- *
- */
-
-#define __SLOW_DOWN_IO \
-	__asm__ __volatile__( \
-		"sb\t$0,0x80(%0)" \
-		: : "r" (mips_io_port_base));
-
-#ifdef CONF_SLOWDOWN_IO
-#ifdef REALLY_SLOW_IO
-#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
-#else
-#define SLOW_DOWN_IO __SLOW_DOWN_IO
-#endif
-#else
-#define SLOW_DOWN_IO
-#endif
-
-/*
- * Change virtual addresses to physical addresses and vv.
- * These are trivial on the 1:1 Linux/MIPS mapping
- */
-extern inline phys_addr_t virt_to_phys(volatile void * address)
-{
-#ifndef CONFIG_64BIT
-	return CPHYSADDR(address);
-#else
-	return XPHYSADDR(address);
-#endif
-}
-
-extern inline void * phys_to_virt(unsigned long address)
-{
-#ifndef CONFIG_64BIT
-	return (void *)KSEG0ADDR(address);
-#else
-	return (void *)CKSEG0ADDR(address);
-#endif
-}
-
-/*
- * IO bus memory addresses are also 1:1 with the physical address
- */
-extern inline unsigned long virt_to_bus(volatile void * address)
-{
-#ifndef CONFIG_64BIT
-	return CPHYSADDR(address);
-#else
-	return XPHYSADDR(address);
-#endif
-}
-
-extern inline void * bus_to_virt(unsigned long address)
-{
-#ifndef CONFIG_64BIT
-	return (void *)KSEG0ADDR(address);
-#else
-	return (void *)CKSEG0ADDR(address);
-#endif
-}
-
-/*
- * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
- * for the processor.
- */
-extern unsigned long isa_slot_offset;
-
-extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-
-#if 0
-extern inline void *ioremap(unsigned long offset, unsigned long size)
-{
-	return __ioremap(offset, size, _CACHE_UNCACHED);
-}
-
-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
-{
-	return __ioremap(offset, size, _CACHE_UNCACHED);
-}
-
-extern void iounmap(void *addr);
-#endif
-
-/*
- * XXX We need system specific versions of these to handle EISA address bits
- * 24-31 on SNI.
- * XXX more SNI hacks.
- */
-#define __raw_readb(addr) (*(volatile unsigned char *)(addr))
-#define __raw_readw(addr) (*(volatile unsigned short *)(addr))
-#define __raw_readl(addr) (*(volatile unsigned int *)(addr))
-#define readb(addr) __raw_readb((addr))
-#define readw(addr) __ioswab16(__raw_readw((addr)))
-#define readl(addr) __ioswab32(__raw_readl((addr)))
-
-#define __raw_writeb(b, addr) (*(volatile unsigned char *)(addr)) = (b)
-#define __raw_writew(b, addr) (*(volatile unsigned short *)(addr)) = (b)
-#define __raw_writel(b, addr) (*(volatile unsigned int *)(addr)) = (b)
-#define writeb(b, addr) __raw_writeb((b), (addr))
-#define writew(b, addr) __raw_writew(__ioswab16(b), (addr))
-#define writel(b, addr) __raw_writel(__ioswab32(b), (addr))
-
-#define memset_io(a,b,c)	memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
-
-/* END SNI HACKS ... */
-
-/*
- * ISA space is 'always mapped' on currently supported MIPS systems, no need
- * to explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define __ISA_IO_base ((char *)(PAGE_OFFSET))
-
-#define isa_readb(a) readb(a)
-#define isa_readw(a) readw(a)
-#define isa_readl(a) readl(a)
-#define isa_writeb(b,a) writeb(b,a)
-#define isa_writew(w,a) writew(w,a)
-#define isa_writel(l,a) writel(l,a)
-
-#define isa_memset_io(a,b,c)     memset_io((a),(b),(c))
-#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
-#define isa_memcpy_toio(a,b,c)   memcpy_toio((a),(b),(c))
-
-/*
- * We don't have csum_partial_copy_fromio() yet, so we cheat here and
- * just copy it. The net code will then do the checksum later.
- */
-#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
-#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
-
-static inline int check_signature(unsigned long io_addr,
-				  const unsigned char *signature, int length)
-{
-	int retval = 0;
-	do {
-		if (readb(io_addr) != *signature)
-			goto out;
-		io_addr++;
-		signature++;
-		length--;
-	} while (length);
-	retval = 1;
-out:
-	return retval;
-}
-#define isa_check_signature(io, s, l) check_signature(i,s,l)
-
-/*
- * Talk about misusing macros..
- */
-
-#define __OUT1(s) \
-static inline void __out##s(unsigned int value, unsigned int port) {
-
-#define __OUT2(m) \
-__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
-
-#define __OUT(m,s,w) \
-__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \
-__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \
-__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \
-	SLOW_DOWN_IO; } \
-__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \
-	SLOW_DOWN_IO; }
-
-#define __IN1(t,s) \
-static inline t __in##s(unsigned int port) { t _v;
-
-/*
- * Required nops will be inserted by the assembler
- */
-#define __IN2(m) \
-__asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
-
-#define __IN(t,m,s,w) \
-__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \
-__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \
-__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \
-__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
-
-#define __INS1(s) \
-static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
-
-#define __INS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
-	".set\tnoreorder\n\t" \
-	".set\tnoat\n" \
-	"1:\tl" #m "\t$1,%4(%5)\n\t" \
-	"subu\t%1,1\n\t" \
-	"s" #m "\t$1,(%0)\n\t" \
-	"bne\t$0,%1,1b\n\t" \
-	"addiu\t%0,%6\n\t" \
-	".set\tat\n\t" \
-	".set\treorder"
-
-#define __INS(m,s,i) \
-__INS1(s) __INS2(m) \
-	: "=r" (addr), "=r" (count) \
-	: "0" (addr), "1" (count), "i" (0), \
-	  "r" (mips_io_port_base+port), "I" (i) \
-	: "$1");} \
-__INS1(s##c) __INS2(m) \
-	: "=r" (addr), "=r" (count) \
-	: "0" (addr), "1" (count), "ir" (port), \
-	  "r" (mips_io_port_base), "I" (i) \
-	: "$1");}
-
-#define __OUTS1(s) \
-static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
-
-#define __OUTS2(m) \
-if (count) \
-__asm__ __volatile__ ( \
-	".set\tnoreorder\n\t" \
-	".set\tnoat\n" \
-	"1:\tl" #m "\t$1,(%0)\n\t" \
-	"subu\t%1,1\n\t" \
-	"s" #m "\t$1,%4(%5)\n\t" \
-	"bne\t$0,%1,1b\n\t" \
-	"addiu\t%0,%6\n\t" \
-	".set\tat\n\t" \
-	".set\treorder"
-
-#define __OUTS(m,s,i) \
-__OUTS1(s) __OUTS2(m) \
-	: "=r" (addr), "=r" (count) \
-	: "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
-	: "$1");} \
-__OUTS1(s##c) __OUTS2(m) \
-	: "=r" (addr), "=r" (count) \
-	: "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
-	: "$1");}
-
-__IN(unsigned char,b,b,8)
-__IN(unsigned short,h,w,16)
-__IN(unsigned int,w,l,32)
-
-__OUT(b,b,8)
-__OUT(h,w,16)
-__OUT(w,l,32)
-
-__INS(b,b,1)
-__INS(h,w,2)
-__INS(w,l,4)
-
-__OUTS(b,b,1)
-__OUTS(h,w,2)
-__OUTS(w,l,4)
-
-
-/*
- * Note that due to the way __builtin_constant_p() works, you
- *  - can't use it inside an inline function (it will never be true)
- *  - you don't have to worry about side effects within the __builtin..
- */
-#define outb(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outbc((val),(port)) : \
-	__outb((val),(port)))
-
-#define inb(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inbc(port) : \
-	__inb(port))
-
-#define outb_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outbc_p((val),(port)) : \
-	__outb_p((val),(port)))
-
-#define inb_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inbc_p(port) : \
-	__inb_p(port))
-
-#define outw(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outwc((val),(port)) : \
-	__outw((val),(port)))
-
-#define inw(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inwc(port) : \
-	__inw(port))
-
-#define outw_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outwc_p((val),(port)) : \
-	__outw_p((val),(port)))
-
-#define inw_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inwc_p(port) : \
-	__inw_p(port))
-
-#define outl(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outlc((val),(port)) : \
-	__outl((val),(port)))
-
-#define inl(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inlc(port) : \
-	__inl(port))
-
-#define outl_p(val,port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outlc_p((val),(port)) : \
-	__outl_p((val),(port)))
-
-#define inl_p(port) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inlc_p(port) : \
-	__inl_p(port))
-
-
-#define outsb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outsbc((port),(addr),(count)) : \
-	__outsb ((port),(addr),(count)))
-
-#define insb(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__insbc((port),(addr),(count)) : \
-	__insb((port),(addr),(count)))
-
-#define outsw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outswc((port),(addr),(count)) : \
-	__outsw ((port),(addr),(count)))
-
-#define insw(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inswc((port),(addr),(count)) : \
-	__insw((port),(addr),(count)))
-
-#define outsl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__outslc((port),(addr),(count)) : \
-	__outsl ((port),(addr),(count)))
-
-#define insl(port,addr,count) \
-((__builtin_constant_p((port)) && (port) < 32768) ? \
-	__inslc((port),(addr),(count)) : \
-	__insl((port),(addr),(count)))
-
-#define IO_SPACE_LIMIT 0xffff
-
-/*
- * The caches on some architectures aren't dma-coherent and have need to
- * handle this in software.  There are three types of operations that
- * can be applied to dma buffers.
- *
- *  - dma_cache_wback_inv(start, size) makes caches and coherent by
- *    writing the content of the caches back to memory, if necessary.
- *    The function also invalidates the affected part of the caches as
- *    necessary before DMA transfers from outside to memory.
- *  - dma_cache_wback(start, size) makes caches and coherent by
- *    writing the content of the caches back to memory, if necessary.
- *    The function also invalidates the affected part of the caches as
- *    necessary before DMA transfers from outside to memory.
- *  - dma_cache_inv(start, size) invalidates the affected parts of the
- *    caches.  Dirty lines of the caches may be written back or simply
- *    be discarded.  This operation is necessary before dma operations
- *    to the memory.
- */
-extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
-extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
-extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-
-#define dma_cache_wback_inv(start,size)	_dma_cache_wback_inv(start,size)
-#define dma_cache_wback(start,size)	_dma_cache_wback(start,size)
-#define dma_cache_inv(start,size)	_dma_cache_inv(start,size)
-
-static inline void sync(void)
-{
-}
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-#define MAP_NOCACHE	(0)
-#define MAP_WRCOMBINE	(0)
-#define MAP_WRBACK	(0)
-#define MAP_WRTHROUGH	(0)
-
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
-	return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-#endif /* _ASM_IO_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/isadep.h b/qemu/roms/u-boot/arch/mips/include/asm/isadep.h
deleted file mode 100644
index 24c6cda79..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/isadep.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Various ISA level dependent constants.
- * Most of the following constants reflect the different layout
- * of Coprocessor 0 registers.
- *
- * Copyright (c) 1998 Harald Koerfgen
- */
-
-#ifndef __ASM_ISADEP_H
-#define __ASM_ISADEP_H
-
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-/*
- * R2000 or R3000
- */
-
-/*
- * kernel or user mode? (CP0_STATUS)
- */
-#define KU_MASK 0x08
-#define	KU_USER 0x08
-#define KU_KERN 0x00
-
-#else
-/*
- * kernel or user mode?
- */
-#define KU_MASK 0x18
-#define	KU_USER 0x10
-#define KU_KERN 0x00
-
-#endif
-
-#endif /* __ASM_ISADEP_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/jz4740.h b/qemu/roms/u-boot/arch/mips/include/asm/jz4740.h
deleted file mode 100644
index 7a7cfff29..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/jz4740.h
+++ /dev/null
@@ -1,1150 +0,0 @@
-/*
- * head file for Ingenic Semiconductor's JZ4740 CPU.
- */
-#ifndef __JZ4740_H__
-#define __JZ4740_H__
-
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
-/* Boot ROM Specification  */
-/* NOR Boot config */
-#define JZ4740_NORBOOT_8BIT	0x00000000	/* 8-bit data bus flash */
-#define JZ4740_NORBOOT_16BIT	0x10101010	/* 16-bit data bus flash */
-#define JZ4740_NORBOOT_32BIT	0x20202020	/* 32-bit data bus flash */
-/* NAND Boot config */
-#define JZ4740_NANDBOOT_B8R3	0xffffffff	/* 8-bit bus & 3 row cycles */
-#define JZ4740_NANDBOOT_B8R2	0xf0f0f0f0	/* 8-bit bus & 2 row cycles */
-#define JZ4740_NANDBOOT_B16R3	0x0f0f0f0f	/* 16-bit bus & 3 row cycles */
-#define JZ4740_NANDBOOT_B16R2	0x00000000	/* 16-bit bus & 2 row cycles */
-
-/* 1st-level interrupts */
-#define JZ4740_IRQ_I2C		1
-#define JZ4740_IRQ_UHC		3
-#define JZ4740_IRQ_UART0	9
-#define JZ4740_IRQ_SADC		12
-#define JZ4740_IRQ_MSC		14
-#define JZ4740_IRQ_RTC		15
-#define JZ4740_IRQ_SSI		16
-#define JZ4740_IRQ_CIM		17
-#define JZ4740_IRQ_AIC		18
-#define JZ4740_IRQ_ETH		19
-#define JZ4740_IRQ_DMAC		20
-#define JZ4740_IRQ_TCU2		21
-#define JZ4740_IRQ_TCU1		22
-#define JZ4740_IRQ_TCU0		23
-#define JZ4740_IRQ_UDC		24
-#define JZ4740_IRQ_GPIO3	25
-#define JZ4740_IRQ_GPIO2	26
-#define JZ4740_IRQ_GPIO1	27
-#define JZ4740_IRQ_GPIO0	28
-#define JZ4740_IRQ_IPU		29
-#define JZ4740_IRQ_LCD		30
-/* 2nd-level interrupts */
-#define JZ4740_IRQ_DMA_0	32  /* 32 to 37 for DMAC channel 0 to 5 */
-#define JZ4740_IRQ_GPIO_0	48  /* 48 to 175 for GPIO pin 0 to 127 */
-
-/* Register Definitions */
-#define JZ4740_CPM_BASE		0x10000000
-#define JZ4740_INTC_BASE	0x10001000
-#define JZ4740_TCU_BASE		0x10002000
-#define JZ4740_WDT_BASE		0x10002000
-#define JZ4740_RTC_BASE		0x10003000
-#define JZ4740_GPIO_BASE	0x10010000
-#define JZ4740_AIC_BASE		0x10020000
-#define JZ4740_ICDC_BASE	0x10020000
-#define JZ4740_MSC_BASE		0x10021000
-#define JZ4740_UART0_BASE	0x10030000
-#define JZ4740_I2C_BASE		0x10042000
-#define JZ4740_SSI_BASE		0x10043000
-#define JZ4740_SADC_BASE	0x10070000
-#define JZ4740_EMC_BASE		0x13010000
-#define JZ4740_DMAC_BASE	0x13020000
-#define JZ4740_UHC_BASE		0x13030000
-#define JZ4740_UDC_BASE		0x13040000
-#define JZ4740_LCD_BASE		0x13050000
-#define JZ4740_SLCD_BASE	0x13050000
-#define JZ4740_CIM_BASE		0x13060000
-#define JZ4740_ETH_BASE		0x13100000
-
-/* 8bit Mode Register of SDRAM bank 0 */
-#define JZ4740_EMC_SDMR0	(JZ4740_EMC_BASE + 0xa000)
-
-/* GPIO (General-Purpose I/O Ports) */
-/*  = 0,1,2,3 */
-#define GPIO_PXPIN(n)	\
-	(JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
-#define GPIO_PXDAT(n)	\
-	(JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
-#define GPIO_PXDATS(n)	\
-	(JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
-#define GPIO_PXDATC(n)	\
-	(JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
-#define GPIO_PXIM(n)	\
-	(JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
-#define GPIO_PXIMS(n)	\
-	(JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
-#define GPIO_PXIMC(n)	\
-	(JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
-#define GPIO_PXPE(n)	\
-	(JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
-#define GPIO_PXPES(n)	\
-	(JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
-#define GPIO_PXPEC(n)	\
-	(JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
-#define GPIO_PXFUN(n)	\
-	(JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
-#define GPIO_PXFUNS(n)	\
-	(JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
-#define GPIO_PXFUNC(n)	\
-	(JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
-#define GPIO_PXSEL(n)	\
-	(JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
-#define GPIO_PXSELS(n)	\
-	(JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
-#define GPIO_PXSELC(n)	\
-	(JZ4740_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
-#define GPIO_PXDIR(n)	\
-	(JZ4740_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
-#define GPIO_PXDIRS(n)	\
-	(JZ4740_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
-#define GPIO_PXDIRC(n)	\
-	(JZ4740_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
-#define GPIO_PXTRG(n)	\
-	(JZ4740_GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
-#define GPIO_PXTRGS(n)	\
-	(JZ4740_GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
-#define GPIO_PXTRGC(n)	\
-	(JZ4740_GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
-
-/* Static Memory Control Register */
-#define EMC_SMCR_STRV_BIT	24
-#define EMC_SMCR_STRV_MASK	(0x0f << EMC_SMCR_STRV_BIT)
-#define EMC_SMCR_TAW_BIT	20
-#define EMC_SMCR_TAW_MASK	(0x0f << EMC_SMCR_TAW_BIT)
-#define EMC_SMCR_TBP_BIT	16
-#define EMC_SMCR_TBP_MASK	(0x0f << EMC_SMCR_TBP_BIT)
-#define EMC_SMCR_TAH_BIT	12
-#define EMC_SMCR_TAH_MASK	(0x07 << EMC_SMCR_TAH_BIT)
-#define EMC_SMCR_TAS_BIT	8
-#define EMC_SMCR_TAS_MASK	(0x07 << EMC_SMCR_TAS_BIT)
-#define EMC_SMCR_BW_BIT		6
-#define EMC_SMCR_BW_MASK	(0x03 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_8BIT	(0 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_16BIT	(1 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_32BIT	(2 << EMC_SMCR_BW_BIT)
-#define EMC_SMCR_BCM		(1 << 3)
-#define EMC_SMCR_BL_BIT		1
-#define EMC_SMCR_BL_MASK	(0x03 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_4		(0 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_8		(1 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_16	(2 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_32	(3 << EMC_SMCR_BL_BIT)
-#define EMC_SMCR_SMT		(1 << 0)
-
-/* Static Memory Bank Addr Config Reg */
-#define EMC_SACR_BASE_BIT	8
-#define EMC_SACR_BASE_MASK	(0xff << EMC_SACR_BASE_BIT)
-#define EMC_SACR_MASK_BIT	0
-#define EMC_SACR_MASK_MASK	(0xff << EMC_SACR_MASK_BIT)
-
-/* NAND Flash Control/Status Register */
-#define EMC_NFCSR_NFCE4		(1 << 7) /* NAND Flash Enable */
-#define EMC_NFCSR_NFE4		(1 << 6) /* NAND Flash FCE# Assertion Enable */
-#define EMC_NFCSR_NFCE3		(1 << 5)
-#define EMC_NFCSR_NFE3		(1 << 4)
-#define EMC_NFCSR_NFCE2		(1 << 3)
-#define EMC_NFCSR_NFE2		(1 << 2)
-#define EMC_NFCSR_NFCE1		(1 << 1)
-#define EMC_NFCSR_NFE1		(1 << 0)
-
-/* NAND Flash ECC Control Register */
-#define EMC_NFECR_PRDY		(1 << 4) /* Parity Ready */
-#define EMC_NFECR_RS_DECODING	(0 << 3) /* RS is in decoding phase */
-#define EMC_NFECR_RS_ENCODING	(1 << 3) /* RS is in encoding phase */
-#define EMC_NFECR_HAMMING	(0 << 2) /* Use HAMMING Correction Algorithm */
-#define EMC_NFECR_RS		(1 << 2) /* Select RS Correction Algorithm */
-#define EMC_NFECR_ERST		(1 << 1) /* ECC Reset */
-#define EMC_NFECR_ECCE		(1 << 0) /* ECC Enable */
-
-/* NAND Flash ECC Data Register */
-#define EMC_NFECC_ECC2_BIT	16
-#define EMC_NFECC_ECC2_MASK	(0xff << EMC_NFECC_ECC2_BIT)
-#define EMC_NFECC_ECC1_BIT	8
-#define EMC_NFECC_ECC1_MASK	(0xff << EMC_NFECC_ECC1_BIT)
-#define EMC_NFECC_ECC0_BIT	0
-#define EMC_NFECC_ECC0_MASK	(0xff << EMC_NFECC_ECC0_BIT)
-
-/* NAND Flash Interrupt Status Register */
-#define EMC_NFINTS_ERRCNT_BIT	29       /* Error Count */
-#define EMC_NFINTS_ERRCNT_MASK	(0x7 << EMC_NFINTS_ERRCNT_BIT)
-#define EMC_NFINTS_PADF		(1 << 4) /* Padding Finished */
-#define EMC_NFINTS_DECF		(1 << 3) /* Decoding Finished */
-#define EMC_NFINTS_ENCF		(1 << 2) /* Encoding Finished */
-#define EMC_NFINTS_UNCOR	(1 << 1) /* Uncorrectable Error Occurred */
-#define EMC_NFINTS_ERR		(1 << 0) /* Error Occurred */
-
-/* NAND Flash Interrupt Enable Register */
-#define EMC_NFINTE_PADFE	(1 << 4) /* Padding Finished Interrupt */
-#define EMC_NFINTE_DECFE	(1 << 3) /* Decoding Finished Interrupt */
-#define EMC_NFINTE_ENCFE	(1 << 2) /* Encoding Finished Interrupt */
-#define EMC_NFINTE_UNCORE	(1 << 1) /* Uncorrectable Error Occurred Intr */
-#define EMC_NFINTE_ERRE		(1 << 0) /* Error Occurred Interrupt */
-
-/* NAND Flash RS Error Report Register */
-#define EMC_NFERR_INDEX_BIT	16       /* Error Symbol Index */
-#define EMC_NFERR_INDEX_MASK	(0x1ff << EMC_NFERR_INDEX_BIT)
-#define EMC_NFERR_MASK_BIT	0        /* Error Symbol Value */
-#define EMC_NFERR_MASK_MASK	(0x1ff << EMC_NFERR_MASK_BIT)
-
-/* DRAM Control Register */
-#define EMC_DMCR_BW_BIT		31
-#define EMC_DMCR_BW		(1 << EMC_DMCR_BW_BIT)
-#define EMC_DMCR_CA_BIT		26
-#define EMC_DMCR_CA_MASK	(0x07 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_8		(0 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_9		(1 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_10	(2 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_11	(3 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_12	(4 << EMC_DMCR_CA_BIT)
-#define EMC_DMCR_RMODE		(1 << 25)
-#define EMC_DMCR_RFSH		(1 << 24)
-#define EMC_DMCR_MRSET		(1 << 23)
-#define EMC_DMCR_RA_BIT		20
-#define EMC_DMCR_RA_MASK	(0x03 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_11	(0 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_12	(1 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_13	(2 << EMC_DMCR_RA_BIT)
-#define EMC_DMCR_BA_BIT		19
-#define EMC_DMCR_BA		(1 << EMC_DMCR_BA_BIT)
-#define EMC_DMCR_PDM		(1 << 18)
-#define EMC_DMCR_EPIN		(1 << 17)
-#define EMC_DMCR_TRAS_BIT	13
-#define EMC_DMCR_TRAS_MASK	(0x07 << EMC_DMCR_TRAS_BIT)
-#define EMC_DMCR_RCD_BIT	11
-#define EMC_DMCR_RCD_MASK	(0x03 << EMC_DMCR_RCD_BIT)
-#define EMC_DMCR_TPC_BIT	8
-#define EMC_DMCR_TPC_MASK	(0x07 << EMC_DMCR_TPC_BIT)
-#define EMC_DMCR_TRWL_BIT	5
-#define EMC_DMCR_TRWL_MASK	(0x03 << EMC_DMCR_TRWL_BIT)
-#define EMC_DMCR_TRC_BIT	2
-#define EMC_DMCR_TRC_MASK	(0x07 << EMC_DMCR_TRC_BIT)
-#define EMC_DMCR_TCL_BIT	0
-#define EMC_DMCR_TCL_MASK	(0x03 << EMC_DMCR_TCL_BIT)
-
-/* Refresh Time Control/Status Register */
-#define EMC_RTCSR_CMF		(1 << 7)
-#define EMC_RTCSR_CKS_BIT	0
-#define EMC_RTCSR_CKS_MASK	(0x07 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_DISABLE	(0 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_4	(1 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_16	(2 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_64	(3 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_256	(4 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_1024	(5 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_2048	(6 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_4096	(7 << EMC_RTCSR_CKS_BIT)
-
-/* SDRAM Bank Address Configuration Register */
-#define EMC_DMAR_BASE_BIT	8
-#define EMC_DMAR_BASE_MASK	(0xff << EMC_DMAR_BASE_BIT)
-#define EMC_DMAR_MASK_BIT	0
-#define EMC_DMAR_MASK_MASK	(0xff << EMC_DMAR_MASK_BIT)
-
-/* Mode Register of SDRAM bank 0 */
-#define EMC_SDMR_BM		(1 << 9) /* Write Burst Mode */
-#define EMC_SDMR_OM_BIT		7        /* Operating Mode */
-#define EMC_SDMR_OM_MASK	(3 << EMC_SDMR_OM_BIT)
-  #define EMC_SDMR_OM_NORMAL	(0 << EMC_SDMR_OM_BIT)
-#define EMC_SDMR_CAS_BIT	4        /* CAS Latency */
-#define EMC_SDMR_CAS_MASK	(7 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_1	(1 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_2	(2 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_3	(3 << EMC_SDMR_CAS_BIT)
-#define EMC_SDMR_BT_BIT		3        /* Burst Type */
-#define EMC_SDMR_BT_MASK	(1 << EMC_SDMR_BT_BIT)
-  #define EMC_SDMR_BT_SEQ	(0 << EMC_SDMR_BT_BIT) /* Sequential */
-  #define EMC_SDMR_BT_INT	(1 << EMC_SDMR_BT_BIT) /* Interleave */
-#define EMC_SDMR_BL_BIT		0        /* Burst Length */
-#define EMC_SDMR_BL_MASK	(7 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_1		(0 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_2		(1 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_4		(2 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_8		(3 << EMC_SDMR_BL_BIT)
-
-#define EMC_SDMR_CAS2_16BIT \
-	(EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS2_32BIT \
-	(EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-#define EMC_SDMR_CAS3_16BIT \
-	(EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS3_32BIT \
-	(EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-
-/* RTC Control Register */
-#define RTC_RCR_WRDY	(1 << 7)  /* Write Ready Flag */
-#define RTC_RCR_HZ	(1 << 6)  /* 1Hz Flag */
-#define RTC_RCR_HZIE	(1 << 5)  /* 1Hz Interrupt Enable */
-#define RTC_RCR_AF	(1 << 4)  /* Alarm Flag */
-#define RTC_RCR_AIE	(1 << 3)  /* Alarm Interrupt Enable */
-#define RTC_RCR_AE	(1 << 2)  /* Alarm Enable */
-#define RTC_RCR_RTCE	(1 << 0)  /* RTC Enable */
-
-/* RTC Regulator Register */
-#define RTC_RGR_LOCK		(1 << 31) /* Lock Bit */
-#define RTC_RGR_ADJC_BIT	16
-#define RTC_RGR_ADJC_MASK	(0x3ff << RTC_RGR_ADJC_BIT)
-#define RTC_RGR_NC1HZ_BIT	0
-#define RTC_RGR_NC1HZ_MASK	(0xffff << RTC_RGR_NC1HZ_BIT)
-
-/* Hibernate Control Register */
-#define RTC_HCR_PD		(1 << 0)  /* Power Down */
-
-/* Hibernate Wakeup Filter Counter Register */
-#define RTC_HWFCR_BIT		5
-#define RTC_HWFCR_MASK		(0x7ff << RTC_HWFCR_BIT)
-
-/* Hibernate Reset Counter Register */
-#define RTC_HRCR_BIT		5
-#define RTC_HRCR_MASK		(0x7f << RTC_HRCR_BIT)
-
-/* Hibernate Wakeup Control Register */
-#define RTC_HWCR_EALM		(1 << 0)  /* RTC alarm wakeup enable */
-
-/* Hibernate Wakeup Status Register */
-#define RTC_HWRSR_HR		(1 << 5)  /* Hibernate reset */
-#define RTC_HWRSR_PPR		(1 << 4)  /* PPR reset */
-#define RTC_HWRSR_PIN		(1 << 1)  /* Wakeup pin status bit */
-#define RTC_HWRSR_ALM		(1 << 0)  /* RTC alarm status bit */
-
-/* Clock Control Register */
-#define CPM_CPCCR_I2CS		(1 << 31)
-#define CPM_CPCCR_CLKOEN	(1 << 30)
-#define CPM_CPCCR_UCS		(1 << 29)
-#define CPM_CPCCR_UDIV_BIT	23
-#define CPM_CPCCR_UDIV_MASK	(0x3f << CPM_CPCCR_UDIV_BIT)
-#define CPM_CPCCR_CE		(1 << 22)
-#define CPM_CPCCR_PCS		(1 << 21)
-#define CPM_CPCCR_LDIV_BIT	16
-#define CPM_CPCCR_LDIV_MASK	(0x1f << CPM_CPCCR_LDIV_BIT)
-#define CPM_CPCCR_MDIV_BIT	12
-#define CPM_CPCCR_MDIV_MASK	(0x0f << CPM_CPCCR_MDIV_BIT)
-#define CPM_CPCCR_PDIV_BIT	8
-#define CPM_CPCCR_PDIV_MASK	(0x0f << CPM_CPCCR_PDIV_BIT)
-#define CPM_CPCCR_HDIV_BIT	4
-#define CPM_CPCCR_HDIV_MASK	(0x0f << CPM_CPCCR_HDIV_BIT)
-#define CPM_CPCCR_CDIV_BIT	0
-#define CPM_CPCCR_CDIV_MASK	(0x0f << CPM_CPCCR_CDIV_BIT)
-
-/* I2S Clock Divider Register */
-#define CPM_I2SCDR_I2SDIV_BIT	0
-#define CPM_I2SCDR_I2SDIV_MASK	(0x1ff << CPM_I2SCDR_I2SDIV_BIT)
-
-/* LCD Pixel Clock Divider Register */
-#define CPM_LPCDR_PIXDIV_BIT	0
-#define CPM_LPCDR_PIXDIV_MASK	(0x1ff << CPM_LPCDR_PIXDIV_BIT)
-
-/* MSC Clock Divider Register */
-#define CPM_MSCCDR_MSCDIV_BIT	0
-#define CPM_MSCCDR_MSCDIV_MASK	(0x1f << CPM_MSCCDR_MSCDIV_BIT)
-
-/* PLL Control Register */
-#define CPM_CPPCR_PLLM_BIT	23
-#define CPM_CPPCR_PLLM_MASK	(0x1ff << CPM_CPPCR_PLLM_BIT)
-#define CPM_CPPCR_PLLN_BIT	18
-#define CPM_CPPCR_PLLN_MASK	(0x1f << CPM_CPPCR_PLLN_BIT)
-#define CPM_CPPCR_PLLOD_BIT	16
-#define CPM_CPPCR_PLLOD_MASK	(0x03 << CPM_CPPCR_PLLOD_BIT)
-#define CPM_CPPCR_PLLS		(1 << 10)
-#define CPM_CPPCR_PLLBP		(1 << 9)
-#define CPM_CPPCR_PLLEN		(1 << 8)
-#define CPM_CPPCR_PLLST_BIT	0
-#define CPM_CPPCR_PLLST_MASK	(0xff << CPM_CPPCR_PLLST_BIT)
-
-/* Low Power Control Register */
-#define CPM_LCR_DOZE_DUTY_BIT	3
-#define CPM_LCR_DOZE_DUTY_MASK	(0x1f << CPM_LCR_DOZE_DUTY_BIT)
-#define CPM_LCR_DOZE_ON		(1 << 2)
-#define CPM_LCR_LPM_BIT		0
-#define CPM_LCR_LPM_MASK	(0x3 << CPM_LCR_LPM_BIT)
-  #define CPM_LCR_LPM_IDLE	(0x0 << CPM_LCR_LPM_BIT)
-  #define CPM_LCR_LPM_SLEEP	(0x1 << CPM_LCR_LPM_BIT)
-
-/* Clock Gate Register */
-#define CPM_CLKGR_UART1		(1 << 15)
-#define CPM_CLKGR_UHC		(1 << 14)
-#define CPM_CLKGR_IPU		(1 << 13)
-#define CPM_CLKGR_DMAC		(1 << 12)
-#define CPM_CLKGR_UDC		(1 << 11)
-#define CPM_CLKGR_LCD		(1 << 10)
-#define CPM_CLKGR_CIM		(1 << 9)
-#define CPM_CLKGR_SADC		(1 << 8)
-#define CPM_CLKGR_MSC		(1 << 7)
-#define CPM_CLKGR_AIC1		(1 << 6)
-#define CPM_CLKGR_AIC2		(1 << 5)
-#define CPM_CLKGR_SSI		(1 << 4)
-#define CPM_CLKGR_I2C		(1 << 3)
-#define CPM_CLKGR_RTC		(1 << 2)
-#define CPM_CLKGR_TCU		(1 << 1)
-#define CPM_CLKGR_UART0		(1 << 0)
-
-/* Sleep Control Register */
-#define CPM_SCR_O1ST_BIT	8
-#define CPM_SCR_O1ST_MASK	(0xff << CPM_SCR_O1ST_BIT)
-#define CPM_SCR_UDCPHY_ENABLE	(1 << 6)
-#define CPM_SCR_USBPHY_DISABLE	(1 << 7)
-#define CPM_SCR_OSC_ENABLE	(1 << 4)
-
-/* Hibernate Control Register */
-#define CPM_HCR_PD		(1 << 0)
-
-/* Wakeup Filter Counter Register in Hibernate Mode */
-#define CPM_HWFCR_TIME_BIT	0
-#define CPM_HWFCR_TIME_MASK	(0x3ff << CPM_HWFCR_TIME_BIT)
-
-/* Reset Counter Register in Hibernate Mode */
-#define CPM_HRCR_TIME_BIT	0
-#define CPM_HRCR_TIME_MASK	(0x7f << CPM_HRCR_TIME_BIT)
-
-/* Wakeup Control Register in Hibernate Mode */
-#define CPM_HWCR_WLE_LOW	(0 << 2)
-#define CPM_HWCR_WLE_HIGH	(1 << 2)
-#define CPM_HWCR_PIN_WAKEUP	(1 << 1)
-#define CPM_HWCR_RTC_WAKEUP	(1 << 0)
-
-/* Wakeup Status Register in Hibernate Mode */
-#define CPM_HWSR_WSR_PIN	(1 << 1)
-#define CPM_HWSR_WSR_RTC	(1 << 0)
-
-/* Reset Status Register */
-#define CPM_RSR_HR		(1 << 2)
-#define CPM_RSR_WR		(1 << 1)
-#define CPM_RSR_PR		(1 << 0)
-
-/* Register definitions */
-#define TCU_TCSR_PWM_SD		(1 << 9)
-#define TCU_TCSR_PWM_INITL_HIGH	(1 << 8)
-#define TCU_TCSR_PWM_EN		(1 << 7)
-#define TCU_TCSR_PRESCALE_BIT	3
-#define TCU_TCSR_PRESCALE_MASK	(0x7 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1	(0x0 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE4	(0x1 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE16	(0x2 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE64	(0x3 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE256	(0x4 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1024	(0x5 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_EXT_EN		(1 << 2)
-#define TCU_TCSR_RTC_EN		(1 << 1)
-#define TCU_TCSR_PCK_EN		(1 << 0)
-
-#define TCU_TER_TCEN5		(1 << 5)
-#define TCU_TER_TCEN4		(1 << 4)
-#define TCU_TER_TCEN3		(1 << 3)
-#define TCU_TER_TCEN2		(1 << 2)
-#define TCU_TER_TCEN1		(1 << 1)
-#define TCU_TER_TCEN0		(1 << 0)
-
-#define TCU_TESR_TCST5		(1 << 5)
-#define TCU_TESR_TCST4		(1 << 4)
-#define TCU_TESR_TCST3		(1 << 3)
-#define TCU_TESR_TCST2		(1 << 2)
-#define TCU_TESR_TCST1		(1 << 1)
-#define TCU_TESR_TCST0		(1 << 0)
-
-#define TCU_TECR_TCCL5		(1 << 5)
-#define TCU_TECR_TCCL4		(1 << 4)
-#define TCU_TECR_TCCL3		(1 << 3)
-#define TCU_TECR_TCCL2		(1 << 2)
-#define TCU_TECR_TCCL1		(1 << 1)
-#define TCU_TECR_TCCL0		(1 << 0)
-
-#define TCU_TFR_HFLAG5		(1 << 21)
-#define TCU_TFR_HFLAG4		(1 << 20)
-#define TCU_TFR_HFLAG3		(1 << 19)
-#define TCU_TFR_HFLAG2		(1 << 18)
-#define TCU_TFR_HFLAG1		(1 << 17)
-#define TCU_TFR_HFLAG0		(1 << 16)
-#define TCU_TFR_FFLAG5		(1 << 5)
-#define TCU_TFR_FFLAG4		(1 << 4)
-#define TCU_TFR_FFLAG3		(1 << 3)
-#define TCU_TFR_FFLAG2		(1 << 2)
-#define TCU_TFR_FFLAG1		(1 << 1)
-#define TCU_TFR_FFLAG0		(1 << 0)
-
-#define TCU_TFSR_HFLAG5		(1 << 21)
-#define TCU_TFSR_HFLAG4		(1 << 20)
-#define TCU_TFSR_HFLAG3		(1 << 19)
-#define TCU_TFSR_HFLAG2		(1 << 18)
-#define TCU_TFSR_HFLAG1		(1 << 17)
-#define TCU_TFSR_HFLAG0		(1 << 16)
-#define TCU_TFSR_FFLAG5		(1 << 5)
-#define TCU_TFSR_FFLAG4		(1 << 4)
-#define TCU_TFSR_FFLAG3		(1 << 3)
-#define TCU_TFSR_FFLAG2		(1 << 2)
-#define TCU_TFSR_FFLAG1		(1 << 1)
-#define TCU_TFSR_FFLAG0		(1 << 0)
-
-#define TCU_TFCR_HFLAG5		(1 << 21)
-#define TCU_TFCR_HFLAG4		(1 << 20)
-#define TCU_TFCR_HFLAG3		(1 << 19)
-#define TCU_TFCR_HFLAG2		(1 << 18)
-#define TCU_TFCR_HFLAG1		(1 << 17)
-#define TCU_TFCR_HFLAG0		(1 << 16)
-#define TCU_TFCR_FFLAG5		(1 << 5)
-#define TCU_TFCR_FFLAG4		(1 << 4)
-#define TCU_TFCR_FFLAG3		(1 << 3)
-#define TCU_TFCR_FFLAG2		(1 << 2)
-#define TCU_TFCR_FFLAG1		(1 << 1)
-#define TCU_TFCR_FFLAG0		(1 << 0)
-
-#define TCU_TMR_HMASK5		(1 << 21)
-#define TCU_TMR_HMASK4		(1 << 20)
-#define TCU_TMR_HMASK3		(1 << 19)
-#define TCU_TMR_HMASK2		(1 << 18)
-#define TCU_TMR_HMASK1		(1 << 17)
-#define TCU_TMR_HMASK0		(1 << 16)
-#define TCU_TMR_FMASK5		(1 << 5)
-#define TCU_TMR_FMASK4		(1 << 4)
-#define TCU_TMR_FMASK3		(1 << 3)
-#define TCU_TMR_FMASK2		(1 << 2)
-#define TCU_TMR_FMASK1		(1 << 1)
-#define TCU_TMR_FMASK0		(1 << 0)
-
-#define TCU_TMSR_HMST5		(1 << 21)
-#define TCU_TMSR_HMST4		(1 << 20)
-#define TCU_TMSR_HMST3		(1 << 19)
-#define TCU_TMSR_HMST2		(1 << 18)
-#define TCU_TMSR_HMST1		(1 << 17)
-#define TCU_TMSR_HMST0		(1 << 16)
-#define TCU_TMSR_FMST5		(1 << 5)
-#define TCU_TMSR_FMST4		(1 << 4)
-#define TCU_TMSR_FMST3		(1 << 3)
-#define TCU_TMSR_FMST2		(1 << 2)
-#define TCU_TMSR_FMST1		(1 << 1)
-#define TCU_TMSR_FMST0		(1 << 0)
-
-#define TCU_TMCR_HMCL5		(1 << 21)
-#define TCU_TMCR_HMCL4		(1 << 20)
-#define TCU_TMCR_HMCL3		(1 << 19)
-#define TCU_TMCR_HMCL2		(1 << 18)
-#define TCU_TMCR_HMCL1		(1 << 17)
-#define TCU_TMCR_HMCL0		(1 << 16)
-#define TCU_TMCR_FMCL5		(1 << 5)
-#define TCU_TMCR_FMCL4		(1 << 4)
-#define TCU_TMCR_FMCL3		(1 << 3)
-#define TCU_TMCR_FMCL2		(1 << 2)
-#define TCU_TMCR_FMCL1		(1 << 1)
-#define TCU_TMCR_FMCL0		(1 << 0)
-
-#define TCU_TSR_WDTS		(1 << 16)
-#define TCU_TSR_STOP5		(1 << 5)
-#define TCU_TSR_STOP4		(1 << 4)
-#define TCU_TSR_STOP3		(1 << 3)
-#define TCU_TSR_STOP2		(1 << 2)
-#define TCU_TSR_STOP1		(1 << 1)
-#define TCU_TSR_STOP0		(1 << 0)
-
-#define TCU_TSSR_WDTSS		(1 << 16)
-#define TCU_TSSR_STPS5		(1 << 5)
-#define TCU_TSSR_STPS4		(1 << 4)
-#define TCU_TSSR_STPS3		(1 << 3)
-#define TCU_TSSR_STPS2		(1 << 2)
-#define TCU_TSSR_STPS1		(1 << 1)
-#define TCU_TSSR_STPS0		(1 << 0)
-
-#define TCU_TSSR_WDTSC		(1 << 16)
-#define TCU_TSSR_STPC5		(1 << 5)
-#define TCU_TSSR_STPC4		(1 << 4)
-#define TCU_TSSR_STPC3		(1 << 3)
-#define TCU_TSSR_STPC2		(1 << 2)
-#define TCU_TSSR_STPC1		(1 << 1)
-#define TCU_TSSR_STPC0		(1 << 0)
-
-/* Register definition */
-#define WDT_TCSR_PRESCALE_BIT	3
-#define WDT_TCSR_PRESCALE_MASK	(0x7 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE1	(0x0 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE4	(0x1 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE16	(0x2 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE64	(0x3 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE256	(0x4 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE1024	(0x5 << WDT_TCSR_PRESCALE_BIT)
-#define WDT_TCSR_EXT_EN		(1 << 2)
-#define WDT_TCSR_RTC_EN		(1 << 1)
-#define WDT_TCSR_PCK_EN		(1 << 0)
-#define WDT_TCER_TCEN		(1 << 0)
-
-/*
- * Define macros for UART_IER
- * UART Interrupt Enable Register
- */
-#define UART_IER_RIE	(1 << 0) /* 0: receive fifo full interrupt disable */
-#define UART_IER_TIE	(1 << 1) /* 0: transmit fifo empty interrupt disable */
-#define UART_IER_RLIE	(1 << 2) /* 0: receive line status interrupt disable */
-#define UART_IER_MIE	(1 << 3) /* 0: modem status interrupt disable */
-#define UART_IER_RTIE	(1 << 4) /* 0: receive timeout interrupt disable */
-
-/*
- * Define macros for UART_ISR
- * UART Interrupt Status Register
- */
-#define UART_ISR_IP	(1 << 0) /* 0: interrupt is pending 1: no interrupt */
-#define UART_ISR_IID	(7 << 1) /* Source of Interrupt */
-#define UART_ISR_IID_MSI  (0 << 1) /* Modem status interrupt */
-#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
-#define UART_ISR_IID_RDI  (2 << 1) /* Receiver data interrupt */
-#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
-/* FIFO mode select, set when UART_FCR.FE is set to 1 */
-#define UART_ISR_FFMS	(3 << 6)
-#define UART_ISR_FFMS_NO_FIFO	(0 << 6)
-#define UART_ISR_FFMS_FIFO_MODE	(3 << 6)
-
-/*
- * Define macros for UART_FCR
- * UART FIFO Control Register
- */
-#define UART_FCR_FE	(1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */
-#define UART_FCR_RFLS	(1 << 1)	/* write 1 to flush receive FIFO */
-#define UART_FCR_TFLS	(1 << 2)	/* write 1 to flush transmit FIFO */
-#define UART_FCR_DMS	(1 << 3)	/* 0: disable DMA mode */
-#define UART_FCR_UUE	(1 << 4)	/* 0: disable UART */
-#define UART_FCR_RTRG	(3 << 6)	/* Receive FIFO Data Trigger */
-#define UART_FCR_RTRG_1	(0 << 6)
-#define UART_FCR_RTRG_4	(1 << 6)
-#define UART_FCR_RTRG_8	(2 << 6)
-#define UART_FCR_RTRG_15	(3 << 6)
-
-/*
- * Define macros for UART_LCR
- * UART Line Control Register
- */
-#define UART_LCR_WLEN	(3 << 0)	/* word length */
-#define UART_LCR_WLEN_5	(0 << 0)
-#define UART_LCR_WLEN_6	(1 << 0)
-#define UART_LCR_WLEN_7	(2 << 0)
-#define UART_LCR_WLEN_8	(3 << 0)
-#define UART_LCR_STOP	(1 << 2)
-	/* 0: 1 stop bit when word length is 5,6,7,8
-	   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UART_LCR_STOP_1	(0 << 2)
-	/* 0: 1 stop bit when word length is 5,6,7,8
-	   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UART_LCR_STOP_2	(1 << 2)
-	/* 0: 1 stop bit when word length is 5,6,7,8
-	   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-
-#define UART_LCR_PE	(1 << 3) /* 0: parity disable */
-#define UART_LCR_PROE	(1 << 4) /* 0: even parity  1: odd parity */
-#define UART_LCR_SPAR	(1 << 5) /* 0: sticky parity disable */
-#define UART_LCR_SBRK	(1 << 6) /* write 0 normal, write 1 send break */
-/* 0: access UART_RDR/TDR/IER  1: access UART_DLLR/DLHR */
-#define UART_LCR_DLAB	(1 << 7)
-
-/*
- * Define macros for UART_LSR
- * UART Line Status Register
- */
-/* 0: receive FIFO is empty  1: receive data is ready */
-#define UART_LSR_DR	(1 << 0)
-/* 0: no overrun error */
-#define UART_LSR_ORER	(1 << 1)
-/* 0: no parity error */
-#define UART_LSR_PER	(1 << 2)
-/* 0; no framing error */
-#define UART_LSR_FER	(1 << 3)
-/* 0: no break detected  1: receive a break signal */
-#define UART_LSR_BRK	(1 << 4)
-/* 1: transmit FIFO half "empty" */
-#define UART_LSR_TDRQ	(1 << 5)
-/* 1: transmit FIFO and shift registers empty */
-#define UART_LSR_TEMT	(1 << 6)
-/* 0: no receive error  1: receive error in FIFO mode */
-#define UART_LSR_RFER	(1 << 7)
-
-/*
- * Define macros for UART_MCR
- * UART Modem Control Register
- */
-#define UART_MCR_DTR	(1 << 0) /* 0: DTR_ ouput high */
-#define UART_MCR_RTS	(1 << 1) /* 0: RTS_ output high */
-/* 0: UART_MSR.RI is set to 0 and RI_ input high */
-#define UART_MCR_OUT1	(1 << 2)
-/* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
-#define UART_MCR_OUT2	(1 << 3)
-#define UART_MCR_LOOP	(1 << 4) /* 0: normal  1: loopback mode */
-#define UART_MCR_MCE	(1 << 7) /* 0: modem function is disable */
-
-/*
- * Define macros for UART_MSR
- * UART Modem Status Register
- */
-#define UART_MSR_DCTS	(1 << 0) /* 0: no change on CTS_ since last read */
-#define UART_MSR_DDSR	(1 << 1) /* 0: no change on DSR_ since last read */
-#define UART_MSR_DRI	(1 << 2) /* 0: no change on RI_  since last read */
-#define UART_MSR_DDCD	(1 << 3) /* 0: no change on DCD_ since last read */
-#define UART_MSR_CTS	(1 << 4) /* 0: CTS_ pin is high */
-#define UART_MSR_DSR	(1 << 5) /* 0: DSR_ pin is high */
-#define UART_MSR_RI	(1 << 6) /* 0: RI_ pin is high */
-#define UART_MSR_DCD	(1 << 7) /* 0: DCD_ pin is high */
-
-/*
- * Define macros for SIRCR
- * Slow IrDA Control Register
- */
-#define SIRCR_TSIRE (1 << 0) /* 0: TX is in UART mode 1: IrDA mode */
-#define SIRCR_RSIRE (1 << 1) /* 0: RX is in UART mode 1: IrDA mode */
-#define SIRCR_TPWS  (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
-				1: 0 pulse width is 1.6us for 115.2Kbps */
-#define SIRCR_TXPL  (1 << 3) /* 0: encoder generates a positive pulse for 0 */
-#define SIRCR_RXPL  (1 << 4) /* 0: decoder interprets positive pulse as 0 */
-
-/* MSC Clock and Control Register (MSC_STRPCL) */
-#define MSC_STRPCL_EXIT_MULTIPLE	(1 << 7)
-#define MSC_STRPCL_EXIT_TRANSFER	(1 << 6)
-#define MSC_STRPCL_START_READWAIT	(1 << 5)
-#define MSC_STRPCL_STOP_READWAIT	(1 << 4)
-#define MSC_STRPCL_RESET		(1 << 3)
-#define MSC_STRPCL_START_OP		(1 << 2)
-#define MSC_STRPCL_CLOCK_CONTROL_BIT	0
-#define MSC_STRPCL_CLOCK_CONTROL_MASK	(0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-#define MSC_STRPCL_CLOCK_CONTROL_STOP	(0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-#define MSC_STRPCL_CLOCK_CONTROL_START	(0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-
-/* MSC Status Register (MSC_STAT) */
-#define MSC_STAT_IS_RESETTING		(1 << 15)
-#define MSC_STAT_SDIO_INT_ACTIVE	(1 << 14)
-#define MSC_STAT_PRG_DONE		(1 << 13)
-#define MSC_STAT_DATA_TRAN_DONE		(1 << 12)
-#define MSC_STAT_END_CMD_RES		(1 << 11)
-#define MSC_STAT_DATA_FIFO_AFULL	(1 << 10)
-#define MSC_STAT_IS_READWAIT		(1 << 9)
-#define MSC_STAT_CLK_EN			(1 << 8)
-#define MSC_STAT_DATA_FIFO_FULL		(1 << 7)
-#define MSC_STAT_DATA_FIFO_EMPTY	(1 << 6)
-#define MSC_STAT_CRC_RES_ERR		(1 << 5)
-#define MSC_STAT_CRC_READ_ERROR		(1 << 4)
-#define MSC_STAT_CRC_WRITE_ERROR_BIT	2
-#define MSC_STAT_CRC_WRITE_ERROR_MASK	(0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* No error on transmission of data */
-  #define MSC_STAT_CRC_WRITE_ERROR_NO	(0 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* Card observed erroneous transmission of data */
-  #define MSC_STAT_CRC_WRITE_ERROR	(1 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* No CRC status is sent back */
-  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-#define MSC_STAT_TIME_OUT_RES		(1 << 1)
-#define MSC_STAT_TIME_OUT_READ		(1 << 0)
-
-/* MSC Bus Clock Control Register (MSC_CLKRT) */
-#define MSC_CLKRT_CLK_RATE_BIT		0
-#define MSC_CLKRT_CLK_RATE_MASK		(0x7 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_1  (0x0 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_2  (0x1 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_4  (0x2 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_8  (0x3 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_16  (0x4 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_32  (0x5 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_64  (0x6 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT)
-
-/* MSC Command Sequence Control Register (MSC_CMDAT) */
-#define MSC_CMDAT_IO_ABORT	(1 << 11)
-#define MSC_CMDAT_BUS_WIDTH_BIT	9
-#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_DMA_EN	(1 << 8)
-#define MSC_CMDAT_INIT		(1 << 7)
-#define MSC_CMDAT_BUSY		(1 << 6)
-#define MSC_CMDAT_STREAM_BLOCK	(1 << 5)
-#define MSC_CMDAT_WRITE		(1 << 4)
-#define MSC_CMDAT_READ		(0 << 4)
-#define MSC_CMDAT_DATA_EN	(1 << 3)
-#define MSC_CMDAT_RESPONSE_BIT	0
-#define MSC_CMDAT_RESPONSE_MASK	(0x7 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_NONE	(0x0 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R1	(0x1 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R2	(0x2 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R3	(0x3 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R4	(0x4 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R5	(0x5 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R6	(0x6 << MSC_CMDAT_RESPONSE_BIT)
-
-/* MSC Interrupts Mask Register (MSC_IMASK) */
-#define MSC_IMASK_SDIO			(1 << 7)
-#define MSC_IMASK_TXFIFO_WR_REQ		(1 << 6)
-#define MSC_IMASK_RXFIFO_RD_REQ		(1 << 5)
-#define MSC_IMASK_END_CMD_RES		(1 << 2)
-#define MSC_IMASK_PRG_DONE		(1 << 1)
-#define MSC_IMASK_DATA_TRAN_DONE	(1 << 0)
-
-#ifndef __ASSEMBLY__
-/* INTC (Interrupt Controller) */
-struct jz4740_intc {
-	uint32_t isr;		/* interrupt source register */
-	uint32_t imr;		/* interrupt mask register */
-	uint32_t imsr;		/* interrupt mask set register */
-	uint32_t imcr;		/* interrupt mask clear register */
-	uint32_t ipr;		/* interrupt pending register */
-};
-
-/* RTC */
-struct jz4740_rtc {
-	uint32_t rcr;		/* rtc control register */
-	uint32_t rsr;		/* rtc second register */
-	uint32_t rsar;		/* rtc second alarm register */
-	uint32_t rgr;		/* rtc regulator register */
-	uint32_t hcr;		/* hibernate control register */
-	uint32_t hwfcr;		/* hibernate wakeup filter counter reg */
-	uint32_t hrcr;		/* hibernate reset counter reg */
-	uint32_t hwcr;		/* hibernate wakeup control register */
-	uint32_t hwrsr;		/* hibernate wakeup status reg */
-	uint32_t hspr;		/* scratch pattern register */
-};
-
-/* CPM (Clock reset and Power control Management) */
-struct jz4740_cpm {
-	uint32_t cpccr; /* 0x00 clock control reg */
-	uint32_t lcr;	/* 0x04 low power control reg */
-	uint32_t rsr;	/* 0x08 reset status reg */
-	uint32_t pad00;
-	uint32_t cppcr; /* 0x10 pll control reg */
-	uint32_t pad01[3];
-	uint32_t clkgr;	/* 0x20 clock gate reg */
-	uint32_t scr;	/* 0x24 sleep control reg */
-	uint32_t pad02[14];
-	uint32_t i2scd; /* 0x60 I2S device clock divider reg */
-	uint32_t lpcdr; /* 0x64 LCD pix clock divider reg */
-	uint32_t msccdr; /* 0x68 MSC device clock divider reg */
-	uint32_t uhccdr; /* 0x6C UHC 48M clock divider reg */
-	uint32_t uhcts; /* 0x70 UHC PHY test point reg */
-	uint32_t ssicd; /* 0x74 SSI clock divider reg */
-};
-
-/* TCU (Timer Counter Unit) */
-struct jz4740_tcu {
-	uint32_t pad00[4];
-	uint32_t ter;	/* 0x10  Timer Counter Enable Register */
-	uint32_t tesr;	/* 0x14  Timer Counter Enable Set Register */
-	uint32_t tecr;	/* 0x18  Timer Counter Enable Clear Register */
-	uint32_t tsr;	/* 0x1C  Timer Stop Register */
-	uint32_t tfr;	/* 0x20  Timer Flag Register */
-	uint32_t tfsr;	/* 0x24  Timer Flag Set Register */
-	uint32_t tfcr;	/* 0x28  Timer Flag Clear Register */
-	uint32_t tssr;	/* 0x2C  Timer Stop Set Register */
-	uint32_t tmr;	/* 0x30  Timer Mask Register */
-	uint32_t tmsr;	/* 0x34  Timer Mask Set Register */
-	uint32_t tmcr;	/* 0x38  Timer Mask Clear Register */
-	uint32_t tscr;	/* 0x3C  Timer Stop Clear Register */
-	uint32_t tdfr0;	/* 0x40  Timer Data Full Register */
-	uint32_t tdhr0;	/* 0x44  Timer Data Half Register */
-	uint32_t tcnt0;	/* 0x48  Timer Counter Register */
-	uint32_t tcsr0;	/* 0x4C  Timer Control Register */
-	uint32_t tdfr1;	/* 0x50 */
-	uint32_t tdhr1;	/* 0x54 */
-	uint32_t tcnt1;	/* 0x58 */
-	uint32_t tcsr1;	/* 0x5C */
-	uint32_t tdfr2;	/* 0x60 */
-	uint32_t tdhr2;	/* 0x64 */
-	uint32_t tcnt2;	/* 0x68 */
-	uint32_t tcsr2;	/* 0x6C */
-	uint32_t tdfr3;	/* 0x70 */
-	uint32_t tdhr3;	/* 0x74 */
-	uint32_t tcnt3;	/* 0x78 */
-	uint32_t tcsr3;	/* 0x7C */
-	uint32_t tdfr4;	/* 0x80 */
-	uint32_t tdhr4;	/* 0x84 */
-	uint32_t tcnt4;	/* 0x88 */
-	uint32_t tcsr4;	/* 0x8C */
-	uint32_t tdfr5;	/* 0x90 */
-	uint32_t tdhr5;	/* 0x94 */
-	uint32_t tcnt5;	/* 0x98 */
-	uint32_t tcsr5;	/* 0x9C */
-};
-
-/* WDT (WatchDog Timer) */
-struct jz4740_wdt {
-	uint16_t tdr; /* 0x00 watchdog timer data reg*/
-	uint16_t pad00;
-	uint8_t tcer; /* 0x04 watchdog counter enable reg*/
-	uint8_t pad01[3];
-	uint16_t tcnt; /* 0x08 watchdog timer counter*/
-	uint16_t pad02;
-	uint16_t tcsr; /* 0x0C watchdog timer control reg*/
-	uint16_t pad03;
-};
-
-struct jz4740_uart {
-	uint8_t rbr_thr_dllr;
-		/* 0x00 R  8b receive buffer reg */
-		/* 0x00 W  8b transmit hold reg */
-		/* 0x00 RW 8b divisor latch low reg */
-	uint8_t pad00[3];
-	uint8_t dlhr_ier;
-		/* 0x04 RW 8b divisor latch high reg */
-		/* 0x04 RW 8b interrupt enable reg */
-	uint8_t pad01[3];
-	uint8_t iir_fcr;
-		/* 0x08 R  8b interrupt identification reg */
-		/* 0x08 W  8b FIFO control reg */
-	uint8_t pad02[3];
-	uint8_t lcr;	/* 0x0C RW 8b Line control reg */
-	uint8_t pad03[3];
-	uint8_t mcr;	/* 0x10 RW 8b modem control reg */
-	uint8_t pad04[3];
-	uint8_t lsr;	/* 0x14 R  8b line status reg */
-	uint8_t pad05[3];
-	uint8_t msr;	/* 0x18 R  8b modem status reg */
-	uint8_t pad06[3];
-	uint8_t spr;	/* 0x1C RW 8b scratch pad reg */
-	uint8_t pad07[3];
-	uint8_t isr;	/* 0x20 RW 8b infrared selection reg */
-	uint8_t pad08[3];
-	uint8_t umr;	/* 0x24 RW 8b */
-};
-
-/* MSC */
-struct jz4740_msc {
-	uint16_t strpcl;/* 0x00 */
-	uint32_t stat;	/* 0x04 */
-	uint16_t clkrt;	/* 0x08 */
-	uint32_t cmdat;	/* 0x0C */
-	uint16_t resto;	/* 0x10 */
-	uint16_t rdto;	/* 0x14 */
-	uint16_t blklen;/* 0x18 */
-	uint16_t nob;	/* 0x1C */
-	uint16_t snob;	/* 0x20 */
-	uint16_t imask;	/* 0x24 */
-	uint16_t ireg;	/* 0x28 */
-	uint8_t  cmd;	/* 0x2C */
-	uint32_t arg;	/* 0x30 */
-	uint16_t res;	/* 0x34 */
-	uint32_t rxfifo;/* 0x38 */
-	uint32_t txfifo;/* 0x3C */
-};
-
-/* External Memory Controller */
-struct jz4740_emc {
-	uint32_t bcr; /* 0x00 BCR */
-	uint32_t pad00[3];
-	uint32_t smcr[5];
-		/* x10 Static Memory Control Register 0 */
-		/* x14 Static Memory Control Register 1 */
-		/* x18 Static Memory Control Register 2 */
-		/* x1c Static Memory Control Register 3 */
-		/* x20 Static Memory Control Register 4 */
-	uint32_t pad01[3];
-	uint32_t sacr[5];
-		/* x30 Static Memory Bank 0 Addr Config Reg */
-		/* x34 Static Memory Bank 1 Addr Config Reg */
-		/* x38 Static Memory Bank 2 Addr Config Reg */
-		/* x3c Static Memory Bank 3 Addr Config Reg */
-		/* x40 Static Memory Bank 4 Addr Config Reg */
-	uint32_t pad02[3];
-	uint32_t nfcsr; /* x050 NAND Flash Control/Status Register */
-
-	uint32_t pad03[11];
-	uint32_t dmcr; /* x80 DRAM Control Register */
-	uint16_t rtcsr; /* x84 Refresh Time Control/Status Register */
-	uint16_t pad04;
-	uint16_t rtcnt; /* x88 Refresh Timer Counter */
-	uint16_t pad05;
-	uint16_t rtcor; /* x8c Refresh Time Constant Register */
-	uint16_t pad06;
-	uint32_t dmar0; /* x90 SDRAM Bank 0 Addr Config Register */
-	uint32_t pad07[27];
-	uint32_t nfecr; /* x100 NAND Flash ECC Control Register */
-	uint32_t nfecc; /* x104 NAND Flash ECC Data Register */
-	uint8_t nfpar[12];
-		/* x108 NAND Flash RS Parity 0 Register */
-		/* x10c NAND Flash RS Parity 1 Register */
-		/* x110 NAND Flash RS Parity 2 Register */
-	uint32_t nfints; /* x114 NAND Flash Interrupt Status Register */
-	uint32_t nfinte; /* x118 NAND Flash Interrupt Enable Register */
-	uint32_t nferr[4];
-		/* x11c NAND Flash RS Error Report 0 Register */
-		/* x120 NAND Flash RS Error Report 1 Register */
-		/* x124 NAND Flash RS Error Report 2 Register */
-		/* x128 NAND Flash RS Error Report 3 Register */
-};
-
-#define __gpio_as_nand()			\
-do {						\
-	writel(0x02018000, GPIO_PXFUNS(1));	\
-	writel(0x02018000, GPIO_PXSELC(1));	\
-	writel(0x02018000, GPIO_PXPES(1));	\
-	writel(0x30000000, GPIO_PXFUNS(2));	\
-	writel(0x30000000, GPIO_PXSELC(2));	\
-	writel(0x30000000, GPIO_PXPES(2));	\
-	writel(0x40000000, GPIO_PXFUNC(2));	\
-	writel(0x40000000, GPIO_PXSELC(2));	\
-	writel(0x40000000, GPIO_PXDIRC(2));	\
-	writel(0x40000000, GPIO_PXPES(2));	\
-	writel(0x00400000, GPIO_PXFUNS(1));	\
-	writel(0x00400000, GPIO_PXSELC(1));	\
-} while (0)
-
-#define __gpio_as_sdram_16bit_4720()		\
-do {						\
-	writel(0x5442bfaa, GPIO_PXFUNS(0));	\
-	writel(0x5442bfaa, GPIO_PXSELC(0));	\
-	writel(0x5442bfaa, GPIO_PXPES(0));	\
-	writel(0x81f9ffff, GPIO_PXFUNS(1));	\
-	writel(0x81f9ffff, GPIO_PXSELC(1));	\
-	writel(0x81f9ffff, GPIO_PXPES(1));	\
-	writel(0x01000000, GPIO_PXFUNS(2));	\
-	writel(0x01000000, GPIO_PXSELC(2));	\
-	writel(0x01000000, GPIO_PXPES(2));	\
-} while (0)
-
-#define __gpio_as_lcd_18bit()			\
-do {						\
-	writel(0x003fffff, GPIO_PXFUNS(2));	\
-	writel(0x003fffff, GPIO_PXSELC(2));	\
-	writel(0x003fffff, GPIO_PXPES(2));	\
-} while (0)
-
-/* MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 */
-#define __gpio_as_msc()				\
-do {						\
-	writel(0x00003f00, GPIO_PXFUNS(3));	\
-	writel(0x00003f00, GPIO_PXSELC(3));	\
-	writel(0x00003f00, GPIO_PXPES(3));	\
-} while (0)
-
-#define __gpio_get_port(p)	(readl(GPIO_PXPIN(p)))
-
-#define __gpio_disable_pull(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel((1 << o), GPIO_PXPES(p));	\
-} while (0)
-
-#define __gpio_enable_pull(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel(1 << (o), GPIO_PXPEC(p));	\
-} while (0)
-
-#define __gpio_port_as_output(p, o)		\
-do {						\
-	writel(1 << (o), GPIO_PXFUNC(p));	\
-	writel(1 << (o), GPIO_PXSELC(p));	\
-	writel(1 << (o), GPIO_PXDIRS(p));	\
-} while (0)
-
-#define __gpio_port_as_input(p, o)		\
-do {						\
-	writel(1 << (o), GPIO_PXFUNC(p));	\
-	writel(1 << (o), GPIO_PXSELC(p));	\
-	writel(1 << (o), GPIO_PXDIRC(p));	\
-} while (0)
-
-#define __gpio_as_output(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	__gpio_port_as_output(p, o);		\
-} while (0)
-
-#define __gpio_as_input(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	__gpio_port_as_input(p, o);		\
-} while (0)
-
-#define __gpio_set_pin(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel((1 << o), GPIO_PXDATS(p));	\
-} while (0)
-
-#define __gpio_clear_pin(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel((1 << o), GPIO_PXDATC(p));	\
-} while (0)
-
-#define __gpio_get_pin(n)			\
-({						\
-	unsigned int p, o, v;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	if (__gpio_get_port(p) & (1 << o))	\
-		v = 1;				\
-	else					\
-		v = 0;				\
-	v;					\
-})
-
-#define __gpio_as_uart0()			\
-do {						\
-	writel(0x06000000, GPIO_PXFUNS(3));	\
-	writel(0x06000000, GPIO_PXSELS(3));	\
-	writel(0x06000000, GPIO_PXPES(3));	\
-} while (0)
-
-#define __gpio_jtag_to_uart0()			\
-do {						\
-	writel(0x80000000, GPIO_PXSELS(2));	\
-} while (0)
-
-/* Clock Control Register */
-#define __cpm_get_pllm()					\
-	((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLM_MASK)	\
-	 >> CPM_CPPCR_PLLM_BIT)
-#define __cpm_get_plln()					\
-	((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLN_MASK)	\
-	 >> CPM_CPPCR_PLLN_BIT)
-#define __cpm_get_pllod()					\
-	((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLOD_MASK)	\
-	 >> CPM_CPPCR_PLLOD_BIT)
-#define __cpm_get_hdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_HDIV_MASK)	\
-	 >> CPM_CPCCR_HDIV_BIT)
-#define __cpm_get_pdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_PDIV_MASK)	\
-	 >> CPM_CPCCR_PDIV_BIT)
-#define __cpm_get_cdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_CDIV_MASK)	\
-	 >> CPM_CPCCR_CDIV_BIT)
-#define __cpm_get_mdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_MDIV_MASK)	\
-	 >> CPM_CPCCR_MDIV_BIT)
-
-static inline unsigned int __cpm_get_pllout(void)
-{
-	uint32_t m, n, no, pllout;
-	uint32_t od[4] = {1, 2, 2, 4};
-
-	struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
-	uint32_t cppcr = readl(&cpm->cppcr);
-
-	if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
-		m = __cpm_get_pllm() + 2;
-		n = __cpm_get_plln() + 2;
-		no = od[__cpm_get_pllod()];
-		pllout = (CONFIG_SYS_EXTAL / (n * no)) * m;
-	} else
-		pllout = CONFIG_SYS_EXTAL;
-
-	return pllout;
-}
-
-extern void pll_init(void);
-extern void sdram_init(void);
-extern void calc_clocks(void);
-extern void rtc_init(void);
-
-#endif	/* !__ASSEMBLY__ */
-#endif	/* __JZ4740_H__ */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/malta.h b/qemu/roms/u-boot/arch/mips/include/asm/malta.h
deleted file mode 100644
index 9e7c045aa..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/malta.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2013 Imagination Technologies
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef _MIPS_ASM_MALTA_H
-#define _MIPS_ASM_MALTA_H
-
-#define MALTA_GT_BASE			0x1be00000
-#define MALTA_GT_PCIIO_BASE		0x18000000
-#define MALTA_GT_UART0_BASE		(MALTA_GT_PCIIO_BASE + 0x3f8)
-
-#define MALTA_MSC01_BIU_BASE		0x1bc80000
-#define MALTA_MSC01_PCI_BASE		0x1bd00000
-#define MALTA_MSC01_PBC_BASE		0x1bd40000
-#define MALTA_MSC01_IP1_BASE		0x1bc00000
-#define MALTA_MSC01_IP1_SIZE		0x00400000
-#define MALTA_MSC01_IP2_BASE1		0x10000000
-#define MALTA_MSC01_IP2_SIZE1		0x08000000
-#define MALTA_MSC01_IP2_BASE2		0x18000000
-#define MALTA_MSC01_IP2_SIZE2		0x04000000
-#define MALTA_MSC01_IP3_BASE		0x1c000000
-#define MALTA_MSC01_IP3_SIZE		0x04000000
-#define MALTA_MSC01_PCIMEM_BASE		0x10000000
-#define MALTA_MSC01_PCIMEM_SIZE		0x10000000
-#define MALTA_MSC01_PCIMEM_MAP		0x10000000
-#define MALTA_MSC01_PCIIO_BASE		0x1b000000
-#define MALTA_MSC01_PCIIO_SIZE		0x00800000
-#define MALTA_MSC01_PCIIO_MAP		0x00000000
-#define MALTA_MSC01_UART0_BASE		(MALTA_MSC01_PCIIO_BASE + 0x3f8)
-
-#define MALTA_ASCIIWORD			0x1f000410
-#define MALTA_ASCIIPOS0			0x1f000418
-#define MALTA_ASCIIPOS1			0x1f000420
-#define MALTA_ASCIIPOS2			0x1f000428
-#define MALTA_ASCIIPOS3			0x1f000430
-#define MALTA_ASCIIPOS4			0x1f000438
-#define MALTA_ASCIIPOS5			0x1f000440
-#define MALTA_ASCIIPOS6			0x1f000448
-#define MALTA_ASCIIPOS7			0x1f000450
-
-#define MALTA_RESET_BASE		0x1f000500
-#define GORESET				0x42
-
-#define MALTA_FLASH_BASE		0x1e000000
-
-#define MALTA_REVISION			0x1fc00010
-#define MALTA_REVISION_CORID_SHF	10
-#define MALTA_REVISION_CORID_MSK	(0x3f << MALTA_REVISION_CORID_SHF)
-#define MALTA_REVISION_CORID_CORE_LV		1
-#define MALTA_REVISION_CORID_CORE_FPGA6		14
-
-#define PCI_CFG_PIIX4_PIRQRCA		0x60
-#define PCI_CFG_PIIX4_PIRQRCB		0x61
-#define PCI_CFG_PIIX4_PIRQRCC		0x62
-#define PCI_CFG_PIIX4_PIRQRCD		0x63
-#define PCI_CFG_PIIX4_SERIRQC		0x64
-#define PCI_CFG_PIIX4_GENCFG		0xb0
-
-#define PCI_CFG_PIIX4_SERIRQC_EN	(1 << 7)
-#define PCI_CFG_PIIX4_SERIRQC_CONT	(1 << 6)
-
-#define PCI_CFG_PIIX4_GENCFG_SERIRQ	(1 << 16)
-
-#endif /* _MIPS_ASM_MALTA_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/mipsregs.h b/qemu/roms/u-boot/arch/mips/include/asm/mipsregs.h
deleted file mode 100644
index 3571e4fdf..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/mipsregs.h
+++ /dev/null
@@ -1,1370 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Modified for further R[236]000 support by Paul M. Antoine, 1996.
- * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- * Copyright (C) 2003, 2004  Maciej W. Rozycki
- */
-#ifndef _ASM_MIPSREGS_H
-#define _ASM_MIPSREGS_H
-
-#if 0
-#include <linux/linkage.h>
-#endif
-
-/*
- * The following macros are especially useful for __asm__
- * inline assembler.
- */
-#ifndef __STR
-#define __STR(x) #x
-#endif
-#ifndef STR
-#define STR(x) __STR(x)
-#endif
-
-/*
- *  Configure language
- */
-#ifdef __ASSEMBLY__
-#define _ULCAST_
-#else
-#define _ULCAST_ (unsigned long)
-#endif
-
-/*
- * Coprocessor 0 register names
- */
-#define CP0_INDEX $0
-#define CP0_RANDOM $1
-#define CP0_ENTRYLO0 $2
-#define CP0_ENTRYLO1 $3
-#define CP0_CONF $3
-#define CP0_CONTEXT $4
-#define CP0_PAGEMASK $5
-#define CP0_WIRED $6
-#define CP0_INFO $7
-#define CP0_BADVADDR $8
-#define CP0_COUNT $9
-#define CP0_ENTRYHI $10
-#define CP0_COMPARE $11
-#define CP0_STATUS $12
-#define CP0_CAUSE $13
-#define CP0_EPC $14
-#define CP0_PRID $15
-#define CP0_CONFIG $16
-#define CP0_LLADDR $17
-#define CP0_WATCHLO $18
-#define CP0_WATCHHI $19
-#define CP0_XCONTEXT $20
-#define CP0_FRAMEMASK $21
-#define CP0_DIAGNOSTIC $22
-#define CP0_DEBUG $23
-#define CP0_DEPC $24
-#define CP0_PERFORMANCE $25
-#define CP0_ECC $26
-#define CP0_CACHEERR $27
-#define CP0_TAGLO $28
-#define CP0_TAGHI $29
-#define CP0_ERROREPC $30
-#define CP0_DESAVE $31
-
-/*
- * R4640/R4650 cp0 register names.  These registers are listed
- * here only for completeness; without MMU these CPUs are not useable
- * by Linux.  A future ELKS port might take make Linux run on them
- * though ...
- */
-#define CP0_IBASE $0
-#define CP0_IBOUND $1
-#define CP0_DBASE $2
-#define CP0_DBOUND $3
-#define CP0_CALG $17
-#define CP0_IWATCH $18
-#define CP0_DWATCH $19
-
-/*
- * Coprocessor 0 Set 1 register names
- */
-#define CP0_S1_DERRADDR0  $26
-#define CP0_S1_DERRADDR1  $27
-#define CP0_S1_INTCONTROL $20
-
-/*
- * Coprocessor 0 Set 2 register names
- */
-#define CP0_S2_SRSCTL	$12	/* MIPSR2 */
-
-/*
- * Coprocessor 0 Set 3 register names
- */
-#define CP0_S3_SRSMAP	$12	/* MIPSR2 */
-
-/*
- *  TX39 Series
- */
-#define CP0_TX39_CACHE	$7
-
-/*
- * Coprocessor 1 (FPU) register names
- */
-#define CP1_REVISION	$0
-#define CP1_STATUS	$31
-
-/*
- * FPU Status Register Values
- */
-/*
- * Status Register Values
- */
-
-#define FPU_CSR_FLUSH	0x01000000	/* flush denormalised results to 0 */
-#define FPU_CSR_COND	0x00800000	/* $fcc0 */
-#define FPU_CSR_COND0	0x00800000	/* $fcc0 */
-#define FPU_CSR_COND1	0x02000000	/* $fcc1 */
-#define FPU_CSR_COND2	0x04000000	/* $fcc2 */
-#define FPU_CSR_COND3	0x08000000	/* $fcc3 */
-#define FPU_CSR_COND4	0x10000000	/* $fcc4 */
-#define FPU_CSR_COND5	0x20000000	/* $fcc5 */
-#define FPU_CSR_COND6	0x40000000	/* $fcc6 */
-#define FPU_CSR_COND7	0x80000000	/* $fcc7 */
-
-/*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
- */
-#define FPU_CSR_ALL_X	0x0003f000
-#define FPU_CSR_UNI_X	0x00020000
-#define FPU_CSR_INV_X	0x00010000
-#define FPU_CSR_DIV_X	0x00008000
-#define FPU_CSR_OVF_X	0x00004000
-#define FPU_CSR_UDF_X	0x00002000
-#define FPU_CSR_INE_X	0x00001000
-
-#define FPU_CSR_ALL_E	0x00000f80
-#define FPU_CSR_INV_E	0x00000800
-#define FPU_CSR_DIV_E	0x00000400
-#define FPU_CSR_OVF_E	0x00000200
-#define FPU_CSR_UDF_E	0x00000100
-#define FPU_CSR_INE_E	0x00000080
-
-#define FPU_CSR_ALL_S	0x0000007c
-#define FPU_CSR_INV_S	0x00000040
-#define FPU_CSR_DIV_S	0x00000020
-#define FPU_CSR_OVF_S	0x00000010
-#define FPU_CSR_UDF_S	0x00000008
-#define FPU_CSR_INE_S	0x00000004
-
-/* rounding mode */
-#define FPU_CSR_RN	0x0	/* nearest */
-#define FPU_CSR_RZ	0x1	/* towards zero */
-#define FPU_CSR_RU	0x2	/* towards +Infinity */
-#define FPU_CSR_RD	0x3	/* towards -Infinity */
-
-/*
- * Values for PageMask register
- */
-#ifdef CONFIG_CPU_VR41XX
-
-/* Why doesn't stupidity hurt ... */
-
-#define PM_1K		0x00000000
-#define PM_4K		0x00001800
-#define PM_16K		0x00007800
-#define PM_64K		0x0001f800
-#define PM_256K		0x0007f800
-
-#else
-
-#define PM_4K		0x00000000
-#define PM_16K		0x00006000
-#define PM_64K		0x0001e000
-#define PM_256K		0x0007e000
-#define PM_1M		0x001fe000
-#define PM_4M		0x007fe000
-#define PM_16M		0x01ffe000
-#define PM_64M		0x07ffe000
-#define PM_256M		0x1fffe000
-
-#endif
-
-/*
- * Values used for computation of new tlb entries
- */
-#define PL_4K		12
-#define PL_16K		14
-#define PL_64K		16
-#define PL_256K		18
-#define PL_1M		20
-#define PL_4M		22
-#define PL_16M		24
-#define PL_64M		26
-#define PL_256M		28
-
-/*
- * R4x00 interrupt enable / cause bits
- */
-#define IE_SW0		(_ULCAST_(1) <<  8)
-#define IE_SW1		(_ULCAST_(1) <<  9)
-#define IE_IRQ0		(_ULCAST_(1) << 10)
-#define IE_IRQ1		(_ULCAST_(1) << 11)
-#define IE_IRQ2		(_ULCAST_(1) << 12)
-#define IE_IRQ3		(_ULCAST_(1) << 13)
-#define IE_IRQ4		(_ULCAST_(1) << 14)
-#define IE_IRQ5		(_ULCAST_(1) << 15)
-
-/*
- * R4x00 interrupt cause bits
- */
-#define C_SW0		(_ULCAST_(1) <<  8)
-#define C_SW1		(_ULCAST_(1) <<  9)
-#define C_IRQ0		(_ULCAST_(1) << 10)
-#define C_IRQ1		(_ULCAST_(1) << 11)
-#define C_IRQ2		(_ULCAST_(1) << 12)
-#define C_IRQ3		(_ULCAST_(1) << 13)
-#define C_IRQ4		(_ULCAST_(1) << 14)
-#define C_IRQ5		(_ULCAST_(1) << 15)
-
-/*
- * Bitfields in the R4xx0 cp0 status register
- */
-#define ST0_IE			0x00000001
-#define ST0_EXL			0x00000002
-#define ST0_ERL			0x00000004
-#define ST0_KSU			0x00000018
-#  define KSU_USER		0x00000010
-#  define KSU_SUPERVISOR	0x00000008
-#  define KSU_KERNEL		0x00000000
-#define ST0_UX			0x00000020
-#define ST0_SX			0x00000040
-#define ST0_KX			0x00000080
-#define ST0_DE			0x00010000
-#define ST0_CE			0x00020000
-
-/*
- * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
- * cacheops in userspace.  This bit exists only on RM7000 and RM9000
- * processors.
- */
-#define ST0_CO			0x08000000
-
-/*
- * Bitfields in the R[23]000 cp0 status register.
- */
-#define ST0_IEC			0x00000001
-#define ST0_KUC			0x00000002
-#define ST0_IEP			0x00000004
-#define ST0_KUP			0x00000008
-#define ST0_IEO			0x00000010
-#define ST0_KUO			0x00000020
-/* bits 6 & 7 are reserved on R[23]000 */
-#define ST0_ISC			0x00010000
-#define ST0_SWC			0x00020000
-#define ST0_CM			0x00080000
-
-/*
- * Bits specific to the R4640/R4650
- */
-#define ST0_UM			(_ULCAST_(1) <<  4)
-#define ST0_IL			(_ULCAST_(1) << 23)
-#define ST0_DL			(_ULCAST_(1) << 24)
-
-/*
- * Enable the MIPS MDMX and DSP ASEs
- */
-#define ST0_MX			0x01000000
-
-/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT	19
-#define TX39_CONF_ICS_MASK	0x00380000
-#define TX39_CONF_ICS_1KB	0x00000000
-#define TX39_CONF_ICS_2KB	0x00080000
-#define TX39_CONF_ICS_4KB	0x00100000
-#define TX39_CONF_ICS_8KB	0x00180000
-#define TX39_CONF_ICS_16KB	0x00200000
-
-#define TX39_CONF_DCS_SHIFT	16
-#define TX39_CONF_DCS_MASK	0x00070000
-#define TX39_CONF_DCS_1KB	0x00000000
-#define TX39_CONF_DCS_2KB	0x00010000
-#define TX39_CONF_DCS_4KB	0x00020000
-#define TX39_CONF_DCS_8KB	0x00030000
-#define TX39_CONF_DCS_16KB	0x00040000
-
-#define TX39_CONF_CWFON		0x00004000
-#define TX39_CONF_WBON		0x00002000
-#define TX39_CONF_RF_SHIFT	10
-#define TX39_CONF_RF_MASK	0x00000c00
-#define TX39_CONF_DOZE		0x00000200
-#define TX39_CONF_HALT		0x00000100
-#define TX39_CONF_LOCK		0x00000080
-#define TX39_CONF_ICE		0x00000020
-#define TX39_CONF_DCE		0x00000010
-#define TX39_CONF_IRSIZE_SHIFT	2
-#define TX39_CONF_IRSIZE_MASK	0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT	0
-#define TX39_CONF_DRSIZE_MASK	0x00000003
-
-/*
- * Status register bits available in all MIPS CPUs.
- */
-#define ST0_IM			0x0000ff00
-#define  STATUSB_IP0		8
-#define  STATUSF_IP0		(_ULCAST_(1) <<  8)
-#define  STATUSB_IP1		9
-#define  STATUSF_IP1		(_ULCAST_(1) <<  9)
-#define  STATUSB_IP2		10
-#define  STATUSF_IP2		(_ULCAST_(1) << 10)
-#define  STATUSB_IP3		11
-#define  STATUSF_IP3		(_ULCAST_(1) << 11)
-#define  STATUSB_IP4		12
-#define  STATUSF_IP4		(_ULCAST_(1) << 12)
-#define  STATUSB_IP5		13
-#define  STATUSF_IP5		(_ULCAST_(1) << 13)
-#define  STATUSB_IP6		14
-#define  STATUSF_IP6		(_ULCAST_(1) << 14)
-#define  STATUSB_IP7		15
-#define  STATUSF_IP7		(_ULCAST_(1) << 15)
-#define  STATUSB_IP8		0
-#define  STATUSF_IP8		(_ULCAST_(1) <<  0)
-#define  STATUSB_IP9		1
-#define  STATUSF_IP9		(_ULCAST_(1) <<  1)
-#define  STATUSB_IP10		2
-#define  STATUSF_IP10		(_ULCAST_(1) <<  2)
-#define  STATUSB_IP11		3
-#define  STATUSF_IP11		(_ULCAST_(1) <<  3)
-#define  STATUSB_IP12		4
-#define  STATUSF_IP12		(_ULCAST_(1) <<  4)
-#define  STATUSB_IP13		5
-#define  STATUSF_IP13		(_ULCAST_(1) <<  5)
-#define  STATUSB_IP14		6
-#define  STATUSF_IP14		(_ULCAST_(1) <<  6)
-#define  STATUSB_IP15		7
-#define  STATUSF_IP15		(_ULCAST_(1) <<  7)
-#define ST0_CH			0x00040000
-#define ST0_SR			0x00100000
-#define ST0_TS			0x00200000
-#define ST0_BEV			0x00400000
-#define ST0_RE			0x02000000
-#define ST0_FR			0x04000000
-#define ST0_CU			0xf0000000
-#define ST0_CU0			0x10000000
-#define ST0_CU1			0x20000000
-#define ST0_CU2			0x40000000
-#define ST0_CU3			0x80000000
-#define ST0_XX			0x80000000	/* MIPS IV naming */
-
-/*
- * Bitfields and bit numbers in the coprocessor 0 cause register.
- *
- * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
- */
-#define  CAUSEB_EXCCODE		2
-#define  CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
-#define  CAUSEB_IP		8
-#define  CAUSEF_IP		(_ULCAST_(255) <<  8)
-#define  CAUSEB_IP0		8
-#define  CAUSEF_IP0		(_ULCAST_(1)   <<  8)
-#define  CAUSEB_IP1		9
-#define  CAUSEF_IP1		(_ULCAST_(1)   <<  9)
-#define  CAUSEB_IP2		10
-#define  CAUSEF_IP2		(_ULCAST_(1)   << 10)
-#define  CAUSEB_IP3		11
-#define  CAUSEF_IP3		(_ULCAST_(1)   << 11)
-#define  CAUSEB_IP4		12
-#define  CAUSEF_IP4		(_ULCAST_(1)   << 12)
-#define  CAUSEB_IP5		13
-#define  CAUSEF_IP5		(_ULCAST_(1)   << 13)
-#define  CAUSEB_IP6		14
-#define  CAUSEF_IP6		(_ULCAST_(1)   << 14)
-#define  CAUSEB_IP7		15
-#define  CAUSEF_IP7		(_ULCAST_(1)   << 15)
-#define  CAUSEB_IV		23
-#define  CAUSEF_IV		(_ULCAST_(1)   << 23)
-#define  CAUSEB_CE		28
-#define  CAUSEF_CE		(_ULCAST_(3)   << 28)
-#define  CAUSEB_BD		31
-#define  CAUSEF_BD		(_ULCAST_(1)   << 31)
-
-/*
- * Bits in the coprocessor 0 config register.
- */
-/* Generic bits.  */
-#define CONF_CM_CACHABLE_NO_WA		0
-#define CONF_CM_CACHABLE_WA		1
-#define CONF_CM_UNCACHED		2
-#define CONF_CM_CACHABLE_NONCOHERENT	3
-#define CONF_CM_CACHABLE_CE		4
-#define CONF_CM_CACHABLE_COW		5
-#define CONF_CM_CACHABLE_CUW		6
-#define CONF_CM_CACHABLE_ACCELERATED	7
-#define CONF_CM_CMASK			7
-#define CONF_BE			(_ULCAST_(1) << 15)
-
-/* Bits common to various processors.  */
-#define CONF_CU			(_ULCAST_(1) <<  3)
-#define CONF_DB			(_ULCAST_(1) <<  4)
-#define CONF_IB			(_ULCAST_(1) <<  5)
-#define CONF_DC			(_ULCAST_(7) <<  6)
-#define CONF_IC			(_ULCAST_(7) <<  9)
-#define CONF_EB			(_ULCAST_(1) << 13)
-#define CONF_EM			(_ULCAST_(1) << 14)
-#define CONF_SM			(_ULCAST_(1) << 16)
-#define CONF_SC			(_ULCAST_(1) << 17)
-#define CONF_EW			(_ULCAST_(3) << 18)
-#define CONF_EP			(_ULCAST_(15)<< 24)
-#define CONF_EC			(_ULCAST_(7) << 28)
-#define CONF_CM			(_ULCAST_(1) << 31)
-
-/* Bits specific to the R4xx0.  */
-#define R4K_CONF_SW		(_ULCAST_(1) << 20)
-#define R4K_CONF_SS		(_ULCAST_(1) << 21)
-#define R4K_CONF_SB		(_ULCAST_(3) << 22)
-
-/* Bits specific to the R5000.  */
-#define R5K_CONF_SE		(_ULCAST_(1) << 12)
-#define R5K_CONF_SS		(_ULCAST_(3) << 20)
-
-/* Bits specific to the RM7000.  */
-#define RM7K_CONF_SE		(_ULCAST_(1) <<  3)
-#define RM7K_CONF_TE		(_ULCAST_(1) << 12)
-#define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
-#define RM7K_CONF_TC		(_ULCAST_(1) << 17)
-#define RM7K_CONF_SI		(_ULCAST_(3) << 20)
-#define RM7K_CONF_SC		(_ULCAST_(1) << 31)
-
-/* Bits specific to the R10000.  */
-#define R10K_CONF_DN		(_ULCAST_(3) <<  3)
-#define R10K_CONF_CT		(_ULCAST_(1) <<  5)
-#define R10K_CONF_PE		(_ULCAST_(1) <<  6)
-#define R10K_CONF_PM		(_ULCAST_(3) <<  7)
-#define R10K_CONF_EC		(_ULCAST_(15)<<  9)
-#define R10K_CONF_SB		(_ULCAST_(1) << 13)
-#define R10K_CONF_SK		(_ULCAST_(1) << 14)
-#define R10K_CONF_SS		(_ULCAST_(7) << 16)
-#define R10K_CONF_SC		(_ULCAST_(7) << 19)
-#define R10K_CONF_DC		(_ULCAST_(7) << 26)
-#define R10K_CONF_IC		(_ULCAST_(7) << 29)
-
-/* Bits specific to the VR41xx.  */
-#define VR41_CONF_CS		(_ULCAST_(1) << 12)
-#define VR41_CONF_P4K		(_ULCAST_(1) << 13)
-#define VR41_CONF_BP		(_ULCAST_(1) << 16)
-#define VR41_CONF_M16		(_ULCAST_(1) << 20)
-#define VR41_CONF_AD		(_ULCAST_(1) << 23)
-
-/* Bits specific to the R30xx.  */
-#define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
-#define R30XX_CONF_REV		(_ULCAST_(1) << 22)
-#define R30XX_CONF_AC		(_ULCAST_(1) << 23)
-#define R30XX_CONF_RF		(_ULCAST_(1) << 24)
-#define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
-#define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
-#define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
-#define R30XX_CONF_SB		(_ULCAST_(1) << 30)
-#define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
-
-/* Bits specific to the TX49.  */
-#define TX49_CONF_DC		(_ULCAST_(1) << 16)
-#define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
-#define TX49_CONF_HALT		(_ULCAST_(1) << 18)
-#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
-
-/* Bits specific to the MIPS32/64 PRA.  */
-#define MIPS_CONF_MT		(_ULCAST_(7) <<  7)
-#define MIPS_CONF_AR		(_ULCAST_(7) << 10)
-#define MIPS_CONF_AT		(_ULCAST_(3) << 13)
-#define MIPS_CONF_M		(_ULCAST_(1) << 31)
-
-/*
- * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
- */
-#define MIPS_CONF1_FP		(_ULCAST_(1) <<  0)
-#define MIPS_CONF1_EP		(_ULCAST_(1) <<  1)
-#define MIPS_CONF1_CA		(_ULCAST_(1) <<  2)
-#define MIPS_CONF1_WR		(_ULCAST_(1) <<  3)
-#define MIPS_CONF1_PC		(_ULCAST_(1) <<  4)
-#define MIPS_CONF1_MD		(_ULCAST_(1) <<  5)
-#define MIPS_CONF1_C2		(_ULCAST_(1) <<  6)
-#define MIPS_CONF1_DA_SHIFT	7
-#define MIPS_CONF1_DA		(_ULCAST_(7) <<  7)
-#define MIPS_CONF1_DL_SHIFT	10
-#define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
-#define MIPS_CONF1_DS_SHIFT	13
-#define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
-#define MIPS_CONF1_IA_SHIFT	16
-#define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
-#define MIPS_CONF1_IL_SHIFT	19
-#define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
-#define MIPS_CONF1_IS_SHIFT	22
-#define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
-#define MIPS_CONF1_TLBS		(_ULCAST_(63)<< 25)
-
-#define MIPS_CONF2_SA		(_ULCAST_(15)<<  0)
-#define MIPS_CONF2_SL		(_ULCAST_(15)<<  4)
-#define MIPS_CONF2_SS		(_ULCAST_(15)<<  8)
-#define MIPS_CONF2_SU		(_ULCAST_(15)<< 12)
-#define MIPS_CONF2_TA		(_ULCAST_(15)<< 16)
-#define MIPS_CONF2_TL		(_ULCAST_(15)<< 20)
-#define MIPS_CONF2_TS		(_ULCAST_(15)<< 24)
-#define MIPS_CONF2_TU		(_ULCAST_(7) << 28)
-
-#define MIPS_CONF3_TL		(_ULCAST_(1) <<  0)
-#define MIPS_CONF3_SM		(_ULCAST_(1) <<  1)
-#define MIPS_CONF3_MT		(_ULCAST_(1) <<  2)
-#define MIPS_CONF3_SP		(_ULCAST_(1) <<  4)
-#define MIPS_CONF3_VINT		(_ULCAST_(1) <<  5)
-#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<  6)
-#define MIPS_CONF3_LPA		(_ULCAST_(1) <<  7)
-#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
-#define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
-
-#define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
-
-#define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
-
-/*
- * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
- */
-#define MIPS_FPIR_S		(_ULCAST_(1) << 16)
-#define MIPS_FPIR_D		(_ULCAST_(1) << 17)
-#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
-#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
-#define MIPS_FPIR_W		(_ULCAST_(1) << 20)
-#define MIPS_FPIR_L		(_ULCAST_(1) << 21)
-#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
-
-#ifndef __ASSEMBLY__
-
-/*
- * Functions to access the R10000 performance counters.  These are basically
- * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
- * performance counter number encoded into bits 1 ... 5 of the instruction.
- * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
- * disassembler these will look like an access to sel 0 or 1.
- */
-#define read_r10k_perf_cntr(counter)				\
-({								\
-	unsigned int __res;					\
-	__asm__ __volatile__(					\
-	"mfpc\t%0, %1"						\
-	: "=r" (__res)						\
-	: "i" (counter));					\
-								\
-	__res;							\
-})
-
-#define write_r10k_perf_cntr(counter,val)			\
-do {								\
-	__asm__ __volatile__(					\
-	"mtpc\t%0, %1"						\
-	:							\
-	: "r" (val), "i" (counter));				\
-} while (0)
-
-#define read_r10k_perf_event(counter)				\
-({								\
-	unsigned int __res;					\
-	__asm__ __volatile__(					\
-	"mfps\t%0, %1"						\
-	: "=r" (__res)						\
-	: "i" (counter));					\
-								\
-	__res;							\
-})
-
-#define write_r10k_perf_cntl(counter,val)			\
-do {								\
-	__asm__ __volatile__(					\
-	"mtps\t%0, %1"						\
-	:							\
-	: "r" (val), "i" (counter));				\
-} while (0)
-
-/*
- * Macros to access the system control coprocessor
- */
-
-#define __read_32bit_c0_register(source, sel)				\
-({ int __res;								\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mfc0\t%0, " #source "\n\t"			\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mfc0\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0\n\t"				\
-			: "=r" (__res));				\
-	__res;								\
-})
-
-#define __read_64bit_c0_register(source, sel)				\
-({ unsigned long long __res;						\
-	if (sizeof(unsigned long) == 4)					\
-		__res = __read_64bit_c0_split(source, sel);		\
-	else if (sel == 0)						\
-		__asm__ __volatile__(					\
-			".set\tmips3\n\t"				\
-			"dmfc0\t%0, " #source "\n\t"			\
-			".set\tmips0"					\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0"					\
-			: "=r" (__res));				\
-	__res;								\
-})
-
-#define __write_32bit_c0_register(register, sel, value)			\
-do {									\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mtc0\t%z0, " #register "\n\t"			\
-			: : "Jr" ((unsigned int)(value)));		\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
-			".set\tmips0"					\
-			: : "Jr" ((unsigned int)(value)));		\
-} while (0)
-
-#define __write_64bit_c0_register(register, sel, value)			\
-do {									\
-	if (sizeof(unsigned long) == 4)					\
-		__write_64bit_c0_split(register, sel, value);		\
-	else if (sel == 0)						\
-		__asm__ __volatile__(					\
-			".set\tmips3\n\t"				\
-			"dmtc0\t%z0, " #register "\n\t"			\
-			".set\tmips0"					\
-			: : "Jr" (value));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
-			".set\tmips0"					\
-			: : "Jr" (value));				\
-} while (0)
-
-#define __read_ulong_c0_register(reg, sel)				\
-	((sizeof(unsigned long) == 4) ?					\
-	(unsigned long) __read_32bit_c0_register(reg, sel) :		\
-	(unsigned long) __read_64bit_c0_register(reg, sel))
-
-#define __write_ulong_c0_register(reg, sel, val)			\
-do {									\
-	if (sizeof(unsigned long) == 4)					\
-		__write_32bit_c0_register(reg, sel, val);		\
-	else								\
-		__write_64bit_c0_register(reg, sel, val);		\
-} while (0)
-
-/*
- * On RM7000/RM9000 these are uses to access cop0 set 1 registers
- */
-#define __read_32bit_c0_ctrl_register(source)				\
-({ int __res;								\
-	__asm__ __volatile__(						\
-		"cfc0\t%0, " #source "\n\t"				\
-		: "=r" (__res));					\
-	__res;								\
-})
-
-#define __write_32bit_c0_ctrl_register(register, value)			\
-do {									\
-	__asm__ __volatile__(						\
-		"ctc0\t%z0, " #register "\n\t"				\
-		: : "Jr" ((unsigned int)(value)));			\
-} while (0)
-
-/*
- * These versions are only needed for systems with more than 38 bits of
- * physical address space running the 32-bit kernel.  That's none atm :-)
- */
-#define __read_64bit_c0_split(source, sel)				\
-({									\
-	unsigned long long __val;					\
-	unsigned long __flags;						\
-									\
-	local_irq_save(__flags);					\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc0\t%M0, " #source "\n\t"			\
-			"dsll\t%L0, %M0, 32\n\t"			\
-			"dsrl\t%M0, %M0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			".set\tmips0"					\
-			: "=r" (__val));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc0\t%M0, " #source ", " #sel "\n\t"		\
-			"dsll\t%L0, %M0, 32\n\t"			\
-			"dsrl\t%M0, %M0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			".set\tmips0"					\
-			: "=r" (__val));				\
-	local_irq_restore(__flags);					\
-									\
-	__val;								\
-})
-
-#define __write_64bit_c0_split(source, sel, val)			\
-do {									\
-	unsigned long __flags;						\
-									\
-	local_irq_save(__flags);					\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
-			"or\t%L0, %L0, %M0\n\t"				\
-			"dmtc0\t%L0, " #source "\n\t"			\
-			".set\tmips0"					\
-			: : "r" (val));					\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
-			"or\t%L0, %L0, %M0\n\t"				\
-			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
-			".set\tmips0"					\
-			: : "r" (val));					\
-	local_irq_restore(__flags);					\
-} while (0)
-
-#define read_c0_index()		__read_32bit_c0_register($0, 0)
-#define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)
-
-#define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
-#define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)
-
-#define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
-#define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)
-
-#define read_c0_conf()		__read_32bit_c0_register($3, 0)
-#define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)
-
-#define read_c0_context()	__read_ulong_c0_register($4, 0)
-#define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)
-
-#define read_c0_userlocal()	__read_ulong_c0_register($4, 2)
-#define write_c0_userlocal(val)	__write_ulong_c0_register($4, 2, val)
-
-#define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
-#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
-
-#define read_c0_wired()		__read_32bit_c0_register($6, 0)
-#define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
-
-#define read_c0_info()		__read_32bit_c0_register($7, 0)
-
-#define read_c0_cache()		__read_32bit_c0_register($7, 0)	/* TX39xx */
-#define write_c0_cache(val)	__write_32bit_c0_register($7, 0, val)
-
-#define read_c0_badvaddr()	__read_ulong_c0_register($8, 0)
-#define write_c0_badvaddr(val)	__write_ulong_c0_register($8, 0, val)
-
-#define read_c0_count()		__read_32bit_c0_register($9, 0)
-#define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
-
-#define read_c0_count2()	__read_32bit_c0_register($9, 6) /* pnx8550 */
-#define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)
-
-#define read_c0_count3()	__read_32bit_c0_register($9, 7) /* pnx8550 */
-#define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)
-
-#define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
-#define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
-
-#define read_c0_compare()	__read_32bit_c0_register($11, 0)
-#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
-
-#define read_c0_compare2()	__read_32bit_c0_register($11, 6) /* pnx8550 */
-#define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)
-
-#define read_c0_compare3()	__read_32bit_c0_register($11, 7) /* pnx8550 */
-#define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)
-
-#define read_c0_status()	__read_32bit_c0_register($12, 0)
-#ifdef CONFIG_MIPS_MT_SMTC
-#define write_c0_status(val)						\
-do {									\
-	__write_32bit_c0_register($12, 0, val);				\
-	__ehb();							\
-} while (0)
-#else
-/*
- * Legacy non-SMTC code, which may be hazardous
- * but which might not support EHB
- */
-#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-#define read_c0_cause()		__read_32bit_c0_register($13, 0)
-#define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)
-
-#define read_c0_epc()		__read_ulong_c0_register($14, 0)
-#define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
-
-#define read_c0_prid()		__read_32bit_c0_register($15, 0)
-
-#define read_c0_config()	__read_32bit_c0_register($16, 0)
-#define read_c0_config1()	__read_32bit_c0_register($16, 1)
-#define read_c0_config2()	__read_32bit_c0_register($16, 2)
-#define read_c0_config3()	__read_32bit_c0_register($16, 3)
-#define read_c0_config4()	__read_32bit_c0_register($16, 4)
-#define read_c0_config5()	__read_32bit_c0_register($16, 5)
-#define read_c0_config6()	__read_32bit_c0_register($16, 6)
-#define read_c0_config7()	__read_32bit_c0_register($16, 7)
-#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
-#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
-#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
-#define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
-#define write_c0_config4(val)	__write_32bit_c0_register($16, 4, val)
-#define write_c0_config5(val)	__write_32bit_c0_register($16, 5, val)
-#define write_c0_config6(val)	__write_32bit_c0_register($16, 6, val)
-#define write_c0_config7(val)	__write_32bit_c0_register($16, 7, val)
-
-/*
- * The WatchLo register.  There may be upto 8 of them.
- */
-#define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
-#define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
-#define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
-#define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
-#define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
-#define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
-#define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
-#define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
-#define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
-#define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
-#define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
-#define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
-#define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
-#define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
-#define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
-#define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)
-
-/*
- * The WatchHi register.  There may be upto 8 of them.
- */
-#define read_c0_watchhi0()	__read_32bit_c0_register($19, 0)
-#define read_c0_watchhi1()	__read_32bit_c0_register($19, 1)
-#define read_c0_watchhi2()	__read_32bit_c0_register($19, 2)
-#define read_c0_watchhi3()	__read_32bit_c0_register($19, 3)
-#define read_c0_watchhi4()	__read_32bit_c0_register($19, 4)
-#define read_c0_watchhi5()	__read_32bit_c0_register($19, 5)
-#define read_c0_watchhi6()	__read_32bit_c0_register($19, 6)
-#define read_c0_watchhi7()	__read_32bit_c0_register($19, 7)
-
-#define write_c0_watchhi0(val)	__write_32bit_c0_register($19, 0, val)
-#define write_c0_watchhi1(val)	__write_32bit_c0_register($19, 1, val)
-#define write_c0_watchhi2(val)	__write_32bit_c0_register($19, 2, val)
-#define write_c0_watchhi3(val)	__write_32bit_c0_register($19, 3, val)
-#define write_c0_watchhi4(val)	__write_32bit_c0_register($19, 4, val)
-#define write_c0_watchhi5(val)	__write_32bit_c0_register($19, 5, val)
-#define write_c0_watchhi6(val)	__write_32bit_c0_register($19, 6, val)
-#define write_c0_watchhi7(val)	__write_32bit_c0_register($19, 7, val)
-
-#define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
-#define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
-
-#define read_c0_intcontrol()	__read_32bit_c0_ctrl_register($20)
-#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
-
-#define read_c0_framemask()	__read_32bit_c0_register($21, 0)
-#define write_c0_framemask(val)	__write_32bit_c0_register($21, 0, val)
-
-/* RM9000 PerfControl performance counter control register */
-#define read_c0_perfcontrol()	__read_32bit_c0_register($22, 0)
-#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
-
-#define read_c0_diag()		__read_32bit_c0_register($22, 0)
-#define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
-
-#define read_c0_diag1()		__read_32bit_c0_register($22, 1)
-#define write_c0_diag1(val)	__write_32bit_c0_register($22, 1, val)
-
-#define read_c0_diag2()		__read_32bit_c0_register($22, 2)
-#define write_c0_diag2(val)	__write_32bit_c0_register($22, 2, val)
-
-#define read_c0_diag3()		__read_32bit_c0_register($22, 3)
-#define write_c0_diag3(val)	__write_32bit_c0_register($22, 3, val)
-
-#define read_c0_diag4()		__read_32bit_c0_register($22, 4)
-#define write_c0_diag4(val)	__write_32bit_c0_register($22, 4, val)
-
-#define read_c0_diag5()		__read_32bit_c0_register($22, 5)
-#define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
-
-#define read_c0_debug()		__read_32bit_c0_register($23, 0)
-#define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
-
-#define read_c0_depc()		__read_ulong_c0_register($24, 0)
-#define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)
-
-/*
- * MIPS32 / MIPS64 performance counters
- */
-#define read_c0_perfctrl0()	__read_32bit_c0_register($25, 0)
-#define write_c0_perfctrl0(val)	__write_32bit_c0_register($25, 0, val)
-#define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)
-#define write_c0_perfcntr0(val)	__write_32bit_c0_register($25, 1, val)
-#define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)
-#define write_c0_perfctrl1(val)	__write_32bit_c0_register($25, 2, val)
-#define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)
-#define write_c0_perfcntr1(val)	__write_32bit_c0_register($25, 3, val)
-#define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)
-#define write_c0_perfctrl2(val)	__write_32bit_c0_register($25, 4, val)
-#define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)
-#define write_c0_perfcntr2(val)	__write_32bit_c0_register($25, 5, val)
-#define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)
-#define write_c0_perfctrl3(val)	__write_32bit_c0_register($25, 6, val)
-#define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)
-#define write_c0_perfcntr3(val)	__write_32bit_c0_register($25, 7, val)
-
-/* RM9000 PerfCount performance counter register */
-#define read_c0_perfcount()	__read_64bit_c0_register($25, 0)
-#define write_c0_perfcount(val)	__write_64bit_c0_register($25, 0, val)
-
-#define read_c0_ecc()		__read_32bit_c0_register($26, 0)
-#define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)
-
-#define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
-#define write_c0_derraddr0(val)	__write_ulong_c0_register($26, 1, val)
-
-#define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)
-
-#define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
-#define write_c0_derraddr1(val)	__write_ulong_c0_register($27, 1, val)
-
-#define read_c0_taglo()		__read_32bit_c0_register($28, 0)
-#define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)
-
-#define read_c0_dtaglo()	__read_32bit_c0_register($28, 2)
-#define write_c0_dtaglo(val)	__write_32bit_c0_register($28, 2, val)
-
-#define read_c0_taghi()		__read_32bit_c0_register($29, 0)
-#define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
-
-#define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
-#define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
-
-/* MIPSR2 */
-#define read_c0_hwrena()	__read_32bit_c0_register($7, 0)
-#define write_c0_hwrena(val)	__write_32bit_c0_register($7, 0, val)
-
-#define read_c0_intctl()	__read_32bit_c0_register($12, 1)
-#define write_c0_intctl(val)	__write_32bit_c0_register($12, 1, val)
-
-#define read_c0_srsctl()	__read_32bit_c0_register($12, 2)
-#define write_c0_srsctl(val)	__write_32bit_c0_register($12, 2, val)
-
-#define read_c0_srsmap()	__read_32bit_c0_register($12, 3)
-#define write_c0_srsmap(val)	__write_32bit_c0_register($12, 3, val)
-
-#define read_c0_ebase()		__read_32bit_c0_register($15, 1)
-#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
-
-/*
- * Macros to access the floating point coprocessor control registers
- */
-#define read_32bit_cp1_register(source)				\
-({ int __res;							\
-	__asm__ __volatile__(					\
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
-	"cfc1\t%0,"STR(source)"\n\t"				\
-	".set\tpop"						\
-	: "=r" (__res));					\
-	__res;})
-
-#define rddsp(mask)							\
-({									\
-	unsigned int __res;						\
-									\
-	__asm__ __volatile__(						\
-	"	.set	push				\n"		\
-	"	.set	noat				\n"		\
-	"	# rddsp $1, %x1				\n"		\
-	"	.word	0x7c000cb8 | (%x1 << 16)	\n"		\
-	"	move	%0, $1				\n"		\
-	"	.set	pop				\n"		\
-	: "=r" (__res)							\
-	: "i" (mask));							\
-	__res;								\
-})
-
-#define wrdsp(val, mask)						\
-do {									\
-	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noat					\n"	\
-	"	move	$1, %0					\n"	\
-	"	# wrdsp $1, %x1					\n"	\
-	"	.word	0x7c2004f8 | (%x1 << 11)		\n"	\
-	"	.set	pop					\n"	\
-	:								\
-	: "r" (val), "i" (mask));					\
-} while (0)
-
-#define mfhi0()								\
-({									\
-	unsigned long __treg;						\
-									\
-	__asm__ __volatile__(						\
-	"	.set	push			\n"			\
-	"	.set	noat			\n"			\
-	"	# mfhi	%0, $ac0		\n"			\
-	"	.word	0x00000810		\n"			\
-	"	move	%0, $1			\n"			\
-	"	.set	pop			\n"			\
-	: "=r" (__treg));						\
-	__treg;								\
-})
-
-#define mfhi1()								\
-({									\
-	unsigned long __treg;						\
-									\
-	__asm__ __volatile__(						\
-	"	.set	push			\n"			\
-	"	.set	noat			\n"			\
-	"	# mfhi	%0, $ac1		\n"			\
-	"	.word	0x00200810		\n"			\
-	"	move	%0, $1			\n"			\
-	"	.set	pop			\n"			\
-	: "=r" (__treg));						\
-	__treg;								\
-})
-
-#define mfhi2()								\
-({									\
-	unsigned long __treg;						\
-									\
-	__asm__ __volatile__(						\
-	"	.set	push			\n"			\
-	"	.set	noat			\n"			\
-	"	# mfhi	%0, $ac2		\n"			\
-	"	.word	0x00400810		\n"			\
-	"	move	%0, $1			\n"			\
-	"	.set	pop			\n"			\
-	: "=r" (__treg));						\
-	__treg;								\
-})
-
-#define mfhi3()								\
-({									\
-	unsigned long __treg;						\
-									\
-	__asm__ __volatile__(						\
-	"	.set	push			\n"			\
-	"	.set	noat			\n"			\
-	"	# mfhi	%0, $ac3		\n"			\
-	"	.word	0x00600810		\n"			\
-	"	move	%0, $1			\n"			\
-	"	.set	pop			\n"			\
-	: "=r" (__treg));						\
-	__treg;								\
-})
-
-#define mflo0()								\
-({									\
-	unsigned long __treg;						\
-									\
-	__asm__ __volatile__(						\
-	"	.set	push			\n"			\
-	"	.set	noat			\n"			\
-	"	# mflo	%0, $ac0		\n"			\
-	"	.word	0x00000812		\n"			\
-	"	move	%0, $1			\n"			\
-	"	.set	pop			\n"			\
-	: "=r" (__treg));						\
-	__treg;								\
-})
-
-#define mflo1()								\
-({									\
-	unsigned long __treg;						\
-									\
-	__asm__ __volatile__(						\
-	"	.set	push			\n"			\
-	"	.set	noat			\n"			\
-	"	# mflo	%0, $ac1		\n"			\
-	"	.word	0x00200812		\n"			\
-	"	move	%0, $1			\n"			\
-	"	.set	pop			\n"			\
-	: "=r" (__treg));						\
-	__treg;								\
-})
-
-#define mflo2()								\
-({									\
-	unsigned long __treg;						\
-									\
-	__asm__ __volatile__(						\
-	"	.set	push			\n"			\
-	"	.set	noat			\n"			\
-	"	# mflo	%0, $ac2		\n"			\
-	"	.word	0x00400812		\n"			\
-	"	move	%0, $1			\n"			\
-	"	.set	pop			\n"			\
-	: "=r" (__treg));						\
-	__treg;								\
-})
-
-#define mflo3()								\
-({									\
-	unsigned long __treg;						\
-									\
-	__asm__ __volatile__(						\
-	"	.set	push			\n"			\
-	"	.set	noat			\n"			\
-	"	# mflo	%0, $ac3		\n"			\
-	"	.word	0x00600812		\n"			\
-	"	move	%0, $1			\n"			\
-	"	.set	pop			\n"			\
-	: "=r" (__treg));						\
-	__treg;								\
-})
-
-#define mthi0(x)							\
-do {									\
-	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noat					\n"	\
-	"	move	$1, %0					\n"	\
-	"	# mthi	$1, $ac0				\n"	\
-	"	.word	0x00200011				\n"	\
-	"	.set	pop					\n"	\
-	:								\
-	: "r" (x));							\
-} while (0)
-
-#define mthi1(x)							\
-do {									\
-	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noat					\n"	\
-	"	move	$1, %0					\n"	\
-	"	# mthi	$1, $ac1				\n"	\
-	"	.word	0x00200811				\n"	\
-	"	.set	pop					\n"	\
-	:								\
-	: "r" (x));							\
-} while (0)
-
-#define mthi2(x)							\
-do {									\
-	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noat					\n"	\
-	"	move	$1, %0					\n"	\
-	"	# mthi	$1, $ac2				\n"	\
-	"	.word	0x00201011				\n"	\
-	"	.set	pop					\n"	\
-	:								\
-	: "r" (x));							\
-} while (0)
-
-#define mthi3(x)							\
-do {									\
-	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noat					\n"	\
-	"	move	$1, %0					\n"	\
-	"	# mthi	$1, $ac3				\n"	\
-	"	.word	0x00201811				\n"	\
-	"	.set	pop					\n"	\
-	:								\
-	: "r" (x));							\
-} while (0)
-
-#define mtlo0(x)							\
-do {									\
-	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noat					\n"	\
-	"	move	$1, %0					\n"	\
-	"	# mtlo	$1, $ac0				\n"	\
-	"	.word	0x00200013				\n"	\
-	"	.set	pop					\n"	\
-	:								\
-	: "r" (x));							\
-} while (0)
-
-#define mtlo1(x)							\
-do {									\
-	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noat					\n"	\
-	"	move	$1, %0					\n"	\
-	"	# mtlo	$1, $ac1				\n"	\
-	"	.word	0x00200813				\n"	\
-	"	.set	pop					\n"	\
-	:								\
-	: "r" (x));							\
-} while (0)
-
-#define mtlo2(x)							\
-do {									\
-	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noat					\n"	\
-	"	move	$1, %0					\n"	\
-	"	# mtlo	$1, $ac2				\n"	\
-	"	.word	0x00201013				\n"	\
-	"	.set	pop					\n"	\
-	:								\
-	: "r" (x));							\
-} while (0)
-
-#define mtlo3(x)							\
-do {									\
-	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noat					\n"	\
-	"	move	$1, %0					\n"	\
-	"	# mtlo	$1, $ac3				\n"	\
-	"	.word	0x00201813				\n"	\
-	"	.set	pop					\n"	\
-	:								\
-	: "r" (x));							\
-} while (0)
-
-/*
- * TLB operations.
- *
- * It is responsibility of the caller to take care of any TLB hazards.
- */
-static inline void tlb_probe(void)
-{
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbp\n\t"
-		".set reorder");
-}
-
-static inline void tlb_read(void)
-{
-#if MIPS34K_MISSED_ITLB_WAR
-	int res = 0;
-
-	__asm__ __volatile__(
-	"	.set	push					\n"
-	"	.set	noreorder				\n"
-	"	.set	noat					\n"
-	"	.set	mips32r2				\n"
-	"	.word	0x41610001		# dvpe $1	\n"
-	"	move	%0, $1					\n"
-	"	ehb						\n"
-	"	.set	pop					\n"
-	: "=r" (res));
-
-	instruction_hazard();
-#endif
-
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbr\n\t"
-		".set reorder");
-
-#if MIPS34K_MISSED_ITLB_WAR
-	if ((res & _ULCAST_(1)))
-		__asm__ __volatile__(
-		"	.set	push				\n"
-		"	.set	noreorder			\n"
-		"	.set	noat				\n"
-		"	.set	mips32r2			\n"
-		"	.word	0x41600021	# evpe		\n"
-		"	ehb					\n"
-		"	.set	pop				\n");
-#endif
-}
-
-static inline void tlb_write_indexed(void)
-{
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbwi\n\t"
-		".set reorder");
-}
-
-static inline void tlb_write_random(void)
-{
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbwr\n\t"
-		".set reorder");
-}
-
-/*
- * Manipulate bits in a c0 register.
- */
-#define __BUILD_SET_C0(name)					\
-static inline unsigned int					\
-set_c0_##name(unsigned int set)					\
-{								\
-	unsigned int res;					\
-								\
-	res = read_c0_##name();					\
-	res |= set;						\
-	write_c0_##name(res);					\
-								\
-	return res;						\
-}								\
-								\
-static inline unsigned int					\
-clear_c0_##name(unsigned int clear)				\
-{								\
-	unsigned int res;					\
-								\
-	res = read_c0_##name();					\
-	res &= ~clear;						\
-	write_c0_##name(res);					\
-								\
-	return res;						\
-}								\
-								\
-static inline unsigned int					\
-change_c0_##name(unsigned int change, unsigned int new)		\
-{								\
-	unsigned int res;					\
-								\
-	res = read_c0_##name();					\
-	res &= ~change;						\
-	res |= (new & change);					\
-	write_c0_##name(res);					\
-								\
-	return res;						\
-}
-
-__BUILD_SET_C0(status)
-__BUILD_SET_C0(cause)
-__BUILD_SET_C0(config)
-__BUILD_SET_C0(intcontrol)
-__BUILD_SET_C0(intctl)
-__BUILD_SET_C0(srsmap)
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_MIPSREGS_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/posix_types.h b/qemu/roms/u-boot/arch/mips/include/asm/posix_types.h
deleted file mode 100644
index 4deac5207..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/posix_types.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle
- */
-#ifndef _ASM_POSIX_TYPES_H
-#define _ASM_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned int	__kernel_dev_t;
-typedef unsigned long	__kernel_ino_t;
-typedef unsigned int	__kernel_mode_t;
-typedef int		__kernel_nlink_t;
-typedef long		__kernel_off_t;
-typedef int		__kernel_pid_t;
-typedef int		__kernel_ipc_pid_t;
-typedef int		__kernel_uid_t;
-typedef int		__kernel_gid_t;
-#if _MIPS_SZLONG != 64
-typedef unsigned int	__kernel_size_t;
-typedef int		__kernel_ssize_t;
-typedef int		__kernel_ptrdiff_t;
-#else
-typedef unsigned long	__kernel_size_t;
-typedef long		__kernel_ssize_t;
-typedef long		__kernel_ptrdiff_t;
-#endif
-typedef long		__kernel_time_t;
-typedef long		__kernel_suseconds_t;
-typedef long		__kernel_clock_t;
-typedef long		__kernel_daddr_t;
-typedef char *		__kernel_caddr_t;
-
-typedef unsigned short	__kernel_uid16_t;
-typedef unsigned short	__kernel_gid16_t;
-typedef int		__kernel_uid32_t;
-typedef int		__kernel_gid32_t;
-typedef __kernel_uid_t	__kernel_old_uid_t;
-typedef __kernel_gid_t	__kernel_old_gid_t;
-
-#ifdef __GNUC__
-typedef long long      __kernel_loff_t;
-#endif
-
-typedef struct {
-	long    val[2];
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
-
-#undef __FD_SET
-static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
-{
-	unsigned long __tmp = __fd / __NFDBITS;
-	unsigned long __rem = __fd % __NFDBITS;
-	__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
-}
-
-#undef __FD_CLR
-static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
-{
-	unsigned long __tmp = __fd / __NFDBITS;
-	unsigned long __rem = __fd % __NFDBITS;
-	__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
-}
-
-#undef __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
-{
-	unsigned long __tmp = __fd / __NFDBITS;
-	unsigned long __rem = __fd % __NFDBITS;
-	return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
-{
-	unsigned long *__tmp = __p->fds_bits;
-	int __i;
-
-	if (__builtin_constant_p(__FDSET_LONGS)) {
-		switch (__FDSET_LONGS) {
-		case 16:
-			__tmp[ 0] = 0; __tmp[ 1] = 0;
-			__tmp[ 2] = 0; __tmp[ 3] = 0;
-			__tmp[ 4] = 0; __tmp[ 5] = 0;
-			__tmp[ 6] = 0; __tmp[ 7] = 0;
-			__tmp[ 8] = 0; __tmp[ 9] = 0;
-			__tmp[10] = 0; __tmp[11] = 0;
-			__tmp[12] = 0; __tmp[13] = 0;
-			__tmp[14] = 0; __tmp[15] = 0;
-			return;
-
-		case 8:
-			__tmp[ 0] = 0; __tmp[ 1] = 0;
-			__tmp[ 2] = 0; __tmp[ 3] = 0;
-			__tmp[ 4] = 0; __tmp[ 5] = 0;
-			__tmp[ 6] = 0; __tmp[ 7] = 0;
-			return;
-
-		case 4:
-			__tmp[ 0] = 0; __tmp[ 1] = 0;
-			__tmp[ 2] = 0; __tmp[ 3] = 0;
-			return;
-		}
-	}
-	__i = __FDSET_LONGS;
-	while (__i) {
-		__i--;
-		*__tmp = 0;
-		__tmp++;
-	}
-}
-
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
-
-#endif /* _ASM_POSIX_TYPES_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/processor.h b/qemu/roms/u-boot/arch/mips/include/asm/processor.h
deleted file mode 100644
index ba7f5381a..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/processor.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 Waldorf GMBH
- * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
- * Copyright (C) 1996 Paul M. Antoine
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_PROCESSOR_H
-#define _ASM_PROCESSOR_H
-
-#include <asm/isadep.h>
-
-#include <asm/cachectl.h>
-#include <asm/mipsregs.h>
-#include <asm/reg.h>
-#include <asm/system.h>
-
-/*
- * Return current * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-/*
- * System setup and hardware flags..
- */
-extern void (*cpu_wait)(void);
-
-extern unsigned int vced_count, vcei_count;
-
-#define NUM_FPU_REGS	32
-
-typedef __u64 fpureg_t;
-
-/*
- * It would be nice to add some more fields for emulator statistics, but there
- * are a number of fixed offsets in offset.h and elsewhere that would have to
- * be recalculated by hand.  So the additional information will be private to
- * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
- */
-
-struct mips_fpu_struct {
-	fpureg_t	fpr[NUM_FPU_REGS];
-	unsigned int	fcr31;
-};
-
-#define NUM_DSP_REGS   6
-
-typedef __u32 dspreg_t;
-
-struct mips_dsp_state {
-	dspreg_t        dspr[NUM_DSP_REGS];
-	unsigned int    dspcontrol;
-};
-
-typedef struct {
-	unsigned long seg;
-} mm_segment_t;
-
-#define ARCH_MIN_TASKALIGN	8
-
-struct mips_abi;
-
-/*
- * If you change thread_struct remember to change the #defines below too!
- */
-struct thread_struct {
-	/* Saved main processor registers. */
-	unsigned long reg16;
-	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
-	unsigned long reg29, reg30, reg31;
-
-	/* Saved cp0 stuff. */
-	unsigned long cp0_status;
-
-	/* Saved fpu/fpu emulator stuff. */
-	struct mips_fpu_struct fpu;
-#ifdef CONFIG_MIPS_MT_FPAFF
-	/* Emulated instruction count */
-	unsigned long emulated_fp;
-	/* Saved per-thread scheduler affinity mask */
-	cpumask_t user_cpus_allowed;
-#endif /* CONFIG_MIPS_MT_FPAFF */
-
-	/* Saved state of the DSP ASE, if available. */
-	struct mips_dsp_state dsp;
-
-	/* Other stuff associated with the thread. */
-	unsigned long cp0_badvaddr;	/* Last user fault */
-	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
-	unsigned long error_code;
-	unsigned long trap_no;
-	unsigned long irix_trampoline;  /* Wheee... */
-	unsigned long irix_oldctx;
-	struct mips_abi *abi;
-};
-
-struct task_struct;
-
-/* Free all resources held by a thread. */
-#define release_thread(thread) do { } while(0)
-
-/* Prepare to copy thread state - unlazy all lazy status */
-#define prepare_to_copy(tsk)	do { } while (0)
-
-#define cpu_relax()	barrier()
-
-/*
- * Return_address is a replacement for __builtin_return_address(count)
- * which on certain architectures cannot reasonably be implemented in GCC
- * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
- * Note that __builtin_return_address(x>=1) is forbidden because GCC
- * aborts compilation on some CPUs.  It's simply not possible to unwind
- * some CPU's stackframes.
- *
- * __builtin_return_address works only for non-leaf functions.  We avoid the
- * overhead of a function call by forcing the compiler to save the return
- * address register on the stack.
- */
-#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
-
-#ifdef CONFIG_CPU_HAS_PREFETCH
-
-#define ARCH_HAS_PREFETCH
-
-static inline void prefetch(const void *addr)
-{
-	__asm__ __volatile__(
-	"	.set	mips4		\n"
-	"	pref	%0, (%1)	\n"
-	"	.set	mips0		\n"
-	:
-	: "i" (Pref_Load), "r" (addr));
-}
-
-#endif
-
-#endif /* _ASM_PROCESSOR_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/ptrace.h b/qemu/roms/u-boot/arch/mips/include/asm/ptrace.h
deleted file mode 100644
index 5659c0c87..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/ptrace.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_PTRACE_H
-#define _ASM_PTRACE_H
-
-/* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
-#define FPR_BASE	32
-#define PC		64
-#define CAUSE		65
-#define BADVADDR	66
-#define MMHI		67
-#define MMLO		68
-#define FPC_CSR		69
-#define FPC_EIR		70
-#define DSP_BASE	71		/* 3 more hi / lo register pairs */
-#define DSP_CONTROL	77
-#define ACX		78
-
-/*
- * This struct defines the way the registers are stored on the stack during a
- * system call/exception. As usual the registers k0/k1 aren't being saved.
- */
-struct pt_regs {
-#ifdef CONFIG_32BIT
-	/* Pad bytes for argument save space on the stack. */
-	unsigned long pad0[6];
-#endif
-
-	/* Saved main processor registers. */
-	unsigned long regs[32];
-
-	/* Saved special registers. */
-	unsigned long cp0_status;
-	unsigned long hi;
-	unsigned long lo;
-#ifdef CONFIG_CPU_HAS_SMARTMIPS
-	unsigned long acx;
-#endif
-	unsigned long cp0_badvaddr;
-	unsigned long cp0_cause;
-	unsigned long cp0_epc;
-#ifdef CONFIG_MIPS_MT_SMTC
-	unsigned long cp0_tcstatus;
-#endif /* CONFIG_MIPS_MT_SMTC */
-} __attribute__ ((aligned (8)));
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS		12
-#define PTRACE_SETREGS		13
-#define PTRACE_GETFPREGS		14
-#define PTRACE_SETFPREGS		15
-/* #define PTRACE_GETFPXREGS		18 */
-/* #define PTRACE_SETFPXREGS		19 */
-
-#define PTRACE_OLDSETOPTIONS	21
-
-#define PTRACE_GET_THREAD_AREA	25
-#define PTRACE_SET_THREAD_AREA	26
-
-/* Calls to trace a 64bit program from a 32bit program.  */
-#define PTRACE_PEEKTEXT_3264	0xc0
-#define PTRACE_PEEKDATA_3264	0xc1
-#define PTRACE_POKETEXT_3264	0xc2
-#define PTRACE_POKEDATA_3264	0xc3
-#define PTRACE_GET_THREAD_AREA_3264	0xc4
-
-#ifdef __KERNEL__
-
-#include <asm/isadep.h>
-
-/*
- * Does the process account for user or for system time?
- */
-#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
-
-#define instruction_pointer(regs) ((regs)->cp0_epc)
-#define profile_pc(regs) instruction_pointer(regs)
-
-#endif
-
-#endif /* _ASM_PTRACE_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/reboot.h b/qemu/roms/u-boot/arch/mips/include/asm/reboot.h
deleted file mode 100644
index 978d20681..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/reboot.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
- * Copyright (C) 2001 MIPS Technologies, Inc.
- */
-#ifndef _ASM_REBOOT_H
-#define _ASM_REBOOT_H
-
-extern void _machine_restart(void);
-
-#endif /* _ASM_REBOOT_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/reg.h b/qemu/roms/u-boot/arch/mips/include/asm/reg.h
deleted file mode 100644
index fc6bc0c16..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/reg.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Various register offset definitions for debuggers, core file
- * examiners and whatnot.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1999 by Ralf Baechle
- * Copyright (C) 1995, 1999 Silicon Graphics
- */
-#ifndef __ASM_MIPS_REG_H
-#define __ASM_MIPS_REG_H
-
-#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
-
-#define EF_R0			6
-#define EF_R1			7
-#define EF_R2			8
-#define EF_R3			9
-#define EF_R4			10
-#define EF_R5			11
-#define EF_R6			12
-#define EF_R7			13
-#define EF_R8			14
-#define EF_R9			15
-#define EF_R10			16
-#define EF_R11			17
-#define EF_R12			18
-#define EF_R13			19
-#define EF_R14			20
-#define EF_R15			21
-#define EF_R16			22
-#define EF_R17			23
-#define EF_R18			24
-#define EF_R19			25
-#define EF_R20			26
-#define EF_R21			27
-#define EF_R22			28
-#define EF_R23			29
-#define EF_R24			30
-#define EF_R25			31
-
-/*
- * k0/k1 unsaved
- */
-#define EF_R26			32
-#define EF_R27			33
-
-#define EF_R28			34
-#define EF_R29			35
-#define EF_R30			36
-#define EF_R31			37
-
-/*
- * Saved special registers
- */
-#define EF_LO			38
-#define EF_HI			39
-
-#define EF_CP0_EPC		40
-#define EF_CP0_BADVADDR		41
-#define EF_CP0_STATUS		42
-#define EF_CP0_CAUSE		43
-#define EF_UNUSED0		44
-
-#define EF_SIZE			180
-
-#endif
-
-#ifdef CONFIG_64BIT
-
-#define EF_R0			 0
-#define EF_R1			 1
-#define EF_R2			 2
-#define EF_R3			 3
-#define EF_R4			 4
-#define EF_R5			 5
-#define EF_R6			 6
-#define EF_R7			 7
-#define EF_R8			 8
-#define EF_R9			 9
-#define EF_R10			10
-#define EF_R11			11
-#define EF_R12			12
-#define EF_R13			13
-#define EF_R14			14
-#define EF_R15			15
-#define EF_R16			16
-#define EF_R17			17
-#define EF_R18			18
-#define EF_R19			19
-#define EF_R20			20
-#define EF_R21			21
-#define EF_R22			22
-#define EF_R23			23
-#define EF_R24			24
-#define EF_R25			25
-
-/*
- * k0/k1 unsaved
- */
-#define EF_R26			26
-#define EF_R27			27
-
-#define EF_R28			28
-#define EF_R29			29
-#define EF_R30			30
-#define EF_R31			31
-
-/*
- * Saved special registers
- */
-#define EF_LO			32
-#define EF_HI			33
-
-#define EF_CP0_EPC		34
-#define EF_CP0_BADVADDR		35
-#define EF_CP0_STATUS		36
-#define EF_CP0_CAUSE		37
-
-#define EF_SIZE			304	/* size in bytes */
-
-#endif /* CONFIG_64BIT */
-
-#endif /* __ASM_MIPS_REG_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/regdef.h b/qemu/roms/u-boot/arch/mips/include/asm/regdef.h
deleted file mode 100644
index 2e65cc3c4..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/regdef.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1985 MIPS Computer Systems, Inc.
- * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
- * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_REGDEF_H
-#define _ASM_REGDEF_H
-
-#include <asm/sgidefs.h>
-
-#if _MIPS_SIM == _MIPS_SIM_ABI32
-
-/*
- * Symbolic register names for 32 bit ABI
- */
-#define zero	$0	/* wired zero */
-#define AT	$1	/* assembler temp  - uppercase because of ".set at" */
-#define v0	$2	/* return value */
-#define v1	$3
-#define a0	$4	/* argument registers */
-#define a1	$5
-#define a2	$6
-#define a3	$7
-#define t0	$8	/* caller saved */
-#define t1	$9
-#define t2	$10
-#define t3	$11
-#define t4	$12
-#define t5	$13
-#define t6	$14
-#define t7	$15
-#define s0	$16	/* callee saved */
-#define s1	$17
-#define s2	$18
-#define s3	$19
-#define s4	$20
-#define s5	$21
-#define s6	$22
-#define s7	$23
-#define t8	$24	/* caller saved */
-#define t9	$25
-#define jp	$25	/* PIC jump register */
-#define k0	$26	/* kernel scratch */
-#define k1	$27
-#define gp	$28	/* global pointer */
-#define sp	$29	/* stack pointer */
-#define fp	$30	/* frame pointer */
-#define s8	$30	/* same like fp! */
-#define ra	$31	/* return address */
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-
-#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
-
-#define zero	$0	/* wired zero */
-#define AT	$at	/* assembler temp - uppercase because of ".set at" */
-#define v0	$2	/* return value - caller saved */
-#define v1	$3
-#define a0	$4	/* argument registers */
-#define a1	$5
-#define a2	$6
-#define a3	$7
-#define a4	$8	/* arg reg 64 bit; caller saved in 32 bit */
-#define ta0	$8
-#define a5	$9
-#define ta1	$9
-#define a6	$10
-#define ta2	$10
-#define a7	$11
-#define ta3	$11
-#define t0	$12	/* caller saved */
-#define t1	$13
-#define t2	$14
-#define t3	$15
-#define s0	$16	/* callee saved */
-#define s1	$17
-#define s2	$18
-#define s3	$19
-#define s4	$20
-#define s5	$21
-#define s6	$22
-#define s7	$23
-#define t8	$24	/* caller saved */
-#define t9	$25	/* callee address for PIC/temp */
-#define jp	$25	/* PIC jump register */
-#define k0	$26	/* kernel temporary */
-#define k1	$27
-#define gp	$28	/* global pointer - caller saved for PIC */
-#define sp	$29	/* stack pointer */
-#define fp	$30	/* frame pointer */
-#define s8	$30	/* callee saved */
-#define ra	$31	/* return address */
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
-
-#endif /* _ASM_REGDEF_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/sections.h b/qemu/roms/u-boot/arch/mips/include/asm/sections.h
deleted file mode 100644
index fc4640a39..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/sections.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_MIPS_SECTIONS_H
-#define __ASM_MIPS_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/sgidefs.h b/qemu/roms/u-boot/arch/mips/include/asm/sgidefs.h
deleted file mode 100644
index 67f265895..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/sgidefs.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1999, 2001 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- */
-#ifndef __ASM_SGIDEFS_H
-#define __ASM_SGIDEFS_H
-
-/*
- * Using a Linux compiler for building Linux seems logic but not to
- * everybody.
- */
-#if 0 /* ndef __linux__ */
-#error Use a Linux compiler or give up.
-#endif
-
-/*
- * Definitions for the ISA levels
- *
- * With the introduction of MIPS32 / MIPS64 instruction sets definitions
- * MIPS ISAs are no longer subsets of each other.  Therefore comparisons
- * on these symbols except with == may result in unexpected results and
- * are forbidden!
- */
-#define _MIPS_ISA_MIPS1		1
-#define _MIPS_ISA_MIPS2		2
-#define _MIPS_ISA_MIPS3		3
-#define _MIPS_ISA_MIPS4		4
-#define _MIPS_ISA_MIPS5		5
-#define _MIPS_ISA_MIPS32	6
-#define _MIPS_ISA_MIPS64	7
-
-/*
- * Subprogram calling convention
- */
-#define _MIPS_SIM_ABI32		1
-#define _MIPS_SIM_NABI32	2
-#define _MIPS_SIM_ABI64		3
-
-#endif /* __ASM_SGIDEFS_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/string.h b/qemu/roms/u-boot/arch/mips/include/asm/string.h
deleted file mode 100644
index 579a591e6..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/string.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
- * Copyright (c) 2000 by Silicon Graphics, Inc.
- * Copyright (c) 2001 MIPS Technologies, Inc.
- */
-#ifndef _ASM_STRING_H
-#define _ASM_STRING_H
-
-/*
- * We don't do inline string functions, since the
- * optimised inline asm versions are not small.
- */
-
-#undef __HAVE_ARCH_STRCPY
-extern char *strcpy(char *__dest, __const__ char *__src);
-
-#undef __HAVE_ARCH_STRNCPY
-extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n);
-
-#undef __HAVE_ARCH_STRCMP
-extern int strcmp(__const__ char *__cs, __const__ char *__ct);
-
-#undef __HAVE_ARCH_STRNCMP
-extern int strncmp(__const__ char *__cs, __const__ char *__ct, __kernel_size_t __count);
-
-#undef __HAVE_ARCH_MEMSET
-extern void *memset(void *__s, int __c, __kernel_size_t __count);
-
-#undef __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *__to, __const__ void *__from, __kernel_size_t __n);
-
-#undef __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *__dest, __const__ void *__src, __kernel_size_t __n);
-
-#endif /* _ASM_STRING_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/system.h b/qemu/roms/u-boot/arch/mips/include/asm/system.h
deleted file mode 100644
index 7a2895284..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/system.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 1999 by Ralf Baechle
- * Copyright (C) 1996 by Paul M. Antoine
- * Copyright (C) 1994 - 1999 by Ralf Baechle
- *
- * Changed set_except_vector declaration to allow return of previous
- * vector address value - necessary for "borrowing" vectors.
- *
- * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.
- */
-#ifndef _ASM_SYSTEM_H
-#define _ASM_SYSTEM_H
-
-#include <asm/sgidefs.h>
-#include <asm/ptrace.h>
-#if 0
-#include <linux/kernel.h>
-#endif
-
-extern __inline__ void
-__sti(void)
-{
-	__asm__ __volatile__(
-		".set\tpush\n\t"
-		".set\treorder\n\t"
-		".set\tnoat\n\t"
-		"mfc0\t$1,$12\n\t"
-		"ori\t$1,0x1f\n\t"
-		"xori\t$1,0x1e\n\t"
-		"mtc0\t$1,$12\n\t"
-		".set\tpop\n\t"
-		: /* no outputs */
-		: /* no inputs */
-		: "$1", "memory");
-}
-
-/*
- * For cli() we have to insert nops to make shure that the new value
- * has actually arrived in the status register before the end of this
- * macro.
- * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
- * no nops at all.
- */
-extern __inline__ void
-__cli(void)
-{
-	__asm__ __volatile__(
-		".set\tpush\n\t"
-		".set\treorder\n\t"
-		".set\tnoat\n\t"
-		"mfc0\t$1,$12\n\t"
-		"ori\t$1,1\n\t"
-		"xori\t$1,1\n\t"
-		".set\tnoreorder\n\t"
-		"mtc0\t$1,$12\n\t"
-		"nop\n\t"
-		"nop\n\t"
-		"nop\n\t"
-		".set\tpop\n\t"
-		: /* no outputs */
-		: /* no inputs */
-		: "$1", "memory");
-}
-
-#define __save_flags(x)							\
-__asm__ __volatile__(							\
-	".set\tpush\n\t"						\
-	".set\treorder\n\t"						\
-	"mfc0\t%0,$12\n\t"						\
-	".set\tpop\n\t"							\
-	: "=r" (x))
-
-#define __save_and_cli(x)						\
-__asm__ __volatile__(							\
-	".set\tpush\n\t"						\
-	".set\treorder\n\t"						\
-	".set\tnoat\n\t"						\
-	"mfc0\t%0,$12\n\t"						\
-	"ori\t$1,%0,1\n\t"						\
-	"xori\t$1,1\n\t"						\
-	".set\tnoreorder\n\t"						\
-	"mtc0\t$1,$12\n\t"						\
-	"nop\n\t"							\
-	"nop\n\t"							\
-	"nop\n\t"							\
-	".set\tpop\n\t"							\
-	: "=r" (x)							\
-	: /* no inputs */						\
-	: "$1", "memory")
-
-#define __restore_flags(flags)						\
-do {									\
-	unsigned long __tmp1;						\
-									\
-	__asm__ __volatile__(						\
-		".set\tnoreorder\t\t\t# __restore_flags\n\t"		\
-		".set\tnoat\n\t"					\
-		"mfc0\t$1, $12\n\t"					\
-		"andi\t%0, 1\n\t"					\
-		"ori\t$1, 1\n\t"					\
-		"xori\t$1, 1\n\t"					\
-		"or\t%0, $1\n\t"					\
-		"mtc0\t%0, $12\n\t"					\
-		"nop\n\t"						\
-		"nop\n\t"						\
-		"nop\n\t"						\
-		".set\tat\n\t"						\
-		".set\treorder"						\
-		: "=r" (__tmp1)						\
-		: "0" (flags)						\
-		: "$1", "memory");					\
-} while(0)
-
-#ifdef CONFIG_SMP
-
-extern void __global_sti(void);
-extern void __global_cli(void);
-extern unsigned long __global_save_flags(void);
-extern void __global_restore_flags(unsigned long);
-#  define sti() __global_sti()
-#  define cli() __global_cli()
-#  define save_flags(x) do { x = __global_save_flags(); } while (0)
-#  define restore_flags(x) __global_restore_flags(x)
-#  define save_and_cli(x) do { save_flags(x); cli(); } while(0)
-
-#else /* Single processor */
-
-#  define sti() __sti()
-#  define cli() __cli()
-#  define save_flags(x) __save_flags(x)
-#  define save_and_cli(x) __save_and_cli(x)
-#  define restore_flags(x) __restore_flags(x)
-
-#endif /* SMP */
-
-/* For spinlocks etc */
-#define local_irq_save(x)	__save_and_cli(x);
-#define local_irq_restore(x)	__restore_flags(x);
-#define local_irq_disable()	__cli();
-#define local_irq_enable()	__sti();
-
-/*
- * These are probably defined overly paranoid ...
- */
-#ifdef CONFIG_CPU_HAS_WB
-
-#include <asm/wbflush.h>
-#define rmb()	do { } while(0)
-#define wmb()	wbflush()
-#define mb()	wbflush()
-
-#else /* CONFIG_CPU_HAS_WB  */
-
-#define mb()						\
-__asm__ __volatile__(					\
-	"# prevent instructions being moved around\n\t"	\
-	".set\tnoreorder\n\t"				\
-	"# 8 nops to fool the R4400 pipeline\n\t"	\
-	"nop;nop;nop;nop;nop;nop;nop;nop\n\t"		\
-	".set\treorder"					\
-	: /* no output */				\
-	: /* no input */				\
-	: "memory")
-#define rmb() mb()
-#define wmb() mb()
-
-#endif /* CONFIG_CPU_HAS_WB  */
-
-#ifdef CONFIG_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#endif
-
-#define set_mb(var, value) \
-do { var = value; mb(); } while (0)
-
-#define set_wmb(var, value) \
-do { var = value; wmb(); } while (0)
-
-#if !defined (_LANGUAGE_ASSEMBLY)
-/*
- * switch_to(n) should switch tasks to task nr n, first
- * checking that n isn't the current task, in which case it does nothing.
- */
-#if 0
-extern asmlinkage void *resume(void *last, void *next);
-#endif
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
-
-#define prepare_to_switch()	do { } while(0)
-#define switch_to(prev,next,last) \
-do { \
-	(last) = resume(prev, next); \
-} while(0)
-
-/*
- * For 32 and 64 bit operands we can take advantage of ll and sc.
- * FIXME: This doesn't work for R3000 machines.
- */
-extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
-{
-#ifdef CONFIG_CPU_HAS_LLSC
-	unsigned long dummy;
-
-	__asm__ __volatile__(
-		".set\tnoreorder\t\t\t# xchg_u32\n\t"
-		".set\tnoat\n\t"
-		"ll\t%0, %3\n"
-		"1:\tmove\t$1, %2\n\t"
-		"sc\t$1, %1\n\t"
-		"beqzl\t$1, 1b\n\t"
-		" ll\t%0, %3\n\t"
-		".set\tat\n\t"
-		".set\treorder"
-		: "=r" (val), "=o" (*m), "=r" (dummy)
-		: "o" (*m), "2" (val)
-		: "memory");
-
-	return val;
-#else
-	unsigned long flags, retval;
-
-	save_flags(flags);
-	cli();
-	retval = *m;
-	*m = val;
-	restore_flags(flags);
-	return retval;
-#endif /* Processor-dependent optimization */
-}
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-#define tas(ptr) (xchg((ptr),1))
-
-static __inline__ unsigned long
-__xchg(unsigned long x, volatile void * ptr, int size)
-{
-	switch (size) {
-		case 4:
-			return xchg_u32(ptr, x);
-	}
-	return x;
-}
-
-extern void *set_except_vector(int n, void *addr);
-
-extern void __die(const char *, struct pt_regs *, const char *where,
-	unsigned long line) __attribute__((noreturn));
-extern void __die_if_kernel(const char *, struct pt_regs *, const char *where,
-	unsigned long line);
-
-#define die(msg, regs)							\
-	__die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
-#define die_if_kernel(msg, regs)					\
-	__die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
-
-#endif /* _ASM_SYSTEM_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/types.h b/qemu/roms/u-boot/arch/mips/include/asm/types.h
deleted file mode 100644
index aebafdbba..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/types.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_TYPES_H
-#define _ASM_TYPES_H
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#else
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG _MIPS_SZLONG
-
-#ifndef __ASSEMBLY__
-
-typedef __signed char s8;
-typedef unsigned char u8;
-
-typedef __signed short s16;
-typedef unsigned short u16;
-
-typedef __signed int s32;
-typedef unsigned int u32;
-
-typedef __signed__ long long s64;
-typedef unsigned long long u64;
-
-#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
-    || defined(CONFIG_64BIT)
-typedef u64 dma_addr_t;
-
-typedef u64 phys_addr_t;
-typedef u64 phys_size_t;
-
-#else
-typedef u32 dma_addr_t;
-
-typedef u32 phys_addr_t;
-typedef u32 phys_size_t;
-
-#endif
-typedef u64 dma64_addr_t;
-
-/*
- * Don't use phys_t.  You've been warned.
- */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-typedef unsigned long long phys_t;
-#else
-typedef unsigned long phys_t;
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_TYPES_H */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/u-boot-mips.h b/qemu/roms/u-boot/arch/mips/include/asm/u-boot-mips.h
deleted file mode 100644
index a5b2fc08f..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/u-boot-mips.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de
- */
-
-static inline unsigned long bss_start(void)
-{
-	extern char __bss_start[];
-	return (unsigned long) &__bss_start;
-}
-
-static inline unsigned long bss_end(void)
-{
-	extern ulong __bss_end;
-	return (unsigned long) &__bss_end;
-}
-
-static inline unsigned long image_copy_end(void)
-{
-	extern char __image_copy_end[];
-	return (unsigned long) &__image_copy_end;
-}
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/u-boot.h b/qemu/roms/u-boot/arch/mips/include/asm/u-boot.h
deleted file mode 100644
index 4909a2a5c..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/u-boot.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- ********************************************************************
- * NOTE: This header file defines an interface to U-Boot. Including
- * this (unmodified) header file in another file is considered normal
- * use of U-Boot, and does *not* fall under the heading of "derived
- * work".
- ********************************************************************
- */
-
-#ifndef _U_BOOT_H_
-#define _U_BOOT_H_	1
-
-#ifdef CONFIG_SYS_GENERIC_BOARD
-
-/* Use the generic board which requires a unified bd_info */
-#include <asm-generic/u-boot.h>
-
-#else /* !CONFIG_SYS_GENERIC_BOARD */
-
-typedef struct bd_info {
-	unsigned long	bi_arch_number;	/* unique id for this board */
-	unsigned long	bi_boot_params;	/* where this board expects params */
-	unsigned long	bi_memstart;	/* start of DRAM memory */
-	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
-	unsigned long	bi_flashstart;	/* start of FLASH memory */
-	unsigned long	bi_flashsize;	/* size  of FLASH memory */
-	unsigned long	bi_flashoffset;	/* reserved area for startup monitor */
-} bd_t;
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
-
-/* For image.h:image_check_target_arch() */
-#define IH_ARCH_DEFAULT IH_ARCH_MIPS
-
-#endif	/* _U_BOOT_H_ */
diff --git a/qemu/roms/u-boot/arch/mips/include/asm/unaligned.h b/qemu/roms/u-boot/arch/mips/include/asm/unaligned.h
deleted file mode 100644
index 1d5112ea6..000000000
--- a/qemu/roms/u-boot/arch/mips/include/asm/unaligned.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef _ASM_MIPS_UNALIGNED_H
-#define _ASM_MIPS_UNALIGNED_H
-
-#include <compiler.h>
-#if defined(__MIPSEB__)
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-#elif defined(__MIPSEL__)
-#define get_unaligned	__get_unaligned_le
-#define put_unaligned	__put_unaligned_le
-#else
-#error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
-#endif
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#endif /* _ASM_MIPS_UNALIGNED_H */
diff --git a/qemu/roms/u-boot/arch/mips/lib/Makefile b/qemu/roms/u-boot/arch/mips/lib/Makefile
deleted file mode 100644
index e483e86f6..000000000
--- a/qemu/roms/u-boot/arch/mips/lib/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y	+= board.o
-endif
-obj-y	+= io.o
-
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
-
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
diff --git a/qemu/roms/u-boot/arch/mips/lib/ashldi3.c b/qemu/roms/u-boot/arch/mips/lib/ashldi3.c
deleted file mode 100644
index 9b50d866a..000000000
--- a/qemu/roms/u-boot/arch/mips/lib/ashldi3.c
+++ /dev/null
@@ -1,25 +0,0 @@
-#include "libgcc.h"
-
-long long __ashldi3(long long u, word_type b)
-{
-	DWunion uu, w;
-	word_type bm;
-
-	if (b == 0)
-		return u;
-
-	uu.ll = u;
-	bm = 32 - b;
-
-	if (bm <= 0) {
-		w.s.low = 0;
-		w.s.high = (unsigned int) uu.s.low << -bm;
-	} else {
-		const unsigned int carries = (unsigned int) uu.s.low >> bm;
-
-		w.s.low = (unsigned int) uu.s.low << b;
-		w.s.high = ((unsigned int) uu.s.high << b) | carries;
-	}
-
-	return w.ll;
-}
diff --git a/qemu/roms/u-boot/arch/mips/lib/ashrdi3.c b/qemu/roms/u-boot/arch/mips/lib/ashrdi3.c
deleted file mode 100644
index f30359b73..000000000
--- a/qemu/roms/u-boot/arch/mips/lib/ashrdi3.c
+++ /dev/null
@@ -1,27 +0,0 @@
-#include "libgcc.h"
-
-long long __ashrdi3(long long u, word_type b)
-{
-	DWunion uu, w;
-	word_type bm;
-
-	if (b == 0)
-		return u;
-
-	uu.ll = u;
-	bm = 32 - b;
-
-	if (bm <= 0) {
-		/* w.s.high = 1..1 or 0..0 */
-		w.s.high =
-		    uu.s.high >> 31;
-		w.s.low = uu.s.high >> -bm;
-	} else {
-		const unsigned int carries = (unsigned int) uu.s.high << bm;
-
-		w.s.high = uu.s.high >> b;
-		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
-	}
-
-	return w.ll;
-}
diff --git a/qemu/roms/u-boot/arch/mips/lib/board.c b/qemu/roms/u-boot/arch/mips/lib/board.c
deleted file mode 100644
index 3feb02071..000000000
--- a/qemu/roms/u-boot/arch/mips/lib/board.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <serial.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <net.h>
-#include <environment.h>
-#include <nand.h>
-#include <onenand_uboot.h>
-#include <spi.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-ulong monitor_flash_len;
-
-static char *failed = "*** failed ***\n";
-
-int __board_early_init_f(void)
-{
-	/*
-	 * Nothing to do in this dummy implementation
-	 */
-	return 0;
-}
-int board_early_init_f(void)
-	__attribute__((weak, alias("__board_early_init_f")));
-
-static int init_func_ram(void)
-{
-#ifdef	CONFIG_BOARD_TYPES
-	int board_type = gd->board_type;
-#else
-	int board_type = 0;	/* use dummy arg */
-#endif
-	puts("DRAM:  ");
-
-	gd->ram_size = initdram(board_type);
-	if (gd->ram_size > 0) {
-		print_size(gd->ram_size, "\n");
-		return 0;
-	}
-	puts(failed);
-	return 1;
-}
-
-static int display_banner(void)
-{
-
-	printf("\n\n%s\n\n", version_string);
-	return 0;
-}
-
-#ifndef CONFIG_SYS_NO_FLASH
-static void display_flash_config(ulong size)
-{
-	puts("Flash: ");
-	print_size(size, "\n");
-}
-#endif
-
-static int init_baudrate(void)
-{
-	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
-	return 0;
-}
-
-
-/*
- * Breath some life into the board...
- *
- * The first part of initialization is running from Flash memory;
- * its main purpose is to initialize the RAM so that we
- * can relocate the monitor code to RAM.
- */
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependend #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-typedef int (init_fnc_t)(void);
-
-init_fnc_t *init_sequence[] = {
-	board_early_init_f,
-	timer_init,
-	env_init,		/* initialize environment */
-	init_baudrate,		/* initialize baudrate settings */
-	serial_init,		/* serial communications setup */
-	console_init_f,
-	display_banner,		/* say that we are here */
-	checkboard,
-	init_func_ram,
-	NULL,
-};
-
-
-void board_init_f(ulong bootflag)
-{
-	gd_t gd_data, *id;
-	bd_t *bd;
-	init_fnc_t **init_fnc_ptr;
-	ulong addr, addr_sp, len;
-	ulong *s;
-
-	/* Pointer is writable since we allocated a register for it.
-	 */
-	gd = &gd_data;
-	/* compiler optimization barrier needed for GCC >= 3.4 */
-	__asm__ __volatile__("" : : : "memory");
-
-	memset((void *)gd, 0, sizeof(gd_t));
-
-	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
-		if ((*init_fnc_ptr)() != 0)
-			hang();
-	}
-
-	/*
-	 * Now that we have DRAM mapped and working, we can
-	 * relocate the code and continue running from DRAM.
-	 */
-	addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
-
-	/* We can reserve some RAM "on top" here.
-	 */
-
-	/* round down to next 4 kB limit.
-	 */
-	addr &= ~(4096 - 1);
-	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
-
-	/* Reserve memory for U-Boot code, data & bss
-	 * round down to next 16 kB limit
-	 */
-	len = bss_end() - CONFIG_SYS_MONITOR_BASE;
-	addr -= len;
-	addr &= ~(16 * 1024 - 1);
-
-	debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
-
-	 /* Reserve memory for malloc() arena.
-	 */
-	addr_sp = addr - TOTAL_MALLOC_LEN;
-	debug("Reserving %dk for malloc() at: %08lx\n",
-			TOTAL_MALLOC_LEN >> 10, addr_sp);
-
-	/*
-	 * (permanently) allocate a Board Info struct
-	 * and a permanent copy of the "global" data
-	 */
-	addr_sp -= sizeof(bd_t);
-	bd = (bd_t *)addr_sp;
-	gd->bd = bd;
-	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
-			sizeof(bd_t), addr_sp);
-
-	addr_sp -= sizeof(gd_t);
-	id = (gd_t *)addr_sp;
-	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
-			sizeof(gd_t), addr_sp);
-
-	/* Reserve memory for boot params.
-	 */
-	addr_sp -= CONFIG_SYS_BOOTPARAMS_LEN;
-	bd->bi_boot_params = addr_sp;
-	debug("Reserving %dk for boot params() at: %08lx\n",
-			CONFIG_SYS_BOOTPARAMS_LEN >> 10, addr_sp);
-
-	/*
-	 * Finally, we set up a new (bigger) stack.
-	 *
-	 * Leave some safety gap for SP, force alignment on 16 byte boundary
-	 * Clear initial stack frame
-	 */
-	addr_sp -= 16;
-	addr_sp &= ~0xF;
-	s = (ulong *)addr_sp;
-	*s-- = 0;
-	*s-- = 0;
-	addr_sp = (ulong)s;
-	debug("Stack Pointer at: %08lx\n", addr_sp);
-
-	/*
-	 * Save local variables to board info struct
-	 */
-	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;	/* start of DRAM */
-	bd->bi_memsize	= gd->ram_size;		/* size of DRAM in bytes */
-
-	memcpy(id, (void *)gd, sizeof(gd_t));
-
-	relocate_code(addr_sp, id, addr);
-
-	/* NOTREACHED - relocate_code() does not return */
-}
-
-/*
- * This is the next part if the initialization sequence: we are now
- * running from RAM and have a "normal" C environment, i. e. global
- * data can be written, BSS has been cleared, the stack size in not
- * that critical any more, etc.
- */
-
-void board_init_r(gd_t *id, ulong dest_addr)
-{
-#ifndef CONFIG_SYS_NO_FLASH
-	ulong size;
-#endif
-	bd_t *bd;
-
-	gd = id;
-	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
-
-	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
-
-	gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
-
-	monitor_flash_len = image_copy_end() - dest_addr;
-
-	serial_initialize();
-
-	bd = gd->bd;
-
-	/* The Malloc area is immediately below the monitor copy in DRAM */
-	mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
-			TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN);
-
-#ifndef CONFIG_SYS_NO_FLASH
-	/* configure available FLASH banks */
-	size = flash_init();
-	display_flash_config(size);
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-	bd->bi_flashsize = size;
-
-#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
-	bd->bi_flashoffset = monitor_flash_len;	/* reserved area for U-Boot */
-#else
-	bd->bi_flashoffset = 0;
-#endif
-#else
-	bd->bi_flashstart = 0;
-	bd->bi_flashsize = 0;
-	bd->bi_flashoffset = 0;
-#endif
-
-#ifdef CONFIG_CMD_NAND
-	puts("NAND:  ");
-	nand_init();		/* go init the NAND */
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
-	onenand_init();
-#endif
-
-	/* relocate environment function pointers etc. */
-	env_relocate();
-
-#if defined(CONFIG_PCI)
-	/*
-	 * Do pci configuration
-	 */
-	pci_init();
-#endif
-
-/** leave this here (after malloc(), environment and PCI are working) **/
-	/* Initialize stdio devices */
-	stdio_init();
-
-	jumptable_init();
-
-	/* Initialize the console (after the relocation and devices init) */
-	console_init_r();
-/** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/
-
-	/* Initialize from environment */
-	load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-#ifdef CONFIG_CMD_SPI
-	puts("SPI:   ");
-	spi_init();		/* go init the SPI */
-	puts("ready\n");
-#endif
-
-#if defined(CONFIG_MISC_INIT_R)
-	/* miscellaneous platform dependent initialisations */
-	misc_init_r();
-#endif
-
-#ifdef CONFIG_BITBANGMII
-	bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
-	puts("Net:   ");
-	eth_initialize(gd->bd);
-#endif
-
-	/* main_loop() can return to retry autoboot, if so just run it again. */
-	for (;;)
-		main_loop();
-
-	/* NOTREACHED - no way out of command loop except booting */
-}
diff --git a/qemu/roms/u-boot/arch/mips/lib/bootm.c b/qemu/roms/u-boot/arch/mips/lib/bootm.c
deleted file mode 100644
index 71bb0d2a1..000000000
--- a/qemu/roms/u-boot/arch/mips/lib/bootm.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <u-boot/zlib.h>
-#include <asm/byteorder.h>
-#include <asm/addrspace.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define	LINUX_MAX_ENVS		256
-#define	LINUX_MAX_ARGS		256
-
-#if defined(CONFIG_MALTA)
-#define mips_boot_malta		1
-#else
-#define mips_boot_malta		0
-#endif
-
-static int linux_argc;
-static char **linux_argv;
-static char *linux_argp;
-
-static char **linux_env;
-static char *linux_env_p;
-static int linux_env_idx;
-
-static ulong arch_get_sp(void)
-{
-	ulong ret;
-
-	__asm__ __volatile__("move %0, $sp" : "=r"(ret) : );
-
-	return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
-	ulong sp;
-
-	sp = arch_get_sp();
-	debug("## Current stack ends at 0x%08lx\n", sp);
-
-	/* adjust sp by 4K to be safe */
-	sp -= 4096;
-	lmb_reserve(lmb, sp, CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp);
-}
-
-static void linux_cmdline_init(void)
-{
-	linux_argc = 1;
-	linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
-	linux_argv[0] = 0;
-	linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
-}
-
-static void linux_cmdline_set(const char *value, size_t len)
-{
-	linux_argv[linux_argc] = linux_argp;
-	memcpy(linux_argp, value, len);
-	linux_argp[len] = 0;
-
-	linux_argp += len + 1;
-	linux_argc++;
-}
-
-static void linux_cmdline_dump(void)
-{
-	int i;
-
-	debug("## cmdline argv at 0x%p, argp at 0x%p\n",
-	      linux_argv, linux_argp);
-
-	for (i = 1; i < linux_argc; i++)
-		debug("   arg %03d: %s\n", i, linux_argv[i]);
-}
-
-static void boot_cmdline_linux(bootm_headers_t *images)
-{
-	const char *bootargs, *next, *quote;
-
-	linux_cmdline_init();
-
-	bootargs = getenv("bootargs");
-	if (!bootargs)
-		return;
-
-	next = bootargs;
-
-	while (bootargs && *bootargs && linux_argc < LINUX_MAX_ARGS) {
-		quote = strchr(bootargs, '"');
-		next = strchr(bootargs, ' ');
-
-		while (next && quote && quote < next) {
-			/*
-			 * we found a left quote before the next blank
-			 * now we have to find the matching right quote
-			 */
-			next = strchr(quote + 1, '"');
-			if (next) {
-				quote = strchr(next + 1, '"');
-				next = strchr(next + 1, ' ');
-			}
-		}
-
-		if (!next)
-			next = bootargs + strlen(bootargs);
-
-		linux_cmdline_set(bootargs, next - bootargs);
-
-		if (*next)
-			next++;
-
-		bootargs = next;
-	}
-
-	linux_cmdline_dump();
-}
-
-static void linux_env_init(void)
-{
-	linux_env = (char **)(((ulong) linux_argp + 15) & ~15);
-	linux_env[0] = 0;
-	linux_env_p = (char *)(linux_env + LINUX_MAX_ENVS);
-	linux_env_idx = 0;
-}
-
-static void linux_env_set(const char *env_name, const char *env_val)
-{
-	if (linux_env_idx < LINUX_MAX_ENVS - 1) {
-		linux_env[linux_env_idx] = linux_env_p;
-
-		strcpy(linux_env_p, env_name);
-		linux_env_p += strlen(env_name);
-
-		if (mips_boot_malta) {
-			linux_env_p++;
-			linux_env[++linux_env_idx] = linux_env_p;
-		} else {
-			*linux_env_p++ = '=';
-		}
-
-		strcpy(linux_env_p, env_val);
-		linux_env_p += strlen(env_val);
-
-		linux_env_p++;
-		linux_env[++linux_env_idx] = 0;
-	}
-}
-
-static void boot_prep_linux(bootm_headers_t *images)
-{
-	char env_buf[12];
-	const char *cp;
-	ulong rd_start, rd_size;
-
-#ifdef CONFIG_MEMSIZE_IN_BYTES
-	sprintf(env_buf, "%lu", (ulong)gd->ram_size);
-	debug("## Giving linux memsize in bytes, %lu\n", (ulong)gd->ram_size);
-#else
-	sprintf(env_buf, "%lu", (ulong)(gd->ram_size >> 20));
-	debug("## Giving linux memsize in MB, %lu\n",
-	      (ulong)(gd->ram_size >> 20));
-#endif /* CONFIG_MEMSIZE_IN_BYTES */
-
-	rd_start = UNCACHED_SDRAM(images->initrd_start);
-	rd_size = images->initrd_end - images->initrd_start;
-
-	linux_env_init();
-
-	linux_env_set("memsize", env_buf);
-
-	sprintf(env_buf, "0x%08lX", rd_start);
-	linux_env_set("initrd_start", env_buf);
-
-	sprintf(env_buf, "0x%lX", rd_size);
-	linux_env_set("initrd_size", env_buf);
-
-	sprintf(env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart));
-	linux_env_set("flash_start", env_buf);
-
-	sprintf(env_buf, "0x%X", (uint) (gd->bd->bi_flashsize));
-	linux_env_set("flash_size", env_buf);
-
-	cp = getenv("ethaddr");
-	if (cp)
-		linux_env_set("ethaddr", cp);
-
-	cp = getenv("eth1addr");
-	if (cp)
-		linux_env_set("eth1addr", cp);
-
-	if (mips_boot_malta) {
-		sprintf(env_buf, "%un8r", gd->baudrate);
-		linux_env_set("modetty0", env_buf);
-	}
-}
-
-static void boot_jump_linux(bootm_headers_t *images)
-{
-	typedef void __noreturn (*kernel_entry_t)(int, ulong, ulong, ulong);
-	kernel_entry_t kernel = (kernel_entry_t) images->ep;
-	ulong linux_extra = 0;
-
-	debug("## Transferring control to Linux (at address %p) ...\n", kernel);
-
-	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
-	if (mips_boot_malta)
-		linux_extra = gd->ram_size;
-
-	/* we assume that the kernel is in place */
-	printf("\nStarting kernel ...\n\n");
-
-	kernel(linux_argc, (ulong)linux_argv, (ulong)linux_env, linux_extra);
-}
-
-int do_bootm_linux(int flag, int argc, char * const argv[],
-			bootm_headers_t *images)
-{
-	/* No need for those on MIPS */
-	if (flag & BOOTM_STATE_OS_BD_T)
-		return -1;
-
-	if (flag & BOOTM_STATE_OS_CMDLINE) {
-		boot_cmdline_linux(images);
-		return 0;
-	}
-
-	if (flag & BOOTM_STATE_OS_PREP) {
-		boot_prep_linux(images);
-		return 0;
-	}
-
-	if (flag & BOOTM_STATE_OS_GO) {
-		boot_jump_linux(images);
-		return 0;
-	}
-
-	boot_cmdline_linux(images);
-	boot_prep_linux(images);
-	boot_jump_linux(images);
-
-	/* does not return */
-	return 1;
-}
diff --git a/qemu/roms/u-boot/arch/mips/lib/io.c b/qemu/roms/u-boot/arch/mips/lib/io.c
deleted file mode 100644
index b2d4a094d..000000000
--- a/qemu/roms/u-boot/arch/mips/lib/io.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * mips_io_port_base is the begin of the address space to which x86 style
- * I/O ports are mapped.
- */
-const unsigned long mips_io_port_base = -1;
diff --git a/qemu/roms/u-boot/arch/mips/lib/libgcc.h b/qemu/roms/u-boot/arch/mips/lib/libgcc.h
deleted file mode 100644
index 05909d58e..000000000
--- a/qemu/roms/u-boot/arch/mips/lib/libgcc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef __ASM_LIBGCC_H
-#define __ASM_LIBGCC_H
-
-#include <asm/byteorder.h>
-
-typedef int word_type __attribute__ ((mode (__word__)));
-
-#ifdef __BIG_ENDIAN
-struct DWstruct {
-	int high, low;
-};
-#elif defined(__LITTLE_ENDIAN)
-struct DWstruct {
-	int low, high;
-};
-#else
-#error I feel sick.
-#endif
-
-typedef union {
-	struct DWstruct s;
-	long long ll;
-} DWunion;
-
-#endif /* __ASM_LIBGCC_H */
diff --git a/qemu/roms/u-boot/arch/mips/lib/lshrdi3.c b/qemu/roms/u-boot/arch/mips/lib/lshrdi3.c
deleted file mode 100644
index bb340accb..000000000
--- a/qemu/roms/u-boot/arch/mips/lib/lshrdi3.c
+++ /dev/null
@@ -1,25 +0,0 @@
-#include "libgcc.h"
-
-long long __lshrdi3(long long u, word_type b)
-{
-	DWunion uu, w;
-	word_type bm;
-
-	if (b == 0)
-		return u;
-
-	uu.ll = u;
-	bm = 32 - b;
-
-	if (bm <= 0) {
-		w.s.high = 0;
-		w.s.low = (unsigned int) uu.s.high >> -bm;
-	} else {
-		const unsigned int carries = (unsigned int) uu.s.high << bm;
-
-		w.s.high = (unsigned int) uu.s.high >> b;
-		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
-	}
-
-	return w.ll;
-}
author	RajithaY <rajithax.yerrumsetty@intel.com>	2017-04-25 03:31:15 -0700
committer	Rajitha Yerrumchetty <rajithax.yerrumsetty@intel.com>	2017-05-22 06:48:08 +0000
commit	bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch)
tree	ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/u-boot/arch/mips
parent	a14b48d18a9ed03ec191cf16b162206998a895ce (diff)