diff options
| author |   RajithaY <rajithax.yerrumsetty@intel.com> | 2017-04-25 03:31:15 -0700 |
|---|---|---|
| committer | Rajitha Yerrumchetty <rajithax.yerrumsetty@intel.com> | 2017-05-22 06:48:08 +0000 |
| commit | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch) | |
| tree | ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/u-boot/arch/avr32 | |
| parent | a14b48d18a9ed03ec191cf16b162206998a895ce (diff) | |
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/arch/avr32')
54 files changed, 0 insertions, 4566 deletions
diff --git a/qemu/roms/u-boot/arch/avr32/config.mk b/qemu/roms/u-boot/arch/avr32/config.mk deleted file mode 100644 index 28a371c80..000000000 --- a/qemu/roms/u-boot/arch/avr32/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := avr32-linux- -endif - -PLATFORM_CPPFLAGS += -DCONFIG_AVR32 -CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 - -PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections - -LDFLAGS_u-boot = --gc-sections --relax diff --git a/qemu/roms/u-boot/arch/avr32/cpu/Makefile b/qemu/roms/u-boot/arch/avr32/cpu/Makefile deleted file mode 100644 index 5e1172125..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2005-2006 Atmel Corporation. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y += start.o - -obj-y += cpu.o -obj-$(CONFIG_SYS_HSDRAMC) += hsdramc.o -obj-y += exception.o -obj-y += cache.o -obj-y += interrupts.o -obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o -obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o diff --git a/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/Makefile b/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/Makefile deleted file mode 100644 index 06f18963e..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (C) 2005-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := portmux.o clk.o mmu.o diff --git a/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/clk.c b/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/clk.c deleted file mode 100644 index d5dbe3b90..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/clk.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2005-2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> - -#include <asm/arch/clk.h> -#include <asm/arch/hardware.h> -#include <asm/arch/portmux.h> - -#include "sm.h" - -void clk_init(void) -{ - uint32_t cksel; - - /* in case of soft resets, disable watchdog */ - sm_writel(WDT_CTRL, SM_BF(KEY, 0x55)); - sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa)); - -#ifdef CONFIG_PLL - /* Initialize the PLL */ - sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES) - | SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1) - | SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1) - | SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT) - | SM_BF(PLLOSC, 0) - | SM_BIT(PLLEN))); - - /* Wait for lock */ - while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ; -#endif - - /* Set up clocks for the CPU and all peripheral buses */ - cksel = 0; - if (CONFIG_SYS_CLKDIV_CPU) - cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1); - if (CONFIG_SYS_CLKDIV_HSB) - cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1); - if (CONFIG_SYS_CLKDIV_PBA) - cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1); - if (CONFIG_SYS_CLKDIV_PBB) - cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1); - sm_writel(PM_CKSEL, cksel); - -#ifdef CONFIG_PLL - /* Use PLL0 as main clock */ - sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); - -#ifdef CONFIG_LCD - /* Set up pixel clock for the LCDC */ - sm_writel(PM_GCCTRL(7), SM_BIT(PLLSEL) | SM_BIT(CEN)); -#endif -#endif -} - -unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, - unsigned long rate, unsigned long parent_rate) -{ - unsigned long divider; - - if (rate == 0 || parent_rate == 0) { - sm_writel(PM_GCCTRL(id), 0); - return 0; - } - - divider = (parent_rate + rate / 2) / rate; - if (divider <= 1) { - sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN)); - rate = parent_rate; - } else { - divider = min(255, divider / 2 - 1); - sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN) - | SM_BF(DIV, divider)); - rate = parent_rate / (2 * (divider + 1)); - } - - return rate; -} diff --git a/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/mmu.c b/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/mmu.c deleted file mode 100644 index 0e28b21ee..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/mmu.c +++ /dev/null @@ -1,78 +0,0 @@ -#include <common.h> -#include <asm/arch/mmu.h> -#include <asm/sysreg.h> - -void mmu_init_r(unsigned long dest_addr) -{ - uintptr_t vmr_table_addr; - - /* Round monitor address down to the nearest page boundary */ - dest_addr &= PAGE_ADDR_MASK; - - /* Initialize TLB entry 0 to cover the monitor, and lock it */ - sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V)); - sysreg_write(TLBELO, dest_addr | MMU_VMR_CACHE_WRBACK); - sysreg_write(MMUCR, SYSREG_BF(DRP, 0) | SYSREG_BF(DLA, 1) - | SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M)); - __builtin_tlbw(); - - /* - * Calculate the address of the VM range table in a PC-relative - * manner to make sure we hit the SDRAM and not the flash. - */ - vmr_table_addr = (uintptr_t)&mmu_vmr_table; - sysreg_write(PTBR, vmr_table_addr); - printf("VMR table @ 0x%08lx\n", vmr_table_addr); - - /* Enable paging */ - sysreg_write(MMUCR, SYSREG_BF(DRP, 1) | SYSREG_BF(DLA, 1) - | SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M) | SYSREG_BIT(E)); -} - -int mmu_handle_tlb_miss(void) -{ - const struct mmu_vm_range *vmr_table; - const struct mmu_vm_range *vmr; - unsigned int fault_pgno; - int first, last; - - fault_pgno = sysreg_read(TLBEAR) >> PAGE_SHIFT; - vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR); - - /* Do a binary search through the VM ranges */ - first = 0; - last = CONFIG_SYS_NR_VM_REGIONS; - while (first < last) { - unsigned int start; - int middle; - - /* Pick the entry in the middle of the remaining range */ - middle = (first + last) >> 1; - vmr = &vmr_table[middle]; - start = vmr->virt_pgno; - - /* Do the bisection thing */ - if (fault_pgno < start) { - last = middle; - } else if (fault_pgno >= (start + vmr->nr_pages)) { - first = middle + 1; - } else { - /* Got it; let's slam it into the TLB */ - uint32_t tlbelo; - - tlbelo = vmr->phys & ~PAGE_ADDR_MASK; - tlbelo |= fault_pgno << PAGE_SHIFT; - sysreg_write(TLBELO, tlbelo); - __builtin_tlbw(); - - /* Zero means success */ - return 0; - } - } - - /* - * Didn't find any matching entries. Return a nonzero value to - * indicate that this should be treated as a fatal exception. - */ - return -1; -} diff --git a/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/portmux.c b/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/portmux.c deleted file mode 100644 index 58327bac8..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/portmux.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> - -#include <asm/arch/chip-features.h> -#include <asm/arch/hardware.h> -#include <asm/arch/portmux.h> - -/* - * Lots of small functions here. We depend on --gc-sections getting - * rid of the ones we don't need. - */ -void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, - unsigned long flags, unsigned long drive_strength) -{ - unsigned long porte_mask = 0; - - if (bus_width > 16) - portmux_select_peripheral(PORTMUX_PORT_E, 0xffff, - PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); - if (addr_width > 23) - porte_mask |= (((1 << (addr_width - 23)) - 1) & 7) << 16; - if (flags & PORTMUX_EBI_CS(2)) - porte_mask |= 1 << 25; - if (flags & PORTMUX_EBI_CS(4)) - porte_mask |= 1 << 21; - if (flags & PORTMUX_EBI_CS(5)) - porte_mask |= 1 << 22; - if (flags & (PORTMUX_EBI_CF(0) | PORTMUX_EBI_CF(1))) - porte_mask |= (1 << 19) | (1 << 20) | (1 << 23); - - portmux_select_peripheral(PORTMUX_PORT_E, porte_mask, - PORTMUX_FUNC_A, 0); - - if (flags & PORTMUX_EBI_NWAIT) - portmux_select_peripheral(PORTMUX_PORT_E, 1 << 24, - PORTMUX_FUNC_A, PORTMUX_PULL_UP); -} - -#ifdef AT32AP700x_CHIP_HAS_MACB -void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength) -{ - unsigned long portc_mask; - - portc_mask = (1 << 3) /* TXD0 */ - | (1 << 4) /* TXD1 */ - | (1 << 7) /* TXEN */ - | (1 << 8) /* TXCK */ - | (1 << 9) /* RXD0 */ - | (1 << 10) /* RXD1 */ - | (1 << 13) /* RXER */ - | (1 << 15) /* RXDV */ - | (1 << 16) /* MDC */ - | (1 << 17); /* MDIO */ - - if (flags & PORTMUX_MACB_MII) - portc_mask |= (1 << 0) /* COL */ - | (1 << 1) /* CRS */ - | (1 << 2) /* TXER */ - | (1 << 5) /* TXD2 */ - | (1 << 6) /* TXD3 */ - | (1 << 11) /* RXD2 */ - | (1 << 12) /* RXD3 */ - | (1 << 14); /* RXCK */ - - if (flags & PORTMUX_MACB_SPEED) - portc_mask |= (1 << 18);/* SPD */ - - /* REVISIT: Some pins are probably pure outputs */ - portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, - PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); -} - -void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength) -{ - unsigned long portc_mask = 0; - unsigned long portd_mask; - - portd_mask = (1 << 13) /* TXD0 */ - | (1 << 14) /* TXD1 */ - | (1 << 11) /* TXEN */ - | (1 << 12) /* TXCK */ - | (1 << 10) /* RXD0 */ - | (1 << 6) /* RXD1 */ - | (1 << 5) /* RXER */ - | (1 << 4) /* RXDV */ - | (1 << 3) /* MDC */ - | (1 << 2); /* MDIO */ - - if (flags & PORTMUX_MACB_MII) - portc_mask = (1 << 19) /* COL */ - | (1 << 23) /* CRS */ - | (1 << 26) /* TXER */ - | (1 << 27) /* TXD2 */ - | (1 << 28) /* TXD3 */ - | (1 << 29) /* RXD2 */ - | (1 << 30) /* RXD3 */ - | (1 << 24); /* RXCK */ - - if (flags & PORTMUX_MACB_SPEED) - portd_mask |= (1 << 15);/* SPD */ - - /* REVISIT: Some pins are probably pure outputs */ - portmux_select_peripheral(PORTMUX_PORT_D, portd_mask, - PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); - portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, - PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_MMCI -void portmux_enable_mmci(unsigned int slot, unsigned long flags, - unsigned long drive_strength) -{ - unsigned long mask; - unsigned long portmux_flags = PORTMUX_PULL_UP; - - /* First, the common CLK signal. It doesn't need a pull-up */ - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 10, - PORTMUX_FUNC_A, 0); - - if (flags & PORTMUX_MMCI_EXT_PULLUP) - portmux_flags = 0; - - /* Then, the per-slot signals */ - switch (slot) { - case 0: - mask = (1 << 11) | (1 << 12); /* CMD and DATA0 */ - if (flags & PORTMUX_MMCI_4BIT) - /* DATA1..DATA3 */ - mask |= (1 << 13) | (1 << 14) | (1 << 15); - portmux_select_peripheral(PORTMUX_PORT_A, mask, - PORTMUX_FUNC_A, portmux_flags); - break; - case 1: - mask = (1 << 6) | (1 << 7); /* CMD and DATA0 */ - if (flags & PORTMUX_MMCI_4BIT) - /* DATA1..DATA3 */ - mask |= (1 << 8) | (1 << 9) | (1 << 10); - portmux_select_peripheral(PORTMUX_PORT_B, mask, - PORTMUX_FUNC_B, portmux_flags); - break; - } -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_SPI -void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength) -{ - unsigned long pin_mask; - - /* MOSI and SCK */ - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 1) | (1 << 2), - PORTMUX_FUNC_A, 0); - /* MISO may float */ - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 0, - PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); - - /* Set up NPCSx as GPIO outputs, initially high */ - pin_mask = (cs_mask & 7) << 3; - if (cs_mask & (1 << 3)) - pin_mask |= 1 << 20; - - portmux_select_gpio(PORTMUX_PORT_A, pin_mask, - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); -} - -void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength) -{ - /* MOSI and SCK */ - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 1) | (1 << 5), - PORTMUX_FUNC_B, 0); - /* MISO may float */ - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 0, - PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); - - /* Set up NPCSx as GPIO outputs, initially high */ - portmux_select_gpio(PORTMUX_PORT_B, (cs_mask & 7) << 2, - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); - portmux_select_gpio(PORTMUX_PORT_A, (cs_mask & 8) << (27 - 3), - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_LCDC -void portmux_enable_lcdc(int pin_config) -{ - unsigned long portc_mask = 0; - unsigned long portd_mask = 0; - unsigned long porte_mask = 0; - - switch (pin_config) { - case 0: - portc_mask = (1 << 19) /* CC */ - | (1 << 20) /* HSYNC */ - | (1 << 21) /* PCLK */ - | (1 << 22) /* VSYNC */ - | (1 << 23) /* DVAL */ - | (1 << 24) /* MODE */ - | (1 << 25) /* PWR */ - | (1 << 26) /* DATA0 */ - | (1 << 27) /* DATA1 */ - | (1 << 28) /* DATA2 */ - | (1 << 29) /* DATA3 */ - | (1 << 30) /* DATA4 */ - | (1 << 31); /* DATA5 */ - - portd_mask = (1 << 0) /* DATA6 */ - | (1 << 1) /* DATA7 */ - | (1 << 2) /* DATA8 */ - | (1 << 3) /* DATA9 */ - | (1 << 4) /* DATA10 */ - | (1 << 5) /* DATA11 */ - | (1 << 6) /* DATA12 */ - | (1 << 7) /* DATA13 */ - | (1 << 8) /* DATA14 */ - | (1 << 9) /* DATA15 */ - | (1 << 10) /* DATA16 */ - | (1 << 11) /* DATA17 */ - | (1 << 12) /* DATA18 */ - | (1 << 13) /* DATA19 */ - | (1 << 14) /* DATA20 */ - | (1 << 15) /* DATA21 */ - | (1 << 16) /* DATA22 */ - | (1 << 17); /* DATA23 */ - break; - - case 1: - portc_mask = (1 << 20) /* HSYNC */ - | (1 << 21) /* PCLK */ - | (1 << 22) /* VSYNC */ - | (1 << 25) /* PWR */ - | (1 << 31); /* DATA5 */ - - portd_mask = (1 << 0) /* DATA6 */ - | (1 << 1) /* DATA7 */ - | (1 << 7) /* DATA13 */ - | (1 << 8) /* DATA14 */ - | (1 << 9) /* DATA15 */ - | (1 << 16) /* DATA22 */ - | (1 << 17); /* DATA23 */ - - porte_mask = (1 << 0) /* CC */ - | (1 << 1) /* DVAL */ - | (1 << 2) /* MODE */ - | (1 << 3) /* DATA0 */ - | (1 << 4) /* DATA1 */ - | (1 << 5) /* DATA2 */ - | (1 << 6) /* DATA3 */ - | (1 << 7) /* DATA4 */ - | (1 << 8) /* DATA8 */ - | (1 << 9) /* DATA9 */ - | (1 << 10) /* DATA10 */ - | (1 << 11) /* DATA11 */ - | (1 << 12) /* DATA12 */ - | (1 << 13) /* DATA16 */ - | (1 << 14) /* DATA17 */ - | (1 << 15) /* DATA18 */ - | (1 << 16) /* DATA19 */ - | (1 << 17) /* DATA20 */ - | (1 << 18); /* DATA21 */ - break; - } - - /* REVISIT: Some pins are probably pure outputs */ - portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, - PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); - portmux_select_peripheral(PORTMUX_PORT_D, portd_mask, - PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); - portmux_select_peripheral(PORTMUX_PORT_E, porte_mask, - PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); -} -#endif diff --git a/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/sm.h b/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/sm.h deleted file mode 100644 index 9a3804efe..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/at32ap700x/sm.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Register definitions for System Manager - */ -#ifndef __CPU_AT32AP_SM_H__ -#define __CPU_AT32AP_SM_H__ - -/* SM register offsets */ -#define SM_PM_MCCTRL 0x0000 -#define SM_PM_CKSEL 0x0004 -#define SM_PM_CPU_MASK 0x0008 -#define SM_PM_HSB_MASK 0x000c -#define SM_PM_PBA_MASK 0x0010 -#define SM_PM_PBB_MASK 0x0014 -#define SM_PM_PLL0 0x0020 -#define SM_PM_PLL1 0x0024 -#define SM_PM_VCTRL 0x0030 -#define SM_PM_VMREF 0x0034 -#define SM_PM_VMV 0x0038 -#define SM_PM_IER 0x0040 -#define SM_PM_IDR 0x0044 -#define SM_PM_IMR 0x0048 -#define SM_PM_ISR 0x004c -#define SM_PM_ICR 0x0050 -#define SM_PM_GCCTRL(x) (0x0060 + 4 * x) -#define SM_RTC_CTRL 0x0080 -#define SM_RTC_VAL 0x0084 -#define SM_RTC_TOP 0x0088 -#define SM_RTC_IER 0x0090 -#define SM_RTC_IDR 0x0094 -#define SM_RTC_IMR 0x0098 -#define SM_RTC_ISR 0x009c -#define SM_RTC_ICR 0x00a0 -#define SM_WDT_CTRL 0x00b0 -#define SM_WDT_CLR 0x00b4 -#define SM_WDT_EXT 0x00b8 -#define SM_RC_RCAUSE 0x00c0 -#define SM_EIM_IER 0x0100 -#define SM_EIM_IDR 0x0104 -#define SM_EIM_IMR 0x0108 -#define SM_EIM_ISR 0x010c -#define SM_EIM_ICR 0x0110 -#define SM_EIM_MODE 0x0114 -#define SM_EIM_EDGE 0x0118 -#define SM_EIM_LEVEL 0x011c -#define SM_EIM_TEST 0x0120 -#define SM_EIM_NMIC 0x0124 - -/* Bitfields in PM_CKSEL */ -#define SM_CPUSEL_OFFSET 0 -#define SM_CPUSEL_SIZE 3 -#define SM_CPUDIV_OFFSET 7 -#define SM_CPUDIV_SIZE 1 -#define SM_HSBSEL_OFFSET 8 -#define SM_HSBSEL_SIZE 3 -#define SM_HSBDIV_OFFSET 15 -#define SM_HSBDIV_SIZE 1 -#define SM_PBASEL_OFFSET 16 -#define SM_PBASEL_SIZE 3 -#define SM_PBADIV_OFFSET 23 -#define SM_PBADIV_SIZE 1 -#define SM_PBBSEL_OFFSET 24 -#define SM_PBBSEL_SIZE 3 -#define SM_PBBDIV_OFFSET 31 -#define SM_PBBDIV_SIZE 1 - -/* Bitfields in PM_PLL0 */ -#define SM_PLLEN_OFFSET 0 -#define SM_PLLEN_SIZE 1 -#define SM_PLLOSC_OFFSET 1 -#define SM_PLLOSC_SIZE 1 -#define SM_PLLOPT_OFFSET 2 -#define SM_PLLOPT_SIZE 3 -#define SM_PLLDIV_OFFSET 8 -#define SM_PLLDIV_SIZE 8 -#define SM_PLLMUL_OFFSET 16 -#define SM_PLLMUL_SIZE 8 -#define SM_PLLCOUNT_OFFSET 24 -#define SM_PLLCOUNT_SIZE 6 -#define SM_PLLTEST_OFFSET 31 -#define SM_PLLTEST_SIZE 1 - -/* Bitfields in PM_VCTRL */ -#define SM_VAUTO_OFFSET 0 -#define SM_VAUTO_SIZE 1 -#define SM_PM_VCTRL_VAL_OFFSET 8 -#define SM_PM_VCTRL_VAL_SIZE 7 - -/* Bitfields in PM_VMREF */ -#define SM_REFSEL_OFFSET 0 -#define SM_REFSEL_SIZE 4 - -/* Bitfields in PM_VMV */ -#define SM_PM_VMV_VAL_OFFSET 0 -#define SM_PM_VMV_VAL_SIZE 8 - -/* Bitfields in PM_ICR */ -#define SM_LOCK0_OFFSET 0 -#define SM_LOCK0_SIZE 1 -#define SM_LOCK1_OFFSET 1 -#define SM_LOCK1_SIZE 1 -#define SM_WAKE_OFFSET 2 -#define SM_WAKE_SIZE 1 -#define SM_VOK_OFFSET 3 -#define SM_VOK_SIZE 1 -#define SM_VMRDY_OFFSET 4 -#define SM_VMRDY_SIZE 1 -#define SM_CKRDY_OFFSET 5 -#define SM_CKRDY_SIZE 1 - -/* Bitfields in PM_GCCTRL */ -#define SM_OSCSEL_OFFSET 0 -#define SM_OSCSEL_SIZE 1 -#define SM_PLLSEL_OFFSET 1 -#define SM_PLLSEL_SIZE 1 -#define SM_CEN_OFFSET 2 -#define SM_CEN_SIZE 1 -#define SM_CPC_OFFSET 3 -#define SM_CPC_SIZE 1 -#define SM_DIVEN_OFFSET 4 -#define SM_DIVEN_SIZE 1 -#define SM_DIV_OFFSET 8 -#define SM_DIV_SIZE 8 - -/* Bitfields in RTC_CTRL */ -#define SM_PCLR_OFFSET 1 -#define SM_PCLR_SIZE 1 -#define SM_TOPEN_OFFSET 2 -#define SM_TOPEN_SIZE 1 -#define SM_CLKEN_OFFSET 3 -#define SM_CLKEN_SIZE 1 -#define SM_PSEL_OFFSET 8 -#define SM_PSEL_SIZE 16 - -/* Bitfields in RTC_VAL */ -#define SM_RTC_VAL_VAL_OFFSET 0 -#define SM_RTC_VAL_VAL_SIZE 31 - -/* Bitfields in RTC_TOP */ -#define SM_RTC_TOP_VAL_OFFSET 0 -#define SM_RTC_TOP_VAL_SIZE 32 - -/* Bitfields in RTC_ICR */ -#define SM_TOPI_OFFSET 0 -#define SM_TOPI_SIZE 1 - -/* Bitfields in WDT_CTRL */ -#define SM_KEY_OFFSET 24 -#define SM_KEY_SIZE 8 - -/* Bitfields in RC_RCAUSE */ -#define SM_POR_OFFSET 0 -#define SM_POR_SIZE 1 -#define SM_BOD_OFFSET 1 -#define SM_BOD_SIZE 1 -#define SM_EXT_OFFSET 2 -#define SM_EXT_SIZE 1 -#define SM_WDT_OFFSET 3 -#define SM_WDT_SIZE 1 -#define SM_NTAE_OFFSET 4 -#define SM_NTAE_SIZE 1 -#define SM_SERP_OFFSET 5 -#define SM_SERP_SIZE 1 - -/* Bitfields in EIM_EDGE */ -#define SM_INT0_OFFSET 0 -#define SM_INT0_SIZE 1 -#define SM_INT1_OFFSET 1 -#define SM_INT1_SIZE 1 -#define SM_INT2_OFFSET 2 -#define SM_INT2_SIZE 1 -#define SM_INT3_OFFSET 3 -#define SM_INT3_SIZE 1 - -/* Bitfields in EIM_LEVEL */ - -/* Bitfields in EIM_TEST */ -#define SM_TESTEN_OFFSET 31 -#define SM_TESTEN_SIZE 1 - -/* Bitfields in EIM_NMIC */ -#define SM_EN_OFFSET 0 -#define SM_EN_SIZE 1 - -/* Bit manipulation macros */ -#define SM_BIT(name) \ - (1 << SM_##name##_OFFSET) -#define SM_BF(name,value) \ - (((value) & ((1 << SM_##name##_SIZE) - 1)) \ - << SM_##name##_OFFSET) -#define SM_BFEXT(name,value) \ - (((value) >> SM_##name##_OFFSET) \ - & ((1 << SM_##name##_SIZE) - 1)) -#define SM_BFINS(name,value,old) \ - (((old) & ~(((1 << SM_##name##_SIZE) - 1) \ - << SM_##name##_OFFSET)) \ - | SM_BF(name,value)) - -/* Register access macros */ -#define sm_readl(reg) \ - readl((void *)ATMEL_BASE_SM + SM_##reg) -#define sm_writel(reg,value) \ - writel((value), (void *)ATMEL_BASE_SM + SM_##reg) - -#endif /* __CPU_AT32AP_SM_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/cpu/cache.c b/qemu/roms/u-boot/arch/avr32/cpu/cache.c deleted file mode 100644 index ab0374e58..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/cache.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#include <asm/arch/cacheflush.h> - -void dcache_clean_range(volatile void *start, size_t size) -{ - unsigned long v, begin, end, linesz; - - linesz = CONFIG_SYS_DCACHE_LINESZ; - - /* You asked for it, you got it */ - begin = (unsigned long)start & ~(linesz - 1); - end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); - - for (v = begin; v < end; v += linesz) - dcache_clean_line((void *)v); - - sync_write_buffer(); -} - -void dcache_invalidate_range(volatile void *start, size_t size) -{ - unsigned long v, begin, end, linesz; - - linesz = CONFIG_SYS_DCACHE_LINESZ; - - /* You asked for it, you got it */ - begin = (unsigned long)start & ~(linesz - 1); - end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); - - for (v = begin; v < end; v += linesz) - dcache_invalidate_line((void *)v); -} - -void dcache_flush_range(volatile void *start, size_t size) -{ - unsigned long v, begin, end, linesz; - - linesz = CONFIG_SYS_DCACHE_LINESZ; - - /* You asked for it, you got it */ - begin = (unsigned long)start & ~(linesz - 1); - end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); - - for (v = begin; v < end; v += linesz) - dcache_flush_line((void *)v); - - sync_write_buffer(); -} - -void icache_invalidate_range(volatile void *start, size_t size) -{ - unsigned long v, begin, end, linesz; - - linesz = CONFIG_SYS_ICACHE_LINESZ; - - /* You asked for it, you got it */ - begin = (unsigned long)start & ~(linesz - 1); - end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); - - for (v = begin; v < end; v += linesz) - icache_invalidate_line((void *)v); -} - -/* - * This is called after loading something into memory. We need to - * make sure that everything that was loaded is actually written to - * RAM, and that the icache will look for it. Cleaning the dcache and - * invalidating the icache will do the trick. - */ -void flush_cache (unsigned long start_addr, unsigned long size) -{ - dcache_clean_range((void *)start_addr, size); - icache_invalidate_range((void *)start_addr, size); -} diff --git a/qemu/roms/u-boot/arch/avr32/cpu/config.mk b/qemu/roms/u-boot/arch/avr32/cpu/config.mk deleted file mode 100644 index 3d2d817f8..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/config.mk +++ /dev/null @@ -1,6 +0,0 @@ -# -# Copyright (C) 2005-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# -PLATFORM_RELFLAGS += -mcpu=ap7000 diff --git a/qemu/roms/u-boot/arch/avr32/cpu/cpu.c b/qemu/roms/u-boot/arch/avr32/cpu/cpu.c deleted file mode 100644 index cef630ed4..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/cpu.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> - -#include <asm/io.h> -#include <asm/sections.h> -#include <asm/sysreg.h> - -#include <asm/arch/clk.h> -#include <asm/arch/hardware.h> - -#include "hsmc3.h" - -/* Sanity checks */ -#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB) \ - || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA) \ - || (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB) -# error Constraint fCPU >= fHSB >= fPB{A,B} violated -#endif -#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1)) -# error Invalid PLL multiplier and/or divider -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int cpu_init(void) -{ - extern void _evba(void); - - gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ; - - /* TODO: Move somewhere else, but needs to be run before we - * increase the clock frequency. */ - hsmc3_writel(MODE0, 0x00031103); - hsmc3_writel(CYCLE0, 0x000c000d); - hsmc3_writel(PULSE0, 0x0b0a0906); - hsmc3_writel(SETUP0, 0x00010002); - - clk_init(); - - /* Update the CPU speed according to the PLL configuration */ - gd->arch.cpu_hz = get_cpu_clk_rate(); - - /* Set up the exception handler table and enable exceptions */ - sysreg_write(EVBA, (unsigned long)&_evba); - asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); - - return 0; -} - -void prepare_to_boot(void) -{ - /* Flush both caches and the write buffer */ - asm volatile("cache %0[4], 010\n\t" - "cache %0[0], 000\n\t" - "sync 0" : : "r"(0) : "memory"); -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - /* This will reset the CPU core, caches, MMU and all internal busses */ - __builtin_mtdr(8, 1 << 13); /* set DC:DBE */ - __builtin_mtdr(8, 1 << 30); /* set DC:RES */ - - /* Flush the pipeline before we declare it a failure */ - asm volatile("sub pc, pc, -4"); - - return -1; -} diff --git a/qemu/roms/u-boot/arch/avr32/cpu/exception.c b/qemu/roms/u-boot/arch/avr32/cpu/exception.c deleted file mode 100644 index 5d1bc689f..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/exception.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/sysreg.h> -#include <asm/ptrace.h> - -DECLARE_GLOBAL_DATA_PTR; - -static const char * const cpu_modes[8] = { - "Application", "Supervisor", "Interrupt level 0", "Interrupt level 1", - "Interrupt level 2", "Interrupt level 3", "Exception", "NMI" -}; - -static void dump_mem(const char *str, unsigned long bottom, unsigned long top) -{ - unsigned long p; - int i; - - printf("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); - - for (p = bottom & ~31; p < top; ) { - printf("%04lx: ", p & 0xffff); - - for (i = 0; i < 8; i++, p += 4) { - unsigned int val; - - if (p < bottom || p >= top) - printf(" "); - else { - val = *(unsigned long *)p; - printf("%08x ", val); - } - } - printf("\n"); - } -} - -void do_unknown_exception(unsigned int ecr, struct pt_regs *regs) -{ - unsigned int mode; - - printf("\n *** Unhandled exception %u at PC=0x%08lx [%08lx]\n", - ecr, regs->pc, regs->pc - gd->reloc_off); - - switch (ecr) { - case ECR_BUS_ERROR_WRITE: - case ECR_BUS_ERROR_READ: - printf("Bus error at address 0x%08lx\n", - sysreg_read(BEAR)); - break; - case ECR_TLB_MULTIPLE: - case ECR_ADDR_ALIGN_X: - case ECR_PROTECTION_X: - case ECR_ADDR_ALIGN_R: - case ECR_ADDR_ALIGN_W: - case ECR_PROTECTION_R: - case ECR_PROTECTION_W: - case ECR_DTLB_MODIFIED: - case ECR_TLB_MISS_X: - case ECR_TLB_MISS_R: - case ECR_TLB_MISS_W: - printf("MMU exception at address 0x%08lx\n", - sysreg_read(TLBEAR)); - break; - } - - printf(" pc: %08lx lr: %08lx sp: %08lx r12: %08lx\n", - regs->pc, regs->lr, regs->sp, regs->r12); - printf(" r11: %08lx r10: %08lx r9: %08lx r8: %08lx\n", - regs->r11, regs->r10, regs->r9, regs->r8); - printf(" r7: %08lx r6: %08lx r5: %08lx r4: %08lx\n", - regs->r7, regs->r6, regs->r5, regs->r4); - printf(" r3: %08lx r2: %08lx r1: %08lx r0: %08lx\n", - regs->r3, regs->r2, regs->r1, regs->r0); - printf("Flags: %c%c%c%c%c\n", - regs->sr & SR_Q ? 'Q' : 'q', - regs->sr & SR_V ? 'V' : 'v', - regs->sr & SR_N ? 'N' : 'n', - regs->sr & SR_Z ? 'Z' : 'z', - regs->sr & SR_C ? 'C' : 'c'); - printf("Mode bits: %c%c%c%c%c%c%c%c%c\n", - regs->sr & SR_H ? 'H' : 'h', - regs->sr & SR_R ? 'R' : 'r', - regs->sr & SR_J ? 'J' : 'j', - regs->sr & SR_EM ? 'E' : 'e', - regs->sr & SR_I3M ? '3' : '.', - regs->sr & SR_I2M ? '2' : '.', - regs->sr & SR_I1M ? '1' : '.', - regs->sr & SR_I0M ? '0' : '.', - regs->sr & SR_GM ? 'G' : 'g'); - mode = (regs->sr >> SYSREG_M0_OFFSET) & 7; - printf("CPU Mode: %s\n", cpu_modes[mode]); - - /* Avoid exception loops */ - if (regs->sp < (gd->arch.stack_end - CONFIG_STACKSIZE) - || regs->sp >= gd->arch.stack_end) - printf("\nStack pointer seems bogus, won't do stack dump\n"); - else - dump_mem("\nStack: ", regs->sp, gd->arch.stack_end); - - panic("Unhandled exception\n"); -} diff --git a/qemu/roms/u-boot/arch/avr32/cpu/hsdramc.c b/qemu/roms/u-boot/arch/avr32/cpu/hsdramc.c deleted file mode 100644 index 7e4817203..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/hsdramc.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> -#include <asm/sdram.h> - -#include <asm/arch/clk.h> -#include <asm/arch/hardware.h> - -#include "hsdramc1.h" - -unsigned long sdram_init(void *sdram_base, const struct sdram_config *config) -{ - unsigned long sdram_size; - uint32_t cfgreg; - unsigned int i; - - cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8) - | HSDRAMC1_BF(NR, config->row_bits - 11) - | HSDRAMC1_BF(NB, config->bank_bits - 1) - | HSDRAMC1_BF(CAS, config->cas) - | HSDRAMC1_BF(TWR, config->twr) - | HSDRAMC1_BF(TRC, config->trc) - | HSDRAMC1_BF(TRP, config->trp) - | HSDRAMC1_BF(TRCD, config->trcd) - | HSDRAMC1_BF(TRAS, config->tras) - | HSDRAMC1_BF(TXSR, config->txsr)); - - if (config->data_bits == SDRAM_DATA_16BIT) - cfgreg |= HSDRAMC1_BIT(DBW); - - hsdramc1_writel(CR, cfgreg); - - /* Send a NOP to turn on the clock (necessary on some chips) */ - hsdramc1_writel(MR, HSDRAMC1_MODE_NOP); - hsdramc1_readl(MR); - writel(0, sdram_base); - - /* - * Initialization sequence for SDRAM, from the data sheet: - * - * 1. A minimum pause of 200 us is provided to precede any - * signal toggle. - */ - udelay(200); - - /* - * 2. A Precharge All command is issued to the SDRAM - */ - hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE); - hsdramc1_readl(MR); - writel(0, sdram_base); - - /* - * 3. Eight auto-refresh (CBR) cycles are provided - */ - hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH); - hsdramc1_readl(MR); - for (i = 0; i < 8; i++) - writel(0, sdram_base); - - /* - * 4. A mode register set (MRS) cycle is issued to program - * SDRAM parameters, in particular CAS latency and burst - * length. - * - * The address will be chosen by the SDRAMC automatically; we - * just have to make sure BA[1:0] are set to 0. - */ - hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE); - hsdramc1_readl(MR); - writel(0, sdram_base); - - /* - * 5. The application must go into Normal Mode, setting Mode - * to 0 in the Mode Register and performing a write access - * at any location in the SDRAM. - */ - hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL); - hsdramc1_readl(MR); - writel(0, sdram_base); - - /* - * 6. Write refresh rate into SDRAMC refresh timer count - * register (refresh rate = timing between refresh cycles). - */ - hsdramc1_writel(TR, config->refresh_period); - - if (config->data_bits == SDRAM_DATA_16BIT) - sdram_size = 1 << (config->row_bits + config->col_bits - + config->bank_bits + 1); - else - sdram_size = 1 << (config->row_bits + config->col_bits - + config->bank_bits + 2); - - return sdram_size; -} diff --git a/qemu/roms/u-boot/arch/avr32/cpu/hsdramc1.h b/qemu/roms/u-boot/arch/avr32/cpu/hsdramc1.h deleted file mode 100644 index e18e074a7..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/hsdramc1.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Register definitions for SDRAM Controller - */ -#ifndef __ASM_AVR32_HSDRAMC1_H__ -#define __ASM_AVR32_HSDRAMC1_H__ - -/* HSDRAMC1 register offsets */ -#define HSDRAMC1_MR 0x0000 -#define HSDRAMC1_TR 0x0004 -#define HSDRAMC1_CR 0x0008 -#define HSDRAMC1_HSR 0x000c -#define HSDRAMC1_LPR 0x0010 -#define HSDRAMC1_IER 0x0014 -#define HSDRAMC1_IDR 0x0018 -#define HSDRAMC1_IMR 0x001c -#define HSDRAMC1_ISR 0x0020 -#define HSDRAMC1_MDR 0x0024 -#define HSDRAMC1_VERSION 0x00fc - -/* Bitfields in MR */ -#define HSDRAMC1_MODE_OFFSET 0 -#define HSDRAMC1_MODE_SIZE 3 - -/* Bitfields in TR */ -#define HSDRAMC1_COUNT_OFFSET 0 -#define HSDRAMC1_COUNT_SIZE 12 - -/* Bitfields in CR */ -#define HSDRAMC1_NC_OFFSET 0 -#define HSDRAMC1_NC_SIZE 2 -#define HSDRAMC1_NR_OFFSET 2 -#define HSDRAMC1_NR_SIZE 2 -#define HSDRAMC1_NB_OFFSET 4 -#define HSDRAMC1_NB_SIZE 1 -#define HSDRAMC1_CAS_OFFSET 5 -#define HSDRAMC1_CAS_SIZE 2 -#define HSDRAMC1_DBW_OFFSET 7 -#define HSDRAMC1_DBW_SIZE 1 -#define HSDRAMC1_TWR_OFFSET 8 -#define HSDRAMC1_TWR_SIZE 4 -#define HSDRAMC1_TRC_OFFSET 12 -#define HSDRAMC1_TRC_SIZE 4 -#define HSDRAMC1_TRP_OFFSET 16 -#define HSDRAMC1_TRP_SIZE 4 -#define HSDRAMC1_TRCD_OFFSET 20 -#define HSDRAMC1_TRCD_SIZE 4 -#define HSDRAMC1_TRAS_OFFSET 24 -#define HSDRAMC1_TRAS_SIZE 4 -#define HSDRAMC1_TXSR_OFFSET 28 -#define HSDRAMC1_TXSR_SIZE 4 - -/* Bitfields in HSR */ -#define HSDRAMC1_DA_OFFSET 0 -#define HSDRAMC1_DA_SIZE 1 - -/* Bitfields in LPR */ -#define HSDRAMC1_LPCB_OFFSET 0 -#define HSDRAMC1_LPCB_SIZE 2 -#define HSDRAMC1_PASR_OFFSET 4 -#define HSDRAMC1_PASR_SIZE 3 -#define HSDRAMC1_TCSR_OFFSET 8 -#define HSDRAMC1_TCSR_SIZE 2 -#define HSDRAMC1_DS_OFFSET 10 -#define HSDRAMC1_DS_SIZE 2 -#define HSDRAMC1_TIMEOUT_OFFSET 12 -#define HSDRAMC1_TIMEOUT_SIZE 2 - -/* Bitfields in IDR */ -#define HSDRAMC1_RES_OFFSET 0 -#define HSDRAMC1_RES_SIZE 1 - -/* Bitfields in MDR */ -#define HSDRAMC1_MD_OFFSET 0 -#define HSDRAMC1_MD_SIZE 2 - -/* Bitfields in VERSION */ -#define HSDRAMC1_VERSION_OFFSET 0 -#define HSDRAMC1_VERSION_SIZE 12 -#define HSDRAMC1_MFN_OFFSET 16 -#define HSDRAMC1_MFN_SIZE 3 - -/* Constants for MODE */ -#define HSDRAMC1_MODE_NORMAL 0 -#define HSDRAMC1_MODE_NOP 1 -#define HSDRAMC1_MODE_BANKS_PRECHARGE 2 -#define HSDRAMC1_MODE_LOAD_MODE 3 -#define HSDRAMC1_MODE_AUTO_REFRESH 4 -#define HSDRAMC1_MODE_EXT_LOAD_MODE 5 -#define HSDRAMC1_MODE_POWER_DOWN 6 - -/* Constants for NC */ -#define HSDRAMC1_NC_8_COLUMN_BITS 0 -#define HSDRAMC1_NC_9_COLUMN_BITS 1 -#define HSDRAMC1_NC_10_COLUMN_BITS 2 -#define HSDRAMC1_NC_11_COLUMN_BITS 3 - -/* Constants for NR */ -#define HSDRAMC1_NR_11_ROW_BITS 0 -#define HSDRAMC1_NR_12_ROW_BITS 1 -#define HSDRAMC1_NR_13_ROW_BITS 2 - -/* Constants for NB */ -#define HSDRAMC1_NB_TWO_BANKS 0 -#define HSDRAMC1_NB_FOUR_BANKS 1 - -/* Constants for CAS */ -#define HSDRAMC1_CAS_ONE_CYCLE 1 -#define HSDRAMC1_CAS_TWO_CYCLES 2 - -/* Constants for DBW */ -#define HSDRAMC1_DBW_32_BITS 0 -#define HSDRAMC1_DBW_16_BITS 1 - -/* Constants for TIMEOUT */ -#define HSDRAMC1_TIMEOUT_AFTER_END 0 -#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END 1 -#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END 2 - -/* Constants for MD */ -#define HSDRAMC1_MD_SDRAM 0 -#define HSDRAMC1_MD_LOW_POWER_SDRAM 1 - -/* Bit manipulation macros */ -#define HSDRAMC1_BIT(name) \ - (1 << HSDRAMC1_##name##_OFFSET) -#define HSDRAMC1_BF(name,value) \ - (((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1)) \ - << HSDRAMC1_##name##_OFFSET) -#define HSDRAMC1_BFEXT(name,value) \ - (((value) >> HSDRAMC1_##name##_OFFSET) \ - & ((1 << HSDRAMC1_##name##_SIZE) - 1)) -#define HSDRAMC1_BFINS(name,value,old) \ - (((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1) \ - << HSDRAMC1_##name##_OFFSET)) \ - | HSDRAMC1_BF(name,value)) - -/* Register access macros */ -#define hsdramc1_readl(reg) \ - readl((void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg) -#define hsdramc1_writel(reg,value) \ - writel((value), (void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg) - -#endif /* __ASM_AVR32_HSDRAMC1_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/cpu/hsmc3.h b/qemu/roms/u-boot/arch/avr32/cpu/hsmc3.h deleted file mode 100644 index ac472952a..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/hsmc3.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Register definitions for Static Memory Controller - */ -#ifndef __CPU_AT32AP_HSMC3_H__ -#define __CPU_AT32AP_HSMC3_H__ - -/* HSMC3 register offsets */ -#define HSMC3_SETUP0 0x0000 -#define HSMC3_PULSE0 0x0004 -#define HSMC3_CYCLE0 0x0008 -#define HSMC3_MODE0 0x000c -#define HSMC3_SETUP1 0x0010 -#define HSMC3_PULSE1 0x0014 -#define HSMC3_CYCLE1 0x0018 -#define HSMC3_MODE1 0x001c -#define HSMC3_SETUP2 0x0020 -#define HSMC3_PULSE2 0x0024 -#define HSMC3_CYCLE2 0x0028 -#define HSMC3_MODE2 0x002c -#define HSMC3_SETUP3 0x0030 -#define HSMC3_PULSE3 0x0034 -#define HSMC3_CYCLE3 0x0038 -#define HSMC3_MODE3 0x003c -#define HSMC3_SETUP4 0x0040 -#define HSMC3_PULSE4 0x0044 -#define HSMC3_CYCLE4 0x0048 -#define HSMC3_MODE4 0x004c -#define HSMC3_SETUP5 0x0050 -#define HSMC3_PULSE5 0x0054 -#define HSMC3_CYCLE5 0x0058 -#define HSMC3_MODE5 0x005c - -/* Bitfields in SETUP0 */ -#define HSMC3_NWE_SETUP_OFFSET 0 -#define HSMC3_NWE_SETUP_SIZE 6 -#define HSMC3_NCS_WR_SETUP_OFFSET 8 -#define HSMC3_NCS_WR_SETUP_SIZE 6 -#define HSMC3_NRD_SETUP_OFFSET 16 -#define HSMC3_NRD_SETUP_SIZE 6 -#define HSMC3_NCS_RD_SETUP_OFFSET 24 -#define HSMC3_NCS_RD_SETUP_SIZE 6 - -/* Bitfields in PULSE0 */ -#define HSMC3_NWE_PULSE_OFFSET 0 -#define HSMC3_NWE_PULSE_SIZE 7 -#define HSMC3_NCS_WR_PULSE_OFFSET 8 -#define HSMC3_NCS_WR_PULSE_SIZE 7 -#define HSMC3_NRD_PULSE_OFFSET 16 -#define HSMC3_NRD_PULSE_SIZE 7 -#define HSMC3_NCS_RD_PULSE_OFFSET 24 -#define HSMC3_NCS_RD_PULSE_SIZE 7 - -/* Bitfields in CYCLE0 */ -#define HSMC3_NWE_CYCLE_OFFSET 0 -#define HSMC3_NWE_CYCLE_SIZE 9 -#define HSMC3_NRD_CYCLE_OFFSET 16 -#define HSMC3_NRD_CYCLE_SIZE 9 - -/* Bitfields in MODE0 */ -#define HSMC3_READ_MODE_OFFSET 0 -#define HSMC3_READ_MODE_SIZE 1 -#define HSMC3_WRITE_MODE_OFFSET 1 -#define HSMC3_WRITE_MODE_SIZE 1 -#define HSMC3_EXNW_MODE_OFFSET 4 -#define HSMC3_EXNW_MODE_SIZE 2 -#define HSMC3_BAT_OFFSET 8 -#define HSMC3_BAT_SIZE 1 -#define HSMC3_DBW_OFFSET 12 -#define HSMC3_DBW_SIZE 2 -#define HSMC3_TDF_CYCLES_OFFSET 16 -#define HSMC3_TDF_CYCLES_SIZE 4 -#define HSMC3_TDF_MODE_OFFSET 20 -#define HSMC3_TDF_MODE_SIZE 1 -#define HSMC3_PMEN_OFFSET 24 -#define HSMC3_PMEN_SIZE 1 -#define HSMC3_PS_OFFSET 28 -#define HSMC3_PS_SIZE 2 - -/* Bitfields in MODE1 */ -#define HSMC3_PD_OFFSET 28 -#define HSMC3_PD_SIZE 2 - -/* Constants for READ_MODE */ -#define HSMC3_READ_MODE_NCS_CONTROLLED 0 -#define HSMC3_READ_MODE_NRD_CONTROLLED 1 - -/* Constants for WRITE_MODE */ -#define HSMC3_WRITE_MODE_NCS_CONTROLLED 0 -#define HSMC3_WRITE_MODE_NWE_CONTROLLED 1 - -/* Constants for EXNW_MODE */ -#define HSMC3_EXNW_MODE_DISABLED 0 -#define HSMC3_EXNW_MODE_RESERVED 1 -#define HSMC3_EXNW_MODE_FROZEN 2 -#define HSMC3_EXNW_MODE_READY 3 - -/* Constants for BAT */ -#define HSMC3_BAT_BYTE_SELECT 0 -#define HSMC3_BAT_BYTE_WRITE 1 - -/* Constants for DBW */ -#define HSMC3_DBW_8_BITS 0 -#define HSMC3_DBW_16_BITS 1 -#define HSMC3_DBW_32_BITS 2 - -/* Bit manipulation macros */ -#define HSMC3_BIT(name) \ - (1 << HSMC3_##name##_OFFSET) -#define HSMC3_BF(name,value) \ - (((value) & ((1 << HSMC3_##name##_SIZE) - 1)) \ - << HSMC3_##name##_OFFSET) -#define HSMC3_BFEXT(name,value) \ - (((value) >> HSMC3_##name##_OFFSET) \ - & ((1 << HSMC3_##name##_SIZE) - 1)) -#define HSMC3_BFINS(name,value,old)\ - (((old) & ~(((1 << HSMC3_##name##_SIZE) - 1) \ - << HSMC3_##name##_OFFSET)) \ - | HSMC3_BF(name,value)) - -/* Register access macros */ -#define hsmc3_readl(reg) \ - readl((void *)ATMEL_BASE_HSMC + HSMC3_##reg) -#define hsmc3_writel(reg,value) \ - writel((value), (void *)ATMEL_BASE_HSMC + HSMC3_##reg) - -#endif /* __CPU_AT32AP_HSMC3_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/cpu/interrupts.c b/qemu/roms/u-boot/arch/avr32/cpu/interrupts.c deleted file mode 100644 index 4a03e19e3..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/interrupts.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <div64.h> - -#include <asm/errno.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/sysreg.h> - -#include <asm/arch/hardware.h> - -#define HANDLER_MASK 0x00ffffff -#define INTLEV_SHIFT 30 -#define INTLEV_MASK 0x00000003 - -DECLARE_GLOBAL_DATA_PTR; - -/* Incremented whenever COUNT reaches 0xffffffff by timer_interrupt_handler */ -volatile unsigned long timer_overflow; - -/* - * Instead of dividing by get_tbclk(), multiply by this constant and - * right-shift the result by 32 bits. - */ -static unsigned long tb_factor; - -unsigned long get_tbclk(void) -{ - return gd->arch.cpu_hz; -} - -unsigned long long get_ticks(void) -{ - unsigned long lo, hi_now, hi_prev; - - do { - hi_prev = timer_overflow; - lo = sysreg_read(COUNT); - hi_now = timer_overflow; - } while (hi_prev != hi_now); - - return ((unsigned long long)hi_now << 32) | lo; -} - -unsigned long get_timer(unsigned long base) -{ - u64 now = get_ticks(); - - now *= tb_factor; - return (unsigned long)(now >> 32) - base; -} - -/* - * For short delays only. It will overflow after a few seconds. - */ -void __udelay(unsigned long usec) -{ - unsigned long cycles; - unsigned long base; - unsigned long now; - - base = sysreg_read(COUNT); - cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100; - - do { - now = sysreg_read(COUNT); - } while ((now - base) < cycles); -} - -static int set_interrupt_handler(unsigned int nr, void (*handler)(void), - unsigned int priority) -{ - extern void _evba(void); - unsigned long intpr; - unsigned long handler_addr = (unsigned long)handler; - - handler_addr -= (unsigned long)&_evba; - - if ((handler_addr & HANDLER_MASK) != handler_addr - || (priority & INTLEV_MASK) != priority) - return -EINVAL; - - intpr = (handler_addr & HANDLER_MASK); - intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT; - writel(intpr, (void *)ATMEL_BASE_INTC + 4 * nr); - - return 0; -} - -int timer_init(void) -{ - extern void timer_interrupt_handler(void); - u64 tmp; - - sysreg_write(COUNT, 0); - - tmp = (u64)CONFIG_SYS_HZ << 32; - tmp += gd->arch.cpu_hz / 2; - do_div(tmp, gd->arch.cpu_hz); - tb_factor = (u32)tmp; - - if (set_interrupt_handler(0, &timer_interrupt_handler, 3)) - return -EINVAL; - - /* For all practical purposes, this gives us an overflow interrupt */ - sysreg_write(COMPARE, 0xffffffff); - return 0; -} diff --git a/qemu/roms/u-boot/arch/avr32/cpu/portmux-gpio.c b/qemu/roms/u-boot/arch/avr32/cpu/portmux-gpio.c deleted file mode 100644 index 640852c2c..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/portmux-gpio.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/gpio.h> - -void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags) -{ - /* Both pull-up and pull-down set means buskeeper */ - if (flags & PORTMUX_PULL_DOWN) - gpio_writel(port, PDERS, pin_mask); - else - gpio_writel(port, PDERC, pin_mask); - if (flags & PORTMUX_PULL_UP) - gpio_writel(port, PUERS, pin_mask); - else - gpio_writel(port, PUERC, pin_mask); - - /* Select drive strength */ - if (flags & PORTMUX_DRIVE_LOW) - gpio_writel(port, ODCR0S, pin_mask); - else - gpio_writel(port, ODCR0C, pin_mask); - if (flags & PORTMUX_DRIVE_HIGH) - gpio_writel(port, ODCR1S, pin_mask); - else - gpio_writel(port, ODCR1C, pin_mask); - - /* Select function */ - if (func & PORTMUX_FUNC_B) - gpio_writel(port, PMR0S, pin_mask); - else - gpio_writel(port, PMR0C, pin_mask); - if (func & PORTMUX_FUNC_C) - gpio_writel(port, PMR1S, pin_mask); - else - gpio_writel(port, PMR1C, pin_mask); - - /* Disable GPIO (i.e. enable peripheral) */ - gpio_writel(port, GPERC, pin_mask); -} - -void portmux_select_gpio(void *port, unsigned long pin_mask, - unsigned long flags) -{ - /* Both pull-up and pull-down set means buskeeper */ - if (flags & PORTMUX_PULL_DOWN) - gpio_writel(port, PDERS, pin_mask); - else - gpio_writel(port, PDERC, pin_mask); - if (flags & PORTMUX_PULL_UP) - gpio_writel(port, PUERS, pin_mask); - else - gpio_writel(port, PUERC, pin_mask); - - /* Enable open-drain mode if requested */ - if (flags & PORTMUX_OPEN_DRAIN) - gpio_writel(port, ODMERS, pin_mask); - else - gpio_writel(port, ODMERC, pin_mask); - - /* Select drive strength */ - if (flags & PORTMUX_DRIVE_LOW) - gpio_writel(port, ODCR0S, pin_mask); - else - gpio_writel(port, ODCR0C, pin_mask); - if (flags & PORTMUX_DRIVE_HIGH) - gpio_writel(port, ODCR1S, pin_mask); - else - gpio_writel(port, ODCR1C, pin_mask); - - /* Select direction and initial pin state */ - if (flags & PORTMUX_DIR_OUTPUT) { - if (flags & PORTMUX_INIT_HIGH) - gpio_writel(port, OVRS, pin_mask); - else - gpio_writel(port, OVRC, pin_mask); - gpio_writel(port, ODERS, pin_mask); - } else { - gpio_writel(port, ODERC, pin_mask); - } - - /* Enable GPIO */ - gpio_writel(port, GPERS, pin_mask); -} diff --git a/qemu/roms/u-boot/arch/avr32/cpu/portmux-pio.c b/qemu/roms/u-boot/arch/avr32/cpu/portmux-pio.c deleted file mode 100644 index 8ce51e64d..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/portmux-pio.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/gpio.h> - -void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags) -{ - if (flags & PORTMUX_PULL_UP) - pio_writel(port, PUER, pin_mask); - else - pio_writel(port, PUDR, pin_mask); - - switch (func) { - case PORTMUX_FUNC_A: - pio_writel(port, ASR, pin_mask); - break; - case PORTMUX_FUNC_B: - pio_writel(port, BSR, pin_mask); - break; - } - - pio_writel(port, PDR, pin_mask); -} - -void portmux_select_gpio(void *port, unsigned long pin_mask, - unsigned long flags) -{ - if (flags & PORTMUX_PULL_UP) - pio_writel(port, PUER, pin_mask); - else - pio_writel(port, PUDR, pin_mask); - - if (flags & PORTMUX_OPEN_DRAIN) - pio_writel(port, MDER, pin_mask); - else - pio_writel(port, MDDR, pin_mask); - - if (flags & PORTMUX_DIR_OUTPUT) { - if (flags & PORTMUX_INIT_HIGH) - pio_writel(port, SODR, pin_mask); - else - pio_writel(port, CODR, pin_mask); - pio_writel(port, OER, pin_mask); - } else { - pio_writel(port, ODR, pin_mask); - } - - pio_writel(port, PER, pin_mask); -} - -void pio_set_output_value(unsigned int pin, int value) -{ - void *port = pio_pin_to_port(pin); - - if (!port) - panic("Invalid GPIO pin %u\n", pin); - - __pio_set_output_value(port, pin & 0x1f, value); -} - -int pio_get_input_value(unsigned int pin) -{ - void *port = pio_pin_to_port(pin); - - if (!port) - panic("Invalid GPIO pin %u\n", pin); - - return __pio_get_input_value(port, pin & 0x1f); -} diff --git a/qemu/roms/u-boot/arch/avr32/cpu/start.S b/qemu/roms/u-boot/arch/avr32/cpu/start.S deleted file mode 100644 index 14a0269a5..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/start.S +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright (C) 2005-2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <asm-offsets.h> -#include <config.h> -#include <asm/ptrace.h> -#include <asm/sysreg.h> - -#define SYSREG_MMUCR_I_OFFSET 2 -#define SYSREG_MMUCR_S_OFFSET 4 - -#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0)) -/* due to errata (unreliable branch folding) clear FE bit explicitly */ -#define CPUCR_INIT ((SYSREG_BIT(BI) | SYSREG_BIT(BE) \ - | SYSREG_BIT(RE) | SYSREG_BIT(IBE) \ - | SYSREG_BIT(IEE)) & ~SYSREG_BIT(FE)) - - /* - * To save some space, we use the same entry point for - * exceptions and reset. This avoids lots of alignment padding - * since the reset vector is always suitably aligned. - */ - .section .exception.text, "ax", @progbits - .global _start - .global _evba - .type _start, @function - .type _evba, @function -_start: - .size _start, 0 -_evba: - .org 0x00 - rjmp unknown_exception /* Unrecoverable exception */ - .org 0x04 - rjmp unknown_exception /* TLB multiple hit */ - .org 0x08 - rjmp unknown_exception /* Bus error data fetch */ - .org 0x0c - rjmp unknown_exception /* Bus error instruction fetch */ - .org 0x10 - rjmp unknown_exception /* NMI */ - .org 0x14 - rjmp unknown_exception /* Instruction address */ - .org 0x18 - rjmp unknown_exception /* ITLB protection */ - .org 0x1c - rjmp unknown_exception /* Breakpoint */ - .org 0x20 - rjmp unknown_exception /* Illegal opcode */ - .org 0x24 - rjmp unknown_exception /* Unimplemented instruction */ - .org 0x28 - rjmp unknown_exception /* Privilege violation */ - .org 0x2c - rjmp unknown_exception /* Floating-point */ - .org 0x30 - rjmp unknown_exception /* Coprocessor absent */ - .org 0x34 - rjmp unknown_exception /* Data Address (read) */ - .org 0x38 - rjmp unknown_exception /* Data Address (write) */ - .org 0x3c - rjmp unknown_exception /* DTLB Protection (read) */ - .org 0x40 - rjmp unknown_exception /* DTLB Protection (write) */ - .org 0x44 - rjmp unknown_exception /* DTLB Modified */ - - .org 0x50 /* ITLB Miss */ - pushm r8-r12,lr - rjmp 1f - .org 0x60 /* DTLB Miss (read) */ - pushm r8-r12,lr - rjmp 1f - .org 0x70 /* DTLB Miss (write) */ - pushm r8-r12,lr -1: mov r12, sp - rcall mmu_handle_tlb_miss - popm r8-r12,lr - brne unknown_exception - rete - - .size _evba, . - _evba - - .align 2 - .type unknown_exception, @function -unknown_exception: - /* Figure out whether we're handling an exception (Exception - * mode) or just booting (Supervisor mode). */ - csrfcz SYSREG_M1_OFFSET - brcc at32ap_cpu_bootstrap - - /* This is an exception. Complain. */ - pushm r0-r12 - sub r8, sp, REG_R12 - REG_R0 - 4 - mov r9, lr - mfsr r10, SYSREG_RAR_EX - mfsr r11, SYSREG_RSR_EX - pushm r8-r11 - mfsr r12, SYSREG_ECR - mov r11, sp - rcall do_unknown_exception -1: rjmp 1b - - /* The COUNT/COMPARE timer interrupt handler */ - .global timer_interrupt_handler - .type timer_interrupt_handler,@function - .align 2 -timer_interrupt_handler: - /* - * Increment timer_overflow and re-write COMPARE with 0xffffffff. - * - * We're running at interrupt level 3, so we don't need to save - * r8-r12 or lr to the stack. - */ - lda.w r8, timer_overflow - ld.w r9, r8[0] - mov r10, -1 - mtsr SYSREG_COMPARE, r10 - sub r9, -1 - st.w r8[0], r9 - rete - - /* - * CPU bootstrap after reset is handled here. SoC code may - * override this in case they need to initialize oscillators, - * etc. - */ - .section .text.at32ap_cpu_bootstrap, "ax", @progbits - .global at32ap_cpu_bootstrap - .weak at32ap_cpu_bootstrap - .type at32ap_cpu_bootstrap, @function - .align 2 -at32ap_cpu_bootstrap: - /* Reset the Status Register */ - mov r0, lo(SR_INIT) - orh r0, hi(SR_INIT) - mtsr SYSREG_SR, r0 - - /* Reset CPUCR and invalidate the BTB */ - mov r2, CPUCR_INIT - mtsr SYSREG_CPUCR, r2 - - /* Flush the caches */ - mov r1, 0 - cache r1[4], 8 - cache r1[0], 0 - sync 0 - - /* Reset the MMU to default settings */ - mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I) - mtsr SYSREG_MMUCR, r0 - - /* Internal RAM should not need any initialization. We might - have to initialize external RAM here if the part doesn't - have internal RAM (or we may use the data cache) */ - - /* Jump to cacheable segment */ - lddpc pc, 1f - - .align 2 -1: .long at32ap_low_level_init - .size _start, . - _start - - /* Common CPU bootstrap code after oscillator/cache/etc. init */ - .section .text.avr32ap_low_level_init, "ax", @progbits - .global at32ap_low_level_init - .type at32ap_low_level_init, @function - .align 2 -at32ap_low_level_init: - lddpc sp, sp_init - - /* Initialize the GOT pointer */ - lddpc r6, got_init -3: rsub r6, pc - - /* Let's go */ - rjmp board_init_f - - .align 2 - .type sp_init,@object -sp_init: - .long CONFIG_SYS_INIT_SP_ADDR -got_init: - .long 3b - _GLOBAL_OFFSET_TABLE_ - - /* - * void relocate_code(new_sp, new_gd, monitor_addr) - * - * Relocate the u-boot image into RAM and continue from there. - * Does not return. - */ - .section .text.relocate_code,"ax",@progbits - .global relocate_code - .type relocate_code,@function -relocate_code: - mov sp, r12 /* use new stack */ - mov r12, r11 /* save new_gd */ - mov r11, r10 /* save destination address */ - - /* copy .text section and flush the cache along the way */ - lda.w r8, _text - lda.w r9, _etext - sub lr, r10, r8 /* relocation offset */ - -1: ldm r8++, r0-r3 - stm r10, r0-r3 - sub r10, -16 - ldm r8++, r0-r3 - stm r10, r0-r3 - sub r10, -16 - cp.w r8, r9 - cache r10[-4], 0x0d /* dcache clean/invalidate */ - cache r10[-4], 0x01 /* icache invalidate */ - brlt 1b - - /* flush write buffer */ - sync 0 - - /* copy data sections */ - lda.w r9, _edata -1: ld.d r0, r8++ - st.d r10++, r0 - cp.w r8, r9 - brlt 1b - - /* zero out .bss */ - mov r0, 0 - mov r1, 0 - lda.w r9, __bss_end - sub r9, r8 -1: st.d r10++, r0 - sub r9, 8 - brgt 1b - - /* jump to RAM */ - sub r0, pc, . - in_ram - add pc, r0, lr - - .align 2 -in_ram: - /* find the new GOT and relocate it */ - lddpc r6, got_init_reloc -3: rsub r6, pc - mov r8, r6 - lda.w r9, _egot - lda.w r10, _got - sub r9, r10 -1: ld.w r0, r8[0] - add r0, lr - st.w r8++, r0 - sub r9, 4 - brgt 1b - - /* Move the exception handlers */ - mfsr r2, SYSREG_EVBA - add r2, lr - mtsr SYSREG_EVBA, r2 - - /* Do the rest of the initialization sequence */ - call board_init_r - - .align 2 -got_init_reloc: - .long 3b - _GLOBAL_OFFSET_TABLE_ - - .size relocate_code, . - relocate_code diff --git a/qemu/roms/u-boot/arch/avr32/cpu/u-boot.lds b/qemu/roms/u-boot/arch/avr32/cpu/u-boot.lds deleted file mode 100644 index cb29a22b1..000000000 --- a/qemu/roms/u-boot/arch/avr32/cpu/u-boot.lds +++ /dev/null @@ -1,56 +0,0 @@ -/* -*- Fundamental -*- - * - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") -OUTPUT_ARCH(avr32) -ENTRY(_start) - -SECTIONS -{ - . = 0; - _text = .; - .text : { - *(.exception.text) - *(.text) - *(.text.*) - } - _etext = .; - - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - . = ALIGN(8); - _data = .; - .data : { - *(.data) - *(.data.*) - } - - . = ALIGN(4); - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - _got = .; - .got : { - *(.got) - } - _egot = .; - - . = ALIGN(8); - _edata = .; - - .bss (NOLOAD) : { - *(.bss) - *(.bss.*) - } - . = ALIGN(8); - __bss_end = .; -} diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/addrspace.h b/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/addrspace.h deleted file mode 100644 index 7b25e2efe..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/addrspace.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ADDRSPACE_H -#define __ASM_AVR32_ADDRSPACE_H - -#include <asm/types.h> - -/* Memory segments when segmentation is enabled */ -#define P0SEG 0x00000000 -#define P1SEG 0x80000000 -#define P2SEG 0xa0000000 -#define P3SEG 0xc0000000 -#define P4SEG 0xe0000000 - -/* Returns the privileged segment base of a given address */ -#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) - -/* Returns the physical address of a PnSEG (n=1,2) address */ -#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) - -/* - * Map an address to a certain privileged segment - */ -#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) -#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) -#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) -#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) - -/* virt_to_phys will only work when address is in P1 or P2 */ -static inline unsigned long virt_to_phys(volatile void *address) -{ - return PHYSADDR(address); -} - -static inline void * phys_to_virt(unsigned long address) -{ - return (void *)P1SEGADDR(address); -} - -#define cached(addr) ((void *)P1SEGADDR(addr)) -#define uncached(addr) ((void *)P2SEGADDR(addr)) - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - * - * This implementation works for memory below 512MiB (flash, etc.) as - * well as above 3.5GiB (internal peripherals.) - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (1 << 7) -#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) -#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0)) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -#endif /* __ASM_AVR32_ADDRSPACE_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h b/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h deleted file mode 100644 index 13d6d3aed..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_CACHEFLUSH_H -#define __ASM_AVR32_CACHEFLUSH_H - -/* - * Invalidate any cacheline containing virtual address vaddr without - * writing anything back to memory. - * - * Note that this function may corrupt unrelated data structures when - * applied on buffers that are not cacheline aligned in both ends. - */ -static inline void dcache_invalidate_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory"); -} - -/* - * Make sure any cacheline containing virtual address vaddr is written - * to memory. - */ -static inline void dcache_clean_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory"); -} - -/* - * Make sure any cacheline containing virtual address vaddr is written - * to memory and then invalidate it. - */ -static inline void dcache_flush_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory"); -} - -/* - * Invalidate any instruction cacheline containing virtual address - * vaddr. - */ -static inline void icache_invalidate_line(volatile void *vaddr) -{ - asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory"); -} - -/* - * Applies the above functions on all lines that are touched by the - * specified virtual address range. - */ -void dcache_invalidate_range(volatile void *start, size_t len); -void dcache_clean_range(volatile void *start, size_t len); -void dcache_flush_range(volatile void *start, size_t len); -void icache_invalidate_range(volatile void *start, size_t len); - -static inline void dcache_flush_unlocked(void) -{ - asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory"); -} - -/* - * Make sure any pending writes are completed before continuing. - */ -#define sync_write_buffer() asm volatile("sync 0" : : : "memory") - -#endif /* __ASM_AVR32_CACHEFLUSH_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/chip-features.h b/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/chip-features.h deleted file mode 100644 index 822286df5..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/chip-features.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2007 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__ -#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__ - -/* Currently, all the AP700x chips have these */ -#define AT32AP700x_CHIP_HAS_USART -#define AT32AP700x_CHIP_HAS_MMCI -#define AT32AP700x_CHIP_HAS_SPI - -/* Only AP7000 has ethernet interface */ -#ifdef CONFIG_AT32AP7000 -#define AT32AP700x_CHIP_HAS_MACB -#endif - -/* AP7000 and AP7002 have LCD controller, but AP7001 does not */ -#if defined(CONFIG_AT32AP7000) || defined(CONFIG_AT32AP7002) -#define AT32AP700x_CHIP_HAS_LCDC -#endif - -#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/clk.h b/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/clk.h deleted file mode 100644 index 0721899fd..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/clk.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ARCH_CLK_H__ -#define __ASM_AVR32_ARCH_CLK_H__ - -#include <asm/arch/chip-features.h> -#include <asm/arch/portmux.h> - -#ifdef CONFIG_PLL -#define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \ - * CONFIG_SYS_PLL0_MUL) -#define MAIN_CLK_RATE PLL0_RATE -#else -#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ) -#endif - -static inline unsigned long get_cpu_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU; -} -static inline unsigned long get_hsb_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB; -} -static inline unsigned long get_pba_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA; -} -static inline unsigned long get_pbb_clk_rate(void) -{ - return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB; -} - -/* Accessors for specific devices. More will be added as needed. */ -static inline unsigned long get_sdram_clk_rate(void) -{ - return get_hsb_clk_rate(); -} -#ifdef AT32AP700x_CHIP_HAS_USART -static inline unsigned long get_usart_clk_rate(unsigned int dev_id) -{ - return get_pba_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_MACB -static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) -{ - return get_pbb_clk_rate(); -} -static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) -{ - return get_hsb_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_MMCI -static inline unsigned long get_mci_clk_rate(void) -{ - return get_pbb_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_SPI -static inline unsigned long get_spi_clk_rate(unsigned int dev_id) -{ - return get_pba_clk_rate(); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_LCDC -static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) -{ - return get_hsb_clk_rate(); -} -#endif - -extern void clk_init(void); - -/* Board code may need the SDRAM base clock as a compile-time constant */ -#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB) - -/* Generic clock control */ -enum gclk_parent { - GCLK_PARENT_OSC0 = 0, - GCLK_PARENT_OSC1 = 1, - GCLK_PARENT_PLL0 = 2, - GCLK_PARENT_PLL1 = 3, -}; - -/* Some generic clocks have specific roles */ -#define GCLK_DAC_SAMPLE_CLK 6 -#define GCLK_LCDC_PIXCLK 7 - -extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, - unsigned long rate, unsigned long parent_rate); - -/** - * gclk_set_rate - configure and enable a generic clock - * @id: Which GCLK[id] to enable - * @parent: Parent clock feeding the GCLK - * @rate: Target rate of the GCLK in Hz - * - * Returns the actual GCLK rate in Hz, after rounding to the nearest - * supported rate. - * - * All three parameters are usually constant, hence the inline. - */ -static inline unsigned long gclk_set_rate(unsigned int id, - enum gclk_parent parent, unsigned long rate) -{ - unsigned long parent_rate; - - if (id > 7) - return 0; - - switch (parent) { - case GCLK_PARENT_OSC0: - parent_rate = CONFIG_SYS_OSC0_HZ; - break; -#ifdef CONFIG_SYS_OSC1_HZ - case GCLK_PARENT_OSC1: - parent_rate = CONFIG_SYS_OSC1_HZ; - break; -#endif -#ifdef PLL0_RATE - case GCLK_PARENT_PLL0: - parent_rate = PLL0_RATE; - break; -#endif -#ifdef PLL1_RATE - case GCLK_PARENT_PLL1: - parent_rate = PLL1_RATE; - break; -#endif - default: - parent_rate = 0; - break; - } - - return __gclk_set_rate(id, parent, rate, parent_rate); -} - -/** - * gclk_enable_output - enable output on a GCLK pin - * @id: Which GCLK[id] pin to enable - * @drive_strength: Drive strength of external GCLK pin, if applicable - */ -static inline void gclk_enable_output(unsigned int id, - unsigned long drive_strength) -{ - switch (id) { - case 0: - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, - PORTMUX_FUNC_A, drive_strength); - break; - case 1: - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31, - PORTMUX_FUNC_A, drive_strength); - break; - case 2: - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19, - PORTMUX_FUNC_A, drive_strength); - break; - case 3: - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29, - PORTMUX_FUNC_A, drive_strength); - break; - case 4: - portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30, - PORTMUX_FUNC_A, drive_strength); - break; - } -} - -#endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/gpio.h b/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/gpio.h deleted file mode 100644 index b5808c5d4..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/gpio.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ARCH_GPIO_H__ -#define __ASM_AVR32_ARCH_GPIO_H__ - -#include <asm/arch/chip-features.h> -#include <asm/arch/hardware.h> - -#define NR_GPIO_CONTROLLERS 5 - -/* - * Pin numbers identifying specific GPIO pins on the chip. - */ -#define GPIO_PIOA_BASE (0) -#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) -#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) -#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) -#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) -#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x)) -#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x)) -#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x)) -#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x)) -#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x)) - -static inline void *pio_pin_to_port(unsigned int pin) -{ - switch (pin >> 5) { - case 0: - return (void *)ATMEL_BASE_PIOA; - case 1: - return (void *)ATMEL_BASE_PIOB; - case 2: - return (void *)ATMEL_BASE_PIOC; - case 3: - return (void *)ATMEL_BASE_PIOD; - case 4: - return (void *)ATMEL_BASE_PIOE; - default: - return NULL; - } -} - -#include <asm/arch-common/portmux-pio.h> - -#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hardware.h b/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hardware.h deleted file mode 100644 index 58ae96525..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hardware.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __AT32AP7000_HARDWARE_H__ -#define __AT32AP7000_HARDWARE_H__ - -/* Internal and external memories */ -#define EBI_SRAM_CS0_BASE 0x00000000 -#define EBI_SRAM_CS0_SIZE 0x04000000 -#define EBI_SRAM_CS4_BASE 0x04000000 -#define EBI_SRAM_CS4_SIZE 0x04000000 -#define EBI_SRAM_CS2_BASE 0x08000000 -#define EBI_SRAM_CS2_SIZE 0x04000000 -#define EBI_SRAM_CS3_BASE 0x0c000000 -#define EBI_SRAM_CS3_SIZE 0x04000000 -#define EBI_SRAM_CS1_BASE 0x10000000 -#define EBI_SRAM_CS1_SIZE 0x10000000 -#define EBI_SRAM_CS5_BASE 0x20000000 -#define EBI_SRAM_CS5_SIZE 0x04000000 - -#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE -#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE - -#define INTERNAL_SRAM_BASE 0x24000000 -#define INTERNAL_SRAM_SIZE 0x00008000 - -/* Devices on the High Speed Bus (HSB) */ -#define LCDC_BASE 0xFF000000 -#define DMAC_BASE 0xFF200000 -#define USB_FIFO 0xFF300000 - -/* Devices on Peripheral Bus A (PBA) */ -#define ATMEL_BASE_SPI0 0xFFE00000 -#define ATMEL_BASE_SPI1 0xFFE00400 -#define ATMEL_BASE_TWI0 0xFFE00800 -#define ATMEL_BASE_USART0 0xFFE00C00 -#define ATMEL_BASE_USART1 0xFFE01000 -#define ATMEL_BASE_USART2 0xFFE01400 -#define ATMEL_BASE_USART3 0xFFE01800 -#define ATMEL_BASE_SSC0 0xFFE01C00 -#define ATMEL_BASE_SSC1 0xFFE02000 -#define ATMEL_BASE_SSC2 0xFFE02400 -#define ATMEL_BASE_PIOA 0xFFE02800 -#define ATMEL_BASE_PIOB 0xFFE02C00 -#define ATMEL_BASE_PIOC 0xFFE03000 -#define ATMEL_BASE_PIOD 0xFFE03400 -#define ATMEL_BASE_PIOE 0xFFE03800 -#define ATMEL_BASE_PSIF 0xFFE03C00 - -/* Devices on Peripheral Bus B (PBB) */ -#define ATMEL_BASE_SM 0xFFF00000 -#define ATMEL_BASE_INTC 0xFFF00400 -#define ATMEL_BASE_HMATRIX 0xFFF00800 -#define ATMEL_BASE_TIMER0 0xFFF00C00 -#define ATMEL_BASE_TIMER1 0xFFF01000 -#define ATMEL_BASE_PWM 0xFFF01400 -#define ATMEL_BASE_MACB0 0xFFF01800 -#define ATMEL_BASE_MACB1 0xFFF01C00 -#define ATMEL_BASE_DAC 0xFFF02000 -#define ATMEL_BASE_MMCI 0xFFF02400 -#define ATMEL_BASE_AUDIOC 0xFFF02800 -#define ATMEL_BASE_HISI 0xFFF02C00 -#define ATMEL_BASE_USB 0xFFF03000 -#define ATMEL_BASE_HSMC 0xFFF03400 -#define ATMEL_BASE_HSDRAMC 0xFFF03800 -#define ATMEL_BASE_ECC 0xFFF03C00 - -#endif /* __AT32AP7000_HARDWARE_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hmatrix.h b/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hmatrix.h deleted file mode 100644 index d2a733fa4..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/hmatrix.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ARCH_HMATRIX_H__ -#define __ASM_AVR32_ARCH_HMATRIX_H__ - -#include <asm/hmatrix-common.h> - -/* Bitfields in SFR4 (EBI) */ -#define HMATRIX_EBI_SDRAM_ENABLE_OFFSET 1 -#define HMATRIX_EBI_SDRAM_ENABLE_SIZE 1 -#define HMATRIX_EBI_NAND_ENABLE_OFFSET 3 -#define HMATRIX_EBI_NAND_ENABLE_SIZE 1 -#define HMATRIX_EBI_CF0_ENABLE_OFFSET 4 -#define HMATRIX_EBI_CF0_ENABLE_SIZE 1 -#define HMATRIX_EBI_CF1_ENABLE_OFFSET 5 -#define HMATRIX_EBI_CF1_ENABLE_SIZE 1 -#define HMATRIX_EBI_PULLUP_DISABLE_OFFSET 8 -#define HMATRIX_EBI_PULLUP_DISABLE_SIZE 1 - -/* HSB masters */ -#define HMATRIX_MASTER_CPU_DCACHE 0 -#define HMATRIX_MASTER_CPU_ICACHE 1 -#define HMATRIX_MASTER_PDC 2 -#define HMATRIX_MASTER_ISI 3 -#define HMATRIX_MASTER_USBA 4 -#define HMATRIX_MASTER_LCDC 5 -#define HMATRIX_MASTER_MACB0 6 -#define HMATRIX_MASTER_MACB1 7 -#define HMATRIX_MASTER_DMACA_M0 8 -#define HMATRIX_MASTER_DMACA_M1 9 - -/* HSB slaves */ -#define HMATRIX_SLAVE_SRAM0 0 -#define HMATRIX_SLAVE_SRAM1 1 -#define HMATRIX_SLAVE_PBA 2 -#define HMATRIX_SLAVE_PBB 3 -#define HMATRIX_SLAVE_EBI 4 -#define HMATRIX_SLAVE_USBA 5 -#define HMATRIX_SLAVE_LCDC 6 -#define HMATRIX_SLAVE_DMACA 7 - -#endif /* __ASM_AVR32_ARCH_HMATRIX_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/mmu.h b/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/mmu.h deleted file mode 100644 index fcd9a0560..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/mmu.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * In order to deal with the hardcoded u-boot requirement that virtual - * addresses are always mapped 1:1 with physical addresses, we implement - * a small virtual memory manager so that we can use the MMU hardware in - * order to get the caching properties right. - * - * A few pages (or possibly just one) are locked in the TLB permanently - * in order to avoid recursive TLB misses, but most pages are faulted in - * on demand. - */ -#ifndef __ASM_ARCH_MMU_H -#define __ASM_ARCH_MMU_H - -#include <asm/sysreg.h> - -#define PAGE_SHIFT 20 -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1)) - -#define MMU_VMR_CACHE_NONE \ - (SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D)) -#define MMU_VMR_CACHE_WBUF \ - (MMU_VMR_CACHE_NONE | SYSREG_BIT(B)) -#define MMU_VMR_CACHE_WRTHRU \ - (MMU_VMR_CACHE_NONE | SYSREG_BIT(TLBELO_C) | SYSREG_BIT(W)) -#define MMU_VMR_CACHE_WRBACK \ - (MMU_VMR_CACHE_WBUF | SYSREG_BIT(TLBELO_C)) - -/* - * This structure is used in our "page table". Instead of the usual - * x86-inspired radix tree, we let each entry cover an arbitrary-sized - * virtual address range and store them in a binary search tree. This is - * somewhat slower, but should use significantly less RAM, and we - * shouldn't get many TLB misses when using 1 MB pages anyway. - * - * With 1 MB pages, we need 12 bits to store the page number. In - * addition, we stick an Invalid bit in the high bit of virt_pgno (if - * set, it cannot possibly match any faulting page), and all the bits - * that need to be written to TLBELO in phys_pgno. - */ -struct mmu_vm_range { - uint16_t virt_pgno; - uint16_t nr_pages; - uint32_t phys; -}; - -/* - * An array of mmu_vm_range objects describing all pageable addresses. - * The array is sorted by virt_pgno so that the TLB miss exception - * handler can do a binary search to find the correct entry. - */ -extern struct mmu_vm_range mmu_vmr_table[]; - -/* - * Initialize the MMU. This will set up a fixed TLB entry for the static - * u-boot image at dest_addr and enable paging. - */ -void mmu_init_r(unsigned long dest_addr); - -/* - * Handle a TLB miss exception. This function is called directly from - * the exception vector table written in assembly. - */ -int mmu_handle_tlb_miss(void); - -#endif /* __ASM_ARCH_MMU_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/portmux.h b/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/portmux.h deleted file mode 100644 index 7ae05408c..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/arch-at32ap700x/portmux.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_ARCH_PORTMUX_H__ -#define __ASM_AVR32_ARCH_PORTMUX_H__ - -#include <asm/arch/gpio.h> - -#define PORTMUX_PORT_A ((void *)ATMEL_BASE_PIOA) -#define PORTMUX_PORT_B ((void *)ATMEL_BASE_PIOB) -#define PORTMUX_PORT_C ((void *)ATMEL_BASE_PIOC) -#define PORTMUX_PORT_D ((void *)ATMEL_BASE_PIOD) -#define PORTMUX_PORT_E ((void *)ATMEL_BASE_PIOE) - -void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, - unsigned long flags, unsigned long drive_strength); - -#define PORTMUX_EBI_CS(x) (1 << (x)) -#define PORTMUX_EBI_NAND (1 << 6) -#define PORTMUX_EBI_CF(x) (1 << ((x) + 7)) -#define PORTMUX_EBI_NWAIT (1 << 9) - -#ifdef AT32AP700x_CHIP_HAS_USART -static inline void portmux_enable_usart0(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9), - PORTMUX_FUNC_B, 0); -} - -static inline void portmux_enable_usart1(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18), - PORTMUX_FUNC_A, 0); -} - -static inline void portmux_enable_usart2(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27), - PORTMUX_FUNC_B, 0); -} - -static inline void portmux_enable_usart3(unsigned long drive_strength) -{ - portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18), - PORTMUX_FUNC_B, 0); -} -#endif -#ifdef AT32AP700x_CHIP_HAS_MACB -void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength); -void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength); - -#define PORTMUX_MACB_RMII (0) -#define PORTMUX_MACB_MII (1 << 0) -#define PORTMUX_MACB_SPEED (1 << 1) - -#endif -#ifdef AT32AP700x_CHIP_HAS_MMCI -void portmux_enable_mmci(unsigned int slot, unsigned long flags, - unsigned long drive_strength); - -#define PORTMUX_MMCI_4BIT (1 << 0) -#define PORTMUX_MMCI_8BIT (PORTMUX_MMCI_4BIT | (1 << 1)) -#define PORTMUX_MMCI_EXT_PULLUP (1 << 2) - -#endif -#ifdef AT32AP700x_CHIP_HAS_SPI -void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength); -void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength); -#endif -#ifdef AT32AP700x_CHIP_HAS_LCDC -void portmux_enable_lcdc(int pin_config); -#endif - -#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/arch-common/portmux-pio.h b/qemu/roms/u-boot/arch/avr32/include/asm/arch-common/portmux-pio.h deleted file mode 100644 index 0d4d6e01e..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/arch-common/portmux-pio.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (C) 2006, 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __AVR32_PORTMUX_PIO_H__ -#define __AVR32_PORTMUX_PIO_H__ - -#include <asm/io.h> - -/* PIO register offsets */ -#define PIO_PER 0x0000 -#define PIO_PDR 0x0004 -#define PIO_PSR 0x0008 -#define PIO_OER 0x0010 -#define PIO_ODR 0x0014 -#define PIO_OSR 0x0018 -#define PIO_IFER 0x0020 -#define PIO_IFDR 0x0024 -#define PIO_ISFR 0x0028 -#define PIO_SODR 0x0030 -#define PIO_CODR 0x0034 -#define PIO_ODSR 0x0038 -#define PIO_PDSR 0x003c -#define PIO_IER 0x0040 -#define PIO_IDR 0x0044 -#define PIO_IMR 0x0048 -#define PIO_ISR 0x004c -#define PIO_MDER 0x0050 -#define PIO_MDDR 0x0054 -#define PIO_MDSR 0x0058 -#define PIO_PUDR 0x0060 -#define PIO_PUER 0x0064 -#define PIO_PUSR 0x0068 -#define PIO_ASR 0x0070 -#define PIO_BSR 0x0074 -#define PIO_ABSR 0x0078 -#define PIO_OWER 0x00a0 -#define PIO_OWDR 0x00a4 -#define PIO_OWSR 0x00a8 - -/* Hardware register access */ -#define pio_readl(base, reg) \ - __raw_readl((void *)base + PIO_##reg) -#define pio_writel(base, reg, value) \ - __raw_writel((value), (void *)base + PIO_##reg) - -/* Portmux API starts here. See doc/README.AVR32-port-muxing */ - -enum portmux_function { - PORTMUX_FUNC_A, - PORTMUX_FUNC_B, -}; - -/* Pull-down, buskeeper and drive strength are not supported */ -#define PORTMUX_DIR_INPUT (0 << 0) -#define PORTMUX_DIR_OUTPUT (1 << 0) -#define PORTMUX_INIT_LOW (0 << 1) -#define PORTMUX_INIT_HIGH (1 << 1) -#define PORTMUX_PULL_UP (1 << 2) -#define PORTMUX_PULL_DOWN (0) -#define PORTMUX_BUSKEEPER PORTMUX_PULL_UP -#define PORTMUX_DRIVE_MIN (0) -#define PORTMUX_DRIVE_LOW (0) -#define PORTMUX_DRIVE_HIGH (0) -#define PORTMUX_DRIVE_MAX (0) -#define PORTMUX_OPEN_DRAIN (1 << 3) - -void portmux_select_peripheral(void *port, unsigned long pin_mask, - enum portmux_function func, unsigned long flags); -void portmux_select_gpio(void *port, unsigned long pin_mask, - unsigned long flags); - -/* Internal helper functions */ - -static inline void __pio_set_output_value(void *port, unsigned int pin, - int value) -{ - /* - * value will usually be constant, but it's pretty cheap - * either way. - */ - if (value) - pio_writel(port, SODR, 1 << pin); - else - pio_writel(port, CODR, 1 << pin); -} - -static inline int __pio_get_input_value(void *port, unsigned int pin) -{ - return (pio_readl(port, PDSR) >> pin) & 1; -} - -void pio_set_output_value(unsigned int pin, int value); -int pio_get_input_value(unsigned int pin); - -/* GPIO API starts here */ - -/* - * GCC doesn't realize that the constant case is extremely trivial, - * so we need to help it make the right decision by using - * always_inline. - */ -__attribute__((always_inline)) -static inline void gpio_set_value(unsigned int pin, int value) -{ - if (__builtin_constant_p(pin)) - __pio_set_output_value(pio_pin_to_port(pin), pin & 0x1f, value); - else - pio_set_output_value(pin, value); -} - -__attribute__((always_inline)) -static inline int gpio_get_value(unsigned int pin) -{ - if (__builtin_constant_p(pin)) - return __pio_get_input_value(pio_pin_to_port(pin), pin & 0x1f); - else - return pio_get_input_value(pin); -} - -#endif /* __AVR32_PORTMUX_PIO_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/bitops.h b/qemu/roms/u-boot/arch/avr32/include/asm/bitops.h deleted file mode 100644 index 0ec678487..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/bitops.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_BITOPS_H -#define __ASM_AVR32_BITOPS_H - -#endif /* __ASM_AVR32_BITOPS_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/byteorder.h b/qemu/roms/u-boot/arch/avr32/include/asm/byteorder.h deleted file mode 100644 index 25e9aff42..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/byteorder.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_BYTEORDER_H -#define __ASM_AVR32_BYTEORDER_H - -#include <asm/types.h> - -#define __arch__swab32(x) __builtin_bswap_32(x) -#define __arch__swab16(x) __builtin_bswap_16(x) - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#include <linux/byteorder/big_endian.h> - -#endif /* __ASM_AVR32_BYTEORDER_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/cache.h b/qemu/roms/u-boot/arch/avr32/include/asm/cache.h deleted file mode 100644 index 486284398..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/cache.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __AVR32_CACHE_H__ -#define __AVR32_CACHE_H__ - -/* - * Since the AVR32 architecture has a queryable cacheline size with a maximum - * value of 256 we set the DMA buffer alignemnt requirement to this maximum - * value. The board config can override this if it knows that the cacheline - * size is a smaller value. AVR32 boards use the CONFIG_SYS_DCACHE_LINESZ - * macro to specify cache line size, so if it is set we use it instead. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#elif defined(CONFIG_SYS_DCACHE_LINESZ) -#define ARCH_DMA_MINALIGN CONFIG_SYS_DCACHE_LINESZ -#else -#define ARCH_DMA_MINALIGN 256 -#endif - -#endif /* __AVR32_CACHE_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/config.h b/qemu/roms/u-boot/arch/avr32/include/asm/config.h deleted file mode 100644 index 63056a4df..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/config.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -#define CONFIG_NEEDS_MANUAL_RELOC - -#endif diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/dma-mapping.h b/qemu/roms/u-boot/arch/avr32/include/asm/dma-mapping.h deleted file mode 100644 index 95ea81ff5..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/dma-mapping.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_DMA_MAPPING_H -#define __ASM_AVR32_DMA_MAPPING_H - -#include <asm/io.h> -#include <asm/arch/cacheflush.h> - -enum dma_data_direction { - DMA_BIDIRECTIONAL = 0, - DMA_TO_DEVICE = 1, - DMA_FROM_DEVICE = 2, -}; -extern void *dma_alloc_coherent(size_t len, unsigned long *handle); - -static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, - enum dma_data_direction dir) -{ - extern void __bad_dma_data_direction(void); - - switch (dir) { - case DMA_BIDIRECTIONAL: - dcache_flush_range(vaddr, len); - break; - case DMA_TO_DEVICE: - dcache_clean_range(vaddr, len); - break; - case DMA_FROM_DEVICE: - dcache_invalidate_range(vaddr, len); - break; - default: - /* This will cause a linker error */ - __bad_dma_data_direction(); - } - - return virt_to_phys(vaddr); -} - -static inline void dma_unmap_single(volatile void *vaddr, size_t len, - unsigned long paddr) -{ - -} - -#endif /* __ASM_AVR32_DMA_MAPPING_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/errno.h b/qemu/roms/u-boot/arch/avr32/include/asm/errno.h deleted file mode 100644 index 4c82b503d..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/global_data.h b/qemu/roms/u-boot/arch/avr32/include/asm/global_data.h deleted file mode 100644 index d82fb7cc6..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/global_data.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_GLOBAL_DATA_H__ -#define __ASM_GLOBAL_DATA_H__ - -/* Architecture-specific global data */ -struct arch_global_data { - unsigned long stack_end; /* highest stack address */ - unsigned long cpu_hz; /* cpu core clock frequency */ -}; - -#include <asm-generic/global_data.h> - -#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5") - -#endif /* __ASM_GLOBAL_DATA_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/hmatrix-common.h b/qemu/roms/u-boot/arch/avr32/include/asm/hmatrix-common.h deleted file mode 100644 index 66ea43a88..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/hmatrix-common.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_HMATRIX_COMMON_H__ -#define __ASM_AVR32_HMATRIX_COMMON_H__ - -/* HMATRIX register offsets */ -struct hmatrix_regs { - u32 MCFG[16]; - u32 SCFG[16]; - struct { - u32 A; - u32 B; - } PRS[16]; - u32 MRCR; - u32 __reserved[3]; - u32 SFR[16]; -}; - -/* Bitfields in MCFG */ -#define HMATRIX_ULBT_OFFSET 0 -#define HMATRIX_ULBT_SIZE 3 - -/* Bitfields in SCFG */ -#define HMATRIX_SLOT_CYCLE_OFFSET 0 -#define HMATRIX_SLOT_CYCLE_SIZE 8 -#define HMATRIX_DEFMSTR_TYPE_OFFSET 16 -#define HMATRIX_DEFMSTR_TYPE_SIZE 2 -#define HMATRIX_FIXED_DEFMSTR_OFFSET 18 -#define HMATRIX_FIXED_DEFMSTR_SIZE 4 -#define HMATRIX_ARBT_OFFSET 24 -#define HMATRIX_ARBT_SIZE 1 - -/* Bitfields in PRS.A */ -#define HMATRIX_M0PR_OFFSET 0 -#define HMATRIX_M0PR_SIZE 4 -#define HMATRIX_M1PR_OFFSET 4 -#define HMATRIX_M1PR_SIZE 4 -#define HMATRIX_M2PR_OFFSET 8 -#define HMATRIX_M2PR_SIZE 4 -#define HMATRIX_M3PR_OFFSET 12 -#define HMATRIX_M3PR_SIZE 4 -#define HMATRIX_M4PR_OFFSET 16 -#define HMATRIX_M4PR_SIZE 4 -#define HMATRIX_M5PR_OFFSET 20 -#define HMATRIX_M5PR_SIZE 4 -#define HMATRIX_M6PR_OFFSET 24 -#define HMATRIX_M6PR_SIZE 4 -#define HMATRIX_M7PR_OFFSET 28 -#define HMATRIX_M7PR_SIZE 4 - -/* Bitfields in PRS.B */ -#define HMATRIX_M8PR_OFFSET 0 -#define HMATRIX_M8PR_SIZE 4 -#define HMATRIX_M9PR_OFFSET 4 -#define HMATRIX_M9PR_SIZE 4 -#define HMATRIX_M10PR_OFFSET 8 -#define HMATRIX_M10PR_SIZE 4 -#define HMATRIX_M11PR_OFFSET 12 -#define HMATRIX_M11PR_SIZE 4 -#define HMATRIX_M12PR_OFFSET 16 -#define HMATRIX_M12PR_SIZE 4 -#define HMATRIX_M13PR_OFFSET 20 -#define HMATRIX_M13PR_SIZE 4 -#define HMATRIX_M14PR_OFFSET 24 -#define HMATRIX_M14PR_SIZE 4 -#define HMATRIX_M15PR_OFFSET 28 -#define HMATRIX_M15PR_SIZE 4 - -/* Constants for ULBT */ -#define HMATRIX_ULBT_INFINITE 0 -#define HMATRIX_ULBT_SINGLE 1 -#define HMATRIX_ULBT_FOUR_BEAT 2 -#define HMATRIX_ULBT_EIGHT_BEAT 3 -#define HMATRIX_ULBT_SIXTEEN_BEAT 4 - -/* Constants for DEFMSTR_TYPE */ -#define HMATRIX_DEFMSTR_TYPE_NO_DEFAULT 0 -#define HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT 1 -#define HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT 2 - -/* Constants for ARBT */ -#define HMATRIX_ARBT_ROUND_ROBIN 0 -#define HMATRIX_ARBT_FIXED_PRIORITY 1 - -/* Bit manipulation macros */ -#define HMATRIX_BIT(name) \ - (1 << HMATRIX_##name##_OFFSET) -#define HMATRIX_BF(name,value) \ - (((value) & ((1 << HMATRIX_##name##_SIZE) - 1)) \ - << HMATRIX_##name##_OFFSET) -#define HMATRIX_BFEXT(name,value) \ - (((value) >> HMATRIX_##name##_OFFSET) \ - & ((1 << HMATRIX_##name##_SIZE) - 1)) -#define HMATRIX_BFINS(name,value,old) \ - (((old) & ~(((1 << HMATRIX_##name##_SIZE) - 1) \ - << HMATRIX_##name##_OFFSET)) \ - | HMATRIX_BF(name,value)) - -/* Register access macros */ -#define __hmatrix_reg(reg) \ - (((volatile struct hmatrix_regs *)ATMEL_BASE_HMATRIX)->reg) -#define hmatrix_read(reg) \ - (__hmatrix_reg(reg)) -#define hmatrix_write(reg, value) \ - do { __hmatrix_reg(reg) = (value); } while (0) - -#define hmatrix_slave_read(slave, reg) \ - hmatrix_read(reg[HMATRIX_SLAVE_##slave]) -#define hmatrix_slave_write(slave, reg, value) \ - hmatrix_write(reg[HMATRIX_SLAVE_##slave], value) - -#endif /* __ASM_AVR32_HMATRIX_COMMON_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/io.h b/qemu/roms/u-boot/arch/avr32/include/asm/io.h deleted file mode 100644 index c8d693361..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/io.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_IO_H -#define __ASM_AVR32_IO_H - -#include <asm/types.h> - -#ifdef __KERNEL__ - -/* - * Generic IO read/write. These perform native-endian accesses. Note - * that some architectures will want to re-define __raw_{read,write}w. - */ -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -/* As long as I/O is only performed in P4 (or possibly P3), we're safe */ -#define writeb(v,a) __raw_writeb(v,a) -#define writew(v,a) __raw_writew(v,a) -#define writel(v,a) __raw_writel(v,a) - -#define readb(a) __raw_readb(a) -#define readw(a) __raw_readw(a) -#define readl(a) __raw_readl(a) - -/* - * Bad read/write accesses... - */ -extern void __readwrite_bug(const char *fn); - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * All I/O is memory mapped, so these macros doesn't make very much sense - */ -#define outb(v,p) __raw_writeb(v, p) -#define outw(v,p) __raw_writew(cpu_to_le16(v),p) -#define outl(v,p) __raw_writel(cpu_to_le32(v),p) - -#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) -#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) -#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) - -#include <asm/arch/addrspace.h> -/* Provides virt_to_phys, phys_to_virt, cached, uncached, map_physmem */ - -#endif /* __KERNEL__ */ - -static inline void sync(void) -{ -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long len) -{ - -} - -#endif /* __ASM_AVR32_IO_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/posix_types.h b/qemu/roms/u-boot/arch/avr32/include/asm/posix_types.h deleted file mode 100644 index c65f4ecb6..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/posix_types.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_POSIX_TYPES_H -#define __ASM_AVR32_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned long __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned int __kernel_uid_t; -typedef unsigned int __kernel_gid_t; -typedef unsigned long __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; -typedef unsigned short __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); -} - - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *__p) -{ - unsigned long *__tmp = __p->fds_bits; - int __i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 16: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - __tmp[ 8] = 0; __tmp[ 9] = 0; - __tmp[10] = 0; __tmp[11] = 0; - __tmp[12] = 0; __tmp[13] = 0; - __tmp[14] = 0; __tmp[15] = 0; - return; - - case 8: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - return; - - case 4: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - return; - } - } - __i = __FDSET_LONGS; - while (__i) { - __i--; - *__tmp = 0; - __tmp++; - } -} - -#endif /* defined(__KERNEL__) */ - -#endif /* __ASM_AVR32_POSIX_TYPES_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/processor.h b/qemu/roms/u-boot/arch/avr32/include/asm/processor.h deleted file mode 100644 index 74d868cdc..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/processor.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_PROCESSOR_H -#define __ASM_AVR32_PROCESSOR_H - -#ifndef __ASSEMBLY__ - -#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; }) - -struct avr32_cpuinfo { - unsigned long loops_per_jiffy; -}; - -extern struct avr32_cpuinfo boot_cpu_data; - -#ifdef CONFIG_SMP -extern struct avr32_cpuinfo cpu_data[]; -#define current_cpu_data cpu_data[smp_processor_id()] -#else -#define cpu_data (&boot_cpu_data) -#define current_cpu_data boot_cpu_data -#endif - -/* TODO: Make configurable (2GB will serve as a reasonable default) */ -#define TASK_SIZE 0x80000000 - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) - -#define cpu_relax() barrier() -#define cpu_sync_pipeline() asm volatile("sub pc, -2" : : : "memory") - -/* This struct contains the CPU context as stored by switch_to() */ -struct thread_struct { - unsigned long pc; - unsigned long ksp; /* Kernel stack pointer */ - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; -}; - -#define INIT_THREAD { \ - .ksp = sizeof(init_stack) + (long)&init_stack, \ -} - -/* - * Do necessary setup to start up a newly executed thread. - */ -#define start_thread(regs, new_pc, new_sp) \ - set_fs(USER_DS); \ - regs->sr = 0; /* User mode. */ \ - regs->gr[REG_PC] = new_pc; \ - regs->gr[REG_SP] = new_sp - -struct task_struct; - -/* Free all resources held by a thread */ -extern void release_thread(struct task_struct *); - -/* Create a kernel thread without removing it from tasklists */ -extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); - -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while(0) - -/* Return saved PC of a blocked thread */ -#define thread_saved_pc(tsk) (tsk->thread.pc) - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_AVR32_PROCESSOR_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/ptrace.h b/qemu/roms/u-boot/arch/avr32/include/asm/ptrace.h deleted file mode 100644 index a32969b5a..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/ptrace.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_PTRACE_H -#define __ASM_AVR32_PTRACE_H - -/* - * Status Register bits - */ -#define SR_H 0x40000000 -#define SR_R 0x20000000 -#define SR_J 0x10000000 -#define SR_DM 0x08000000 -#define SR_D 0x04000000 -#define MODE_NMI 0x01c00000 -#define MODE_EXCEPTION 0x01800000 -#define MODE_INT3 0x01400000 -#define MODE_INT2 0x01000000 -#define MODE_INT1 0x00c00000 -#define MODE_INT0 0x00800000 -#define MODE_SUPERVISOR 0x00400000 -#define MODE_USER 0x00000000 -#define MODE_MASK 0x01c00000 -#define SR_EM 0x00200000 -#define SR_I3M 0x00100000 -#define SR_I2M 0x00080000 -#define SR_I1M 0x00040000 -#define SR_I0M 0x00020000 -#define SR_GM 0x00010000 - -#define MODE_SHIFT 22 -#define SR_EM_BIT 21 -#define SR_I3M_BIT 20 -#define SR_I2M_BIT 19 -#define SR_I1M_BIT 18 -#define SR_I0M_BIT 17 -#define SR_GM_BIT 16 - -/* The user-visible part */ -#define SR_Q 0x00000010 -#define SR_V 0x00000008 -#define SR_N 0x00000004 -#define SR_Z 0x00000002 -#define SR_C 0x00000001 - -/* - * The order is defined by the stdsp instruction. r0 is stored first, so it - * gets the highest address. - * - * Registers 0-12 are general-purpose registers (r12 is normally used for - * the function return value). - * Register 13 is the stack pointer - * Register 14 is the link register - * Register 15 is the program counter - */ -#define FRAME_SIZE_FULL 72 -#define REG_R12_ORIG 68 -#define REG_R0 64 -#define REG_R1 60 -#define REG_R2 56 -#define REG_R3 52 -#define REG_R4 48 -#define REG_R5 44 -#define REG_R6 40 -#define REG_R7 36 -#define REG_R8 32 -#define REG_R9 28 -#define REG_R10 34 -#define REG_R11 20 -#define REG_R12 16 -#define REG_SP 12 -#define REG_LR 8 - -#define FRAME_SIZE_MIN 8 -#define REG_PC 4 -#define REG_SR 0 - -#ifndef __ASSEMBLY__ -struct pt_regs { - /* These are always saved */ - unsigned long sr; - unsigned long pc; - - /* These are sometimes saved */ - unsigned long lr; - unsigned long sp; - unsigned long r12; - unsigned long r11; - unsigned long r10; - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - - /* Only saved on system call */ - unsigned long r12_orig; -}; - -#ifdef __KERNEL__ -# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER) -# define instruction_pointer(regs) ((regs)->pc) -extern void show_regs (struct pt_regs *); - -static __inline__ int valid_user_regs(struct pt_regs *regs) -{ - /* - * Some of the Java bits might be acceptable if/when we - * implement some support for that stuff... - */ - if ((regs->sr & 0xffff0000) == 0) - return 1; - - /* - * Force status register flags to be sane and report this - * illegal behaviour... - */ - regs->sr &= 0x0000ffff; - return 0; -} -#endif - -#endif /* ! __ASSEMBLY__ */ - -#endif /* __ASM_AVR32_PTRACE_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/sdram.h b/qemu/roms/u-boot/arch/avr32/include/asm/sdram.h deleted file mode 100644 index 83d515bda..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/sdram.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_SDRAM_H -#define __ASM_AVR32_SDRAM_H - -struct sdram_config { - /* Number of data bits. */ - enum { - SDRAM_DATA_16BIT = 16, - SDRAM_DATA_32BIT = 32, - } data_bits; - - /* Number of address bits */ - uint8_t row_bits, col_bits, bank_bits; - - /* SDRAM timings in cycles */ - uint8_t cas, twr, trc, trp, trcd, tras, txsr; - - /* SDRAM refresh period in cycles */ - unsigned long refresh_period; -}; - -/* - * Attempt to initialize the SDRAM controller using the specified - * parameters. Return the expected size of the memory area based on - * the number of address and data bits. - * - * The caller should verify that the configuration is correct by - * running a memory test, e.g. get_ram_size(). - */ -extern unsigned long sdram_init(void *sdram_base, - const struct sdram_config *config); - -#endif /* __ASM_AVR32_SDRAM_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/sections.h b/qemu/roms/u-boot/arch/avr32/include/asm/sections.h deleted file mode 100644 index 6b7804fe0..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/sections.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_SECTIONS_H -#define __ASM_AVR32_SECTIONS_H - -#include <asm-generic/sections.h> - -/* References to section boundaries */ - -extern char __data_lma[], __edata_lma[]; -extern char __got_start[], __got_lma[], __got_end[]; - -#endif /* __ASM_AVR32_SECTIONS_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/setup.h b/qemu/roms/u-boot/arch/avr32/include/asm/setup.h deleted file mode 100644 index e05e65ebc..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/setup.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * Based on linux/include/asm-arm/setup.h - * Copyright (C) 1997-1999 Russel King - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_SETUP_H__ -#define __ASM_AVR32_SETUP_H__ - -#define COMMAND_LINE_SIZE 256 - -/* Magic number indicating that a tag table is present */ -#define ATAG_MAGIC 0xa2a25441 - -#ifndef __ASSEMBLY__ - -/* - * Generic memory range, used by several tags. - * - * addr is always physical. - * size is measured in bytes. - * next is for use by the OS, e.g. for grouping regions into - * linked lists. - */ -struct tag_mem_range { - u32 addr; - u32 size; - struct tag_mem_range * next; -}; - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 -/* ATAG_MEM uses tag_mem_range */ - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410003 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* Ramdisk image (may be compressed) */ -#define ATAG_RDIMG 0x54410004 -/* ATAG_RDIMG uses tag_mem_range */ - -/* Information about various clocks present in the system */ -#define ATAG_CLOCK 0x54410005 - -struct tag_clock { - u32 clock_id; /* Which clock are we talking about? */ - u32 clock_flags; /* Special features */ - u64 clock_hz; /* Clock speed in Hz */ -}; - -/* The clock types we know about */ -#define ACLOCK_BOOTCPU 0 /* The CPU we're booting from */ -#define ACLOCK_HSB 1 /* Deprecated */ - -/* Memory reserved for the system (e.g. the bootloader) */ -#define ATAG_RSVD_MEM 0x54410006 -/* ATAG_RSVD_MEM uses tag_mem_range */ - -/* Ethernet information */ - -#define ATAG_ETHERNET 0x54410007 - -struct tag_ethernet { - u8 mac_index; - u8 mii_phy_addr; - u8 hw_address[6]; -}; - -#define AETH_INVALID_PHY 0xff - -/* board information information */ -#define ATAG_BOARDINFO 0x54410008 - -struct tag_boardinfo { - u32 board_number; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem_range mem_range; - struct tag_cmdline cmdline; - struct tag_clock clock; - struct tag_ethernet ethernet; - struct tag_boardinfo boardinfo; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(struct tag *); -}; - -#define __tag __attribute_used__ __attribute__((__section__(".taglist"))) -#define __tagtable(tag, fn) \ - static struct tagtable __tagtable_##fn __tag = { tag, fn } - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -#endif /* !__ASSEMBLY__ */ - -#endif /* __ASM_AVR32_SETUP_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/string.h b/qemu/roms/u-boot/arch/avr32/include/asm/string.h deleted file mode 100644 index dba0219fb..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/string.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_STRING_H -#define __ASM_AVR32_STRING_H - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *s, int c, __kernel_size_t n); - -#endif /* __ASM_AVR32_STRING_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/sysreg.h b/qemu/roms/u-boot/arch/avr32/include/asm/sysreg.h deleted file mode 100644 index 4f6970448..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/sysreg.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * System registers for AVR32 - */ -#ifndef __ASM_AVR32_SYSREG_H__ -#define __ASM_AVR32_SYSREG_H__ - -/* system register offsets */ -#define SYSREG_SR 0x0000 -#define SYSREG_EVBA 0x0004 -#define SYSREG_ACBA 0x0008 -#define SYSREG_CPUCR 0x000c -#define SYSREG_ECR 0x0010 -#define SYSREG_RSR_SUP 0x0014 -#define SYSREG_RSR_INT0 0x0018 -#define SYSREG_RSR_INT1 0x001c -#define SYSREG_RSR_INT2 0x0020 -#define SYSREG_RSR_INT3 0x0024 -#define SYSREG_RSR_EX 0x0028 -#define SYSREG_RSR_NMI 0x002c -#define SYSREG_RSR_DBG 0x0030 -#define SYSREG_RAR_SUP 0x0034 -#define SYSREG_RAR_INT0 0x0038 -#define SYSREG_RAR_INT1 0x003c -#define SYSREG_RAR_INT2 0x0040 -#define SYSREG_RAR_INT3 0x0044 -#define SYSREG_RAR_EX 0x0048 -#define SYSREG_RAR_NMI 0x004c -#define SYSREG_RAR_DBG 0x0050 -#define SYSREG_JECR 0x0054 -#define SYSREG_JOSP 0x0058 -#define SYSREG_JAVA_LV0 0x005c -#define SYSREG_JAVA_LV1 0x0060 -#define SYSREG_JAVA_LV2 0x0064 -#define SYSREG_JAVA_LV3 0x0068 -#define SYSREG_JAVA_LV4 0x006c -#define SYSREG_JAVA_LV5 0x0070 -#define SYSREG_JAVA_LV6 0x0074 -#define SYSREG_JAVA_LV7 0x0078 -#define SYSREG_JTBA 0x007c -#define SYSREG_JBCR 0x0080 -#define SYSREG_CONFIG0 0x0100 -#define SYSREG_CONFIG1 0x0104 -#define SYSREG_COUNT 0x0108 -#define SYSREG_COMPARE 0x010c -#define SYSREG_TLBEHI 0x0110 -#define SYSREG_TLBELO 0x0114 -#define SYSREG_PTBR 0x0118 -#define SYSREG_TLBEAR 0x011c -#define SYSREG_MMUCR 0x0120 -#define SYSREG_TLBARLO 0x0124 -#define SYSREG_TLBARHI 0x0128 -#define SYSREG_PCCNT 0x012c -#define SYSREG_PCNT0 0x0130 -#define SYSREG_PCNT1 0x0134 -#define SYSREG_PCCR 0x0138 -#define SYSREG_BEAR 0x013c -#define SYSREG_SABAL 0x0300 -#define SYSREG_SABAH 0x0304 -#define SYSREG_SABD 0x0308 - -/* Bitfields in SR */ -#define SYSREG_SR_C_OFFSET 0 -#define SYSREG_SR_C_SIZE 1 -#define SYSREG_Z_OFFSET 1 -#define SYSREG_Z_SIZE 1 -#define SYSREG_SR_N_OFFSET 2 -#define SYSREG_SR_N_SIZE 1 -#define SYSREG_SR_V_OFFSET 3 -#define SYSREG_SR_V_SIZE 1 -#define SYSREG_Q_OFFSET 4 -#define SYSREG_Q_SIZE 1 -#define SYSREG_L_OFFSET 5 -#define SYSREG_L_SIZE 1 -#define SYSREG_T_OFFSET 14 -#define SYSREG_T_SIZE 1 -#define SYSREG_SR_R_OFFSET 15 -#define SYSREG_SR_R_SIZE 1 -#define SYSREG_GM_OFFSET 16 -#define SYSREG_GM_SIZE 1 -#define SYSREG_I0M_OFFSET 17 -#define SYSREG_I0M_SIZE 1 -#define SYSREG_I1M_OFFSET 18 -#define SYSREG_I1M_SIZE 1 -#define SYSREG_I2M_OFFSET 19 -#define SYSREG_I2M_SIZE 1 -#define SYSREG_I3M_OFFSET 20 -#define SYSREG_I3M_SIZE 1 -#define SYSREG_EM_OFFSET 21 -#define SYSREG_EM_SIZE 1 -#define SYSREG_M0_OFFSET 22 -#define SYSREG_M0_SIZE 1 -#define SYSREG_M1_OFFSET 23 -#define SYSREG_M1_SIZE 1 -#define SYSREG_M2_OFFSET 24 -#define SYSREG_M2_SIZE 1 -#define SYSREG_SR_D_OFFSET 26 -#define SYSREG_SR_D_SIZE 1 -#define SYSREG_DM_OFFSET 27 -#define SYSREG_DM_SIZE 1 -#define SYSREG_SR_J_OFFSET 28 -#define SYSREG_SR_J_SIZE 1 -#define SYSREG_H_OFFSET 29 -#define SYSREG_H_SIZE 1 - -/* Bitfields in CPUCR */ -#define SYSREG_BI_OFFSET 0 -#define SYSREG_BI_SIZE 1 -#define SYSREG_BE_OFFSET 1 -#define SYSREG_BE_SIZE 1 -#define SYSREG_FE_OFFSET 2 -#define SYSREG_FE_SIZE 1 -#define SYSREG_RE_OFFSET 3 -#define SYSREG_RE_SIZE 1 -#define SYSREG_IBE_OFFSET 4 -#define SYSREG_IBE_SIZE 1 -#define SYSREG_IEE_OFFSET 5 -#define SYSREG_IEE_SIZE 1 - -/* Bitfields in ECR */ -#define SYSREG_ECR_OFFSET 0 -#define SYSREG_ECR_SIZE 32 - -/* Bitfields in CONFIG0 */ -#define SYSREG_CONFIG0_R_OFFSET 0 -#define SYSREG_CONFIG0_R_SIZE 1 -#define SYSREG_CONFIG0_D_OFFSET 1 -#define SYSREG_CONFIG0_D_SIZE 1 -#define SYSREG_CONFIG0_S_OFFSET 2 -#define SYSREG_CONFIG0_S_SIZE 1 -#define SYSREG_O_OFFSET 3 -#define SYSREG_O_SIZE 1 -#define SYSREG_P_OFFSET 4 -#define SYSREG_P_SIZE 1 -#define SYSREG_CONFIG0_J_OFFSET 5 -#define SYSREG_CONFIG0_J_SIZE 1 -#define SYSREG_F_OFFSET 6 -#define SYSREG_F_SIZE 1 -#define SYSREG_MMUT_OFFSET 7 -#define SYSREG_MMUT_SIZE 3 -#define SYSREG_AR_OFFSET 10 -#define SYSREG_AR_SIZE 3 -#define SYSREG_AT_OFFSET 13 -#define SYSREG_AT_SIZE 3 -#define SYSREG_PROCESSORREVISION_OFFSET 16 -#define SYSREG_PROCESSORREVISION_SIZE 8 -#define SYSREG_PROCESSORID_OFFSET 24 -#define SYSREG_PROCESSORID_SIZE 8 - -/* Bitfields in CONFIG1 */ -#define SYSREG_DASS_OFFSET 0 -#define SYSREG_DASS_SIZE 3 -#define SYSREG_DLSZ_OFFSET 3 -#define SYSREG_DLSZ_SIZE 3 -#define SYSREG_DSET_OFFSET 6 -#define SYSREG_DSET_SIZE 4 -#define SYSREG_IASS_OFFSET 10 -#define SYSREG_IASS_SIZE 3 -#define SYSREG_ILSZ_OFFSET 13 -#define SYSREG_ILSZ_SIZE 3 -#define SYSREG_ISET_OFFSET 16 -#define SYSREG_ISET_SIZE 4 -#define SYSREG_DMMUSZ_OFFSET 20 -#define SYSREG_DMMUSZ_SIZE 6 -#define SYSREG_IMMUSZ_OFFSET 26 -#define SYSREG_IMMUSZ_SIZE 6 - -/* Bitfields in TLBEHI */ -#define SYSREG_ASID_OFFSET 0 -#define SYSREG_ASID_SIZE 8 -#define SYSREG_TLBEHI_I_OFFSET 8 -#define SYSREG_TLBEHI_I_SIZE 1 -#define SYSREG_TLBEHI_V_OFFSET 9 -#define SYSREG_TLBEHI_V_SIZE 1 -#define SYSREG_VPN_OFFSET 10 -#define SYSREG_VPN_SIZE 22 - -/* Bitfields in TLBELO */ -#define SYSREG_W_OFFSET 0 -#define SYSREG_W_SIZE 1 -#define SYSREG_TLBELO_D_OFFSET 1 -#define SYSREG_TLBELO_D_SIZE 1 -#define SYSREG_SZ_OFFSET 2 -#define SYSREG_SZ_SIZE 2 -#define SYSREG_AP_OFFSET 4 -#define SYSREG_AP_SIZE 3 -#define SYSREG_B_OFFSET 7 -#define SYSREG_B_SIZE 1 -#define SYSREG_G_OFFSET 8 -#define SYSREG_G_SIZE 1 -#define SYSREG_TLBELO_C_OFFSET 9 -#define SYSREG_TLBELO_C_SIZE 1 -#define SYSREG_PFN_OFFSET 10 -#define SYSREG_PFN_SIZE 22 - -/* Bitfields in MMUCR */ -#define SYSREG_E_OFFSET 0 -#define SYSREG_E_SIZE 1 -#define SYSREG_M_OFFSET 1 -#define SYSREG_M_SIZE 1 -#define SYSREG_MMUCR_I_OFFSET 2 -#define SYSREG_MMUCR_I_SIZE 1 -#define SYSREG_MMUCR_N_OFFSET 3 -#define SYSREG_MMUCR_N_SIZE 1 -#define SYSREG_MMUCR_S_OFFSET 4 -#define SYSREG_MMUCR_S_SIZE 1 -#define SYSREG_DLA_OFFSET 8 -#define SYSREG_DLA_SIZE 6 -#define SYSREG_DRP_OFFSET 14 -#define SYSREG_DRP_SIZE 6 -#define SYSREG_ILA_OFFSET 20 -#define SYSREG_ILA_SIZE 6 -#define SYSREG_IRP_OFFSET 26 -#define SYSREG_IRP_SIZE 6 - -/* Bitfields in PCCR */ -#define SYSREG_PCCR_R_OFFSET 1 -#define SYSREG_PCCR_R_SIZE 1 -#define SYSREG_PCCR_C_OFFSET 2 -#define SYSREG_PCCR_C_SIZE 1 -#define SYSREG_PCCR_S_OFFSET 3 -#define SYSREG_PCCR_S_SIZE 1 -#define SYSREG_IEC_OFFSET 4 -#define SYSREG_IEC_SIZE 1 -#define SYSREG_IE0_OFFSET 5 -#define SYSREG_IE0_SIZE 1 -#define SYSREG_IE1_OFFSET 6 -#define SYSREG_IE1_SIZE 1 -#define SYSREG_FC_OFFSET 8 -#define SYSREG_FC_SIZE 1 -#define SYSREG_F0_OFFSET 9 -#define SYSREG_F0_SIZE 1 -#define SYSREG_F1_OFFSET 10 -#define SYSREG_F1_SIZE 1 -#define SYSREG_CONF0_OFFSET 12 -#define SYSREG_CONF0_SIZE 6 -#define SYSREG_CONF1_OFFSET 18 -#define SYSREG_CONF1_SIZE 6 - -/* Constants for ECR */ -#define ECR_UNRECOVERABLE 0 -#define ECR_TLB_MULTIPLE 1 -#define ECR_BUS_ERROR_WRITE 2 -#define ECR_BUS_ERROR_READ 3 -#define ECR_NMI 4 -#define ECR_ADDR_ALIGN_X 5 -#define ECR_PROTECTION_X 6 -#define ECR_DEBUG 7 -#define ECR_ILLEGAL_OPCODE 8 -#define ECR_UNIMPL_INSTRUCTION 9 -#define ECR_PRIVILEGE_VIOLATION 10 -#define ECR_FPE 11 -#define ECR_COPROC_ABSENT 12 -#define ECR_ADDR_ALIGN_R 13 -#define ECR_ADDR_ALIGN_W 14 -#define ECR_PROTECTION_R 15 -#define ECR_PROTECTION_W 16 -#define ECR_DTLB_MODIFIED 17 -#define ECR_TLB_MISS_X 20 -#define ECR_TLB_MISS_R 24 -#define ECR_TLB_MISS_W 28 - -/* Bit manipulation macros */ -#define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET) -#define SYSREG_BF(name,value) \ - (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \ - << SYSREG_##name##_OFFSET) -#define SYSREG_BFEXT(name,value) \ - (((value) >> SYSREG_##name##_OFFSET) \ - & ((1 << SYSREG_##name##_SIZE) - 1)) -#define SYSREG_BFINS(name,value,old) \ - (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \ - << SYSREG_##name##_OFFSET)) \ - | SYSREG_BF(name,value)) - -/* Register access macros */ -#define sysreg_read(reg) \ - ((unsigned long)__builtin_mfsr(SYSREG_##reg)) -#define sysreg_write(reg, value) \ - __builtin_mtsr(SYSREG_##reg, value) - -#endif /* __ASM_AVR32_SYSREG_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/types.h b/qemu/roms/u-boot/arch/avr32/include/asm/types.h deleted file mode 100644 index 65de677ec..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/types.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_AVR32_TYPES_H -#define __ASM_AVR32_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - -typedef __signed__ char s8; -typedef unsigned char u8; - -typedef __signed__ short s16; -typedef unsigned short u16; - -typedef __signed__ int s32; -typedef unsigned int u32; - -typedef __signed__ long long s64; -typedef unsigned long long u64; - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#ifdef CONFIG_LBD -typedef u64 sector_t; -#define HAVE_SECTOR_T -#endif - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - - -#endif /* __ASM_AVR32_TYPES_H */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/u-boot.h b/qemu/roms/u-boot/arch/avr32/include/asm/u-boot.h deleted file mode 100644 index 6aef80874..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/u-boot.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_U_BOOT_H__ -#define __ASM_U_BOOT_H__ 1 - -typedef struct bd_info { - unsigned char bi_phy_id[4]; - unsigned long bi_board_number; - void *bi_boot_params; - struct { - unsigned long start; - unsigned long size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; - unsigned long bi_flashstart; - unsigned long bi_flashsize; - unsigned long bi_flashoffset; -} bd_t; - -#define bi_memstart bi_dram[0].start -#define bi_memsize bi_dram[0].size - -/* For image.h:image_check_target_arch() */ -#define IH_ARCH_DEFAULT IH_ARCH_AVR32 - -#endif /* __ASM_U_BOOT_H__ */ diff --git a/qemu/roms/u-boot/arch/avr32/include/asm/unaligned.h b/qemu/roms/u-boot/arch/avr32/include/asm/unaligned.h deleted file mode 100644 index 6cecbbb21..000000000 --- a/qemu/roms/u-boot/arch/avr32/include/asm/unaligned.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/unaligned.h> diff --git a/qemu/roms/u-boot/arch/avr32/lib/Makefile b/qemu/roms/u-boot/arch/avr32/lib/Makefile deleted file mode 100644 index bb45cbe15..000000000 --- a/qemu/roms/u-boot/arch/avr32/lib/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += memset.o -obj-y += board.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o -obj-y += interrupts.o diff --git a/qemu/roms/u-boot/arch/avr32/lib/board.c b/qemu/roms/u-boot/arch/avr32/lib/board.c deleted file mode 100644 index 7680102f5..000000000 --- a/qemu/roms/u-boot/arch/avr32/lib/board.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <stdio_dev.h> -#include <version.h> -#include <net.h> -#include <atmel_mci.h> - -#ifdef CONFIG_BITBANGMII -#include <miiphy.h> -#endif - -#include <asm/sections.h> -#include <asm/arch/mmu.h> -#include <asm/arch/hardware.h> - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -#include <mmc.h> -#endif -DECLARE_GLOBAL_DATA_PTR; - -unsigned long monitor_flash_len; - -/* Weak aliases for optional board functions */ -static int __do_nothing(void) -{ - return 0; -} -int board_postclk_init(void) __attribute__((weak, alias("__do_nothing"))); -int board_early_init_r(void) __attribute__((weak, alias("__do_nothing"))); - -/* provide cpu_mmc_init, to overwrite provide board_mmc_init */ -int cpu_mmc_init(bd_t *bd) -{ - /* This calls the atmel_mci_init in gen_atmel_mci.c */ - return atmel_mci_init((void *)ATMEL_BASE_MMCI); -} - -#ifdef CONFIG_SYS_DMA_ALLOC_LEN -#include <asm/arch/cacheflush.h> -#include <asm/io.h> - -static unsigned long dma_alloc_start; -static unsigned long dma_alloc_end; -static unsigned long dma_alloc_brk; - -static void dma_alloc_init(void) -{ - unsigned long monitor_addr; - - monitor_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off; - dma_alloc_end = monitor_addr - CONFIG_SYS_MALLOC_LEN; - dma_alloc_start = dma_alloc_end - CONFIG_SYS_DMA_ALLOC_LEN; - dma_alloc_brk = dma_alloc_start; - - printf("DMA: Using memory from 0x%08lx to 0x%08lx\n", - dma_alloc_start, dma_alloc_end); - - dcache_invalidate_range(cached(dma_alloc_start), - dma_alloc_end - dma_alloc_start); -} - -void *dma_alloc_coherent(size_t len, unsigned long *handle) -{ - unsigned long paddr = dma_alloc_brk; - - if (dma_alloc_brk + len > dma_alloc_end) - return NULL; - - dma_alloc_brk = ((paddr + len + CONFIG_SYS_DCACHE_LINESZ - 1) - & ~(CONFIG_SYS_DCACHE_LINESZ - 1)); - - *handle = paddr; - return uncached(paddr); -} -#else -static inline void dma_alloc_init(void) -{ - -} -#endif - -static int init_baudrate(void) -{ - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - return 0; -} - -static int display_banner (void) -{ - printf ("\n\n%s\n\n", version_string); - printf ("U-Boot code: %08lx -> %08lx data: %08lx -> %08lx\n", - (unsigned long)_text, (unsigned long)_etext, - (unsigned long)_data, (unsigned long)(&__bss_end)); - return 0; -} - -static int display_dram_config (void) -{ - int i; - - puts ("DRAM Configuration:\n"); - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); - print_size (gd->bd->bi_dram[i].size, "\n"); - } - - return 0; -} - -static void display_flash_config (void) -{ - puts ("Flash: "); - print_size(gd->bd->bi_flashsize, " "); - printf("at address 0x%08lx\n", gd->bd->bi_flashstart); -} - -void board_init_f(ulong board_type) -{ - gd_t gd_data; - gd_t *new_gd; - bd_t *bd; - unsigned long *new_sp; - unsigned long monitor_len; - unsigned long monitor_addr; - unsigned long addr; - long sdram_size; - - /* Initialize the global data pointer */ - memset(&gd_data, 0, sizeof(gd_data)); - gd = &gd_data; - - /* Perform initialization sequence */ - board_early_init_f(); - cpu_init(); - board_postclk_init(); - env_init(); - init_baudrate(); - serial_init(); - console_init_f(); - display_banner(); - sdram_size = initdram(board_type); - - /* If we have no SDRAM, we can't go on */ - if (sdram_size <= 0) - panic("No working SDRAM available\n"); - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - * - * Reserve memory at end of RAM for (top down in that order): - * - u-boot image - * - heap for malloc() - * - board info struct - * - global data struct - * - stack - */ - addr = CONFIG_SYS_SDRAM_BASE + sdram_size; - monitor_len = (char *)(&__bss_end) - _text; - - /* - * Reserve memory for u-boot code, data and bss. - * Round down to next 4 kB limit. - */ - addr -= monitor_len; - addr &= ~(4096UL - 1); - monitor_addr = addr; - - /* Reserve memory for malloc() */ - addr -= CONFIG_SYS_MALLOC_LEN; - -#ifdef CONFIG_SYS_DMA_ALLOC_LEN - /* Reserve DMA memory (must be cache aligned) */ - addr &= ~(CONFIG_SYS_DCACHE_LINESZ - 1); - addr -= CONFIG_SYS_DMA_ALLOC_LEN; -#endif - -#ifdef CONFIG_LCD -#ifdef CONFIG_FB_ADDR - printf("LCD: Frame buffer allocated at preset 0x%08x\n", - CONFIG_FB_ADDR); - gd->fb_base = CONFIG_FB_ADDR; -#else - addr = lcd_setmem(addr); - printf("LCD: Frame buffer allocated at 0x%08lx\n", addr); - gd->fb_base = addr; -#endif /* CONFIG_FB_ADDR */ -#endif /* CONFIG_LCD */ - - /* Allocate a Board Info struct on a word boundary */ - addr -= sizeof(bd_t); - addr &= ~3UL; - gd->bd = bd = (bd_t *)addr; - - /* Allocate a new global data copy on a 8-byte boundary. */ - addr -= sizeof(gd_t); - addr &= ~7UL; - new_gd = (gd_t *)addr; - - /* And finally, a new, bigger stack. */ - new_sp = (unsigned long *)addr; - gd->arch.stack_end = addr; - *(--new_sp) = 0; - *(--new_sp) = 0; - - /* - * Initialize the board information struct with the - * information we have. - */ - bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - bd->bi_dram[0].size = sdram_size; - - memcpy(new_gd, gd, sizeof(gd_t)); - - relocate_code((unsigned long)new_sp, new_gd, monitor_addr); -} - -void board_init_r(gd_t *new_gd, ulong dest_addr) -{ -#ifndef CONFIG_ENV_IS_NOWHERE - extern char * env_name_spec; -#endif - bd_t *bd; - - gd = new_gd; - bd = gd->bd; - - gd->flags |= GD_FLG_RELOC; - gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; - - /* Enable the MMU so that we can keep u-boot simple */ - mmu_init_r(dest_addr); - - board_early_init_r(); - - monitor_flash_len = _edata - _text; - -#if defined(CONFIG_NEEDS_MANUAL_RELOC) - /* - * We have to relocate the command table manually - */ - fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), - ll_entry_count(cmd_tbl_t, cmd)); -#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ - - /* there are some other pointer constants we must deal with */ -#ifndef CONFIG_ENV_IS_NOWHERE - env_name_spec += gd->reloc_off; -#endif - - timer_init(); - - /* The malloc area is right below the monitor image in RAM */ - mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); - dma_alloc_init(); - - enable_interrupts(); - - bd->bi_flashstart = 0; - bd->bi_flashsize = 0; - bd->bi_flashoffset = 0; - -#ifndef CONFIG_SYS_NO_FLASH - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; - bd->bi_flashsize = flash_init(); - bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text; - - if (bd->bi_flashsize) - display_flash_config(); -#endif - - if (bd->bi_dram[0].size) - display_dram_config(); - - gd->bd->bi_boot_params = malloc(CONFIG_SYS_BOOTPARAMS_LEN); - if (!gd->bd->bi_boot_params) - puts("WARNING: Cannot allocate space for boot parameters\n"); - - /* initialize environment */ - env_relocate(); - - stdio_init(); - jumptable_init(); - console_init_r(); - - /* Initialize from environment */ - load_addr = getenv_ulong("loadaddr", 16, load_addr); - -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#if defined(CONFIG_CMD_NET) - puts("Net: "); - eth_initialize(gd->bd); -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI - mmc_initialize(gd->bd); -#endif - for (;;) { - main_loop(); - } -} diff --git a/qemu/roms/u-boot/arch/avr32/lib/bootm.c b/qemu/roms/u-boot/arch/avr32/lib/bootm.c deleted file mode 100644 index 1c26f1b36..000000000 --- a/qemu/roms/u-boot/arch/avr32/lib/bootm.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <image.h> -#include <u-boot/zlib.h> -#include <asm/byteorder.h> -#include <asm/arch/addrspace.h> -#include <asm/io.h> -#include <asm/setup.h> -#include <asm/arch/clk.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* CPU-specific hook to allow flushing of caches, etc. */ -extern void prepare_to_boot(void); - -static struct tag *setup_start_tag(struct tag *params) -{ - params->hdr.tag = ATAG_CORE; - params->hdr.size = tag_size(tag_core); - - params->u.core.flags = 0; - params->u.core.pagesize = 4096; - params->u.core.rootdev = 0; - - return tag_next(params); -} - -static struct tag *setup_memory_tags(struct tag *params) -{ - bd_t *bd = gd->bd; - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - params->hdr.tag = ATAG_MEM; - params->hdr.size = tag_size(tag_mem_range); - - params->u.mem_range.addr = bd->bi_dram[i].start; - params->u.mem_range.size = bd->bi_dram[i].size; - - params = tag_next(params); - } - - return params; -} - -static struct tag *setup_commandline_tag(struct tag *params, char *cmdline) -{ - if (!cmdline) - return params; - - /* eat leading white space */ - while (*cmdline == ' ') cmdline++; - - /* - * Don't include tags for empty command lines; let the kernel - * use its default command line. - */ - if (*cmdline == '\0') - return params; - - params->hdr.tag = ATAG_CMDLINE; - params->hdr.size = - (sizeof (struct tag_header) + strlen(cmdline) + 1 + 3) >> 2; - strcpy(params->u.cmdline.cmdline, cmdline); - - return tag_next(params); -} - -static struct tag *setup_ramdisk_tag(struct tag *params, - unsigned long rd_start, - unsigned long rd_end) -{ - if (rd_start == rd_end) - return params; - - params->hdr.tag = ATAG_RDIMG; - params->hdr.size = tag_size(tag_mem_range); - - params->u.mem_range.addr = rd_start; - params->u.mem_range.size = rd_end - rd_start; - - return tag_next(params); -} - -static struct tag *setup_clock_tags(struct tag *params) -{ - params->hdr.tag = ATAG_CLOCK; - params->hdr.size = tag_size(tag_clock); - params->u.clock.clock_id = ACLOCK_BOOTCPU; - params->u.clock.clock_flags = 0; - params->u.clock.clock_hz = gd->arch.cpu_hz; - -#ifdef CONFIG_AT32AP7000 - /* - * New kernels don't need this, but we should be backwards - * compatible for a while... - */ - params = tag_next(params); - - params->hdr.tag = ATAG_CLOCK; - params->hdr.size = tag_size(tag_clock); - params->u.clock.clock_id = ACLOCK_HSB; - params->u.clock.clock_flags = 0; - params->u.clock.clock_hz = get_hsb_clk_rate(); -#endif - - return tag_next(params); -} - -static struct tag *setup_ethernet_tag(struct tag *params, - char *addr, int index) -{ - char *s, *e; - int i; - - params->hdr.tag = ATAG_ETHERNET; - params->hdr.size = tag_size(tag_ethernet); - - params->u.ethernet.mac_index = index; - params->u.ethernet.mii_phy_addr = gd->bd->bi_phy_id[index]; - - s = addr; - for (i = 0; i < 6; i++) { - params->u.ethernet.hw_address[i] = simple_strtoul(s, &e, 16); - s = e + 1; - } - - return tag_next(params); -} - -static struct tag *setup_ethernet_tags(struct tag *params) -{ - char name[16] = "ethaddr"; - char *addr; - int i = 0; - - do { - addr = getenv(name); - if (addr) - params = setup_ethernet_tag(params, addr, i); - sprintf(name, "eth%daddr", ++i); - } while (i < 4); - - return params; -} - -static struct tag *setup_boardinfo_tag(struct tag *params) -{ - params->hdr.tag = ATAG_BOARDINFO; - params->hdr.size = tag_size(tag_boardinfo); - - params->u.boardinfo.board_number = gd->bd->bi_board_number; - - return tag_next(params); -} - -static void setup_end_tag(struct tag *params) -{ - params->hdr.tag = ATAG_NONE; - params->hdr.size = 0; -} - -int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) -{ - void (*theKernel)(int magic, void *tagtable); - struct tag *params, *params_start; - char *commandline = getenv("bootargs"); - - /* - * allow the PREP bootm subcommand, it is required for bootm to work - * - * TODO: Andreas Bießmann <andreas.devel@googlemail.com> refactor the - * do_bootm_linux() for avr32 - */ - if (flag & BOOTM_STATE_OS_PREP) - return 0; - - if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) - return 1; - - theKernel = (void *)images->ep; - - bootstage_mark(BOOTSTAGE_ID_RUN_OS); - - params = params_start = (struct tag *)gd->bd->bi_boot_params; - params = setup_start_tag(params); - params = setup_memory_tags(params); - if (images->rd_start) { - params = setup_ramdisk_tag(params, - PHYSADDR(images->rd_start), - PHYSADDR(images->rd_end)); - } - params = setup_commandline_tag(params, commandline); - params = setup_clock_tags(params); - params = setup_ethernet_tags(params); - params = setup_boardinfo_tag(params); - setup_end_tag(params); - - printf("\nStarting kernel at %p (params at %p)...\n\n", - theKernel, params_start); - - prepare_to_boot(); - - theKernel(ATAG_MAGIC, params_start); - /* does not return */ - - return 1; -} diff --git a/qemu/roms/u-boot/arch/avr32/lib/interrupts.c b/qemu/roms/u-boot/arch/avr32/lib/interrupts.c deleted file mode 100644 index bacb2d186..000000000 --- a/qemu/roms/u-boot/arch/avr32/lib/interrupts.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#include <asm/sysreg.h> - -void enable_interrupts(void) -{ - asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET)); -} - -int disable_interrupts(void) -{ - unsigned long sr; - - sr = sysreg_read(SR); - asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET)); - -#ifdef CONFIG_AT32UC3A0xxx - /* Two NOPs are required after masking interrupts on the - * AT32UC3A0512ES. See errata 41.4.5.5. */ - asm("nop"); - asm("nop"); -#endif - - return !SYSREG_BFEXT(GM, sr); -} diff --git a/qemu/roms/u-boot/arch/avr32/lib/memset.S b/qemu/roms/u-boot/arch/avr32/lib/memset.S deleted file mode 100644 index ac2d38860..000000000 --- a/qemu/roms/u-boot/arch/avr32/lib/memset.S +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - /* - * r12: void *b - * r11: int c - * r10: size_t len - * - * Returns b in r12 - */ - .section .text.memset, "ax", @progbits - - .global memset - .type memset, @function - .align 2 -memset: - mov r9, r12 - mov r8, r12 - or r11, r11, r11 << 8 - andl r9, 3, COH - brne 1f - -2: or r11, r11, r11 << 16 - sub r10, 4 - brlt 5f - - /* Let's do some real work */ -4: st.w r8++, r11 - sub r10, 4 - brge 4b - - /* - * When we get here, we've got less than 4 bytes to set. r10 - * might be negative. - */ -5: sub r10, -4 - reteq r12 - - /* Fastpath ends here, exactly 32 bytes from memset */ - - /* Handle unaligned count or pointer */ - bld r10, 1 - brcc 6f - st.b r8++, r11 - st.b r8++, r11 - bld r10, 0 - retcc r12 -6: st.b r8++, r11 - mov pc, lr - - /* Handle unaligned pointer */ -1: sub r10, 4 - brlt 5b - add r10, r9 - lsl r9, 1 - add pc, r9 - st.b r8++, r11 - st.b r8++, r11 - st.b r8++, r11 - rjmp 2b - - .size memset, . - memset |