Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

1050 files changed, 175116 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/arch/arm/config.mk b/qemu/roms/u-boot/arch/arm/config.mk
new file mode 100644
index 000000000..66ecc2ee4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/config.mk
@@ -0,0 +1,131 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifndef CONFIG_STANDALONE_LOAD_ADDR
+ifneq ($(CONFIG_OMAP_COMMON),)
+CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
+else
+CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
+endif
+endif
+
+LDFLAGS_FINAL += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
+		     -fno-common -ffixed-r9
+PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
+      $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
+
+# Support generic board on ARM
+__HAVE_ARCH_GENERIC_BOARD := y
+
+PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
+
+# Choose between ARM/Thumb instruction sets
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+PF_CPPFLAGS_ARM := $(call cc-option, -mthumb -mthumb-interwork,\
+			$(call cc-option,-marm,)\
+			$(call cc-option,-mno-thumb-interwork,)\
+		)
+else
+PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \
+		$(call cc-option,-mno-thumb-interwork,)
+endif
+
+# Only test once
+ifneq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+archprepare: checkthumb
+
+checkthumb:
+	@if test "$(call cc-version)" -lt "0404"; then \
+		echo -n '*** Your GCC does not produce working '; \
+		echo 'binaries in THUMB mode.'; \
+		echo '*** Your board is configured for THUMB mode.'; \
+		false; \
+	fi
+endif
+endif
+
+# Try if EABI is supported, else fall back to old API,
+# i. e. for example:
+# - with ELDK 4.2 (EABI supported), use:
+#	-mabi=aapcs-linux
+# - with ELDK 4.1 (gcc 4.x, no EABI), use:
+#	-mabi=apcs-gnu
+# - with ELDK 3.1 (gcc 3.x), use:
+#	-mapcs-32
+PF_CPPFLAGS_ABI := $(call cc-option,\
+			-mabi=aapcs-linux,\
+			$(call cc-option,\
+				-mapcs-32,\
+				$(call cc-option,\
+					-mabi=apcs-gnu,\
+				)\
+			)\
+		)
+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARM) $(PF_CPPFLAGS_ABI)
+
+# For EABI, make sure to provide raise()
+ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
+# This file is parsed many times, so the string may get added multiple
+# times. Also, the prefix needs to be different based on whether
+# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry
+# before adding the correct one.
+PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \
+	$(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
+endif
+
+# needed for relocation
+LDFLAGS_u-boot += -pie
+
+#
+# FIXME: binutils versions < 2.22 have a bug in the assembler where
+# branches to weak symbols can be incorrectly optimized in thumb mode
+# to a short branch (b.n instruction) that won't reach when the symbol
+# gets preempted
+#
+# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
+#
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+ifeq ($(GAS_BUG_12532),)
+export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
+	then echo y; else echo n; fi)
+endif
+ifeq ($(GAS_BUG_12532),y)
+PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
+endif
+endif
+
+ifneq ($(CONFIG_SPL_BUILD),y)
+# Check that only R_ARM_RELATIVE relocations are generated.
+ALL-y += checkarmreloc
+# The movt / movw can hardcode 16 bit parts of the addresses in the
+# instruction. Relocation is not supported for that case, so disable
+# such usage by requiring word relocations.
+PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
+endif
+
+# limit ourselves to the sections we want in the .bin.
+ifdef CONFIG_ARM64
+OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+else
+OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
+endif
+
+ifneq ($(CONFIG_IMX_CONFIG),)
+ifdef CONFIG_SPL
+ifndef CONFIG_SPL_BUILD
+ALL-y += SPL
+endif
+else
+ifeq ($(CONFIG_OF_SEPARATE),y)
+ALL-y += u-boot-dtb.imx
+else
+ALL-y += u-boot.imx
+endif
+endif
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/Makefile b/qemu/roms/u-boot/arch/arm/cpu/Makefile
new file mode 100644
index 000000000..35d8d387b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/Makefile
@@ -0,0 +1,6 @@
+obj-$(CONFIG_AT91FAMILY) += at91-common/
+obj-$(CONFIG_TEGRA20) += tegra20-common/
+obj-$(CONFIG_TEGRA30) += tegra30-common/
+obj-$(CONFIG_TEGRA114) += tegra114-common/
+obj-$(CONFIG_TEGRA124) += tegra124-common/
+obj-$(CONFIG_TEGRA) += tegra-common/
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm1136/Makefile
new file mode 100644
index 000000000..3279f125f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+obj-y	= cpu.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/config.mk b/qemu/roms/u-boot/arch/arm/cpu/arm1136/config.mk
new file mode 100644
index 000000000..a82c6cec9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# Make ARMv5 to allow more compilers to work, even though its v6.
+PLATFORM_CPPFLAGS += -march=armv5
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm1136/cpu.c
new file mode 100644
index 000000000..a7aed4b2b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/cpu.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+#ifdef CONFIG_LCD
+	{
+		extern void lcd_disable(void);
+		extern void lcd_panel_disable(void);
+
+		lcd_disable(); /* proper disable of lcd & panel */
+		lcd_panel_disable();
+	}
+#endif
+
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+	/* flush I/D-cache */
+	cache_flush();
+
+	return 0;
+}
+
+static void cache_flush(void)
+{
+	unsigned long i = 0;
+	/* clean entire data cache */
+	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+	/* invalidate both caches and flush btb */
+	asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+	/* mem barrier to sync things */
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#endif
+
+void invalidate_dcache_all(void)
+{
+	asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+}
+
+void flush_dcache_all(void)
+{
+	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (!check_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (!check_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/Makefile
new file mode 100644
index 000000000..9670ed938
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= generic.o
+obj-y	+= timer.o
+obj-y	+= devices.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/devices.c
new file mode 100644
index 000000000..ae5db86da
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/devices.c
@@ -0,0 +1,51 @@
+/*
+ *
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+void mx31_uart1_hw_init(void)
+{
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+}
+
+void mx31_uart2_hw_init(void)
+{
+	/* setup pins for UART2 */
+	mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
+	mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
+}
+
+#ifdef CONFIG_MXC_SPI
+/*
+ * Note: putting several spi setups here makes no sense as they may differ
+ * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
+ */
+void mx31_spi2_hw_init(void)
+{
+	/* SPI2 */
+	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
+
+	/* start SPI2 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/generic.c b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/generic.c
new file mode 100644
index 000000000..060d46b82
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/generic.c
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+static u32 mx31_decode_pll(u32 reg, u32 infreq)
+{
+	u32 mfi = GET_PLL_MFI(reg);
+	s32 mfn = GET_PLL_MFN(reg);
+	u32 mfd = GET_PLL_MFD(reg);
+	u32 pd =  GET_PLL_PD(reg);
+
+	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
+	mfd += 1;
+	pd += 1;
+
+	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+		mfd * pd);
+}
+
+static u32 mx31_get_mpl_dpdgck_clk(void)
+{
+	u32 infreq;
+
+	if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+		infreq = MXC_CLK32 * 1024;
+	else
+		infreq = MXC_HCLK;
+
+	return mx31_decode_pll(readl(CCM_MPCTL), infreq);
+}
+
+static u32 mx31_get_mcu_main_clk(void)
+{
+	/* For now we assume mpl_dpdgck_clk == mcu_main_clk
+	 * which should be correct for most boards
+	 */
+	return mx31_get_mpl_dpdgck_clk();
+}
+
+static u32 mx31_get_ipg_clk(void)
+{
+	u32 freq = mx31_get_mcu_main_clk();
+	u32 pdr0 = readl(CCM_PDR0);
+
+	freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
+	freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
+
+	return freq;
+}
+
+/* hsp is the clock for the ipu */
+static u32 mx31_get_hsp_clk(void)
+{
+	u32 freq = mx31_get_mcu_main_clk();
+	u32 pdr0 = readl(CCM_PDR0);
+
+	freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
+
+	return freq;
+}
+
+void mx31_dump_clocks(void)
+{
+	u32 cpufreq = mx31_get_mcu_main_clk();
+	printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
+	printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
+	printf("hsp clock     : %dHz\n", mx31_get_hsp_clk());
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return mx31_get_mcu_main_clk();
+	case MXC_IPG_CLK:
+	case MXC_IPG_PERCLK:
+	case MXC_CSPI_CLK:
+	case MXC_UART_CLK:
+	case MXC_ESDHC_CLK:
+	case MXC_I2C_CLK:
+		return mx31_get_ipg_clk();
+	case MXC_IPU_CLK:
+		return mx31_get_hsp_clk();
+	}
+	return -1;
+}
+
+u32 imx_get_uartclk(void)
+{
+	return mxc_get_clock(MXC_UART_CLK);
+}
+
+void mx31_gpio_mux(unsigned long mode)
+{
+	unsigned long reg, shift, tmp;
+
+	reg = IOMUXC_BASE + (mode & 0x1fc);
+	shift = (~mode & 0x3) * 8;
+
+	tmp = readl(reg);
+	tmp &= ~(0xff << shift);
+	tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
+	writel(tmp, reg);
+}
+
+void mx31_set_pad(enum iomux_pins pin, u32 config)
+{
+	u32 field, l, reg;
+
+	pin &= IOMUX_PADNUM_MASK;
+	reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
+	field = (pin + 2) % 3;
+
+	l = readl(reg);
+	l &= ~(0x1ff << (field * 10));
+	l |= config << (field * 10);
+	writel(l, reg);
+
+}
+
+void mx31_set_gpr(enum iomux_gp_func gp, char en)
+{
+	u32 l;
+	struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
+
+	l = readl(&iomuxc->gpr);
+	if (en)
+		l |= gp;
+	else
+		l &= ~gp;
+
+	writel(l, &iomuxc->gpr);
+}
+
+void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
+{
+	struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
+	struct mx31_weim_cscr *cscr = &weim->cscr[cs];
+
+	writel(weimcs->upper, &cscr->upper);
+	writel(weimcs->lower, &cscr->lower);
+	writel(weimcs->additional, &cscr->additional);
+}
+
+struct mx3_cpu_type mx31_cpu_type[] = {
+	{ .srev = 0x00, .v = 0x10 },
+	{ .srev = 0x10, .v = 0x11 },
+	{ .srev = 0x11, .v = 0x11 },
+	{ .srev = 0x12, .v = 0x1F },
+	{ .srev = 0x13, .v = 0x1F },
+	{ .srev = 0x14, .v = 0x12 },
+	{ .srev = 0x15, .v = 0x12 },
+	{ .srev = 0x28, .v = 0x20 },
+	{ .srev = 0x29, .v = 0x20 },
+};
+
+u32 get_cpu_rev(void)
+{
+	u32 i, srev;
+
+	/* read SREV register from IIM module */
+	struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
+	srev = readl(&iim->iim_srev);
+
+	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
+		if (srev == mx31_cpu_type[i].srev)
+			return mx31_cpu_type[i].v;
+
+	return srev | 0x8000;
+}
+
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct clock_control_regs *ccm =
+		(struct clock_control_regs *)CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x07;
+
+	switch (cause) {
+	case 0x0000:
+		return "POR";
+	case 0x0001:
+		return "RST";
+	case 0x0002:
+		return "WDOG";
+	case 0x0006:
+		return "JTAG";
+	case 0x0007:
+		return "ARM11P power gating";
+	default:
+		return "unknown reset";
+	}
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 srev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
+			(srev & 0xF0) >> 4, (srev & 0x0F),
+			((srev & 0x8000) ? " unknown" : ""),
+			mx31_get_mcu_main_clk() / 1000000);
+	printf("Reset cause: %s\n", get_reset_cause());
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/timer.c
new file mode 100644
index 000000000..f111242e5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx31/timer.c
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <div64.h>
+#include <watchdog.h>
+#include <asm/io.h>
+
+#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
+
+/* General purpose timers registers */
+#define GPTCR	__REG(TIMER_BASE)		/* Control register	*/
+#define GPTPR	__REG(TIMER_BASE + 0x4)		/* Prescaler register	*/
+#define GPTSR	__REG(TIMER_BASE + 0x8)		/* Status register	*/
+#define GPTCNT	__REG(TIMER_BASE + 0x24)	/* Counter register	*/
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
+#define GPTCR_FRR		(1 << 9)	/* Freerun / restart	*/
+#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source		*/
+#define GPTCR_TEN		1		/* Timer enable		*/
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+
+#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, MXC_CLK32);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	time *= MXC_CLK32;
+	do_div(time, CONFIG_SYS_HZ);
+	return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us = us * MXC_CLK32 + 999999;
+	do_div(us, 1000000);
+	return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME	((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK	(1000000 / MXC_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	do_div(tick, TICK_PER_TIME);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us += US_PER_TICK - 1;
+	do_div(us, US_PER_TICK);
+	return us;
+}
+#endif
+
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
+int timer_init(void)
+{
+	int i;
+
+	/* setup GP Timer 1 */
+	GPTCR = GPTCR_SWR;
+	for (i = 0; i < 100; i++)
+		GPTCR = 0; /* We have no udelay by now */
+	GPTPR = 0; /* 32Khz */
+	/* Freerun Mode, PERCLK1 input */
+	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	ulong now = GPTCNT; /* current tick value */
+
+	if (now >= gd->arch.lastinc)	/* normal mode (non roll) */
+		/* move stamp forward with absolut diff ticks */
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	else			/* we have rollover of incrementer */
+		gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
+}
+
+ulong get_timer_masked(void)
+{
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return MXC_CLK32;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/Makefile
new file mode 100644
index 000000000..c533215c3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= generic.o
+obj-y	+= timer.o
+obj-y	+= mx35_sdram.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/generic.c b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/generic.c
new file mode 100644
index 000000000..8d3f92cae
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/generic.c
@@ -0,0 +1,547 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+#include <netdev.h>
+#include <spl.h>
+
+#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
+#define CLK_CODE_ARM(c)		(((c) >> 16) & 0xFF)
+#define CLK_CODE_AHB(c)		(((c) >>  8) & 0xFF)
+#define CLK_CODE_PATH(c)	((c) & 0xFF)
+
+#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+static int g_clk_mux_auto[8] = {
+	CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
+	CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
+};
+
+static int g_clk_mux_consumer[16] = {
+	CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
+	-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
+	CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
+	-1, -1, CLK_CODE(4, 2, 0), -1,
+};
+
+static int hsp_div_table[3][16] = {
+	{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
+	{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
+	{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
+};
+
+u32 get_cpu_rev(void)
+{
+	int reg;
+	struct iim_regs *iim =
+		(struct iim_regs *)IIM_BASE_ADDR;
+	reg = readl(&iim->iim_srev);
+	if (!reg) {
+		reg = readw(ROMPATCH_REV);
+		reg <<= 4;
+	} else {
+		reg += CHIP_REV_1_0;
+	}
+
+	return 0x35000 + (reg & 0xFF);
+}
+
+static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
+{
+	int *pclk_mux;
+	if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
+		pclk_mux = g_clk_mux_consumer +
+			((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
+			MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
+	} else {
+		pclk_mux = g_clk_mux_auto +
+			((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
+			MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
+	}
+
+	if ((*pclk_mux) == -1)
+		return -1;
+
+	if (fi && fd) {
+		if (!CLK_CODE_PATH(*pclk_mux)) {
+			*fi = *fd = 1;
+			return CLK_CODE_ARM(*pclk_mux);
+		}
+		if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
+			*fi = 3;
+			*fd = 4;
+		} else {
+			*fi = 2;
+			*fd = 3;
+		}
+	}
+	return CLK_CODE_ARM(*pclk_mux);
+}
+
+static int get_ahb_div(u32 pdr0)
+{
+	int *pclk_mux;
+
+	pclk_mux = g_clk_mux_consumer +
+		((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
+		MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
+
+	if ((*pclk_mux) == -1)
+		return -1;
+
+	return CLK_CODE_AHB(*pclk_mux);
+}
+
+static u32 decode_pll(u32 reg, u32 infreq)
+{
+	u32 mfi = (reg >> 10) & 0xf;
+	s32 mfn = reg & 0x3ff;
+	u32 mfd = (reg >> 16) & 0x3ff;
+	u32 pd = (reg >> 26) & 0xf;
+
+	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
+	mfd += 1;
+	pd += 1;
+
+	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+		mfd * pd);
+}
+
+static u32 get_mcu_main_clk(void)
+{
+	u32 arm_div = 0, fi = 0, fd = 0;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
+	fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
+	return fi / (arm_div * fd);
+}
+
+static u32 get_ipg_clk(void)
+{
+	u32 freq = get_mcu_main_clk();
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 pdr0 = readl(&ccm->pdr0);
+
+	return freq / (get_ahb_div(pdr0) * 2);
+}
+
+static u32 get_ipg_per_clk(void)
+{
+	u32 freq = get_mcu_main_clk();
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 pdr0 = readl(&ccm->pdr0);
+	u32 pdr4 = readl(&ccm->pdr4);
+	u32 div;
+	if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
+		div = CCM_GET_DIVIDER(pdr4,
+			MXC_CCM_PDR4_PER0_PODF_MASK,
+			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
+	} else {
+		div = CCM_GET_DIVIDER(pdr0,
+			MXC_CCM_PDR0_PER_PODF_MASK,
+			MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
+		div *= get_ahb_div(pdr0);
+	}
+	return freq / div;
+}
+
+u32 imx_get_uartclk(void)
+{
+	u32 freq;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 pdr4 = readl(&ccm->pdr4);
+
+	if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
+		freq = get_mcu_main_clk();
+	else
+		freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
+	freq /= CCM_GET_DIVIDER(pdr4,
+			MXC_CCM_PDR4_UART_PODF_MASK,
+			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
+	return freq;
+}
+
+unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
+{
+	u32 nfc_pdf, hsp_podf;
+	u32 pll, ret_val = 0, usb_podf;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 reg = readl(&ccm->pdr0);
+	u32 reg4 = readl(&ccm->pdr4);
+
+	reg |= 0x1;
+
+	switch (clk) {
+	case CPU_CLK:
+		ret_val = get_mcu_main_clk();
+		break;
+	case AHB_CLK:
+		ret_val = get_mcu_main_clk();
+		break;
+	case HSP_CLK:
+		if (reg & CLKMODE_CONSUMER) {
+			hsp_podf = (reg >> 20) & 0x3;
+			pll = get_mcu_main_clk();
+			hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
+			if (hsp_podf > 0) {
+				ret_val = pll / hsp_podf;
+			} else {
+				puts("mismatch HSP with ARM clock setting\n");
+				ret_val = 0;
+			}
+		} else {
+			ret_val = get_mcu_main_clk();
+		}
+		break;
+	case IPG_CLK:
+		ret_val = get_ipg_clk();
+		break;
+	case IPG_PER_CLK:
+		ret_val = get_ipg_per_clk();
+		break;
+	case NFC_CLK:
+		nfc_pdf = (reg4 >> 28) & 0xF;
+		pll = get_mcu_main_clk();
+		/* AHB/nfc_pdf */
+		ret_val = pll / (nfc_pdf + 1);
+		break;
+	case USB_CLK:
+		usb_podf = (reg4 >> 22) & 0x3F;
+		if (reg4 & 0x200)
+			pll = get_mcu_main_clk();
+		else
+			pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
+
+		ret_val = pll / (usb_podf + 1);
+		break;
+	default:
+		printf("Unknown clock: %d\n", clk);
+		break;
+	}
+
+	return ret_val;
+}
+unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
+{
+	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 mpdr2 = readl(&ccm->pdr2);
+	u32 mpdr3 = readl(&ccm->pdr3);
+	u32 mpdr4 = readl(&ccm->pdr4);
+
+	switch (clk) {
+	case UART1_BAUD:
+	case UART2_BAUD:
+	case UART3_BAUD:
+		clk_sel = mpdr3 & (1 << 14);
+		pdf = (mpdr4 >> 10) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case SSI1_BAUD:
+		pre_pdf = (mpdr2 >> 24) & 0x7;
+		pdf = mpdr2 & 0x3F;
+		clk_sel = mpdr2 & (1 << 6);
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	case SSI2_BAUD:
+		pre_pdf = (mpdr2 >> 27) & 0x7;
+		pdf = (mpdr2 >> 8) & 0x3F;
+		clk_sel = mpdr2 & (1 << 6);
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	case CSI_BAUD:
+		clk_sel = mpdr2 & (1 << 7);
+		pdf = (mpdr2 >> 16) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case MSHC_CLK:
+		pre_pdf = readl(&ccm->pdr1);
+		clk_sel = (pre_pdf & 0x80);
+		pdf = (pre_pdf >> 22) & 0x3F;
+		pre_pdf = (pre_pdf >> 28) & 0x7;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	case ESDHC1_CLK:
+		clk_sel = mpdr3 & 0x40;
+		pdf = mpdr3 & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case ESDHC2_CLK:
+		clk_sel = mpdr3 & 0x40;
+		pdf = (mpdr3 >> 8) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case ESDHC3_CLK:
+		clk_sel = mpdr3 & 0x40;
+		pdf = (mpdr3 >> 16) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case SPDIF_CLK:
+		clk_sel = mpdr3 & 0x400000;
+		pre_pdf = (mpdr3 >> 29) & 0x7;
+		pdf = (mpdr3 >> 23) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	default:
+		printf("%s(): This clock: %d not supported yet\n",
+				__func__, clk);
+		break;
+	}
+
+	return ret_val;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return get_mcu_main_clk();
+	case MXC_AHB_CLK:
+		break;
+	case MXC_IPG_CLK:
+		return get_ipg_clk();
+	case MXC_IPG_PERCLK:
+	case MXC_I2C_CLK:
+		return get_ipg_per_clk();
+	case MXC_UART_CLK:
+		return imx_get_uartclk();
+	case MXC_ESDHC1_CLK:
+		return mxc_get_peri_clock(ESDHC1_CLK);
+	case MXC_ESDHC2_CLK:
+		return mxc_get_peri_clock(ESDHC2_CLK);
+	case MXC_ESDHC3_CLK:
+		return mxc_get_peri_clock(ESDHC3_CLK);
+	case MXC_USB_CLK:
+		return mxc_get_main_clock(USB_CLK);
+	case MXC_FEC_CLK:
+		return get_ipg_clk();
+	case MXC_CSPI_CLK:
+		return get_ipg_clk();
+	}
+	return -1;
+}
+
+#ifdef CONFIG_FEC_MXC
+/*
+ * The MX35 has no fuse for MAC, return a NULL MAC
+ */
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	memset(mac, 0, 6);
+}
+
+u32 imx_get_fecclk(void)
+{
+	return mxc_get_clock(MXC_IPG_CLK);
+}
+#endif
+
+int do_mx35_showclocks(cmd_tbl_t *cmdtp,
+	int flag, int argc, char * const argv[])
+{
+	u32 cpufreq = get_mcu_main_clk();
+	printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
+	printf("ipg clock     : %dHz\n", get_ipg_clk());
+	printf("ipg per clock : %dHz\n", get_ipg_per_clk());
+	printf("uart clock    : %dHz\n", mxc_get_clock(MXC_UART_CLK));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
+	"display clocks",
+	""
+);
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x0F;
+
+	switch (cause) {
+	case 0x0000:
+		return "POR";
+	case 0x0002:
+		return "JTAG";
+	case 0x0004:
+		return "RST";
+	case 0x0008:
+		return "WDOG";
+	default:
+		return "unknown reset";
+	}
+}
+
+int print_cpuinfo(void)
+{
+	u32 srev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX35 rev %d.%d at %d MHz.\n",
+		(srev & 0xF0) >> 4, (srev & 0x0F),
+		get_mcu_main_clk() / 1000000);
+
+	printf("Reset cause: %s\n", get_reset_cause());
+
+	return 0;
+}
+#endif
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+	rc = fecmxc_initialize(bis);
+#endif
+
+	return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
+#endif
+	return 0;
+}
+
+#define RCSR_MEM_CTL_WEIM	0
+#define RCSR_MEM_CTL_NAND	1
+#define RCSR_MEM_CTL_ATA	2
+#define RCSR_MEM_CTL_EXPANSION	3
+#define RCSR_MEM_TYPE_NOR	0
+#define RCSR_MEM_TYPE_ONENAND	2
+#define RCSR_MEM_TYPE_SD	0
+#define RCSR_MEM_TYPE_I2C	2
+#define RCSR_MEM_TYPE_SPI	3
+
+u32 spl_boot_device(void)
+{
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 rcsr = readl(&ccm->rcsr);
+	u32 mem_type, mem_ctl;
+
+	/* In external mode, no boot device is returned */
+	if ((rcsr >> 10) & 0x03)
+		return BOOT_DEVICE_NONE;
+
+	mem_ctl = (rcsr >> 25) & 0x03;
+	mem_type = (rcsr >> 23) & 0x03;
+
+	switch (mem_ctl) {
+	case RCSR_MEM_CTL_WEIM:
+		switch (mem_type) {
+		case RCSR_MEM_TYPE_NOR:
+			return BOOT_DEVICE_NOR;
+		case RCSR_MEM_TYPE_ONENAND:
+			return BOOT_DEVICE_ONENAND;
+		default:
+			return BOOT_DEVICE_NONE;
+		}
+	case RCSR_MEM_CTL_NAND:
+		return BOOT_DEVICE_NAND;
+	case RCSR_MEM_CTL_EXPANSION:
+		switch (mem_type) {
+		case RCSR_MEM_TYPE_SD:
+			return BOOT_DEVICE_MMC1;
+		case RCSR_MEM_TYPE_I2C:
+			return BOOT_DEVICE_I2C;
+		case RCSR_MEM_TYPE_SPI:
+			return BOOT_DEVICE_SPI;
+		default:
+			return BOOT_DEVICE_NONE;
+		}
+	}
+
+	return BOOT_DEVICE_NONE;
+}
+
+#ifdef CONFIG_SPL_BUILD
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+		return MMCSD_MODE_FAT;
+#else
+		return MMCSD_MODE_RAW;
+#endif
+		break;
+	case BOOT_DEVICE_NAND:
+		return 0;
+		break;
+	default:
+		puts("spl: ERROR:  unsupported device\n");
+		hang();
+	}
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/mx35_sdram.c b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
new file mode 100644
index 000000000..d358f5f2f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+
+#define ESDCTL_DDR2_EMR2	0x04000000
+#define ESDCTL_DDR2_EMR3	0x06000000
+#define ESDCTL_PRECHARGE	0x00000400
+#define ESDCTL_DDR2_EN_DLL	0x02000400
+#define ESDCTL_DDR2_RESET_DLL	0x00000333
+#define ESDCTL_DDR2_MR		0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+enum {
+	SMODE_NORMAL =	0,
+	SMODE_PRECHARGE,
+	SMODE_AUTO_REFRESH,
+	SMODE_LOAD_REG,
+	SMODE_MANUAL_REFRESH
+};
+
+#define set_mode(x, en, m)	(x | (en << 31) | (m << 28))
+
+static inline void dram_wait(unsigned int count)
+{
+	volatile unsigned int wait = count;
+
+	while (wait--)
+		;
+
+}
+
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+	u32 row, u32 col, u32 dsize, u32 refresh)
+{
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+	u32 *cfg_reg, *ctl_reg;
+	u32 val;
+	u32 ctlval;
+
+	switch (start_address) {
+	case CSD0_BASE_ADDR:
+		cfg_reg = &esdc->esdcfg0;
+		ctl_reg = &esdc->esdctl0;
+		break;
+	case CSD1_BASE_ADDR:
+		cfg_reg = &esdc->esdcfg1;
+		ctl_reg = &esdc->esdctl1;
+		break;
+	default:
+		return;
+	}
+
+	/* The MX35 supports 11 up to 14 rows */
+	if (row < 11 || row > 14 || col < 8 || col > 10)
+		return;
+	ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
+
+	/* Initialize MISC register for DDR2 */
+	val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+		ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+	writel(val, &esdc->esdmisc);
+	val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+	writel(val, &esdc->esdmisc);
+
+	/*
+	 * according to DDR2 specs, wait a while before
+	 * the PRECHARGE_ALL command
+	 */
+	dram_wait(0x20000);
+
+	/* Load DDR2 config and timing */
+	writel(ddr2_config, cfg_reg);
+
+	/* Precharge ALL */
+	writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+		ctl_reg);
+	writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+	/* Load mode */
+	writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+		ctl_reg);
+	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+	/* Precharge ALL */
+	writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+		ctl_reg);
+	writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+	/* Set mode auto refresh : at least two refresh are required */
+	writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
+		ctl_reg);
+	writel(0xda, start_address);
+	writel(0xda, start_address);
+
+	writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+		ctl_reg);
+	writeb(0xda, start_address + ESDCTL_DDR2_MR);
+	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+	/* OCD mode exit */
+	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+	/* Set normal mode */
+	writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
+		ctl_reg);
+
+	dram_wait(0x20000);
+
+	/* Do not set delay lines, only for MDDR */
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/timer.c
new file mode 100644
index 000000000..cc6166f93
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/mx35/timer.c
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp	(gd->arch.tbl)
+#define lastinc		(gd->arch.lastinc)
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR       (1<<15)	/* Software reset */
+#define GPTCR_FRR       (1<<9)	/* Freerun / restart */
+#define GPTCR_CLKSOURCE_32   (4<<6)	/* Clock source */
+#define GPTCR_TEN       (1)	/* Timer enable */
+
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, MXC_CLK32);
+
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us = us * MXC_CLK32 + 999999;
+	do_div(us, 1000000);
+
+	return us;
+}
+
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ * The 32KHz 32-bit timer overruns in 134217 seconds
+ */
+int timer_init(void)
+{
+	int i;
+	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+	struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
+
+	/* setup GP Timer 1 */
+	writel(GPTCR_SWR, &gpt->ctrl);
+
+	writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
+
+	for (i = 0; i < 100; i++)
+		writel(0, &gpt->ctrl); /* We have no udelay by now */
+	writel(0, &gpt->pre); /* prescaler = 1 */
+	/* Freerun Mode, 32KHz input */
+	writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+			&gpt->ctrl);
+	writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+	ulong now = readl(&gpt->counter); /* current tick value */
+
+	if (now >= lastinc) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp forward with absolut diff ticks
+		 */
+		timestamp += (now - lastinc);
+	} else {
+		/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	}
+	lastinc = now;
+	return timestamp;
+}
+
+ulong get_timer_masked(void)
+{
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return MXC_CLK32;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm1136/start.S
new file mode 100644
index 000000000..3e2358e13
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/start.S
@@ -0,0 +1,346 @@
+/*
+ *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
+ *
+ *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+.globl _start
+_start: b	reset
+#ifdef CONFIG_SPL_BUILD
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+
+_hang:
+	.word	do_hang
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678	/* now 16*4=64 */
+#else
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_SPL_BUILD */
+.global _end_vect
+_end_vect:
+
+	.balignl 16,0xdeadbeef
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/* the mask ROM code should have PLL and others stable */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl  cpu_init_crit
+#endif
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+	bx	lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Jump to board specific initialization... The Mask ROM will have already initialized
+	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
+	 */
+	mov	ip, lr		/* persevere link reg across call */
+	bl	lowlevel_init	/* go setup pll,mux,memory */
+	mov	lr, ip		/* restore link */
+	mov	pc, lr		/* back to my caller */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
+	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
+
+	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
+	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp				@ save current stack into r0 (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
+
+	str	lr, [r13]			@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13			@ switch modes, make sure moves will execute
+	mov	lr, pc				@ capture return pc
+	movs	pc, lr				@ jump to next instruction & switch modes.
+	.endm
+
+	.macro get_bad_stack_swi
+	sub	r13, r13, #4			@ space on current stack for scratch reg.
+	str	r0, [r13]			@ save R0's value.
+	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
+	str	lr, [r0]			@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
+	ldr	lr, [r0]			@ restore lr
+	ldr	r0, [r13]			@ restore r0
+	add	r13, r13, #4			@ pop stack entry
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+#endif	/* CONFIG_SPL_BUILD */
+
+/*
+ * exception handlers
+ */
+#ifdef CONFIG_SPL_BUILD
+	.align	5
+do_hang:
+	bl	hang				/* hang and never return */
+#else	/* !CONFIG_SPL_BUILD */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack_swi
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+	.align 5
+.global arm1136_cache_flush
+arm1136_cache_flush:
+#if !defined(CONFIG_SYS_ICACHE_OFF)
+		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
+#endif
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+		mcr	p15, 0, r1, c7, c14, 0	@ invalidate D cache
+#endif
+		mov	pc, lr			@ back to caller
+#endif	/* CONFIG_SPL_BUILD */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1136/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/arm1136/u-boot-spl.lds
new file mode 100644
index 000000000..0299902f2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1136/u-boot-spl.lds
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+	__start = .;
+	  arch/arm/cpu/arm1136/start.o	(.text*)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm1176/Makefile
new file mode 100644
index 000000000..deec42744
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+obj-y	= cpu.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/Makefile
new file mode 100644
index 000000000..0ad36906d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/Makefile
@@ -0,0 +1,16 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+obj-y	:= lowlevel_init.o
+obj-y	+= init.o reset.o timer.o mbox.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/init.c b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/init.c
new file mode 100644
index 000000000..e90d3bba1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/init.c
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+
+int arch_cpu_init(void)
+{
+	icache_enable();
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S
new file mode 100644
index 000000000..c7b084328
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+	mov	pc, lr
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/mbox.c b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/mbox.c
new file mode 100644
index 000000000..3b17a31ea
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/mbox.c
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mbox.h>
+
+#define TIMEOUT 1000 /* ms */
+
+int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv)
+{
+	struct bcm2835_mbox_regs *regs =
+		(struct bcm2835_mbox_regs *)BCM2835_MBOX_PHYSADDR;
+	ulong endtime = get_timer(0) + TIMEOUT;
+	u32 val;
+
+	debug("time: %lu timeout: %lu\n", get_timer(0), endtime);
+
+	if (send & BCM2835_CHAN_MASK) {
+		printf("mbox: Illegal mbox data 0x%08x\n", send);
+		return -1;
+	}
+
+	/* Drain any stale responses */
+
+	for (;;) {
+		val = readl(&regs->status);
+		if (val & BCM2835_MBOX_STATUS_RD_EMPTY)
+			break;
+		if (get_timer(0) >= endtime) {
+			printf("mbox: Timeout draining stale responses\n");
+			return -1;
+		}
+		val = readl(&regs->read);
+	}
+
+	/* Wait for space to send */
+
+	for (;;) {
+		val = readl(&regs->status);
+		if (!(val & BCM2835_MBOX_STATUS_WR_FULL))
+			break;
+		if (get_timer(0) >= endtime) {
+			printf("mbox: Timeout waiting for send space\n");
+			return -1;
+		}
+	}
+
+	/* Send the request */
+
+	val = BCM2835_MBOX_PACK(chan, send);
+	debug("mbox: TX raw: 0x%08x\n", val);
+	writel(val, &regs->write);
+
+	/* Wait for the response */
+
+	for (;;) {
+		val = readl(&regs->status);
+		if (!(val & BCM2835_MBOX_STATUS_RD_EMPTY))
+			break;
+		if (get_timer(0) >= endtime) {
+			printf("mbox: Timeout waiting for response\n");
+			return -1;
+		}
+	}
+
+	/* Read the response */
+
+	val = readl(&regs->read);
+	debug("mbox: RX raw: 0x%08x\n", val);
+
+	/* Validate the response */
+
+	if (BCM2835_MBOX_UNPACK_CHAN(val) != chan) {
+		printf("mbox: Response channel mismatch\n");
+		return -1;
+	}
+
+	*recv = BCM2835_MBOX_UNPACK_DATA(val);
+
+	return 0;
+}
+
+#ifdef DEBUG
+void dump_buf(struct bcm2835_mbox_hdr *buffer)
+{
+	u32 *p;
+	u32 words;
+	int i;
+
+	p = (u32 *)buffer;
+	words = buffer->buf_size / 4;
+	for (i = 0; i < words; i++)
+		printf("    0x%04x: 0x%08x\n", i * 4, p[i]);
+}
+#endif
+
+int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
+{
+	int ret;
+	u32 rbuffer;
+	struct bcm2835_mbox_tag_hdr *tag;
+	int tag_index;
+
+#ifdef DEBUG
+	printf("mbox: TX buffer\n");
+	dump_buf(buffer);
+#endif
+
+	ret = bcm2835_mbox_call_raw(chan, (u32)buffer, &rbuffer);
+	if (ret)
+		return ret;
+	if (rbuffer != (u32)buffer) {
+		printf("mbox: Response buffer mismatch\n");
+		return -1;
+	}
+
+#ifdef DEBUG
+	printf("mbox: RX buffer\n");
+	dump_buf(buffer);
+#endif
+
+	/* Validate overall response status */
+
+	if (buffer->code != BCM2835_MBOX_RESP_CODE_SUCCESS) {
+		printf("mbox: Header response code invalid\n");
+		return -1;
+	}
+
+	/* Validate each tag's response status */
+
+	tag = (void *)(buffer + 1);
+	tag_index = 0;
+	while (tag->tag) {
+		if (!(tag->val_len & BCM2835_MBOX_TAG_VAL_LEN_RESPONSE)) {
+			printf("mbox: Tag %d missing val_len response bit\n",
+				tag_index);
+			return -1;
+		}
+		/*
+		 * Clear the reponse bit so clients can just look right at the
+		 * length field without extra processing
+		 */
+		tag->val_len &= ~BCM2835_MBOX_TAG_VAL_LEN_RESPONSE;
+		tag = (void *)(((u8 *)tag) + sizeof(*tag) + tag->val_buf_size);
+		tag_index++;
+	}
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/reset.c b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/reset.c
new file mode 100644
index 000000000..8c37ad9fd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/reset.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/wdog.h>
+
+#define RESET_TIMEOUT 10
+
+void reset_cpu(ulong addr)
+{
+	struct bcm2835_wdog_regs *regs =
+		(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
+	uint32_t rstc;
+
+	rstc = readl(&regs->rstc);
+	rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK;
+	rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET;
+
+	writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, &regs->wdog);
+	writel(BCM2835_WDOG_PASSWORD | rstc, &regs->rstc);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/timer.c
new file mode 100644
index 000000000..017907cfb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/bcm2835/timer.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+ulong get_timer_us(ulong base)
+{
+	struct bcm2835_timer_regs *regs =
+		(struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR;
+
+	return readl(&regs->clo) - base;
+}
+
+ulong get_timer(ulong base)
+{
+	ulong us = get_timer_us(0);
+	us /= (1000000 / CONFIG_SYS_HZ);
+	us -= base;
+	return us;
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong endtime;
+	signed long diff;
+
+	endtime = get_timer_us(0) + usec;
+
+	do {
+		ulong now = get_timer_us(0);
+		diff = endtime - now;
+	} while (diff >= 0);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/config.mk b/qemu/roms/u-boot/arch/arm/cpu/arm1176/config.mk
new file mode 100644
index 000000000..5dc2ebb27
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# Make ARMv5 to allow more compilers to work, even though its v6.
+PLATFORM_CPPFLAGS += -march=armv5t
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm1176/cpu.c
new file mode 100644
index 000000000..2d8165121
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/cpu.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush (void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+	/* flush I/D-cache */
+	cache_flush();
+
+	return 0;
+}
+
+/* flush I/D-cache */
+static void cache_flush (void)
+{
+	/* invalidate both caches and flush btb */
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
+	/* mem barrier to sync things */
+	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm1176/start.S
new file mode 100644
index 000000000..ce620115d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/start.S
@@ -0,0 +1,331 @@
+/*
+ *  armboot - Startup Code for ARM1176 CPU-core
+ *
+ * Copyright (c) 2007	Samsung Electronics
+ *
+ * Copyright (C) 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
+ * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
+ * jsgood (jsgood.yang@samsung.com)
+ * Base codes by scsuh (sc.suh)
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+
+#ifndef CONFIG_SYS_PHY_UBOOT_BASE
+#define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
+#endif
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+.globl _start
+_start: b	reset
+#ifndef CONFIG_SPL_BUILD
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+	.word undefined_instruction
+_software_interrupt:
+	.word software_interrupt
+_prefetch_abort:
+	.word prefetch_abort
+_data_abort:
+	.word data_abort
+_not_used:
+	.word not_used
+_irq:
+	.word irq
+_fiq:
+	.word fiq
+_pad:
+	.word 0x12345678 /* now 16*4=64 */
+#else
+	. = _start + 64
+#endif
+
+.global _end_vect
+_end_vect:
+	.balignl 16,0xdeadbeef
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0, cpsr
+	bic	r0, r0, #0x3f
+	orr	r0, r0, #0xd3
+	msr	cpsr, r0
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+cpu_init_crit:
+	/*
+	 * When booting from NAND - it has definitely been a reset, so, no need
+	 * to flush caches and disable the MMU
+	 */
+#ifndef CONFIG_SPL_BUILD
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+
+	/* Prepare to disable the MMU */
+	adr	r2, mmu_disable_phys
+	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
+	b	mmu_disable
+
+	.align 5
+	/* Run in a single cache-line */
+mmu_disable:
+	mcr	p15, 0, r0, c1, c0, 0
+	nop
+	nop
+	mov	pc, r2
+mmu_disable_phys:
+
+#ifdef CONFIG_DISABLE_TCM
+	/*
+	 * Disable the TCMs
+	 */
+	mrc	p15, 0, r0, c0, c0, 2	/* Return TCM details */
+	cmp	r0, #0
+	beq	skip_tcmdisable
+	mov	r1, #0
+	mov	r2, #1
+	tst	r0, r2
+	mcrne	p15, 0, r1, c9, c1, 1	/* Disable Instruction TCM if present*/
+	tst	r0, r2, LSL #16
+	mcrne	p15, 0, r1, c9, c1, 0	/* Disable Data TCM if present*/
+skip_tcmdisable:
+#endif
+#endif
+
+#ifdef CONFIG_PERIPORT_REMAP
+	/* Peri port setup */
+	ldr	r0, =CONFIG_PERIPORT_BASE
+	orr	r0, r0, #CONFIG_PERIPORT_SIZE
+	mcr	p15,0,r0,c15,c2,4
+#endif
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	bl	lowlevel_init		/* go setup pll,mux,memory */
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+	mov	pc, lr
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ */
+
+	.macro	bad_save_user_regs
+	/* carve out a frame on current user stack */
+	sub	sp, sp, #S_FRAME_SIZE
+	/* Save user registers (now in svc mode) r0-r12 */
+	stmia	sp, {r0 - r12}
+
+	ldr	r2, IRQ_STACK_START_IN
+	/* get values for "aborted" pc and cpsr (into parm regs) */
+	ldmia	r2, {r2 - r3}
+	/* grab pointer to old stack */
+	add	r0, sp, #S_FRAME_SIZE
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	/* save sp_SVC, lr_SVC, pc, cpsr */
+	stmia	r5, {r0 - r3}
+	/* save current stack into r0 (param register) */
+	mov	r0, sp
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+
+	/* save caller lr in position 0 of saved stack */
+	str	lr, [r13]
+	/* get the spsr */
+	mrs	lr, spsr
+	/* save spsr in position 1 of saved stack */
+	str	lr, [r13, #4]
+
+	/* prepare SVC-Mode */
+	mov	r13, #MODE_SVC
+	@ msr	spsr_c, r13
+	/* switch modes, make sure moves will execute */
+	msr	spsr, r13
+	/* capture return pc */
+	mov	lr, pc
+	/* jump to next instruction & switch modes. */
+	movs	pc, lr
+	.endm
+
+	.macro get_bad_stack_swi
+	/* space on current stack for scratch reg. */
+	sub	r13, r13, #4
+	/* save R0's value. */
+	str	r0, [r13]
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+	/* save caller lr in position 0 of saved stack */
+	str	lr, [r0]
+	/* get the spsr */
+	mrs	lr, spsr
+	/* save spsr in position 1 of saved stack */
+	str	lr, [r0, #4]
+	/* restore lr */
+	ldr	lr, [r0]
+	/* restore r0 */
+	ldr	r0, [r13]
+	/* pop stack entry */
+	add	r13, r13, #4
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack_swi
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+#endif /* CONFIG_SPL_BUILD */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/Makefile
new file mode 100644
index 000000000..a4c1edfc7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/Makefile
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= aemif.o clock.o init.o mux.o timer.o
+obj-y	+= lowlevel_init.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/aemif.c
new file mode 100644
index 000000000..a0f57289e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/aemif.c
@@ -0,0 +1,78 @@
+/*
+ * TNETV107X: Asynchronous EMIF Configuration
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+
+#define ASYNC_EMIF_BASE			TNETV107X_ASYNC_EMIF_CNTRL_BASE
+#define ASYNC_EMIF_CONFIG(cs)		(ASYNC_EMIF_BASE+0x10+(cs)*4)
+#define ASYNC_EMIF_ONENAND_CONTROL	(ASYNC_EMIF_BASE+0x5c)
+#define ASYNC_EMIF_NAND_CONTROL		(ASYNC_EMIF_BASE+0x60)
+#define ASYNC_EMIF_WAITCYCLE_CONFIG	(ASYNC_EMIF_BASE+0x4)
+
+#define CONFIG_SELECT_STROBE(v)		((v) ? 1 << 31 : 0)
+#define CONFIG_EXTEND_WAIT(v)		((v) ? 1 << 30 : 0)
+#define CONFIG_WR_SETUP(v)		(((v) & 0x0f) << 26)
+#define CONFIG_WR_STROBE(v)		(((v) & 0x3f) << 20)
+#define CONFIG_WR_HOLD(v)		(((v) & 0x07) << 17)
+#define CONFIG_RD_SETUP(v)		(((v) & 0x0f) << 13)
+#define CONFIG_RD_STROBE(v)		(((v) & 0x3f) << 7)
+#define CONFIG_RD_HOLD(v)		(((v) & 0x07) << 4)
+#define CONFIG_TURN_AROUND(v)		(((v) & 0x03) << 2)
+#define CONFIG_WIDTH(v)			(((v) & 0x03) << 0)
+
+#define NUM_CS				4
+
+#define set_config_field(reg, field, val)			\
+	do {							\
+		if (val != -1) {				\
+			reg &= ~CONFIG_##field(0xffffffff);	\
+			reg |=	CONFIG_##field(val);		\
+		}						\
+	} while (0)
+
+void configure_async_emif(int cs, struct async_emif_config *cfg)
+{
+	unsigned long tmp;
+
+	if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
+		tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
+		tmp |= (1 << cs);
+		__raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
+
+	} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
+		tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
+		tmp |= (1 << cs);
+		__raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
+	}
+
+	tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
+
+	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
+	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
+	set_config_field(tmp, WR_SETUP,		cfg->wr_setup);
+	set_config_field(tmp, WR_STROBE,	cfg->wr_strobe);
+	set_config_field(tmp, WR_HOLD,		cfg->wr_hold);
+	set_config_field(tmp, RD_SETUP,		cfg->rd_setup);
+	set_config_field(tmp, RD_STROBE,	cfg->rd_strobe);
+	set_config_field(tmp, RD_HOLD,		cfg->rd_hold);
+	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
+	set_config_field(tmp, WIDTH,		cfg->width);
+
+	__raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
+}
+
+void init_async_emif(int num_cs, struct async_emif_config *config)
+{
+	int cs;
+
+	clk_enable(TNETV107X_LPSC_AEMIF);
+
+	for (cs = 0; cs < num_cs; cs++)
+		configure_async_emif(cs, config + cs);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/clock.c b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/clock.c
new file mode 100644
index 000000000..3708b6f59
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/clock.c
@@ -0,0 +1,432 @@
+/*
+ * TNETV107X: Clock management APIs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+
+#define CLOCK_BASE		TNETV107X_CLOCK_CONTROL_BASE
+#define PSC_BASE		TNETV107X_PSC_BASE
+
+#define BIT(x)			(1 << (x))
+
+#define MAX_PREDIV		64
+#define MAX_POSTDIV		8
+#define MAX_MULT		512
+#define MAX_DIV			(MAX_PREDIV * MAX_POSTDIV)
+
+/* LPSC registers */
+#define PSC_PTCMD		0x120
+#define PSC_PTSTAT		0x128
+#define PSC_MDSTAT(n)		(0x800 + (n) * 4)
+#define PSC_MDCTL(n)		(0xA00 + (n) * 4)
+
+#define PSC_MDCTL_LRSTZ		BIT(8)
+
+#define psc_reg_read(reg)	__raw_readl((u32 *)(PSC_BASE + (reg)))
+#define psc_reg_write(reg, val)	__raw_writel(val, (u32 *)(PSC_BASE + (reg)))
+
+/* SSPLL registers */
+struct sspll_regs {
+	u32	modes;
+	u32	postdiv;
+	u32	prediv;
+	u32	mult_factor;
+	u32	divider_range;
+	u32	bw_divider;
+	u32	spr_amount;
+	u32	spr_rate_div;
+	u32	diag;
+};
+
+/* SSPLL base addresses */
+static struct sspll_regs *sspll_regs[] = {
+	(struct sspll_regs *)(CLOCK_BASE + 0x040),
+	(struct sspll_regs *)(CLOCK_BASE + 0x080),
+	(struct sspll_regs *)(CLOCK_BASE + 0x0c0),
+};
+
+#define sspll_reg(pll, reg)		(&(sspll_regs[pll]->reg))
+#define sspll_reg_read(pll, reg)	__raw_readl(sspll_reg(pll, reg))
+#define sspll_reg_write(pll, reg, val)	__raw_writel(val, sspll_reg(pll, reg))
+
+
+/* PLL Control Registers */
+struct pllctl_regs {
+	u32	ctl;		/* 00 */
+	u32	ocsel;		/* 04 */
+	u32	secctl;		/* 08 */
+	u32	__pad0;
+	u32	mult;		/* 10 */
+	u32	prediv;		/* 14 */
+	u32	div1;		/* 18 */
+	u32	div2;		/* 1c */
+	u32	div3;		/* 20 */
+	u32	oscdiv1;	/* 24 */
+	u32	postdiv;	/* 28 */
+	u32	bpdiv;		/* 2c */
+	u32	wakeup;		/* 30 */
+	u32	__pad1;
+	u32	cmd;		/* 38 */
+	u32	stat;		/* 3c */
+	u32	alnctl;		/* 40 */
+	u32	dchange;	/* 44 */
+	u32	cken;		/* 48 */
+	u32	ckstat;		/* 4c */
+	u32	systat;		/* 50 */
+	u32	ckctl;		/* 54 */
+	u32	__pad2[2];
+	u32	div4;		/* 60 */
+	u32	div5;		/* 64 */
+	u32	div6;		/* 68 */
+	u32	div7;		/* 6c */
+	u32	div8;		/* 70 */
+};
+
+struct lpsc_map {
+	int	pll, div;
+};
+
+static struct pllctl_regs *pllctl_regs[] = {
+	(struct pllctl_regs *)(CLOCK_BASE + 0x700),
+	(struct pllctl_regs *)(CLOCK_BASE + 0x300),
+	(struct pllctl_regs *)(CLOCK_BASE + 0x500),
+};
+
+#define pllctl_reg(pll, reg)		(&(pllctl_regs[pll]->reg))
+#define pllctl_reg_read(pll, reg)	__raw_readl(pllctl_reg(pll, reg))
+#define pllctl_reg_write(pll, reg, val)	__raw_writel(val, pllctl_reg(pll, reg))
+
+#define pllctl_reg_rmw(pll, reg, mask, val)			\
+	pllctl_reg_write(pll, reg,				\
+		(pllctl_reg_read(pll, reg) & ~(mask)) | val)
+
+#define pllctl_reg_setbits(pll, reg, mask)			\
+	pllctl_reg_rmw(pll, reg, 0, mask)
+
+#define pllctl_reg_clrbits(pll, reg, mask)			\
+	pllctl_reg_rmw(pll, reg, mask, 0)
+
+/* PLLCTL Bits */
+#define PLLCTL_CLKMODE		BIT(8)
+#define PLLCTL_PLLSELB		BIT(7)
+#define PLLCTL_PLLENSRC		BIT(5)
+#define PLLCTL_PLLDIS		BIT(4)
+#define PLLCTL_PLLRST		BIT(3)
+#define PLLCTL_PLLPWRDN		BIT(1)
+#define PLLCTL_PLLEN		BIT(0)
+
+#define PLLDIV_ENABLE		BIT(15)
+
+static int pll_div_offset[] = {
+#define div_offset(reg)	offsetof(struct pllctl_regs, reg)
+	div_offset(div1), div_offset(div2), div_offset(div3),
+	div_offset(div4), div_offset(div5), div_offset(div6),
+	div_offset(div7), div_offset(div8),
+};
+
+static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
+static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
+
+/* Mappings from PLL+DIV to subsystem clocks */
+#define sys_arm1176_clk		{SYS_PLL, 0}
+#define sys_dsp_clk		{SYS_PLL, 1}
+#define sys_ddr_clk		{SYS_PLL, 2}
+#define sys_full_clk		{SYS_PLL, 3}
+#define sys_lcd_clk		{SYS_PLL, 4}
+#define sys_vlynq_ref_clk	{SYS_PLL, 5}
+#define sys_tsc_clk		{SYS_PLL, 6}
+#define sys_half_clk		{SYS_PLL, 7}
+
+#define eth_clk_5		{ETH_PLL, 0}
+#define eth_clk_50		{ETH_PLL, 1}
+#define eth_clk_125		{ETH_PLL, 2}
+#define eth_clk_250		{ETH_PLL, 3}
+#define eth_clk_25		{ETH_PLL, 4}
+
+#define tdm_clk			{TDM_PLL, 0}
+#define tdm_extra_clk		{TDM_PLL, 1}
+#define tdm1_clk		{TDM_PLL, 2}
+
+static const struct lpsc_map lpsc_clk_map[] = {
+	[TNETV107X_LPSC_ARM]			= sys_arm1176_clk,
+	[TNETV107X_LPSC_GEM]			= sys_dsp_clk,
+	[TNETV107X_LPSC_DDR2_PHY]		= sys_ddr_clk,
+	[TNETV107X_LPSC_TPCC]			= sys_full_clk,
+	[TNETV107X_LPSC_TPTC0]			= sys_full_clk,
+	[TNETV107X_LPSC_TPTC1]			= sys_full_clk,
+	[TNETV107X_LPSC_RAM]			= sys_full_clk,
+	[TNETV107X_LPSC_MBX_LITE]		= sys_arm1176_clk,
+	[TNETV107X_LPSC_LCD]			= sys_lcd_clk,
+	[TNETV107X_LPSC_ETHSS]			= eth_clk_125,
+	[TNETV107X_LPSC_AEMIF]			= sys_full_clk,
+	[TNETV107X_LPSC_CHIP_CFG]		= sys_half_clk,
+	[TNETV107X_LPSC_TSC]			= sys_tsc_clk,
+	[TNETV107X_LPSC_ROM]			= sys_half_clk,
+	[TNETV107X_LPSC_UART2]			= sys_half_clk,
+	[TNETV107X_LPSC_PKTSEC]			= sys_half_clk,
+	[TNETV107X_LPSC_SECCTL]			= sys_half_clk,
+	[TNETV107X_LPSC_KEYMGR]			= sys_half_clk,
+	[TNETV107X_LPSC_KEYPAD]			= sys_half_clk,
+	[TNETV107X_LPSC_GPIO]			= sys_half_clk,
+	[TNETV107X_LPSC_MDIO]			= sys_half_clk,
+	[TNETV107X_LPSC_SDIO0]			= sys_half_clk,
+	[TNETV107X_LPSC_UART0]			= sys_half_clk,
+	[TNETV107X_LPSC_UART1]			= sys_half_clk,
+	[TNETV107X_LPSC_TIMER0]			= sys_half_clk,
+	[TNETV107X_LPSC_TIMER1]			= sys_half_clk,
+	[TNETV107X_LPSC_WDT_ARM]		= sys_half_clk,
+	[TNETV107X_LPSC_WDT_DSP]		= sys_half_clk,
+	[TNETV107X_LPSC_SSP]			= sys_half_clk,
+	[TNETV107X_LPSC_TDM0]			= tdm_clk,
+	[TNETV107X_LPSC_VLYNQ]			= sys_vlynq_ref_clk,
+	[TNETV107X_LPSC_MCDMA]			= sys_half_clk,
+	[TNETV107X_LPSC_USB0]			= sys_half_clk,
+	[TNETV107X_LPSC_TDM1]			= tdm1_clk,
+	[TNETV107X_LPSC_DEBUGSS]		= sys_half_clk,
+	[TNETV107X_LPSC_ETHSS_RGMII]		= eth_clk_250,
+	[TNETV107X_LPSC_SYSTEM]			= sys_half_clk,
+	[TNETV107X_LPSC_IMCOP]			= sys_dsp_clk,
+	[TNETV107X_LPSC_SPARE]			= sys_half_clk,
+	[TNETV107X_LPSC_SDIO1]			= sys_half_clk,
+	[TNETV107X_LPSC_USB1]			= sys_half_clk,
+	[TNETV107X_LPSC_USBSS]			= sys_half_clk,
+	[TNETV107X_LPSC_DDR2_EMIF1_VRST]	= sys_ddr_clk,
+	[TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST]	= sys_ddr_clk,
+};
+
+static const unsigned long pll_ext_freq[] = {
+	[SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
+	[ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
+	[TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
+};
+
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, postdiv = 1;
+	unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
+	unsigned long ret;
+	u32 bypass;
+
+	bypass = __raw_readl((u32 *)(CLOCK_BASE));
+	if (!(bypass & pll_bypass_mask[pll])) {
+		mult	= sspll_reg_read(pll, mult_factor);
+		prediv	= sspll_reg_read(pll, prediv) + 1;
+		postdiv	= sspll_reg_read(pll, postdiv) + 1;
+	}
+
+	if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
+		ref = pll_ext_freq[pll];
+
+	if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
+		return ref;
+
+	ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
+	ret /= (prediv * postdiv);
+
+	return ret;
+}
+
+static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
+					int div)
+{
+	int divider = 1;
+	unsigned long divreg;
+
+	divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
+
+	if (divreg & PLLDIV_ENABLE)
+		divider = (divreg & pll_div_mask[pll]) + 1;
+
+	return fpll / divider;
+}
+
+static unsigned long pll_div_freq_get(int pll, int div)
+{
+	unsigned int fpll = pll_freq_get(pll);
+
+	return __pll_div_freq_get(pll, fpll, div);
+}
+
+static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
+			       unsigned long hz)
+{
+	int divider = (fpll / hz - 1);
+
+	divider &= pll_div_mask[pll];
+	divider |= PLLDIV_ENABLE;
+
+	__raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
+	pllctl_reg_setbits(pll, alnctl, (1 << div));
+	pllctl_reg_setbits(pll, dchange, (1 << div));
+}
+
+static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
+{
+	unsigned int fpll = pll_freq_get(pll);
+
+	__pll_div_freq_set(pll, fpll, div, hz);
+
+	pllctl_reg_write(pll, cmd, 1);
+
+	/* Wait until new divider takes effect */
+	while (pllctl_reg_read(pll, stat) & 0x01);
+
+	return __pll_div_freq_get(pll, fpll, div);
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
+}
+
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
+{
+	unsigned long fpll, divider, pll;
+
+	pll = lpsc_clk_map[clk].pll;
+	fpll = pll_freq_get(pll);
+	divider = (fpll / hz - 1);
+	divider &= pll_div_mask[pll];
+
+	return fpll / (divider + 1);
+}
+
+int clk_set_rate(unsigned int clk, unsigned long _hz)
+{
+	unsigned long hz;
+
+	hz = clk_round_rate(clk, _hz);
+	if (hz != _hz)
+		return -EINVAL;	/* Cannot set to target freq */
+
+	pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
+	return 0;
+}
+
+void lpsc_control(int mod, unsigned long state, int lrstz)
+{
+	u32 mdctl;
+
+	mdctl = psc_reg_read(PSC_MDCTL(mod));
+	mdctl &= ~0x1f;
+	mdctl |= state;
+
+	if (lrstz == 0)
+		mdctl &= ~PSC_MDCTL_LRSTZ;
+	else if (lrstz == 1)
+		mdctl |= PSC_MDCTL_LRSTZ;
+
+	psc_reg_write(PSC_MDCTL(mod), mdctl);
+
+	psc_reg_write(PSC_PTCMD, 1);
+
+	/* wait for power domain transition to end */
+	while (psc_reg_read(PSC_PTSTAT) & 1);
+
+	/* Wait for module state change */
+	while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
+}
+
+int lpsc_status(unsigned int id)
+{
+	return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
+}
+
+static void init_pll(const struct pll_init_data *data)
+{
+	unsigned long fpll;
+	unsigned long best_pre = 0, best_post = 0, best_mult = 0;
+	unsigned long div, prediv, postdiv, mult;
+	unsigned long delta, actual;
+	long best_delta = -1;
+	int i;
+	u32 tmp;
+
+	if (data->pll == SYS_PLL)
+		return; /* cannot reconfigure system pll on the fly */
+
+	tmp = pllctl_reg_read(data->pll, ctl);
+	if (data->internal_osc) {
+		tmp &= ~PLLCTL_CLKMODE;
+		fpll = CONFIG_SYS_INT_OSC_FREQ;
+	} else {
+		tmp |= PLLCTL_CLKMODE;
+		fpll = pll_ext_freq[data->pll];
+	}
+	pllctl_reg_write(data->pll, ctl, tmp);
+
+	mult = data->pll_freq / fpll;
+	for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
+		div = (fpll * mult) / data->pll_freq;
+		if (div < 1 || div > MAX_DIV)
+			continue;
+
+		for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
+			prediv = div / postdiv;
+			if (prediv < 1 || prediv > MAX_PREDIV)
+				continue;
+
+			actual = (fpll / prediv) * (mult / postdiv);
+			delta = (actual - data->pll_freq);
+			if (delta < 0)
+				delta = -delta;
+			if ((delta < best_delta) || (best_delta == -1)) {
+				best_delta = delta;
+				best_mult = mult;
+				best_pre = prediv;
+				best_post = postdiv;
+				if (delta == 0)
+					goto done;
+			}
+		}
+	}
+done:
+
+	if (best_delta == -1) {
+		printf("pll cannot derive %lu from %lu\n",
+				data->pll_freq, fpll);
+		return;
+	}
+
+	fpll = fpll * best_mult;
+	fpll /= best_pre * best_post;
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
+
+	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
+
+	sspll_reg_write(data->pll, mult_factor,	(best_mult - 1) << 8);
+	sspll_reg_write(data->pll, prediv,	best_pre - 1);
+	sspll_reg_write(data->pll, postdiv,	best_post - 1);
+
+	for (i = 0; i < 10; i++)
+		if (data->div_freq[i])
+			__pll_div_freq_set(data->pll, fpll, i,
+					   data->div_freq[i]);
+
+	pllctl_reg_write(data->pll, cmd, 1);
+
+	/* Wait until pll "go" operation completes */
+	while (pllctl_reg_read(data->pll, stat) & 0x01);
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
+	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+}
+
+void init_plls(int num_pll, struct pll_init_data *config)
+{
+	int i;
+
+	for (i = 0; i < num_pll; i++)
+		init_pll(&config[i]);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/init.c b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/init.c
new file mode 100644
index 000000000..d8708267d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/init.c
@@ -0,0 +1,22 @@
+/*
+ * TNETV107X: Architecture initialization
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void chip_configuration_unlock(void)
+{
+       __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
+       __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
+}
+
+int arch_cpu_init(void)
+{
+       icache_enable();
+       chip_configuration_unlock();
+
+       return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
new file mode 100644
index 000000000..a8bce4784
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
@@ -0,0 +1,10 @@
+/*
+ * TNETV107X: Low-level pre-relocation initialization
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+	/* nothing for now, maybe needed for more exotic boot modes */
+	mov	pc, lr
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/mux.c b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/mux.c
new file mode 100644
index 000000000..310d84dfb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/mux.c
@@ -0,0 +1,319 @@
+/*
+ * TNETV107X: Pinmux configuration
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+
+#define MUX_MODE_1		0x00
+#define MUX_MODE_2		0x04
+#define MUX_MODE_3		0x0c
+#define MUX_MODE_4		0x1c
+
+#define MUX_DEBUG		0
+
+static const struct pin_config pin_table[] = {
+	/*		  reg	shift	mode	*/
+	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(11,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(11,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(15,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(19,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(20,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(26,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_2),
+};
+
+const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
+
+int mux_select_pin(short index)
+{
+	const struct pin_config *cfg;
+	unsigned long mask, mode, reg;
+
+	if (index >= pin_table_size)
+		return 0;
+
+	cfg = &pin_table[index];
+
+	mask = 0x1f << cfg->mask_offset;
+	mode = cfg->mode << cfg->mask_offset;
+
+	reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
+	reg = (reg & ~mask) | mode;
+	__raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
+
+	return 1;
+}
+
+int mux_select_pins(const short *pins)
+{
+	int i, ret = 1;
+
+	for (i = 0; pins[i] >= 0; i++)
+		ret &= mux_select_pin(pins[i]);
+
+	return ret;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/timer.c
new file mode 100644
index 000000000..6e0dd0d2b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm1176/tnetv107x/timer.c
@@ -0,0 +1,93 @@
+/*
+ * TNETV107X: Timer implementation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+struct timer_regs {
+	u_int32_t pid12;
+	u_int32_t pad[3];
+	u_int32_t tim12;
+	u_int32_t tim34;
+	u_int32_t prd12;
+	u_int32_t prd34;
+	u_int32_t tcr;
+	u_int32_t tgcr;
+	u_int32_t wdtcr;
+};
+
+#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
+
+#define TIMER_LOAD_VAL	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define TIM_CLK_DIV	16
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init(void)
+{
+	clk_enable(TNETV107X_LPSC_TIMER0);
+
+	lastinc = timestamp = 0;
+
+	/* We are using timer34 in unchained 32-bit mode, full speed */
+	__raw_writel(0x0, &regs->tcr);
+	__raw_writel(0x0, &regs->tgcr);
+	__raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
+	__raw_writel(0x0, &regs->tim34);
+	__raw_writel(TIMER_LOAD_VAL, &regs->prd34);
+	__raw_writel(2 << 22, &regs->tcr);
+
+	return 0;
+}
+
+static ulong get_timer_raw(void)
+{
+	ulong now = __raw_readl(&regs->tim34);
+
+	if (now >= lastinc)
+		timestamp += now - lastinc;
+	else
+		timestamp += now + TIMER_LOAD_VAL - lastinc;
+
+	lastinc = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+	tmo *= usec;
+	tmo /= (1000 * TIM_CLK_DIV);
+
+	endtime = get_timer_raw() + tmo;
+
+	do {
+		ulong now = get_timer_raw();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm720t/Makefile
new file mode 100644
index 000000000..6badb3bb8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+obj-y	= interrupts.o cpu.o
+
+obj-$(CONFIG_TEGRA) += tegra-common/
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/config.mk b/qemu/roms/u-boot/arch/arm/cpu/arm720t/config.mk
new file mode 100644
index 000000000..772fb413e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm720t/cpu.c
new file mode 100644
index 000000000..745fccdfb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/cpu.c
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * cleanup_before_linux() - Prepare the CPU to jump to Linux
+ *
+ * This function is called just before we call Linux, it
+ * prepares the processor for linux
+ */
+int cleanup_before_linux(void)
+{
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/interrupts.c b/qemu/roms/u-boot/arch/arm/cpu/arm720t/interrupts.c
new file mode 100644
index 000000000..e8ba1ae09
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/interrupts.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_USE_IRQ
+void do_irq (struct pt_regs *pt_regs)
+{
+}
+#endif
+
+#if defined(CONFIG_TEGRA)
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init (void)
+{
+	/* No timer routines for tegra as yet */
+	lastdec = 0;
+	timestamp = 0;
+
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm720t/start.S
new file mode 100644
index 000000000..1a3484269
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/start.S
@@ -0,0 +1,307 @@
+/*
+ *  armboot - Startup Code for ARM720 CPU-core
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/hardware.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start: b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+#ifdef CONFIG_SPL_BUILD
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt:	.word _software_interrupt
+_prefetch_abort:	.word _prefetch_abort
+_data_abort:		.word _data_abort
+_not_used:		.word _not_used
+_irq:			.word _irq
+_fiq:			.word _fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#else
+_undefined_instruction: .word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_SPL_BUILD */
+
+	.balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from RAM!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+	mov	pc, lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+
+	mov	ip, lr
+	/*
+	 * before relocating, we have to setup RAM timing
+	 * because memory timing is board-dependent, you will
+	 * find a lowlevel_init.S in your board directory.
+	 */
+	bl	lowlevel_init
+	mov	lr, ip
+
+	mov	pc, lr
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC
+
+	ldr	r2, IRQ_STACK_START_IN
+	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
+	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
+	mov	r0, sp
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+
+	str	lr, [r13]			@ save caller lr / spsr
+	mrs	lr, spsr
+	str	lr, [r13, #4]
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	msr	spsr_c, r13
+	mov	lr, pc
+	movs	pc, lr
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+#endif /* CONFIG_SPL_BUILD */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/Makefile
new file mode 100644
index 000000000..a9c2b675a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-y	+= cpu.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/cpu.c
new file mode 100644
index 000000000..168f525ec
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include "cpu.h"
+
+int get_num_cpus(void)
+{
+	struct apb_misc_gp_ctlr *gp;
+	uint rev;
+
+	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
+
+	switch (rev) {
+	case CHIPID_TEGRA20:
+		return 2;
+		break;
+	case CHIPID_TEGRA30:
+	case CHIPID_TEGRA114:
+	default:
+		return 4;
+		break;
+	}
+}
+
+/*
+ * Timing tables for each SOC for all four oscillator options.
+ */
+struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
+	/*
+	 * T20: 1 GHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      22:20    3
+	 * PLLX_BASE  n      17: 8   10
+	 * PLLX_BASE  m       4: 0    5
+	 * PLLX_MISC  cpcon  11: 8    4
+	 */
+	{
+		{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+		{ .n =  625, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
+		{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+		{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+	},
+	/*
+	 * T25: 1.2 GHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      22:20    3
+	 * PLLX_BASE  n      17: 8   10
+	 * PLLX_BASE  m       4: 0    5
+	 * PLLX_MISC  cpcon  11: 8    4
+	 */
+	{
+		{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+		{ .n = 750, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
+		{ .n = 600, .m =  6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+		{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+	},
+	/*
+	 * T30: 1.4 GHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      22:20    3
+	 * PLLX_BASE  n      17: 8   10
+	 * PLLX_BASE  m       4: 0    5
+	 * PLLX_MISC  cpcon  11: 8    4
+	 */
+	{
+		{ .n = 862, .m =  8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
+		{ .n = 583, .m =  8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
+		{ .n = 700, .m =  6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
+		{ .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
+	},
+	/*
+	 * T114: 700 MHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      23:20    4
+	 * PLLX_BASE  n      15: 8    8
+	 * PLLX_BASE  m       7: 0    8
+	 */
+	{
+		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
+	},
+
+	/*
+	 * T124: 700 MHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      23:20    4
+	 * PLLX_BASE  n      15: 8    8
+	 * PLLX_BASE  m       7: 0    8
+	 */
+	{
+		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
+	},
+};
+
+static inline void pllx_set_iddq(void)
+{
+#if defined(CONFIG_TEGRA124)
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	/* Disable IDDQ */
+	reg = readl(&clkrst->crc_pllx_misc3);
+	reg &= ~PLLX_IDDQ_MASK;
+	writel(reg, &clkrst->crc_pllx_misc3);
+	udelay(2);
+	debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
+	      readl(&clkrst->crc_pllx_misc3));
+#endif
+}
+
+int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
+		u32 divp, u32 cpcon)
+{
+	int chip = tegra_get_chip();
+	u32 reg;
+
+	/* If PLLX is already enabled, just return */
+	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
+		debug("pllx_set_rate: PLLX already enabled, returning\n");
+		return 0;
+	}
+
+	debug(" pllx_set_rate entry\n");
+
+	pllx_set_iddq();
+
+	/* Set BYPASS, m, n and p to PLLX_BASE */
+	reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
+	reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
+	writel(reg, &pll->pll_base);
+
+	/* Set cpcon to PLLX_MISC */
+	if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
+		reg = (cpcon << PLL_CPCON_SHIFT);
+	else
+		reg = 0;
+
+	/* Set dccon to PLLX_MISC if freq > 600MHz */
+	if (divn > 600)
+		reg |= (1 << PLL_DCCON_SHIFT);
+	writel(reg, &pll->pll_misc);
+
+	/* Disable BYPASS */
+	reg = readl(&pll->pll_base);
+	reg &= ~PLL_BYPASS_MASK;
+	writel(reg, &pll->pll_base);
+	debug("pllx_set_rate: base = 0x%08X\n", reg);
+
+	/* Set lock_enable to PLLX_MISC */
+	reg = readl(&pll->pll_misc);
+	reg |= PLL_LOCK_ENABLE_MASK;
+	writel(reg, &pll->pll_misc);
+	debug("pllx_set_rate: misc = 0x%08X\n", reg);
+
+	/* Enable PLLX last, once it's all configured */
+	reg = readl(&pll->pll_base);
+	reg |= PLL_ENABLE_MASK;
+	writel(reg, &pll->pll_base);
+	debug("pllx_set_rate: base final = 0x%08X\n", reg);
+
+	return 0;
+}
+
+void init_pllx(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
+	int soc_type, sku_info, chip_sku;
+	enum clock_osc_freq osc;
+	struct clk_pll_table *sel;
+
+	debug("init_pllx entry\n");
+
+	/* get SOC (chip) type */
+	soc_type = tegra_get_chip();
+	debug(" init_pllx: SoC = 0x%02X\n", soc_type);
+
+	/* get SKU info */
+	sku_info = tegra_get_sku_info();
+	debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
+
+	/* get chip SKU, combo of the above info */
+	chip_sku = tegra_get_chip_sku();
+	debug(" init_pllx: Chip SKU = %d\n", chip_sku);
+
+	/* get osc freq */
+	osc = clock_get_osc_freq();
+	debug(" init_pllx: osc = %d\n", osc);
+
+	/* set pllx */
+	sel = &tegra_pll_x_table[chip_sku][osc];
+	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
+}
+
+void enable_cpu_clock(int enable)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 clk;
+
+	/*
+	 * NOTE:
+	 * Regardless of whether the request is to enable or disable the CPU
+	 * clock, every processor in the CPU complex except the master (CPU 0)
+	 * will have it's clock stopped because the AVP only talks to the
+	 * master.
+	 */
+
+	if (enable) {
+		/* Initialize PLLX */
+		init_pllx();
+
+		/* Wait until all clocks are stable */
+		udelay(PLL_STABILIZATION_DELAY);
+
+		writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+		writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+	}
+
+	/*
+	 * Read the register containing the individual CPU clock enables and
+	 * always stop the clocks to CPUs > 0.
+	 */
+	clk = readl(&clkrst->crc_clk_cpu_cmplx);
+	clk |= 1 << CPU1_CLK_STP_SHIFT;
+	if (get_num_cpus() == 4)
+		clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
+
+	/* Stop/Unstop the CPU clock */
+	clk &= ~CPU0_CLK_STP_MASK;
+	clk |= !enable << CPU0_CLK_STP_SHIFT;
+	writel(clk, &clkrst->crc_clk_cpu_cmplx);
+
+	clock_enable(PERIPH_ID_CPU);
+}
+
+static int is_cpu_powered(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
+}
+
+static void remove_cpu_io_clamps(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Remove the clamps on the CPU I/O signals */
+	reg = readl(&pmc->pmc_remove_clamping);
+	reg |= CPU_CLMP;
+	writel(reg, &pmc->pmc_remove_clamping);
+
+	/* Give I/O signals time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+}
+
+void powerup_cpu(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+	int timeout = IO_STABILIZATION_DELAY;
+
+	if (!is_cpu_powered()) {
+		/* Toggle the CPU power state (OFF -> ON) */
+		reg = readl(&pmc->pmc_pwrgate_toggle);
+		reg &= PARTID_CP;
+		reg |= START_CP;
+		writel(reg, &pmc->pmc_pwrgate_toggle);
+
+		/* Wait for the power to come up */
+		while (!is_cpu_powered()) {
+			if (timeout-- == 0)
+				printf("CPU failed to power up!\n");
+			else
+				udelay(10);
+		}
+
+		/*
+		 * Remove the I/O clamps from CPU power partition.
+		 * Recommended only on a Warm boot, if the CPU partition gets
+		 * power gated. Shouldn't cause any harm when called after a
+		 * cold boot according to HW, probably just redundant.
+		 */
+		remove_cpu_io_clamps();
+	}
+}
+
+void reset_A9_cpu(int reset)
+{
+	/*
+	* NOTE:  Regardless of whether the request is to hold the CPU in reset
+	*        or take it out of reset, every processor in the CPU complex
+	*        except the master (CPU 0) will be held in reset because the
+	*        AVP only talks to the master. The AVP does not know that there
+	*        are multiple processors in the CPU complex.
+	*/
+	int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
+	int num_cpus = get_num_cpus();
+	int cpu;
+
+	debug("reset_a9_cpu entry\n");
+	/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
+	for (cpu = 1; cpu < num_cpus; cpu++)
+		reset_cmplx_set_enable(cpu, mask, 1);
+	reset_cmplx_set_enable(0, mask, reset);
+
+	/* Enable/Disable master CPU reset */
+	reset_set_enable(PERIPH_ID_CPU, reset);
+}
+
+void clock_enable_coresight(int enable)
+{
+	u32 rst, src = 2;
+
+	debug("clock_enable_coresight entry\n");
+	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
+	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
+
+	if (enable) {
+		/*
+		 * Put CoreSight on PLLP_OUT0 and divide it down as per
+		 * PLLP base frequency based on SoC type (T20/T30+).
+		 * Clock divider request would setup CSITE clock as 144MHz
+		 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
+		 */
+		src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
+		clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
+
+		/* Unlock the CPU CoreSight interfaces */
+		rst = CORESIGHT_UNLOCK;
+		writel(rst, CSITE_CPU_DBG0_LAR);
+		writel(rst, CSITE_CPU_DBG1_LAR);
+		if (get_num_cpus() == 4) {
+			writel(rst, CSITE_CPU_DBG2_LAR);
+			writel(rst, CSITE_CPU_DBG3_LAR);
+		}
+	}
+}
+
+void halt_avp(void)
+{
+	for (;;) {
+		writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
+		       FLOW_CTLR_HALT_COP_EVENTS);
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/cpu.h b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/cpu.h
new file mode 100644
index 000000000..b4ca44fce
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2010-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <asm/types.h>
+
+/* Stabilization delays, in usec */
+#define PLL_STABILIZATION_DELAY (300)
+#define IO_STABILIZATION_DELAY	(1000)
+
+#if defined(CONFIG_TEGRA20)
+#define NVBL_PLLP_KHZ	216000
+#define CSITE_KHZ	144000
+#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
+	defined(CONFIG_TEGRA124)
+#define NVBL_PLLP_KHZ	408000
+#define CSITE_KHZ	204000
+#else
+#error "Unknown Tegra chip!"
+#endif
+
+#define PLLX_ENABLED		(1 << 30)
+#define CCLK_BURST_POLICY	0x20008888
+#define SUPER_CCLK_DIVIDER	0x80000000
+
+/* Calculate clock fractional divider value from ref and target frequencies */
+#define CLK_DIVIDER(REF, FREQ)  ((((REF) * 2) / FREQ) - 2)
+
+/* Calculate clock frequency value from reference and clock divider value */
+#define CLK_FREQUENCY(REF, REG)  (((REF) * 2) / (REG + 2))
+
+/* AVP/CPU ID */
+#define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
+#define PG_UP_TAG_0             0x0
+
+#define CORESIGHT_UNLOCK	0xC5ACCE55;
+
+#define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
+#define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
+#define CSITE_CPU_DBG1_LAR		(NV_PA_CSITE_BASE + 0x12FB0)
+#define CSITE_CPU_DBG2_LAR		(NV_PA_CSITE_BASE + 0x14FB0)
+#define CSITE_CPU_DBG3_LAR		(NV_PA_CSITE_BASE + 0x16FB0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS	(NV_PA_FLOW_BASE + 4)
+#define FLOW_MODE_STOP			2
+#define HALT_COP_EVENT_JTAG		(1 << 28)
+#define HALT_COP_EVENT_IRQ_1		(1 << 11)
+#define HALT_COP_EVENT_FIQ_1		(1 << 9)
+
+#define FLOW_MODE_NONE		0
+
+#define SIMPLE_PLLX     (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
+
+struct clk_pll_table {
+	u16	n;
+	u16	m;
+	u8	p;
+	u8	cpcon;
+};
+
+void clock_enable_coresight(int enable);
+void enable_cpu_clock(int enable);
+void halt_avp(void)  __attribute__ ((noreturn));
+void init_pllx(void);
+void powerup_cpu(void);
+void reset_A9_cpu(int reset);
+void start_cpu(u32 reset_vector);
+int tegra_get_chip(void);
+int tegra_get_sku_info(void);
+int tegra_get_chip_sku(void);
+void adjust_pllp_out_freqs(void);
+void pmic_enable_cpu_vdd(void);
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/spl.c b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/spl.c
new file mode 100644
index 000000000..347954102
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra-common/spl.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2012
+ * NVIDIA Inc, <www.nvidia.com>
+ *
+ * Allen Martin <amartin@nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/apb_misc.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch/spl.h>
+#include "cpu.h"
+
+void spl_board_init(void)
+{
+	struct apb_misc_pp_ctlr *apb_misc =
+				(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
+
+	/* enable JTAG */
+	writel(0xC0, &apb_misc->cfg_ctl);
+
+	board_init_uart_f();
+
+	/* Initialize periph GPIOs */
+	gpio_early_init_uart();
+
+	clock_early_init();
+	preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_RAM;
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	debug("image entry point: 0x%X\n", spl_image->entry_point);
+
+	start_cpu((u32)spl_image->entry_point);
+	halt_avp();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra114/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra114/Makefile
new file mode 100644
index 000000000..ea3e55ea6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra114/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+#obj-y	+= cpu.o t11x.o
+obj-y	+= cpu.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra114/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra114/cpu.c
new file mode 100644
index 000000000..5ed3bb9d9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra114-specific CPU init code */
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("enable_cpu_power_rail entry\n");
+
+	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+	pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
+	pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
+
+	/*
+	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+	 * set it for 25ms (102MHz * .025)
+	 */
+	reg = 0x26E8F0;
+	writel(reg, &pmc->pmc_cpupwrgood_timer);
+
+	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+
+	/*
+	 * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
+	 * to 408 to satisfy the requirement of having at least 16 CPU clock
+	 * cycles before clamp removal.
+	 */
+
+	clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
+	setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
+}
+
+static void enable_cpu_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("enable_cpu_clocks entry\n");
+
+	/* Wait for PLL-X to lock */
+	do {
+		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+	} while ((reg & PLL_LOCK_MASK) == 0);
+
+	/* Wait until all clocks are stable */
+	udelay(PLL_STABILIZATION_DELAY);
+
+	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+	/* Always enable the main CPU complex clocks */
+	clock_enable(PERIPH_ID_CPU);
+	clock_enable(PERIPH_ID_CPULP);
+	clock_enable(PERIPH_ID_CPUG);
+}
+
+static void remove_cpu_resets(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("remove_cpu_resets entry\n");
+	/* Take the slow non-CPU partition out of reset */
+	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
+	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
+
+	/* Take the fast non-CPU partition out of reset */
+	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
+	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the slow cluster */
+	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
+	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the fast cluster */
+	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
+	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
+	reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
+	reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
+	reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The T114 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void t114_init_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	u32 val;
+
+	debug("t114_init_clocks entry\n");
+
+	/* Set active CPU cluster to G */
+	clrbits_le32(&flow->cluster_control, 1);
+
+	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
+
+	debug("Setting up PLLX\n");
+	init_pllx();
+
+	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+	writel(val, &clkrst->crc_clk_sys_rate);
+
+	/* Enable clocks to required peripherals. TBD - minimize this list */
+	debug("Enabling clocks\n");
+
+	clock_set_enable(PERIPH_ID_CACHE2, 1);
+	clock_set_enable(PERIPH_ID_GPIO, 1);
+	clock_set_enable(PERIPH_ID_TMR, 1);
+	clock_set_enable(PERIPH_ID_RTC, 1);
+	clock_set_enable(PERIPH_ID_CPU, 1);
+	clock_set_enable(PERIPH_ID_EMC, 1);
+	clock_set_enable(PERIPH_ID_I2C5, 1);
+	clock_set_enable(PERIPH_ID_FUSE, 1);
+	clock_set_enable(PERIPH_ID_PMC, 1);
+	clock_set_enable(PERIPH_ID_APBDMA, 1);
+	clock_set_enable(PERIPH_ID_MEM, 1);
+	clock_set_enable(PERIPH_ID_IRAMA, 1);
+	clock_set_enable(PERIPH_ID_IRAMB, 1);
+	clock_set_enable(PERIPH_ID_IRAMC, 1);
+	clock_set_enable(PERIPH_ID_IRAMD, 1);
+	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+	clock_set_enable(PERIPH_ID_MSELECT, 1);
+	clock_set_enable(PERIPH_ID_EMC1, 1);
+	clock_set_enable(PERIPH_ID_MC1, 1);
+	clock_set_enable(PERIPH_ID_DVFS, 1);
+
+	/*
+	 * Set MSELECT clock source as PLLP (00), and ask for a clock
+	 * divider that would set the MSELECT clock at 102MHz for a
+	 * PLLP base of 408MHz.
+	 */
+	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+		CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
+
+	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+	/* Give clocks time to stabilize */
+	udelay(1000);
+
+	/* Take required peripherals out of reset */
+	debug("Taking periphs out of reset\n");
+	reset_set_enable(PERIPH_ID_CACHE2, 0);
+	reset_set_enable(PERIPH_ID_GPIO, 0);
+	reset_set_enable(PERIPH_ID_TMR, 0);
+	reset_set_enable(PERIPH_ID_COP, 0);
+	reset_set_enable(PERIPH_ID_EMC, 0);
+	reset_set_enable(PERIPH_ID_I2C5, 0);
+	reset_set_enable(PERIPH_ID_FUSE, 0);
+	reset_set_enable(PERIPH_ID_APBDMA, 0);
+	reset_set_enable(PERIPH_ID_MEM, 0);
+	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+	reset_set_enable(PERIPH_ID_MSELECT, 0);
+	reset_set_enable(PERIPH_ID_EMC1, 0);
+	reset_set_enable(PERIPH_ID_MC1, 0);
+	reset_set_enable(PERIPH_ID_DVFS, 0);
+
+	debug("t114_init_clocks exit\n");
+}
+
+static bool is_partition_powered(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Get power gate status */
+	reg = readl(&pmc->pmc_pwrgate_status);
+	return !!(reg & (1 << partid));
+}
+
+static bool is_clamp_enabled(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Get clamp status. */
+	reg = readl(&pmc->pmc_clamp_status);
+	return !!(reg & (1 << partid));
+}
+
+static void power_partition(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("%s: part ID = %08X\n", __func__, partid);
+	/* Is the partition already on? */
+	if (!is_partition_powered(partid)) {
+		/* No, toggle the partition power state (OFF -> ON) */
+		debug("power_partition, toggling state\n");
+		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+		/* Wait for the power to come up */
+		while (!is_partition_powered(partid))
+			;
+
+		/* Wait for the clamp status to be cleared */
+		while (is_clamp_enabled(partid))
+			;
+
+		/* Give I/O signals time to stabilize */
+		udelay(IO_STABILIZATION_DELAY);
+	}
+}
+
+void powerup_cpus(void)
+{
+	debug("powerup_cpus entry\n");
+
+	/* We boot to the fast cluster */
+	debug("powerup_cpus entry: G cluster\n");
+	/* Power up the fast cluster rail partition */
+	power_partition(CRAIL);
+
+	/* Power up the fast cluster non-CPU partition */
+	power_partition(C0NC);
+
+	/* Power up the fast cluster CPU0 partition */
+	power_partition(CE0);
+}
+
+void start_cpu(u32 reset_vector)
+{
+	u32 imme, inst;
+
+	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+	t114_init_clocks();
+
+	/* Enable VDD_CPU */
+	enable_cpu_power_rail();
+
+	/* Get the CPU(s) running */
+	enable_cpu_clocks();
+
+	/* Enable CoreSight */
+	clock_enable_coresight(1);
+
+	/* Take CPU(s) out of reset */
+	remove_cpu_resets();
+
+	/* Set the entry point for CPU execution from reset */
+
+	/*
+	 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
+	 * See nvbug 1193357 for details.
+	 */
+
+	/* mov r0, #lsb(reset_vector) */
+	imme = reset_vector & 0xffff;
+	inst = imme & 0xfff;
+	inst |= ((imme >> 12) << 16);
+	inst |= 0xe3000000;
+	writel(inst, 0x4003fff0);
+
+	/* movt r0, #msb(reset_vector) */
+	imme = (reset_vector >> 16) & 0xffff;
+	inst = imme & 0xfff;
+	inst |= ((imme >> 12) << 16);
+	inst |= 0xe3400000;
+	writel(inst, 0x4003fff4);
+
+	/* bx r0 */
+	writel(0xe12fff10, 0x4003fff8);
+
+	/* b -12 */
+	imme = (u32)-20;
+	inst = (imme >> 2) & 0xffffff;
+	inst |= 0xea000000;
+	writel(inst, 0x4003fffc);
+
+	/* Write to orignal location for compatibility */
+	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+	/* If the CPU(s) don't already have power, power 'em up */
+	powerup_cpus();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra124/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra124/Makefile
new file mode 100644
index 000000000..61abf45d3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra124/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= cpu.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra124/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra124/cpu.c
new file mode 100644
index 000000000..6ff6aeb54
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra124/cpu.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ahb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/ap.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra124-specific CPU init code */
+
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("enable_cpu_power_rail entry\n");
+
+	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+	pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
+	pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
+
+	pmic_enable_cpu_vdd();
+
+	/*
+	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+	 * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
+	 */
+	writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
+
+	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+}
+
+static void enable_cpu_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("enable_cpu_clocks entry\n");
+
+	/* Wait for PLL-X to lock */
+	do {
+		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+		debug("%s: PLLX base = 0x%08X\n", __func__, reg);
+	} while ((reg & PLL_LOCK_MASK) == 0);
+
+	debug("%s: PLLX locked, delay for stable clocks\n", __func__);
+	/* Wait until all clocks are stable */
+	udelay(PLL_STABILIZATION_DELAY);
+
+	debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
+	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+	debug("%s: Enabling clock to all CPUs\n", __func__);
+	/* Enable the clock to all CPUs */
+	reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
+		CLR_CPU0_CLK_STP;
+	writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
+
+	debug("%s: Enabling main CPU complex clocks\n", __func__);
+	/* Always enable the main CPU complex clocks */
+	clock_enable(PERIPH_ID_CPU);
+	clock_enable(PERIPH_ID_CPULP);
+	clock_enable(PERIPH_ID_CPUG);
+
+	debug("%s: Done\n", __func__);
+}
+
+static void remove_cpu_resets(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("remove_cpu_resets entry\n");
+
+	/* Take the slow and fast partitions out of reset */
+	reg = CLR_NONCPURESET;
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the slow cluster */
+	reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+		CLR_L2RESET | CLR_PRESETDBG;
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the fast cluster */
+	reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+		CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
+		CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
+		CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
+		CLR_L2RESET | CLR_PRESETDBG;
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The Tegra124 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void tegra124_init_clocks(void)
+{
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 val;
+
+	debug("tegra124_init_clocks entry\n");
+
+	/* Set active CPU cluster to G */
+	clrbits_le32(&flow->cluster_control, 1);
+
+	/* Change the oscillator drive strength */
+	val = readl(&clkrst->crc_osc_ctrl);
+	val &= ~OSC_XOFS_MASK;
+	val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
+	writel(val, &clkrst->crc_osc_ctrl);
+
+	/* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
+	val = readl(&pmc->pmc_osc_edpd_over);
+	val &= ~PMC_XOFS_MASK;
+	val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
+	writel(val, &pmc->pmc_osc_edpd_over);
+
+	/* Set HOLD_CKE_LOW_EN to 1 */
+	setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
+
+	debug("Setting up PLLX\n");
+	init_pllx();
+
+	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+	writel(val, &clkrst->crc_clk_sys_rate);
+
+	/* Enable clocks to required peripherals. TBD - minimize this list */
+	debug("Enabling clocks\n");
+
+	clock_set_enable(PERIPH_ID_CACHE2, 1);
+	clock_set_enable(PERIPH_ID_GPIO, 1);
+	clock_set_enable(PERIPH_ID_TMR, 1);
+	clock_set_enable(PERIPH_ID_CPU, 1);
+	clock_set_enable(PERIPH_ID_EMC, 1);
+	clock_set_enable(PERIPH_ID_I2C5, 1);
+	clock_set_enable(PERIPH_ID_APBDMA, 1);
+	clock_set_enable(PERIPH_ID_MEM, 1);
+	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+	clock_set_enable(PERIPH_ID_MSELECT, 1);
+	clock_set_enable(PERIPH_ID_DVFS, 1);
+
+	/*
+	 * Set MSELECT clock source as PLLP (00), and ask for a clock
+	 * divider that would set the MSELECT clock at 102MHz for a
+	 * PLLP base of 408MHz.
+	 */
+	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+				    CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
+
+	/* Give clock time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+
+	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+	/* Give clock time to stabilize */
+	udelay(IO_STABILIZATION_DELAY);
+
+	/* Take required peripherals out of reset */
+	debug("Taking periphs out of reset\n");
+	reset_set_enable(PERIPH_ID_CACHE2, 0);
+	reset_set_enable(PERIPH_ID_GPIO, 0);
+	reset_set_enable(PERIPH_ID_TMR, 0);
+	reset_set_enable(PERIPH_ID_COP, 0);
+	reset_set_enable(PERIPH_ID_EMC, 0);
+	reset_set_enable(PERIPH_ID_I2C5, 0);
+	reset_set_enable(PERIPH_ID_APBDMA, 0);
+	reset_set_enable(PERIPH_ID_MEM, 0);
+	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+	reset_set_enable(PERIPH_ID_MSELECT, 0);
+	reset_set_enable(PERIPH_ID_DVFS, 0);
+
+	debug("tegra124_init_clocks exit\n");
+}
+
+static bool is_partition_powered(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Get power gate status */
+	reg = readl(&pmc->pmc_pwrgate_status);
+	return !!(reg & (1 << partid));
+}
+
+static void power_partition(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("%s: part ID = %08X\n", __func__, partid);
+	/* Is the partition already on? */
+	if (!is_partition_powered(partid)) {
+		/* No, toggle the partition power state (OFF -> ON) */
+		debug("power_partition, toggling state\n");
+		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+		/* Wait for the power to come up */
+		while (!is_partition_powered(partid))
+			;
+
+		/* Give I/O signals time to stabilize */
+		udelay(IO_STABILIZATION_DELAY);
+	}
+}
+
+void powerup_cpus(void)
+{
+	debug("powerup_cpus entry\n");
+
+	/* We boot to the fast cluster */
+	debug("powerup_cpus entry: G cluster\n");
+
+	/* Power up the fast cluster rail partition */
+	debug("powerup_cpus: CRAIL\n");
+	power_partition(CRAIL);
+
+	/* Power up the fast cluster non-CPU partition */
+	debug("powerup_cpus: C0NC\n");
+	power_partition(C0NC);
+
+	/* Power up the fast cluster CPU0 partition */
+	debug("powerup_cpus: CE0\n");
+	power_partition(CE0);
+
+	debug("powerup_cpus: done\n");
+}
+
+void start_cpu(u32 reset_vector)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+	tegra124_init_clocks();
+
+	/* Set power-gating timer multiplier */
+	writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
+	       &pmc->pmc_pwrgate_timer_mult);
+
+	enable_cpu_power_rail();
+	enable_cpu_clocks();
+	clock_enable_coresight(1);
+	remove_cpu_resets();
+	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+	powerup_cpus();
+	debug("start_cpu exit, should continue @ reset_vector\n");
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra20/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra20/Makefile
new file mode 100644
index 000000000..12243fa9b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra20/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= cpu.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra20/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra20/cpu.c
new file mode 100644
index 000000000..253389955
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra20/cpu.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/pmc.h>
+#include "../tegra-common/cpu.h"
+
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	reg = readl(&pmc->pmc_cntrl);
+	reg |= CPUPWRREQ_OE;
+	writel(reg, &pmc->pmc_cntrl);
+
+	/*
+	 * The TI PMU65861C needs a 3.75ms delay between enabling
+	 * the power rail and enabling the CPU clock.  This delay
+	 * between SM1EN and SM1 is for switching time + the ramp
+	 * up of the voltage to the CPU (VDD_CPU from PMU).
+	 */
+	udelay(3750);
+}
+
+void start_cpu(u32 reset_vector)
+{
+	/* Enable VDD_CPU */
+	enable_cpu_power_rail();
+
+	/* Hold the CPUs in reset */
+	reset_A9_cpu(1);
+
+	/* Disable the CPU clock */
+	enable_cpu_clock(0);
+
+	/* Enable CoreSight */
+	clock_enable_coresight(1);
+
+	/*
+	 * Set the entry point for CPU execution from reset,
+	 *  if it's a non-zero value.
+	 */
+	if (reset_vector)
+		writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+	/* Enable the CPU clock */
+	enable_cpu_clock(1);
+
+	/* If the CPU doesn't already have power, power it up */
+	powerup_cpu();
+
+	/* Take the CPU out of reset */
+	reset_A9_cpu(0);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra30/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra30/Makefile
new file mode 100644
index 000000000..6ff4c5521
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra30/Makefile
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+obj-y	+= cpu.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra30/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra30/cpu.c
new file mode 100644
index 000000000..a80648389
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra30-specific CPU init code */
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}
+
+#define TPS65911_I2C_ADDR		0x5A
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2300 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+#define I2C_SEND_2_BYTES		0x0A02
+
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	debug("enable_cpu_power_rail entry\n");
+	reg = readl(&pmc->pmc_cntrl);
+	reg |= CPUPWRREQ_OE;
+	writel(reg, &pmc->pmc_cntrl);
+
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.4V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
+	udelay(1000);
+	tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
+	udelay(10 * 1000);
+}
+
+/**
+ * The T30 requires some special clock initialization, including setting up
+ * the dvc i2c, turning on mselect and selecting the G CPU cluster
+ */
+void t30_init_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	u32 val;
+
+	debug("t30_init_clocks entry\n");
+	/* Set active CPU cluster to G */
+	clrbits_le32(flow->cluster_control, 1 << 0);
+
+	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
+
+	val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
+		(1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
+		(0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
+		(0 << CLK_SYS_RATE_APB_RATE_SHIFT);
+	writel(val, &clkrst->crc_clk_sys_rate);
+
+	/* Put i2c, mselect in reset and enable clocks */
+	reset_set_enable(PERIPH_ID_DVC_I2C, 1);
+	clock_set_enable(PERIPH_ID_DVC_I2C, 1);
+	reset_set_enable(PERIPH_ID_MSELECT, 1);
+	clock_set_enable(PERIPH_ID_MSELECT, 1);
+
+	/* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
+	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
+
+	/*
+	 * Our high-level clock routines are not available prior to
+	 * relocation. We use the low-level functions which require a
+	 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
+	 */
+	clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
+
+	/*
+	 * Give clocks time to stabilize, then take i2c and mselect out of
+	 * reset
+	 */
+	udelay(1000);
+	reset_set_enable(PERIPH_ID_DVC_I2C, 0);
+	reset_set_enable(PERIPH_ID_MSELECT, 0);
+}
+
+static void set_cpu_running(int run)
+{
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+
+	debug("set_cpu_running entry, run = %d\n", run);
+	writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
+}
+
+void start_cpu(u32 reset_vector)
+{
+	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+	t30_init_clocks();
+
+	/* Enable VDD_CPU */
+	enable_cpu_power_rail();
+
+	set_cpu_running(0);
+
+	/* Hold the CPUs in reset */
+	reset_A9_cpu(1);
+
+	/* Disable the CPU clock */
+	enable_cpu_clock(0);
+
+	/* Enable CoreSight */
+	clock_enable_coresight(1);
+
+	/*
+	 * Set the entry point for CPU execution from reset,
+	 *  if it's a non-zero value.
+	 */
+	if (reset_vector)
+		writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+	/* Enable the CPU clock */
+	enable_cpu_clock(1);
+
+	/* If the CPU doesn't already have power, power it up */
+	powerup_cpu();
+
+	/* Take the CPU out of reset */
+	reset_A9_cpu(0);
+
+	set_cpu_running(1);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm920t/Makefile
new file mode 100644
index 000000000..aac8043f6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+
+obj-y	+= cpu.o
+obj-$(CONFIG_USE_IRQ)	+= interrupts.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/a320/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm920t/a320/Makefile
new file mode 100644
index 000000000..bbdab588c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/a320/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= reset.o
+obj-y	+= timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/a320/reset.S b/qemu/roms/u-boot/arch/arm/cpu/arm920t/a320/reset.S
new file mode 100644
index 000000000..81f9dc983
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/a320/reset.S
@@ -0,0 +1,10 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.global reset_cpu
+reset_cpu:
+	b	reset_cpu
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/a320/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/a320/timer.c
new file mode 100644
index 000000000..1ac5b6012
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/a320/timer.c
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <faraday/ftpmu010.h>
+#include <faraday/fttmr010.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_CLOCK	32768
+#define TIMER_LOAD_VAL	0xffffffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, gd->arch.timer_rate_hz);
+
+	return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+	usec *= gd->arch.timer_rate_hz;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+int timer_init(void)
+{
+	struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	gd->arch.timer_rate_hz = TIMER_CLOCK;
+	gd->arch.tbu = gd->arch.tbl = 0;
+
+	return 0;
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+	struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
+
+	/* increment tbu if tbl has rolled over */
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long start;
+	ulong tmo;
+
+	start = get_ticks();		/* get current timestamp */
+	tmo = usec_to_tick(usec);	/* convert usecs to ticks */
+	while ((get_ticks() - start) < tmo)
+		;			/* loop till time has passed */
+}
+
+/*
+ * get_timer(base) can be used to check for timeouts or
+ * to measure elasped time relative to an event:
+ *
+ * ulong start_time = get_timer(0) sets start_time to the current
+ * time value.
+ * get_timer(start_time) returns the time elapsed since then.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
+ulong get_timer(ulong base)
+{
+	return tick_to_time(get_ticks()) - base;
+}
+
+/*
+ * Return the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return gd->arch.timer_rate_hz;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/Makefile
new file mode 100644
index 000000000..561b4b4cb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= lowlevel_init.o
+obj-y	+= reset.o
+obj-y	+= timer.o
+obj-y	+= clock.o
+obj-y	+= cpu.o
+obj-y	+= at91rm9200_devices.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c
new file mode 100644
index 000000000..fc54327c0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c
@@ -0,0 +1,67 @@
+/*
+ * [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c]
+ *
+ * (C) Copyright 2011
+ * Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
+
+void at91_serial0_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 17, 1);		/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 18, PUP);		/* RXD0 */
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 20, PUP);		/* RXD1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 21, 1);		/* TXD1 */
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 22, PUP);		/* RXD2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 23, 1);		/* TXD2 */
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTA, 30, PUP);		/* DRXD */
+	at91_set_a_periph(AT91_PIO_PORTA, 31, 1);		/* DTXD */
+	/* writing SYS to PCER has no effect on AT91RM9200 */
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/clock.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/clock.c
new file mode 100644
index 000000000..2813bf782
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/clock.c
@@ -0,0 +1,157 @@
+/*
+ * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
+ *
+ * Copyright (C) 2011 Andreas Bießmann
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned long at91_css_to_rate(unsigned long css)
+{
+	switch (css) {
+	case AT91_PMC_MCKR_CSS_SLOW:
+		return CONFIG_SYS_AT91_SLOW_CLOCK;
+	case AT91_PMC_MCKR_CSS_MAIN:
+		return gd->arch.main_clk_rate_hz;
+	case AT91_PMC_MCKR_CSS_PLLA:
+		return gd->arch.plla_rate_hz;
+	case AT91_PMC_MCKR_CSS_PLLB:
+		return gd->arch.pllb_rate_hz;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_ATMEL
+static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
+{
+	unsigned i, div = 0, mul = 0, diff = 1 << 30;
+	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
+
+	/* PLL output max 240 MHz (or 180 MHz per errata) */
+	if (out_freq > 240000000)
+		goto fail;
+
+	for (i = 1; i < 256; i++) {
+		int diff1;
+		unsigned input, mul1;
+
+		/*
+		 * PLL input between 1MHz and 32MHz per spec, but lower
+		 * frequences seem necessary in some cases so allow 100K.
+		 * Warning: some newer products need 2MHz min.
+		 */
+		input = main_freq / i;
+		if (input < 100000)
+			continue;
+		if (input > 32000000)
+			continue;
+
+		mul1 = out_freq / input;
+		if (mul1 > 2048)
+			continue;
+		if (mul1 < 2)
+			goto fail;
+
+		diff1 = out_freq - input * mul1;
+		if (diff1 < 0)
+			diff1 = -diff1;
+		if (diff > diff1) {
+			diff = diff1;
+			div = i;
+			mul = mul1;
+			if (diff == 0)
+				break;
+		}
+	}
+	if (i == 256 && diff > (out_freq >> 5))
+		goto fail;
+	return ret | ((mul - 1) << 16) | div;
+fail:
+	return 0;
+}
+#endif
+
+static u32 at91_pll_rate(u32 freq, u32 reg)
+{
+	unsigned mul, div;
+
+	div = reg & 0xff;
+	mul = (reg >> 16) & 0x7ff;
+	if (div && mul) {
+		freq /= div;
+		freq *= mul + 1;
+	} else
+		freq = 0;
+
+	return freq;
+}
+
+int at91_clock_init(unsigned long main_clock)
+{
+	unsigned freq, mckr;
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+	unsigned tmp;
+	/*
+	 * When the bootloader initialized the main oscillator correctly,
+	 * there's no problem using the cycle counter.  But if it didn't,
+	 * or when using oscillator bypass mode, we must be told the speed
+	 * of the main clock.
+	 */
+	if (!main_clock) {
+		do {
+			tmp = readl(&pmc->mcfr);
+		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
+		tmp &= AT91_PMC_MCFR_MAINF_MASK;
+		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+	}
+#endif
+	gd->arch.main_clk_rate_hz = main_clock;
+
+	/* report if PLLA is more than mildly overclocked */
+	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+
+#ifdef CONFIG_USB_ATMEL
+	/*
+	 * USB clock init:  choose 48 MHz PLLB value,
+	 * disable 48MHz clock during usb peripheral suspend.
+	 *
+	 * REVISIT:  assumes MCK doesn't derive from PLLB!
+	 */
+	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+			     AT91_PMC_PLLBR_USBDIV_2;
+	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+					      gd->arch.at91_pllb_usb_init);
+#endif
+
+	/*
+	 * MCK and CPU derive from one of those primary clocks.
+	 * For now, assume this parentage won't change.
+	 */
+	mckr = readl(&pmc->mckr);
+	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+	freq = gd->arch.mck_rate_hz;
+
+	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
+	/* mdiv */
+	gd->arch.mck_rate_hz = freq /
+			(1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+	gd->arch.cpu_clk_rate_hz = freq;
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/cpu.c
new file mode 100644
index 000000000..b0f411b1c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/cpu.c
@@ -0,0 +1,26 @@
+/*
+ * [origin: arch/arm/cpu/arm926ejs/at91/cpu.c]
+ *
+ * (C) Copyright 2011
+ * Andreas Bießmann, andreas.devel@googlemail.com
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#endif
+
+int arch_cpu_init(void)
+{
+	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/lowlevel_init.S
new file mode 100644
index 000000000..d2934a352
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/lowlevel_init.S
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_mc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+
+#define ARM920T_CONTROL	0xC0000000	/* @ set bit 31 (iA) and 30 (nF) */
+
+_MTEXT_BASE:
+#undef START_FROM_MEM
+#ifdef START_FROM_MEM
+	.word	CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
+#else
+	.word	CONFIG_SYS_TEXT_BASE
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr     r1, =AT91_ASM_PMC_MOR
+	/* Main oscillator Enable register */
+#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
+	ldr     r0, =0x0000FF01		/* Enable main oscillator */
+#else
+	ldr     r0, =0x0000FF00		/* Disable main oscillator */
+#endif
+	str     r0, [r1] /*AT91C_CKGR_MOR] */
+	/* Add loop to compensate Main Oscillator startup time */
+	ldr     r0, =0x00000010
+LoopOsc:
+	subs    r0, r0, #1
+	bhi     LoopOsc
+
+	/* memory control configuration */
+	/* this isn't very elegant, but	 what the heck */
+	ldr	r0, =SMRDATA
+	ldr	r1, _MTEXT_BASE
+	sub	r0, r0, r1
+	ldr	r2, =SMRDATAE
+	sub	r2, r2, r1
+pllloop:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	pllloop
+	/* delay - this is all done by guess */
+	ldr	r0, =0x00010000
+	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
+lock:
+	subs	r0, r0, #1
+	bhi	lock
+	ldr	r0, =SMRDATA1
+	ldr	r1, _MTEXT_BASE
+	sub	r0, r0, r1
+	ldr	r2, =SMRDATA1E
+	sub	r2, r2, r1
+sdinit:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	sdinit
+
+	/* switch from FastBus to Asynchronous clock mode */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #ARM920T_CONTROL
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word AT91_ASM_MC_EBI_CFG
+	.word CONFIG_SYS_EBI_CFGR_VAL
+	.word AT91_ASM_MC_SMC_CSR0
+	.word CONFIG_SYS_SMC_CSR0_VAL
+	.word AT91_ASM_PMC_PLLAR
+	.word CONFIG_SYS_PLLAR_VAL
+	.word AT91_ASM_PMC_PLLBR
+	.word CONFIG_SYS_PLLBR_VAL
+	.word AT91_ASM_PMC_MCKR
+	.word CONFIG_SYS_MCKR_VAL
+SMRDATAE:
+	/* here there's a delay */
+SMRDATA1:
+	.word AT91_ASM_PIOC_ASR
+	.word CONFIG_SYS_PIOC_ASR_VAL
+	.word AT91_ASM_PIOC_BSR
+	.word CONFIG_SYS_PIOC_BSR_VAL
+	.word AT91_ASM_PIOC_PDR
+	.word CONFIG_SYS_PIOC_PDR_VAL
+	.word AT91_ASM_MC_EBI_CSA
+	.word CONFIG_SYS_EBI_CSA_VAL
+	.word AT91_ASM_MC_SDRAMC_CR
+	.word CONFIG_SYS_SDRC_CR_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL1
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL2
+	.word CONFIG_SYS_SDRAM1
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_TR
+	.word CONFIG_SYS_SDRC_TR_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL3
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+SMRDATA1E:
+	/* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/reset.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/reset.c
new file mode 100644
index 000000000..d47777a36
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/reset.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_st.h>
+
+void  __attribute__((weak)) board_reset(void)
+{
+	/* true empty function for defining weak symbol */
+}
+
+void reset_cpu(ulong ignored)
+{
+	at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;
+
+	board_reset();
+
+	/* Reset the cpu by setting up the watchdog timer */
+	writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
+		&st->wdmr);
+	writel(AT91_ST_CR_WDRST, &st->cr);
+	/* and let it timeout */
+	while (1)
+		;
+	/* Never reached */
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/timer.c
new file mode 100644
index 000000000..6aa299472
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/at91/timer.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_tc.h>
+#include <asm/arch/at91_pmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* the number of clocks per CONFIG_SYS_HZ */
+#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
+
+int timer_init(void)
+{
+	at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	/* enables TC1.0 clock */
+	writel(1 << ATMEL_ID_TC0, &pmc->pcer);	/* enable clock */
+
+	writel(0, &tc->bcr);
+	writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
+		AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
+
+	writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
+	/* set to MCLK/2 and restart the timer
+	when the value in TC_RC is reached */
+	writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
+
+	writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
+	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
+
+	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
+	gd->arch.lastinc = 0;
+	gd->arch.tbl = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+ulong get_timer_raw(void)
+{
+	at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
+	u32 now;
+
+	now = readl(&tc->tc[0].cv) & 0x0000ffff;
+
+	if (now >= gd->arch.lastinc) {
+		/* normal mode */
+		gd->arch.tbl += now - gd->arch.lastinc;
+	} else {
+		/* we have an overflow ... */
+		gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
+	}
+	gd->arch.lastinc = now;
+
+	return gd->arch.tbl;
+}
+
+ulong get_timer_masked(void)
+{
+	return get_timer_raw()/TIMER_LOAD_VAL;
+}
+
+void udelay_masked(unsigned long usec)
+{
+	u32 tmo;
+	u32 endtime;
+	signed long diff;
+
+	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+	tmo *= usec;
+	tmo /= 1000;
+
+	endtime = get_timer_raw() + tmo;
+
+	do {
+		u32 now = get_timer_raw();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/config.mk b/qemu/roms/u-boot/arch/arm/cpu/arm920t/config.mk
new file mode 100644
index 000000000..799afff02
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/config.mk
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -march=armv4
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/cpu.c
new file mode 100644
index 000000000..d73b51dce
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/cpu.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+	/* flush I/D-cache */
+	cache_flush();
+
+	return 0;
+}
+
+/* flush I/D-cache */
+static void cache_flush (void)
+{
+	unsigned long i = 0;
+
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/Makefile
new file mode 100644
index 000000000..638333a48
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/Makefile
@@ -0,0 +1,21 @@
+#
+# Cirrus Logic EP93xx CPU-specific Makefile
+#
+# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+#
+# Copyright (C) 2004, 2005
+# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+#
+# Copyright (C) 2006
+# Dominic Rath <Dominic.Rath@gmx.de>
+#
+# Based on an original Makefile, which is
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y   = cpu.o led.o speed.o timer.o
+obj-y   += lowlevel_init.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/cpu.c
new file mode 100644
index 000000000..bb5ffd292
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/cpu.c
@@ -0,0 +1,37 @@
+/*
+ * Cirrus Logic EP93xx CPU-specific support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
+extern void reset_cpu(ulong addr)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	uint32_t value;
+
+	/* Unlock DeviceCfg and set SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value |= SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Unlock DeviceCfg and clear SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value &= ~SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Dying... */
+	while (1)
+		; /* noop */
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/led.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/led.c
new file mode 100644
index 000000000..614472918
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/led.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/ep93xx.h>
+#include <config.h>
+#include <status_led.h>
+
+static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN,
+			       1 << STATUS_LED_RED};
+
+inline void switch_LED_on(uint8_t led)
+{
+	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+	writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
+	saved_state[led] = STATUS_LED_ON;
+}
+
+inline void switch_LED_off(uint8_t led)
+{
+	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+	writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
+	saved_state[led] = STATUS_LED_OFF;
+}
+
+void red_led_on(void)
+{
+	switch_LED_on(STATUS_LED_RED);
+}
+
+void red_led_off(void)
+{
+	switch_LED_off(STATUS_LED_RED);
+}
+
+void green_led_on(void)
+{
+	switch_LED_on(STATUS_LED_GREEN);
+}
+
+void green_led_off(void)
+{
+	switch_LED_off(STATUS_LED_GREEN);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	__led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+	if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+			red_led_off();
+		else
+			red_led_on();
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
+			green_led_off();
+		else
+			green_led_on();
+	}
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == state)
+			red_led_on();
+		else
+			red_led_off();
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == state)
+			green_led_on();
+		else
+			green_led_off();
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
new file mode 100644
index 000000000..bf2fa2ac3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
@@ -0,0 +1,49 @@
+/*
+ * Low-level initialization for EP93xx
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <version.h>
+#include <asm/arch/ep93xx.h>
+
+.globl lowlevel_init
+lowlevel_init:
+	/* backup return address */
+	ldr r1, =SYSCON_SCRATCH0
+	str lr, [r1]
+
+	/* Turn on both LEDs */
+	bl red_led_on
+	bl green_led_on
+
+	/* Configure flash wait states before we switch to the PLL */
+	bl flash_cfg
+
+	/* Set up PLL */
+	bl pll_cfg
+
+	/* Turn off the Green LED and leave the Red LED on */
+	bl green_led_off
+
+	/* Setup SDRAM */
+	bl sdram_cfg
+
+	/* Turn on Green LED, Turn off the Red LED */
+	bl green_led_on
+	bl red_led_off
+
+	/* FIXME: we use async mode for now */
+	mrc p15, 0, r0, c1, c0, 0
+	orr r0, r0, #0xc0000000
+	mcr p15, 0, r0, c1, c0, 0
+
+	/* restore return address */
+	ldr r1, =SYSCON_SCRATCH0
+	ldr lr, [r1]
+
+	mov pc, lr
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/speed.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/speed.c
new file mode 100644
index 000000000..9dc60b6ff
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/speed.c
@@ -0,0 +1,96 @@
+/*
+ * Cirrus Logic EP93xx PLL support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+/*
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+
+/*
+ * return the PLL output frequency
+ *
+ * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
+ * / (X2IPD + 1) / 2^PS
+ */
+static ulong get_PLLCLK(uint32_t *pllreg)
+{
+	uint8_t i;
+	const uint32_t clkset = readl(pllreg);
+	uint64_t rate = CONFIG_SYS_CLK_FREQ;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
+	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
+	for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
+		rate >>= 1;
+
+	return (ulong)rate;
+}
+
+/* return FCLK frequency */
+ulong get_FCLK()
+{
+	const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t fclk_div =
+		fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
+	const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
+
+	return fclk_rate;
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t hclk_div =
+		hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
+	const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
+
+	return hclk_rate;
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t pclk_div =
+		pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
+	const ulong pclk_rate = get_HCLK() / pclk_div;
+
+	return pclk_rate;
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	ulong uclk_rate;
+
+	const uint32_t value = readl(&syscon->pwrcnt);
+	if (value & SYSCON_PWRCNT_UART_BAUD)
+		uclk_rate = CONFIG_SYS_CLK_FREQ;
+	else
+		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
+
+	return uclk_rate;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/timer.c
new file mode 100644
index 000000000..c2f239aab
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/timer.c
@@ -0,0 +1,120 @@
+/*
+ * Cirrus Logic EP93xx timer support.
+ *
+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
+ * author unknown.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+#define TIMER_CLKSEL	(1 << 3)
+#define TIMER_ENABLE	(1 << 7)
+
+#define TIMER_FREQ			508469		/* ticks / second */
+#define TIMER_MAX_VAL			0xFFFFFFFF
+
+static struct ep93xx_timer
+{
+	unsigned long long ticks;
+	unsigned long last_read;
+} timer;
+
+static inline unsigned long long usecs_to_ticks(unsigned long usecs)
+{
+	unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
+	do_div(ticks, 1000 * 1000);
+
+	return ticks;
+}
+
+static inline void read_timer(void)
+{
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+	const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
+
+	if (now >= timer.last_read)
+		timer.ticks += now - timer.last_read;
+	else
+		/* an overflow occurred */
+		timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
+
+	timer.last_read = now;
+}
+
+/*
+ * Get the number of ticks (in CONFIG_SYS_HZ resolution)
+ */
+unsigned long long get_ticks(void)
+{
+	unsigned long long sys_ticks;
+
+	read_timer();
+
+	sys_ticks = timer.ticks * CONFIG_SYS_HZ;
+	do_div(sys_ticks, TIMER_FREQ);
+
+	return sys_ticks;
+}
+
+unsigned long get_timer_masked(void)
+{
+	return get_ticks();
+}
+
+unsigned long get_timer(unsigned long base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long target;
+
+	read_timer();
+
+	target = timer.ticks + usecs_to_ticks(usec);
+
+	while (timer.ticks < target)
+		read_timer();
+}
+
+int timer_init(void)
+{
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+
+	/* use timer 3 with 508KHz and free running, not enabled now */
+	writel(TIMER_CLKSEL, &timer_regs->timer3.control);
+
+	/* set initial timer value */
+	writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
+
+	/* Enable the timer */
+	writel(TIMER_ENABLE | TIMER_CLKSEL,
+		&timer_regs->timer3.control);
+
+	/* Reset the timer */
+	read_timer();
+	timer.ticks = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
new file mode 100644
index 000000000..96994043e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		*(.__image_copy_start)
+	  arch/arm/cpu/arm920t/start.o	(.text*)
+		/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
+	  . = 0x1000;
+	  LONG(0x53555243)
+	  *(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata*) }
+
+	. = ALIGN(4);
+	.data : { *(.data*) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	__bss_start = .;
+	.bss : { *(.bss*) }
+	__bss_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/Makefile
new file mode 100644
index 000000000..54ce646d9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= generic.o
+obj-y	+= speed.o
+obj-y	+= timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/generic.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/generic.c
new file mode 100644
index 000000000..1441ab439
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/generic.c
@@ -0,0 +1,77 @@
+/*
+ *  arch/arm/mach-imx/generic.c
+ *
+ *  author: Sascha Hauer
+ *  Created: april 20th, 2004
+ *  Copyright: Synertronixx GmbH
+ *
+ *  Common code for i.MX machines
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_IMX
+
+#include <asm/arch/imx-regs.h>
+
+void imx_gpio_mode(int gpio_mode)
+{
+	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
+	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
+	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
+	unsigned int tmp;
+
+	/* Pullup enable */
+	if(gpio_mode & GPIO_PUEN)
+		PUEN(port) |= (1<<pin);
+	else
+		PUEN(port) &= ~(1<<pin);
+
+	/* Data direction */
+	if(gpio_mode & GPIO_OUT)
+		DDIR(port) |= 1<<pin;
+	else
+		DDIR(port) &= ~(1<<pin);
+
+	/* Primary / alternate function */
+	if(gpio_mode & GPIO_AF)
+		GPR(port) |= (1<<pin);
+	else
+		GPR(port) &= ~(1<<pin);
+
+	/* use as gpio? */
+	if( ocr == 3 )
+		GIUS(port) |= (1<<pin);
+	else
+		GIUS(port) &= ~(1<<pin);
+
+	/* Output / input configuration */
+	/* FIXME: I'm not very sure about OCR and ICONF, someone
+	 * should have a look over it
+	 */
+	if(pin<16) {
+		tmp = OCR1(port);
+		tmp &= ~( 3<<(pin*2));
+		tmp |= (ocr << (pin*2));
+		OCR1(port) = tmp;
+
+		if( gpio_mode &	GPIO_AOUT )
+			ICONFA1(port) &= ~( 3<<(pin*2));
+		if( gpio_mode &	GPIO_BOUT )
+			ICONFB1(port) &= ~( 3<<(pin*2));
+	} else {
+		tmp = OCR2(port);
+		tmp &= ~( 3<<((pin-16)*2));
+		tmp |= (ocr << ((pin-16)*2));
+		OCR2(port) = tmp;
+
+		if( gpio_mode &	GPIO_AOUT )
+			ICONFA2(port) &= ~( 3<<((pin-16)*2));
+		if( gpio_mode &	GPIO_BOUT )
+			ICONFB2(port) &= ~( 3<<((pin-16)*2));
+	}
+}
+
+#endif /* CONFIG_IMX */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/speed.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/speed.c
new file mode 100644
index 000000000..1951313dd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/speed.c
@@ -0,0 +1,86 @@
+/*
+ *
+ * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#if defined (CONFIG_IMX)
+
+#include <asm/arch/imx-regs.h>
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ * SH FIXME: 16780000 in our case
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+ulong get_systemPLLCLK(void)
+{
+	/* FIXME: We assume System_SEL = 0 here */
+	u32 spctl0 = SPCTL0;
+	u32 mfi = (spctl0 >> 10) & 0xf;
+	u32 mfn = spctl0 & 0x3f;
+	u32 mfd = (spctl0 >> 16) & 0x3f;
+	u32 pd =  (spctl0 >> 26) & 0xf;
+
+	mfi = mfi<=5 ? 5 : mfi;
+
+	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+}
+
+ulong get_mcuPLLCLK(void)
+{
+	/* FIXME: We assume System_SEL = 0 here */
+	u32 mpctl0 = MPCTL0;
+	u32 mfi = (mpctl0 >> 10) & 0xf;
+	u32 mfn = mpctl0 & 0x3f;
+	u32 mfd = (mpctl0 >> 16) & 0x3f;
+	u32 pd =  (mpctl0 >> 26) & 0xf;
+
+	mfi = mfi<=5 ? 5 : mfi;
+
+	return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+}
+
+ulong get_FCLK(void)
+{
+	return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
+	printf("bclkdiv: %d\n", bclkdiv);
+	return get_systemPLLCLK() / bclkdiv;
+}
+
+/* return BCLK frequency */
+ulong get_BCLK(void)
+{
+	return get_HCLK();
+}
+
+ulong get_PERCLK1(void)
+{
+	return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
+}
+
+ulong get_PERCLK2(void)
+{
+	return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
+}
+
+ulong get_PERCLK3(void)
+{
+	return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
+}
+
+#endif /* defined (CONFIG_IMX) */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/timer.c
new file mode 100644
index 000000000..b62558f92
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/imx/timer.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#if defined (CONFIG_IMX)
+
+#include <asm/arch/imx-regs.h>
+
+int timer_init (void)
+{
+	int i;
+	/* setup GP Timer 1 */
+	TCTL1 = TCTL_SWR;
+	for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
+	TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
+	TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
+
+	/* Reset the timer */
+	TCTL1 &= ~TCTL_TEN;
+	TCTL1 |= TCTL_TEN; /* Enable timer */
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer (ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+ulong get_timer_masked (void)
+{
+	return TCN1;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong endtime = get_timer_masked() + usec;
+	signed long diff;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+void __udelay (unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;
+}
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+	/* Disable watchdog and set Time-Out field to 0 */
+	WCR = 0x00000000;
+
+	/* Write Service Sequence */
+	WSR = 0x00005555;
+	WSR = 0x0000AAAA;
+
+	/* Enable watchdog */
+	WCR = 0x00000001;
+
+	while (1);
+	/*NOTREACHED*/
+}
+
+#endif /* defined (CONFIG_IMX) */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/interrupts.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/interrupts.c
new file mode 100644
index 000000000..0e04d3668
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/interrupts.c
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+
+#if defined (CONFIG_ARCH_INTEGRATOR)
+void do_irq (struct pt_regs *pt_regs)
+{
+	/* ASSUMED to be a timer interrupt  */
+	/* Just clear it - count handled in */
+	/* integratorap.c                   */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/ks8695/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ks8695/Makefile
new file mode 100644
index 000000000..400aa89e9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ks8695/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= lowlevel_init.o
+obj-y	+= timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
new file mode 100644
index 000000000..a2a07f2f2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
@@ -0,0 +1,189 @@
+/*
+ *  lowlevel_init.S - basic hardware initialization for the KS8695 CPU
+ *
+ *  Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/platform.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ *************************************************************************
+ *
+ * Handy dandy macros
+ *
+ *************************************************************************
+ */
+
+/* Delay a bit */
+.macro DELAY_FOR cycles, reg0
+	ldr     \reg0, =\cycles
+	subs    \reg0, \reg0, #1
+	subne   pc,  pc, #0xc
+.endm
+
+/*
+ *************************************************************************
+ *
+ * Some local storage.
+ *
+ *************************************************************************
+ */
+
+/* Should we boot with an interactive console or not */
+.globl serial_console
+
+/*
+ *************************************************************************
+ *
+ * Raw hardware initialization code. The important thing is to get
+ * SDRAM setup and running. We do some other basic things here too,
+ * like getting the PLL set for high speed, and init the LEDs.
+ *
+ *************************************************************************
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+#if DEBUG
+	/*
+	 * enable UART for early debug trace
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
+	mov	r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
+	str	r2, [r1]
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
+	mov	r2, #KS8695_UART_LINEC_WLEN8
+	str	r2, [r1]		/* 8 data bits, no parity, 1 stop */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
+	mov	r2, #0x41
+	str	r2, [r1]		/* write 'A' */
+#endif
+#if DEBUG
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
+	mov	r2, #0x42
+	str	r2, [r1]
+#endif
+
+	/*
+	 * remap the memory and flash regions. we want to end up with
+	 * ram from address 0, and flash at 32MB.
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
+	ldr	r2, =0xbfc00040
+	str	r2, [r1]		/* large flash map */
+	ldr	pc, =(highflash+0x02000000-0x00f00000)	/* jump to high flash address */
+highflash:
+	ldr	r2, =0x8fe00040
+	str	r2, [r1]		/* remap flash range */
+
+	/*
+	 * remap the second select region to the 4MB immediately after
+	 * the first region. This way if you have a larger flash (say 8Mb)
+	 * then you can have it all mapped nicely. Has no effect if you
+	 * only have a 4Mb or smaller flash.
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
+	ldr	r2, =0x9fe40040
+	str	r2, [r1]		/* remap flash2 region, contiguous */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
+	ldr	r2, =0x30000005
+	str	r2, [r1]		/* enable both flash selects */
+
+#ifdef CONFIG_CM41xx
+	/*
+	 * map the second flash chip, using the external IO lines.
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
+	ldr	r2, =0xafe80b6d
+	str	r2, [r1]		/* remap io0 region, contiguous */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
+	ldr	r2, =0xbfec0b6d
+	str	r2, [r1]		/* remap io1 region, contiguous */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
+	ldr	r2, =0x30050005
+	str	r2, [r1]		/* enable second flash */
+#endif
+
+	/*
+	 * before relocating, we have to setup RAM timing
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
+#if (PHYS_SDRAM_1_SIZE == 0x02000000)
+	ldr	r2, =0x7fc0000e		/* 32MB */
+#else
+	ldr	r2, =0x3fc0000e		/* 16MB */
+#endif
+	str	r2, [r1]		/* configure sdram bank0 setup */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
+	mov	r2, #0
+	str	r2, [r1]		/* configure sdram bank1 setup */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
+	ldr	r2, =0x0000000a
+	str	r2, [r1]		/* set RAS/CAS timing */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
+	ldr	r2, =0x00030000
+	str	r2, [r1]		/* send NOP command */
+	DELAY_FOR 0x100, r0
+	ldr	r2, =0x00010000
+	str	r2, [r1]		/* send PRECHARGE-ALL */
+	DELAY_FOR 0x100, r0
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
+	ldr	r2, =0x00000020
+	str	r2, [r1]		/* set for fast refresh */
+	DELAY_FOR 0x100, r0
+	ldr	r2, =0x00000190
+	str	r2, [r1]		/* set normal refresh timing */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
+	ldr	r2, =0x00020033
+	str	r2, [r1]		/* send mode command */
+	DELAY_FOR 0x100, r0
+	ldr	r2, =0x01f00000
+	str	r2, [r1]		/* enable sdram fifos */
+
+	/*
+	 * set pll to top speed
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
+	mov	r2, #0
+	str	r2, [r1]		/* set pll clock to 166MHz */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
+	ldr	r2, [r1]		/* Get switch ctrl0 register       */
+	and	r2, r2, #0x0fc00000	/* Mask out LED control bits       */
+	orr	r2, r2, #0x01800000	/* Set Link/activity/speed actions */
+	str	r2, [r1]
+
+#ifdef CONFIG_CM4008
+	ldr	r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
+	ldr	r2, =0x0000fe30
+	str	r2, [r1]		/* enable LED's as outputs	    */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
+	ldr	r2, =0x0000fe20
+	str	r2, [r1]		/* turn on power LED		    */
+#endif
+#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
+	ldr	r2, [r1]		/* get current GPIO input data	    */
+	tst	r2, #0x8		/* check if "erase" depressed	    */
+	beq	nobutton
+	mov	r2, #0			/* be quiet on boot, no console	    */
+	ldr	r1, =serial_console
+	str	r2, [r1]
+nobutton:
+#endif
+
+	add	lr, lr, #0x02000000	/* flash is now mapped high */
+	add	ip, ip, #0x02000000	/* this is a hack */
+	mov	pc, lr			/* all done, return */
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/ks8695/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ks8695/timer.c
new file mode 100644
index 000000000..23db5572d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/ks8695/timer.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/*
+ * Initial timer set constants. Nothing complicated, just set for a 1ms
+ * tick.
+ */
+#define	TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_1)
+#define	TIMER_COUNT	(TIMER_INTERVAL / 2)
+#define	TIMER_PULSE	TIMER_COUNT
+
+/*
+ * Handy KS8695 register access functions.
+ */
+#define	ks8695_read(a)    *((volatile ulong *) (KS8695_IO_BASE + (a)))
+#define	ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
+
+ulong timer_ticks;
+
+int timer_init (void)
+{
+	/* Set the hadware timer for 1ms */
+	ks8695_write(KS8695_TIMER1, TIMER_COUNT);
+	ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
+	ks8695_write(KS8695_TIMER_CTRL, 0x2);
+	timer_ticks = 0;
+
+	return 0;
+}
+
+ulong get_timer_masked(void)
+{
+	/* Check for timer wrap */
+	if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
+		/* Clear interrupt condition */
+		ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
+		timer_ticks++;
+	}
+	return timer_ticks;
+}
+
+ulong get_timer(ulong base)
+{
+       return (get_timer_masked() - base);
+}
+
+void __udelay(ulong usec)
+{
+	ulong start = get_timer_masked();
+	ulong end;
+
+	/* Only 1ms resolution :-( */
+	end = usec / 1000;
+	while (get_timer(start) < end)
+		;
+}
+
+void reset_cpu (ulong ignored)
+{
+	ulong tc;
+
+	/* Set timer0 to watchdog, and let it timeout */
+	tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
+	ks8695_write(KS8695_TIMER_CTRL, tc);
+	ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
+	ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
+
+	/* Should only wait here till watchdog resets */
+	for (;;)
+		;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/Makefile
new file mode 100644
index 000000000..e44c549ba
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_USE_IRQ) += interrupts.o
+obj-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
+obj-y	+= speed.o
+obj-y	+= timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
new file mode 100644
index 000000000..fede51a16
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2010
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+typedef ulong (*getfreq)(void);
+
+static const getfreq freq_f[] = {
+	get_FCLK,
+	get_HCLK,
+	get_PCLK,
+};
+
+static const char freq_c[] = { 'F', 'H', 'P' };
+
+int print_cpuinfo(void)
+{
+	int i;
+	char buf[32];
+/* the S3C2400 seems to be lacking a CHIP ID register */
+#ifndef CONFIG_S3C2400
+	ulong cpuid;
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	cpuid = readl(&gpio->gstatus1);
+	printf("CPUID: %8lX\n", cpuid);
+#endif
+	for (i = 0; i < ARRAY_SIZE(freq_f); i++)
+		printf("%cCLK: %8s MHz\n", freq_c[i], strmhz(buf, freq_f[i]()));
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/interrupts.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
new file mode 100644
index 000000000..036e3b906
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/arch/s3c24x0_cpu.h>
+#include <asm/proc-armv/ptrace.h>
+
+void do_irq (struct pt_regs *pt_regs)
+{
+	struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
+	u_int32_t intpnd = readl(&irq->INTPND);
+
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/speed.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/speed.c
new file mode 100644
index 000000000..3701c5d9a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/speed.c
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* This code should work for both the S3C2400 and the S3C2410
+ * as they seem to have the same PLL and clock machinery inside.
+ * The different address mapping is handled by the s3c24xx.h files below.
+ */
+
+#include <common.h>
+#ifdef CONFIG_S3C24X0
+
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+#define MPLL 0
+#define UPLL 1
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+	ulong r, m, p, s;
+
+	if (pllreg == MPLL)
+		r = readl(&clk_power->mpllcon);
+	else if (pllreg == UPLL)
+		r = readl(&clk_power->upllcon);
+	else
+		hang();
+
+	m = ((r & 0xFF000) >> 12) + 8;
+	p = ((r & 0x003F0) >> 4) + 2;
+	s = r & 0x3;
+
+#if defined(CONFIG_S3C2440)
+	if (pllreg == MPLL)
+		return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
+#endif
+	return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
+
+}
+
+/* return FCLK frequency */
+ulong get_FCLK(void)
+{
+	return get_PLLCLK(MPLL);
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+#ifdef CONFIG_S3C2440
+	switch (readl(&clk_power->clkdivn) & 0x6) {
+	default:
+	case 0:
+		return get_FCLK();
+	case 2:
+		return get_FCLK() / 2;
+	case 4:
+		return (readl(&clk_power->camdivn) & (1 << 9)) ?
+			get_FCLK() / 8 : get_FCLK() / 4;
+	case 6:
+		return (readl(&clk_power->camdivn) & (1 << 8)) ?
+			get_FCLK() / 6 : get_FCLK() / 3;
+	}
+#else
+	return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
+#endif
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+
+	return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	return get_PLLCLK(UPLL);
+}
+
+#endif /* CONFIG_S3C24X0 */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/timer.c
new file mode 100644
index 000000000..ba1e616b8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#ifdef CONFIG_S3C24X0
+
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int timer_init(void)
+{
+	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+	ulong tmr;
+
+	/* use PWM Timer 4 because it has no output */
+	/* prescaler for Timer 4 is 16 */
+	writel(0x0f00, &timers->tcfg0);
+	if (gd->arch.tbu == 0) {
+		/*
+		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
+		 * (default) and prescaler = 16. Should be 10390
+		 * @33.25MHz and 15625 @ 50 MHz
+		 */
+		gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
+		gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
+	}
+	/* load value for 10 ms timeout */
+	writel(gd->arch.tbu, &timers->tcntb4);
+	/* auto load, manual update of timer 4 */
+	tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
+	writel(tmr, &timers->tcon);
+	/* auto load, start timer 4 */
+	tmr = (tmr & ~0x0700000) | 0x0500000;
+	writel(tmr, &timers->tcon);
+	gd->arch.lastinc = 0;
+	gd->arch.tbl = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay (unsigned long usec)
+{
+	ulong tmo;
+	ulong start = get_ticks();
+
+	tmo = usec / 1000;
+	tmo *= (gd->arch.tbu * 100);
+	tmo /= 1000;
+
+	while ((ulong) (get_ticks() - start) < tmo)
+		/*NOP*/;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong tmr = get_ticks();
+
+	return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
+}
+
+void udelay_masked(unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= (gd->arch.tbu * 100);
+		tmo /= 1000;
+	} else {
+		tmo = usec * (gd->arch.tbu * 100);
+		tmo /= (1000 * 1000);
+	}
+
+	endtime = get_ticks() + tmo;
+
+	do {
+		ulong now = get_ticks();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+	ulong now = readl(&timers->tcnto4) & 0xffff;
+
+	if (gd->arch.lastinc >= now) {
+		/* normal mode */
+		gd->arch.tbl += gd->arch.lastinc - now;
+	} else {
+		/* we have an overflow ... */
+		gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now;
+	}
+	gd->arch.lastinc = now;
+
+	return gd->arch.tbl;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
+
+/*
+ * reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu(ulong ignored)
+{
+	struct s3c24x0_watchdog *watchdog;
+
+	watchdog = s3c24x0_get_base_watchdog();
+
+	/* Disable watchdog */
+	writel(0x0000, &watchdog->wtcon);
+
+	/* Initialize watchdog timer count register */
+	writel(0x0001, &watchdog->wtcnt);
+
+	/* Enable watchdog timer; assert reset at timer timeout */
+	writel(0x0021, &watchdog->wtcon);
+
+	while (1)
+		/* loop forever and wait for reset to happen */;
+
+	/*NOTREACHED*/
+}
+
+#endif /* CONFIG_S3C24X0 */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm920t/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm920t/start.S
new file mode 100644
index 000000000..7bf094aec
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm920t/start.S
@@ -0,0 +1,361 @@
+/*
+ *  armboot - Startup Code for ARM920 CPU-core
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <common.h>
+#include <config.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:	b	start_code
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:	.word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+
+	.balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (called from the ARM reset exception vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual start code
+ */
+
+start_code:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0, cpsr
+	bic	r0, r0, #0x1f
+	orr	r0, r0, #0xd3
+	msr	cpsr, r0
+
+#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
+	/*
+	 * relocate exception table
+	 */
+	ldr	r0, =_start
+	ldr	r1, =0x0
+	mov	r2, #16
+copyex:
+	subs	r2, r2, #1
+	ldr	r3, [r0], #4
+	str	r3, [r1], #4
+	bne	copyex
+#endif
+
+#ifdef CONFIG_S3C24X0
+	/* turn off the watchdog */
+
+# if defined(CONFIG_S3C2400)
+#  define pWTCON	0x15300000
+#  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
+#  define CLKDIVN	0x14800014	/* clock divisor register */
+#else
+#  define pWTCON	0x53000000
+#  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
+#  define INTSUBMSK	0x4A00001C
+#  define CLKDIVN	0x4C000014	/* clock divisor register */
+# endif
+
+	ldr	r0, =pWTCON
+	mov	r1, #0x0
+	str	r1, [r0]
+
+	/*
+	 * mask all IRQs by setting all bits in the INTMR - default
+	 */
+	mov	r1, #0xffffffff
+	ldr	r0, =INTMSK
+	str	r1, [r0]
+# if defined(CONFIG_S3C2410)
+	ldr	r1, =0x3ff
+	ldr	r0, =INTSUBMSK
+	str	r1, [r0]
+# endif
+
+	/* FCLK:HCLK:PCLK = 1:2:4 */
+	/* default FCLK is 120 MHz ! */
+	ldr	r0, =CLKDIVN
+	mov	r1, #3
+	str	r1, [r0]
+#endif	/* CONFIG_S3C24X0 */
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+	mov	pc, lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * before relocating, we have to setup RAM timing
+	 * because memory timing is board-dependend, you will
+	 * find a lowlevel_init.S in your board directory.
+	 */
+	mov	ip, lr
+
+	bl	lowlevel_init
+
+	mov	lr, ip
+	mov	pc, lr
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC	0x13
+#define I_BIT		0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	ldr	r2, IRQ_STACK_START_IN
+	ldmia	r2, {r2 - r3}			@ get pc, cpsr
+	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r7, sp, #S_PC
+	stmdb	r7, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r7, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r7, #4]			@ Save CPSR
+	str	r0, [r7, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	/* return & move spsr_svc into cpsr */
+	subs	pc, lr, #4
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+
+	str	lr, [r13]			@ save caller lr / spsr
+	mrs	lr, spsr
+	str	lr, [r13, #4]
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13
+	mov	lr, pc
+	movs	pc, lr
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align  5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/Makefile
new file mode 100644
index 000000000..125299537
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+obj-y	= cpu.o cache.o
+
+ifdef	CONFIG_SPL_BUILD
+ifdef	CONFIG_SPL_NO_CPU_SUPPORT_CODE
+extra-y	:=
+endif
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/Makefile
new file mode 100644
index 000000000..fca98ef42
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= cpu.o timer.o dram.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/cpu.c
new file mode 100644
index 000000000..8b02d0be0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/cpu.c
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada100.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID	(1<<8)
+#define L2C_RAM_SEL	(1<<4)
+
+int arch_cpu_init(void)
+{
+	u32 val;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+
+	/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
+	val = readl(&cpuregs->cpu_conf);
+	val = val | SET_MRVL_ID;
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable Clocks for all hardware units */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on AIB and AIB-APB Functional clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
+
+	/* ensure L2 cache is not mapped as SRAM */
+	val = readl(&cpuregs->cpu_conf);
+	val = val & ~(L2C_RAM_SEL);
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK, &apb1clkres->gpio);
+
+#ifdef CONFIG_I2C_MV
+	/* Enable general I2C clock */
+	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+
+	/* Enable power I2C clock */
+	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+#endif
+
+	/*
+	 * Enable Functional and APB clock at 14.7456MHz
+	 * for configured UART console
+	 */
+#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart3);
+#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart2);
+#else
+	writel(UARTCLK14745KHZ, &apb1clkres->uart1);
+#endif
+	icache_enable();
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 id;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/dram.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/dram.c
new file mode 100644
index 000000000..8d7c71ff6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/dram.c
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * ARMADA100 DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet Appendix A.17
+ */
+struct armd1ddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+	u32	pad[3];
+};
+
+struct armd1ddr_registers {
+	u8	pad[0x100 - 0x000];
+	struct armd1ddr_map_registers mmap[2];
+};
+
+/*
+ * armd1_sdram_base - reads SDRAM Base Address Register
+ */
+u32 armd1_sdram_base(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * armd1_sdram_size - reads SDRAM size
+ */
+u32 armd1_sdram_size(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return ((0x8 << (result - 0x7)) * 1024 * 1024);
+	}
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = armd1_sdram_base(i);
+		gd->bd->bi_dram[i].size = armd1_sdram_size(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/timer.c
new file mode 100644
index 000000000..bbd0505bd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada100.h>
+
+/*
+ * Timer registers
+ * Refer Section A.6 in Datasheet
+ */
+struct armd1tmr_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr;
+};
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
+
+/* For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	volatile int loop=100;
+
+	writel(COUNT_RD_REQ, &armd1timers->cvwr);
+	while (loop--);
+	return(readl(&armd1timers->cvwr));
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->arch.tbl) {
+		/* normal mode */
+		gd->arch.tbu += now - gd->arch.tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
+	}
+	gd->arch.tbl = now;
+
+	return gd->arch.tbu;
+}
+
+ulong get_timer(ulong base)
+{
+	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+		base);
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime);
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+
+	/* Enable Timer clock at 3.25 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &armd1timers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &armd1timers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x1, &armd1timers->preload_ctrl[TIMER]);
+
+	/* Enable timer 0 */
+	writel(0x1, &armd1timers->cer);
+	/* init the gd->arch.tbu and gd->arch.tbl value */
+	gd->arch.tbl = read_timer();
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+#define MPMU_APRR_WDTR	(1<<4)
+#define TMR_WFAR	0xbaba	/* WDT Register First key */
+#define TMP_WSAR	0xeb10	/* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	u32 val;
+
+	/* negate hardware reset to the WDT after system reset */
+	val = readl(&mpmu->aprr);
+	val = val | MPMU_APRR_WDTR;
+	writel(val, &mpmu->aprr);
+
+	/* reset/enable WDT clock */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+
+	/* clear previous WDT status */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0, &armd1timers->wdt_sts);
+
+	/* set match counter */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0xf, &armd1timers->wdt_match_r);
+
+	/* enable WDT reset */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0x3, &armd1timers->wdt_match_en);
+
+	while(1);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/Makefile
new file mode 100644
index 000000000..698a28dc5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/Makefile
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AT91CAP9)	+= at91cap9_devices.o
+obj-$(CONFIG_AT91SAM9260)	+= at91sam9260_devices.o
+obj-$(CONFIG_AT91SAM9G20)	+= at91sam9260_devices.o
+obj-$(CONFIG_AT91SAM9XE)	+= at91sam9260_devices.o
+obj-$(CONFIG_AT91SAM9261)	+= at91sam9261_devices.o
+obj-$(CONFIG_AT91SAM9G10)	+= at91sam9261_devices.o
+obj-$(CONFIG_AT91SAM9263)	+= at91sam9263_devices.o
+obj-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
+obj-$(CONFIG_AT91SAM9M10G45)	+= at91sam9m10g45_devices.o
+obj-$(CONFIG_AT91SAM9G45)	+= at91sam9m10g45_devices.o
+obj-$(CONFIG_AT91SAM9N12)	+= at91sam9n12_devices.o
+obj-$(CONFIG_AT91SAM9X5)	+= at91sam9x5_devices.o
+obj-$(CONFIG_AT91_EFLASH)	+= eflash.o
+obj-$(CONFIG_AT91_LED)	+= led.o
+obj-y += clock.o
+obj-y += cpu.o
+obj-y	+= reset.o
+obj-y	+= timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+obj-y	+= lowlevel_init.o
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
new file mode 100644
index 000000000..16eeca737
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void at91_serial0_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 23, 0);		/* RXD0 */
+	writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
+	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);		/* RXD1 */
+	writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
+	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);		/* RXD2 */
+	writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
+}
+
+void at91_serial3_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);		/* DRXD */
+	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
+	writel(1 << AT91_ID_SYS, &pmc->pcer);
+}
+
+void at91_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	at91_serial0_hw_init();
+#endif
+
+#ifdef CONFIG_USART1
+	at91_serial1_hw_init();
+#endif
+
+#ifdef CONFIG_USART2
+	at91_serial2_hw_init();
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	at91_serial3_hw_init();
+#endif
+}
+
+#ifdef CONFIG_HAS_DATAFLASH
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_b_periph(AT91_PIO_PORTA, 0, 0);	/* SPI0_MISO */
+	at91_set_b_periph(AT91_PIO_PORTA, 1, 0);	/* SPI0_MOSI */
+	at91_set_b_periph(AT91_PIO_PORTA, 2, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
+	}
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* SPI1_MISO */
+	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* SPI1_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_SPCK */
+
+	/* Enable clock */
+	writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
+	}
+
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTB, 21, 0);	/* ETXCK_EREFCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 22, 0);	/* ERXDV */
+	at91_set_a_periph(AT91_PIO_PORTB, 25, 0);	/* ERX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 26, 0);	/* ERX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 27, 0);	/* ERXER */
+	at91_set_a_periph(AT91_PIO_PORTB, 28, 0);	/* ETXEN */
+	at91_set_a_periph(AT91_PIO_PORTB, 23, 0);	/* ETX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 24, 0);	/* ETX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* EMDIO */
+	at91_set_a_periph(AT91_PIO_PORTB, 29, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_b_periph(AT91_PIO_PORTC, 25, 0);	/* ECRS */
+	at91_set_b_periph(AT91_PIO_PORTC, 26, 0);	/* ECOL */
+	at91_set_b_periph(AT91_PIO_PORTC, 22, 0);	/* ERX2 */
+	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);	/* ERX3 */
+	at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ERXCK */
+	at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ETX2 */
+	at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ETX3 */
+	at91_set_b_periph(AT91_PIO_PORTC, 24, 0);	/* ETXER */
+#endif
+}
+#endif
+
+#ifdef CONFIG_AT91_CAN
+void at91_can_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* CAN_TX */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);	/* CAN_RX */
+
+	/* Enable clock */
+	writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
new file mode 100644
index 000000000..cae4abcdf
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
+
+void at91_serial0_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 5, PUP);		/* RXD0 */
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 6, 1);		/* TXD1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 7, PUP);		/* RXD1 */
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 8, 1);		/* TXD2 */
+	at91_set_a_periph(AT91_PIO_PORTB, 9, PUP);		/* RXD2 */
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);		/* DRXD */
+	at91_set_a_periph(AT91_PIO_PORTB, 15, 1);		/* DTXD */
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
+	}
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 0, PUP);	/* SPI1_MISO */
+	at91_set_a_periph(AT91_PIO_PORTB, 1, PUP);	/* SPI1_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTB, 2, PUP);	/* SPI1_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+	}
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	/* Enable EMAC clock */
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
+	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* ETXCK_EREFCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ERXDV */
+	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ERX0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERX1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* ERXER */
+	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ETXEN */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ETX0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ETX1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* EMDIO */
+	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ECRS */
+	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECOL */
+	at91_set_b_periph(AT91_PIO_PORTA, 25, 0);	/* ERX2 */
+	at91_set_b_periph(AT91_PIO_PORTA, 26, 0);	/* ERX3 */
+	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ERXCK */
+#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
+	/*
+	 * use PA10, PA11 for ETX2, ETX3.
+	 * PA23 and PA24 are for TWI EEPROM
+	 */
+	at91_set_b_periph(AT91_PIO_PORTA, 10, 0);	/* ETX2 */
+	at91_set_b_periph(AT91_PIO_PORTA, 11, 0);	/* ETX3 */
+#else
+	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* ETX2 */
+	at91_set_b_periph(AT91_PIO_PORTA, 24, 0);	/* ETX3 */
+#if defined(CONFIG_AT91SAM9G20)
+	/* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
+	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
+	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
+#endif
+#endif
+	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* ETXER */
+#endif
+}
+#endif
+
+#if defined(CONFIG_GENERIC_ATMEL_MCI)
+void at91_mci_hw_init(void)
+{
+	/* Enable mci clock */
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	writel(1 << ATMEL_ID_MCI, &pmc->pcer);
+
+	at91_set_a_periph(AT91_PIO_PORTA, 8, 1);	/* MCCK */
+#if defined(CONFIG_ATMEL_MCI_PORTB)
+	at91_set_b_periph(AT91_PIO_PORTA, 1, 1);	/* MCCDB */
+	at91_set_b_periph(AT91_PIO_PORTA, 0, 1);	/* MCDB0 */
+	at91_set_b_periph(AT91_PIO_PORTA, 5, 1);	/* MCDB1 */
+	at91_set_b_periph(AT91_PIO_PORTA, 4, 1);	/* MCDB2 */
+	at91_set_b_periph(AT91_PIO_PORTA, 3, 1);	/* MCDB3 */
+#else
+	at91_set_a_periph(AT91_PIO_PORTA, 7, 1);	/* MCCDA */
+	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);	/* MCDA0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 9, 1);	/* MCDA1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);	/* MCDA2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);	/* MCDA3 */
+#endif
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
new file mode 100644
index 000000000..a445c7507
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
+
+void at91_serial0_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 1);		/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);		/* RXD0 */
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 12, 1);		/* TXD1 */
+	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);		/* RXD1 */
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 1);		/* TXD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);		/* RXD2 */
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
+	}
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 30, PUP);	/* SPI1_MISO */
+	at91_set_a_periph(AT91_PIO_PORTB, 31, PUP);	/* SPI1_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTB, 29, PUP);	/* SPI1_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
+	}
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
new file mode 100644
index 000000000..6b51d5f35
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009-2011
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
+
+void at91_serial0_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);		/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, PUP);		/* RXD0 */
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
+	at91_set_a_periph(AT91_PIO_PORTD, 1, PUP);		/* RXD1 */
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
+	at91_set_a_periph(AT91_PIO_PORTD, 3, PUP);		/* RXD2 */
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 30, PUP);		/* DRXD */
+	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_b_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
+	at91_set_b_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
+	at91_set_b_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
+	}
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 12, PUP);	/* SPI1_MISO */
+	at91_set_a_periph(AT91_PIO_PORTB, 13, PUP);	/* SPI1_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);	/* SPI1_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
+	}
+}
+#endif
+
+#if defined(CONFIG_GENERIC_ATMEL_MCI)
+void at91_mci_hw_init(void)
+{
+	/* Enable mci clock */
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
+
+	at91_set_a_periph(AT91_PIO_PORTA, 6, PUP);	/* MCI1_CK */
+
+#if defined(CONFIG_ATMEL_MCI_PORTB)
+	at91_set_a_periph(AT91_PIO_PORTA, 21, PUP);	/* MCI1_CDB */
+	at91_set_a_periph(AT91_PIO_PORTA, 22, PUP);	/* MCI1_DB0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 23, PUP);	/* MCI1_DB1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 24, PUP);	/* MCI1_DB2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 25, PUP);	/* MCI1_DB3 */
+#else
+	at91_set_a_periph(AT91_PIO_PORTA, 7, PUP);	/* MCI1_CDA */
+	at91_set_a_periph(AT91_PIO_PORTA, 8, PUP);	/* MCI1_DA0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 9, PUP);	/* MCI1_DA1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, PUP);	/* MCI1_DA2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 11, PUP);	/* MCI1_DA3 */
+#endif
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTE, 21, 0);	/* ETXCK_EREFCK */
+	at91_set_b_periph(AT91_PIO_PORTC, 25, 0);	/* ERXDV */
+	at91_set_a_periph(AT91_PIO_PORTE, 25, 0);	/* ERX0 */
+	at91_set_a_periph(AT91_PIO_PORTE, 26, 0);	/* ERX1 */
+	at91_set_a_periph(AT91_PIO_PORTE, 27, 0);	/* ERXER */
+	at91_set_a_periph(AT91_PIO_PORTE, 28, 0);	/* ETXEN */
+	at91_set_a_periph(AT91_PIO_PORTE, 23, 0);	/* ETX0 */
+	at91_set_a_periph(AT91_PIO_PORTE, 24, 0);	/* ETX1 */
+	at91_set_a_periph(AT91_PIO_PORTE, 30, 0);	/* EMDIO */
+	at91_set_a_periph(AT91_PIO_PORTE, 29, 0);	/* EMDC */
+
+#ifndef CONFIG_RMII
+	at91_set_a_periph(AT91_PIO_PORTE, 22, 0);	/* ECRS */
+	at91_set_b_periph(AT91_PIO_PORTC, 26, 0);	/* ECOL */
+	at91_set_b_periph(AT91_PIO_PORTC, 22, 0);	/* ERX2 */
+	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);	/* ERX3 */
+	at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ERXCK */
+	at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ETX2 */
+	at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ETX3 */
+	at91_set_b_periph(AT91_PIO_PORTC, 24, 0);	/* ETXER */
+#endif
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_NEW
+void at91_uhp_hw_init(void)
+{
+	/* Enable VBus on UHP ports */
+	at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
+	at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
+}
+#endif
+
+#ifdef CONFIG_AT91_CAN
+void at91_can_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* CAN_TX */
+	at91_set_a_periph(AT91_PIO_PORTA, 14, 1);	/* CAN_RX */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_CAN, &pmc->pcer);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
new file mode 100644
index 000000000..7d7725c4b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
+
+void at91_serial0_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 19, 1);	/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 18, PUP);	/* RXD0 */
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 5, PUP);		/* RXD1 */
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);		/* TXD2 */
+	at91_set_a_periph(AT91_PIO_PORTD, 7, PUP);		/* RXD2 */
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* DRXD */
+	at91_set_a_periph(AT91_PIO_PORTB, 13, 1);	/* DTXD */
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 0, PUP);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTB, 1, PUP);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTB, 2, PUP);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_b_periph(AT91_PIO_PORTB, 18, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_b_periph(AT91_PIO_PORTB, 19, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_b_periph(AT91_PIO_PORTD, 27, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 19, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTD, 27, 1);
+	}
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);	/* SPI1_MISO */
+	at91_set_a_periph(AT91_PIO_PORTB, 15, PUP);	/* SPI1_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTB, 16, PUP);	/* SPI1_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_b_periph(AT91_PIO_PORTD, 28, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_a_periph(AT91_PIO_PORTD, 18, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_a_periph(AT91_PIO_PORTD, 19, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTD, 28, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTD, 18, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTD, 19, 1);
+	}
+
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ETXCK_EREFCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERXDV */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ERX0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ERX1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ERXER */
+	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ETXEN */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* ETX0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* ETX1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* EMDIO */
+	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* EMDC */
+#ifndef CONFIG_RMII
+	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECRS */
+	at91_set_b_periph(AT91_PIO_PORTA, 30, 0);	/* ECOL */
+	at91_set_b_periph(AT91_PIO_PORTA, 8,  0);	/* ERX2 */
+	at91_set_b_periph(AT91_PIO_PORTA, 9,  0);	/* ERX3 */
+	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ERXCK */
+	at91_set_b_periph(AT91_PIO_PORTA, 6,  0);	/* ETX2 */
+	at91_set_b_periph(AT91_PIO_PORTA, 7,  0);	/* ETX3 */
+	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ETXER */
+#endif
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
new file mode 100644
index 000000000..39f17a1e1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2013 Atmel Corporation
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+
+unsigned int has_lcdc()
+{
+	return 1;
+}
+
+void at91_serial0_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 0, 1);		/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);		/* RXD0 */
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 5, 1);		/* TXD1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 6, 0);		/* RXD1 */
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 7, 1);		/* TXD2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 8, 0);		/* RXD2 */
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_serial3_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_b_periph(AT91_PIO_PORTC, 22, 1);		/* TXD3 */
+	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);		/* RXD3 */
+	writel(1 << ATMEL_ID_USART3, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
+	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+	if (cs_mask & (1 << 0))
+		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+	if (cs_mask & (1 << 1))
+		at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+	if (cs_mask & (1 << 2))
+		at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
+	if (cs_mask & (1 << 3))
+		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_b_periph(AT91_PIO_PORTA, 21, 0);	/* SPI1_MISO */
+	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* SPI1_MOSI */
+	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* SPI1_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+	if (cs_mask & (1 << 0))
+		at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
+	if (cs_mask & (1 << 1))
+		at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
+	if (cs_mask & (1 << 2))
+		at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
+	if (cs_mask & (1 << 3))
+		at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
+}
+#endif
+
+void at91_mci_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* MCCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* MCCDA */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* MCDA0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* MCDA1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* MCDA2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* MCDA3 */
+
+	writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+}
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDPWR */
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDEN */
+	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDDOTCK */
+
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDD0 */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDD1 */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD8 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD9 */
+	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD12 */
+	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD15 */
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD16 */
+	at91_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD17 */
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDD20 */
+	at91_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
+
+	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
new file mode 100644
index 000000000..0ec32c3ab
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+/*
+ * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
+ * peripheral pins. Good to have if hardware is soldered optionally
+ * or in case of SPI no slave is selected. Avoid lines to float
+ * needlessly. Use a short local PUP define.
+ *
+ * Due to errata "TXD floats when CTS is inactive" pullups are always
+ * on for TXD pins.
+ */
+#ifdef CONFIG_AT91_GPIO_PULLUP
+# define PUP CONFIG_AT91_GPIO_PULLUP
+#else
+# define PUP 0
+#endif
+
+void at91_serial0_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);		/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 7, PUP);		/* RXD0 */
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);		/* TXD1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, PUP);		/* RXD1 */
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);		/* TXD2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 14, PUP);		/* RXD2 */
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 21, PUP);		/* DRXD */
+	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* DTXD */
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 25, PUP);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTA, 26, PUP);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, PUP);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI, &pmc->pcer);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_b_periph(AT91_PIO_PORTB, 7, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_b_periph(AT91_PIO_PORTD, 9, 1);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_pio_output(AT91_PIO_PORTA, 28, 1);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_pio_output(AT91_PIO_PORTB, 7, 1);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_pio_output(AT91_PIO_PORTD, 8, 1);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_pio_output(AT91_PIO_PORTD, 9, 1);
+	}
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
new file mode 100644
index 000000000..6d9457223
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+unsigned int get_chip_id(void)
+{
+	/* The 0x40 is the offset of cidr in DBGU */
+	return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+	/* The 0x44 is the offset of exid in DBGU */
+	return readl(ATMEL_BASE_DBGU + 0x44);
+}
+
+unsigned int has_emac1()
+{
+	return cpu_is_at91sam9x25();
+}
+
+unsigned int has_emac0()
+{
+	return !(cpu_is_at91sam9g15());
+}
+
+unsigned int has_lcdc()
+{
+	return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()
+		|| cpu_is_at91sam9x35();
+}
+
+char *get_cpu_name()
+{
+	unsigned int extension_id = get_extension_chip_id();
+
+	if (cpu_is_at91sam9x5()) {
+		switch (extension_id) {
+		case ARCH_EXID_AT91SAM9G15:
+			return "AT91SAM9G15";
+		case ARCH_EXID_AT91SAM9G25:
+			return "AT91SAM9G25";
+		case ARCH_EXID_AT91SAM9G35:
+			return "AT91SAM9G35";
+		case ARCH_EXID_AT91SAM9X25:
+			return "AT91SAM9X25";
+		case ARCH_EXID_AT91SAM9X35:
+			return "AT91SAM9X35";
+		default:
+			return "Unknown CPU type";
+		}
+	} else {
+		return "Unknown CPU type";
+	}
+}
+
+void at91_seriald_hw_init(void)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);	/* DRXD */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);	/* DTXD */
+
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+void at91_serial0_hw_init(void)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 0, 1);	/* TXD */
+	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* RXD */
+
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 5, 1);	/* TXD */
+	at91_set_a_periph(AT91_PIO_PORTA, 6, 0);	/* RXD */
+
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 7, 1);	/* TXD */
+	at91_set_a_periph(AT91_PIO_PORTA, 8, 0);	/* RXD */
+
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_mci_hw_init(void)
+{
+	/* Initialize the MCI0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 17, 1);	/* MCCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 16, 1);	/* MCCDA */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 1);	/* MCDA0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 18, 1);	/* MCDA1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 19, 1);	/* MCDA2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 20, 1);	/* MCDA3 */
+
+	/* Enable clock for MCI0 */
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+	if (cs_mask & (1 << 0))
+		at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
+	if (cs_mask & (1 << 1))
+		at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
+	if (cs_mask & (1 << 2))
+		at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
+	if (cs_mask & (1 << 3))
+		at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
+	if (cs_mask & (1 << 4))
+		at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
+	if (cs_mask & (1 << 5))
+		at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
+	if (cs_mask & (1 << 6))
+		at91_set_pio_output(AT91_PIO_PORTA, 1, 0);
+	if (cs_mask & (1 << 7))
+		at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	at91_set_b_periph(AT91_PIO_PORTA, 21, 0);	/* SPI1_MISO */
+	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* SPI1_MOSI */
+	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* SPI1_SPCK */
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+	if (cs_mask & (1 << 0))
+		at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
+	if (cs_mask & (1 << 1))
+		at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
+	if (cs_mask & (1 << 2))
+		at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
+	if (cs_mask & (1 << 3))
+		at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
+	if (cs_mask & (1 << 4))
+		at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
+	if (cs_mask & (1 << 5))
+		at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
+	if (cs_mask & (1 << 6))
+		at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
+	if (cs_mask & (1 << 7))
+		at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
+}
+#endif
+
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+void at91_uhp_hw_init(void)
+{
+	/* Enable VBus on UHP ports */
+	at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */
+	at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */
+#if defined(CONFIG_USB_OHCI_NEW)
+	/* port C is OHCI only */
+	at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */
+#endif
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+	if (has_emac0()) {
+		/* Enable EMAC0 clock */
+		writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+		/* EMAC0 pins setup */
+		at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* ETXCK */
+		at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* ERXDV */
+		at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ERX0 */
+		at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* ERX1 */
+		at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ERXER */
+		at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ETXEN */
+		at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ETX0 */
+		at91_set_a_periph(AT91_PIO_PORTB, 10, 0);	/* ETX1 */
+		at91_set_a_periph(AT91_PIO_PORTB, 5, 0);	/* EMDIO */
+		at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* EMDC */
+	}
+
+	if (has_emac1()) {
+		/* Enable EMAC1 clock */
+		writel(1 << ATMEL_ID_EMAC1, &pmc->pcer);
+		/* EMAC1 pins setup */
+		at91_set_b_periph(AT91_PIO_PORTC, 29, 0);	/* ETXCK */
+		at91_set_b_periph(AT91_PIO_PORTC, 28, 0);	/* ECRSDV */
+		at91_set_b_periph(AT91_PIO_PORTC, 20, 0);	/* ERXO */
+		at91_set_b_periph(AT91_PIO_PORTC, 21, 0);	/* ERX1 */
+		at91_set_b_periph(AT91_PIO_PORTC, 16, 0);	/* ERXER */
+		at91_set_b_periph(AT91_PIO_PORTC, 27, 0);	/* ETXEN */
+		at91_set_b_periph(AT91_PIO_PORTC, 18, 0);	/* ETX0 */
+		at91_set_b_periph(AT91_PIO_PORTC, 19, 0);	/* ETX1 */
+		at91_set_b_periph(AT91_PIO_PORTC, 31, 0);	/* EMDIO */
+		at91_set_b_periph(AT91_PIO_PORTC, 30, 0);	/* EMDC */
+	}
+
+#ifndef CONFIG_RMII
+	/* Only emac0 support MII */
+	if (has_emac0()) {
+		at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* ECRS */
+		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* ECOL */
+		at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ERX2 */
+		at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* ERX3 */
+		at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* ERXCK */
+		at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* ETX2 */
+		at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX3 */
+		at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ETXER */
+	}
+#endif
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/clock.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/clock.c
new file mode 100644
index 000000000..31315b58e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -0,0 +1,189 @@
+/*
+ * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
+ *
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned long at91_css_to_rate(unsigned long css)
+{
+	switch (css) {
+	case AT91_PMC_MCKR_CSS_SLOW:
+		return CONFIG_SYS_AT91_SLOW_CLOCK;
+	case AT91_PMC_MCKR_CSS_MAIN:
+		return gd->arch.main_clk_rate_hz;
+	case AT91_PMC_MCKR_CSS_PLLA:
+		return gd->arch.plla_rate_hz;
+	case AT91_PMC_MCKR_CSS_PLLB:
+		return gd->arch.pllb_rate_hz;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_ATMEL
+static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
+{
+	unsigned i, div = 0, mul = 0, diff = 1 << 30;
+	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
+
+	/* PLL output max 240 MHz (or 180 MHz per errata) */
+	if (out_freq > 240000000)
+		goto fail;
+
+	for (i = 1; i < 256; i++) {
+		int diff1;
+		unsigned input, mul1;
+
+		/*
+		 * PLL input between 1MHz and 32MHz per spec, but lower
+		 * frequences seem necessary in some cases so allow 100K.
+		 * Warning: some newer products need 2MHz min.
+		 */
+		input = main_freq / i;
+#if defined(CONFIG_AT91SAM9G20)
+		if (input < 2000000)
+			continue;
+#endif
+		if (input < 100000)
+			continue;
+		if (input > 32000000)
+			continue;
+
+		mul1 = out_freq / input;
+#if defined(CONFIG_AT91SAM9G20)
+		if (mul > 63)
+			continue;
+#endif
+		if (mul1 > 2048)
+			continue;
+		if (mul1 < 2)
+			goto fail;
+
+		diff1 = out_freq - input * mul1;
+		if (diff1 < 0)
+			diff1 = -diff1;
+		if (diff > diff1) {
+			diff = diff1;
+			div = i;
+			mul = mul1;
+			if (diff == 0)
+				break;
+		}
+	}
+	if (i == 256 && diff > (out_freq >> 5))
+		goto fail;
+	return ret | ((mul - 1) << 16) | div;
+fail:
+	return 0;
+}
+#endif
+
+static u32 at91_pll_rate(u32 freq, u32 reg)
+{
+	unsigned mul, div;
+
+	div = reg & 0xff;
+	mul = (reg >> 16) & 0x7ff;
+	if (div && mul) {
+		freq /= div;
+		freq *= mul + 1;
+	} else
+		freq = 0;
+
+	return freq;
+}
+
+int at91_clock_init(unsigned long main_clock)
+{
+	unsigned freq, mckr;
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+	unsigned tmp;
+	/*
+	 * When the bootloader initialized the main oscillator correctly,
+	 * there's no problem using the cycle counter.  But if it didn't,
+	 * or when using oscillator bypass mode, we must be told the speed
+	 * of the main clock.
+	 */
+	if (!main_clock) {
+		do {
+			tmp = readl(&pmc->mcfr);
+		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
+		tmp &= AT91_PMC_MCFR_MAINF_MASK;
+		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+	}
+#endif
+	gd->arch.main_clk_rate_hz = main_clock;
+
+	/* report if PLLA is more than mildly overclocked */
+	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+
+#ifdef CONFIG_USB_ATMEL
+	/*
+	 * USB clock init:  choose 48 MHz PLLB value,
+	 * disable 48MHz clock during usb peripheral suspend.
+	 *
+	 * REVISIT:  assumes MCK doesn't derive from PLLB!
+	 */
+	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+			     AT91_PMC_PLLBR_USBDIV_2;
+	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+					      gd->arch.at91_pllb_usb_init);
+#endif
+
+	/*
+	 * MCK and CPU derive from one of those primary clocks.
+	 * For now, assume this parentage won't change.
+	 */
+	mckr = readl(&pmc->mckr);
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
+		|| defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
+	/* plla divisor by 2 */
+	gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+#endif
+	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+	freq = gd->arch.mck_rate_hz;
+
+	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
+#if defined(CONFIG_AT91SAM9G20)
+	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
+	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+		freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
+	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
+		freq /= 2;			/* processor clock division */
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
+		|| defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
+	/* mdiv <==> divisor
+	 *  0   <==>   1
+	 *  1   <==>   2
+	 *  2   <==>   4
+	 *  3   <==>   3
+	 */
+	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+		(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
+		? freq / 3
+		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+#else
+	gd->arch.mck_rate_hz = freq /
+			(1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+#endif
+	gd->arch.cpu_clk_rate_hz = freq;
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/config.mk b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/config.mk
new file mode 100644
index 000000000..370630d4d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/config.mk
@@ -0,0 +1,2 @@
+PF_CPPFLAGS_TUNE := $(call cc-option,-mtune=arm926ejs,)
+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_TUNE)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/cpu.c
new file mode 100644
index 000000000..da1d35907
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/cpu.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
+#include <asm/arch/clk.h>
+
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#endif
+
+int arch_cpu_init(void)
+{
+	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+}
+
+void arch_preboot_os(void)
+{
+	ulong cpiv;
+	at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
+
+	cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+	/*
+	 * Disable PITC
+	 * Add 0x1000 to current counter to stop it faster
+	 * without waiting for wrapping back to 0
+	 */
+	writel(cpiv + 0x1000, &pit->mr);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char buf[32];
+
+	printf("CPU: %s\n", ATMEL_CPU_NAME);
+	printf("Crystal frequency: %8s MHz\n",
+					strmhz(buf, get_main_clk_rate()));
+	printf("CPU clock        : %8s MHz\n",
+					strmhz(buf, get_cpu_clk_rate()));
+	printf("Master clock     : %8s MHz\n",
+					strmhz(buf, get_mck_clk_rate()));
+
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/eflash.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/eflash.c
new file mode 100644
index 000000000..3f3926428
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/eflash.c
@@ -0,0 +1,254 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * this driver supports the enhanced embedded flash in the Atmel
+ * AT91SAM9XE devices with the following geometry:
+ *
+ * AT91SAM9XE128: 1 plane of  8 regions of 32 pages (total  256 pages)
+ * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total  512 pages)
+ * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages)
+ * (the exact geometry is read from the flash at runtime, so any
+ *  future devices should already be covered)
+ *
+ * Regions can be write/erase protected.
+ * Whole (!) pages can be individually written with erase on the fly.
+ * Writing partial pages will corrupt the rest of the page.
+ *
+ * The flash is presented to u-boot with each region being a sector,
+ * having the following effects:
+ * Each sector can be hardware protected (protect on/off).
+ * Each page in a sector can be rewritten anytime.
+ * Since pages are erased when written, the "erase" does nothing.
+ * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected
+ * by u-Boot commands.
+ *
+ * Note: Redundant environment will not work in this flash since
+ * it does use partial page writes. Make sure the environment spans
+ * whole pages!
+ */
+
+/*
+ * optional TODOs (nice to have features):
+ *
+ * make the driver coexist with other NOR flash drivers
+ *	(use an index into flash_info[], requires work
+ *	in those other drivers, too)
+ * Make the erase command fill the sectors with 0xff
+ *	(if the flashes grow larger in the future and
+ *	someone puts a jffs2 into them)
+ * do a read-modify-write for partially programmed pages
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_eefc.h>
+#include <asm/arch/at91_dbu.h>
+
+/* checks to detect configuration errors */
+#if CONFIG_SYS_MAX_FLASH_BANKS!=1
+#error eflash: this driver can only handle 1 bank
+#endif
+
+/* global structure */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static u32 pagesize;
+
+unsigned long flash_init (void)
+{
+	at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
+	at91_dbu_t *dbu = (at91_dbu_t *) ATMEL_BASE_DBGU;
+	u32 id, size, nplanes, planesize, nlocks;
+	u32 addr, i, tmp=0;
+
+	debug("eflash: init\n");
+
+	flash_info[0].flash_id = FLASH_UNKNOWN;
+
+	/* check if its an AT91ARM9XE SoC */
+	if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) {
+		puts("eflash: not an AT91SAM9XE\n");
+		return 0;
+	}
+
+	/* now query the eflash for its structure */
+	writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr);
+	while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
+		;
+	id = readl(&eefc->frr);		/* word 0 */
+	size = readl(&eefc->frr);	/* word 1 */
+	pagesize = readl(&eefc->frr);	/* word 2 */
+	nplanes = readl(&eefc->frr);	/* word 3 */
+	planesize = readl(&eefc->frr);	/* word 4 */
+	debug("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n",
+		id, size, pagesize, nplanes, planesize);
+	for (i=1; i<nplanes; i++) {
+		tmp = readl(&eefc->frr);	/* words 5..4+nplanes-1 */
+	};
+	nlocks = readl(&eefc->frr);	/* word 4+nplanes */
+	debug("nlocks=%u\n", nlocks);
+	/* since we are going to use the lock regions as sectors, check count */
+	if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) {
+		printf("eflash: number of lock regions(%u) "\
+			"> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n",
+			nlocks);
+		nlocks = CONFIG_SYS_MAX_FLASH_SECT;
+	}
+	flash_info[0].size = size;
+	flash_info[0].sector_count = nlocks;
+	flash_info[0].flash_id = id;
+
+	addr = ATMEL_BASE_FLASH;
+	for (i=0; i<nlocks; i++) {
+		tmp = readl(&eefc->frr);	/* words 4+nplanes+1.. */
+		flash_info[0].start[i] = addr;
+		flash_info[0].protect[i] = 0;
+		addr += tmp;
+	};
+
+	/* now read the protection information for all regions */
+	writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr);
+	while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
+		;
+	for (i=0; i<flash_info[0].sector_count; i++) {
+		if (i%32 == 0)
+			tmp = readl(&eefc->frr);
+		flash_info[0].protect[i] = (tmp >> (i%32)) & 1;
+#if defined(CONFIG_EFLASH_PROTSECTORS)
+		if (i < CONFIG_EFLASH_PROTSECTORS)
+			flash_info[0].protect[i] = 1;
+#endif
+	}
+
+	return size;
+}
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	puts("AT91SAM9XE embedded flash\n  Size: ");
+	print_size(info->size, " in ");
+	printf("%d Sectors\n", info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+int flash_real_protect (flash_info_t *info, long sector, int prot)
+{
+	at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
+	u32 pagenum = (info->start[sector]-ATMEL_BASE_FLASH)/pagesize;
+	u32 i, tmp=0;
+
+	debug("protect sector=%ld prot=%d\n", sector, prot);
+
+#if defined(CONFIG_EFLASH_PROTSECTORS)
+	if (sector < CONFIG_EFLASH_PROTSECTORS) {
+		if (!prot) {
+			printf("eflash: sector %lu cannot be unprotected\n",
+				sector);
+		}
+		return 1; /* return anyway, caller does not care for result */
+	}
+#endif
+	if (prot) {
+		writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB |
+			(pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
+	} else {
+		writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB |
+			(pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
+	}
+	while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
+		;
+	/* now re-read the protection information for all regions */
+	writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr);
+	while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
+		;
+	for (i=0; i<info->sector_count; i++) {
+		if (i%32 == 0)
+			tmp = readl(&eefc->frr);
+		info->protect[i] = (tmp >> (i%32)) & 1;
+	}
+	return 0;
+}
+
+static u32 erase_write_page (u32 pagenum)
+{
+	at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
+
+	debug("erase+write page=%u\n", pagenum);
+
+	/* give erase and write page command */
+	writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP |
+		(pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
+	while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
+		;
+	/* return status */
+	return readl(&eefc->fsr)
+		& (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE);
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	debug("erase first=%d last=%d\n", s_first, s_last);
+	puts("this flash does not need and support erasing!\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	u32 pagenum;
+	u32 *src32, *dst32;
+	u32 i;
+
+	debug("write src=%08lx addr=%08lx cnt=%lx\n",
+		(ulong)src, addr, cnt);
+
+	/* REQUIRE addr to be on a page start, abort if not */
+	if (addr % pagesize) {
+		printf ("eflash: start %08lx is not on page start\n"\
+			"        write aborted\n", addr);
+		return 1;
+	}
+
+	/* now start copying data */
+	pagenum = (addr-ATMEL_BASE_FLASH)/pagesize;
+	src32 = (u32 *) src;
+	dst32 = (u32 *) addr;
+	while (cnt > 0) {
+		i = pagesize / 4;
+		/* fill page buffer */
+		while (i--)
+			*dst32++ = *src32++;
+		/* write page */
+		if (erase_write_page(pagenum))
+			return 1;
+		pagenum++;
+		if (cnt > pagesize)
+			cnt -= pagesize;
+		else
+			cnt = 0;
+	}
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/led.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/led.c
new file mode 100644
index 000000000..46ed05502
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/led.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+
+#ifdef CONFIG_RED_LED
+void red_led_on(void)
+{
+	gpio_set_value(CONFIG_RED_LED, 1);
+}
+
+void red_led_off(void)
+{
+	gpio_set_value(CONFIG_RED_LED, 0);
+}
+#endif
+
+#ifdef CONFIG_GREEN_LED
+void green_led_on(void)
+{
+	gpio_set_value(CONFIG_GREEN_LED, 0);
+}
+
+void green_led_off(void)
+{
+	gpio_set_value(CONFIG_GREEN_LED, 1);
+}
+#endif
+
+#ifdef CONFIG_YELLOW_LED
+void yellow_led_on(void)
+{
+	gpio_set_value(CONFIG_YELLOW_LED, 0);
+}
+
+void yellow_led_off(void)
+{
+	gpio_set_value(CONFIG_YELLOW_LED, 1);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
new file mode 100644
index 000000000..a9ec81a75
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
@@ -0,0 +1,246 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_wdt.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_rstc.h>
+#ifdef CONFIG_ATMEL_LEGACY
+#include <asm/arch/at91sam9_matrix.h>
+#endif
+#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
+#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
+#endif
+
+.globl lowlevel_init
+.type lowlevel_init,function
+lowlevel_init:
+
+POS1:
+	adr	r5, POS1	/* r5 = POS1 run time */
+	ldr	r0, =POS1	/* r0 = POS1 compile */
+	sub	r5, r5, r0	/* r0 = CONFIG_SYS_TEXT_BASE-1 */
+
+	/* memory control configuration 1 */
+	ldr	r0, =SMRDATA
+	ldr	r2, =SMRDATA1
+	add	r0, r0, r5
+	add	r2, r2, r5
+0:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	0b
+
+/* ----------------------------------------------------------------------------
+ * PMC Init Step 1.
+ * ----------------------------------------------------------------------------
+ * - Check if the PLL is already initialized
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_ASM_PMC_MCKR)
+	ldr	r0, [r1]
+	and	r0, r0, #3
+	cmp	r0, #0
+	bne	PLL_setup_end
+
+/* ---------------------------------------------------------------------------
+ * - Enable the Main Oscillator
+ * ---------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_ASM_PMC_MOR)
+	ldr	r2, =(AT91_ASM_PMC_SR)
+	/* Main oscillator Enable register PMC_MOR: */
+	ldr	r0, =CONFIG_SYS_MOR_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
+	mov	r4, #AT91_PMC_IXR_MOSCS
+MOSCS_Loop:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_IXR_MOSCS
+	bne	MOSCS_Loop
+
+/* ----------------------------------------------------------------------------
+ * PMC Init Step 2.
+ * ----------------------------------------------------------------------------
+ * Setup PLLA
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_ASM_PMC_PLLAR)
+	ldr	r0, =CONFIG_SYS_PLLAR_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status register to detect when the PLLA is locked */
+	mov	r4, #AT91_PMC_IXR_LOCKA
+MOSCS_Loop1:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_IXR_LOCKA
+	bne	MOSCS_Loop1
+
+/* ----------------------------------------------------------------------------
+ * PMC Init Step 3.
+ * ----------------------------------------------------------------------------
+ * - Switch on the Main Oscillator
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_ASM_PMC_MCKR)
+
+	/* -Master Clock Controller register PMC_MCKR */
+	ldr	r0, =CONFIG_SYS_MCKR1_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status to detect when the Master clock is ready */
+	mov	r4, #AT91_PMC_IXR_MCKRDY
+MCKRDY_Loop:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_IXR_MCKRDY
+	bne	MCKRDY_Loop
+
+	ldr	r0, =CONFIG_SYS_MCKR2_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status to detect when the Master clock is ready */
+	mov	r4, #AT91_PMC_IXR_MCKRDY
+MCKRDY_Loop1:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_IXR_MCKRDY
+	bne	MCKRDY_Loop1
+PLL_setup_end:
+
+/* ----------------------------------------------------------------------------
+ * - memory control configuration 2
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r0, =(AT91_ASM_SDRAMC_TR)
+	ldr	r1, [r0]
+	cmp	r1, #0
+	bne	SDRAM_setup_end
+
+	ldr	r0, =SMRDATA1
+	ldr	r2, =SMRDATA2
+	add	r0, r0, r5
+	add	r2, r2, r5
+2:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	2b
+
+SDRAM_setup_end:
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word AT91_ASM_WDT_MR
+	.word CONFIG_SYS_WDTC_WDMR_VAL
+	/* configure PIOx as EBI0 D[16-31] */
+#if defined(CONFIG_AT91SAM9263)
+	.word AT91_ASM_PIOD_PDR
+	.word CONFIG_SYS_PIOD_PDR_VAL1
+	.word AT91_ASM_PIOD_PUDR
+	.word CONFIG_SYS_PIOD_PPUDR_VAL
+	.word AT91_ASM_PIOD_ASR
+	.word CONFIG_SYS_PIOD_PPUDR_VAL
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
+	|| defined(CONFIG_AT91SAM9G20)
+	.word AT91_ASM_PIOC_PDR
+	.word CONFIG_SYS_PIOC_PDR_VAL1
+	.word AT91_ASM_PIOC_PUDR
+	.word CONFIG_SYS_PIOC_PPUDR_VAL
+#endif
+	.word AT91_ASM_MATRIX_CSA0
+	.word CONFIG_SYS_MATRIX_EBICSA_VAL
+
+	/* flash */
+	.word AT91_ASM_SMC_MODE0
+	.word CONFIG_SYS_SMC0_MODE0_VAL
+
+	.word AT91_ASM_SMC_CYCLE0
+	.word CONFIG_SYS_SMC0_CYCLE0_VAL
+
+	.word AT91_ASM_SMC_PULSE0
+	.word CONFIG_SYS_SMC0_PULSE0_VAL
+
+	.word AT91_ASM_SMC_SETUP0
+	.word CONFIG_SYS_SMC0_SETUP0_VAL
+
+SMRDATA1:
+	.word AT91_ASM_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL1
+	.word AT91_ASM_SDRAMC_TR
+	.word CONFIG_SYS_SDRC_TR_VAL1
+	.word AT91_ASM_SDRAMC_CR
+	.word CONFIG_SYS_SDRC_CR_VAL
+	.word AT91_ASM_SDRAMC_MDR
+	.word CONFIG_SYS_SDRC_MDR_VAL
+	.word AT91_ASM_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL2
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL1
+	.word AT91_ASM_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL3
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL2
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL3
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL4
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL5
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL6
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL7
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL8
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL9
+	.word AT91_ASM_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL4
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL10
+	.word AT91_ASM_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL5
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL11
+	.word AT91_ASM_SDRAMC_TR
+	.word CONFIG_SYS_SDRC_TR_VAL2
+	.word CONFIG_SYS_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL12
+	/* User reset enable*/
+	.word AT91_ASM_RSTC_MR
+	.word CONFIG_SYS_RSTC_RMR_VAL
+#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
+	/* MATRIX_MCFG - REMAP all masters */
+	.word AT91_ASM_MATRIX_MCFG
+	.word 0x1FF
+#endif
+SMRDATA2:
+	.word 0
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/reset.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/reset.c
new file mode 100644
index 000000000..e67f47bd0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/reset.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_rstc.h>
+
+/* Reset the cpu by telling the reset controller to do so */
+void reset_cpu(ulong ignored)
+{
+	at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
+
+	writel(AT91_RSTC_KEY
+		| AT91_RSTC_CR_PROCRST	/* Processor Reset */
+		| AT91_RSTC_CR_PERRST	/* Peripheral Reset */
+#ifdef CONFIG_AT91RESET_EXTRST
+		| AT91_RSTC_CR_EXTRST	/* External Reset (assert nRST pin) */
+#endif
+		, &rstc->cr);
+	/* never reached */
+	while (1)
+		;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/timer.c
new file mode 100644
index 000000000..b0b7fb93f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/at91/timer.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <div64.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
+ * setting the 20 bit counter period to its maximum (0xfffff).
+ * (See the relevant data sheets to understand that this really works)
+ *
+ * We do also mimic the typical powerpc way of incrementing
+ * two 32 bit registers called tbl and tbu.
+ *
+ * Those registers increment at 1/16 the main clock rate.
+ */
+
+#define TIMER_LOAD_VAL	0xfffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, gd->arch.timer_rate_hz);
+
+	return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+	usec *= gd->arch.timer_rate_hz;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+/*
+ * Use the PITC in full 32 bit incrementing mode
+ */
+int timer_init(void)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
+
+	/* Enable PITC Clock */
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+
+	/* Enable PITC */
+	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
+
+	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+	gd->arch.tbu = gd->arch.tbl = 0;
+
+	return 0;
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+	at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
+
+	ulong now = readl(&pit->piir);
+
+	/* increment tbu if tbl has rolled over */
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long start;
+	ulong tmo;
+
+	start = get_ticks();		/* get current timestamp */
+	tmo = usec_to_tick(usec);	/* convert usecs to ticks */
+	while ((get_ticks() - start) < tmo)
+		;			/* loop till time has passed */
+}
+
+/*
+ * get_timer(base) can be used to check for timeouts or
+ * to measure elasped time relative to an event:
+ *
+ * ulong start_time = get_timer(0) sets start_time to the current
+ * time value.
+ * get_timer(start_time) returns the time elapsed since then.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
+ulong get_timer(ulong base)
+{
+	return tick_to_time(get_ticks()) - base;
+}
+
+/*
+ * Return the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return gd->arch.timer_rate_hz;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/cache.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/cache.c
new file mode 100644
index 000000000..e86c2edd3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/cache.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2011
+ * Ilya Yanok, EmCraft Systems
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <linux/types.h>
+#include <common.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#endif
+
+void invalidate_dcache_all(void)
+{
+	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
+}
+
+void flush_dcache_all(void)
+{
+	asm volatile(
+		"0:"
+		"mrc p15, 0, r15, c7, c14, 3\n"
+		"bne 0b\n"
+		"mcr p15, 0, %0, c7, c10, 4\n"
+		 : : "r"(0) : "memory"
+	);
+}
+
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (!check_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (!check_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+void __l2_cache_disable(void) {}
+
+void l2_cache_disable(void)
+	__attribute__((weak, alias("__l2_cache_disable")));
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/config.mk b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/config.mk
new file mode 100644
index 000000000..bdb3da183
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/config.mk
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -march=armv5te
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/cpu.c
new file mode 100644
index 000000000..e37e87b68
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/cpu.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+	l2_cache_disable();
+
+	/* flush I/D-cache */
+	cache_flush();
+
+	return 0;
+}
+
+/* flush I/D-cache */
+static void cache_flush (void)
+{
+	unsigned long i = 0;
+
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/Makefile
new file mode 100644
index 000000000..7d67191de
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y				+= cpu.o misc.o timer.o psc.o pinmux.o reset.o
+obj-$(CONFIG_DA850_LOWLEVEL)	+= da850_lowlevel.o
+obj-$(CONFIG_SOC_DM355)	+= dm355.o
+obj-$(CONFIG_SOC_DM365)	+= dm365.o
+obj-$(CONFIG_SOC_DM644X)	+= dm644x.o
+obj-$(CONFIG_SOC_DM646X)	+= dm646x.o
+obj-$(CONFIG_SOC_DA830)	+= da830_pinmux.o
+obj-$(CONFIG_SOC_DA850)	+= da850_pinmux.o
+obj-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_FRAMEWORK)	+= spl.o
+obj-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
+obj-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
+endif
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+obj-y	+= lowlevel_init.o
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/config.mk b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/config.mk
new file mode 100644
index 000000000..69e9d5ab2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/config.mk
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+ifndef CONFIG_SPL_BUILD
+ALL-$(CONFIG_SPL_FRAMEWORK)	+= u-boot.ais
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/cpu.c
new file mode 100644
index 000000000..ff6114775
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2004 Texas Instruments.
+ * Copyright (C) 2009 David Brownell
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* offsets from PLL controller base */
+#define PLLC_PLLCTL	0x100
+#define PLLC_PLLM	0x110
+#define PLLC_PREDIV	0x114
+#define PLLC_PLLDIV1	0x118
+#define PLLC_PLLDIV2	0x11c
+#define PLLC_PLLDIV3	0x120
+#define PLLC_POSTDIV	0x128
+#define PLLC_BPDIV	0x12c
+#define PLLC_PLLDIV4	0x160
+#define PLLC_PLLDIV5	0x164
+#define PLLC_PLLDIV6	0x168
+#define PLLC_PLLDIV7	0x16c
+#define PLLC_PLLDIV8	0x170
+#define PLLC_PLLDIV9	0x174
+
+#define BIT(x)		(1 << (x))
+
+/* SOC-specific pll info */
+#ifdef CONFIG_SOC_DM355
+#define ARM_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
+#ifdef CONFIG_SOC_DM644X
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV2
+#endif
+
+#ifdef CONFIG_SOC_DM646X
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
+#ifdef CONFIG_SOC_DA8XX
+unsigned int sysdiv[9] = {
+	PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
+	PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
+};
+
+int clk_get(enum davinci_clk_ids id)
+{
+	int pre_div;
+	int pllm;
+	int post_div;
+	int pll_out;
+	unsigned int pll_base;
+
+	pll_out = CONFIG_SYS_OSCIN_FREQ;
+
+	if (id == DAVINCI_AUXCLK_CLKID)
+		goto out;
+
+	if ((id >> 16) == 1)
+		pll_base = (unsigned int)davinci_pllc1_regs;
+	else
+		pll_base = (unsigned int)davinci_pllc0_regs;
+
+	id &= 0xFFFF;
+
+	/*
+	 * Lets keep this simple. Combining operations can result in
+	 * unexpected approximations
+	 */
+	pre_div = (readl(pll_base + PLLC_PREDIV) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
+	pllm = readl(pll_base + PLLC_PLLM) + 1;
+
+	pll_out /= pre_div;
+	pll_out *= pllm;
+
+	if (id == DAVINCI_PLLM_CLKID)
+		goto out;
+
+	post_div = (readl(pll_base + PLLC_POSTDIV) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
+
+	pll_out /= post_div;
+
+	if (id == DAVINCI_PLLC_CLKID)
+		goto out;
+
+	pll_out /= (readl(pll_base + sysdiv[id - 1]) &
+		DAVINCI_PLLC_DIV_MASK) + 1;
+
+out:
+	return pll_out;
+}
+
+int set_cpu_clk_info(void)
+{
+	gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
+	/* DDR PHY uses an x2 input clock */
+	gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
+				(clk_get(DAVINCI_DDR_CLKID) / 1000000);
+	gd->bd->bi_dsp_freq = 0;
+	return 0;
+}
+
+#else /* CONFIG_SOC_DA8XX */
+
+static unsigned pll_div(volatile void *pllbase, unsigned offset)
+{
+	u32	div;
+
+	div = REG(pllbase + offset);
+	return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
+}
+
+static inline unsigned pll_prediv(volatile void *pllbase)
+{
+#ifdef CONFIG_SOC_DM355
+	/* this register read seems to fail on pll0 */
+	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
+		return 8;
+	else
+		return pll_div(pllbase, PLLC_PREDIV);
+#elif defined(CONFIG_SOC_DM365)
+	return pll_div(pllbase, PLLC_PREDIV);
+#endif
+	return 1;
+}
+
+static inline unsigned pll_postdiv(volatile void *pllbase)
+{
+#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
+	return pll_div(pllbase, PLLC_POSTDIV);
+#elif defined(CONFIG_SOC_DM6446)
+	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
+		return pll_div(pllbase, PLLC_POSTDIV);
+#endif
+	return 1;
+}
+
+static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
+{
+	volatile void	*pllbase = (volatile void *) pll_addr;
+#ifdef CONFIG_SOC_DM646X
+	unsigned	base = CONFIG_REFCLK_FREQ / 1000;
+#else
+	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
+#endif
+
+	/* the PLL might be bypassed */
+	if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
+		base /= pll_prediv(pllbase);
+#if defined(CONFIG_SOC_DM365)
+		base *=  2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
+#else
+		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
+#endif
+		base /= pll_postdiv(pllbase);
+	}
+	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
+}
+
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
+}
+#endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
+}
+#endif
+
+int set_cpu_clk_info(void)
+{
+	unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
+#if defined(CONFIG_SOC_DM365)
+	pllbase = DAVINCI_PLL_CNTRL1_BASE;
+#endif
+	gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
+
+#ifdef DSP_PLLDIV
+	gd->bd->bi_dsp_freq =
+		pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
+#else
+	gd->bd->bi_dsp_freq = 0;
+#endif
+
+	pllbase = DAVINCI_PLL_CNTRL1_BASE;
+#if defined(CONFIG_SOC_DM365)
+	pllbase = DAVINCI_PLL_CNTRL0_BASE;
+#endif
+	gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
+
+	return 0;
+}
+
+#endif /* !CONFIG_SOC_DA8XX */
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_DRIVER_TI_EMAC)
+	davinci_emac_initialize();
+#endif
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
new file mode 100644
index 000000000..edaab4532
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
@@ -0,0 +1,139 @@
+/*
+ * Pinmux configurations for the DA830 SoCs
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux_defs.h>
+
+/* SPI0 pin muxer settings */
+const struct pinmux_config spi0_pins_base[] = {
+	{ pinmux(7), 1, 3 },  /* SPI0_SOMI */
+	{ pinmux(7), 1, 4 },  /* SPI0_SIMO */
+	{ pinmux(7), 1, 6 }   /* SPI0_CLK */
+};
+
+const struct pinmux_config spi0_pins_scs0[] = {
+	{ pinmux(7), 1, 7 }   /* SPI0_SCS[0] */
+};
+
+const struct pinmux_config spi0_pins_ena[] = {
+	{ pinmux(7), 1, 5 }   /* SPI0_ENA */
+};
+
+/* NAND pin muxer settings */
+const struct pinmux_config emifa_pins_cs0[] = {
+	{ pinmux(18), 1, 2 }   /* EMA_CS[0] */
+};
+
+const struct pinmux_config emifa_pins_cs2[] = {
+	{ pinmux(18), 1, 3 }   /* EMA_CS[2] */
+};
+
+const struct pinmux_config emifa_pins_cs3[] = {
+	{ pinmux(18), 1, 4 }   /* EMA_CS[3] */
+};
+
+#ifdef CONFIG_USE_NAND
+const struct pinmux_config emifa_pins[] = {
+	{ pinmux(13), 1, 6 },  /* EMA_D[0] */
+	{ pinmux(13), 1, 7 },  /* EMA_D[1] */
+	{ pinmux(14), 1, 0 },  /* EMA_D[2] */
+	{ pinmux(14), 1, 1 },  /* EMA_D[3] */
+	{ pinmux(14), 1, 2 },  /* EMA_D[4] */
+	{ pinmux(14), 1, 3 },  /* EMA_D[5] */
+	{ pinmux(14), 1, 4 },  /* EMA_D[6] */
+	{ pinmux(14), 1, 5 },  /* EMA_D[7] */
+	{ pinmux(14), 1, 6 },  /* EMA_D[8] */
+	{ pinmux(14), 1, 7 },  /* EMA_D[9] */
+	{ pinmux(15), 1, 0 },  /* EMA_D[10] */
+	{ pinmux(15), 1, 1 },  /* EMA_D[11] */
+	{ pinmux(15), 1, 2 },  /* EMA_D[12] */
+	{ pinmux(15), 1, 3 },  /* EMA_D[13] */
+	{ pinmux(15), 1, 4 },  /* EMA_D[14] */
+	{ pinmux(15), 1, 5 },  /* EMA_D[15] */
+	{ pinmux(15), 1, 6 },  /* EMA_A[0] */
+	{ pinmux(15), 1, 7 },  /* EMA_A[1] */
+	{ pinmux(16), 1, 0 },  /* EMA_A[2] */
+	{ pinmux(16), 1, 1 },  /* EMA_A[3] */
+	{ pinmux(16), 1, 2 },  /* EMA_A[4] */
+	{ pinmux(16), 1, 3 },  /* EMA_A[5] */
+	{ pinmux(16), 1, 4 },  /* EMA_A[6] */
+	{ pinmux(16), 1, 5 },  /* EMA_A[7] */
+	{ pinmux(16), 1, 6 },  /* EMA_A[8] */
+	{ pinmux(16), 1, 7 },  /* EMA_A[9] */
+	{ pinmux(17), 1, 0 },  /* EMA_A[10] */
+	{ pinmux(17), 1, 1 },  /* EMA_A[11] */
+	{ pinmux(17), 1, 2 },  /* EMA_A[12] */
+	{ pinmux(17), 1, 3 },  /* EMA_BA[1] */
+	{ pinmux(17), 1, 4 },  /* EMA_BA[0] */
+	{ pinmux(17), 1, 5 },  /* EMA_CLK */
+	{ pinmux(17), 1, 6 },  /* EMA_SDCKE */
+	{ pinmux(17), 1, 7 },  /* EMA_CAS */
+	{ pinmux(18), 1, 0 },  /* EMA_CAS */
+	{ pinmux(18), 1, 1 },  /* EMA_WE */
+	{ pinmux(18), 1, 5 },  /* EMA_OE */
+	{ pinmux(18), 1, 6 },  /* EMA_WE_DQM[1] */
+	{ pinmux(18), 1, 7 },  /* EMA_WE_DQM[0] */
+	{ pinmux(10), 1, 0 }   /* Tristate */
+};
+#endif
+
+/* EMAC PHY interface pins */
+const struct pinmux_config emac_pins_rmii[] = {
+	{ pinmux(10), 2, 1 },  /* RMII_TXD[0] */
+	{ pinmux(10), 2, 2 },  /* RMII_TXD[1] */
+	{ pinmux(10), 2, 3 },  /* RMII_TXEN */
+	{ pinmux(10), 2, 4 },  /* RMII_CRS_DV */
+	{ pinmux(10), 2, 5 },  /* RMII_RXD[0] */
+	{ pinmux(10), 2, 6 },  /* RMII_RXD[1] */
+	{ pinmux(10), 2, 7 }   /* RMII_RXER */
+};
+
+const struct pinmux_config emac_pins_mdio[] = {
+	{ pinmux(11), 2, 0 },  /* MDIO_CLK */
+	{ pinmux(11), 2, 1 }   /* MDIO_D */
+};
+
+const struct pinmux_config emac_pins_rmii_clk_source[] = {
+	{ pinmux(9), 0, 5 }    /* ref.clk from external source */
+};
+
+/* UART2 pin muxer settings */
+const struct pinmux_config uart2_pins_txrx[] = {
+	{ pinmux(8), 2, 7 },   /* UART2_RXD */
+	{ pinmux(9), 2, 0 }    /* UART2_TXD */
+};
+
+/* I2C0 pin muxer settings */
+const struct pinmux_config i2c0_pins[] = {
+	{ pinmux(8), 2, 3 },   /* I2C0_SDA */
+	{ pinmux(8), 2, 4 }    /* I2C0_SCL */
+};
+
+/* USB0_DRVVBUS pin muxer settings */
+const struct pinmux_config usb_pins[] = {
+	{ pinmux(9), 1, 1 }    /* USB0_DRVVBUS */
+};
+
+#ifdef CONFIG_DAVINCI_MMC
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins_8bit[] = {
+	{ pinmux(15), 2, 7 },  /* MMCSD0_CLK */
+	{ pinmux(16), 2, 0 },  /* MMCSD0_CMD */
+	{ pinmux(13), 2, 6 },  /* MMCSD0_DAT_0 */
+	{ pinmux(13), 2, 7 },  /* MMCSD0_DAT_1 */
+	{ pinmux(14), 2, 0 },  /* MMCSD0_DAT_2 */
+	{ pinmux(14), 2, 1 },  /* MMCSD0_DAT_3 */
+	{ pinmux(14), 2, 2 },  /* MMCSD0_DAT_4 */
+	{ pinmux(14), 2, 3 },  /* MMCSD0_DAT_5 */
+	{ pinmux(14), 2, 4 },  /* MMCSD0_DAT_6 */
+	{ pinmux(14), 2, 5 }   /* MMCSD0_DAT_7 */
+	/* DA830 supports 8-bit mode */
+};
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
new file mode 100644
index 000000000..b91e948ce
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -0,0 +1,313 @@
+/*
+ * SoC-specific lowlevel code for DA850
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/arch/da850_lowlevel.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/pll_defs.h>
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
+#if defined(CONFIG_SYS_DA850_PLL_INIT)
+static void da850_waitloop(unsigned long loopcnt)
+{
+	unsigned long	i;
+
+	for (i = 0; i < loopcnt; i++)
+		asm("   NOP");
+}
+
+static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
+{
+	if (reg == davinci_pllc0_regs)
+		/* Unlock PLL registers. */
+		clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
+
+	/*
+	 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
+	 * through MMR
+	 */
+	clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
+	/* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
+	clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
+
+	/* Set PLLEN=0 => PLL BYPASS MODE */
+	clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
+
+	da850_waitloop(150);
+
+	if (reg == davinci_pllc0_regs) {
+		/*
+		 * Select the Clock Mode bit 8 as External Clock or On Chip
+		 * Oscilator
+		 */
+		dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
+		setbits_le32(&reg->pllctl,
+			(CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
+	}
+
+	/* Clear PLLRST bit to reset the PLL */
+	clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
+
+	/* Disable the PLL output */
+	setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
+
+	/* PLL initialization sequence */
+	/*
+	 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
+	 * power down bit
+	 */
+	clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
+
+	/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
+	clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
+
+#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
+	/* program the prediv */
+	if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
+		writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
+			&reg->prediv);
+#endif
+
+	/* Program the required multiplier value in PLLM */
+	writel(pllmult, &reg->pllm);
+
+	/* program the postdiv */
+	if (reg == davinci_pllc0_regs)
+		writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
+			&reg->postdiv);
+	else
+		writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
+			&reg->postdiv);
+
+	/*
+	 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
+	 * no GO operation is currently in progress
+	 */
+	while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
+		;
+
+	if (reg == davinci_pllc0_regs) {
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
+		writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
+	} else {
+		writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
+		writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
+		writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
+	}
+
+	/*
+	 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
+	 * transition.
+	 */
+	setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
+
+	/*
+	 * Wait for the GOSTAT bit in PLLSTAT to clear to 0
+	 * (completion of phase alignment).
+	 */
+	while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
+		;
+
+	/* Wait for PLL to reset properly. See PLL spec for PLL reset time */
+	da850_waitloop(200);
+
+	/* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
+	setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
+
+	/* Wait for PLL to lock. See PLL spec for PLL lock time */
+	da850_waitloop(2400);
+
+	/*
+	 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
+	 * mode
+	 */
+	setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
+
+
+	/*
+	 * clear EMIFA and EMIFB clock source settings, let them
+	 * run off SYSCLK
+	 */
+	if (reg == davinci_pllc0_regs)
+		dv_maskbits(&davinci_syscfg_regs->cfgchip3,
+			~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DA850_PLL_INIT */
+
+#if defined(CONFIG_SYS_DA850_DDR_INIT)
+static int da850_ddr_setup(void)
+{
+	unsigned long	tmp;
+
+	/* Enable the Clock to DDR2/mDDR */
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+	if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
+		/* Begin VTP Calibration */
+		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
+		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
+		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+
+		/* Polling READY bit to see when VTP calibration is done */
+		tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+		while ((tmp & VTP_READY) != VTP_READY)
+			tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+
+		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
+		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
+	}
+	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
+	writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+
+	if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
+		/* DDR2 */
+		clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
+			(1 << DDR_SLEW_DDR_PDENA_BIT) |
+			(1 << DDR_SLEW_CMOSEN_BIT));
+	} else {
+		/* MOBILE DDR */
+		setbits_le32(&davinci_syscfg1_regs->ddr_slew,
+			(1 << DDR_SLEW_DDR_PDENA_BIT) |
+			(1 << DDR_SLEW_CMOSEN_BIT));
+	}
+
+	/*
+	 * SDRAM Configuration Register (SDCR):
+	 * First set the BOOTUNLOCK bit to make configuration bits
+	 * writeable.
+	 */
+	setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
+
+	/*
+	 * Write the new value of these bits and clear BOOTUNLOCK.
+	 * At the same time, set the TIMUNLOCK bit to allow changing
+	 * the timing registers
+	 */
+	tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
+	tmp &= ~DV_DDR_BOOTUNLOCK;
+	tmp |= DV_DDR_TIMUNLOCK;
+	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
+
+	/* write memory configuration and timing */
+	if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
+		/* MOBILE DDR only*/
+		writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+			&dv_ddr2_regs_ctrl->sdbcr2);
+	}
+	writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+	writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+	/* clear the TIMUNLOCK bit and write the value of the CL field */
+	tmp &= ~DV_DDR_TIMUNLOCK;
+	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
+
+	/*
+	 * LPMODEN and MCLKSTOPEN must be set!
+	 * Without this bits set, PSC don;t switch states !!
+	 */
+	writel(CONFIG_SYS_DA850_DDR2_SDRCR |
+		(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
+		(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
+		&dv_ddr2_regs_ctrl->sdrcr);
+
+	/* SyncReset the Clock to EMIF3A SDRAM */
+	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+	/* Enable the Clock to EMIF3A SDRAM */
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+	/* disable self refresh */
+	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
+		DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
+	writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+
+	return 0;
+}
+#endif /* CONFIG_SYS_DA850_DDR_INIT */
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+	return;
+}
+
+int arch_cpu_init(void)
+{
+	/* Unlock kick registers */
+	writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+	writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+	dv_maskbits(&davinci_syscfg_regs->suspsrc,
+		CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
+
+	/* configure pinmux settings */
+	if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
+		return 1;
+
+#if defined(CONFIG_SYS_DA850_PLL_INIT)
+	/* PLL setup */
+	da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
+	da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
+#endif
+	/* setup CSn config */
+#if defined(CONFIG_SYS_DA850_CS2CFG)
+	writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
+#endif
+#if defined(CONFIG_SYS_DA850_CS3CFG)
+	writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
+#endif
+
+	da8xx_configure_lpsc_items(lpsc, lpsc_size);
+
+	/* GPIO setup */
+	board_gpio_init();
+
+
+	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+	/*
+	 * Fix Power and Emulation Management Register
+	 * see sprufw3a.pdf page 37 Table 24
+	 */
+	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+		DAVINCI_UART_PWREMU_MGMT_UTRST),
+#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
+	       &davinci_uart0_ctrl_regs->pwremu_mgmt);
+#else
+	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
+#endif
+
+#if defined(CONFIG_SYS_DA850_DDR_INIT)
+	da850_ddr_setup();
+#endif
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
new file mode 100644
index 000000000..6105f6390
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
@@ -0,0 +1,181 @@
+/*
+ * Pinmux configurations for the DA850 SoCs
+ *
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux_defs.h>
+
+/* SPI pin muxer settings */
+const struct pinmux_config spi1_pins_base[] = {
+	{ pinmux(5), 1, 2 }, /* SPI1_CLK */
+	{ pinmux(5), 1, 4 }, /* SPI1_SOMI */
+	{ pinmux(5), 1, 5 }, /* SPI1_SIMO */
+};
+
+const struct pinmux_config spi1_pins_scs0[] = {
+	{ pinmux(5), 1, 1 }, /* SPI1_SCS[0] */
+};
+
+/* UART pin muxer settings */
+const struct pinmux_config uart0_pins_txrx[] = {
+	{ pinmux(3), 2, 4 }, /* UART0_RXD */
+	{ pinmux(3), 2, 5 }, /* UART0_TXD */
+};
+
+const struct pinmux_config uart0_pins_rtscts[] = {
+	{ pinmux(3), 2, 6 },
+	{ pinmux(3), 2, 7 },
+};
+
+const struct pinmux_config uart1_pins_txrx[] = {
+	{ pinmux(4), 2, 6 }, /* UART1_RXD */
+	{ pinmux(4), 2, 7 }, /* UART1_TXD */
+};
+
+const struct pinmux_config uart2_pins_txrx[] = {
+	{ pinmux(4), 2, 4 }, /* UART2_RXD */
+	{ pinmux(4), 2, 5 }, /* UART2_TXD */
+};
+
+const struct pinmux_config uart2_pins_rtscts[] = {
+	{ pinmux(0), 4, 6 }, /* UART2_RTS */
+	{ pinmux(0), 4, 7 }, /* UART2_CTS */
+};
+
+/* EMAC pin muxer settings*/
+const struct pinmux_config emac_pins_rmii[] = {
+	{ pinmux(14), 8, 2 }, /* RMII_TXD[1] */
+	{ pinmux(14), 8, 3 }, /* RMII_TXD[0] */
+	{ pinmux(14), 8, 4 }, /* RMII_TXEN */
+	{ pinmux(14), 8, 5 }, /* RMII_RXD[1] */
+	{ pinmux(14), 8, 6 }, /* RMII_RXD[0] */
+	{ pinmux(14), 8, 7 }, /* RMII_RXER */
+	{ pinmux(15), 0, 0 }, /* RMII_MHz_50_CLK */
+	{ pinmux(15), 8, 1 }, /* RMII_CRS_DV */
+};
+
+const struct pinmux_config emac_pins_mii[] = {
+	{ pinmux(2), 8, 1 }, /* MII_TXEN */
+	{ pinmux(2), 8, 2 }, /* MII_TXCLK */
+	{ pinmux(2), 8, 3 }, /* MII_COL */
+	{ pinmux(2), 8, 4 }, /* MII_TXD[3] */
+	{ pinmux(2), 8, 5 }, /* MII_TXD[2] */
+	{ pinmux(2), 8, 6 }, /* MII_TXD[1] */
+	{ pinmux(2), 8, 7 }, /* MII_TXD[0] */
+	{ pinmux(3), 8, 0 }, /* MII_RXCLK */
+	{ pinmux(3), 8, 1 }, /* MII_RXDV */
+	{ pinmux(3), 8, 2 }, /* MII_RXER */
+	{ pinmux(3), 8, 3 }, /* MII_CRS */
+	{ pinmux(3), 8, 4 }, /* MII_RXD[3] */
+	{ pinmux(3), 8, 5 }, /* MII_RXD[2] */
+	{ pinmux(3), 8, 6 }, /* MII_RXD[1] */
+	{ pinmux(3), 8, 7 }, /* MII_RXD[0] */
+};
+
+const struct pinmux_config emac_pins_mdio[] = {
+	{ pinmux(4), 8, 0 }, /* MDIO_CLK */
+	{ pinmux(4), 8, 1 }, /* MDIO_D */
+};
+
+/* I2C pin muxer settings */
+const struct pinmux_config i2c0_pins[] = {
+	{ pinmux(4), 2, 2 }, /* I2C0_SCL */
+	{ pinmux(4), 2, 3 }, /* I2C0_SDA */
+};
+
+const struct pinmux_config i2c1_pins[] = {
+	{ pinmux(4), 4, 4 }, /* I2C1_SCL */
+	{ pinmux(4), 4, 5 }, /* I2C1_SDA */
+};
+
+/* EMIFA pin muxer settings */
+const struct pinmux_config emifa_pins_cs2[] = {
+	{ pinmux(7), 1, 0 }, /* EMA_CS2 */
+};
+
+const struct pinmux_config emifa_pins_cs3[] = {
+	{ pinmux(7), 1, 1 }, /* EMA_CS[3] */
+};
+
+const struct pinmux_config emifa_pins_cs4[] = {
+	{ pinmux(7), 1, 2 }, /* EMA_CS[4] */
+};
+
+const struct pinmux_config emifa_pins_nand[] = {
+	{ pinmux(7), 1, 4 },  /* EMA_WE */
+	{ pinmux(7), 1, 5 },  /* EMA_OE */
+	{ pinmux(9), 1, 0 },  /* EMA_D[7] */
+	{ pinmux(9), 1, 1 },  /* EMA_D[6] */
+	{ pinmux(9), 1, 2 },  /* EMA_D[5] */
+	{ pinmux(9), 1, 3 },  /* EMA_D[4] */
+	{ pinmux(9), 1, 4 },  /* EMA_D[3] */
+	{ pinmux(9), 1, 5 },  /* EMA_D[2] */
+	{ pinmux(9), 1, 6 },  /* EMA_D[1] */
+	{ pinmux(9), 1, 7 },  /* EMA_D[0] */
+	{ pinmux(12), 1, 5 }, /* EMA_A[2] */
+	{ pinmux(12), 1, 6 }, /* EMA_A[1] */
+};
+
+/* NOR pin muxer settings */
+const struct pinmux_config emifa_pins_nor[] = {
+	{ pinmux(5), 1, 6 },  /* EMA_BA[1] */
+	{ pinmux(6), 1, 6 },  /* EMA_WAIT[1] */
+	{ pinmux(7), 1, 4 },  /* EMA_WE */
+	{ pinmux(7), 1, 5 },  /* EMA_OE */
+	{ pinmux(8), 1, 0 },  /* EMA_D[15] */
+	{ pinmux(8), 1, 1 },  /* EMA_D[14] */
+	{ pinmux(8), 1, 2 },  /* EMA_D[13] */
+	{ pinmux(8), 1, 3 },  /* EMA_D[12] */
+	{ pinmux(8), 1, 4 },  /* EMA_D[11] */
+	{ pinmux(8), 1, 5 },  /* EMA_D[10] */
+	{ pinmux(8), 1, 6 },  /* EMA_D[9] */
+	{ pinmux(8), 1, 7 },  /* EMA_D[8] */
+	{ pinmux(9), 1, 0 },  /* EMA_D[7] */
+	{ pinmux(9), 1, 1 },  /* EMA_D[6] */
+	{ pinmux(9), 1, 2 },  /* EMA_D[5] */
+	{ pinmux(9), 1, 3 },  /* EMA_D[4] */
+	{ pinmux(9), 1, 4 },  /* EMA_D[3] */
+	{ pinmux(9), 1, 5 },  /* EMA_D[2] */
+	{ pinmux(9), 1, 6 },  /* EMA_D[1] */
+	{ pinmux(9), 1, 7 },  /* EMA_D[0] */
+	{ pinmux(10), 1, 1 }, /* EMA_A[22] */
+	{ pinmux(10), 1, 2 }, /* EMA_A[21] */
+	{ pinmux(10), 1, 3 }, /* EMA_A[20] */
+	{ pinmux(10), 1, 4 }, /* EMA_A[19] */
+	{ pinmux(10), 1, 5 }, /* EMA_A[18] */
+	{ pinmux(10), 1, 6 }, /* EMA_A[17] */
+	{ pinmux(10), 1, 7 }, /* EMA_A[16] */
+	{ pinmux(11), 1, 0 }, /* EMA_A[15] */
+	{ pinmux(11), 1, 1 }, /* EMA_A[14] */
+	{ pinmux(11), 1, 2 }, /* EMA_A[13] */
+	{ pinmux(11), 1, 3 }, /* EMA_A[12] */
+	{ pinmux(11), 1, 4 }, /* EMA_A[11] */
+	{ pinmux(11), 1, 5 }, /* EMA_A[10] */
+	{ pinmux(11), 1, 6 }, /* EMA_A[9] */
+	{ pinmux(11), 1, 7 }, /* EMA_A[8] */
+	{ pinmux(12), 1, 0 }, /* EMA_A[7] */
+	{ pinmux(12), 1, 1 }, /* EMA_A[6] */
+	{ pinmux(12), 1, 2 }, /* EMA_A[5] */
+	{ pinmux(12), 1, 3 }, /* EMA_A[4] */
+	{ pinmux(12), 1, 4 }, /* EMA_A[3] */
+	{ pinmux(12), 1, 5 }, /* EMA_A[2] */
+	{ pinmux(12), 1, 6 }, /* EMA_A[1] */
+	{ pinmux(12), 1, 7 }, /* EMA_A[0] */
+};
+
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins[] = {
+	{ pinmux(10), 2, 0 },	/* MMCSD0_CLK */
+	{ pinmux(10), 2, 1 },	/* MMCSD0_CMD */
+	{ pinmux(10), 2, 2 },	/* MMCSD0_DAT_0 */
+	{ pinmux(10), 2, 3 },	/* MMCSD0_DAT_1 */
+	{ pinmux(10), 2, 4 },	/* MMCSD0_DAT_2 */
+	{ pinmux(10), 2, 5 },	/* MMCSD0_DAT_3 */
+	/* DA850 supports only 4-bit mode, remaining pins are not configured */
+};
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm355.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm355.c
new file mode 100644
index 000000000..f9550a16d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm355.c
@@ -0,0 +1,30 @@
+/*
+ * SoC-specific code for tms320dm355 and similar chips
+ *
+ * Copyright (C) 2009 David Brownell
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
+
+#ifdef CONFIG_SYS_I2C_DAVINCI
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_LPSC_I2C);
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX3) |= (1 << 20) | (1 << 19);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm365.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm365.c
new file mode 100644
index 000000000..f6ca527e7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm365.c
@@ -0,0 +1,20 @@
+/*
+ * SoC-specific code for tms320dm365 and similar chips
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+}
+
+#ifdef CONFIG_SYS_I2C_DAVINCI
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_LPSC_I2C);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
new file mode 100644
index 000000000..ee096fe72
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
@@ -0,0 +1,459 @@
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ * Actually used for booting from NAND with nand_spl.
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <asm/arch/hardware.h>
+
+void dm365_waitloop(unsigned long loopcnt)
+{
+	unsigned long	i;
+
+	for (i = 0; i < loopcnt; i++)
+		asm("   NOP");
+}
+
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
+{
+	unsigned int clksrc = 0x0;
+
+	/* Power up the PLL */
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
+
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
+	setbits_le32(&dv_pll0_regs->pllctl,
+		clksrc << PLLCTL_CLOCK_MODE_SHIFT);
+
+	/*
+	 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+	 * through MMR
+	 */
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
+
+	/* Set PLLEN=0 => PLL BYPASS MODE */
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+	dm365_waitloop(150);
+
+	 /* PLLRST=1(reset assert) */
+	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+	dm365_waitloop(300);
+
+	/*Bring PLL out of Reset*/
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+	/* Program the Multiper and Pre-Divider for PLL1 */
+	writel(pllmult, &dv_pll0_regs->pllm);
+	writel(prediv, &dv_pll0_regs->prediv);
+
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+		PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+		&dv_pll0_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+
+	/* Program the PostDiv for PLL1 */
+	writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
+
+	/* Post divider setting for PLL1 */
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
+
+	dm365_waitloop(300);
+
+	/* Set the GOSET bit */
+	writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
+
+	dm365_waitloop(300);
+
+	/* Wait for PLL to LOCK */
+	while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
+		== PLL0_LOCK))
+		;
+
+	/* Enable the PLL Bit of PLLCTL*/
+	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+	return 0;
+}
+
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
+{
+	unsigned int clksrc = 0x0;
+
+	/* Power up the PLL*/
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
+
+	/*
+	 * Select the Clock Mode as Onchip Oscilator or External Clock on
+	 * MXI pin
+	 * VDB has input on MXI pin
+	 */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
+	setbits_le32(&dv_pll1_regs->pllctl,
+		clksrc << PLLCTL_CLOCK_MODE_SHIFT);
+
+	/*
+	 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+	 * through MMR
+	 */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
+
+	/* Set PLLEN=0 => PLL BYPASS MODE */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+	dm365_waitloop(50);
+
+	 /* PLLRST=1(reset assert) */
+	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+	dm365_waitloop(300);
+
+	/* Bring PLL out of Reset */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+	/* Program the Multiper and Pre-Divider for PLL2 */
+	writel(pllm, &dv_pll1_regs->pllm);
+	writel(prediv, &dv_pll1_regs->prediv);
+
+	writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
+
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+		PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+		&dv_pll1_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+
+	/* Post divider setting for PLL2 */
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
+
+	/* GoCmd for PostDivider to take effect */
+	writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
+
+	dm365_waitloop(150);
+
+	/* Wait for PLL to LOCK */
+	while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
+		== PLL1_LOCK))
+		;
+
+	dm365_waitloop(4100);
+
+	/* Enable the PLL2 */
+	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+	/* do this after PLL's have been set up */
+	writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
+		&dv_sys_module_regs->peri_clkctl);
+
+	return 0;
+}
+
+int dm365_ddr_setup(void)
+{
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+	clrbits_le32(&dv_sys_module_regs->vtpiocr,
+		VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
+
+	/* Set bit CLRZ (bit 13) */
+	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
+
+	/* Check VTP READY Status */
+	while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
+		;
+
+	/* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
+	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
+
+	/* Set bit LOCK(bit7) */
+	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
+
+	/*
+	 * Powerdown VTP as it is locked (bit 6)
+	 * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
+	 */
+	setbits_le32(&dv_sys_module_regs->vtpiocr,
+		VPTIO_IOPWRDN | VPTIO_PWRDN);
+
+	/* Wait for calibration to complete */
+	dm365_waitloop(150);
+
+	/* Set the DDR2 to synreset, then enable it again */
+	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+	writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+
+	/* Program SDRAM Bank Config Register */
+	writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
+		&dv_ddr2_regs_ctrl->sdbcr);
+	writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
+		&dv_ddr2_regs_ctrl->sdbcr);
+
+	/* Program SDRAM Timing Control Register1 */
+	writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+	/* Program SDRAM Timing Control Register2 */
+	writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+	writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+
+	writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
+
+	/* Program SDRAM Refresh Control Register */
+	writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
+
+	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+	return 0;
+}
+
+static void dm365_vpss_sync_reset(void)
+{
+	unsigned int PdNum = 0;
+
+	/* VPSS_CLKMD 1:1 */
+	setbits_le32(&dv_sys_module_regs->vpss_clkctl,
+		VPSS_CLK_CTL_VPSS_CLKMD);
+
+	/* LPSC SyncReset DDR Clock Enable */
+	writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
+		~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
+		&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
+
+	writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+	while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
+		;
+	while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
+		PSC_MD_STATE_MSK) == PSC_SYNCRESET))
+		;
+}
+
+static void dm365_por_reset(void)
+{
+	struct davinci_timer *wdog =
+		(struct davinci_timer *)DAVINCI_WDOG_BASE;
+
+	if (readl(&dv_pll0_regs->rstype) &
+		(PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
+		dm365_vpss_sync_reset();
+
+		writel(DV_TMPBUF_VAL, TMPBUF);
+		setbits_le32(TMPSTATUS, FLAG_PORRST);
+		writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
+		writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
+
+		while (1);
+	}
+}
+
+static void dm365_wdt_reset(void)
+{
+	struct davinci_timer *wdog =
+		(struct davinci_timer *)DAVINCI_WDOG_BASE;
+
+	if (readl(TMPBUF) != DV_TMPBUF_VAL) {
+		writel(DV_TMPBUF_VAL, TMPBUF);
+		setbits_le32(TMPSTATUS, FLAG_PORRST);
+		setbits_le32(TMPSTATUS, FLAG_FLGOFF);
+
+		dm365_waitloop(100);
+
+		dm365_vpss_sync_reset();
+
+		writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
+		writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
+
+		while (1);
+	}
+}
+
+static void dm365_wdt_flag_on(void)
+{
+	/* VPSS_CLKMD 1:2 */
+	clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
+		VPSS_CLK_CTL_VPSS_CLKMD);
+	writel(0, TMPBUF);
+	setbits_le32(TMPSTATUS, FLAG_FLGON);
+}
+
+void dm365_psc_init(void)
+{
+	unsigned char i = 0;
+	unsigned char lpsc_start;
+	unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
+	unsigned int  PdNum = 0;
+
+	lpscmin = 0;
+	lpscmax = 2;
+
+	for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
+		if (lpscgroup == 0) {
+			/* Enabling LPSC 3 to 28 SCR first */
+			lpsc_start = DAVINCI_LPSC_VPSSMSTR;
+			lpsc_end   = DAVINCI_LPSC_TIMER1;
+		} else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
+			lpsc_start = DAVINCI_LPSC_CFG5;
+			lpsc_end   = DAVINCI_LPSC_VPSSMASTER;
+		} else {
+			lpsc_start = DAVINCI_LPSC_MJCP;
+			lpsc_end   = DAVINCI_LPSC_HDVICP;
+		}
+
+		/* NEXT=0x3, Enable LPSC's */
+		for (i = lpsc_start; i <= lpsc_end; i++)
+			setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
+
+		/*
+		 * Program goctl to start transition sequence for LPSCs
+		 * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
+		 * Domain 0 Modules
+		 */
+		writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+		/*
+		 * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
+		 */
+		while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
+			== 0))
+			;
+
+		/* Wait for MODSTAT = ENABLE from LPSC's */
+		for (i = lpsc_start; i <= lpsc_end; i++)
+			while (!((readl(&dv_psc_regs->mdstat[i]) &
+				PSC_MD_STATE_MSK) == PSC_ENABLE))
+				;
+	}
+}
+
+static void dm365_emif_init(void)
+{
+	writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
+	writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
+
+	setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
+
+	writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
+
+	return;
+}
+
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+	unsigned long value)
+{
+	clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
+	setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
+}
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+	return;
+}
+
+#if defined(CONFIG_POST)
+int post_log(char *format, ...)
+{
+	return 0;
+}
+#endif
+
+void dm36x_lowlevel_init(ulong bootflag)
+{
+	struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
+		(struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
+		DAVINCI_UART_CTRL_BASE);
+
+	/* Mask all interrupts */
+	writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
+	writel(0x0, &dv_aintc_regs->eabase);
+	writel(0x0, &dv_aintc_regs->eint0);
+	writel(0x0, &dv_aintc_regs->eint1);
+
+	/* Clear all interrupts */
+	writel(0xffffffff, &dv_aintc_regs->fiq0);
+	writel(0xffffffff, &dv_aintc_regs->fiq1);
+	writel(0xffffffff, &dv_aintc_regs->irq0);
+	writel(0xffffffff, &dv_aintc_regs->irq1);
+
+	dm365_por_reset();
+	dm365_wdt_reset();
+
+	/* System PSC setup - enable all */
+	dm365_psc_init();
+
+	/* Setup Pinmux */
+	dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
+	dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
+	dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
+	dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
+	dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
+
+	/* PLL setup */
+	dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
+		CONFIG_SYS_DM36x_PLL1_PREDIV);
+	dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
+		CONFIG_SYS_DM36x_PLL2_PREDIV);
+
+	/* GPIO setup */
+	board_gpio_init();
+
+	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+	/*
+	 * Fix Power and Emulation Management Register
+	 * see sprufh2.pdf page 38 Table 22
+	 */
+	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+		DAVINCI_UART_PWREMU_MGMT_UTRST),
+	       &davinci_uart_ctrl_regs->pwremu_mgmt);
+
+	puts("ddr init\n");
+	dm365_ddr_setup();
+
+	puts("emif init\n");
+	dm365_emif_init();
+
+	dm365_wdt_flag_on();
+
+#if defined(CONFIG_POST)
+	/*
+	 * Do memory tests, calls arch_memory_failure_handle()
+	 * if error detected.
+	 */
+	memory_post_test(0);
+#endif
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm644x.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm644x.c
new file mode 100644
index 000000000..c58e271e2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm644x.c
@@ -0,0 +1,81 @@
+/*
+ * SoC-specific code for tms320dm644x chips
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+#define PINMUX0_EMACEN (1 << 31)
+#define PINMUX0_AECS5  (1 << 11)
+#define PINMUX0_AECS4  (1 << 10)
+
+#define PINMUX1_I2C    (1 <<  7)
+#define PINMUX1_UART1  (1 <<  1)
+#define PINMUX1_UART0  (1 <<  0)
+
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x00006001;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= PINMUX1_UART0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+void davinci_enable_emac(void)
+{
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable EMAC. */
+	REG(PINMUX0) |= PINMUX0_EMACEN;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_DAVINCI
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_LPSC_I2C);
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= PINMUX1_I2C;
+}
+#endif
+
+void davinci_errata_workarounds(void)
+{
+	/*
+	 * Workaround for TMS320DM6446 errata 1.3.22:
+	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
+	 *   Revision(s) Affected: 1.3 and earlier
+	 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/*
+	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
+	 * as suggested in TMS320DM6446 errata 2.1.2:
+	 *
+	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
+	 * low priority modules can occupy the bus and prevent high priority
+	 * modules like the VPSS from getting the required DDR2 throughput.
+	 * A hex value of 0x20 should provide a good ARM (cache enabled)
+	 * performance and still allow good utilization by the VPSS or other
+	 * modules.
+	 */
+	REG(VBPR) = 0x20;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm646x.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm646x.c
new file mode 100644
index 000000000..cfea8300d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dm646x.c
@@ -0,0 +1,26 @@
+/*
+ * SoC-specific code for TMS320DM646x chips
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_DM646X_LPSC_UART0);
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+void davinci_enable_emac(void)
+{
+	lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_DAVINCI
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_DM646X_LPSC_I2C);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dp83848.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dp83848.c
new file mode 100644
index 000000000..603d507c7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/dp83848.c
@@ -0,0 +1,128 @@
+/*
+ * National Semiconductor DP83848 PHY Driver for TI DaVinci
+ * (TMS320DM644x) based boards.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * --------------------------------------------------------
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <dp83848.h>
+#include <asm/arch/emac_defs.h>
+#include "../../../../../drivers/net/davinci_emac.h"
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_CMD_NET
+
+int dp83848_is_phy_connected(int phy_addr)
+{
+	u_int16_t	id1, id2;
+
+	if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
+		return(0);
+	if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
+		return(0);
+
+	if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
+		return(1);
+
+	return(0);
+}
+
+int dp83848_get_link_speed(int phy_addr)
+{
+	u_int16_t		tmp;
+	volatile emac_regs*	emac = (emac_regs *)EMAC_BASE_ADDR;
+
+	if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
+		return(0);
+
+	if (!(tmp & DP83848_LINK_STATUS))	/* link up? */
+		return(0);
+
+	if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
+		return(0);
+
+	/* Speed doesn't matter, there is no setting for it in EMAC... */
+	if (tmp & DP83848_DUPLEX) {
+		/* set DM644x EMAC for Full Duplex  */
+		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
+			EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
+	} else {
+		/*set DM644x EMAC for Half Duplex  */
+		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
+	}
+
+	return(1);
+}
+
+
+int dp83848_init_phy(int phy_addr)
+{
+	int	ret = 1;
+
+	if (!dp83848_get_link_speed(phy_addr)) {
+		/* Try another time */
+		udelay(100000);
+		ret = dp83848_get_link_speed(phy_addr);
+	}
+
+	/* Disable PHY Interrupts */
+	davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
+
+	return(ret);
+}
+
+
+int dp83848_auto_negotiate(int phy_addr)
+{
+	u_int16_t	tmp;
+
+
+	if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
+		return(0);
+
+	/* Restart Auto_negotiation  */
+	tmp &= ~DP83848_AUTONEG;	/* remove autonegotiation enable */
+	tmp |= DP83848_ISOLATE;		/* Electrically isolate PHY */
+	davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
+
+	/* Set the Auto_negotiation Advertisement Register
+	 * MII advertising for Next page, 100BaseTxFD and HD,
+	 * 10BaseTFD and HD, IEEE 802.3
+	 */
+	tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
+		DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
+	davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
+
+
+	/* Read Control Register */
+	if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
+		return(0);
+
+	tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
+	davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
+
+	/* Restart Auto_negotiation  */
+	tmp |= DP83848_RESTART_AUTONEG;
+	davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
+
+	/*check AutoNegotiate complete */
+	udelay(10000);
+	if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
+		return(0);
+
+	if (!(tmp & DP83848_AUTONEG_COMP))
+		return(0);
+
+	return (dp83848_get_link_speed(phy_addr));
+}
+
+#endif	/* CONFIG_CMD_NET */
+
+#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/et1011c.c
new file mode 100644
index 000000000..9d53875b9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/et1011c.c
@@ -0,0 +1,42 @@
+/*
+ * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <miiphy.h>
+#include <asm/arch/emac_defs.h>
+#include "../../../../../drivers/net/davinci_emac.h"
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_CMD_NET
+
+/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
+
+#define MII_PHY_CONFIG_REG		22
+
+/* PHY Config bits */
+#define PHY_SYS_CLK_EN			(1 << 4)
+
+int et1011c_get_link_speed(int phy_addr)
+{
+	u_int16_t	data;
+
+	if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
+		davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
+		/* Enable 125MHz clock sourced from PHY */
+		davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
+			data | PHY_SYS_CLK_EN);
+		return (1);
+	}
+	return (0);
+}
+
+#endif	/* CONFIG_CMD_NET */
+
+#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/ksz8873.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/ksz8873.c
new file mode 100644
index 000000000..4af5dd213
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/ksz8873.c
@@ -0,0 +1,53 @@
+/*
+ * Micrel KSZ8873 PHY Driver for TI DaVinci
+ * (TMS320DM644x) based boards.
+ *
+ * Copyright (C) 2011 Heiko Schocher <hsdenx.de>
+ *
+ * based on:
+ * National Semiconductor DP83848 PHY Driver for TI DaVinci
+ * (TMS320DM644x) based boards.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * --------------------------------------------------------
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/io.h>
+#include "../../../../../drivers/net/davinci_emac.h"
+
+int ksz8873_is_phy_connected(int phy_addr)
+{
+	u_int16_t	dummy;
+
+	return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
+}
+
+int ksz8873_get_link_speed(int phy_addr)
+{
+	emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
+
+	/* we always have a link to the switch, 100 FD */
+	writel((EMAC_MACCONTROL_MIIEN_ENABLE |
+		EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
+	       &emac->MACCONTROL);
+	return 1;
+}
+
+
+int ksz8873_init_phy(int phy_addr)
+{
+	return 1;
+}
+
+
+int ksz8873_auto_negotiate(int phy_addr)
+{
+	return dp83848_get_link_speed(phy_addr);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
new file mode 100644
index 000000000..e91623497
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
@@ -0,0 +1,693 @@
+/*
+ * Low-level board setup code for TI DaVinci SoC based boards.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Partially based on TI sources, original copyrights follow:
+ */
+
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
+ *
+ * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
+ *
+ * Modified for DV-EVM board by Swaminathan S, Nov 2005
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+#define MDSTAT_STATE	0x3f
+
+.globl	lowlevel_init
+lowlevel_init:
+#ifdef CONFIG_SOC_DM644X
+
+	/*-------------------------------------------------------*
+	 * Mask all IRQs by setting all bits in the EINT default *
+	 *-------------------------------------------------------*/
+	mov	r1, $0
+	ldr	r0, =EINT_ENABLE0
+	str	r1, [r0]
+	ldr	r0, =EINT_ENABLE1
+	str	r1, [r0]
+
+	/*------------------------------------------------------*
+	 * Put the GEM in reset					*
+	 *------------------------------------------------------*/
+
+	/* Put the GEM in reset */
+	ldr	r8, PSC_GEM_FLAG_CLEAR
+	ldr	r6, MDCTL_GEM
+	ldr	r7, [r6]
+	and	r7, r7, r8
+	str	r7, [r6]
+
+	/* Enable the Power Domain Transition Command */
+	ldr	r6, PTCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x02
+	str	r7, [r6]
+
+	/* Check for Transition Complete(PTSTAT) */
+checkStatClkStopGem:
+	ldr	r6, PTSTAT
+	ldr	r7, [r6]
+	ands	r7, r7, $0x02
+	bne	checkStatClkStopGem
+
+	/* Check for GEM Reset Completion */
+checkGemStatClkStop:
+	ldr	r6, MDSTAT_GEM
+	ldr	r7, [r6]
+	ands	r7, r7, $0x100
+	bne	checkGemStatClkStop
+
+	/* Do this for enabling a WDT initiated reset this is a workaround
+	   for a chip bug.  Not required under normal situations */
+	ldr	r6, P1394
+	mov	r10, $0
+	str	r10, [r6]
+
+	/*------------------------------------------------------*
+	 * Enable L1 & L2 Memories in Fast mode                 *
+	 *------------------------------------------------------*/
+	ldr	r6, DFT_ENABLE
+	mov	r10, $0x01
+	str	r10, [r6]
+
+	ldr	r6, MMARG_BRF0
+	ldr	r10, MMARG_BRF0_VAL
+	str	r10, [r6]
+
+	ldr	r6, DFT_ENABLE
+	mov	r10, $0
+	str	r10, [r6]
+
+	/*------------------------------------------------------*
+	 * DDR2 PLL Initialization				*
+	 *------------------------------------------------------*/
+
+	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
+	mov	r10, $0
+	ldr	r6, PLL2_CTL
+	ldr	r7, PLL_CLKSRC_MASK
+	ldr	r8, [r6]
+	and	r8, r8, r7
+	mov	r9, r10, lsl $8
+	orr	r8, r8, r9
+	str	r8, [r6]
+
+	/* Select the PLLEN source */
+	ldr	r7, PLL_ENSRC_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Bypass the PLL */
+	ldr	r7, PLL_BYPASS_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
+	mov	r10, $0x20
+WaitPPL2Loop:
+	subs	r10, r10, $1
+	bne	WaitPPL2Loop
+
+	/* Reset the PLL */
+	ldr	r7, PLL_RESET_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Power up the PLL */
+	ldr	r7, PLL_PWRUP_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Enable the PLL from Disable Mode */
+	ldr	r7, PLL_DISABLE_ENABLE_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Program the PLL Multiplier */
+	ldr	r6, PLL2_PLLM
+	mov	r2, $0x17	/* 162 MHz */
+	str	r2, [r6]
+
+	/* Program the PLL2 Divisor Value */
+	ldr	r6, PLL2_DIV2
+	mov	r3, $0x01
+	str	r3, [r6]
+
+	/* Program the PLL2 Divisor Value */
+	ldr	r6, PLL2_DIV1
+	mov	r4, $0x0b	/* 54 MHz */
+	str	r4, [r6]
+
+	/* PLL2 DIV2 MMR */
+	ldr	r8, PLL2_DIV_MASK
+	ldr	r6, PLL2_DIV2
+	ldr	r9, [r6]
+	and	r8, r8, r9
+	mov	r9, $0x01
+	mov	r9, r9, lsl $15
+	orr	r8, r8, r9
+	str	r8, [r6]
+
+	/* Program the GOSET bit to take new divider values */
+	ldr	r6, PLL2_PLLCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Wait for Done */
+	ldr	r6, PLL2_PLLSTAT
+doneLoop_0:
+	ldr	r7, [r6]
+	ands	r7, r7, $0x01
+	bne	doneLoop_0
+
+	/* PLL2 DIV1 MMR */
+	ldr	r8, PLL2_DIV_MASK
+	ldr	r6, PLL2_DIV1
+	ldr	r9, [r6]
+	and	r8, r8, r9
+	mov	r9, $0x01
+	mov	r9, r9, lsl $15
+	orr	r8, r8, r9
+	str	r8, [r6]
+
+	/* Program the GOSET bit to take new divider values */
+	ldr	r6, PLL2_PLLCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Wait for Done */
+	ldr	r6, PLL2_PLLSTAT
+doneLoop:
+	ldr	r7, [r6]
+	ands	r7, r7, $0x01
+	bne	doneLoop
+
+	/* Wait for PLL to Reset Properly */
+	mov	r10, $0x218
+ResetPPL2Loop:
+	subs	r10, r10, $1
+	bne	ResetPPL2Loop
+
+	/* Bring PLL out of Reset */
+	ldr	r6, PLL2_CTL
+	ldr	r8, [r6]
+	orr	r8, r8, $0x08
+	str	r8, [r6]
+
+	/* Wait for PLL to Lock */
+	ldr	r10, PLL_LOCK_COUNT
+PLL2Lock:
+	subs	r10, r10, $1
+	bne	PLL2Lock
+
+	/* Enable the PLL */
+	ldr	r6, PLL2_CTL
+	ldr	r8, [r6]
+	orr	r8, r8, $0x01
+	str	r8, [r6]
+
+	/*------------------------------------------------------*
+	 * Issue Soft Reset to DDR Module			*
+	 *------------------------------------------------------*/
+
+	/* Shut down the DDR2 LPSC Module */
+	ldr	r8, PSC_FLAG_CLEAR
+	ldr	r6, MDCTL_DDR2
+	ldr	r7, [r6]
+	and	r7, r7, r8
+	orr	r7, r7, $0x03
+	str	r7, [r6]
+
+	/* Enable the Power Domain Transition Command */
+	ldr	r6, PTCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Check for Transition Complete(PTSTAT) */
+checkStatClkStop:
+	ldr	r6, PTSTAT
+	ldr	r7, [r6]
+	ands	r7, r7, $0x01
+	bne	checkStatClkStop
+
+	/* Check for DDR2 Controller Enable Completion */
+checkDDRStatClkStop:
+	ldr	r6, MDSTAT_DDR2
+	ldr	r7, [r6]
+	and	r7, r7, $MDSTAT_STATE
+	cmp	r7, $0x03
+	bne	checkDDRStatClkStop
+
+	/*------------------------------------------------------*
+	 * Program DDR2 MMRs for 162MHz Setting			*
+	 *------------------------------------------------------*/
+
+	/* Program PHY Control Register */
+	ldr	r6, DDRCTL
+	ldr	r7, DDRCTL_VAL
+	str	r7, [r6]
+
+	/* Program SDRAM Bank Config Register */
+	ldr	r6, SDCFG
+	ldr	r7, SDCFG_VAL
+	str	r7, [r6]
+
+	/* Program SDRAM TIM-0 Config Register */
+	ldr	r6, SDTIM0
+	ldr	r7, SDTIM0_VAL_162MHz
+	str	r7, [r6]
+
+	/* Program SDRAM TIM-1 Config Register */
+	ldr	r6, SDTIM1
+	ldr	r7, SDTIM1_VAL_162MHz
+	str	r7, [r6]
+
+	/* Program the SDRAM Bank Config Control Register */
+	ldr	r10, MASK_VAL
+	ldr	r8, SDCFG
+	ldr	r9, SDCFG_VAL
+	and	r9, r9, r10
+	str	r9, [r8]
+
+	/* Program SDRAM SDREF Config Register */
+	ldr	r6, SDREF
+	ldr	r7, SDREF_VAL
+	str	r7, [r6]
+
+	/*------------------------------------------------------*
+	 * Issue Soft Reset to DDR Module			*
+	 *------------------------------------------------------*/
+
+	/* Issue a Dummy DDR2 read/write */
+	ldr	r8, DDR2_START_ADDR
+	ldr	r7, DUMMY_VAL
+	str	r7, [r8]
+	ldr	r7, [r8]
+
+	/* Shut down the DDR2 LPSC Module */
+	ldr	r8, PSC_FLAG_CLEAR
+	ldr	r6, MDCTL_DDR2
+	ldr	r7, [r6]
+	and	r7, r7, r8
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Enable the Power Domain Transition Command */
+	ldr	r6, PTCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Check for Transition Complete(PTSTAT) */
+checkStatClkStop2:
+	ldr	r6, PTSTAT
+	ldr	r7, [r6]
+	ands	r7, r7, $0x01
+	bne	checkStatClkStop2
+
+	/* Check for DDR2 Controller Enable Completion */
+checkDDRStatClkStop2:
+	ldr	r6, MDSTAT_DDR2
+	ldr	r7, [r6]
+	and	r7, r7, $MDSTAT_STATE
+	cmp	r7, $0x01
+	bne	checkDDRStatClkStop2
+
+	/*------------------------------------------------------*
+	 * Turn DDR2 Controller Clocks On			*
+	 *------------------------------------------------------*/
+
+	/* Enable the DDR2 LPSC Module */
+	ldr	r6, MDCTL_DDR2
+	ldr	r7, [r6]
+	orr	r7, r7, $0x03
+	str	r7, [r6]
+
+	/* Enable the Power Domain Transition Command */
+	ldr	r6, PTCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Check for Transition Complete(PTSTAT) */
+checkStatClkEn2:
+	ldr	r6, PTSTAT
+	ldr	r7, [r6]
+	ands	r7, r7, $0x01
+	bne	checkStatClkEn2
+
+	/* Check for DDR2 Controller Enable Completion */
+checkDDRStatClkEn2:
+	ldr	r6, MDSTAT_DDR2
+	ldr	r7, [r6]
+	and	r7, r7, $MDSTAT_STATE
+	cmp	r7, $0x03
+	bne	checkDDRStatClkEn2
+
+	/*  DDR Writes and Reads */
+	ldr	r6, CFGTEST
+	mov	r3, $0x01
+	str	r3, [r6]
+
+	/*------------------------------------------------------*
+	 * System PLL Initialization				*
+	 *------------------------------------------------------*/
+
+	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
+	mov	r2, $0
+	ldr	r6, PLL1_CTL
+	ldr	r7, PLL_CLKSRC_MASK
+	ldr	r8, [r6]
+	and	r8, r8, r7
+	mov	r9, r2, lsl $8
+	orr	r8, r8, r9
+	str	r8, [r6]
+
+	/* Select the PLLEN source */
+	ldr	r7, PLL_ENSRC_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Bypass the PLL */
+	ldr	r7, PLL_BYPASS_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
+	mov	r10, $0x20
+
+WaitLoop:
+	subs	r10, r10, $1
+	bne	WaitLoop
+
+	/* Reset the PLL */
+	ldr	r7, PLL_RESET_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Disable the PLL */
+	orr	r8, r8, $0x10
+	str	r8, [r6]
+
+	/* Power up the PLL */
+	ldr	r7, PLL_PWRUP_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Enable the PLL from Disable Mode */
+	ldr	r7, PLL_DISABLE_ENABLE_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Program the PLL Multiplier */
+	ldr	r6, PLL1_PLLM
+	mov	r3, $0x15	/* For 594MHz */
+	str	r3, [r6]
+
+	/* Wait for PLL to Reset Properly */
+	mov	r10, $0xff
+
+ResetLoop:
+	subs	r10, r10, $1
+	bne	ResetLoop
+
+	/* Bring PLL out of Reset */
+	ldr	r6, PLL1_CTL
+	orr	r8, r8, $0x08
+	str	r8, [r6]
+
+	/* Wait for PLL to Lock */
+	ldr	r10, PLL_LOCK_COUNT
+
+PLL1Lock:
+	subs	r10, r10, $1
+	bne	PLL1Lock
+
+	/* Enable the PLL */
+	orr	r8, r8, $0x01
+	str	r8, [r6]
+
+	nop
+	nop
+	nop
+	nop
+
+	/*------------------------------------------------------*
+	 * AEMIF configuration for NOR Flash (double check)     *
+	 *------------------------------------------------------*/
+	ldr	r0, _PINMUX0
+	ldr	r1, _DEV_SETTING
+	str	r1, [r0]
+
+	ldr	r0, WAITCFG
+	ldr	r1, WAITCFG_VAL
+	ldr	r2, [r0]
+	orr	r2, r2, r1
+	str	r2, [r0]
+
+	ldr	r0, ACFG3
+	ldr	r1, ACFG3_VAL
+	ldr	r2, [r0]
+	and	r1, r2, r1
+	str	r1, [r0]
+
+	ldr	r0, ACFG4
+	ldr	r1, ACFG4_VAL
+	ldr	r2, [r0]
+	and	r1, r2, r1
+	str	r1, [r0]
+
+	ldr	r0, ACFG5
+	ldr	r1, ACFG5_VAL
+	ldr	r2, [r0]
+	and	r1, r2, r1
+	str	r1, [r0]
+
+	/*--------------------------------------*
+	 * VTP manual Calibration               *
+	 *--------------------------------------*/
+	ldr	r0, VTPIOCR
+	ldr	r1, VTP_MMR0
+	str	r1, [r0]
+
+	ldr	r0, VTPIOCR
+	ldr	r1, VTP_MMR1
+	str	r1, [r0]
+
+	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
+	ldr	r10, VTP_LOCK_COUNT
+VTPLock:
+	subs	r10, r10, $1
+	bne	VTPLock
+
+	ldr	r6, DFT_ENABLE
+	mov	r10, $0x01
+	str	r10, [r6]
+
+	ldr	r6, DDRVTPR
+	ldr	r7, [r6]
+	mov	r8, r7, LSL #32-10
+	mov	r8, r8, LSR #32-10        /* grab low 10 bits  */
+	ldr	r7, VTP_RECAL
+	orr	r8, r7, r8
+	ldr	r7, VTP_EN
+	orr	r8, r7, r8
+	str	r8, [r0]
+
+
+	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
+	ldr	r10, VTP_LOCK_COUNT
+VTP1Lock:
+	subs	r10, r10, $1
+	bne	VTP1Lock
+
+	ldr	r1, [r0]
+	ldr	r2, VTP_MASK
+	and	r2, r1, r2
+	str	r2, [r0]
+
+	ldr	r6, DFT_ENABLE
+	mov	r10, $0
+	str	r10, [r6]
+
+	/*
+	 * Call board-specific lowlevel init.
+	 * That MUST be present and THAT returns
+	 * back to arch calling code with "mov pc, lr."
+	 */
+	b	dv_board_init
+
+.ltorg
+
+_PINMUX0:
+	.word	0x01c40000		/* Device Configuration Registers */
+_PINMUX1:
+	.word	0x01c40004		/* Device Configuration Registers */
+
+_DEV_SETTING:
+	.word	0x00000c1f
+
+WAITCFG:
+	.word	0x01e00004
+WAITCFG_VAL:
+	.word	0
+ACFG3:
+	.word	0x01e00014
+ACFG3_VAL:
+	.word	0x3ffffffd
+ACFG4:
+	.word	0x01e00018
+ACFG4_VAL:
+	.word	0x3ffffffd
+ACFG5:
+	.word	0x01e0001c
+ACFG5_VAL:
+	.word	0x3ffffffd
+
+MDCTL_DDR2:
+	.word	0x01c41a34
+MDSTAT_DDR2:
+	.word	0x01c41834
+
+PTCMD:
+	.word	0x01c41120
+PTSTAT:
+	.word	0x01c41128
+
+EINT_ENABLE0:
+	.word	0x01c48018
+EINT_ENABLE1:
+	.word	0x01c4801c
+
+PSC_FLAG_CLEAR:
+	.word	0xffffffe0
+PSC_GEM_FLAG_CLEAR:
+	.word	0xfffffeff
+
+/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
+DDRCTL:
+	.word	0x200000e4
+DDRCTL_VAL:
+	.word	0x50006405
+SDREF:
+	.word	0x2000000c
+SDREF_VAL:
+	.word	0x000005c3
+SDCFG:
+	.word	0x20000008
+SDCFG_VAL:
+#ifdef	DDR_4BANKS
+	.word	0x00178622
+#elif defined DDR_8BANKS
+	.word	0x00178632
+#else
+#error "Unknown DDR configuration!!!"
+#endif
+SDTIM0:
+	.word	0x20000010
+SDTIM0_VAL_162MHz:
+	.word	0x28923211
+SDTIM1:
+	.word	0x20000014
+SDTIM1_VAL_162MHz:
+	.word	0x0016c722
+VTPIOCR:
+	.word	0x200000f0	/* VTP IO Control register */
+DDRVTPR:
+	.word	0x01c42030	/* DDR VPTR MMR */
+VTP_MMR0:
+	.word	0x201f
+VTP_MMR1:
+	.word	0xa01f
+DFT_ENABLE:
+	.word	0x01c4004c
+VTP_LOCK_COUNT:
+	.word	0x5b0
+VTP_MASK:
+	.word	0xffffdfff
+VTP_RECAL:
+	.word	0x08000
+VTP_EN:
+	.word	0x02000
+CFGTEST:
+	.word	0x80010000
+MASK_VAL:
+	.word	0x00000fff
+
+/* GEM Power Up & LPSC Control Register */
+MDCTL_GEM:
+	.word	0x01c41a9c
+MDSTAT_GEM:
+	.word	0x01c4189c
+
+/* For WDT reset chip bug */
+P1394:
+	.word	0x01c41a20
+
+PLL_CLKSRC_MASK:
+	.word	0xfffffeff	/* Mask the Clock Mode bit */
+PLL_ENSRC_MASK:
+	.word	0xffffffdf	/* Select the PLLEN source */
+PLL_BYPASS_MASK:
+	.word	0xfffffffe	/* Put the PLL in BYPASS */
+PLL_RESET_MASK:
+	.word	0xfffffff7	/* Put the PLL in Reset Mode */
+PLL_PWRUP_MASK:
+	.word	0xfffffffd	/* PLL Power up Mask Bit  */
+PLL_DISABLE_ENABLE_MASK:
+	.word	0xffffffef	/* Enable the PLL from Disable */
+PLL_LOCK_COUNT:
+	.word	0x2000
+
+/* PLL1-SYSTEM PLL MMRs */
+PLL1_CTL:
+	.word	0x01c40900
+PLL1_PLLM:
+	.word	0x01c40910
+
+/* PLL2-SYSTEM PLL MMRs */
+PLL2_CTL:
+	.word	0x01c40d00
+PLL2_PLLM:
+	.word	0x01c40d10
+PLL2_DIV1:
+	.word	0x01c40d18
+PLL2_DIV2:
+	.word	0x01c40d1c
+PLL2_PLLCMD:
+	.word	0x01c40d38
+PLL2_PLLSTAT:
+	.word	0x01c40d3c
+PLL2_DIV_MASK:
+	.word	0xffff7fff
+
+MMARG_BRF0:
+	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
+MMARG_BRF0_VAL:
+	.word	0x00444400
+
+DDR2_START_ADDR:
+	.word	0x80000000
+DUMMY_VAL:
+	.word	0xa55aa55a
+#else /* CONFIG_SOC_DM644X */
+	mov pc, lr
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/lxt972.c
new file mode 100644
index 000000000..c482fd937
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/lxt972.c
@@ -0,0 +1,113 @@
+/*
+ * Intel LXT971/LXT972 PHY Driver for TI DaVinci
+ * (TMS320DM644x) based boards.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * --------------------------------------------------------
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <miiphy.h>
+#include <lxt971a.h>
+#include <asm/arch/emac_defs.h>
+#include "../../../../../drivers/net/davinci_emac.h"
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_CMD_NET
+
+int lxt972_is_phy_connected(int phy_addr)
+{
+	u_int16_t id1, id2;
+
+	if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
+		return(0);
+	if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
+		return(0);
+
+	if ((id1 == (0x0013)) && ((id2  & 0xfff0) == 0x78e0))
+		return(1);
+
+	return(0);
+}
+
+int lxt972_get_link_speed(int phy_addr)
+{
+	u_int16_t stat1, tmp;
+	volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
+
+	if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
+		return(0);
+
+	if (!(stat1 & PHY_LXT971_STAT2_LINK))	/* link up? */
+		return(0);
+
+	if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
+		return(0);
+
+	tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
+
+	davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
+	/* Read back */
+	if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
+		return(0);
+
+	/* Speed doesn't matter, there is no setting for it in EMAC... */
+	if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
+		/* set DM644x EMAC for Full Duplex  */
+		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
+			EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
+	} else {
+		/*set DM644x EMAC for Half Duplex  */
+		emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
+	}
+
+	return(1);
+}
+
+
+int lxt972_init_phy(int phy_addr)
+{
+	int ret = 1;
+
+	if (!lxt972_get_link_speed(phy_addr)) {
+		/* Try another time */
+		ret = lxt972_get_link_speed(phy_addr);
+	}
+
+	/* Disable PHY Interrupts */
+	davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
+
+	return(ret);
+}
+
+
+int lxt972_auto_negotiate(int phy_addr)
+{
+	u_int16_t tmp;
+
+	if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
+		return(0);
+
+	/* Restart Auto_negotiation  */
+	tmp |= BMCR_ANRESTART;
+	davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
+
+	/*check AutoNegotiate complete */
+	udelay (10000);
+	if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
+		return(0);
+
+	if (!(tmp & BMSR_ANEGCOMPLETE))
+		return(0);
+
+	return (lxt972_get_link_speed(phy_addr));
+}
+
+#endif	/* CONFIG_CMD_NET */
+
+#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/misc.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/misc.c
new file mode 100644
index 000000000..e18bdfc72
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/misc.c
@@ -0,0 +1,138 @@
+/*
+ * Miscelaneous DaVinci functions.
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_BUILD
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size(
+			(void *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_MAX_RAM_BANK_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+/*
+ * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
+ * Returns 1 if found, 0 otherwise.
+ */
+int dvevm_read_mac_address(uint8_t *buf)
+{
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
+	/* Read MAC address. */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
+		CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
+		goto i2cerr;
+
+	/* Check that MAC address is valid. */
+	if (!is_valid_ether_addr(buf))
+		goto err;
+
+	return 1; /* Found */
+
+i2cerr:
+	printf("Read from EEPROM @ 0x%02x failed\n",
+		CONFIG_SYS_I2C_EEPROM_ADDR);
+err:
+#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
+
+	return 0;
+}
+
+/*
+ * Set the mii mode as MII or RMII
+ */
+#if defined(CONFIG_SOC_DA8XX)
+void davinci_emac_mii_mode_sel(int mode_sel)
+{
+	int val;
+
+	val = readl(&davinci_syscfg_regs->cfgchip3);
+	if (mode_sel == 0)
+		val &= ~(1 << 8);
+	else
+		val |= (1 << 8);
+	writel(val, &davinci_syscfg_regs->cfgchip3);
+}
+#endif
+/*
+ * If there is no MAC address in the environment, then it will be initialized
+ * (silently) from the value in the EEPROM.
+ */
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
+{
+	uint8_t env_enetaddr[6];
+	int ret;
+
+	ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
+	if (!ret) {
+		/*
+		 * There is no MAC address in the environment, so we
+		 * initialize it from the value in the EEPROM.
+		 */
+		debug("### Setting environment from EEPROM MAC address = "
+			"\"%pM\"\n",
+			env_enetaddr);
+		ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
+	}
+	if (!ret)
+		printf("Failed to set mac address from EEPROM: %d\n", ret);
+}
+#endif	/* CONFIG_DRIVER_TI_EMAC */
+
+#if defined(CONFIG_SOC_DA8XX)
+#ifndef CONFIG_USE_IRQ
+void irq_init(void)
+{
+	/*
+	 * Mask all IRQs by clearing the global enable and setting
+	 * the enable clear for all the 90 interrupts.
+	 */
+	writel(0, &davinci_aintc_regs->ger);
+
+	writel(0, &davinci_aintc_regs->hier);
+
+	writel(0xffffffff, &davinci_aintc_regs->ecr1);
+	writel(0xffffffff, &davinci_aintc_regs->ecr2);
+	writel(0xffffffff, &davinci_aintc_regs->ecr3);
+}
+#endif
+
+/*
+ * Enable PSC for various peripherals.
+ */
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+				    const int n_items)
+{
+	int i;
+
+	for (i = 0; i < n_items; i++)
+		lpsc_on(item[i].lpsc_no);
+
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/pinmux.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/pinmux.c
new file mode 100644
index 000000000..e9d8c87cc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/pinmux.c
@@ -0,0 +1,90 @@
+/*
+ * DaVinci pinmux functions.
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+/*
+ * Change the setting of a pin multiplexer field.
+ *
+ * Takes an array of pinmux settings similar to:
+ *
+ * struct pinmux_config uart_pins[] = {
+ *	{ &davinci_syscfg_regs->pinmux[8], 2, 7 },
+ *	{ &davinci_syscfg_regs->pinmux[9], 2, 0 }
+ * };
+ *
+ * Stepping through the array, each pinmux[n] register has the given value
+ * set in the pin mux field specified.
+ *
+ * The number of pins in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Returns 0 if all field numbers and values are in the correct range,
+ * else returns -1.
+ */
+int davinci_configure_pin_mux(const struct pinmux_config *pins,
+			      const int n_pins)
+{
+	int i;
+
+	/* check for invalid pinmux values */
+	for (i = 0; i < n_pins; i++) {
+		if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
+		    (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
+			return -1;
+	}
+
+	/* configure the pinmuxes */
+	for (i = 0; i < n_pins; i++) {
+		const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
+		const unsigned int value = pins[i].value << offset;
+		const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
+		const dv_reg *mux = pins[i].mux;
+
+		writel(value | (readl(mux) & (~mask)), mux);
+	}
+
+	return 0;
+}
+
+/*
+ * Configure multiple pinmux resources.
+ *
+ * Takes an pinmux_resource array of pinmux_config and pin counts:
+ *
+ * const struct pinmux_resource pinmuxes[] = {
+ *	PINMUX_ITEM(uart_pins),
+ *	PINMUX_ITEM(i2c_pins),
+ * };
+ *
+ * The number of items in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Each item entry is configured in the defined order. If configuration
+ * of any item fails, -1 is returned and none of the following items are
+ * configured. On success, 0 is returned.
+ */
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+				    const int n_items)
+{
+	int i;
+
+	for (i = 0; i < n_items; i++) {
+		if (davinci_configure_pin_mux(item[i].pins,
+					      item[i].n_pins) != 0)
+			return -1;
+	}
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/psc.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/psc.c
new file mode 100644
index 000000000..8d99e2e99
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/psc.c
@@ -0,0 +1,160 @@
+/*
+ * Power and Sleep Controller (PSC) functions.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/*
+ * The PSC manages three inputs to a "module" which may be a peripheral or
+ * CPU.  Those inputs are the module's:  clock; reset signal; and sometimes
+ * its power domain.  For our purposes, we only care whether clock and power
+ * are active, and the module is out of reset.
+ *
+ * DaVinci chips may include two separate power domains: "Always On" and "DSP".
+ * Chips without a DSP generally have only one domain.
+ *
+ * The "Always On" power domain is always on when the chip is on, and is
+ * powered by the VDD pins (on DM644X). The majority of DaVinci modules
+ * lie within the "Always On" power domain.
+ *
+ * A separate domain called the "DSP" domain houses the C64x+ and other video
+ * hardware such as VICP. In some chips, the "DSP" domain is not always on.
+ * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
+ */
+
+/* Works on Always On power domain only (no PD argument) */
+static void lpsc_transition(unsigned int id, unsigned int state)
+{
+	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
+#ifdef CONFIG_SOC_DA8XX
+	struct davinci_psc_regs *psc_regs;
+#endif
+
+#ifndef CONFIG_SOC_DA8XX
+	if (id >= DAVINCI_LPSC_GEM)
+		return;			/* Don't work on DSP Power Domain */
+
+	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+	ptstat = REG_P(PSC_PTSTAT);
+	ptcmd = REG_P(PSC_PTCMD);
+#else
+	if (id < DAVINCI_LPSC_PSC1_BASE) {
+		if (id >= PSC_PSC0_MODULE_ID_CNT)
+			return;
+		psc_regs = davinci_psc0_regs;
+		mdstat = &psc_regs->psc0.mdstat[id];
+		mdctl = &psc_regs->psc0.mdctl[id];
+	} else {
+		id -= DAVINCI_LPSC_PSC1_BASE;
+		if (id >= PSC_PSC1_MODULE_ID_CNT)
+			return;
+		psc_regs = davinci_psc1_regs;
+		mdstat = &psc_regs->psc1.mdstat[id];
+		mdctl = &psc_regs->psc1.mdctl[id];
+	}
+	ptstat = &psc_regs->ptstat;
+	ptcmd = &psc_regs->ptcmd;
+#endif
+
+	while (readl(ptstat) & 0x01)
+		continue;
+
+	if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
+		return; /* Already in that state */
+
+	writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
+
+	switch (id) {
+#ifdef CONFIG_SOC_DM644X
+	/* Special treatment for some modules as for sprue14 p.7.4.2 */
+	case DAVINCI_LPSC_VPSSSLV:
+	case DAVINCI_LPSC_EMAC:
+	case DAVINCI_LPSC_EMAC_WRAPPER:
+	case DAVINCI_LPSC_MDIO:
+	case DAVINCI_LPSC_USB:
+	case DAVINCI_LPSC_ATA:
+	case DAVINCI_LPSC_VLYNQ:
+	case DAVINCI_LPSC_UHPI:
+	case DAVINCI_LPSC_DDR_EMIF:
+	case DAVINCI_LPSC_AEMIF:
+	case DAVINCI_LPSC_MMC_SD:
+	case DAVINCI_LPSC_MEMSTICK:
+	case DAVINCI_LPSC_McBSP:
+	case DAVINCI_LPSC_GPIO:
+		writel(readl(mdctl) | 0x200, mdctl);
+		break;
+#endif
+	}
+
+	writel(0x01, ptcmd);
+
+	while (readl(ptstat) & 0x01)
+		continue;
+	while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
+		continue;
+}
+
+void lpsc_on(unsigned int id)
+{
+	lpsc_transition(id, 0x03);
+}
+
+void lpsc_syncreset(unsigned int id)
+{
+	lpsc_transition(id, 0x01);
+}
+
+void lpsc_disable(unsigned int id)
+{
+	lpsc_transition(id, 0x0);
+}
+
+/* Not all DaVinci chips have a DSP power domain. */
+#ifdef CONFIG_SOC_DM644X
+
+/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+void dsp_on(void)
+{
+	int i;
+
+	if (REG(PSC_PDSTAT1) & 0x1f)
+		return;			/* Already on */
+
+	REG(PSC_GBLCTL) |= 0x01;
+	REG(PSC_PDCTL1) |= 0x01;
+	REG(PSC_PDCTL1) &= ~0x100;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+	REG(PSC_PTCMD) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (REG(PSC_EPCPR) & 0x02)
+			break;
+	}
+
+	REG(PSC_CHP_SHRTSW) = 0x01;
+	REG(PSC_PDCTL1) |= 0x100;
+	REG(PSC_EPCCR) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (!(REG(PSC_PTSTAT) & 0x02))
+			break;
+	}
+
+	REG(PSC_GBLCTL) &= ~0x1f;
+}
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+#endif /* have a DSP */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/reset.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/reset.c
new file mode 100644
index 000000000..6b0f15428
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/reset.c
@@ -0,0 +1,32 @@
+/*
+ *  Processor reset using WDT.
+ *
+ * Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer_defs.h>
+#include <asm/arch/hardware.h>
+
+void reset_cpu(unsigned long a)
+{
+	struct davinci_timer *const wdttimer =
+		(struct davinci_timer *)DAVINCI_WDOG_BASE;
+	writel(0x08, &wdttimer->tgcr);
+	writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
+	writel(0, &wdttimer->tim12);
+	writel(0, &wdttimer->tim34);
+	writel(0, &wdttimer->prd12);
+	writel(0, &wdttimer->prd34);
+	writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr);
+	writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr);
+	writel(0xa5c64000, &wdttimer->wdtcr);
+	writel(0xda7e4000, &wdttimer->wdtcr);
+	writel(0x4000, &wdttimer->wdtcr);
+	while (1)
+		/*nothing*/;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/spl.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/spl.c
new file mode 100644
index 000000000..59b304efc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <spl.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <nand.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <spi_flash.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
+}
+#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
+
+void board_init_f(ulong dummy)
+{
+	/* First, setup our stack pointer. */
+	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+	/* Second, perform our low-level init. */
+#ifdef CONFIG_SOC_DM365
+	dm36x_lowlevel_init(0);
+#endif
+#ifdef CONFIG_SOC_DA8XX
+	arch_cpu_init();
+#endif
+
+	/* Third, we clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Finally, setup gd and move to the next step. */
+	gd = &gdata;
+	board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
+
+u32 spl_boot_mode(void)
+{
+	return MMCSD_MODE_RAW;
+}
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_NAND_SIMPLE
+	return BOOT_DEVICE_NAND;
+#elif defined(CONFIG_SPL_SPI_LOAD)
+	return BOOT_DEVICE_SPI;
+#elif defined(CONFIG_SPL_MMC_LOAD)
+	return BOOT_DEVICE_MMC1;
+#else
+	puts("Unknown boot device\n");
+	hang();
+#endif
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/timer.c
new file mode 100644
index 000000000..c7d0652e8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/davinci/timer.c
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer_defs.h>
+#include <div64.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct davinci_timer * const timer =
+	(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+#define TIM_CLK_DIV	16
+
+int timer_init(void)
+{
+	/* We are using timer34 in unchained 32-bit mode, full speed */
+	writel(0x0, &timer->tcr);
+	writel(0x0, &timer->tgcr);
+	writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
+	writel(0x0, &timer->tim34);
+	writel(TIMER_LOAD_VAL, &timer->prd34);
+	writel(2 << 22, &timer->tcr);
+	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+	gd->arch.timer_reset_value = 0;
+
+	return(0);
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+	unsigned long now = readl(&timer->tim34);
+
+	/* increment tbu if tbl has rolled over */
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
+
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+ulong get_timer(ulong base)
+{
+	unsigned long long timer_diff;
+
+	timer_diff = get_ticks() - gd->arch.timer_reset_value;
+
+	return lldiv(timer_diff,
+		     (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long endtime;
+
+	endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
+			1000000UL);
+	endtime += get_ticks();
+
+	while (get_ticks() < endtime)
+		;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return gd->arch.timer_rate_hz;
+}
+
+#ifdef CONFIG_HW_WATCHDOG
+static struct davinci_timer * const wdttimer =
+	(struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
+
+/*
+ * See prufw2.pdf for using Timer as a WDT
+ */
+void davinci_hw_watchdog_enable(void)
+{
+	writel(0x0, &wdttimer->tcr);
+	writel(0x0, &wdttimer->tgcr);
+	/* TIMMODE = 2h */
+	writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
+	writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
+	writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
+	writel(2 << 22, &wdttimer->tcr);
+	writel(0x0, &wdttimer->tim12);
+	writel(0x0, &wdttimer->tim34);
+	/* set WDEN bit, WDKEY 0xa5c6 */
+	writel(0xa5c64000, &wdttimer->wdtcr);
+	/* clear counter register */
+	writel(0xda7e4000, &wdttimer->wdtcr);
+}
+
+void davinci_hw_watchdog_reset(void)
+{
+	writel(0xa5c64000, &wdttimer->wdtcr);
+	writel(0xda7e4000, &wdttimer->wdtcr);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/Makefile
new file mode 100644
index 000000000..c230ce899
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= cpu.o
+obj-y	+= dram.o
+obj-y	+= mpp.o
+obj-y	+= timer.o
+obj-y	+= cache.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/cache.c
new file mode 100644
index 000000000..e18a3097d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/cache.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
+
+void l2_cache_disable()
+{
+	u32 ctrl;
+
+	ctrl = readfr_extra_feature_reg();
+	ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
+	writefr_extra_feature_reg(ctrl);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
new file mode 100644
index 000000000..d4711c070
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -0,0 +1,380 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <u-boot/md5.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <hush.h>
+
+#define BUFLEN	16
+
+void reset_cpu(unsigned long ignored)
+{
+	struct kwcpu_registers *cpureg =
+	    (struct kwcpu_registers *)KW_CPU_REG_BASE;
+
+	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+		&cpureg->rstoutn_mask);
+	writel(readl(&cpureg->sys_soft_rst) | 1,
+		&cpureg->sys_soft_rst);
+	while (1) ;
+}
+
+/*
+ * Generates Ramdom hex number reading some time varient system registers
+ * and using md5 algorithm
+ */
+unsigned char get_random_hex(void)
+{
+	int i;
+	u32 inbuf[BUFLEN];
+	u8 outbuf[BUFLEN];
+
+	/*
+	 * in case of 88F6281/88F6282/88F6192 A0,
+	 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
+	 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
+	 * reserved regs and does not have names at this moment
+	 * (no errata available)
+	 */
+	writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
+	for (i = 0; i < BUFLEN; i++) {
+		inbuf[i] = readl(KW_REG_UNDOC_0x1470);
+	}
+	md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
+	return outbuf[outbuf[7] % 0x0f];
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int kw_winctrl_calcsize(unsigned int sizeval)
+{
+	int i;
+	unsigned int j = 0;
+	u32 val = sizeval >> 1;
+
+	for (i = 0; val >= 0x10000; i++) {
+		j |= (1 << i);
+		val = val >> 1;
+	}
+	return (0x0000ffff & j);
+}
+
+/*
+ * kw_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Kirkwood Soc to addess different
+ * devices. Each window can be configured for size, BAR and remap addr
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ *
+ * Reference Documentation:
+ * Mbus-L to Mbus Bridge Registers Configuration.
+ * (Sec 25.1 and 25.3 of Datasheet)
+ */
+int kw_config_adr_windows(void)
+{
+	struct kwwin_registers *winregs =
+		(struct kwwin_registers *)KW_CPU_WIN_BASE;
+
+	/* Window 0: PCIE MEM address space */
+	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
+		KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
+
+	writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
+	writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
+	writel(0x0, &winregs[0].remap_hi);
+
+	/* Window 1: PCIE IO address space */
+	writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
+		KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
+	writel(KW_DEFADR_PCI_IO, &winregs[1].base);
+	writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
+	writel(0x0, &winregs[1].remap_hi);
+
+	/* Window 2: NAND Flash address space */
+	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
+		KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
+	writel(KW_DEFADR_NANDF, &winregs[2].base);
+	writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
+	writel(0x0, &winregs[2].remap_hi);
+
+	/* Window 3: SPI Flash address space */
+	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
+		KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
+	writel(KW_DEFADR_SPIF, &winregs[3].base);
+	writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
+	writel(0x0, &winregs[3].remap_hi);
+
+	/* Window 4: BOOT Memory address space */
+	writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
+		KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
+	writel(KW_DEFADR_BOOTROM, &winregs[4].base);
+
+	/* Window 5: Security SRAM address space */
+	writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
+		KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
+	writel(KW_DEFADR_SASRAM, &winregs[5].base);
+
+	/* Window 6-7: Disabled */
+	writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
+	writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
+
+	return 0;
+}
+
+/*
+ * kw_config_gpio - GPIO configuration
+ */
+void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
+{
+	struct kwgpio_registers *gpio0reg =
+		(struct kwgpio_registers *)KW_GPIO0_BASE;
+	struct kwgpio_registers *gpio1reg =
+		(struct kwgpio_registers *)KW_GPIO1_BASE;
+
+	/* Init GPIOS to default values as per board requirement */
+	writel(gpp0_oe_val, &gpio0reg->dout);
+	writel(gpp1_oe_val, &gpio1reg->dout);
+	writel(gpp0_oe, &gpio0reg->oe);
+	writel(gpp1_oe, &gpio1reg->oe);
+}
+
+/*
+ * kw_config_mpp - Multi-Purpose Pins Functionality configuration
+ *
+ * Each MPP can be configured to different functionality through
+ * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
+ *
+ * There are maximum 64 Multi-Pourpose Pins on Kirkwood
+ * Each MPP functionality can be configuration by a 4bit value
+ * of MPP control reg, the value and associated functionality depends
+ * upon used SoC varient
+ */
+int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
+		u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
+{
+	u32 *mppreg = (u32 *) KW_MPP_BASE;
+
+	/* program mpp registers */
+	writel(mpp0_7, &mppreg[0]);
+	writel(mpp8_15, &mppreg[1]);
+	writel(mpp16_23, &mppreg[2]);
+	writel(mpp24_31, &mppreg[3]);
+	writel(mpp32_39, &mppreg[4]);
+	writel(mpp40_47, &mppreg[5]);
+	writel(mpp48_55, &mppreg[6]);
+	return 0;
+}
+
+/*
+ * SYSRSTn Duration Counter Support
+ *
+ * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
+ * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
+ * The SYSRSTn duration counter is useful for implementing a manufacturer
+ * or factory reset. Upon a long reset assertion that is greater than a
+ * pre-configured environment variable value for sysrstdelay,
+ * The counter value is stored in the SYSRSTn Length Counter Register
+ * The counter is based on the 25-MHz reference clock (40ns)
+ * It is a 29-bit counter, yielding a maximum counting duration of
+ * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
+ * it remains at this value until counter reset is triggered by setting
+ * bit 31 of KW_REG_SYSRST_CNT
+ */
+static void kw_sysrst_action(void)
+{
+	int ret;
+	char *s = getenv("sysrstcmd");
+
+	if (!s) {
+		debug("Error.. %s failed, check sysrstcmd\n",
+			__FUNCTION__);
+		return;
+	}
+
+	debug("Starting %s process...\n", __FUNCTION__);
+	ret = run_command(s, 0);
+	if (ret < 0)
+		debug("Error.. %s failed\n", __FUNCTION__);
+	else
+		debug("%s process finished\n", __FUNCTION__);
+}
+
+static void kw_sysrst_check(void)
+{
+	u32 sysrst_cnt, sysrst_dly;
+	char *s;
+
+	/*
+	 * no action if sysrstdelay environment variable is not defined
+	 */
+	s = getenv("sysrstdelay");
+	if (s == NULL)
+		return;
+
+	/* read sysrstdelay value */
+	sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
+
+	/* read SysRst Length counter register (bits 28:0) */
+	sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
+	debug("H/w Rst hold time: %d.%d secs\n",
+		sysrst_cnt / SYSRST_CNT_1SEC_VAL,
+		sysrst_cnt % SYSRST_CNT_1SEC_VAL);
+
+	/* clear the counter for next valid read*/
+	writel(1 << 31, KW_REG_SYSRST_CNT);
+
+	/*
+	 * sysrst_action:
+	 * if H/w Reset key is pressed and hold for time
+	 * more than sysrst_dly in seconds
+	 */
+	if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
+		kw_sysrst_action();
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char *rev;
+	u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
+	u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
+
+	if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
+		printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
+		return -1;
+	}
+
+	switch (revid) {
+	case 0:
+		rev = "Z0";
+		break;
+	case 2:
+		rev = "A0";
+		break;
+	case 3:
+		rev = "A1";
+		break;
+	default:
+		rev = "??";
+		break;
+	}
+
+	printf("SoC:   Kirkwood 88F%04x_%s\n", devid, rev);
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	u32 reg;
+	struct kwcpu_registers *cpureg =
+		(struct kwcpu_registers *)KW_CPU_REG_BASE;
+
+	/* Linux expects` the internal registers to be at 0xf1000000 */
+	writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
+
+	/* Enable and invalidate L2 cache in write through mode */
+	writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
+	invalidate_l2_cache();
+
+	kw_config_adr_windows();
+
+#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
+	/*
+	 * Configures the I/O voltage of the pads connected to Egigabit
+	 * Ethernet interface to 1.8V
+	 * By default it is set to 3.3V
+	 */
+	reg = readl(KW_REG_MPP_OUT_DRV_REG);
+	reg |= (1 << 7);
+	writel(reg, KW_REG_MPP_OUT_DRV_REG);
+#endif
+#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
+	/*
+	 * Set egiga port0/1 in normal functional mode
+	 * This is required becasue on kirkwood by default ports are in reset mode
+	 * OS egiga driver may not have provision to set them in normal mode
+	 * and if u-boot is build without network support, network may fail at OS level
+	 */
+	reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
+	reg &= ~(1 << 4);	/* Clear PortReset Bit */
+	writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
+	reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
+	reg &= ~(1 << 4);	/* Clear PortReset Bit */
+	writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
+#endif
+#ifdef CONFIG_KIRKWOOD_PCIE_INIT
+	/*
+	 * Enable PCI Express Port0
+	 */
+	reg = readl(&cpureg->ctrl_stat);
+	reg |= (1 << 0);	/* Set PEX0En Bit */
+	writel(reg, &cpureg->ctrl_stat);
+#endif
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+	volatile u32 temp;
+
+	/*CPU streaming & write allocate */
+	temp = readfr_extra_feature_reg();
+	temp &= ~(1 << 28);	/* disable wr alloc */
+	writefr_extra_feature_reg(temp);
+
+	temp = readfr_extra_feature_reg();
+	temp &= ~(1 << 29);	/* streaming disabled */
+	writefr_extra_feature_reg(temp);
+
+	/* L2Cache settings */
+	temp = readfr_extra_feature_reg();
+	/* Disable L2C pre fetch - Set bit 24 */
+	temp |= (1 << 24);
+	/* enable L2C - Set bit 22 */
+	temp |= (1 << 22);
+	writefr_extra_feature_reg(temp);
+
+	icache_enable();
+	/* Change reset vector to address 0x0 */
+	temp = get_cr();
+	set_cr(temp & ~CR_V);
+
+	/* checks and execute resset to factory event */
+	kw_sysrst_check();
+
+	return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_MVGBE
+int cpu_eth_init(bd_t *bis)
+{
+	mvgbe_initialize(bis);
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/dram.c
new file mode 100644
index 000000000..d73ae47c3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/dram.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct kw_sdram_bank {
+	u32	win_bar;
+	u32	win_sz;
+};
+
+struct kw_sdram_addr_dec {
+	struct kw_sdram_bank	sdram_bank[4];
+};
+
+#define KW_REG_CPUCS_WIN_ENABLE		(1 << 0)
+#define KW_REG_CPUCS_WIN_WR_PROTECT	(1 << 1)
+#define KW_REG_CPUCS_WIN_WIN0_CS(x)	(((x) & 0x3) << 2)
+#define KW_REG_CPUCS_WIN_SIZE(x)	(((x) & 0xff) << 24)
+
+/*
+ * kw_sdram_bar - reads SDRAM Base Address Register
+ */
+u32 kw_sdram_bar(enum memory_bank bank)
+{
+	struct kw_sdram_addr_dec *base =
+		(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+	u32 result = 0;
+	u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
+
+	if ((!enable) || (bank > BANK3))
+		return 0;
+
+	result = readl(&base->sdram_bank[bank].win_bar);
+	return result;
+}
+
+/*
+ * kw_sdram_bs_set - writes SDRAM Bank size
+ */
+static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
+{
+	struct kw_sdram_addr_dec *base =
+		(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+	/* Read current register value */
+	u32 reg = readl(&base->sdram_bank[bank].win_sz);
+
+	/* Clear window size */
+	reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
+
+	/* Set new window size */
+	reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
+
+	writel(reg, &base->sdram_bank[bank].win_sz);
+}
+
+/*
+ * kw_sdram_bs - reads SDRAM Bank size
+ */
+u32 kw_sdram_bs(enum memory_bank bank)
+{
+	struct kw_sdram_addr_dec *base =
+		(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+	u32 result = 0;
+	u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
+
+	if ((!enable) || (bank > BANK3))
+		return 0;
+	result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
+	result += 0x01000000;
+	return result;
+}
+
+void kw_sdram_size_adjust(enum memory_bank bank)
+{
+	u32 size;
+
+	/* probe currently equipped RAM size */
+	size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
+
+	/* adjust SDRAM window size accordingly */
+	kw_sdram_bs_set(bank, size);
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
new file mode 100644
index 000000000..0ba6f098c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
@@ -0,0 +1,90 @@
+/*
+ * arch/arm/mach-kirkwood/mpp.c
+ *
+ * MPP functions for Marvell Kirkwood SoCs
+ * Referenced from Linux kernel source
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+
+static u32 kirkwood_variant(void)
+{
+	switch (readl(KW_REG_DEVICE_ID) & 0x03) {
+	case 1:
+		return MPP_F6192_MASK;
+	case 2:
+		return MPP_F6281_MASK;
+	default:
+		debug("MPP setup: unknown kirkwood variant\n");
+		return 0;
+	}
+}
+
+#define MPP_CTRL(i)	(KW_MPP_BASE + (i* 4))
+#define MPP_NR_REGS	(1 + MPP_MAX/8)
+
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
+{
+	u32 mpp_ctrl[MPP_NR_REGS];
+	unsigned int variant_mask;
+	int i;
+
+	variant_mask = kirkwood_variant();
+	if (!variant_mask)
+		return;
+
+	debug( "initial MPP regs:");
+	for (i = 0; i < MPP_NR_REGS; i++) {
+		mpp_ctrl[i] = readl(MPP_CTRL(i));
+		debug(" %08x", mpp_ctrl[i]);
+	}
+	debug("\n");
+
+
+	while (*mpp_list) {
+		unsigned int num = MPP_NUM(*mpp_list);
+		unsigned int sel = MPP_SEL(*mpp_list);
+		unsigned int sel_save;
+		int shift;
+
+		if (num > MPP_MAX) {
+			debug("kirkwood_mpp_conf: invalid MPP "
+					"number (%u)\n", num);
+			continue;
+		}
+		if (!(*mpp_list & variant_mask)) {
+			debug("kirkwood_mpp_conf: requested MPP%u config "
+				"unavailable on this hardware\n", num);
+			continue;
+		}
+
+		shift = (num & 7) << 2;
+
+		if (mpp_save) {
+			sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf;
+			*mpp_save = num | (sel_save << 8) | variant_mask;
+			mpp_save++;
+		}
+
+		mpp_ctrl[num / 8] &= ~(0xf << shift);
+		mpp_ctrl[num / 8] |= sel << shift;
+
+		mpp_list++;
+	}
+
+	debug("  final MPP regs:");
+	for (i = 0; i < MPP_NR_REGS; i++) {
+		writel(mpp_ctrl[i], MPP_CTRL(i));
+		debug(" %08x", mpp_ctrl[i]);
+	}
+	debug("\n");
+
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/timer.c
new file mode 100644
index 000000000..a08f4a145
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/kirkwood/timer.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/kirkwood.h>
+
+#define UBOOT_CNTR	0	/* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct kwtmr_val {
+	u32 reload;	/* Timer reload reg */
+	u32 val;	/* Timer value reg */
+};
+
+/* Timer registers */
+struct kwtmr_registers {
+	u32 ctrl;	/* Timer control reg */
+	u32 pad[3];
+	struct kwtmr_val tmr[2];
+	u32 wdt_reload;
+	u32 wdt_val;
+};
+
+struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG			&kwtmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum)	&kwtmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum)		&kwtmr_regs->tmr[tmrnum].val
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS		0
+#define TRG_ARM_TIMER_REL_MASK		0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS		0
+#define TVR_ARM_TIMER_MASK		0xffffffff
+#define TVR_ARM_TIMER_MAX		0xffffffff
+#define TIMER_LOAD_VAL 			0xffffffff
+
+#define READ_TIMER			(readl(CNTMR_VAL_REG(UBOOT_CNTR)) /	\
+					 (CONFIG_SYS_TCLK / 1000))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER;
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec +
+			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	uint current;
+	ulong delayticks;
+
+	current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
+	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+	if (current < delayticks) {
+		delayticks -= current;
+		while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
+		while ((TIMER_LOAD_VAL - delayticks) <
+			readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
+	} else {
+		while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
+			(current - delayticks)) ;
+	}
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+	unsigned int cntmrctrl;
+
+	/* load value into timer */
+	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+	/* enable timer in auto reload mode */
+	cntmrctrl = readl(CNTMR_CTRL_REG);
+	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+	writel(cntmrctrl, CNTMR_CTRL_REG);
+
+	/* init the timestamp and lastdec value */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
new file mode 100644
index 000000000..314f004eb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y   = cpu.o clk.o devices.o timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
new file mode 100644
index 000000000..b7a44d59d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+
+unsigned int get_sys_clk_rate(void)
+{
+	if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
+		return RTC_CLK_FREQUENCY * 397;
+	else
+		return OSC_CLK_FREQUENCY;
+}
+
+unsigned int get_hclk_pll_rate(void)
+{
+	unsigned long long fin, fref, fcco, fout;
+	u32 val, m_div, n_div, p_div;
+
+	/*
+	 * Valid frequency ranges:
+	 *     1 * 10^6 <=  Fin <=  20 * 10^6
+	 *     1 * 10^6 <= Fref <=  27 * 10^6
+	 *   156 * 10^6 <= Fcco <= 320 * 10^6
+	 */
+
+	fref = fin = get_sys_clk_rate();
+	if (fin > 20000000ULL || fin < 1000000ULL)
+		return 0;
+
+	val = readl(&clk->hclkpll_ctrl);
+	m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
+	n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
+	if (val & CLK_HCLK_PLL_DIRECT)
+		p_div = 0;
+	else
+		p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
+	p_div = 1 << p_div;
+
+	if (val & CLK_HCLK_PLL_BYPASS) {
+		do_div(fin, p_div);
+		return fin;
+	}
+
+	do_div(fref, n_div);
+	if (fref > 27000000ULL || fref < 1000000ULL)
+		return 0;
+
+	fout = fref * m_div;
+	if (val & CLK_HCLK_PLL_FEEDBACK) {
+		fcco = fout;
+		do_div(fout, p_div);
+	} else
+		fcco = fout * p_div;
+
+	if (fcco > 320000000ULL || fcco < 156000000ULL)
+		return 0;
+
+	return fout;
+}
+
+unsigned int get_hclk_clk_div(void)
+{
+	u32 val;
+
+	val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
+
+	return 1 << val;
+}
+
+unsigned int get_hclk_clk_rate(void)
+{
+	return get_hclk_pll_rate() / get_hclk_clk_div();
+}
+
+unsigned int get_periph_clk_div(void)
+{
+	u32 val;
+
+	val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
+
+	return (val >> 2) + 1;
+}
+
+unsigned int get_periph_clk_rate(void)
+{
+	if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
+		return get_sys_clk_rate();
+
+	return get_hclk_pll_rate() / get_periph_clk_div();
+}
+
+int get_serial_clock(void)
+{
+	return get_periph_clk_rate();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
new file mode 100644
index 000000000..35095a958
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/wdt.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct wdt_regs  *wdt = (struct wdt_regs *)WDT_BASE;
+
+void reset_cpu(ulong addr)
+{
+	/* Enable watchdog clock */
+	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+
+	/* Reset pulse length is 13005 peripheral clock frames */
+	writel(13000, &wdt->pulse);
+
+	/* Force WDOG_RESET2 and RESOUT_N signal active */
+	writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
+	       &wdt->mctrl);
+
+	while (1)
+		/* NOP */;
+}
+
+#if defined(CONFIG_ARCH_CPU_INIT)
+int arch_cpu_init(void)
+{
+	/*
+	 * It might be necessary to flush data cache, if U-boot is loaded
+	 * from kickstart bootloader, e.g. from S1L loader
+	 */
+	flush_dcache_all();
+
+	return 0;
+}
+#else
+#error "You have to select CONFIG_ARCH_CPU_INIT"
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	printf("CPU:   NXP LPC32XX\n");
+	printf("CPU clock:        %uMHz\n", get_hclk_pll_rate() / 1000000);
+	printf("AHB bus clock:    %uMHz\n", get_hclk_clk_rate() / 1000000);
+	printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
+
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
new file mode 100644
index 000000000..b5676578f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/uart.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs    *clk  = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+
+void lpc32xx_uart_init(unsigned int uart_id)
+{
+	if (uart_id < 1 || uart_id > 7)
+		return;
+
+	/* Disable loopback mode, if it is set by S1L bootloader */
+	clrbits_le32(&ctrl->loop,
+		     UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
+
+	if (uart_id < 3 || uart_id > 6)
+		return;
+
+	/* Enable UART system clock */
+	setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
+
+	/* Set UART into autoclock mode */
+	clrsetbits_le32(&ctrl->clkmode,
+			UART_CLKMODE_MASK(uart_id),
+			UART_CLKMODE_AUTO(uart_id));
+
+	/* Bypass pre-divider of UART clock */
+	writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
+	       &clk->u3clk + (uart_id - 3));
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
new file mode 100644
index 000000000..dc1217e69
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/timer.h>
+#include <asm/io.h>
+
+static struct timer_regs  *timer0 = (struct timer_regs *)TIMER0_BASE;
+static struct timer_regs  *timer1 = (struct timer_regs *)TIMER1_BASE;
+static struct clk_pm_regs *clk    = (struct clk_pm_regs *)CLK_PM_BASE;
+
+static void lpc32xx_timer_clock(u32 bit, int enable)
+{
+	if (enable)
+		setbits_le32(&clk->timclk_ctrl1, bit);
+	else
+		clrbits_le32(&clk->timclk_ctrl1, bit);
+}
+
+static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
+{
+	writel(TIMER_TCR_COUNTER_RESET,   &timer->tcr);
+	writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
+	writel(0, &timer->tc);
+	writel(0, &timer->pr);
+
+	/* Count mode is every rising PCLK edge */
+	writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
+
+	/* Set prescale counter value */
+	writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
+}
+
+static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
+{
+	if (enable)
+		writel(TIMER_TCR_COUNTER_ENABLE,  &timer->tcr);
+	else
+		writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
+}
+
+int timer_init(void)
+{
+	lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
+	lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
+	lpc32xx_timer_count(timer0, 1);
+
+	return 0;
+}
+
+ulong get_timer(ulong base)
+{
+	return readl(&timer0->tc) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
+	lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
+	lpc32xx_timer_count(timer1, 1);
+
+	while (readl(&timer1->tc) < usec)
+		/* NOP */;
+
+	lpc32xx_timer_count(timer1, 0);
+	lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
new file mode 100644
index 000000000..365892c41
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= clock.o reset.o timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
new file mode 100644
index 000000000..1f6f66eba
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * Get the peripheral bus frequency depending on pll pin settings
+ */
+ulong get_bus_freq(ulong dummy)
+{
+	struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
+					MB86R0x_CRG_BASE;
+	uint32_t pllmode;
+
+	pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE;
+
+	if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20)
+		return 40000000;
+
+	return 41164767;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
new file mode 100644
index 000000000..7bd77ff20
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * Reset the cpu by setting software reset request bit
+ */
+void reset_cpu(ulong ignored)
+{
+	struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
+					MB86R0x_CRG_BASE;
+
+	writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr);
+	while (1)
+		/* NOP */;
+	/* Never reached */
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
new file mode 100644
index 000000000..bb078196d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2010
+ * Matthias Weisser, Graf-Syteco <weisserm@arcor.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <div64.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#define TIMER_LOAD_VAL	0xffffffff
+#define TIMER_FREQ	(CONFIG_MB86R0x_IOCLK  / 256)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, TIMER_FREQ);
+
+	return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+	usec *= TIMER_FREQ;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init(void)
+{
+	struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
+					MB86R0x_TIMER_BASE;
+	ulong ctrl = readl(&timer->control);
+
+	writel(TIMER_LOAD_VAL, &timer->load);
+
+	ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S |
+		MB86R0x_TIMER_SIZE_32;
+
+	writel(ctrl, &timer->control);
+
+	/* capture current value time */
+	lastdec = readl(&timer->value);
+	timestamp = 0; /* start "advancing" time stamp from 0 */
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long long get_ticks(void)
+{
+	struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
+					MB86R0x_TIMER_BASE;
+	ulong now = readl(&timer->value);
+
+	if (now <= lastdec) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolut diff ticks */
+		timestamp += lastdec - now;
+	} else {
+		/* we have rollover of incrementer */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+	lastdec = now;
+	return timestamp;
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = usec_to_tick(usec);
+	tmp = get_ticks();			/* get current timestamp */
+
+	while ((get_ticks() - tmp) < tmo)	/* loop till event */
+		 /*NOP*/;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+	tbclk = TIMER_FREQ;
+	return tbclk;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/Makefile
new file mode 100644
index 000000000..134c69d42
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	= generic.o timer.o reset.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/generic.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/generic.c
new file mode 100644
index 000000000..4e9c0b548
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -0,0 +1,249 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on mx27/generic.c:
+ *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+/*
+ *  get the system pll clock in Hz
+ *
+ *                  mfi + mfn / (mfd +1)
+ *  f = 2 * f_ref * --------------------
+ *                        pd + 1
+ */
+static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+{
+	unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
+	    & CCM_PLL_MFI_MASK;
+	int mfn = (pll >> CCM_PLL_MFN_SHIFT)
+	    & CCM_PLL_MFN_MASK;
+	unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
+	    & CCM_PLL_MFD_MASK;
+	unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
+	    & CCM_PLL_PD_MASK;
+
+	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
+	mfd += 1;
+	pd += 1;
+
+	return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
+		     mfd * pd);
+}
+
+static ulong imx_get_mpllclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = MXC_HCLK;
+
+	return imx_decode_pll(readl(&ccm->mpctl), fref);
+}
+
+static ulong imx_get_armclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong cctl = readl(&ccm->cctl);
+	ulong fref = imx_get_mpllclk();
+	ulong div;
+
+	if (cctl & CCM_CCTL_ARM_SRC)
+		fref = lldiv((u64) fref * 3, 4);
+
+	div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
+	       & CCM_CCTL_ARM_DIV_MASK) + 1;
+
+	return fref / div;
+}
+
+static ulong imx_get_ahbclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong cctl = readl(&ccm->cctl);
+	ulong fref = imx_get_armclk();
+	ulong div;
+
+	div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
+	       & CCM_CCTL_AHB_DIV_MASK) + 1;
+
+	return fref / div;
+}
+
+static ulong imx_get_ipgclk(void)
+{
+	return imx_get_ahbclk() / 2;
+}
+
+static ulong imx_get_perclk(int clk)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = imx_get_ahbclk();
+	ulong div;
+
+	div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
+	div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
+
+	return fref / div;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	if (clk >= MXC_CLK_NUM)
+		return -1;
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return imx_get_armclk();
+	case MXC_AHB_CLK:
+		return imx_get_ahbclk();
+	case MXC_IPG_CLK:
+	case MXC_CSPI_CLK:
+	case MXC_FEC_CLK:
+		return imx_get_ipgclk();
+	default:
+		return imx_get_perclk(clk);
+	}
+}
+
+u32 get_cpu_rev(void)
+{
+	u32 srev;
+	u32 system_rev = 0x25000;
+
+	/* read SREV register from IIM module */
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	srev = readl(&iim->iim_srev);
+
+	switch (srev) {
+	case 0x00:
+		system_rev |= CHIP_REV_1_0;
+		break;
+	case 0x01:
+		system_rev |= CHIP_REV_1_1;
+		break;
+	case 0x02:
+		system_rev |= CHIP_REV_1_2;
+		break;
+	default:
+		system_rev |= 0x8000;
+		break;
+	}
+
+	return system_rev;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x0f;
+
+	if (cause == 0)
+		return "POR";
+	else if (cause == 1)
+		return "RST";
+	else if ((cause & 2) == 2)
+		return "WDOG";
+	else if ((cause & 4) == 4)
+		return "SW RESET";
+	else if ((cause & 8) == 8)
+		return "JTAG";
+	else
+		return "unknown reset";
+
+}
+
+int print_cpuinfo(void)
+{
+	char buf[32];
+	u32 cpurev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX25 rev%d.%d%s at %s MHz\n",
+		(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
+		((cpurev & 0x8000) ? " unknown" : ""),
+		strmhz(buf, imx_get_armclk()));
+	printf("Reset cause: %s\n\n", get_reset_cause());
+	return 0;
+}
+#endif
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+#endif
+}
+
+#if defined(CONFIG_FEC_MXC)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong val;
+
+	val = readl(&ccm->cgr0);
+	val |= (1 << 23);
+	writel(val, &ccm->cgr0);
+	return fecmxc_initialize(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#else
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	int i;
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+			(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	for (i = 0; i < 6; i++)
+		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
+#endif /* CONFIG_FEC_MXC */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/reset.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/reset.c
new file mode 100644
index 000000000..5db689dbb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/reset.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let it time out
+ */
+void reset_cpu(ulong ignored)
+{
+	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
+	/* Disable watchdog and set Time-Out field to 0 */
+	writew(0, &regs->wcr);
+
+	/* Write Service Sequence */
+	writew(WSR_UNLOCK1, &regs->wsr);
+	writew(WSR_UNLOCK2, &regs->wsr);
+
+	/* Enable watchdog */
+	writew(WCR_WDE, &regs->wcr);
+
+	while (1) ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/timer.c
new file mode 100644
index 000000000..7f1979173
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx25/timer.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *	Add support for MX25
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/* nothing really to do with interrupts, just starts up a counter. */
+/* The 32KHz 32-bit timer overruns in 134217 seconds */
+int timer_init(void)
+{
+	int i;
+	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+
+	/* setup GP Timer 1 */
+	writel(GPT_CTRL_SWR, &gpt->ctrl);
+
+	writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
+
+	for (i = 0; i < 100; i++)
+		writel(0, &gpt->ctrl); /* We have no udelay by now */
+	writel(0, &gpt->pre); /* prescaler = 1 */
+	/* Freerun Mode, 32KHz input */
+	writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
+			&gpt->ctrl);
+	writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/Makefile
new file mode 100644
index 000000000..4976bbb89
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	= generic.o reset.o timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/generic.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/generic.c
new file mode 100644
index 000000000..5ee9f07d8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/generic.c
@@ -0,0 +1,379 @@
+/*
+ *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#ifdef CONFIG_MXC_MMC
+#include <asm/arch/mxcmmc.h>
+#endif
+
+/*
+ *  get the system pll clock in Hz
+ *
+ *                  mfi + mfn / (mfd +1)
+ *  f = 2 * f_ref * --------------------
+ *                        pd + 1
+ */
+static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+{
+	unsigned int mfi = (pll >> 10) & 0xf;
+	unsigned int mfn = pll & 0x3ff;
+	unsigned int mfd = (pll >> 16) & 0x3ff;
+	unsigned int pd =  (pll >> 26) & 0xf;
+
+	mfi = mfi <= 5 ? 5 : mfi;
+
+	return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
+			(mfd + 1) * (pd + 1));
+}
+
+static ulong clk_in_32k(void)
+{
+	return 1024 * CONFIG_MX27_CLK32;
+}
+
+static ulong clk_in_26m(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
+		/* divide by 1.5 */
+		return 26000000 * 2 / 3;
+	} else {
+		return 26000000;
+	}
+}
+
+static ulong imx_get_mpllclk(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+	ulong cscr = readl(&pll->cscr);
+	ulong fref;
+
+	if (cscr & CSCR_MCU_SEL)
+		fref = clk_in_26m();
+	else
+		fref = clk_in_32k();
+
+	return imx_decode_pll(readl(&pll->mpctl0), fref);
+}
+
+static ulong imx_get_armclk(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+	ulong cscr = readl(&pll->cscr);
+	ulong fref = imx_get_mpllclk();
+	ulong div;
+
+	if (!(cscr & CSCR_ARM_SRC_MPLL))
+		fref = lldiv((fref * 2), 3);
+
+	div = ((cscr >> 12) & 0x3) + 1;
+
+	return lldiv(fref, div);
+}
+
+static ulong imx_get_ahbclk(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+	ulong cscr = readl(&pll->cscr);
+	ulong fref = imx_get_mpllclk();
+	ulong div;
+
+	div = ((cscr >> 8) & 0x3) + 1;
+
+	return lldiv(fref * 2, 3 * div);
+}
+
+static __attribute__((unused)) ulong imx_get_spllclk(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+	ulong cscr = readl(&pll->cscr);
+	ulong fref;
+
+	if (cscr & CSCR_SP_SEL)
+		fref = clk_in_26m();
+	else
+		fref = clk_in_32k();
+
+	return imx_decode_pll(readl(&pll->spctl0), fref);
+}
+
+static ulong imx_decode_perclk(ulong div)
+{
+	return lldiv((imx_get_mpllclk() * 2), (div * 3));
+}
+
+static ulong imx_get_perclk1(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
+}
+
+static ulong imx_get_perclk2(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
+}
+
+static __attribute__((unused)) ulong imx_get_perclk3(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
+}
+
+static __attribute__((unused)) ulong imx_get_perclk4(void)
+{
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return imx_get_armclk();
+	case MXC_I2C_CLK:
+		return imx_get_ahbclk()/2;
+	case MXC_UART_CLK:
+		return imx_get_perclk1();
+	case MXC_FEC_CLK:
+		return imx_get_ahbclk();
+	case MXC_ESDHC_CLK:
+		return imx_get_perclk2();
+	}
+	return -1;
+}
+
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo (void)
+{
+	char buf[32];
+
+	printf("CPU:   Freescale i.MX27 at %s MHz\n\n",
+			strmhz(buf, imx_get_mpllclk()));
+	return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FEC_MXC)
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	/* enable FEC clock */
+	writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
+	writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
+	return fecmxc_initialize(bis);
+#else
+	return 0;
+#endif
+}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_MXC_MMC
+	return mxc_mmc_init(bis);
+#else
+	return 0;
+#endif
+}
+
+void imx_gpio_mode(int gpio_mode)
+{
+	struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
+	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
+	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
+	unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
+	unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
+	unsigned int tmp;
+
+	/* Pullup enable */
+	if (gpio_mode & GPIO_PUEN) {
+		writel(readl(&regs->port[port].puen) | (1 << pin),
+				&regs->port[port].puen);
+	} else {
+		writel(readl(&regs->port[port].puen) & ~(1 << pin),
+				&regs->port[port].puen);
+	}
+
+	/* Data direction */
+	if (gpio_mode & GPIO_OUT) {
+		writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
+				&regs->port[port].gpio_dir);
+	} else {
+		writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
+				&regs->port[port].gpio_dir);
+	}
+
+	/* Primary / alternate function */
+	if (gpio_mode & GPIO_AF) {
+		writel(readl(&regs->port[port].gpr) | (1 << pin),
+				&regs->port[port].gpr);
+	} else {
+		writel(readl(&regs->port[port].gpr) & ~(1 << pin),
+				&regs->port[port].gpr);
+	}
+
+	/* use as gpio? */
+	if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
+		writel(readl(&regs->port[port].gius) | (1 << pin),
+				&regs->port[port].gius);
+	} else {
+		writel(readl(&regs->port[port].gius) & ~(1 << pin),
+				&regs->port[port].gius);
+	}
+
+	/* Output / input configuration */
+	if (pin < 16) {
+		tmp = readl(&regs->port[port].ocr1);
+		tmp &= ~(3 << (pin * 2));
+		tmp |= (ocr << (pin * 2));
+		writel(tmp, &regs->port[port].ocr1);
+
+		writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
+				&regs->port[port].iconfa1);
+		writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
+				&regs->port[port].iconfa1);
+		writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
+				&regs->port[port].iconfb1);
+		writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
+				&regs->port[port].iconfb1);
+	} else {
+		pin -= 16;
+
+		tmp = readl(&regs->port[port].ocr2);
+		tmp &= ~(3 << (pin * 2));
+		tmp |= (ocr << (pin * 2));
+		writel(tmp, &regs->port[port].ocr2);
+
+		writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
+				&regs->port[port].iconfa2);
+		writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
+				&regs->port[port].iconfa2);
+		writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
+				&regs->port[port].iconfb2);
+		writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
+				&regs->port[port].iconfb2);
+	}
+}
+
+#ifdef CONFIG_MXC_UART
+void mx27_uart1_init_pins(void)
+{
+	int i;
+	unsigned int mode[] = {
+		PE12_PF_UART1_TXD,
+		PE13_PF_UART1_RXD,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+}
+#endif /* CONFIG_MXC_UART */
+
+#ifdef CONFIG_FEC_MXC
+void mx27_fec_init_pins(void)
+{
+	int i;
+	unsigned int mode[] = {
+		PD0_AIN_FEC_TXD0,
+		PD1_AIN_FEC_TXD1,
+		PD2_AIN_FEC_TXD2,
+		PD3_AIN_FEC_TXD3,
+		PD4_AOUT_FEC_RX_ER,
+		PD5_AOUT_FEC_RXD1,
+		PD6_AOUT_FEC_RXD2,
+		PD7_AOUT_FEC_RXD3,
+		PD8_AF_FEC_MDIO,
+		PD9_AIN_FEC_MDC | GPIO_PUEN,
+		PD10_AOUT_FEC_CRS,
+		PD11_AOUT_FEC_TX_CLK,
+		PD12_AOUT_FEC_RXD0,
+		PD13_AOUT_FEC_RX_DV,
+		PD14_AOUT_FEC_CLR,
+		PD15_AOUT_FEC_COL,
+		PD16_AIN_FEC_TX_ER,
+		PF23_AIN_FEC_TX_EN,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+}
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	int i;
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+			(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	for (i = 0; i < 6; i++)
+		mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_MXC_MMC
+void mx27_sd1_init_pins(void)
+{
+	int i;
+	unsigned int mode[] = {
+		PE18_PF_SD1_D0,
+		PE19_PF_SD1_D1,
+		PE20_PF_SD1_D2,
+		PE21_PF_SD1_D3,
+		PE22_PF_SD1_CMD,
+		PE23_PF_SD1_CLK,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+}
+
+void mx27_sd2_init_pins(void)
+{
+	int i;
+	unsigned int mode[] = {
+		PB4_PF_SD2_D0,
+		PB5_PF_SD2_D1,
+		PB6_PF_SD2_D2,
+		PB7_PF_SD2_D3,
+		PB8_PF_SD2_CMD,
+		PB9_PF_SD2_CLK,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mode); i++)
+		imx_gpio_mode(mode[i]);
+
+}
+#endif /* CONFIG_MXC_MMC */
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif /* CONFIG_SYS_DCACHE_OFF */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/reset.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/reset.c
new file mode 100644
index 000000000..f7b4a1c83
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/reset.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let it time out
+ */
+void reset_cpu(ulong ignored)
+{
+	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
+	/* Disable watchdog and set Time-Out field to 0 */
+	writel(0x00000000, &regs->wcr);
+
+	/* Write Service Sequence */
+	writel(0x00005555, &regs->wsr);
+	writel(0x0000AAAA, &regs->wsr);
+
+	/* Enable watchdog */
+	writel(WCR_WDE, &regs->wcr);
+
+	while (1);
+	/*NOTREACHED*/
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/timer.c
new file mode 100644
index 000000000..40fe2aafc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mx27/timer.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
+#define GPTCR_FRR		(1 << 8)	/* Freerun / restart	*/
+#define GPTCR_CLKSOURCE_32	(4 << 1)	/* Clock source		*/
+#define GPTCR_TEN		1		/* Timer enable		*/
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp	(gd->arch.tbl)
+#define lastinc		(gd->arch.lastinc)
+
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, CONFIG_MX27_CLK32);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	time *= CONFIG_MX27_CLK32;
+	do_div(time, CONFIG_SYS_HZ);
+	return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us = us * CONFIG_MX27_CLK32 + 999999;
+	do_div(us, 1000000);
+	return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME	((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
+		CONFIG_SYS_HZ)
+#define US_PER_TICK	(1000000 / CONFIG_MX27_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	do_div(tick, TICK_PER_TIME);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us += US_PER_TICK - 1;
+	do_div(us, US_PER_TICK);
+	return us;
+}
+#endif
+
+/* nothing really to do with interrupts, just starts up a counter. */
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
+int timer_init(void)
+{
+	int i;
+	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	/* setup GP Timer 1 */
+	writel(GPTCR_SWR, &regs->gpt_tctl);
+
+	writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
+	writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
+
+	for (i = 0; i < 100; i++)
+		writel(0, &regs->gpt_tctl); /* We have no udelay by now */
+	writel(0, &regs->gpt_tprer); /* 32Khz */
+	/* Freerun Mode, PERCLK1 input */
+	writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+			&regs->gpt_tctl);
+	writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
+	ulong now = readl(&regs->gpt_tcn); /* current tick value */
+
+	if (now >= lastinc) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp forward with absolut diff ticks
+		 */
+		timestamp += (now - lastinc);
+	} else {
+		/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	}
+	lastinc = now;
+	return timestamp;
+}
+
+ulong get_timer_masked(void)
+{
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_MX27_CLK32;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/Makefile
new file mode 100644
index 000000000..6c5949455
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -0,0 +1,85 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-$(CONFIG_SPL_BUILD) := start.o
+
+obj-y	= clock.o mxs.o iomux.o timer.o
+
+ifdef	CONFIG_SPL_BUILD
+obj-y	+= spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
+endif
+
+# Specify the target for use in elftosb call
+MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
+MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
+
+# Generate HAB-capable IVT
+#
+# Note on computing the post-IVT size field value for the U-Boot binary.
+# The value is the result of adding the following:
+#  -> The size of U-Boot binary aligned to 64B (u-boot.bin)
+#  -> The size of IVT block aligned to 64B (u-boot.ivt)
+#  -> The size of U-Boot signature (u-boot.sig), 3904 B
+#  -> The 64B hole in front of U-Boot binary for 'struct mxs_spl_data' passing
+#
+quiet_cmd_mkivt_mxs = MXSIVT  $@
+cmd_mkivt_mxs =								\
+	sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ;		\
+	echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" |	\
+	tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev |	\
+	sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@
+
+# Align binary to 64B
+quiet_cmd_mkalign_mxs = MXSALGN $@
+cmd_mkalign_mxs =							\
+	dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null &&			\
+	mv $@ $^
+
+# Assemble the CSF file
+quiet_cmd_mkcsfreq_mxs = MXSCSFR $@
+cmd_mkcsfreq_mxs =							\
+	ivt=$(word 1,$^) ;						\
+	bin=$(word 2,$^) ;						\
+	csf=$(word 3,$^) ;						\
+	sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" |		\
+		sed '/^\#\#Blocks/ d' > $@ ;				\
+	echo "  Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \
+	echo "           $3 0x0 0x40 \"$$ivt\"" >> $@
+
+# Sign files
+quiet_cmd_mkcst_mxs = MXSCST  $@
+cmd_mkcst_mxs = cst -o $@ < $^						\
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
+
+spl/u-boot-spl.ivt: spl/u-boot-spl.bin
+	$(call if_changed,mkalign_mxs)
+	$(call if_changed,mkivt_mxs,$(CONFIG_SPL_TEXT_BASE),\
+		0x00008000,0x00008040)
+
+u-boot.ivt: u-boot.bin
+	$(call if_changed,mkalign_mxs)
+	$(call if_changed,mkivt_mxs,$(CONFIG_SYS_TEXT_BASE),\
+		0x40001000,0x40001040)
+
+spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf
+	$(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000)
+
+u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
+	$(call if_changed,mkcsfreq_mxs,$(CONFIG_SYS_TEXT_BASE),0x40001000)
+
+%.sig: %.csf
+	$(call if_changed,mkcst_mxs)
+
+quiet_cmd_mkimage_mxs = MKIMAGE $@
+cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
+
+u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE
+	$(call if_changed,mkimage_mxs)
+
+u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE
+	$(call if_changed,mkimage_mxs)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/clock.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/clock.c
new file mode 100644
index 000000000..e9d8800f8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -0,0 +1,436 @@
+/*
+ * Freescale i.MX23/i.MX28 clock setup code
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * The PLL frequency is 480MHz and XTAL frequency is 24MHz
+ *   iMX23: datasheet section 4.2
+ *   iMX28: datasheet section 10.2
+ */
+#define	PLL_FREQ_KHZ	480000
+#define	PLL_FREQ_COEF	18
+#define	XTAL_FREQ_KHZ	24000
+
+#define	PLL_FREQ_MHZ	(PLL_FREQ_KHZ / 1000)
+#define	XTAL_FREQ_MHZ	(XTAL_FREQ_KHZ / 1000)
+
+#if defined(CONFIG_MX23)
+#define MXC_SSPCLK_MAX MXC_SSPCLK0
+#elif defined(CONFIG_MX28)
+#define MXC_SSPCLK_MAX MXC_SSPCLK3
+#endif
+
+static uint32_t mxs_get_pclk(void)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
+
+	clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
+
+	/* No support of fractional divider calculation */
+	if (clkctrl &
+		(CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
+		return 0;
+	}
+
+	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+
+	/* XTAL Path */
+	if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
+		div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
+			CLKCTRL_CPU_DIV_XTAL_OFFSET;
+		return XTAL_FREQ_MHZ / div;
+	}
+
+	/* REF Path */
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
+	div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
+	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
+}
+
+static uint32_t mxs_get_hclk(void)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	uint32_t div;
+	uint32_t clkctrl;
+
+	clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);
+
+	/* No support of fractional divider calculation */
+	if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN)
+		return 0;
+
+	div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
+	return mxs_get_pclk() / div;
+}
+
+static uint32_t mxs_get_emiclk(void)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
+
+	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+	clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
+
+	/* XTAL Path */
+	if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) {
+		div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >>
+			CLKCTRL_EMI_DIV_XTAL_OFFSET;
+		return XTAL_FREQ_MHZ / div;
+	}
+
+	/* REF Path */
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
+	div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
+	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
+}
+
+static uint32_t mxs_get_gpmiclk(void)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+#if defined(CONFIG_MX23)
+	uint8_t *reg =
+		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
+#elif defined(CONFIG_MX28)
+	uint8_t *reg =
+		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
+#endif
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
+
+	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+	clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
+
+	/* XTAL Path */
+	if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) {
+		div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
+		return XTAL_FREQ_MHZ / div;
+	}
+
+	/* REF Path */
+	clkfrac = readb(reg);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
+	div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
+	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
+}
+
+/*
+ * Set IO clock frequency, in kHz
+ */
+void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	uint32_t div;
+	int io_reg;
+
+	if (freq == 0)
+		return;
+
+	if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
+		return;
+
+	div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
+
+	if (div < 18)
+		div = 18;
+
+	if (div > 35)
+		div = 35;
+
+	io_reg = CLKCTRL_FRAC0_IO0 - io;	/* Register order is reversed */
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_set[io_reg]);
+	writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac0[io_reg]);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]);
+}
+
+/*
+ * Get IO clock, returns IO clock in kHz
+ */
+static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	uint8_t ret;
+	int io_reg;
+
+	if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
+		return 0;
+
+	io_reg = CLKCTRL_FRAC0_IO0 - io;	/* Register order is reversed */
+
+	ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &
+		CLKCTRL_FRAC_FRAC_MASK;
+
+	return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
+}
+
+/*
+ * Configure SSP clock frequency, in kHz
+ */
+void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	uint32_t clk, clkreg;
+
+	if (ssp > MXC_SSPCLK_MAX)
+		return;
+
+	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
+			(ssp * sizeof(struct mxs_register_32));
+
+	clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
+	while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
+		;
+
+	if (xtal)
+		clk = XTAL_FREQ_KHZ;
+	else
+		clk = mxs_get_ioclk(ssp >> 1);
+
+	if (freq > clk)
+		return;
+
+	/* Calculate the divider and cap it if necessary */
+	clk /= freq;
+	if (clk > CLKCTRL_SSP_DIV_MASK)
+		clk = CLKCTRL_SSP_DIV_MASK;
+
+	clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk);
+	while (readl(clkreg) & CLKCTRL_SSP_BUSY)
+		;
+
+	if (xtal)
+		writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
+			&clkctrl_regs->hw_clkctrl_clkseq_set);
+	else
+		writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
+			&clkctrl_regs->hw_clkctrl_clkseq_clr);
+}
+
+/*
+ * Return SSP frequency, in kHz
+ */
+static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	uint32_t clkreg;
+	uint32_t clk, tmp;
+
+	if (ssp > MXC_SSPCLK_MAX)
+		return 0;
+
+	tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
+	if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp))
+		return XTAL_FREQ_KHZ;
+
+	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
+			(ssp * sizeof(struct mxs_register_32));
+
+	tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
+
+	if (tmp == 0)
+		return 0;
+
+	clk = mxs_get_ioclk(ssp >> 1);
+
+	return clk / tmp;
+}
+
+/*
+ * Set SSP/MMC bus frequency, in kHz)
+ */
+void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
+{
+	struct mxs_ssp_regs *ssp_regs;
+	const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus);
+	const uint32_t sspclk = mxs_get_sspclk(clk);
+	uint32_t reg;
+	uint32_t divide, rate, tgtclk;
+
+	ssp_regs = mxs_ssp_regs_by_bus(bus);
+
+	/*
+	 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
+	 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
+	 * CLOCK_RATE could be any integer from 0 to 255.
+	 */
+	for (divide = 2; divide < 254; divide += 2) {
+		rate = sspclk / freq / divide;
+		if (rate <= 256)
+			break;
+	}
+
+	tgtclk = sspclk / divide / rate;
+	while (tgtclk > freq) {
+		rate++;
+		tgtclk = sspclk / divide / rate;
+	}
+	if (rate > 256)
+		rate = 256;
+
+	/* Always set timeout the maximum */
+	reg = SSP_TIMING_TIMEOUT_MASK |
+		(divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) |
+		((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET);
+	writel(reg, &ssp_regs->hw_ssp_timing);
+
+	debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n",
+		bus, tgtclk, freq);
+}
+
+void mxs_set_lcdclk(uint32_t freq)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	uint32_t fp, x, k_rest, k_best, x_best, tk;
+	int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff;
+
+	if (freq == 0)
+		return;
+
+#if defined(CONFIG_MX23)
+	writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
+#elif defined(CONFIG_MX28)
+	writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
+#endif
+
+	/*
+	 *             /               18 \     1       1
+	 * freq kHz = | 480000000 Hz * --  | * --- * ------
+	 *             \                x /     k     1000
+	 *
+	 *      480000000 Hz   18
+	 *      ------------ * --
+	 *        freq kHz      x
+	 * k = -------------------
+	 *             1000
+	 */
+
+	fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18;
+
+	for (x = 18; x <= 35; x++) {
+		tk = fp / x;
+		if ((tk / 1000 == 0) || (tk / 1000 > 255))
+			continue;
+
+		k_rest = tk % 1000;
+
+		if (k_rest < (k_best_l % 1000)) {
+			k_best_l = tk;
+			x_best_l = x;
+		}
+
+		if (k_rest > (k_best_t % 1000)) {
+			k_best_t = tk;
+			x_best_t = x;
+		}
+	}
+
+	if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) {
+		k_best = k_best_l;
+		x_best = x_best_l;
+	} else {
+		k_best = k_best_t;
+		x_best = x_best_t;
+	}
+
+	k_best /= 1000;
+
+#if defined(CONFIG_MX23)
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
+	writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);
+
+	writel(CLKCTRL_PIX_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_pix_set);
+	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
+			CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,
+			k_best << CLKCTRL_PIX_DIV_OFFSET);
+
+	while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
+		;
+#elif defined(CONFIG_MX28)
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
+	writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
+
+	writel(CLKCTRL_DIS_LCDIF_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_lcdif_set);
+	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
+			CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
+			k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
+
+	while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
+		;
+#endif
+}
+
+uint32_t mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return mxs_get_pclk() * 1000000;
+	case MXC_GPMI_CLK:
+		return mxs_get_gpmiclk() * 1000000;
+	case MXC_AHB_CLK:
+	case MXC_IPG_CLK:
+		return mxs_get_hclk() * 1000000;
+	case MXC_EMI_CLK:
+		return mxs_get_emiclk();
+	case MXC_IO0_CLK:
+		return mxs_get_ioclk(MXC_IOCLK0);
+	case MXC_IO1_CLK:
+		return mxs_get_ioclk(MXC_IOCLK1);
+	case MXC_XTAL_CLK:
+		return XTAL_FREQ_KHZ * 1000;
+	case MXC_SSP0_CLK:
+		return mxs_get_sspclk(MXC_SSPCLK0);
+#ifdef CONFIG_MX28
+	case MXC_SSP1_CLK:
+		return mxs_get_sspclk(MXC_SSPCLK1);
+	case MXC_SSP2_CLK:
+		return mxs_get_sspclk(MXC_SSPCLK2);
+	case MXC_SSP3_CLK:
+		return mxs_get_sspclk(MXC_SSPCLK3);
+#endif
+	}
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/iomux.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/iomux.c
new file mode 100644
index 000000000..2e6be06fd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/iomux.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                       <armlinux@phytec.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+
+#if	defined(CONFIG_MX23)
+#define	DRIVE_OFFSET	0x200
+#define	PULL_OFFSET	0x400
+#elif	defined(CONFIG_MX28)
+#define	DRIVE_OFFSET	0x300
+#define	PULL_OFFSET	0x600
+#else
+#error "Please select CONFIG_MX23 or CONFIG_MX28"
+#endif
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxs_iomux_setup_pad(iomux_cfg_t pad)
+{
+	u32 reg, ofs, bp, bm;
+	void *iomux_base = (void *)MXS_PINCTRL_BASE;
+	struct mxs_register_32 *mxs_reg;
+
+	/* muxsel */
+	ofs = 0x100;
+	ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
+	bp = PAD_PIN(pad) % 16 * 2;
+	bm = 0x3 << bp;
+	reg = readl(iomux_base + ofs);
+	reg &= ~bm;
+	reg |= PAD_MUXSEL(pad) << bp;
+	writel(reg, iomux_base + ofs);
+
+	/* drive */
+	ofs = DRIVE_OFFSET;
+	ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
+	/* mA */
+	if (PAD_MA_VALID(pad)) {
+		bp = PAD_PIN(pad) % 8 * 4;
+		bm = 0x3 << bp;
+		reg = readl(iomux_base + ofs);
+		reg &= ~bm;
+		reg |= PAD_MA(pad) << bp;
+		writel(reg, iomux_base + ofs);
+	}
+	/* vol */
+	if (PAD_VOL_VALID(pad)) {
+		bp = PAD_PIN(pad) % 8 * 4 + 2;
+		mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
+		if (PAD_VOL(pad))
+			writel(1 << bp, &mxs_reg->reg_set);
+		else
+			writel(1 << bp, &mxs_reg->reg_clr);
+	}
+
+	/* pull */
+	if (PAD_PULL_VALID(pad)) {
+		ofs = PULL_OFFSET;
+		ofs += PAD_BANK(pad) * 0x10;
+		bp = PAD_PIN(pad);
+		mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
+		if (PAD_PULL(pad))
+			writel(1 << bp, &mxs_reg->reg_set);
+		else
+			writel(1 << bp, &mxs_reg->reg_clr);
+	}
+
+	return 0;
+}
+
+int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
+{
+	const iomux_cfg_t *p = pad_list;
+	int i;
+	int ret;
+
+	for (i = 0; i < count; i++) {
+		ret = mxs_iomux_setup_pad(*p);
+		if (ret)
+			return ret;
+		p++;
+	}
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs.c
new file mode 100644
index 000000000..365542fe0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -0,0 +1,299 @@
+/*
+ * Freescale i.MX23/i.MX28 common code
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/imx-common/dma.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
+inline void lowlevel_init(void) {}
+
+void reset_cpu(ulong ignored) __attribute__((noreturn));
+
+void reset_cpu(ulong ignored)
+{
+	struct mxs_rtc_regs *rtc_regs =
+		(struct mxs_rtc_regs *)MXS_RTC_BASE;
+	struct mxs_lcdif_regs *lcdif_regs =
+		(struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+
+	/*
+	 * Shut down the LCD controller as it interferes with BootROM boot mode
+	 * pads sampling.
+	 */
+	writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
+
+	/* Wait 1 uS before doing the actual watchdog reset */
+	writel(1, &rtc_regs->hw_rtc_watchdog);
+	writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
+
+	/* Endless loop, reset will exit from here */
+	for (;;)
+		;
+}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+
+/*
+ * This function will craft a jumptable at 0x0 which will redirect interrupt
+ * vectoring to proper location of U-Boot in RAM.
+ *
+ * The structure of the jumptable will be as follows:
+ *  ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
+ *  <destination address> ... for each previous ldr, thus also repeated 8 times
+ *
+ * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
+ * offset 0x18 from current value of PC register. Note that PC is already
+ * incremented by 4 when computing the offset, so the effective offset is
+ * actually 0x20, this the associated <destination address>. Loading the PC
+ * register with an address performs a jump to that address.
+ */
+void mx28_fixup_vt(uint32_t start_addr)
+{
+	/* ldr pc, [pc, #0x18] */
+	const uint32_t ldr_pc = 0xe59ff018;
+	/* Jumptable location is 0x0 */
+	uint32_t *vt = (uint32_t *)0x0;
+	int i;
+
+	for (i = 0; i < 8; i++) {
+		vt[i] = ldr_pc;
+		vt[i + 8] = start_addr + (4 * i);
+	}
+}
+
+#ifdef	CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	mx28_fixup_vt(gd->relocaddr);
+	return 0;
+}
+#endif
+
+int arch_cpu_init(void)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	extern uint32_t _start;
+
+	mx28_fixup_vt((uint32_t)&_start);
+
+	/*
+	 * Enable NAND clock
+	 */
+	/* Clear bypass bit */
+	writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
+		&clkctrl_regs->hw_clkctrl_clkseq_set);
+
+	/* Set GPMI clock to ref_gpmi / 12 */
+	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
+		CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
+
+	udelay(1000);
+
+	/*
+	 * Configure GPIO unit
+	 */
+	mxs_gpio_init();
+
+#ifdef	CONFIG_APBH_DMA
+	/* Start APBH DMA */
+	mxs_dma_init();
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static const char *get_cpu_type(void)
+{
+	struct mxs_digctl_regs *digctl_regs =
+		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+
+	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
+	case HW_DIGCTL_CHIPID_MX23:
+		return "23";
+	case HW_DIGCTL_CHIPID_MX28:
+		return "28";
+	default:
+		return "??";
+	}
+}
+
+static const char *get_cpu_rev(void)
+{
+	struct mxs_digctl_regs *digctl_regs =
+		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+	uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
+
+	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
+	case HW_DIGCTL_CHIPID_MX23:
+		switch (rev) {
+		case 0x0:
+			return "1.0";
+		case 0x1:
+			return "1.1";
+		case 0x2:
+			return "1.2";
+		case 0x3:
+			return "1.3";
+		case 0x4:
+			return "1.4";
+		default:
+			return "??";
+		}
+	case HW_DIGCTL_CHIPID_MX28:
+		switch (rev) {
+		case 0x1:
+			return "1.2";
+		default:
+			return "??";
+		}
+	default:
+		return "??";
+	}
+}
+
+int print_cpuinfo(void)
+{
+	struct mxs_spl_data *data = (struct mxs_spl_data *)
+		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+
+	printf("CPU:   Freescale i.MX%s rev%s at %d MHz\n",
+		get_cpu_type(),
+		get_cpu_rev(),
+		mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("BOOT:  %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
+	return 0;
+}
+#endif
+
+int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	printf("CPU:   %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("BUS:   %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
+	printf("EMI:   %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
+	printf("GPMI:  %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
+	return 0;
+}
+
+/*
+ * Initializes on-chip ethernet controllers.
+ */
+#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
+int cpu_eth_init(bd_t *bis)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	/* Turn on ENET clocks */
+	clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+		CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
+
+	/* Set up ENET PLL for 50 MHz */
+	/* Power on ENET PLL */
+	writel(CLKCTRL_PLL2CTRL0_POWER,
+		&clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
+
+	udelay(10);
+
+	/* Gate on ENET PLL */
+	writel(CLKCTRL_PLL2CTRL0_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
+
+	/* Enable pad output */
+	setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
+
+	return 0;
+}
+#endif
+
+__weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
+{
+	mac[0] = 0x00;
+	mac[1] = 0x04; /* Use FSL vendor MAC address by default */
+
+	if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
+		mac[5] += 1;
+}
+
+#ifdef	CONFIG_MX28_FEC_MAC_IN_OCOTP
+
+#define	MXS_OCOTP_MAX_TIMEOUT	1000000
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	struct mxs_ocotp_regs *ocotp_regs =
+		(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
+	uint32_t data;
+
+	memset(mac, 0, 6);
+
+	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
+
+	if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+				MXS_OCOTP_MAX_TIMEOUT)) {
+		printf("MXS FEC: Can't get MAC from OCOTP\n");
+		return;
+	}
+
+	data = readl(&ocotp_regs->hw_ocotp_cust0);
+
+	mac[2] = (data >> 24) & 0xff;
+	mac[3] = (data >> 16) & 0xff;
+	mac[4] = (data >> 8) & 0xff;
+	mac[5] = data & 0xff;
+	mx28_adjust_mac(dev_id, mac);
+}
+#else
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	memset(mac, 0, 6);
+}
+#endif
+
+int mxs_dram_init(void)
+{
+	struct mxs_spl_data *data = (struct mxs_spl_data *)
+		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+
+	if (data->mem_dram_size == 0) {
+		printf("MXS:\n"
+			"Error, the RAM size passed up from SPL is 0!\n");
+		hang();
+	}
+
+	gd->ram_size = data->mem_dram_size;
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
+	"display clocks",
+	""
+);
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs_init.h b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
new file mode 100644
index 000000000..1200ae1ad
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs_init.h
@@ -0,0 +1,29 @@
+/*
+ * Freescale i.MX28 SPL functions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__M28_INIT_H__
+#define	__M28_INIT_H__
+
+void early_delay(int delay);
+
+void mxs_power_init(void);
+
+#ifdef	CONFIG_SPL_MXS_PSWITCH_WAIT
+void mxs_power_wait_pswitch(void);
+#else
+static inline void mxs_power_wait_pswitch(void) { }
+#endif
+
+void mxs_mem_init(void);
+uint32_t mxs_mem_get_size(void);
+
+void mxs_lradc_init(void);
+void mxs_lradc_enable_batt_measurement(void);
+
+#endif	/* __M28_INIT_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg
new file mode 100644
index 000000000..1520bba3f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg
@@ -0,0 +1,10 @@
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD     0x1000     spl/u-boot-spl.bin
+ LOAD     0x8000     spl/u-boot-spl.ivt
+ LOAD     0x8040     spl/u-boot-spl.sig
+ CALL HAB 0x8000     0x0
+ LOAD     0x40002000 u-boot.bin
+ LOAD     0x40001000 u-boot.ivt
+ LOAD     0x40001040 u-boot.sig
+ CALL HAB 0x40001000 0x0
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
new file mode 100644
index 000000000..55510e9cd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
@@ -0,0 +1,6 @@
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD     0x1000     spl/u-boot-spl.bin
+ CALL     0x1000     0x0
+ LOAD     0x40002000 u-boot.bin
+ CALL     0x40002000 0x0
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
new file mode 100644
index 000000000..bb78cb0c8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
@@ -0,0 +1,8 @@
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD     0x1000     spl/u-boot-spl.bin
+ LOAD IVT 0x8000     0x1000
+ CALL HAB 0x8000     0x0
+ LOAD     0x40002000 u-boot.bin
+ LOAD IVT 0x8000     0x40002000
+ CALL HAB 0x8000     0x0
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
new file mode 100644
index 000000000..d3e136991
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -0,0 +1,170 @@
+/*
+ * Freescale i.MX28 Boot setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <linux/compiler.h>
+
+#include "mxs_init.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+static gd_t gdata __section(".data");
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+static bd_t bdata __section(".data");
+#endif
+
+/*
+ * This delay function is intended to be used only in early stage of boot, where
+ * clock are not set up yet. The timer used here is reset on every boot and
+ * takes a few seconds to roll. The boot doesn't take that long, so to keep the
+ * code simple, it doesn't take rolling into consideration.
+ */
+void early_delay(int delay)
+{
+	struct mxs_digctl_regs *digctl_regs =
+		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+
+	uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
+	st += delay;
+	while (st > readl(&digctl_regs->hw_digctl_microseconds))
+		;
+}
+
+#define	MUX_CONFIG_BOOTMODE_PAD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+static const iomux_cfg_t iomux_boot[] = {
+#if defined(CONFIG_MX23)
+	MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
+#elif defined(CONFIG_MX28)
+	MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
+	MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
+	MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
+	MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
+	MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
+	MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
+#endif
+};
+
+static uint8_t mxs_get_bootmode_index(void)
+{
+	uint8_t bootmode = 0;
+	int i;
+	uint8_t masked;
+
+	/* Setup IOMUX of bootmode pads to GPIO */
+	mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
+
+#if defined(CONFIG_MX23)
+	/* Setup bootmode pins as GPIO input */
+	gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
+	gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
+	gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2);
+	gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3);
+	gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5);
+
+	/* Read bootmode pads */
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
+#elif defined(CONFIG_MX28)
+	/* Setup bootmode pins as GPIO input */
+	gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
+	gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
+	gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2);
+	gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3);
+	gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4);
+	gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5);
+
+	/* Read bootmode pads */
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
+#endif
+
+	for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
+		masked = bootmode & mxs_boot_modes[i].boot_mask;
+		if (masked == mxs_boot_modes[i].boot_pads)
+			break;
+	}
+
+	return i;
+}
+
+static void mxs_spl_fixup_vectors(void)
+{
+	/*
+	 * Copy our vector table to 0x0, since due to HAB, we cannot
+	 * be loaded to 0x0. We want to have working vectoring though,
+	 * thus this fixup. Our vectoring table is PIC, so copying is
+	 * fine.
+	 */
+	extern uint32_t _start;
+	memcpy(0x0, &_start, 0x60);
+}
+
+static void mxs_spl_console_init(void)
+{
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	gd->bd = &bdata;
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();
+	gd->have_console = 1;
+#endif
+}
+
+void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
+			 const iomux_cfg_t *iomux_setup,
+			 const unsigned int iomux_size)
+{
+	struct mxs_spl_data *data = (struct mxs_spl_data *)
+		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+	uint8_t bootmode = mxs_get_bootmode_index();
+	gd = &gdata;
+
+	mxs_spl_fixup_vectors();
+
+	mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
+
+	mxs_spl_console_init();
+
+	mxs_power_init();
+
+	mxs_mem_init();
+	data->mem_dram_size = mxs_mem_get_size();
+
+	data->boot_mode_idx = bootmode;
+
+	mxs_power_wait_pswitch();
+}
+
+/* Support aparatus */
+inline void board_init_f(unsigned long bootflag)
+{
+	for (;;)
+		;
+}
+
+inline void board_init_r(gd_t *id, ulong dest_addr)
+{
+	for (;;)
+		;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
new file mode 100644
index 000000000..cdfcddd82
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
@@ -0,0 +1,70 @@
+/*
+ * Freescale i.MX28 Battery measurement init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+#include "mxs_init.h"
+
+void mxs_lradc_init(void)
+{
+	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
+
+	writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
+	writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
+	writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);
+
+	clrsetbits_le32(&regs->hw_lradc_ctrl3,
+			LRADC_CTRL3_CYCLE_TIME_MASK,
+			LRADC_CTRL3_CYCLE_TIME_6MHZ);
+
+	clrsetbits_le32(&regs->hw_lradc_ctrl4,
+			LRADC_CTRL4_LRADC7SELECT_MASK |
+			LRADC_CTRL4_LRADC6SELECT_MASK,
+			LRADC_CTRL4_LRADC7SELECT_CHANNEL7 |
+			LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
+}
+
+void mxs_lradc_enable_batt_measurement(void)
+{
+	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
+
+	/* Check if the channel is present at all. */
+	if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
+		return;
+
+	writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
+	writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);
+
+	clrsetbits_le32(&regs->hw_lradc_conversion,
+			LRADC_CONVERSION_SCALE_FACTOR_MASK,
+			LRADC_CONVERSION_SCALE_FACTOR_LI_ION);
+	writel(LRADC_CONVERSION_AUTOMATIC, &regs->hw_lradc_conversion_set);
+
+	/* Configure the channel. */
+	writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
+		&regs->hw_lradc_ctrl2_clr);
+	writel(0xffffffff, &regs->hw_lradc_ch7_clr);
+	clrbits_le32(&regs->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK);
+	writel(LRADC_CH_ACCUMULATE, &regs->hw_lradc_ch7_clr);
+
+	/* Schedule the channel. */
+	writel(1 << 7, &regs->hw_lradc_ctrl0_set);
+
+	/* Start the channel sampling. */
+	writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) |
+		((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) |
+		100, &regs->hw_lradc_delay3);
+
+	writel(0xffffffff, &regs->hw_lradc_ch7_clr);
+
+	writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
new file mode 100644
index 000000000..3baf4ddef
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -0,0 +1,331 @@
+/*
+ * Freescale i.MX28 RAM init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/compiler.h>
+
+#include "mxs_init.h"
+
+static uint32_t dram_vals[] = {
+/*
+ * i.MX28 DDR2 at 200MHz
+ */
+#if defined(CONFIG_MX28)
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000100, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010101, 0x01010101,
+	0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
+	0x00000100, 0x00000100, 0x00000000, 0x00000002,
+	0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
+	0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
+	0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00000003, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000612, 0x01000F02,
+	0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
+	0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300,
+	0x07000300, 0x07400300, 0x07400300, 0x00000005,
+	0x00000000, 0x00000000, 0x01000000, 0x01020408,
+	0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010000, 0x00030404,
+	0x00000003, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x01010000,
+	0x01000000, 0x03030000, 0x00010303, 0x01020202,
+	0x00000000, 0x02040303, 0x21002103, 0x00061200,
+	0x06120612, 0x04420442, 0x04420442, 0x00040004,
+	0x00040004, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0xffffffff
+
+/*
+ * i.MX23 DDR at 133MHz
+ */
+#elif defined(CONFIG_MX23)
+	0x01010001, 0x00010100, 0x01000101, 0x00000001,
+	0x00000101, 0x00000000, 0x00010000, 0x01000001,
+	0x00000000, 0x00000001, 0x07000200, 0x00070202,
+	0x02020000, 0x04040a01, 0x00000201, 0x02040000,
+	0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
+	0x02061521, 0x0000000a, 0x00080008, 0x00200020,
+	0x00200020, 0x00200020, 0x000003f7, 0x00000000,
+	0x00000000, 0x00000020, 0x00000020, 0x00c80000,
+	0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
+	0x00000101, 0x00040001, 0x00000000, 0x00000000,
+	0x00010000
+#else
+#error Unsupported memory initialization
+#endif
+};
+
+__weak void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+}
+
+#ifdef CONFIG_MX28
+static void initialize_dram_values(void)
+{
+	int i;
+
+	mxs_adjust_memory_params(dram_vals);
+
+	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
+		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+}
+#else
+static void initialize_dram_values(void)
+{
+	int i;
+
+	mxs_adjust_memory_params(dram_vals);
+
+	/*
+	 * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
+	 * per FSL bootlets code.
+	 *
+	 * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
+	 * "reserved".
+	 * HW_DRAM_CTL8 is setup as the last element.
+	 * So skip the initialization of these HW_DRAM_CTL registers.
+	 */
+	for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
+		if (i == 8 || i == 27 || i == 28 || i == 35)
+			continue;
+		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+	}
+
+	/*
+	 * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
+	 * element to be set
+	 */
+	writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
+}
+#endif
+
+static void mxs_mem_init_clock(void)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+#if defined(CONFIG_MX23)
+	/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
+	const unsigned char divider = 33;
+#elif defined(CONFIG_MX28)
+	/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
+	const unsigned char divider = 21;
+#endif
+
+	/* Gate EMI clock */
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
+
+	/* Set fractional divider for ref_emi */
+	writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
+
+	/* Ungate EMI clock */
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
+
+	early_delay(11000);
+
+	/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
+	writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
+		(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
+		&clkctrl_regs->hw_clkctrl_emi);
+
+	/* Unbypass EMI */
+	writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
+		&clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+	early_delay(10000);
+}
+
+static void mxs_mem_setup_cpu_and_hbus(void)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
+	 * and ungate CPU clock */
+	writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
+		(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
+
+	/* Set CPU bypass */
+	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+		&clkctrl_regs->hw_clkctrl_clkseq_set);
+
+	/* HBUS = 151MHz */
+	writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
+	writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
+		&clkctrl_regs->hw_clkctrl_hbus_clr);
+
+	early_delay(10000);
+
+	/* CPU clock divider = 1 */
+	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
+			CLKCTRL_CPU_DIV_CPU_MASK, 1);
+
+	/* Disable CPU bypass */
+	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+		&clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+	early_delay(15000);
+}
+
+static void mxs_mem_setup_vdda(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
+		(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
+		POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
+		&power_regs->hw_power_vddactrl);
+}
+
+uint32_t mxs_mem_get_size(void)
+{
+	uint32_t sz, da;
+	uint32_t *vt = (uint32_t *)0x20;
+	/* The following is "subs pc, r14, #4", used as return from DABT. */
+	const uint32_t data_abort_memdetect_handler = 0xe25ef004;
+
+	/* Replace the DABT handler. */
+	da = vt[4];
+	vt[4] = data_abort_memdetect_handler;
+
+	sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+
+	/* Restore the old DABT handler. */
+	vt[4] = da;
+
+	return sz;
+}
+
+#ifdef CONFIG_MX23
+static void mx23_mem_setup_vddmem(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	clrbits_le32(&power_regs->hw_power_vddmemctrl,
+		POWER_VDDMEMCTRL_ENABLE_ILIMIT);
+
+}
+
+static void mx23_mem_init(void)
+{
+	/*
+	 * Reset/ungate the EMI block. This is essential, otherwise the system
+	 * suffers from memory instability. This thing is mx23 specific and is
+	 * no longer present on mx28.
+	 */
+	mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
+
+	mx23_mem_setup_vddmem();
+
+	/*
+	 * Configure the DRAM registers
+	 */
+
+	/* Clear START and SREFRESH bit from DRAM_CTL8 */
+	clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
+
+	initialize_dram_values();
+
+	/* Set START bit in DRAM_CTL8 */
+	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
+
+	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
+	early_delay(20000);
+
+	/* Adjust EMI port priority. */
+	clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
+	early_delay(20000);
+
+	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
+	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
+}
+#endif
+
+#ifdef CONFIG_MX28
+static void mx28_mem_init(void)
+{
+	struct mxs_pinctrl_regs *pinctrl_regs =
+		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
+
+	/* Set DDR2 mode */
+	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
+		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
+
+	/*
+	 * Configure the DRAM registers
+	 */
+
+	/* Clear START bit from DRAM_CTL16 */
+	clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
+
+	initialize_dram_values();
+
+	/* Clear SREFRESH bit from DRAM_CTL17 */
+	clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
+
+	/* Set START bit in DRAM_CTL16 */
+	setbits_le32(MXS_DRAM_BASE + 0x40, 1);
+
+	/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
+	while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
+		;
+}
+#endif
+
+void mxs_mem_init(void)
+{
+	early_delay(11000);
+
+	mxs_mem_init_clock();
+
+	mxs_mem_setup_vdda();
+
+#if defined(CONFIG_MX23)
+	mx23_mem_init();
+#elif defined(CONFIG_MX28)
+	mx28_mem_init();
+#endif
+
+	early_delay(10000);
+
+	mxs_mem_setup_cpu_and_hbus();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
new file mode 100644
index 000000000..d25019a51
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -0,0 +1,1155 @@
+/*
+ * Freescale i.MX28 Boot PMIC init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+#include "mxs_init.h"
+
+/**
+ * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
+ *
+ * This function switches the CPU core clock from PLL to 24MHz XTAL
+ * oscilator. This is necessary if the PLL is being reconfigured to
+ * prevent crash of the CPU core.
+ */
+static void mxs_power_clock2xtal(void)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	/* Set XTAL as CPU reference clock */
+	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+		&clkctrl_regs->hw_clkctrl_clkseq_set);
+}
+
+/**
+ * mxs_power_clock2pll() - Switch CPU core clock source to PLL
+ *
+ * This function switches the CPU core clock from 24MHz XTAL oscilator
+ * to PLL. This can only be called once the PLL has re-locked and once
+ * the PLL is stable after reconfiguration.
+ */
+static void mxs_power_clock2pll(void)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
+			CLKCTRL_PLL0CTRL0_POWER);
+	early_delay(100);
+	setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
+			CLKCTRL_CLKSEQ_BYPASS_CPU);
+}
+
+/**
+ * mxs_power_set_auto_restart() - Set the auto-restart bit
+ *
+ * This function ungates the RTC block and sets the AUTO_RESTART
+ * bit to work around a design bug on MX28EVK Rev. A .
+ */
+
+static void mxs_power_set_auto_restart(void)
+{
+	struct mxs_rtc_regs *rtc_regs =
+		(struct mxs_rtc_regs *)MXS_RTC_BASE;
+
+	writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
+	while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
+		;
+
+	writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
+	while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
+		;
+
+	/* Do nothing if flag already set */
+	if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
+		return;
+
+	while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
+		;
+
+	setbits_le32(&rtc_regs->hw_rtc_persistent0,
+			RTC_PERSISTENT0_AUTO_RESTART);
+	writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
+	writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
+	while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
+		;
+	while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
+		;
+}
+
+/**
+ * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
+ *
+ * This function configures the VDDIO, VDDA and VDDD linear regulators output
+ * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
+ * converter. This is the recommended setting for the case where we use both
+ * linear regulators and DC-DC converter to power the VDDIO rail.
+ */
+static void mxs_power_set_linreg(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	/* Set linear regulator 25mV below switching converter */
+	clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+			POWER_VDDDCTRL_LINREG_OFFSET_MASK,
+			POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+	clrsetbits_le32(&power_regs->hw_power_vddactrl,
+			POWER_VDDACTRL_LINREG_OFFSET_MASK,
+			POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+	clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+			POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
+			POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
+}
+
+/**
+ * mxs_get_batt_volt() - Measure battery input voltage
+ *
+ * This function retrieves the battery input voltage and returns it.
+ */
+static int mxs_get_batt_volt(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+	volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+	volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+	volt *= 8;
+	return volt;
+}
+
+/**
+ * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
+ *
+ * This function checks if the battery input voltage is higher than 3.6V and
+ * therefore allows the system to successfully boot using this power source.
+ */
+static int mxs_is_batt_ready(void)
+{
+	return (mxs_get_batt_volt() >= 3600);
+}
+
+/**
+ * mxs_is_batt_good() - Test if battery is operational at all
+ *
+ * This function starts recharging the battery and tests if the input current
+ * provided by the 5V input recharging the battery is also sufficient to power
+ * the DC-DC converter.
+ */
+static int mxs_is_batt_good(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	uint32_t volt = mxs_get_batt_volt();
+
+	if ((volt >= 2400) && (volt <= 4300))
+		return 1;
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+		0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+		&power_regs->hw_power_5vctrl_clr);
+
+	clrsetbits_le32(&power_regs->hw_power_charge,
+		POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+		POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
+
+	writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
+	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+		&power_regs->hw_power_5vctrl_clr);
+
+	early_delay(500000);
+
+	volt = mxs_get_batt_volt();
+
+	if (volt >= 3500)
+		return 0;
+
+	if (volt >= 2400)
+		return 1;
+
+	writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+		&power_regs->hw_power_charge_clr);
+	writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+
+	return 0;
+}
+
+/**
+ * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
+ *
+ * This function enables the 5V detection comparator and sets the 5V valid
+ * threshold to 4.4V . We use 4.4V threshold here to make sure that even
+ * under high load, the voltage drop on the 5V input won't be so critical
+ * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
+ * converter and thus making the system crash.
+ */
+static void mxs_power_setup_5v_detect(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	/* Start 5V detection */
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+			POWER_5VCTRL_VBUSVALID_TRSH_MASK,
+			POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
+			POWER_5VCTRL_PWRUP_VBUS_CMPS);
+}
+
+/**
+ * mxs_src_power_init() - Preconfigure the power block
+ *
+ * This function configures reasonable values for the DC-DC control loop
+ * and battery monitor.
+ */
+static void mxs_src_power_init(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	/* Improve efficieny and reduce transient ripple */
+	writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
+		POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
+
+	clrsetbits_le32(&power_regs->hw_power_dclimits,
+			POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
+			0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
+
+	setbits_le32(&power_regs->hw_power_battmonitor,
+			POWER_BATTMONITOR_EN_BATADJ);
+
+	/* Increase the RCSCALE level for quick DCDC response to dynamic load */
+	clrsetbits_le32(&power_regs->hw_power_loopctrl,
+			POWER_LOOPCTRL_EN_RCSCALE_MASK,
+			POWER_LOOPCTRL_RCSCALE_THRESH |
+			POWER_LOOPCTRL_EN_RCSCALE_8X);
+
+	clrsetbits_le32(&power_regs->hw_power_minpwr,
+			POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
+
+	/* 5V to battery handoff ... FIXME */
+	setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+	early_delay(30);
+	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+}
+
+/**
+ * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
+ *
+ * This function configures the necessary parameters for the 4P2 linear
+ * regulator to supply the DC-DC converter from 5V input.
+ */
+static void mxs_power_init_4p2_params(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	/* Setup 4P2 parameters */
+	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+		POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
+		POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_HEADROOM_ADJ_MASK,
+		0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
+
+	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+		POWER_DCDC4P2_DROPOUT_CTRL_MASK,
+		POWER_DCDC4P2_DROPOUT_CTRL_100MV |
+		POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+		0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+}
+
+/**
+ * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
+ * @xfer:	Select if the input shall be enabled or disabled
+ *
+ * This function enables or disables the 4P2 input into the DC-DC converter.
+ */
+static void mxs_enable_4p2_dcdc_input(int xfer)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
+	uint32_t prev_5v_brnout, prev_5v_droop;
+
+	prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
+				POWER_5VCTRL_PWDN_5VBRNOUT;
+	prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
+				POWER_CTRL_ENIRQ_VDD5V_DROOP;
+
+	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
+	writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+		&power_regs->hw_power_reset);
+
+	clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
+
+	if (xfer && (readl(&power_regs->hw_power_5vctrl) &
+			POWER_5VCTRL_ENABLE_DCDC)) {
+		return;
+	}
+
+	/*
+	 * Recording orignal values that will be modified temporarlily
+	 * to handle a chip bug. See chip errata for CQ ENGR00115837
+	 */
+	tmp = readl(&power_regs->hw_power_5vctrl);
+	vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
+	vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
+
+	pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
+
+	/*
+	 * Disable mechanisms that get erroneously tripped by when setting
+	 * the DCDC4P2 EN_DCDC
+	 */
+	clrbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_VBUSVALID_5VDETECT |
+		POWER_5VCTRL_VBUSVALID_TRSH_MASK);
+
+	writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
+
+	if (xfer) {
+		setbits_le32(&power_regs->hw_power_5vctrl,
+				POWER_5VCTRL_DCDC_XFER);
+		early_delay(20);
+		clrbits_le32(&power_regs->hw_power_5vctrl,
+				POWER_5VCTRL_DCDC_XFER);
+
+		setbits_le32(&power_regs->hw_power_5vctrl,
+				POWER_5VCTRL_ENABLE_DCDC);
+	} else {
+		setbits_le32(&power_regs->hw_power_dcdc4p2,
+				POWER_DCDC4P2_ENABLE_DCDC);
+	}
+
+	early_delay(25);
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+			POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
+
+	if (vbus_5vdetect)
+		writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
+
+	if (!pwd_bo)
+		clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
+
+	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
+		writel(POWER_CTRL_VBUS_VALID_IRQ,
+			&power_regs->hw_power_ctrl_clr);
+
+	if (prev_5v_brnout) {
+		writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+			&power_regs->hw_power_5vctrl_set);
+		writel(POWER_RESET_UNLOCK_KEY,
+			&power_regs->hw_power_reset);
+	} else {
+		writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+			&power_regs->hw_power_5vctrl_clr);
+		writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+			&power_regs->hw_power_reset);
+	}
+
+	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
+		writel(POWER_CTRL_VDD5V_DROOP_IRQ,
+			&power_regs->hw_power_ctrl_clr);
+
+	if (prev_5v_droop)
+		clrbits_le32(&power_regs->hw_power_ctrl,
+				POWER_CTRL_ENIRQ_VDD5V_DROOP);
+	else
+		setbits_le32(&power_regs->hw_power_ctrl,
+				POWER_CTRL_ENIRQ_VDD5V_DROOP);
+}
+
+/**
+ * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
+ *
+ * This function enables the 4P2 regulator and switches the DC-DC converter
+ * to use the 4P2 input.
+ */
+static void mxs_power_init_4p2_regulator(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	uint32_t tmp, tmp2;
+
+	setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
+
+	writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
+
+	writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+		&power_regs->hw_power_5vctrl_clr);
+	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
+
+	/* Power up the 4p2 rail and logic/control */
+	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+		&power_regs->hw_power_5vctrl_clr);
+
+	/*
+	 * Start charging up the 4p2 capacitor. We ramp of this charge
+	 * gradually to avoid large inrush current from the 5V cable which can
+	 * cause transients/problems
+	 */
+	mxs_enable_4p2_dcdc_input(0);
+
+	if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
+		/*
+		 * If we arrived here, we were unable to recover from mx23 chip
+		 * errata 5837. 4P2 is disabled and sufficient battery power is
+		 * not present. Exiting to not enable DCDC power during 5V
+		 * connected state.
+		 */
+		clrbits_le32(&power_regs->hw_power_dcdc4p2,
+			POWER_DCDC4P2_ENABLE_DCDC);
+		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+			&power_regs->hw_power_5vctrl_set);
+		hang();
+	}
+
+	/*
+	 * Here we set the 4p2 brownout level to something very close to 4.2V.
+	 * We then check the brownout status. If the brownout status is false,
+	 * the voltage is already close to the target voltage of 4.2V so we
+	 * can go ahead and set the 4P2 current limit to our max target limit.
+	 * If the brownout status is true, we need to ramp us the current limit
+	 * so that we don't cause large inrush current issues. We step up the
+	 * current limit until the brownout status is false or until we've
+	 * reached our maximum defined 4p2 current limit.
+	 */
+	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+			POWER_DCDC4P2_BO_MASK,
+			22 << POWER_DCDC4P2_BO_OFFSET);	/* 4.15V */
+
+	if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
+		setbits_le32(&power_regs->hw_power_5vctrl,
+			0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+	} else {
+		tmp = (readl(&power_regs->hw_power_5vctrl) &
+			POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
+			POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+		while (tmp < 0x3f) {
+			if (!(readl(&power_regs->hw_power_sts) &
+					POWER_STS_DCDC_4P2_BO)) {
+				tmp = readl(&power_regs->hw_power_5vctrl);
+				tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+				early_delay(100);
+				writel(tmp, &power_regs->hw_power_5vctrl);
+				break;
+			} else {
+				tmp++;
+				tmp2 = readl(&power_regs->hw_power_5vctrl);
+				tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+				tmp2 |= tmp <<
+					POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+				writel(tmp2, &power_regs->hw_power_5vctrl);
+				early_delay(100);
+			}
+		}
+	}
+
+	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
+	writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+}
+
+/**
+ * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
+ *
+ * This function configures the DC-DC converter to be supplied from the 4P2
+ * linear regulator.
+ */
+static void mxs_power_init_dcdc_4p2_source(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	if (!(readl(&power_regs->hw_power_dcdc4p2) &
+		POWER_DCDC4P2_ENABLE_DCDC)) {
+		hang();
+	}
+
+	mxs_enable_4p2_dcdc_input(1);
+
+	if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
+		clrbits_le32(&power_regs->hw_power_dcdc4p2,
+			POWER_DCDC4P2_ENABLE_DCDC);
+		writel(POWER_5VCTRL_ENABLE_DCDC,
+			&power_regs->hw_power_5vctrl_clr);
+		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+			&power_regs->hw_power_5vctrl_set);
+	}
+}
+
+/**
+ * mxs_power_enable_4p2() - Power up the 4P2 regulator
+ *
+ * This function drives the process of powering up the 4P2 linear regulator
+ * and switching the DC-DC converter input over to the 4P2 linear regulator.
+ */
+static void mxs_power_enable_4p2(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	uint32_t vdddctrl, vddactrl, vddioctrl;
+	uint32_t tmp;
+
+	vdddctrl = readl(&power_regs->hw_power_vdddctrl);
+	vddactrl = readl(&power_regs->hw_power_vddactrl);
+	vddioctrl = readl(&power_regs->hw_power_vddioctrl);
+
+	setbits_le32(&power_regs->hw_power_vdddctrl,
+		POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
+		POWER_VDDDCTRL_PWDN_BRNOUT);
+
+	setbits_le32(&power_regs->hw_power_vddactrl,
+		POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
+		POWER_VDDACTRL_PWDN_BRNOUT);
+
+	setbits_le32(&power_regs->hw_power_vddioctrl,
+		POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
+
+	mxs_power_init_4p2_params();
+	mxs_power_init_4p2_regulator();
+
+	/* Shutdown battery (none present) */
+	if (!mxs_is_batt_ready()) {
+		clrbits_le32(&power_regs->hw_power_dcdc4p2,
+				POWER_DCDC4P2_BO_MASK);
+		writel(POWER_CTRL_DCDC4P2_BO_IRQ,
+				&power_regs->hw_power_ctrl_clr);
+		writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
+				&power_regs->hw_power_ctrl_clr);
+	}
+
+	mxs_power_init_dcdc_4p2_source();
+
+	writel(vdddctrl, &power_regs->hw_power_vdddctrl);
+	early_delay(20);
+	writel(vddactrl, &power_regs->hw_power_vddactrl);
+	early_delay(20);
+	writel(vddioctrl, &power_regs->hw_power_vddioctrl);
+
+	/*
+	 * Check if FET is enabled on either powerout and if so,
+	 * disable load.
+	 */
+	tmp = 0;
+	tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
+			POWER_VDDDCTRL_DISABLE_FET);
+	tmp |= !(readl(&power_regs->hw_power_vddactrl) &
+			POWER_VDDACTRL_DISABLE_FET);
+	tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
+			POWER_VDDIOCTRL_DISABLE_FET);
+	if (tmp)
+		writel(POWER_CHARGE_ENABLE_LOAD,
+			&power_regs->hw_power_charge_clr);
+}
+
+/**
+ * mxs_boot_valid_5v() - Boot from 5V supply
+ *
+ * This function configures the power block to boot from valid 5V input.
+ * This is called only if the 5V is reliable and can properly supply the
+ * CPU. This function proceeds to configure the 4P2 converter to be supplied
+ * from the 5V input.
+ */
+static void mxs_boot_valid_5v(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	/*
+	 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
+	 * disconnect event. FIXME
+	 */
+	writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
+		&power_regs->hw_power_5vctrl_set);
+
+	/* Configure polarity to check for 5V disconnection. */
+	writel(POWER_CTRL_POLARITY_VBUSVALID |
+		POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
+		&power_regs->hw_power_ctrl_clr);
+
+	writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
+		&power_regs->hw_power_ctrl_clr);
+
+	mxs_power_enable_4p2();
+}
+
+/**
+ * mxs_powerdown() - Shut down the system
+ *
+ * This function powers down the CPU completely.
+ */
+static void mxs_powerdown(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
+	writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+		&power_regs->hw_power_reset);
+}
+
+/**
+ * mxs_batt_boot() - Configure the power block to boot from battery input
+ *
+ * This function configures the power block to boot from the battery voltage
+ * supply.
+ */
+static void mxs_batt_boot(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
+	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
+
+	clrbits_le32(&power_regs->hw_power_dcdc4p2,
+			POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
+	writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
+
+	/* 5V to battery handoff. */
+	setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+	early_delay(30);
+	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+
+	writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
+
+	clrsetbits_le32(&power_regs->hw_power_minpwr,
+			POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
+
+	mxs_power_set_linreg();
+
+	clrbits_le32(&power_regs->hw_power_vdddctrl,
+		POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
+
+	clrbits_le32(&power_regs->hw_power_vddactrl,
+		POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
+
+	clrbits_le32(&power_regs->hw_power_vddioctrl,
+		POWER_VDDIOCTRL_DISABLE_FET);
+
+	setbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
+
+	setbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_ENABLE_DCDC);
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+		0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+
+	mxs_power_enable_4p2();
+}
+
+/**
+ * mxs_handle_5v_conflict() - Test if the 5V input is reliable
+ *
+ * This function tests if the 5V input can reliably supply the system. If it
+ * can, then proceed to configuring the system to boot from 5V source, otherwise
+ * try booting from battery supply. If we can not boot from battery supply
+ * either, shut down the system.
+ */
+static void mxs_handle_5v_conflict(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	uint32_t tmp;
+
+	setbits_le32(&power_regs->hw_power_vddioctrl,
+			POWER_VDDIOCTRL_BO_OFFSET_MASK);
+
+	for (;;) {
+		tmp = readl(&power_regs->hw_power_sts);
+
+		if (tmp & POWER_STS_VDDIO_BO) {
+			/*
+			 * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
+			 * unreliable
+			 */
+			mxs_powerdown();
+			break;
+		}
+
+		if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
+			mxs_boot_valid_5v();
+			break;
+		} else {
+			mxs_powerdown();
+			break;
+		}
+
+		if (tmp & POWER_STS_PSWITCH_MASK) {
+			mxs_batt_boot();
+			break;
+		}
+	}
+}
+
+/**
+ * mxs_5v_boot() - Configure the power block to boot from 5V input
+ *
+ * This function handles configuration of the power block when supplied by
+ * a 5V input.
+ */
+static void mxs_5v_boot(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	/*
+	 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
+	 * but their implementation always returns 1 so we omit it here.
+	 */
+	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+		mxs_boot_valid_5v();
+		return;
+	}
+
+	early_delay(1000);
+	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+		mxs_boot_valid_5v();
+		return;
+	}
+
+	mxs_handle_5v_conflict();
+}
+
+/**
+ * mxs_init_batt_bo() - Configure battery brownout threshold
+ *
+ * This function configures the battery input brownout threshold. The value
+ * at which the battery brownout happens is configured to 3.0V in the code.
+ */
+static void mxs_init_batt_bo(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	/* Brownout at 3V */
+	clrsetbits_le32(&power_regs->hw_power_battmonitor,
+		POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
+		15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+
+	writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+	writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
+}
+
+/**
+ * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
+ *
+ * This function turns off the VDDD linear regulator and therefore makes
+ * the VDDD rail be supplied only by the DC-DC converter.
+ */
+static void mxs_switch_vddd_to_dcdc_source(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+		POWER_VDDDCTRL_LINREG_OFFSET_MASK,
+		POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+	clrbits_le32(&power_regs->hw_power_vdddctrl,
+		POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
+		POWER_VDDDCTRL_DISABLE_STEPPING);
+}
+
+/**
+ * mxs_power_configure_power_source() - Configure power block source
+ *
+ * This function is the core of the power configuration logic. The function
+ * selects the power block input source and configures the whole power block
+ * accordingly. After the configuration is complete and the system is stable
+ * again, the function switches the CPU clock source back to PLL. Finally,
+ * the function switches the voltage rails to DC-DC converter.
+ */
+static void mxs_power_configure_power_source(void)
+{
+	int batt_ready, batt_good;
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	struct mxs_lradc_regs *lradc_regs =
+		(struct mxs_lradc_regs *)MXS_LRADC_BASE;
+
+	mxs_src_power_init();
+
+	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+		batt_ready = mxs_is_batt_ready();
+		if (batt_ready) {
+			/* 5V source detected, good battery detected. */
+			mxs_batt_boot();
+		} else {
+			batt_good = mxs_is_batt_good();
+			if (!batt_good) {
+				/* 5V source detected, bad battery detected. */
+				writel(LRADC_CONVERSION_AUTOMATIC,
+					&lradc_regs->hw_lradc_conversion_clr);
+				clrbits_le32(&power_regs->hw_power_battmonitor,
+					POWER_BATTMONITOR_BATT_VAL_MASK);
+			}
+			mxs_5v_boot();
+		}
+	} else {
+		/* 5V not detected, booting from battery. */
+		mxs_batt_boot();
+	}
+
+	mxs_power_clock2pll();
+
+	mxs_init_batt_bo();
+
+	mxs_switch_vddd_to_dcdc_source();
+
+#ifdef CONFIG_MX23
+	/* Fire up the VDDMEM LinReg now that we're all set. */
+	writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
+		&power_regs->hw_power_vddmemctrl);
+#endif
+}
+
+/**
+ * mxs_enable_output_rail_protection() - Enable power rail protection
+ *
+ * This function enables overload protection on the power rails. This is
+ * triggered if the power rails' voltage drops rapidly due to overload and
+ * in such case, the supply to the powerrail is cut-off, protecting the
+ * CPU from damage. Note that under such condition, the system will likely
+ * crash or misbehave.
+ */
+static void mxs_enable_output_rail_protection(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
+		POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+
+	setbits_le32(&power_regs->hw_power_vdddctrl,
+			POWER_VDDDCTRL_PWDN_BRNOUT);
+
+	setbits_le32(&power_regs->hw_power_vddactrl,
+			POWER_VDDACTRL_PWDN_BRNOUT);
+
+	setbits_le32(&power_regs->hw_power_vddioctrl,
+			POWER_VDDIOCTRL_PWDN_BRNOUT);
+}
+
+/**
+ * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
+ *
+ * This function tests if the VDDIO rail is supplied by linear regulator
+ * or by the DC-DC converter. Returns 1 if powered by linear regulator,
+ * returns 0 if powered by the DC-DC converter.
+ */
+static int mxs_get_vddio_power_source_off(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	uint32_t tmp;
+
+	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+		tmp = readl(&power_regs->hw_power_vddioctrl);
+		if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
+			if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
+				POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
+				return 1;
+			}
+		}
+
+		if (!(readl(&power_regs->hw_power_5vctrl) &
+			POWER_5VCTRL_ENABLE_DCDC)) {
+			if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
+				POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
+				return 1;
+			}
+		}
+	}
+
+	return 0;
+
+}
+
+/**
+ * mxs_get_vddd_power_source_off() - Get VDDD rail power source
+ *
+ * This function tests if the VDDD rail is supplied by linear regulator
+ * or by the DC-DC converter. Returns 1 if powered by linear regulator,
+ * returns 0 if powered by the DC-DC converter.
+ */
+static int mxs_get_vddd_power_source_off(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	uint32_t tmp;
+
+	tmp = readl(&power_regs->hw_power_vdddctrl);
+	if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
+		if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
+			POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+			return 1;
+		}
+	}
+
+	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+		if (!(readl(&power_regs->hw_power_5vctrl) &
+			POWER_5VCTRL_ENABLE_DCDC)) {
+			return 1;
+		}
+	}
+
+	if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
+		if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
+			POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+struct mxs_vddx_cfg {
+	uint32_t		*reg;
+	uint8_t			step_mV;
+	uint16_t		lowest_mV;
+	int			(*powered_by_linreg)(void);
+	uint32_t		trg_mask;
+	uint32_t		bo_irq;
+	uint32_t		bo_enirq;
+	uint32_t		bo_offset_mask;
+	uint32_t		bo_offset_offset;
+};
+
+static const struct mxs_vddx_cfg mxs_vddio_cfg = {
+	.reg			= &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+					hw_power_vddioctrl),
+#if defined(CONFIG_MX23)
+	.step_mV		= 25,
+#else
+	.step_mV		= 50,
+#endif
+	.lowest_mV		= 2800,
+	.powered_by_linreg	= mxs_get_vddio_power_source_off,
+	.trg_mask		= POWER_VDDIOCTRL_TRG_MASK,
+	.bo_irq			= POWER_CTRL_VDDIO_BO_IRQ,
+	.bo_enirq		= POWER_CTRL_ENIRQ_VDDIO_BO,
+	.bo_offset_mask		= POWER_VDDIOCTRL_BO_OFFSET_MASK,
+	.bo_offset_offset	= POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
+};
+
+static const struct mxs_vddx_cfg mxs_vddd_cfg = {
+	.reg			= &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+					hw_power_vdddctrl),
+	.step_mV		= 25,
+	.lowest_mV		= 800,
+	.powered_by_linreg	= mxs_get_vddd_power_source_off,
+	.trg_mask		= POWER_VDDDCTRL_TRG_MASK,
+	.bo_irq			= POWER_CTRL_VDDD_BO_IRQ,
+	.bo_enirq		= POWER_CTRL_ENIRQ_VDDD_BO,
+	.bo_offset_mask		= POWER_VDDDCTRL_BO_OFFSET_MASK,
+	.bo_offset_offset	= POWER_VDDDCTRL_BO_OFFSET_OFFSET,
+};
+
+#ifdef CONFIG_MX23
+static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
+	.reg			= &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+					hw_power_vddmemctrl),
+	.step_mV		= 50,
+	.lowest_mV		= 1700,
+	.powered_by_linreg	= NULL,
+	.trg_mask		= POWER_VDDMEMCTRL_TRG_MASK,
+	.bo_irq			= 0,
+	.bo_enirq		= 0,
+	.bo_offset_mask		= 0,
+	.bo_offset_offset	= 0,
+};
+#endif
+
+/**
+ * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
+ * @cfg:		Configuration data of the DC-DC converter rail
+ * @new_target:		New target voltage of the DC-DC converter rail
+ * @new_brownout:	New brownout trigger voltage
+ *
+ * This function configures the output voltage on the DC-DC converter rail.
+ * The rail is selected by the @cfg argument. The new voltage target is
+ * selected by the @new_target and the voltage is specified in mV. The
+ * new brownout value is selected by the @new_brownout argument and the
+ * value is also in mV.
+ */
+static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
+				uint32_t new_target, uint32_t new_brownout)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+	uint32_t cur_target, diff, bo_int = 0;
+	uint32_t powered_by_linreg = 0;
+	int adjust_up, tmp;
+
+	new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
+
+	cur_target = readl(cfg->reg);
+	cur_target &= cfg->trg_mask;
+	cur_target *= cfg->step_mV;
+	cur_target += cfg->lowest_mV;
+
+	adjust_up = new_target > cur_target;
+	if (cfg->powered_by_linreg)
+		powered_by_linreg = cfg->powered_by_linreg();
+
+	if (adjust_up && cfg->bo_irq) {
+		if (powered_by_linreg) {
+			bo_int = readl(cfg->reg);
+			clrbits_le32(cfg->reg, cfg->bo_enirq);
+		}
+		setbits_le32(cfg->reg, cfg->bo_offset_mask);
+	}
+
+	do {
+		if (abs(new_target - cur_target) > 100) {
+			if (adjust_up)
+				diff = cur_target + 100;
+			else
+				diff = cur_target - 100;
+		} else {
+			diff = new_target;
+		}
+
+		diff -= cfg->lowest_mV;
+		diff /= cfg->step_mV;
+
+		clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
+
+		if (powered_by_linreg ||
+			(readl(&power_regs->hw_power_sts) &
+				POWER_STS_VDD5V_GT_VDDIO))
+			early_delay(500);
+		else {
+			for (;;) {
+				tmp = readl(&power_regs->hw_power_sts);
+				if (tmp & POWER_STS_DC_OK)
+					break;
+			}
+		}
+
+		cur_target = readl(cfg->reg);
+		cur_target &= cfg->trg_mask;
+		cur_target *= cfg->step_mV;
+		cur_target += cfg->lowest_mV;
+	} while (new_target > cur_target);
+
+	if (cfg->bo_irq) {
+		if (adjust_up && powered_by_linreg) {
+			writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
+			if (bo_int & cfg->bo_enirq)
+				setbits_le32(cfg->reg, cfg->bo_enirq);
+		}
+
+		clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
+				new_brownout << cfg->bo_offset_offset);
+	}
+}
+
+/**
+ * mxs_setup_batt_detect() - Start the battery voltage measurement logic
+ *
+ * This function starts and configures the LRADC block. This allows the
+ * power initialization code to measure battery voltage and based on this
+ * knowledge, decide whether to boot at all, boot from battery or boot
+ * from 5V input.
+ */
+static void mxs_setup_batt_detect(void)
+{
+	mxs_lradc_init();
+	mxs_lradc_enable_batt_measurement();
+	early_delay(10);
+}
+
+/**
+ * mxs_ungate_power() - Ungate the POWER block
+ *
+ * This function ungates clock to the power block. In case the power block
+ * was still gated at this point, it will not be possible to configure the
+ * block and therefore the power initialization would fail. This function
+ * is only needed on i.MX233, on i.MX28 the power block is always ungated.
+ */
+static void mxs_ungate_power(void)
+{
+#ifdef CONFIG_MX23
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
+#endif
+}
+
+/**
+ * mxs_power_init() - The power block init main function
+ *
+ * This function calls all the power block initialization functions in
+ * proper sequence to start the power block.
+ */
+void mxs_power_init(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	mxs_ungate_power();
+
+	mxs_power_clock2xtal();
+	mxs_power_set_auto_restart();
+	mxs_power_set_linreg();
+	mxs_power_setup_5v_detect();
+
+	mxs_setup_batt_detect();
+
+	mxs_power_configure_power_source();
+	mxs_enable_output_rail_protection();
+
+	mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
+	mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
+#ifdef CONFIG_MX23
+	mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
+#endif
+	writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
+		POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
+		POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
+		POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+
+	writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
+
+	early_delay(1000);
+}
+
+#ifdef	CONFIG_SPL_MXS_PSWITCH_WAIT
+/**
+ * mxs_power_wait_pswitch() - Wait for power switch to be pressed
+ *
+ * This function waits until the power-switch was pressed to start booting
+ * the board.
+ */
+void mxs_power_wait_pswitch(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
+		;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/start.S
new file mode 100644
index 000000000..34a0fcb46
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/start.S
@@ -0,0 +1,185 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Groger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Zupke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
+ *
+ * Change to support call back into iMX28 bootrom
+ * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <version.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:
+	b	reset
+	b	undefined_instruction
+	b	software_interrupt
+	b	prefetch_abort
+	b	data_abort
+	b	not_used
+	b	irq
+	b	fiq
+
+/*
+ * Vector table, located at address 0x20.
+ * This table allows the code running AFTER SPL, the U-Boot, to install it's
+ * interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
+ * including it's interrupt vectoring table and the table at 0x0 is still the
+ * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
+ * is still used.
+ */
+_vt_reset:
+	.word	_reset
+_vt_undefined_instruction:
+	.word	_hang
+_vt_software_interrupt:
+	.word	_hang
+_vt_prefetch_abort:
+	.word	_hang
+_vt_data_abort:
+	.word	_hang
+_vt_not_used:
+	.word	_reset
+_vt_irq:
+	.word	_hang
+_vt_fiq:
+	.word	_hang
+
+reset:
+	ldr	pc, _vt_reset
+undefined_instruction:
+	ldr	pc, _vt_undefined_instruction
+software_interrupt:
+	ldr	pc, _vt_software_interrupt
+prefetch_abort:
+	ldr	pc, _vt_prefetch_abort
+data_abort:
+	ldr	pc, _vt_data_abort
+not_used:
+	ldr	pc, _vt_not_used
+irq:
+	ldr	pc, _vt_irq
+fiq:
+	ldr	pc, _vt_fiq
+
+	.balignl 16,0xdeadbeef
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+_reset:
+	/*
+	 * If the CPU is configured in "Wait JTAG connection mode", the stack
+	 * pointer is not configured and is zero. This will cause crash when
+	 * trying to push data onto stack right below here. Load the SP and make
+	 * it point to the end of OCRAM if the SP is zero.
+	 */
+	cmp	sp, #0x00000000
+	ldreq	sp, =CONFIG_SYS_INIT_SP_ADDR
+
+	/*
+	 * Store all registers on old stack pointer, this will allow us later to
+	 * return to the BootROM and let the BootROM load U-Boot into RAM.
+	 *
+	 * WARNING: Register r0 and r1 are used by the BootROM to pass data
+	 *          to the called code. Register r0 will contain arbitrary
+	 *          data that are set in the BootStream. In case this code
+	 *          was started with CALL instruction, register r1 will contain
+	 *          pointer to the return value this function can then set.
+	 *          The code below MUST NOT CHANGE register r0 and r1 !
+	 */
+	push	{r0-r12,r14}
+
+	/* Save control register c1 */
+	mrc	p15, 0, r2, c1, c0, 0
+	push	{r2}
+
+	/* Set the cpu to SVC32 mode and store old CPSR register content. */
+	mrs	r2, cpsr
+	push	{r2}
+	bic	r2, r2, #0x1f
+	orr	r2, r2, #0xd3
+	msr	cpsr, r2
+
+	bl	board_init_ll
+
+	/* Restore BootROM's CPU mode (especially FIQ). */
+	pop	{r2}
+	msr	cpsr,r2
+
+	/*
+	 * Restore c1 register. Especially set exception vector location
+	 * back to BootROM space which is required by bootrom for USB boot.
+	 */
+	pop	{r2}
+	mcr	p15, 0, r2, c1, c0, 0
+
+	pop	{r0-r12,r14}
+
+	/*
+	 * In case this code was started by the CALL instruction, the register
+	 * r0 is examined by the BootROM after this code returns. The value in
+	 * r0 must be set to 0 to indicate successful return.
+	 */
+	mov r0, #0
+
+	bx	lr
+
+_hang:
+1:
+	bl	1b				/* hang and never return */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/timer.c
new file mode 100644
index 000000000..99d3fb873
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/timer.c
@@ -0,0 +1,159 @@
+/*
+ * Freescale i.MX28 timer driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+/* Maximum fixed count */
+#if defined(CONFIG_MX23)
+#define TIMER_LOAD_VAL 0xffff
+#elif defined(CONFIG_MX28)
+#define TIMER_LOAD_VAL 0xffffffff
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp (gd->arch.tbl)
+#define lastdec (gd->arch.lastinc)
+
+/*
+ * This driver uses 1kHz clock source.
+ */
+#define	MXS_INCREMENTER_HZ		1000
+
+static inline unsigned long tick_to_time(unsigned long tick)
+{
+	return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
+}
+
+static inline unsigned long time_to_tick(unsigned long time)
+{
+	return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
+}
+
+/* Calculate how many ticks happen in "us" microseconds */
+static inline unsigned long us_to_tick(unsigned long us)
+{
+	return (us * MXS_INCREMENTER_HZ) / 1000000;
+}
+
+int timer_init(void)
+{
+	struct mxs_timrot_regs *timrot_regs =
+		(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
+
+	/* Reset Timers and Rotary Encoder module */
+	mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
+
+	/* Set fixed_count to 0 */
+#if defined(CONFIG_MX23)
+	writel(0, &timrot_regs->hw_timrot_timcount0);
+#elif defined(CONFIG_MX28)
+	writel(0, &timrot_regs->hw_timrot_fixed_count0);
+#endif
+
+	/* Set UPDATE bit and 1Khz frequency */
+	writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
+		TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
+		&timrot_regs->hw_timrot_timctrl0);
+
+	/* Set fixed_count to maximal value */
+#if defined(CONFIG_MX23)
+	writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
+#elif defined(CONFIG_MX28)
+	writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
+#endif
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	struct mxs_timrot_regs *timrot_regs =
+		(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
+	uint32_t now;
+
+	/* Current tick value */
+#if defined(CONFIG_MX23)
+	/* Upper bits are the valid ones. */
+	now = readl(&timrot_regs->hw_timrot_timcount0) >>
+		TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
+#elif defined(CONFIG_MX28)
+	now = readl(&timrot_regs->hw_timrot_running_count0);
+#endif
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp forward with absolut diff ticks
+		 */
+		timestamp += (lastdec - now);
+	} else {
+		/* we have rollover of decrementer */
+		timestamp += (TIMER_LOAD_VAL - now) + lastdec;
+
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
+#define	MXS_HW_DIGCTL_MICROSECONDS	0x8001c0c0
+
+void __udelay(unsigned long usec)
+{
+	uint32_t old, new, incr;
+	uint32_t counter = 0;
+
+	old = readl(MXS_HW_DIGCTL_MICROSECONDS);
+
+	while (counter < usec) {
+		new = readl(MXS_HW_DIGCTL_MICROSECONDS);
+
+		/* Check if the timer wrapped. */
+		if (new < old) {
+			incr = 0xffffffff - old;
+			incr += new;
+		} else {
+			incr = new - old;
+		}
+
+		/*
+		 * Check if we are close to the maximum time and the counter
+		 * would wrap if incremented. If that's the case, break out
+		 * from the loop as the requested delay time passed.
+		 */
+		if (counter + incr < counter)
+			break;
+
+		counter += incr;
+		old = new;
+	}
+}
+
+ulong get_tbclk(void)
+{
+	return MXS_INCREMENTER_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
new file mode 100644
index 000000000..3a51879d5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
@@ -0,0 +1,18 @@
+options {
+	driveTag = 0x00;
+	flags = 0x01;
+}
+
+sources {
+	u_boot_spl="spl/u-boot-spl.bin";
+	u_boot="u-boot.bin";
+}
+
+section (0) {
+	load u_boot_spl > 0x0000;
+	load ivt (entry = 0x0014) > 0x8000;
+	call 0x8000;
+
+	load u_boot > 0x40000100;
+	call 0x40000100;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
new file mode 100644
index 000000000..c60615a45
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
@@ -0,0 +1,14 @@
+sources {
+	u_boot_spl="spl/u-boot-spl.bin";
+	u_boot="u-boot.bin";
+}
+
+section (0) {
+	load u_boot_spl > 0x0000;
+	load ivt (entry = 0x0014) > 0x8000;
+	hab call 0x8000;
+
+	load u_boot > 0x40000100;
+	load ivt (entry = 0x40000100) > 0x8000;
+	hab call 0x8000;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
new file mode 100644
index 000000000..f4bf8ac1d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = CONFIG_SPL_TEXT_BASE;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/arm926ejs/mxs/start.o	(.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/Makefile
new file mode 100644
index 000000000..cdf1345d5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= timer.o gpio.o
+obj-y	+= reset.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/gpio.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/gpio.c
new file mode 100644
index 000000000..eff5b2b75
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/gpio.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+static unsigned long gpio_base[4] = {
+	NOMADIK_GPIO0_BASE,
+	NOMADIK_GPIO1_BASE,
+	NOMADIK_GPIO2_BASE,
+	NOMADIK_GPIO3_BASE
+};
+
+enum gpio_registers {
+	GPIO_DAT =	0x00,		/* data register */
+	GPIO_DATS =	0x04,		/* data set */
+	GPIO_DATC =	0x08,		/* data clear */
+	GPIO_PDIS =	0x0c,		/* pull disable */
+	GPIO_DIR =	0x10,		/* direction */
+	GPIO_DIRS =	0x14,		/* direction set */
+	GPIO_DIRC =	0x18,		/* direction clear */
+	GPIO_AFSLA =	0x20,		/* alternate function select A */
+	GPIO_AFSLB =	0x24,		/* alternate function select B */
+};
+
+static inline unsigned long gpio_to_base(int gpio)
+{
+	return gpio_base[gpio / 32];
+}
+
+static inline u32 gpio_to_bit(int gpio)
+{
+	return 1 << (gpio & 0x1f);
+}
+
+void nmk_gpio_af(int gpio, int alternate_function)
+{
+	unsigned long base = gpio_to_base(gpio);
+	u32 bit = gpio_to_bit(gpio);
+	u32 afunc, bfunc;
+
+	/* alternate function is 0..3, with one bit per register */
+	afunc = readl(base + GPIO_AFSLA) & ~bit;
+	bfunc = readl(base + GPIO_AFSLB) & ~bit;
+	if (alternate_function & 1) afunc |= bit;
+	if (alternate_function & 2) bfunc |= bit;
+	writel(afunc, base + GPIO_AFSLA);
+	writel(bfunc, base + GPIO_AFSLB);
+}
+
+void nmk_gpio_dir(int gpio, int dir)
+{
+	unsigned long base = gpio_to_base(gpio);
+	u32 bit = gpio_to_bit(gpio);
+
+	if (dir)
+		writel(bit, base + GPIO_DIRS);
+	else
+		writel(bit, base + GPIO_DIRC);
+}
+
+void nmk_gpio_set(int gpio, int val)
+{
+	unsigned long base = gpio_to_base(gpio);
+	u32 bit = gpio_to_bit(gpio);
+
+	if (val)
+		writel(bit, base + GPIO_DATS);
+	else
+		writel(bit, base + GPIO_DATC);
+}
+
+int nmk_gpio_get(int gpio)
+{
+	unsigned long base = gpio_to_base(gpio);
+	u32 bit = gpio_to_bit(gpio);
+
+	return readl(base + GPIO_DAT) & bit;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/reset.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/reset.S
new file mode 100644
index 000000000..ec954726a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/reset.S
@@ -0,0 +1,14 @@
+#include <config.h>
+/*
+ * Processor reset for Nomadik
+ */
+
+	.align 5
+.globl reset_cpu
+reset_cpu:
+	ldr	r0, =NOMADIK_SRC_BASE	/* System and Reset Controller */
+	ldr	r1, =0x1
+	str	r1, [r0, #0x18]
+
+_loop_forever:
+	b	_loop_forever
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/timer.c
new file mode 100644
index 000000000..775d0b748
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/nomadik/timer.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mtu.h>
+
+/*
+ * The timer is a decrementer, we'll left it free running at 2.4MHz.
+ * We have 2.4 ticks per microsecond and an overflow in almost 30min
+ */
+#define TIMER_CLOCK		(24 * 100 * 1000)
+#define COUNT_TO_USEC(x)	((x) * 5 / 12)	/* overflows at 6min */
+#define USEC_TO_COUNT(x)	((x) * 12 / 5)	/* overflows at 6min */
+#define TICKS_PER_HZ		(TIMER_CLOCK / CONFIG_SYS_HZ)
+#define TICKS_TO_HZ(x)		((x) / TICKS_PER_HZ)
+
+/* macro to read the decrementing 32 bit timer as an increasing count */
+#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
+
+/* Configure a free-running, auto-wrap counter with no prescaler */
+int timer_init(void)
+{
+	ulong val;
+
+	writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
+	       CONFIG_SYS_TIMERBASE + MTU_CR(0));
+
+	/* Reset the timer */
+	writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
+	/*
+	 * The load-register isn't really immediate: it changes on clock
+	 * edges, so we must wait for our newly-written value to appear.
+	 * Since we might miss reading 0, wait for any change in value.
+	 */
+	val = READ_TIMER();
+	while (READ_TIMER() == val)
+		;
+
+	return 0;
+}
+
+/* Return how many HZ passed since "base" */
+ulong get_timer(ulong base)
+{
+	return  TICKS_TO_HZ(READ_TIMER()) - base;
+}
+
+/* Delay x useconds */
+void __udelay(unsigned long usec)
+{
+	ulong ini, end;
+
+	ini = READ_TIMER();
+	end = ini + USEC_TO_COUNT(usec);
+	while ((signed)(end - READ_TIMER()) > 0)
+		;
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/Makefile
new file mode 100644
index 000000000..add923276
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= timer.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o
+obj-y	+= reset.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/cpuinfo.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
new file mode 100644
index 000000000..587d99a2b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/cpuinfo.c
@@ -0,0 +1,242 @@
+/*
+ * OMAP1 CPU identification code
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/compiler.h>
+
+#if defined(CONFIG_OMAP)
+
+#define omap_readw(x)		*(volatile unsigned short *)(x)
+#define omap_readl(x)		*(volatile unsigned long *)(x)
+
+#define OMAP_DIE_ID_0		0xfffe1800
+#define OMAP_DIE_ID_1		0xfffe1804
+#define OMAP_PRODUCTION_ID_0	0xfffe2000
+#define OMAP_PRODUCTION_ID_1	0xfffe2004
+#define OMAP32_ID_0		0xfffed400
+#define OMAP32_ID_1		0xfffed404
+
+struct omap_id {
+	u16	jtag_id;	/* Used to determine OMAP type */
+	u8	die_rev;	/* Processor revision */
+	u32	omap_id;	/* OMAP revision */
+	u32	type;		/* Cpu id bits [31:08], cpu class bits [07:00] */
+};
+
+/* Register values to detect the OMAP version */
+static struct omap_id omap_ids[] = {
+	{ .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
+	{ .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
+	{ .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
+	{ .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
+	{ .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000},
+	{ .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000},
+	{ .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00},
+	{ .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00},
+	{ .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
+	{ .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00},
+	{ .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000},
+	{ .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00},
+	{ .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00},
+	{ .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300},
+	{ .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300},
+	{ .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300},
+	{ .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000},
+	{ .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000},
+	{ .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000},
+};
+
+/*
+ * Get OMAP type from PROD_ID.
+ * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM.
+ * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense.
+ * Undocumented register in TEST BLOCK is used as fallback; This seems to
+ * work on 1510, 1610 & 1710. The official way hopefully will work in future
+ * processors.
+ */
+static u16 omap_get_jtag_id(void)
+{
+	u32 prod_id, omap_id;
+
+	prod_id = omap_readl(OMAP_PRODUCTION_ID_1);
+	omap_id = omap_readl(OMAP32_ID_1);
+
+	/* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */
+	if (((prod_id >> 20) == 0) || (prod_id == omap_id))
+		prod_id = 0;
+	else
+		prod_id &= 0xffff;
+
+	if (prod_id)
+		return prod_id;
+
+	/* Use OMAP32_ID_1 as fallback */
+	prod_id = ((omap_id >> 12) & 0xffff);
+
+	return prod_id;
+}
+
+/*
+ * Get OMAP revision from DIE_REV.
+ * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID.
+ * Undocumented register in the TEST BLOCK is used as fallback.
+ * REVISIT: This does not seem to work on 1510
+ */
+static u8 omap_get_die_rev(void)
+{
+	u32 die_rev;
+
+	die_rev = omap_readl(OMAP_DIE_ID_1);
+
+	/* Check for broken OMAP_DIE_ID on early 1710 */
+	if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id())
+		die_rev = 0;
+
+	die_rev = (die_rev >> 17) & 0xf;
+	if (die_rev)
+		return die_rev;
+
+	die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf;
+
+	return die_rev;
+}
+
+static unsigned long dpll1(void)
+{
+	unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG);
+	unsigned long rate;
+
+	rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */
+	if (pll_ctl_val & 0x10) {
+		/* PLL enabled, apply multiplier and divisor */
+		if (pll_ctl_val & 0xf80)
+			rate *= (pll_ctl_val & 0xf80) >> 7;
+		rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
+	} else {
+		/* PLL disabled, apply bypass divisor */
+		switch (pll_ctl_val & 0xc) {
+		case 0:
+			break;
+		case 0x4:
+			rate /= 2;
+			break;
+		default:
+			rate /= 4;
+			break;
+		}
+	}
+
+	return rate;
+}
+
+static unsigned long armcore(void)
+{
+	unsigned short arm_ckctl = omap_readw(ARM_CKCTL);
+
+	return (dpll1() >> ((arm_ckctl & 0x0030) >> 4));
+}
+
+int print_cpuinfo (void)
+{
+	int i;
+	u16 jtag_id;
+	u8 die_rev;
+	u32 omap_id;
+	u8 cpu_type;
+	__maybe_unused u32 system_serial_high;
+	__maybe_unused u32 system_serial_low;
+	u32 system_rev = 0;
+
+	jtag_id = omap_get_jtag_id();
+	die_rev = omap_get_die_rev();
+	omap_id = omap_readl(OMAP32_ID_0);
+
+#ifdef DEBUG
+	printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0));
+	printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n",
+	       omap_readl(OMAP_DIE_ID_1),
+	       (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf);
+	printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0));
+	printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n",
+	       omap_readl(OMAP_PRODUCTION_ID_1),
+	       omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff);
+	printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0));
+	printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1));
+	printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev);
+#endif
+
+	system_serial_high = omap_readl(OMAP_DIE_ID_0);
+	system_serial_low = omap_readl(OMAP_DIE_ID_1);
+
+	/* First check only the major version in a safe way */
+	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
+		if (jtag_id == (omap_ids[i].jtag_id)) {
+			system_rev = omap_ids[i].type;
+			break;
+		}
+	}
+
+	/* Check if we can find the die revision */
+	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
+		if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) {
+			system_rev = omap_ids[i].type;
+			break;
+		}
+	}
+
+	/* Finally check also the omap_id */
+	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
+		if (jtag_id == omap_ids[i].jtag_id
+		    && die_rev == omap_ids[i].die_rev
+		    && omap_id == omap_ids[i].omap_id) {
+			system_rev = omap_ids[i].type;
+			break;
+		}
+	}
+
+	/* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */
+	cpu_type = system_rev >> 24;
+
+	switch (cpu_type) {
+	case 0x07:
+		system_rev |= 0x07;
+		break;
+	case 0x03:
+	case 0x15:
+		system_rev |= 0x15;
+		break;
+	case 0x16:
+	case 0x17:
+		system_rev |= 0x16;
+		break;
+	case 0x24:
+		system_rev |= 0x24;
+		break;
+	default:
+		printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
+	}
+
+	printf("CPU:   OMAP%04x", system_rev >> 16);
+	if ((system_rev >> 8) & 0xff)
+		printf("%x", (system_rev >> 8) & 0xff);
+#ifdef DEBUG
+	printf(" revision %i handled as %02xxx id: %08x%08x",
+	       die_rev, system_rev & 0xff, system_serial_low, system_serial_high);
+#endif
+	printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n",
+	       armcore() / 1000000, (armcore() / 100000) % 10,
+	       dpll1() / 1000000, (dpll1() / 100000) % 10);
+
+	return 0;
+}
+
+#endif /* #if defined(CONFIG_OMAP) */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/reset.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/reset.S
new file mode 100644
index 000000000..1c557b0d9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/reset.S
@@ -0,0 +1,29 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, rstctl1	/* get clkm1 reset ctl */
+	mov	r3, #0x0
+	strh	r3, [r1]	/* clear it */
+	mov	r3, #0x8
+	strh	r3, [r1]	/* force dsp+arm reset */
+_loop_forever:
+	b	_loop_forever
+
+rstctl1:
+	.word	0xfffece10
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/timer.c
new file mode 100644
index 000000000..b9715656c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/omap/timer.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
+#define TIMER_LOAD_VAL	0xffffffff
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER	readl(CONFIG_SYS_TIMERBASE+8) \
+			/ (TIMER_CLOCK / CONFIG_SYS_HZ)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+int timer_init (void)
+{
+	int32_t val;
+
+	/* Start the decrementer ticking down from 0xffffffff */
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
+	val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay (unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	if(usec >= 1000){		/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;		/* finish normalize. */
+	}else{				/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	tmp = get_timer (0);		/* get current timestamp */
+	if( (tmo + tmp + 1) < tmp )	/* if setting this fordward will roll time stamp */
+		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastdec value */
+	else
+		tmo += tmp;		/* else, set advancing stamp wake up time */
+
+	while (get_timer_masked () < tmo)/* loop till event */
+		/*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;  /* capure current decrementer value time */
+	timestamp = 0;	       /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;		/* current tick value */
+
+	if (lastdec >= now) {		/* normal mode (non roll) */
+		/* normal mode */
+		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
+	} else {			/* we have overflow of the count down timer */
+		/* nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and cause problems.
+		 */
+		timestamp += lastdec + (TIMER_LOAD_VAL / (TIMER_CLOCK /
+					CONFIG_SYS_HZ)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;		/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;		/* finish normalize. */
+	} else {			/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/Makefile
new file mode 100644
index 000000000..546ebcb52
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/Makefile
@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= cpu.o
+obj-y	+= dram.o
+obj-y	+= timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+obj-y	+= lowlevel_init.o
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/cpu.c
new file mode 100644
index 000000000..b55c5f094
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -0,0 +1,295 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <u-boot/md5.h>
+#include <asm/arch/cpu.h>
+#include <hush.h>
+
+#define BUFLEN	16
+
+void reset_cpu(unsigned long ignored)
+{
+	struct orion5x_cpu_registers *cpureg =
+	    (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
+
+	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+		&cpureg->rstoutn_mask);
+	writel(readl(&cpureg->sys_soft_rst) | 1,
+		&cpureg->sys_soft_rst);
+	while (1)
+		;
+}
+
+/*
+ * Compute Window Size field value from size expressed in bytes
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
+ * NOTES:
+ * 1) A sizeval equal to 0x0 specifies 4 GiB.
+ * 2) A return value of 0x0 specifies 64 KiB.
+ */
+unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
+{
+	/*
+	 * Calculate the number of 64 KiB blocks needed minus one (rounding up).
+	 * For sizeval > 0 this is equivalent to:
+	 * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
+	 */
+	sizeval = (sizeval - 1) >> 16;
+
+	/*
+	 * Propagate 'one' bits to the right by 'oring' them.
+	 * We need only treat bits 15-0.
+	 */
+	sizeval |= sizeval >> 1;  /* 'Or' bit 15 onto bit 14 */
+	sizeval |= sizeval >> 2;  /* 'Or' bits 15-14 onto bits 13-12 */
+	sizeval |= sizeval >> 4;  /* 'Or' bits 15-12 onto bits 11-8 */
+	sizeval |= sizeval >> 8;  /* 'Or' bits 15-8 onto bits 7-0*/
+
+	return sizeval;
+}
+
+/*
+ * orion5x_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Orion5x Soc to addess different
+ * devices. Each window can be configured for size, BAR and remap addr
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ *
+ * NOTES:
+ *
+ * 1) in order to avoid windows with inconsistent control and base values
+ *    (which could prevent access to BOOTCS and hence execution from FLASH)
+ *    always disable window before writing the base value then reenable it
+ *    by writing the control value.
+ *
+ * 2) in order to avoid losing access to BOOTCS when disabling window 7,
+ *    first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
+ *    then configure windows 6 for its own target.
+ *
+ * Reference Documentation:
+ * Mbus-L to Mbus Bridge Registers Configuration.
+ * (Sec 25.1 and 25.3 of Datasheet)
+ */
+int orion5x_config_adr_windows(void)
+{
+	struct orion5x_win_registers *winregs =
+		(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
+
+/* Disable window 0, configure it for its intended target, enable it. */
+	writel(0, &winregs[0].ctrl);
+	writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
+	writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
+	writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
+		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
+		ORION5X_WIN_ENABLE), &winregs[0].ctrl);
+/* Disable window 1, configure it for its intended target, enable it. */
+	writel(0, &winregs[1].ctrl);
+	writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
+	writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
+	writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
+		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
+		ORION5X_WIN_ENABLE), &winregs[1].ctrl);
+/* Disable window 2, configure it for its intended target, enable it. */
+	writel(0, &winregs[2].ctrl);
+	writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
+		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
+		ORION5X_WIN_ENABLE), &winregs[2].ctrl);
+/* Disable window 3, configure it for its intended target, enable it. */
+	writel(0, &winregs[3].ctrl);
+	writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
+		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
+		ORION5X_WIN_ENABLE), &winregs[3].ctrl);
+/* Disable window 4, configure it for its intended target, enable it. */
+	writel(0, &winregs[4].ctrl);
+	writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
+		ORION5X_WIN_ENABLE), &winregs[4].ctrl);
+/* Disable window 5, configure it for its intended target, enable it. */
+	writel(0, &winregs[5].ctrl);
+	writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
+		ORION5X_WIN_ENABLE), &winregs[5].ctrl);
+/* Disable window 6, configure it for FLASH, enable it. */
+	writel(0, &winregs[6].ctrl);
+	writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
+		ORION5X_WIN_ENABLE), &winregs[6].ctrl);
+/* Disable window 7, configure it for FLASH, enable it. */
+	writel(0, &winregs[7].ctrl);
+	writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
+		ORION5X_WIN_ENABLE), &winregs[7].ctrl);
+/* Disable window 6, configure it for its intended target, enable it. */
+	writel(0, &winregs[6].ctrl);
+	writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+		ORION5X_WIN_ENABLE), &winregs[6].ctrl);
+
+	return 0;
+}
+
+/*
+ * Orion5x identification is done through PCIE space.
+ */
+
+u32 orion5x_device_id(void)
+{
+	return readl(PCIE_DEV_ID_OFF) >> 16;
+}
+
+u32 orion5x_device_rev(void)
+{
+	return readl(PCIE_DEV_REV_OFF) & 0xff;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+
+/* Display device and revision IDs.
+ * This function must cover all known device/revision
+ * combinations, not only the one for which u-boot is
+ * compiled; this way, one can identify actual HW in
+ * case of a mismatch.
+ */
+int print_cpuinfo(void)
+{
+	char dev_str[7]; /* room enough for 0x0000 plus null byte */
+	char rev_str[5]; /* room enough for 0x00 plus null byte */
+	char *dev_name = NULL;
+	char *rev_name = NULL;
+
+	u32 dev = orion5x_device_id();
+	u32 rev = orion5x_device_rev();
+
+	if (dev == MV88F5181_DEV_ID) {
+		dev_name = "MV88F5181";
+		if (rev == MV88F5181_REV_B1)
+			rev_name = "B1";
+		else if (rev == MV88F5181L_REV_A1) {
+			dev_name = "MV88F5181L";
+			rev_name = "A1";
+		} else if (rev == MV88F5181L_REV_A0) {
+			dev_name = "MV88F5181L";
+			rev_name = "A0";
+		}
+	} else if (dev == MV88F5182_DEV_ID) {
+		dev_name = "MV88F5182";
+		if (rev == MV88F5182_REV_A2)
+			rev_name = "A2";
+	} else if (dev == MV88F5281_DEV_ID) {
+		dev_name = "MV88F5281";
+		if (rev == MV88F5281_REV_D2)
+			rev_name = "D2";
+		else if (rev == MV88F5281_REV_D1)
+			rev_name = "D1";
+		else if (rev == MV88F5281_REV_D0)
+			rev_name = "D0";
+	} else if (dev == MV88F6183_DEV_ID) {
+		dev_name = "MV88F6183";
+		if (rev == MV88F6183_REV_B0)
+			rev_name = "B0";
+	}
+	if (dev_name == NULL) {
+		sprintf(dev_str, "0x%04x", dev);
+		dev_name = dev_str;
+	}
+	if (rev_name == NULL) {
+		sprintf(rev_str, "0x%02x", rev);
+		rev_name = rev_str;
+	}
+
+	printf("SoC:   Orion5x %s-%s\n", dev_name, rev_name);
+
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	/* Enable and invalidate L2 cache in write through mode */
+	invalidate_l2_cache();
+
+	orion5x_config_adr_windows();
+
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+	u32 temp;
+
+	/*CPU streaming & write allocate */
+	temp = readfr_extra_feature_reg();
+	temp &= ~(1 << 28);	/* disable wr alloc */
+	writefr_extra_feature_reg(temp);
+
+	temp = readfr_extra_feature_reg();
+	temp &= ~(1 << 29);	/* streaming disabled */
+	writefr_extra_feature_reg(temp);
+
+	/* L2Cache settings */
+	temp = readfr_extra_feature_reg();
+	/* Disable L2C pre fetch - Set bit 24 */
+	temp |= (1 << 24);
+	/* enable L2C - Set bit 22 */
+	temp |= (1 << 22);
+	writefr_extra_feature_reg(temp);
+
+	icache_enable();
+	/* Change reset vector to address 0x0 */
+	temp = get_cr();
+	set_cr(temp & ~CR_V);
+
+	/* Set CPIOs and MPPs - values provided by board
+	   include file */
+	writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
+	writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
+	writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
+	writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
+	writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
+	writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
+
+	/* initialize timer */
+	timer_init_r();
+	return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_MVGBE
+int cpu_eth_init(bd_t *bis)
+{
+	mvgbe_initialize(bis);
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/dram.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/dram.c
new file mode 100644
index 000000000..9ed93d25b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/dram.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * orion5x_sdram_bar - reads SDRAM Base Address Register
+ */
+u32 orion5x_sdram_bar(enum memory_bank bank)
+{
+	struct orion5x_ddr_addr_decode_registers *winregs =
+		(struct orion5x_ddr_addr_decode_registers *)
+		ORION5X_DRAM_BASE;
+
+	u32 result = 0;
+	u32 enable = 0x01 & winregs[bank].size;
+
+	if ((!enable) || (bank > BANK3))
+		return 0;
+
+	result = winregs[bank].base;
+	return result;
+}
+int dram_init (void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size(
+			(long *) orion5x_sdram_bar(0),
+			CONFIG_MAX_RAM_BANK_SIZE);
+	return 0;
+}
+
+void dram_init_banksize (void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
+		gd->bd->bi_dram[i].size = get_ram_size(
+			(long *) (gd->bd->bi_dram[i].start),
+			CONFIG_MAX_RAM_BANK_SIZE);
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
new file mode 100644
index 000000000..4dacc296e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
@@ -0,0 +1,277 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include "asm/arch/orion5x.h"
+
+/*
+ * Configuration values for SDRAM access setup
+ */
+
+#define SDRAM_CONFIG			0x3148400
+#define SDRAM_MODE			0x62
+#define SDRAM_CONTROL			0x4041000
+#define SDRAM_TIME_CTRL_LOW		0x11602220
+#define SDRAM_TIME_CTRL_HI		0x40c
+#define SDRAM_OPEN_PAGE_EN		0x0
+/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
+#define SDRAM_BANK0_SIZE		0x3ff0001
+#define SDRAM_ADDR_CTRL			0x10
+
+#define SDRAM_OP_NOP			0x05
+#define SDRAM_OP_SETMODE		0x03
+
+#define SDRAM_PAD_CTRL_WR_EN		0x80000000
+#define SDRAM_PAD_CTRL_TUNE_EN		0x00010000
+#define SDRAM_PAD_CTRL_DRVN_MASK	0x0000003f
+#define SDRAM_PAD_CTRL_DRVP_MASK	0x00000fc0
+
+/*
+ * For Guideline MEM-3 - Drive Strength value
+ */
+
+#define DDR1_PAD_STRENGTH_DEFAULT	0x00001000
+#define SDRAM_PAD_CTRL_DRV_STR_MASK	0x00003000
+
+/*
+ * For Guideline MEM-4 - DQS Reference Delay Tuning
+ */
+
+#define MSAR_ARMDDRCLCK_MASK		0x000000f0
+#define MSAR_ARMDDRCLCK_H_MASK		0x00000100
+
+#define MSAR_ARMDDRCLCK_333_167		0x00000000
+#define MSAR_ARMDDRCLCK_500_167		0x00000030
+#define MSAR_ARMDDRCLCK_667_167		0x00000060
+#define MSAR_ARMDDRCLCK_400_200_1	0x000001E0
+#define MSAR_ARMDDRCLCK_400_200		0x00000010
+#define MSAR_ARMDDRCLCK_600_200		0x00000050
+#define MSAR_ARMDDRCLCK_800_200		0x00000070
+
+#define FTDLL_DDR1_166MHZ		0x0047F001
+
+#define FTDLL_DDR1_200MHZ		0x0044D001
+
+/*
+ * Low-level init happens right after start.S has switched to SVC32,
+ * flushed and disabled caches and disabled MMU. We're still running
+ * from the boot chip select, so the first thing we should do is set
+ * up RAM for us to relocate into.
+ */
+
+.globl lowlevel_init
+
+lowlevel_init:
+
+	/* Use 'r4 as the base for internal register accesses */
+	ldr	r4, =ORION5X_REGS_PHY_BASE
+
+	/* move internal registers from the default 0xD0000000
+	 * to their intended location, defined by SoC */
+	ldr	r3, =0xD0000000
+	add	r3, r3, #0x20000
+	str	r4, [r3, #0x80]
+
+	/* Use R3 as the base for DRAM registers */
+	add	r3, r4, #0x01000
+
+	/*DDR SDRAM Initialization Control */
+	ldr	r6, =0x00000001
+	str	r6, [r3, #0x480]
+
+	/* Use R3 as the base for PCI registers */
+	add	r3, r4, #0x31000
+
+	/* Disable arbiter */
+	ldr	r6, =0x00000030
+	str	r6, [r3, #0xd00]
+
+	/* Use R3 as the base for DRAM registers */
+	add	r3, r4, #0x01000
+
+	/* set all dram windows to 0 */
+	mov	r6, #0
+	str	r6, [r3, #0x504]
+	str	r6, [r3, #0x50C]
+	str	r6, [r3, #0x514]
+	str	r6, [r3, #0x51C]
+
+	/* 1) Configure SDRAM  */
+	ldr	r6, =SDRAM_CONFIG
+	str	r6, [r3, #0x400]
+
+	/* 2) Set SDRAM Control reg */
+	ldr	r6, =SDRAM_CONTROL
+	str	r6, [r3, #0x404]
+
+	/* 3) Write SDRAM address control register */
+	ldr	r6, =SDRAM_ADDR_CTRL
+	str	r6, [r3, #0x410]
+
+	/* 4) Write SDRAM bank 0 size register */
+	ldr	r6, =SDRAM_BANK0_SIZE
+	str	r6, [r3, #0x504]
+	/* keep other banks disabled */
+
+	/* 5) Write SDRAM open pages control register */
+	ldr	r6, =SDRAM_OPEN_PAGE_EN
+	str	r6, [r3, #0x414]
+
+	/* 6) Write SDRAM timing Low register */
+	ldr	r6, =SDRAM_TIME_CTRL_LOW
+	str	r6, [r3, #0x408]
+
+	/* 7) Write SDRAM timing High register */
+	ldr	r6, =SDRAM_TIME_CTRL_HI
+	str	r6, [r3, #0x40C]
+
+	/* 8) Write SDRAM mode register */
+	/* The CPU must not attempt to change the SDRAM Mode register setting */
+	/* prior to DRAM controller completion of the DRAM initialization     */
+	/* sequence. To guarantee this restriction, it is recommended that    */
+	/* the CPU sets the SDRAM Operation register to NOP command, performs */
+	/* read polling until the register is back in Normal operation value, */
+	/* and then sets SDRAM Mode register to its new value.		      */
+
+	/* 8.1 write 'nop' to SDRAM operation */
+	ldr	r6, =SDRAM_OP_NOP
+	str	r6, [r3, #0x418]
+
+	/* 8.2 poll SDRAM operation until back in 'normal' mode.  */
+1:
+	ldr	r6, [r3, #0x418]
+	cmp	r6, #0
+	bne	1b
+
+	/* 8.3 Now its safe to write new value to SDRAM Mode register	      */
+	ldr	r6, =SDRAM_MODE
+	str	r6, [r3, #0x41C]
+
+	/* 8.4 Set new mode */
+	ldr	r6, =SDRAM_OP_SETMODE
+	str	r6, [r3, #0x418]
+
+	/* 8.5 poll SDRAM operation until back in 'normal' mode.  */
+2:
+	ldr	r6, [r3, #0x418]
+	cmp	r6, #0
+	bne	2b
+
+	/* DDR SDRAM Address/Control Pads Calibration */
+	ldr	r6, [r3, #0x4C0]
+
+	/* Set Bit [31] to make the register writable			*/
+	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	str	r6, [r3, #0x4C0]
+
+	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+	/* Get the final N locked value of driving strength [22:17]	*/
+	mov	r1, r6
+	mov	r1, r1, LSL #9
+	mov	r1, r1, LSR #26	 /* r1[5:0]<DrvN>  = r3[22:17]<LockN>	*/
+	orr	r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN>	*/
+
+	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
+	orr	r6, r6, r1
+	str	r6, [r3, #0x4C0]
+
+	/* DDR SDRAM Data Pads Calibration				*/
+	ldr	r6, [r3, #0x4C4]
+
+	/* Set Bit [31] to make the register writable			*/
+	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	str	r6, [r3, #0x4C4]
+
+	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+	/* Get the final N locked value of driving strength [22:17]	*/
+	mov	r1, r6
+	mov	r1, r1, LSL #9
+	mov	r1, r1, LSR #26
+	orr	r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>	*/
+
+	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
+	orr	r6, r6, r1
+
+	str	r6, [r3, #0x4C4]
+
+	/* Implement Guideline (GL# MEM-3) Drive Strength Value		*/
+	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/
+
+	ldr	r1, =DDR1_PAD_STRENGTH_DEFAULT
+
+	/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
+	ldr	r6, [r3, #0x4C0]
+	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	str	r6, [r3, #0x4C0]
+
+	/* Correct strength and disable writes again */
+	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+	orr	r6, r6, r1
+	str	r6, [r3, #0x4C0]
+
+	/* Enable writes to DDR SDRAM Data Pads Calibration register */
+	ldr	r6, [r3, #0x4C4]
+	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	str	r6, [r3, #0x4C4]
+
+	/* Correct strength and disable writes again */
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	orr	r6, r6, r1
+	str	r6, [r3, #0x4C4]
+
+	/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning	*/
+	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/
+
+	/* Get the "sample on reset" register for the DDR frequancy	*/
+	ldr	r3, =0x10000
+	ldr	r6, [r3, #0x010]
+	ldr	r1, =MSAR_ARMDDRCLCK_MASK
+	and	r1, r6, r1
+
+	ldr	r6, =FTDLL_DDR1_166MHZ
+	cmp	r1, #MSAR_ARMDDRCLCK_333_167
+	beq	3f
+	cmp	r1, #MSAR_ARMDDRCLCK_500_167
+	beq	3f
+	cmp	r1, #MSAR_ARMDDRCLCK_667_167
+	beq	3f
+
+	ldr	r6, =FTDLL_DDR1_200MHZ
+	cmp	r1, #MSAR_ARMDDRCLCK_400_200_1
+	beq	3f
+	cmp	r1, #MSAR_ARMDDRCLCK_400_200
+	beq	3f
+	cmp	r1, #MSAR_ARMDDRCLCK_600_200
+	beq	3f
+	cmp	r1, #MSAR_ARMDDRCLCK_800_200
+	beq	3f
+
+	ldr	r6, =0
+
+3:
+	/* Use R3 as the base for DRAM registers */
+	add	r3, r4, #0x01000
+
+	ldr	r2, [r3, #0x484]
+	orr	r2, r2, r6
+	str	r2, [r3, #0x484]
+
+	/* Return to U-boot via saved link register */
+	mov	pc, lr
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/timer.c
new file mode 100644
index 000000000..ec4f6bee8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/orion5x/timer.c
@@ -0,0 +1,171 @@
+/*
+  * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on original Kirkwood support which is
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define UBOOT_CNTR	0	/* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct orion5x_tmr_val {
+	u32 reload;	/* Timer reload reg */
+	u32 val;	/* Timer value reg */
+};
+
+/* Timer registers */
+struct orion5x_tmr_registers {
+	u32 ctrl;	/* Timer control reg */
+	u32 pad[3];
+	struct orion5x_tmr_val tmr[2];
+	u32 wdt_reload;
+	u32 wdt_val;
+};
+
+struct orion5x_tmr_registers *orion5x_tmr_regs =
+	(struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG			(&orion5x_tmr_regs->ctrl)
+#define CNTMR_RELOAD_REG(tmrnum)	(&orion5x_tmr_regs->tmr[tmrnum].reload)
+#define CNTMR_VAL_REG(tmrnum)		(&orion5x_tmr_regs->tmr[tmrnum].val)
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS		0
+#define TRG_ARM_TIMER_REL_MASK		0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS		0
+#define TVR_ARM_TIMER_MASK		0xffffffff
+#define TVR_ARM_TIMER_MAX		0xffffffff
+#define TIMER_LOAD_VAL 			0xffffffff
+
+static inline ulong read_timer(void)
+{
+	return readl(CNTMR_VAL_REG(UBOOT_CNTR))
+	      / (CONFIG_SYS_TCLK / 1000);
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec +
+			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+static inline ulong uboot_cntr_val(void)
+{
+	return readl(CNTMR_VAL_REG(UBOOT_CNTR));
+}
+
+void __udelay(unsigned long usec)
+{
+	uint current;
+	ulong delayticks;
+
+	current = uboot_cntr_val();
+	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+	if (current < delayticks) {
+		delayticks -= current;
+		while (uboot_cntr_val() < current)
+			;
+		while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
+			;
+	} else {
+		while (uboot_cntr_val() > (current - delayticks))
+			;
+	}
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+	unsigned int cntmrctrl;
+
+	/* load value into timer */
+	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+	/* enable timer in auto reload mode */
+	cntmrctrl = readl(CNTMR_CTRL_REG);
+	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+	writel(cntmrctrl, CNTMR_CTRL_REG);
+	return 0;
+}
+
+void timer_init_r(void)
+{
+	/* init the timestamp and lastdec value */
+	lastdec = read_timer();
+	timestamp = 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/Makefile
new file mode 100644
index 000000000..988341f8f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Lei Wen <leiwen@marvell.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= cpu.o timer.o dram.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/cpu.c
new file mode 100644
index 000000000..4e2a177c0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/pantheon.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID	(1<<8)
+#define L2C_RAM_SEL	(1<<4)
+
+int arch_cpu_init(void)
+{
+	u32 val;
+	struct panthcpu_registers *cpuregs =
+		(struct panthcpu_registers*) PANTHEON_CPU_BASE;
+
+	struct panthapb_registers *apbclkres =
+		(struct panthapb_registers*) PANTHEON_APBC_BASE;
+
+	struct panthmpmu_registers *mpmu =
+		(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
+
+	struct panthapmu_registers *apmu =
+		(struct panthapmu_registers *) PANTHEON_APMU_BASE;
+
+	/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
+	val = readl(&cpuregs->cpu_conf);
+	val = val | SET_MRVL_ID;
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Turn on clock gating (PMUM_CCGR) */
+	writel(0xFFFFFFFF, &mpmu->ccgr);
+
+	/* Turn on clock gating (PMUM_ACGR) */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on uart2 clock */
+	writel(UARTCLK14745KHZ, &apbclkres->uart0);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK, &apbclkres->gpio);
+
+#ifdef CONFIG_I2C_MV
+	/* Enable I2C clock */
+	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
+	writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
+#endif
+
+#ifdef CONFIG_MV_SDHCI
+	/* Enable mmc clock */
+	writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+			&apmu->sd1);
+	writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+			&apmu->sd3);
+#endif
+
+	icache_enable();
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 id;
+	struct panthcpu_registers *cpuregs =
+		(struct panthcpu_registers*) PANTHEON_CPU_BASE;
+
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/dram.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/dram.c
new file mode 100644
index 000000000..f77e3d0ab
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/dram.c
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>,
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pantheon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Pantheon DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet 4.4
+ */
+struct panthddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+	u32	pad[3];
+};
+
+struct panthddr_registers {
+	u8	pad[0x100 - 0x000];
+	struct panthddr_map_registers mmap[2];
+};
+
+/*
+ * panth_sdram_base - reads SDRAM Base Address Register
+ */
+u32 panth_sdram_base(int chip_sel)
+{
+	struct panthddr_registers *ddr_regs =
+		(struct panthddr_registers *)PANTHEON_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * panth_sdram_size - reads SDRAM size
+ */
+u32 panth_sdram_size(int chip_sel)
+{
+	struct panthddr_registers *ddr_regs =
+		(struct panthddr_registers *)PANTHEON_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return ((0x8 << (result - 0x7)) * 1024 * 1024);
+	}
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = panth_sdram_base(i);
+		gd->bd->bi_dram[i].size = panth_sdram_size(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/*
+		 * If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash
+		 */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/timer.c
new file mode 100644
index 000000000..6382d3b0c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/pantheon/timer.c
@@ -0,0 +1,201 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/pantheon.h>
+
+/*
+ * Timer registers
+ * Refer 6.2.9 in Datasheet
+ */
+struct panthtmr_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr[3];
+};
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
+
+/*
+ * For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct panthtmr_registers *panthtimers =
+		(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
+	volatile int loop=100;
+	ulong val;
+
+	writel(COUNT_RD_REQ, &panthtimers->cvwr);
+	while (loop--)
+		val = readl(&panthtimers->cvwr);
+
+	/*
+	 * This stop gcc complain and prevent loop mistake init to 0
+	 */
+	val = readl(&panthtimers->cvwr);
+
+	return val;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->arch.tbl) {
+		/* normal mode */
+		gd->arch.tbu += now - gd->arch.tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
+	}
+	gd->arch.tbl = now;
+
+	return gd->arch.tbu;
+}
+
+ulong get_timer(ulong base)
+{
+	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+		base);
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime)
+		;
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct panthapb_registers *apb1clkres =
+		(struct panthapb_registers *) PANTHEON_APBC_BASE;
+	struct panthtmr_registers *panthtimers =
+		(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
+
+	/* Enable Timer clock at 3.25 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &panthtimers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &panthtimers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x1, &panthtimers->preload_ctrl[TIMER]);
+
+	/* Enable timer 0 */
+	writel(0x1, &panthtimers->cer);
+	/* init the gd->arch.tbu and gd->arch.tbl value */
+	gd->arch.tbl = read_timer();
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+#define MPMU_APRR_WDTR	(1<<4)
+#define TMR_WFAR	0xbaba	/* WDT Register First key */
+#define TMP_WSAR	0xeb10	/* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+	struct panthmpmu_registers *mpmu =
+		(struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
+	struct panthtmr_registers *panthtimers =
+		(struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
+	u32 val;
+
+	/* negate hardware reset to the WDT after system reset */
+	val = readl(&mpmu->aprr);
+	val = val | MPMU_APRR_WDTR;
+	writel(val, &mpmu->aprr);
+
+	/* reset/enable WDT clock */
+	writel(APBC_APBCLK, &mpmu->wdtpcr);
+
+	/* clear previous WDT status */
+	writel(TMR_WFAR, &panthtimers->wfar);
+	writel(TMP_WSAR, &panthtimers->wsar);
+	writel(0, &panthtimers->wdt_sts);
+
+	/* set match counter */
+	writel(TMR_WFAR, &panthtimers->wfar);
+	writel(TMP_WSAR, &panthtimers->wsar);
+	writel(0xf, &panthtimers->wdt_match_r);
+
+	/* enable WDT reset */
+	writel(TMR_WFAR, &panthtimers->wfar);
+	writel(TMP_WSAR, &panthtimers->wsar);
+	writel(0x3, &panthtimers->wdt_match_en);
+
+	/*enable functional WDT clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/Makefile
new file mode 100644
index 000000000..3f190bc0c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -0,0 +1,21 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= cpu.o \
+	   reset.o \
+	   timer.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o spl_boot.o
+obj-$(CONFIG_SPEAR600) += spear600.o
+obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
+obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
+obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
+obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+endif
+
+extra-$(CONFIG_SPL_BUILD) := start.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/cpu.c
new file mode 100644
index 000000000..3757ffb2c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_misc.h>
+
+int arch_cpu_init(void)
+{
+	struct misc_regs *const misc_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 periph1_clken, periph_clk_cfg;
+
+	periph1_clken = readl(&misc_p->periph1_clken);
+
+#if defined(CONFIG_SPEAR3XX)
+	periph1_clken |= MISC_GPT2ENB;
+#elif defined(CONFIG_SPEAR600)
+	periph1_clken |= MISC_GPT3ENB;
+#endif
+
+#if defined(CONFIG_PL011_SERIAL)
+	periph1_clken |= MISC_UART0ENB;
+
+	periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
+	periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
+	periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+	writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
+#endif
+#if defined(CONFIG_DESIGNWARE_ETH)
+	periph1_clken |= MISC_ETHENB;
+#endif
+#if defined(CONFIG_DW_UDC)
+	periph1_clken |= MISC_USBDENB;
+#endif
+#if defined(CONFIG_DW_I2C)
+	periph1_clken |= MISC_I2CENB;
+#endif
+#if defined(CONFIG_ST_SMI)
+	periph1_clken |= MISC_SMIENB;
+#endif
+#if defined(CONFIG_NAND_FSMC)
+	periph1_clken |= MISC_FSMCENB;
+#endif
+
+	writel(periph1_clken, &misc_p->periph1_clken);
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+#ifdef CONFIG_SPEAR300
+	printf("CPU:   SPEAr300\n");
+#elif defined(CONFIG_SPEAR310)
+	printf("CPU:   SPEAr310\n");
+#elif defined(CONFIG_SPEAR320)
+	printf("CPU:   SPEAr320\n");
+#elif defined(CONFIG_SPEAR600)
+	printf("CPU:   SPEAr600\n");
+#else
+#error CPU not supported in spear platform
+#endif
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/reset.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/reset.c
new file mode 100644
index 000000000..9546e80bc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/reset.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_syscntl.h>
+
+void reset_cpu(ulong ignored)
+{
+	struct syscntl_regs *syscntl_regs_p =
+	    (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
+
+	printf("System is going to reboot ...\n");
+
+	/*
+	 * This 1 second delay will allow the above message
+	 * to be printed before reset
+	 */
+	udelay((1000 * 1000));
+
+	/* Going into slow mode before resetting SOC */
+	writel(0x02, &syscntl_regs_p->scctrl);
+
+	/*
+	 * Writing any value to the system status register will
+	 * reset the SoC
+	 */
+	writel(0x00, &syscntl_regs_p->scsysstat);
+
+	/* system will restart */
+	while (1)
+		;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spear600.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spear600.c
new file mode 100644
index 000000000..6474e9d55
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spear600.c
@@ -0,0 +1,217 @@
+/*
+ * (C) Copyright 2000-2009
+ * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_defs.h>
+
+static void sel_1v8(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddr1v8, ddr2v5;
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000003;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000010;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
+		;
+}
+
+static void sel_2v5(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddr1v8, ddr2v5;
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000003;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000010;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
+		;
+}
+
+/*
+ * plat_ddr_init:
+ */
+void plat_ddr_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddrpad;
+	u32 core3v3, ddr1v8, ddr2v5;
+
+	/* DDR pad register configurations */
+	ddrpad = readl(&misc_p->ddr_pad);
+	ddrpad &= ~DDR_PAD_CNF_MSK;
+
+#if (CONFIG_DDR_HCLK)
+	ddrpad |= 0xEAAB;
+#elif (CONFIG_DDR_2HCLK)
+	ddrpad |= 0xEAAD;
+#elif (CONFIG_DDR_PLL2)
+	ddrpad |= 0xEAAD;
+#endif
+	writel(ddrpad, &misc_p->ddr_pad);
+
+	/* Compensation register configurations */
+	core3v3 = readl(&misc_p->core_3v3_compensation);
+	core3v3 &= 0x8080ffe0;
+	core3v3 |= 0x78000002;
+	writel(core3v3, &misc_p->core_3v3_compensation);
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000004;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000004;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
+		/* Software memory configuration */
+		if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
+			sel_1v8();
+		else
+			sel_2v5();
+	} else {
+		/* Hardware memory configuration */
+		if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
+			sel_1v8();
+		else
+			sel_2v5();
+	}
+}
+
+/*
+ * soc_init:
+ */
+void soc_init(void)
+{
+	/* Nothing to be done for SPEAr600 */
+}
+
+/*
+ * xxx_boot_selected:
+ *
+ * return true if the particular booting option is selected
+ * return false otherwise
+ */
+static u32 read_bootstrap(void)
+{
+	return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
+		& CONFIG_SPEAR_BOOTSTRAPMASK;
+}
+
+int snor_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (SNOR_BOOT_SUPPORTED) {
+		/* Check whether SNOR boot is selected */
+		if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
+			CONFIG_SPEAR_ONLYSNORBOOT)
+			return true;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND8BOOT)
+			return true;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND16BOOT)
+			return true;
+	}
+
+	return false;
+}
+
+int nand_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (NAND_BOOT_SUPPORTED) {
+		/* Check whether NAND boot is selected */
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND8BOOT)
+			return true;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND16BOOT)
+			return true;
+	}
+
+	return false;
+}
+
+int pnor_boot_selected(void)
+{
+	/* Parallel NOR boot is not selected in any SPEAr600 revision */
+	return false;
+}
+
+int usb_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (USB_BOOT_SUPPORTED) {
+		/* Check whether USB boot is selected */
+		if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
+			return true;
+	}
+
+	return false;
+}
+
+int tftp_boot_selected(void)
+{
+	/* TFTP boot is not selected in any SPEAr600 revision */
+	return false;
+}
+
+int uart_boot_selected(void)
+{
+	/* UART boot is not selected in any SPEAr600 revision */
+	return false;
+}
+
+int spi_boot_selected(void)
+{
+	/* SPI boot is not selected in any SPEAr600 revision */
+	return false;
+}
+
+int i2c_boot_selected(void)
+{
+	/* I2C boot is not selected in any SPEAr600 revision */
+	return false;
+}
+
+int mmc_boot_selected(void)
+{
+	return false;
+}
+
+void plat_late_init(void)
+{
+	spear_late_init();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl.c
new file mode 100644
index 000000000..b55040435
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_syscntl.h>
+
+static void ddr_clock_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 clkenb, ddrpll;
+
+	clkenb = readl(&misc_p->periph1_clken);
+	clkenb &= ~PERIPH_MPMCMSK;
+	clkenb |= PERIPH_MPMC_WE;
+
+	/* Intentionally done twice */
+	writel(clkenb, &misc_p->periph1_clken);
+	writel(clkenb, &misc_p->periph1_clken);
+
+	ddrpll = readl(&misc_p->pll_ctr_reg);
+	ddrpll &= ~MEM_CLK_SEL_MSK;
+#if (CONFIG_DDR_HCLK)
+	ddrpll |= MEM_CLK_HCLK;
+#elif (CONFIG_DDR_2HCLK)
+	ddrpll |= MEM_CLK_2HCLK;
+#elif (CONFIG_DDR_PLL2)
+	ddrpll |= MEM_CLK_PLL2;
+#else
+#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
+#endif
+	writel(ddrpll, &misc_p->pll_ctr_reg);
+
+	writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
+			&misc_p->periph1_clken);
+}
+
+static void mpmc_init_values(void)
+{
+	u32 i;
+	u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+	u32 *mpmc_val_p = &mpmc_conf_vals[0];
+
+	for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
+		writel(*mpmc_val_p, mpmc_reg_p);
+
+	mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+
+	/*
+	 * MPMC controller start
+	 * MPMC waiting for DLLLOCKREG high
+	 */
+	writel(0x01000100, &mpmc_reg_p[7]);
+
+	while (!(readl(&mpmc_reg_p[3]) & 0x10000))
+		;
+}
+
+static void mpmc_init(void)
+{
+	/* Clock related settings for DDR */
+	ddr_clock_init();
+
+	/*
+	 * DDR pad register bits are different for different SoCs
+	 * Compensation values are also handled separately
+	 */
+	plat_ddr_init();
+
+	/* Initialize mpmc register values */
+	mpmc_init_values();
+}
+
+static void pll_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	/* Initialize PLLs */
+	writel(FREQ_332, &misc_p->pll1_frq);
+	writel(0x1C0A, &misc_p->pll1_cntl);
+	writel(0x1C0E, &misc_p->pll1_cntl);
+	writel(0x1C06, &misc_p->pll1_cntl);
+	writel(0x1C0E, &misc_p->pll1_cntl);
+
+	writel(FREQ_332, &misc_p->pll2_frq);
+	writel(0x1C0A, &misc_p->pll2_cntl);
+	writel(0x1C0E, &misc_p->pll2_cntl);
+	writel(0x1C06, &misc_p->pll2_cntl);
+	writel(0x1C0E, &misc_p->pll2_cntl);
+
+	/* wait for pll locks */
+	while (!(readl(&misc_p->pll1_cntl) & 0x1))
+		;
+	while (!(readl(&misc_p->pll2_cntl) & 0x1))
+		;
+}
+
+static void mac_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
+			&misc_p->periph1_clken);
+
+	writel(SYNTH23, &misc_p->gmac_synth_clk);
+
+	switch (get_socrev()) {
+	case SOC_SPEAR600_AA:
+	case SOC_SPEAR600_AB:
+	case SOC_SPEAR600_BA:
+	case SOC_SPEAR600_BB:
+	case SOC_SPEAR600_BC:
+	case SOC_SPEAR600_BD:
+		writel(0x0, &misc_p->gmac_ctr_reg);
+		break;
+
+	case SOC_SPEAR300:
+	case SOC_SPEAR310:
+	case SOC_SPEAR320:
+		writel(0x4, &misc_p->gmac_ctr_reg);
+		break;
+	}
+
+	writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
+			&misc_p->periph1_clken);
+
+	writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
+			&misc_p->periph1_rst);
+	writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
+			&misc_p->periph1_rst);
+}
+
+static void sys_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct syscntl_regs *syscntl_p =
+		(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
+
+	/* Set system state to SLOW */
+	writel(SLOW, &syscntl_p->scctrl);
+	writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
+
+	/* Initialize PLLs */
+	pll_init();
+
+	/*
+	 * Ethernet configuration
+	 * To be done only if the tftp boot is not selected already
+	 * Boot code ensures the correct configuration in tftp booting
+	 */
+	if (!tftp_boot_selected())
+		mac_init();
+
+	writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
+	writel(0x555, &misc_p->amba_clk_cfg);
+
+	writel(NORMAL, &syscntl_p->scctrl);
+
+	/* Wait for system to switch to normal mode */
+	while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
+		!= NORMAL)
+		;
+}
+
+/*
+ * get_socrev
+ *
+ * Get SoC Revision.
+ * @return SOC_SPEARXXX
+ */
+int get_socrev(void)
+{
+#if defined(CONFIG_SPEAR600)
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 soc_id = readl(&misc_p->soc_core_id);
+	u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
+	u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
+
+	if ((pri_socid == 'B') && (sec_socid == 'B'))
+		return SOC_SPEAR600_BB;
+	else if ((pri_socid == 'B') && (sec_socid == 'C'))
+		return SOC_SPEAR600_BC;
+	else if ((pri_socid == 'B') && (sec_socid == 'D'))
+		return SOC_SPEAR600_BD;
+	else if (soc_id == 0)
+		return SOC_SPEAR600_BA;
+	else
+		return SOC_SPEAR_NA;
+#elif defined(CONFIG_SPEAR300)
+	return SOC_SPEAR300;
+#elif defined(CONFIG_SPEAR310)
+	return SOC_SPEAR310;
+#elif defined(CONFIG_SPEAR320)
+	return SOC_SPEAR320;
+#endif
+}
+
+void lowlevel_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	const char *u_boot_rev = U_BOOT_VERSION;
+
+	/* Initialize PLLs */
+	sys_init();
+
+	/* Initialize UART */
+	serial_init();
+
+	/* Print U-Boot SPL version string */
+	serial_puts("\nU-Boot SPL ");
+	/* Avoid a second "U-Boot" coming from this string */
+	u_boot_rev = &u_boot_rev[7];
+	serial_puts(u_boot_rev);
+	serial_puts(" (");
+	serial_puts(U_BOOT_DATE);
+	serial_puts(" - ");
+	serial_puts(U_BOOT_TIME);
+	serial_puts(")\n");
+
+#if defined(CONFIG_OS_BOOT)
+	writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
+			&misc_p->periph1_clken);
+#endif
+
+	/* Enable IPs (release reset) */
+	writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
+
+	/* Initialize MPMC */
+	serial_puts("Configure DDR\n");
+	mpmc_init();
+
+	/* SoC specific initialization */
+	soc_init();
+}
+
+void spear_late_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	writel(0x80000007, &misc_p->arb_icm_ml1);
+	writel(0x80000007, &misc_p->arb_icm_ml2);
+	writel(0x80000007, &misc_p->arb_icm_ml3);
+	writel(0x80000007, &misc_p->arb_icm_ml4);
+	writel(0x80000007, &misc_p->arb_icm_ml5);
+	writel(0x80000007, &misc_p->arb_icm_ml6);
+	writel(0x80000007, &misc_p->arb_icm_ml7);
+	writel(0x80000007, &misc_p->arb_icm_ml8);
+	writel(0x80000007, &misc_p->arb_icm_ml9);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl_boot.c
new file mode 100644
index 000000000..c846d758c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spl_boot.c
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <image.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/arch/spr_defs.h>
+#include <linux/mtd/st_smi.h>
+
+static const char kernel_name[] = "Linux";
+static const char loader_name[] = "U-Boot";
+
+int image_check_header(image_header_t *hdr, const char *name)
+{
+	if (image_check_magic(hdr) &&
+	    (!strncmp(image_get_name(hdr), name, strlen(name))) &&
+	    image_check_hcrc(hdr)) {
+		return 1;
+	}
+	return 0;
+}
+
+int image_check_data(image_header_t *hdr)
+{
+	if (image_check_dcrc(hdr))
+		return 1;
+
+	return 0;
+}
+
+/*
+ * SNOR (Serial NOR flash) related functions
+ */
+void snor_init(void)
+{
+	struct smi_regs *const smicntl =
+		(struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+
+	/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
+	writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
+	       &smicntl->smi_cr1);
+}
+
+static int snor_image_load(u8 *load_addr, void (**image_p)(void),
+			   const char *image_name)
+{
+	image_header_t *header;
+
+	/*
+	 * Since calculating the crc in the SNOR flash does not
+	 * work, we copy the image to the destination address
+	 * minus the header size. And point the header to this
+	 * new destination. This will not work for address 0
+	 * of course.
+	 */
+	header = (image_header_t *)load_addr;
+	memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)),
+	       (const ulong *)load_addr,
+	       image_get_data_size(header) + sizeof(image_header_t));
+	header = (image_header_t *)(image_get_load(header) -
+				    sizeof(image_header_t));
+
+	if (image_check_header(header, image_name)) {
+		if (image_check_data(header)) {
+			/* Jump to boot image */
+			*image_p = (void *)image_get_load(header);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+static void boot_image(void (*image)(void))
+{
+	void (*funcp)(void) __noreturn = (void *)image;
+
+	(*funcp)();
+}
+
+/*
+ * spl_boot:
+ *
+ * All supported booting types of all supported SoCs are listed here.
+ * Generic readback APIs are provided for each supported booting type
+ * eg. nand_read_skip_bad
+ */
+u32 spl_boot(void)
+{
+	void (*image)(void);
+
+#ifdef CONFIG_SPEAR_USBTTY
+	plat_late_init();
+	return 1;
+#endif
+
+	/*
+	 * All the supported booting devices are listed here. Each of
+	 * the booting type supported by the platform would define the
+	 * macro xxx_BOOT_SUPPORTED to true.
+	 */
+
+	if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
+		/* SNOR-SMI initialization */
+		snor_init();
+
+		serial_puts("Booting via SNOR\n");
+		/* Serial NOR booting */
+		if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE,
+					    &image, loader_name)) {
+			/* Platform related late initialasations */
+			plat_late_init();
+
+			/* Jump to boot image */
+			serial_puts("Jumping to U-Boot\n");
+			boot_image(image);
+			return 1;
+		}
+	}
+
+	if (NAND_BOOT_SUPPORTED && nand_boot_selected()) {
+		/* NAND booting */
+		/* Not ported from XLoader to SPL yet */
+		return 0;
+	}
+
+	if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
+		/* PNOR booting */
+		/* Not ported from XLoader to SPL yet */
+		return 0;
+	}
+
+	if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) {
+		/* MMC booting */
+		/* Not ported from XLoader to SPL yet */
+		return 0;
+	}
+
+	if (SPI_BOOT_SUPPORTED && spi_boot_selected()) {
+		/* SPI booting */
+		/* Not supported for any platform as of now */
+		return 0;
+	}
+
+	if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) {
+		/* I2C booting */
+		/* Not supported for any platform as of now */
+		return 0;
+	}
+
+	/*
+	 * All booting types without memory are listed as below
+	 * Control has to be returned to BootROM in case of all
+	 * the following booting scenarios
+	 */
+
+	if (USB_BOOT_SUPPORTED && usb_boot_selected()) {
+		plat_late_init();
+		return 1;
+	}
+
+	if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) {
+		plat_late_init();
+		return 1;
+	}
+
+	if (UART_BOOT_SUPPORTED && uart_boot_selected()) {
+		plat_late_init();
+		return 1;
+	}
+
+	/* Ideally, the control should not reach here. */
+	hang();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
new file mode 100644
index 000000000..3d6ad04ab
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000001,
+	0x00000000,
+	0x01000000,
+	0x00000101,
+	0x00000001,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x00010001,
+	0x00000003,
+	0x01000201,
+	0x06000202,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000404,
+	0x02030202,
+	0x03000204,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x08080a01,
+	0x0000023f,
+	0x00040800,
+	0x00000000,
+	0x00000f02,
+	0x00001b1b,
+	0x7f000000,
+	0x005f0000,
+	0x1c040b6a,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x000007ff,
+	0x00000000,
+	0x47ec00c8,
+	0x00c8001f,
+	0x00000000,
+	0x0000cd98,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00270000,
+	0x00250027,
+	0x00300000,
+	0x008900b7,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
new file mode 100644
index 000000000..105b3058f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
@@ -0,0 +1,119 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+	0x00000001,
+	0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+	0x02020201,
+	0x02020202,
+#endif
+	0x01000000,
+	0x00000101,
+	0x00000101,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x01010001,
+	0x00000201,
+	0x01000101,
+	0x06000002,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000405,
+	0x03040202,
+	0x04000305,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x0a0a0a01,
+	0x0000023f,
+	0x00050a00,
+	0x11000000,
+	0x00001302,
+	0x00000A0A,
+	0x72000000,
+	0x00550000,
+	0x2b050e86,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00000a24,
+	0x43C20000,
+	0x5b1c00c8,
+	0x00c8002e,
+	0x00000000,
+	0x0001046b,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00210000,
+	0x00010021,
+	0x00200000,
+	0x006c0090,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
new file mode 100644
index 000000000..00b6b2927
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x03030301,
+	0x03030303,
+	0x01000000,
+	0x00000101,
+	0x00000001,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x00010001,
+	0x00000003,
+	0x01000201,
+	0x06000202,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000404,
+	0x02020202,
+	0x03000203,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x08080a01,
+	0x0000023f,
+	0x00030600,
+	0x00000000,
+	0x00000a02,
+	0x00001c1c,
+	0x7f000000,
+	0x005f0000,
+	0x12030743,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x0000050e,
+	0x00000000,
+	0x2d8900c8,
+	0x00c80014,
+	0x00000000,
+	0x00008236,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00400000,
+	0x003a0040,
+	0x00680000,
+	0x00d80120,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
new file mode 100644
index 000000000..a406c3e8c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+	0x00000001,
+	0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+	0x02020201,
+	0x02020202,
+#endif
+	0x01000000,
+	0x00000101,
+	0x00000101,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x01010001,
+	0x00000201,
+	0x01000101,
+	0x06000002,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+#ifdef CONFIG_X600
+	0x02030206,
+#else
+	0x02010106,
+#endif
+	0x03000405,
+	0x03040202,
+	0x04000305,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x0a0a0a01,
+	0x0000023f,
+	0x00050a00,
+	0x11000000,
+	0x00001302,
+	0x00000A0A,
+#ifdef CONFIG_X600
+	0x7f000000,
+	0x005c0000,
+#else
+	0x72000000,
+	0x00550000,
+#endif
+	0x2b050e86,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00000a24,
+	0x43C20000,
+	0x5b1c00c8,
+	0x00c8002e,
+	0x00000000,
+	0x0001046b,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00210000,
+	0x00010021,
+	0x00200000,
+	0x006c0090,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/start.S
new file mode 100644
index 000000000..7dbd5dbf9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/start.S
@@ -0,0 +1,106 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <config.h>
+
+.globl _start
+_start:
+	b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+_software_interrupt:
+_prefetch_abort:
+_data_abort:
+_not_used:
+_irq:
+_fiq:
+	.word infinite_loop
+
+infinite_loop:
+	b	infinite_loop
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * Below are the critical initializations already taken place in BootROM.
+ * So, these are not taken care in Xloader
+ * 1. Relocation to RAM
+ * 2. Initializing stacks
+ *
+ *************************************************************************
+ */
+
+/*
+ * the actual reset code
+ */
+
+reset:
+/*
+ * Xloader has to return back to BootROM in a few cases.
+ * eg. Ethernet boot, UART boot, USB boot
+ * Saving registers for returning back
+ */
+	stmdb	sp!, {r0-r12,r14}
+	bl	cpu_init_crit
+/*
+ * Clearing bss area is not done in Xloader.
+ * BSS area lies in the DDR location which is not yet initialized
+ * bss is assumed to be uninitialized.
+ */
+	bl	spl_boot
+	ldmia	sp!, {r0-r12,pc}
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * enable instruction cache
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	stmdb	sp!, {lr}
+	bl	lowlevel_init	/* go setup pll,mux,memory */
+	ldmia	sp!, {pc}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/timer.c
new file mode 100644
index 000000000..c88e962a3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_gpt.h>
+#include <asm/arch/spr_misc.h>
+
+#define GPT_RESOLUTION	(CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
+#define READ_TIMER()	(readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
+
+static struct gpt_regs *const gpt_regs_p =
+    (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
+
+static struct misc_regs *const misc_regs_p =
+    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+int timer_init(void)
+{
+	u32 synth;
+
+	/* Prescaler setting */
+#if defined(CONFIG_SPEAR3XX)
+	writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
+	synth = MISC_GPT4SYNTH;
+#elif defined(CONFIG_SPEAR600)
+	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
+	synth = MISC_GPT3SYNTH;
+#else
+# error Incorrect config. Can only be spear{600|300|310|320}
+#endif
+
+	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
+	       &misc_regs_p->periph_clk_cfg);
+
+	/* disable timers */
+	writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
+
+	/* load value for free running */
+	writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
+
+	/* auto reload, start timer */
+	writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
+
+	/* Reset the timer */
+	lastdec = READ_TIMER();
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer(ulong base)
+{
+	return (get_timer_masked() / GPT_RESOLUTION) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong tmo;
+	ulong start = get_timer_masked();
+	ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
+	ulong rndoff;
+
+	rndoff = (usec % 10) ? 1 : 0;
+
+	/* tenudelcnt timer tick gives 10 microsecconds delay */
+	tmo = ((usec / 10) + rndoff) * tenudelcnt;
+
+	while ((ulong) (get_timer_masked() - start) < tmo)
+		;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER();
+
+	if (now >= lastdec) {
+		/* normal mode */
+		timestamp += now - lastdec;
+	} else {
+		/* we have an overflow ... */
+		timestamp += now + GPT_FREE_RUNNING - lastdec;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+	return udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SPEAR_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
new file mode 100644
index 000000000..b6d0f65b6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/arm926ejs/spear/start.o	(.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/start.S
new file mode 100644
index 000000000..071732705
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/start.S
@@ -0,0 +1,372 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <version.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
+.globl _start
+_start:
+.globl _NOR_BOOT_CFG
+_NOR_BOOT_CFG:
+	.word	CONFIG_SYS_DV_NOR_BOOT_CFG
+	b	reset
+#else
+.globl _start
+_start:
+	b	reset
+#endif
+#ifdef CONFIG_SPL_BUILD
+/* No exception handlers in preloader */
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+
+_hang:
+	.word	do_hang
+/* pad to 64 byte boundary */
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+#else
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+	.word undefined_instruction
+_software_interrupt:
+	.word software_interrupt
+_prefetch_abort:
+	.word prefetch_abort
+_data_abort:
+	.word data_abort
+_not_used:
+	.word not_used
+_irq:
+	.word irq
+_fiq:
+	.word fiq
+
+#endif	/* CONFIG_SPL_BUILD */
+	.balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+	bx	lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+	/*
+	 * flush D cache before disabling it
+	 */
+	mov	r0, #0
+flush_dcache:
+	mrc	p15, 0, r15, c7, c10, 3
+	bne	flush_dcache
+
+	mcr	p15, 0, r0, c8, c7, 0	/* invalidate TLB */
+	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I Cache */
+
+	/*
+	 * disable MMU and D cache
+	 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
+	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
+#else
+	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */
+#endif
+	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
+#ifndef CONFIG_SYS_ICACHE_OFF
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+#endif
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	mov	ip, lr		/* perserve link reg across call */
+	bl	lowlevel_init	/* go setup pll,mux,memory */
+	mov	lr, ip		/* restore link */
+	mov	pc, lr		/* back to my caller */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	@ carve out a frame on current user stack
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
+	ldr	r2, IRQ_STACK_START_IN
+	@ get values for "aborted" pc and cpsr (into parm regs)
+	ldmia	r2, {r2 - r3}
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp		@ save current stack into r0 (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	add	r8, sp, #S_PC
+	stmdb	r8, {sp, lr}^		@ Calling SP, LR
+	str	lr, [r8, #0]		@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]		@ Save CPSR
+	str	r0, [r8, #8]		@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+
+	str	lr, [r13]	@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr	@ get the spsr
+	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
+	mov	r13, #MODE_SVC	@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13	@ switch modes, make sure moves will execute
+	mov	lr, pc		@ capture return pc
+	movs	pc, lr		@ jump to next instruction & switch modes.
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+#endif	/* CONFIG_SPL_BUILD */
+
+/*
+ * exception handlers
+ */
+#ifdef CONFIG_SPL_BUILD
+	.align	5
+do_hang:
+1:
+	bl	1b				/* hang and never return */
+#else	/* !CONFIG_SPL_BUILD */
+	.align  5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+#endif	/* CONFIG_SPL_BUILD */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/versatile/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/versatile/Makefile
new file mode 100644
index 000000000..907f5161a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/versatile/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= timer.o
+obj-y	+= reset.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/versatile/reset.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/versatile/reset.S
new file mode 100644
index 000000000..1c557b0d9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/versatile/reset.S
@@ -0,0 +1,29 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, rstctl1	/* get clkm1 reset ctl */
+	mov	r3, #0x0
+	strh	r3, [r1]	/* clear it */
+	mov	r3, #0x8
+	strh	r3, [r1]	/* force dsp+arm reset */
+_loop_forever:
+	b	_loop_forever
+
+rstctl1:
+	.word	0xfffece10
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/versatile/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/versatile/timer.c
new file mode 100644
index 000000000..5d694d85e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/versatile/timer.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#define TIMER_ENABLE	(1 << 7)
+#define TIMER_MODE_MSK	(1 << 6)
+#define TIMER_MODE_FR	(0 << 6)
+#define TIMER_MODE_PD	(1 << 6)
+
+#define TIMER_INT_EN	(1 << 5)
+#define TIMER_PRS_MSK	(3 << 2)
+#define TIMER_PRS_8S	(1 << 3)
+#define TIMER_SIZE_MSK	(1 << 2)
+#define TIMER_ONE_SHT	(1 << 0)
+
+int timer_init (void)
+{
+	ulong	tmr_ctrl_val;
+
+	/* 1st disable the Timer */
+	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
+	tmr_ctrl_val &= ~TIMER_ENABLE;
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
+
+	/*
+	 * The Timer Control Register has one Undefined/Shouldn't Use Bit
+	 * So we should do read/modify/write Operation
+	 */
+
+	/*
+	 * Timer Mode : Free Running
+	 * Interrupt : Disabled
+	 * Prescale : 8 Stage, Clk/256
+	 * Tmr Siz : 16 Bit Counter
+	 * Tmr in Wrapping Mode
+	 */
+	tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
+	tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
+	tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
+
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
+
+	return 0;
+}
+
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm946es/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm946es/Makefile
new file mode 100644
index 000000000..a44bddc2f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm946es/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+
+obj-y	= cpu.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm946es/config.mk b/qemu/roms/u-boot/arch/arm/cpu/arm946es/config.mk
new file mode 100644
index 000000000..438668d6f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm946es/config.mk
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS +=  -march=armv4
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm946es/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm946es/cpu.c
new file mode 100644
index 000000000..0c8d92d73
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm946es/cpu.c
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+	/* ARM926E-S needs the protection unit enabled for the icache to have
+	 * been enabled	 - left for possible later use
+	 * should turn off the protection unit as well....
+	 */
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+	/* flush I/D-cache */
+	cache_flush();
+
+	return 0;
+}
+
+/* flush I/D-cache */
+static void cache_flush (void)
+{
+	unsigned long i = 0;
+
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+	asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm946es/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm946es/start.S
new file mode 100644
index 000000000..7d5014583
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm946es/start.S
@@ -0,0 +1,345 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:
+	b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+	.word undefined_instruction
+_software_interrupt:
+	.word software_interrupt
+_prefetch_abort:
+	.word prefetch_abort
+_data_abort:
+	.word data_abort
+_not_used:
+	.word not_used
+_irq:
+	.word irq
+_fiq:
+	.word fiq
+
+	.balignl 16,0xdeadbeef
+
+_vectors_end:
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+	mov	pc, lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 0	/* flush v4 I-cache */
+	mcr	p15, 0, r0, c7, c6, 0	/* flush v4 D-cache */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
+	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	mov	ip, lr		/* perserve link reg across call */
+	bl	lowlevel_init	/* go setup memory */
+	mov	lr, ip		/* restore link */
+	mov	pc, lr		/* back to my caller */
+#endif
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	@ carve out a frame on current user stack
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
+
+	ldr	r2, IRQ_STACK_START_IN
+	@ get values for "aborted" pc and cpsr (into parm regs)
+	ldmia	r2, {r2 - r3}
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp		@ save current stack into r0 (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	add	r8, sp, #S_PC
+	stmdb	r8, {sp, lr}^		@ Calling SP, LR
+	str	lr, [r8, #0]		@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]		@ Save CPSR
+	str	r0, [r8, #8]		@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+
+	str	lr, [r13]	@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr	@ get the spsr
+	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
+	mov	r13, #MODE_SVC	@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13	@ switch modes, make sure moves will execute
+	mov	lr, pc		@ capture return pc
+	movs	pc, lr		@ jump to next instruction & switch modes.
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align  5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+
+# ifdef CONFIG_INTEGRATOR
+
+	/* Satisfied by general board level routine */
+
+#else
+
+	.align	5
+.globl reset_cpu
+reset_cpu:
+
+	ldr	r1, rstctl1	/* get clkm1 reset ctl */
+	mov	r3, #0x0
+	strh	r3, [r1]	/* clear it */
+	mov	r3, #0x8
+	strh	r3, [r1]	/* force dsp+arm reset */
+_loop_forever:
+	b	_loop_forever
+
+rstctl1:
+	.word	0xfffece10
+
+#endif	/* #ifdef CONFIG_INTEGRATOR */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/Makefile
new file mode 100644
index 000000000..3279f125f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+obj-y	= cpu.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/config.mk b/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/config.mk
new file mode 100644
index 000000000..438668d6f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/config.mk
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS +=  -march=armv4
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/cpu.c
new file mode 100644
index 000000000..0d00e4b7a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/cpu.c
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPU specific code for an unknown cpu
+ * - hence fairly empty......
+ */
+
+#include <common.h>
+#include <command.h>
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+	/* Since the CM has unknown processor we do not support
+	 * cache operations
+	 */
+
+	return (0);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/start.S
new file mode 100644
index 000000000..7404ea734
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/arm_intcm/start.S
@@ -0,0 +1,305 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table
+ *
+ *************************************************************************
+ */
+
+.globl _start
+_start:
+	b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+	.word undefined_instruction
+_software_interrupt:
+	.word software_interrupt
+_prefetch_abort:
+	.word prefetch_abort
+_data_abort:
+	.word data_abort
+_not_used:
+	.word not_used
+_irq:
+	.word irq
+_fiq:
+	.word fiq
+
+	.balignl 16,0xdeadbeef
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+	mov	pc, lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+	/*  arm_int_generic assumes the ARM boot monitor, or user software,
+	 * has initialized the platform
+	 */
+	mov	pc, lr		/* back to my caller */
+#endif
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	@ carve out a frame on current user stack
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12
+
+	ldr	r2, IRQ_STACK_START_IN
+	@ get values for "aborted" pc and cpsr (into parm regs)
+	ldmia	r2, {r2 - r3}
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp		@ save current stack into r0 (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	add	r8, sp, #S_PC
+	stmdb	r8, {sp, lr}^		@ Calling SP, LR
+	str	lr, [r8, #0]		@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]		@ Save CPSR
+	str	r0, [r8, #8]		@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+
+	str	lr, [r13]	@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr	@ get the spsr
+	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
+	mov	r13, #MODE_SVC	@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13	@ switch modes, make sure moves will execute
+	mov	lr, pc		@ capture return pc
+	movs	pc, lr		@ jump to next instruction & switch modes.
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align  5
+.globl undefined_instruction
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+.globl software_interrupt
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+.globl prefetch_abort
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+.globl data_abort
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+.globl not_used
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+	.align	5
+.globl irq
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+.globl fiq
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+.globl irq
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+.globl fiq
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/Makefile
new file mode 100644
index 000000000..ab869b1ee
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/Makefile
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	:= start.o
+
+obj-y	+= cache_v7.o
+
+obj-y	+= cpu.o
+obj-y	+= syslib.o
+
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
+ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
+obj-y	+= lowlevel_init.o
+endif
+endif
+
+ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
+obj-y	+= nonsec_virt.o
+obj-y	+= virt-v7.o
+endif
+
+obj-$(CONFIG_KONA) += kona-common/
+obj-$(CONFIG_OMAP_COMMON) += omap-common/
+obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
+obj-$(CONFIG_TEGRA) += tegra-common/
+
+ifneq (,$(filter s5pc1xx exynos,$(SOC)))
+obj-y += s5p-common/
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/Makefile
new file mode 100644
index 000000000..5566310d9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AM33XX)	+= clock_am33xx.o
+obj-$(CONFIG_TI814X)	+= clock_ti814x.o
+obj-$(CONFIG_AM43XX)	+= clock_am43xx.o
+
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
+obj-y	+= clock.o
+endif
+
+obj-$(CONFIG_TI816X)	+= clock_ti816x.o
+obj-y	+= sys_info.o
+obj-y	+= mem.o
+obj-y	+= ddr.o
+obj-y	+= emif4.o
+obj-y	+= board.o
+obj-y	+= mux.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/board.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/board.c
new file mode 100644
index 000000000..28c16f8d0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/board.c
@@ -0,0 +1,251 @@
+/*
+ * board.c
+ *
+ * Common board functions for AM33XX based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <asm/errno.h>
+#include <linux/compiler.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/davinci_rtc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct gpio_bank gpio_bank_am33xx[] = {
+	{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
+	{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+#ifdef CONFIG_AM43XX
+	{ (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+#endif
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int cpu_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	ret = omap_mmc_init(0, 0, 0, -1, -1);
+	if (ret)
+		return ret;
+
+	return omap_mmc_init(1, 0, 0, -1, -1);
+}
+#endif
+
+/* AM33XX has two MUSB controllers which can be host or gadget */
+#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
+	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* USB 2.0 PHY Control */
+#define CM_PHY_PWRDN			(1 << 0)
+#define CM_PHY_OTG_PWRDN		(1 << 1)
+#define OTGVDET_EN			(1 << 19)
+#define OTGSESSENDEN			(1 << 20)
+
+static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
+{
+	if (on) {
+		clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
+				OTGVDET_EN | OTGSESSENDEN);
+	} else {
+		clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
+	}
+}
+
+static struct musb_hdrc_config musb_config = {
+	.multipoint     = 1,
+	.dyn_fifo       = 1,
+	.num_eps        = 16,
+	.ram_bits       = 12,
+};
+
+#ifdef CONFIG_AM335X_USB0
+static void am33xx_otg0_set_phy_power(u8 on)
+{
+	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
+}
+
+struct omap_musb_board_data otg0_board_data = {
+	.set_phy_power = am33xx_otg0_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg0_plat = {
+	.mode           = CONFIG_AM335X_USB0_MODE,
+	.config         = &musb_config,
+	.power          = 50,
+	.platform_ops	= &musb_dsps_ops,
+	.board_data	= &otg0_board_data,
+};
+#endif
+
+#ifdef CONFIG_AM335X_USB1
+static void am33xx_otg1_set_phy_power(u8 on)
+{
+	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
+}
+
+struct omap_musb_board_data otg1_board_data = {
+	.set_phy_power = am33xx_otg1_set_phy_power,
+};
+
+static struct musb_hdrc_platform_data otg1_plat = {
+	.mode           = CONFIG_AM335X_USB1_MODE,
+	.config         = &musb_config,
+	.power          = 50,
+	.platform_ops	= &musb_dsps_ops,
+	.board_data	= &otg1_board_data,
+};
+#endif
+#endif
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_AM335X_USB0
+	musb_register(&otg0_plat, &otg0_board_data,
+		(void *)USB0_OTG_BASE);
+#endif
+#ifdef CONFIG_AM335X_USB1
+	musb_register(&otg1_plat, &otg1_board_data,
+		(void *)USB1_OTG_BASE);
+#endif
+	return 0;
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*
+ * This function is the place to do per-board things such as ramp up the
+ * MPU clock frequency.
+ */
+__weak void am33xx_spl_board_init(void)
+{
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
+static void rtc32k_enable(void)
+{
+	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(RTC_KICK0R_WE, &rtc->kick0r);
+	writel(RTC_KICK1R_WE, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+#endif
+
+static void uart_soft_reset(void)
+{
+	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+	u32 regval;
+
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_RESET;
+	writel(regval, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_SMART_IDLE_EN;
+	writel(regval, &uart_base->uartsyscfg);
+}
+
+static void watchdog_disable(void)
+{
+	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
+
+void s_init(void)
+{
+	/*
+	 * The ROM will only have set up sufficient pinmux to allow for the
+	 * first 4KiB NOR to be read, we must finish doing what we know of
+	 * the NOR mux in this space in order to continue.
+	 */
+#ifdef CONFIG_NOR_BOOT
+	enable_norboot_pin_mux();
+#endif
+	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	save_omap_boot_params();
+#endif
+	watchdog_disable();
+	timer_init();
+	set_uart_mux_conf();
+	setup_clocks_for_console();
+	uart_soft_reset();
+#ifdef CONFIG_NOR_BOOT
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();
+	gd->have_console = 1;
+#elif defined(CONFIG_SPL_BUILD)
+	gd = &gdata;
+	preloader_console_init();
+#endif
+	prcm_init();
+	set_mux_conf_regs();
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+#endif
+	sdram_init();
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif /* !CONFIG_SYS_DCACHE_OFF */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock.c
new file mode 100644
index 000000000..0672798fe
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock.c
@@ -0,0 +1,177 @@
+/*
+ * clock.c
+ *
+ * Clock initialization for AM33XX boards.
+ * Derived from OMAP4 boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+static void setup_post_dividers(const struct dpll_regs *dpll_regs,
+			 const struct dpll_params *params)
+{
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, dpll_regs->cm_div_m3_dpll);
+	if (params->m4 >= 0)
+		writel(params->m4, dpll_regs->cm_div_m4_dpll);
+	if (params->m5 >= 0)
+		writel(params->m5, dpll_regs->cm_div_m5_dpll);
+	if (params->m6 >= 0)
+		writel(params->m6, dpll_regs->cm_div_m6_dpll);
+}
+
+static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
+{
+	clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
+{
+	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("DPLL locking failed for 0x%x\n",
+		       dpll_regs->cm_clkmode_dpll);
+		hang();
+	}
+}
+
+static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+	clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
+{
+	if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("Bypassing DPLL failed 0x%x\n",
+		       dpll_regs->cm_clkmode_dpll);
+	}
+}
+
+static void bypass_dpll(const struct dpll_regs *dpll_regs)
+{
+	do_bypass_dpll(dpll_regs);
+	wait_for_bypass(dpll_regs);
+}
+
+void do_setup_dpll(const struct dpll_regs *dpll_regs,
+		   const struct dpll_params *params)
+{
+	u32 temp;
+
+	if (!params)
+		return;
+
+	temp = readl(dpll_regs->cm_clksel_dpll);
+
+	bypass_dpll(dpll_regs);
+
+	/* Set M & N */
+	temp &= ~CM_CLKSEL_DPLL_M_MASK;
+	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+	temp &= ~CM_CLKSEL_DPLL_N_MASK;
+	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+	writel(temp, dpll_regs->cm_clksel_dpll);
+
+	setup_post_dividers(dpll_regs, params);
+
+	/* Wait till the DPLL locks */
+	do_lock_dpll(dpll_regs);
+	wait_for_lock(dpll_regs);
+}
+
+static void setup_dplls(void)
+{
+	const struct dpll_params *params;
+
+	params = get_dpll_core_params();
+	do_setup_dpll(&dpll_core_regs, params);
+
+	params = get_dpll_mpu_params();
+	do_setup_dpll(&dpll_mpu_regs, params);
+
+	params = get_dpll_per_params();
+	do_setup_dpll(&dpll_per_regs, params);
+	writel(0x300, &cmwkup->clkdcoldodpllper);
+
+	params = get_dpll_ddr_params();
+	do_setup_dpll(&dpll_ddr_regs, params);
+}
+
+static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+	u32 bound = LDELAY;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock enable failed for 0x%p idlest 0x%x\n",
+			       clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+				       u32 wait_for_enable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Enable clock module - %p\n", clkctrl_addr);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Enable clock domain - %p\n", clkctrl_reg);
+}
+
+void do_enable_clocks(u32 *const *clk_domains,
+		      u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
+{
+	u32 i, max = 100;
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++) {
+		enable_clock_domain(clk_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+		enable_clock_module(clk_modules_explicit_en[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+}
+
+void prcm_init()
+{
+	enable_basic_clocks();
+	setup_dplls();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
new file mode 100644
index 000000000..92142c893
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -0,0 +1,161 @@
+/*
+ * clock_am33xx.c
+ *
+ * clocks for AM33XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define OSC	(V_OSCK/1000000)
+
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
+
+const struct dpll_regs dpll_mpu_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x88,
+	.cm_idlest_dpll		= CM_WKUP + 0x20,
+	.cm_clksel_dpll		= CM_WKUP + 0x2C,
+	.cm_div_m2_dpll		= CM_WKUP + 0xA8,
+};
+
+const struct dpll_regs dpll_core_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x90,
+	.cm_idlest_dpll		= CM_WKUP + 0x5C,
+	.cm_clksel_dpll		= CM_WKUP + 0x68,
+	.cm_div_m4_dpll		= CM_WKUP + 0x80,
+	.cm_div_m5_dpll		= CM_WKUP + 0x84,
+	.cm_div_m6_dpll		= CM_WKUP + 0xD8,
+};
+
+const struct dpll_regs dpll_per_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x8C,
+	.cm_idlest_dpll		= CM_WKUP + 0x70,
+	.cm_clksel_dpll		= CM_WKUP + 0x9C,
+	.cm_div_m2_dpll		= CM_WKUP + 0xAC,
+};
+
+const struct dpll_regs dpll_ddr_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x94,
+	.cm_idlest_dpll		= CM_WKUP + 0x34,
+	.cm_clksel_dpll		= CM_WKUP + 0x40,
+	.cm_div_m2_dpll		= CM_WKUP + 0xA0,
+};
+
+struct dpll_params dpll_mpu_opp100 = {
+		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core_opp100 = {
+		1000, OSC-1, -1, -1, 10, 8, 4};
+const struct dpll_params dpll_mpu = {
+		MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+		50, OSC-1, -1, -1, 1, 1, 1};
+const struct dpll_params dpll_per = {
+		960, OSC-1, 5, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	return &dpll_mpu;
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	return &dpll_core;
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	return &dpll_per;
+}
+
+void setup_clocks_for_console(void)
+{
+	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart1clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart2clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart3clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart4clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	clrsetbits_le32(&cmper->uart5clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+void enable_basic_clocks(void)
+{
+	u32 *const clk_domains[] = {
+		&cmper->l3clkstctrl,
+		&cmper->l4fwclkstctrl,
+		&cmper->l3sclkstctrl,
+		&cmper->l4lsclkstctrl,
+		&cmwkup->wkclkstctrl,
+		&cmper->emiffwclkctrl,
+		&cmrtc->clkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en[] = {
+		&cmper->l3clkctrl,
+		&cmper->l4lsclkctrl,
+		&cmper->l4fwclkctrl,
+		&cmwkup->wkl4wkclkctrl,
+		&cmper->l3instrclkctrl,
+		&cmper->l4hsclkctrl,
+		&cmwkup->wkgpio0clkctrl,
+		&cmwkup->wkctrlclkctrl,
+		&cmper->timer2clkctrl,
+		&cmper->gpmcclkctrl,
+		&cmper->elmclkctrl,
+		&cmper->mmc0clkctrl,
+		&cmper->mmc1clkctrl,
+		&cmwkup->wkup_i2c0ctrl,
+		&cmper->gpio1clkctrl,
+		&cmper->gpio2clkctrl,
+		&cmper->gpio3clkctrl,
+		&cmper->i2c1clkctrl,
+		&cmper->cpgmac0clkctrl,
+		&cmper->spi0clkctrl,
+		&cmrtc->rtcclkctrl,
+		&cmper->usb0clkctrl,
+		&cmper->emiffwclkctrl,
+		&cmper->emifclkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+	/* Select the Master osc 24 MHZ as Timer2 clock source */
+	writel(0x1, &cmdpll->clktimer2clk);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
new file mode 100644
index 000000000..d0bc2340c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -0,0 +1,112 @@
+/*
+ * clock_am43xx.c
+ *
+ * clocks for AM43XX based boards
+ * Derived from AM33XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
+
+const struct dpll_regs dpll_mpu_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x560,
+	.cm_idlest_dpll		= CM_WKUP + 0x564,
+	.cm_clksel_dpll		= CM_WKUP + 0x56c,
+	.cm_div_m2_dpll		= CM_WKUP + 0x570,
+};
+
+const struct dpll_regs dpll_core_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x520,
+	.cm_idlest_dpll		= CM_WKUP + 0x524,
+	.cm_clksel_dpll		= CM_WKUP + 0x52C,
+	.cm_div_m4_dpll		= CM_WKUP + 0x538,
+	.cm_div_m5_dpll		= CM_WKUP + 0x53C,
+	.cm_div_m6_dpll		= CM_WKUP + 0x540,
+};
+
+const struct dpll_regs dpll_per_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x5E0,
+	.cm_idlest_dpll		= CM_WKUP + 0x5E4,
+	.cm_clksel_dpll		= CM_WKUP + 0x5EC,
+	.cm_div_m2_dpll		= CM_WKUP + 0x5F0,
+};
+
+const struct dpll_regs dpll_ddr_regs = {
+	.cm_clkmode_dpll	= CM_WKUP + 0x5A0,
+	.cm_idlest_dpll		= CM_WKUP + 0x5A4,
+	.cm_clksel_dpll		= CM_WKUP + 0x5AC,
+	.cm_div_m2_dpll		= CM_WKUP + 0x5B0,
+	.cm_div_m4_dpll		= CM_WKUP + 0x5B8,
+};
+
+void setup_clocks_for_console(void)
+{
+	/* Do not add any spl_debug prints in this function */
+	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	/* Enable UART0 */
+	clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+void enable_basic_clocks(void)
+{
+	u32 *const clk_domains[] = {
+		&cmper->l3clkstctrl,
+		&cmper->l3sclkstctrl,
+		&cmper->l4lsclkstctrl,
+		&cmwkup->wkclkstctrl,
+		&cmper->emifclkstctrl,
+		0
+	};
+
+	u32 *const clk_modules_explicit_en[] = {
+		&cmper->l3clkctrl,
+		&cmper->l4lsclkctrl,
+		&cmper->l4fwclkctrl,
+		&cmwkup->wkl4wkclkctrl,
+		&cmper->l3instrclkctrl,
+		&cmper->l4hsclkctrl,
+		&cmwkup->wkgpio0clkctrl,
+		&cmwkup->wkctrlclkctrl,
+		&cmper->timer2clkctrl,
+		&cmper->gpmcclkctrl,
+		&cmper->elmclkctrl,
+		&cmper->mmc0clkctrl,
+		&cmper->mmc1clkctrl,
+		&cmwkup->wkup_i2c0ctrl,
+		&cmper->gpio1clkctrl,
+		&cmper->gpio2clkctrl,
+		&cmper->gpio3clkctrl,
+		&cmper->gpio4clkctrl,
+		&cmper->gpio5clkctrl,
+		&cmper->i2c1clkctrl,
+		&cmper->cpgmac0clkctrl,
+		&cmper->emiffwclkctrl,
+		&cmper->emifclkctrl,
+		&cmper->otfaemifclkctrl,
+		&cmper->qspiclkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+	/* Select the Master osc clk as Timer2 clock source */
+	writel(0x1, &cmdpll->clktimer2clk);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
new file mode 100644
index 000000000..9b5a47b01
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -0,0 +1,404 @@
+/*
+ * clock_ti814x.c
+ *
+ * Clocks for TI814X based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/* PRCM */
+#define PRCM_MOD_EN		0x2
+
+/* CLK_SRC */
+#define OSC_SRC0		0
+#define OSC_SRC1		1
+
+#define L3_OSC_SRC		OSC_SRC0
+
+#define OSC_0_FREQ		20
+
+#define DCO_HS2_MIN		500
+#define DCO_HS2_MAX		1000
+#define DCO_HS1_MIN		1000
+#define DCO_HS1_MAX		2000
+
+#define SELFREQDCO_HS2		0x00000801
+#define SELFREQDCO_HS1		0x00001001
+
+#define MPU_N			0x1
+#define MPU_M			0x3C
+#define MPU_M2			1
+#define MPU_CLKCTRL		0x1
+
+#define L3_N			19
+#define L3_M			880
+#define L3_M2			4
+#define L3_CLKCTRL		0x801
+
+#define DDR_N			19
+#define DDR_M			666
+#define DDR_M2			2
+#define DDR_CLKCTRL		0x801
+
+/* ADPLLJ register values */
+#define ADPLLJ_CLKCTRL_HS2	0x00000801 /* HS2 mode, TINT2 = 1 */
+#define ADPLLJ_CLKCTRL_HS1	0x00001001 /* HS1 mode, TINT2 = 1 */
+#define ADPLLJ_CLKCTRL_CLKDCOLDOEN	(1 << 29)
+#define ADPLLJ_CLKCTRL_IDLE		(1 << 23)
+#define ADPLLJ_CLKCTRL_CLKOUTEN		(1 << 20)
+#define ADPLLJ_CLKCTRL_CLKOUTLDOEN	(1 << 19)
+#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ	(1 << 17)
+#define ADPLLJ_CLKCTRL_LPMODE		(1 << 12)
+#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN	(1 << 11)
+#define ADPLLJ_CLKCTRL_REGM4XEN		(1 << 10)
+#define ADPLLJ_CLKCTRL_TINITZ		(1 << 0)
+#define ADPLLJ_CLKCTRL_CLKDCO		(ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
+					 ADPLLJ_CLKCTRL_CLKOUTEN | \
+					 ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
+					 ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
+
+#define ADPLLJ_STATUS_PHASELOCK		(1 << 10)
+#define ADPLLJ_STATUS_FREQLOCK		(1 << 9)
+#define ADPLLJ_STATUS_PHSFRQLOCK	(ADPLLJ_STATUS_PHASELOCK | \
+					 ADPLLJ_STATUS_FREQLOCK)
+#define ADPLLJ_STATUS_BYPASSACK		(1 << 8)
+#define ADPLLJ_STATUS_BYPASS		(1 << 0)
+#define ADPLLJ_STATUS_BYPASSANDACK	(ADPLLJ_STATUS_BYPASSACK | \
+					 ADPLLJ_STATUS_BYPASS)
+
+#define ADPLLJ_TENABLE_ENB		(1 << 0)
+#define ADPLLJ_TENABLEDIV_ENB		(1 << 0)
+
+#define ADPLLJ_M2NDIV_M2SHIFT		16
+
+#define MPU_PLL_BASE			(PLL_SUBSYS_BASE + 0x048)
+#define L3_PLL_BASE			(PLL_SUBSYS_BASE + 0x110)
+#define DDR_PLL_BASE			(PLL_SUBSYS_BASE + 0x290)
+
+struct ad_pll {
+	unsigned int pwrctrl;
+	unsigned int clkctrl;
+	unsigned int tenable;
+	unsigned int tenablediv;
+	unsigned int m2ndiv;
+	unsigned int mn2div;
+	unsigned int fracdiv;
+	unsigned int bwctrl;
+	unsigned int fracctrl;
+	unsigned int status;
+	unsigned int m3div;
+	unsigned int rampctrl;
+};
+
+#define OSC_SRC_CTRL			(PLL_SUBSYS_BASE + 0x2C0)
+
+#define ENET_CLKCTRL_CMPL		0x30000
+
+#define SATA_PLL_BASE			(CTRL_BASE + 0x0720)
+
+struct sata_pll {
+	unsigned int pllcfg0;
+	unsigned int pllcfg1;
+	unsigned int pllcfg2;
+	unsigned int pllcfg3;
+	unsigned int pllcfg4;
+	unsigned int pllstatus;
+	unsigned int rxstatus;
+	unsigned int txstatus;
+	unsigned int testcfg;
+};
+
+#define SEL_IN_FREQ		(0x1 << 31)
+#define DIGCLRZ			(0x1 << 30)
+#define ENDIGLDO		(0x1 << 4)
+#define APLL_CP_CURR		(0x1 << 3)
+#define ENBGSC_REF		(0x1 << 2)
+#define ENPLLLDO		(0x1 << 1)
+#define ENPLL			(0x1 << 0)
+
+#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
+#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
+#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
+#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
+			ENPLLLDO | ENPLL)
+
+#define PLL_LOCK		(0x1 << 0)
+
+#define ENSATAMODE		(0x1 << 31)
+#define PLLREFSEL		(0x1 << 30)
+#define MDIVINT			(0x4b << 18)
+#define EN_CLKAUX		(0x1 << 5)
+#define EN_CLK125M		(0x1 << 4)
+#define EN_CLK100M		(0x1 << 3)
+#define EN_CLK50M		(0x1 << 2)
+
+#define SATA_PLLCFG1 (ENSATAMODE |	\
+		      PLLREFSEL |	\
+		      MDIVINT |		\
+		      EN_CLKAUX |	\
+		      EN_CLK125M |	\
+		      EN_CLK100M |	\
+		      EN_CLK50M)
+
+#define DIGLDO_EN_CAPLESSMODE	(0x1 << 22)
+#define PLLDO_EN_LDO_STABLE	(0x1 << 11)
+#define PLLDO_EN_BUF_CUR	(0x1 << 7)
+#define PLLDO_EN_LP		(0x1 << 6)
+#define PLLDO_CTRL_TRIM_1_4V	(0x10 << 1)
+
+#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE |	\
+		      PLLDO_EN_LDO_STABLE |	\
+		      PLLDO_EN_BUF_CUR |	\
+		      PLLDO_EN_LP |		\
+		      PLLDO_CTRL_TRIM_1_4V)
+
+const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
+const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
+
+/*
+ * Enable the peripheral clock for required peripherals
+ */
+static void enable_per_clocks(void)
+{
+	/* HSMMC1 */
+	writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
+	while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Ethernet */
+	writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
+	writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
+	while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+		;
+	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
+	while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+		;
+
+	/* RTC clocks */
+	writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
+	writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
+	while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
+		;
+}
+
+/*
+ * select the HS1 or HS2 for DCO Freq
+ * return : CLKCTRL
+ */
+static u32 pll_dco_freq_sel(u32 clkout_dco)
+{
+	if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
+		return SELFREQDCO_HS2;
+	else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
+		return SELFREQDCO_HS1;
+	else
+		return -1;
+}
+
+/*
+ * select the sigma delta config
+ * return: sigma delta val
+ */
+static u32 pll_sigma_delta_val(u32 clkout_dco)
+{
+	u32 sig_val = 0;
+
+	sig_val = (clkout_dco + 225) / 250;
+	sig_val = sig_val << 24;
+
+	return sig_val;
+}
+
+/*
+ * configure individual ADPLLJ
+ */
+static void pll_config(u32 base, u32 n, u32 m, u32 m2,
+		       u32 clkctrl_val, int adpllj)
+{
+	const struct ad_pll *adpll = (struct ad_pll *)base;
+	u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
+	u32 sig_val = 0, hs_mod = 0;
+
+	m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
+	mn2val = m;
+
+	/* calculate clkout_dco */
+	clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
+
+	/* sigma delta & Hs mode selection skip for ADPLLS*/
+	if (adpllj) {
+		sig_val = pll_sigma_delta_val(clkout_dco);
+		hs_mod = pll_dco_freq_sel(clkout_dco);
+	}
+
+	/* by-pass pll */
+	read_clkctrl = readl(&adpll->clkctrl);
+	writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
+	while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
+		!= ADPLLJ_STATUS_BYPASSANDACK)
+		;
+
+	/* clear TINITZ */
+	read_clkctrl = readl(&adpll->clkctrl);
+	writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
+
+	/*
+	 * ref_clk = 20/(n + 1);
+	 * clkout_dco = ref_clk * m;
+	 * clk_out = clkout_dco/m2;
+	*/
+	read_clkctrl = readl(&adpll->clkctrl) &
+			     ~(ADPLLJ_CLKCTRL_LPMODE |
+			     ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
+			     ADPLLJ_CLKCTRL_REGM4XEN);
+	writel(m2nval, &adpll->m2ndiv);
+	writel(mn2val, &adpll->mn2div);
+
+	/* Skip for modena(ADPLLS) */
+	if (adpllj) {
+		writel(sig_val, &adpll->fracdiv);
+		writel((read_clkctrl | hs_mod), &adpll->clkctrl);
+	}
+
+	/* Load M2, N2 dividers of ADPLL */
+	writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
+	writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
+
+	/* Load M, N dividers of ADPLL */
+	writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
+	writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
+
+	/* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
+	read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
+	if (adpllj)
+		writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
+						&adpll->clkctrl);
+
+	/* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
+	read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
+	writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
+
+	/* Wait for phase and freq lock */
+	while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
+	       ADPLLJ_STATUS_PHSFRQLOCK)
+		;
+}
+
+static void unlock_pll_control_mmr(void)
+{
+	/* TRM 2.10.1.4 and 3.2.7-3.2.11 */
+	writel(0x1EDA4C3D, 0x481C5040);
+	writel(0x2FF1AC2B, 0x48140060);
+	writel(0xF757FDC0, 0x48140064);
+	writel(0xE2BC3A6D, 0x48140068);
+	writel(0x1EBF131D, 0x4814006c);
+	writel(0x6F361E05, 0x48140070);
+}
+
+static void mpu_pll_config(void)
+{
+	pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
+}
+
+static void l3_pll_config(void)
+{
+	u32 l3_osc_src, rd_osc_src = 0;
+
+	l3_osc_src = L3_OSC_SRC;
+	rd_osc_src = readl(OSC_SRC_CTRL);
+
+	if (OSC_SRC0 == l3_osc_src)
+		writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
+	else
+		writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
+
+	pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
+}
+
+void ddr_pll_config(unsigned int ddrpll_m)
+{
+	pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
+}
+
+void sata_pll_config(void)
+{
+	/*
+	 * This sequence for configuring the SATA PLL
+	 * resident in the control module is documented
+	 * in TI8148 TRM section 21.3.1
+	 */
+	writel(SATA_PLLCFG1, &spll->pllcfg1);
+	udelay(50);
+
+	writel(SATA_PLLCFG3, &spll->pllcfg3);
+	udelay(50);
+
+	writel(SATA_PLLCFG0_1, &spll->pllcfg0);
+	udelay(50);
+
+	writel(SATA_PLLCFG0_2, &spll->pllcfg0);
+	udelay(50);
+
+	writel(SATA_PLLCFG0_3, &spll->pllcfg0);
+	udelay(50);
+
+	writel(SATA_PLLCFG0_4, &spll->pllcfg0);
+	udelay(50);
+
+	while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
+		;
+}
+
+void enable_dmm_clocks(void)
+{
+	writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
+	writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
+	writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
+	while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
+		;
+	writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
+	while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
+		;
+	while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
+		;
+	writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
+	while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
+		;
+	writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
+	while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
+		;
+}
+
+void setup_clocks_for_console(void)
+{
+	unlock_pll_control_mmr();
+	/* UART0 */
+	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+		;
+}
+/*
+ * Configure the PLL/PRCM for necessary peripherals
+ */
+void prcm_init(void)
+{
+	/* Enable the control module */
+	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
+
+	/* Configure PLLs */
+	mpu_pll_config();
+	l3_pll_config();
+	sata_pll_config();
+
+	/* Enable the required peripherals */
+	enable_per_clocks();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
new file mode 100644
index 000000000..ace4a5afe
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/clock_ti816x.c
@@ -0,0 +1,445 @@
+/*
+ * clock_ti816x.c
+ *
+ * Clocks for TI816X based boards
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * Based on TI-PSP-04.00.02.14 :
+ *
+ * Copyright (C) 2009, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#include <asm/emif.h>
+
+#define CM_PLL_BASE		(CTRL_BASE + 0x0400)
+
+/* Main PLL */
+#define MAIN_N			64
+#define MAIN_P			0x1
+#define MAIN_INTFREQ1		0x8
+#define MAIN_FRACFREQ1		0x800000
+#define MAIN_MDIV1		0x2
+#define MAIN_INTFREQ2		0xE
+#define MAIN_FRACFREQ2		0x0
+#define MAIN_MDIV2		0x1
+#define MAIN_INTFREQ3		0x8
+#define MAIN_FRACFREQ3		0xAAAAB0
+#define MAIN_MDIV3		0x3
+#define MAIN_INTFREQ4		0x9
+#define MAIN_FRACFREQ4		0x55554F
+#define MAIN_MDIV4		0x3
+#define MAIN_INTFREQ5		0x9
+#define MAIN_FRACFREQ5		0x374BC6
+#define MAIN_MDIV5		0xC
+#define MAIN_MDIV6		0x48
+#define MAIN_MDIV7		0x4
+
+/* DDR PLL */
+#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x4
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x3
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */
+#define DDR_N			50
+#define DDR_P			0x1
+#define DDR_MDIV1		0x2
+#define DDR_INTFREQ2		0x9
+#define DDR_FRACFREQ2		0x0
+#define DDR_MDIV2		0x19
+#define DDR_INTFREQ3		0x13
+#define DDR_FRACFREQ3		0x800000
+#define DDR_MDIV3		0x2
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */
+#define DDR_N			59
+#define DDR_P			0x1
+#define DDR_MDIV1		0x2
+#define DDR_INTFREQ2		0x8
+#define DDR_FRACFREQ2		0xD99999
+#define DDR_MDIV2		0x1E
+#define DDR_INTFREQ3		0x8
+#define DDR_FRACFREQ3		0x0
+#define DDR_MDIV3		0x4
+#define DDR_INTFREQ4		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ4		0x0
+#define DDR_MDIV4		0x4
+#define DDR_INTFREQ5		0xE /* Expansion DDR clk */
+#define DDR_FRACFREQ5		0x0
+#define DDR_MDIV5		0x4
+#endif
+
+#define CONTROL_STATUS			(CTRL_BASE + 0x40)
+#define DDR_RCD				(CTRL_BASE + 0x070C)
+#define CM_TIMER1_CLKSEL		(PRCM_BASE + 0x390)
+#define DMM_PAT_BASE_ADDR		(DMM_BASE + 0x420)
+#define CM_ALWON_CUST_EFUSE_CLKCTRL	(PRCM_BASE + 0x1628)
+
+#define INTCPS_SYSCONFIG	0x48200010
+#define CM_SYSCLK10_CLKSEL	0x48180324
+
+struct cm_pll {
+	unsigned int mainpll_ctrl;	/* offset 0x400 */
+	unsigned int mainpll_pwd;
+	unsigned int mainpll_freq1;
+	unsigned int mainpll_div1;
+	unsigned int mainpll_freq2;
+	unsigned int mainpll_div2;
+	unsigned int mainpll_freq3;
+	unsigned int mainpll_div3;
+	unsigned int mainpll_freq4;
+	unsigned int mainpll_div4;
+	unsigned int mainpll_freq5;
+	unsigned int mainpll_div5;
+	unsigned int resv0[1];
+	unsigned int mainpll_div6;
+	unsigned int resv1[1];
+	unsigned int mainpll_div7;
+	unsigned int ddrpll_ctrl;	/* offset 0x440 */
+	unsigned int ddrpll_pwd;
+	unsigned int resv2[1];
+	unsigned int ddrpll_div1;
+	unsigned int ddrpll_freq2;
+	unsigned int ddrpll_div2;
+	unsigned int ddrpll_freq3;
+	unsigned int ddrpll_div3;
+	unsigned int ddrpll_freq4;
+	unsigned int ddrpll_div4;
+	unsigned int ddrpll_freq5;
+	unsigned int ddrpll_div5;
+	unsigned int videopll_ctrl;	/* offset 0x470 */
+	unsigned int videopll_pwd;
+	unsigned int videopll_freq1;
+	unsigned int videopll_div1;
+	unsigned int videopll_freq2;
+	unsigned int videopll_div2;
+	unsigned int videopll_freq3;
+	unsigned int videopll_div3;
+	unsigned int resv3[4];
+	unsigned int audiopll_ctrl;	/* offset 0x4A0 */
+	unsigned int audiopll_pwd;
+	unsigned int resv4[2];
+	unsigned int audiopll_freq2;
+	unsigned int audiopll_div2;
+	unsigned int audiopll_freq3;
+	unsigned int audiopll_div3;
+	unsigned int audiopll_freq4;
+	unsigned int audiopll_div4;
+	unsigned int audiopll_freq5;
+	unsigned int audiopll_div5;
+};
+
+const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
+const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
+const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+void enable_dmm_clocks(void)
+{
+	writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
+	writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
+	writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
+
+	/* Wait for clocks to be active */
+	while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
+		;
+	/* Wait for emif0 to be fully functional, including OCP */
+	while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
+		;
+	/* Wait for emif1 to be fully functional, including OCP */
+	while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
+		;
+
+	writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
+	/* Wait for dmm to be fully functional, including OCP */
+	while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
+		;
+
+	/* Enable Tiled Access */
+	writel(0x80000000, DMM_PAT_BASE_ADDR);
+}
+
+/* assume delay is aprox at least 1us */
+static void ddr_delay(int d)
+{
+	int i;
+
+	/*
+	 * read a control register.
+	 * this is a bit more delay and cannot be optimized by the compiler
+	 * assuming one read takes 200 cycles and A8 is runing 1 GHz
+	 * somewhat conservative setting
+	 */
+	for (i = 0; i < 50*d; i++)
+		readl(CONTROL_STATUS);
+}
+
+static void main_pll_init_ti816x(void)
+{
+	u32 main_pll_ctrl = 0;
+
+	/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFFFFFFFB;
+	main_pll_ctrl |= BIT(2);
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+	/* Enable PLL by setting BIT3 in its ctrl reg */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFFFFFFF7;
+	main_pll_ctrl |= BIT(3);
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+	/* Write the values of N,P in the CTRL reg  */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFF;
+	main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+
+	/* Power up clock1-7 */
+	writel(0x0, &cmpll->mainpll_pwd);
+
+	/* Program the freq and divider values for clock1-7 */
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
+		&cmpll->mainpll_freq1);
+	writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
+		&cmpll->mainpll_freq2);
+	writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
+		&cmpll->mainpll_freq3);
+	writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
+		&cmpll->mainpll_freq4);
+	writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
+
+	writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
+		&cmpll->mainpll_freq5);
+	writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
+
+	writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
+
+	writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
+
+	/* Wait for PLL to lock */
+	while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
+		;
+
+	/* Put the PLL in normal mode, disable bypass */
+	main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
+	main_pll_ctrl &= 0xFFFFFFFB;
+	writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
+}
+
+static void ddr_pll_bypass_ti816x(void)
+{
+	u32 ddr_pll_ctrl = 0;
+
+	/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
+	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+	ddr_pll_ctrl &= 0xFFFFFFFB;
+	ddr_pll_ctrl |= BIT(2);
+	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+}
+
+static void ddr_pll_init_ti816x(void)
+{
+	u32 ddr_pll_ctrl = 0;
+	/* Enable PLL by setting BIT3 in its ctrl reg */
+	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+	ddr_pll_ctrl &= 0xFFFFFFF7;
+	ddr_pll_ctrl |= BIT(3);
+	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+	/* Write the values of N,P in the CTRL reg  */
+	ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
+	ddr_pll_ctrl &= 0xFF;
+	ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
+	writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
+
+	ddr_delay(10);
+
+	/* Power up clock1-5 */
+	writel(0x0, &cmpll->ddrpll_pwd);
+
+	/* Program the freq and divider values for clock1-3 */
+	writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
+	ddr_delay(1);
+	writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
+	writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
+		&cmpll->ddrpll_freq2);
+	writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
+	writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
+	ddr_delay(1);
+	writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
+	ddr_delay(1);
+	writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
+		&cmpll->ddrpll_freq3);
+	ddr_delay(1);
+	writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
+		&cmpll->ddrpll_freq3);
+
+	ddr_delay(5);
+
+	/* Wait for PLL to lock */
+	while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
+		;
+
+	/* Power up RCD */
+	writel(BIT(0), DDR_RCD);
+}
+
+static void peripheral_enable(void)
+{
+	/* Wake-up the l3_slow clock */
+	writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
+
+	/*
+	 * Note on Timers:
+	 * There are 8 timers(0-7) out of which timer 0 is a secure timer.
+	 * Timer 0 mux should not be changed
+	 *
+	 * To access the timer registers we need the to be
+	 * enabled which is what we do in the first step
+	 */
+
+	/* Enable timer1 */
+	writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
+	/* Select timer1 clock to be CLKIN (27MHz) */
+	writel(BIT(1), CM_TIMER1_CLKSEL);
+
+	/* Wait for timer1 to be ON-ACTIVE */
+	while (((readl(&cmalwon->l3slowclkstctrl)
+					& (0x80000<<1))>>20) != 1)
+		;
+	/* Wait for timer1 to be enabled */
+	while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
+		;
+	/* Active posted mode */
+	writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
+	while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
+		;
+	/* Start timer1  */
+	writel(BIT(0), (DM_TIMER1_BASE + 0x38));
+
+	/* eFuse */
+	writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
+	while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
+		;
+
+	/* Enable gpio0 */
+	writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
+	while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
+		;
+	writel((BIT(8)), &cmalwon->gpio0clkctrl);
+
+	/* Enable spi */
+	writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
+	while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Enable i2c0 */
+	writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
+	while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Enable ethernet0 */
+	writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
+	writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
+	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
+
+	/* Enable hsmmc */
+	writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
+	while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
+		;
+}
+
+void setup_clocks_for_console(void)
+{
+	/* Fix ROM code bug - from TI-PSP-04.00.02.14 */
+	writel(0x0, CM_SYSCLK10_CLKSEL);
+
+	ddr_pll_bypass_ti816x();
+
+	/* Enable uart0-2 */
+	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+		;
+	writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
+	while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
+		;
+	writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
+	while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
+		;
+	while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
+		;
+}
+
+void prcm_init(void)
+{
+	/* Enable the control */
+	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
+
+	main_pll_init_ti816x();
+	ddr_pll_init_ti816x();
+
+	/*
+	 * With clk freqs setup to desired values,
+	 * enable the required peripherals
+	 */
+	peripheral_enable();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/config.mk b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/config.mk
new file mode 100644
index 000000000..5294d1670
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= MLO
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
+else
+ALL-y	+= u-boot.img
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/ddr.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/ddr.c
new file mode 100644
index 000000000..9a625c466
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -0,0 +1,266 @@
+/*
+ * DDR Configuration for AM33xx devices.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+/**
+ * Base address for EMIF instances
+ */
+static struct emif_reg_struct *emif_reg[2] = {
+				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
+				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
+
+/**
+ * Base addresses for DDR PHY cmd/data regs
+ */
+static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
+				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
+				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
+
+static struct ddr_data_regs *ddr_data_reg[2] = {
+				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
+				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
+
+/**
+ * Base address for ddr io control instances
+ */
+static struct ddr_cmdtctrl *ioctrl_reg = {
+			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
+
+static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+
+	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
+	if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
+	    ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+	    ((mr & 0xff000000) >> 24) == (mr & 0xff))
+		return mr & 0xff;
+	else
+		return mr;
+}
+
+static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
+}
+
+static void configure_mr(int nr, u32 cs)
+{
+	u32 mr_addr;
+
+	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(nr, cs, LPDDR2_MR10, 0x56);
+
+	set_mr(nr, cs, LPDDR2_MR1, 0x43);
+	set_mr(nr, cs, LPDDR2_MR2, 0x2);
+
+	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+	set_mr(nr, cs, mr_addr, 0x2);
+}
+
+/*
+ * Configure EMIF4D5 registers and MR registers
+ */
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
+{
+	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+	writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+
+	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
+	writel(regs->emif_rd_wr_lvl_rmp_win,
+	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
+	writel(regs->emif_rd_wr_lvl_rmp_ctl,
+	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+	writel(regs->emif_rd_wr_exec_thresh,
+	       &emif_reg[nr]->emif_rd_wr_exec_thresh);
+
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+
+	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+		configure_mr(nr, 0);
+		configure_mr(nr, 1);
+	}
+}
+
+/**
+ * Configure SDRAM
+ */
+void config_sdram(const struct emif_regs *regs, int nr)
+{
+	if (regs->zq_config) {
+		/*
+		 * A value of 0x2800 for the REF CTRL will give us
+		 * about 570us for a delay, which will be long enough
+		 * to configure things.
+		 */
+		writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
+		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+	}
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+}
+
+/**
+ * Set SDRAM timings
+ */
+void set_sdram_timings(const struct emif_regs *regs, int nr)
+{
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
+}
+
+void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+}
+
+/*
+ * Configure EXT PHY registers
+ */
+static void ext_phy_settings(const struct emif_regs *regs, int nr)
+{
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	const u32 *ext_phy_ctrl_const_regs;
+	u32 i = 0;
+	u32 size;
+
+	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base =
+			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+	/*
+	 * external phy 6-24 registers do not change with
+	 * ddr frequency
+	 */
+	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
+
+	if (!size)
+		return;
+
+	for (i = 0; i < size; i++) {
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+	}
+}
+
+/**
+ * Configure DDR PHY
+ */
+void config_ddr_phy(const struct emif_regs *regs, int nr)
+{
+	/*
+	 * disable initialization and refreshes for now until we
+	 * finish programming EMIF regs.
+	 */
+	setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+		     EMIF_REG_INITREF_DIS_MASK);
+
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
+
+	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
+		ext_phy_settings(regs, nr);
+}
+
+/**
+ * Configure DDR CMD control registers
+ */
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
+{
+	if (!cmd)
+		return;
+
+	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
+	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
+
+	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
+	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
+
+	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
+	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
+}
+
+/**
+ * Configure DDR DATA registers
+ */
+void config_ddr_data(const struct ddr_data *data, int nr)
+{
+	int i;
+
+	if (!data)
+		return;
+
+	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
+		writel(data->datardsratio0,
+			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
+		writel(data->datawdsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
+		writel(data->datawiratio0,
+			&(ddr_data_reg[nr]+i)->dt0wiratio0);
+		writel(data->datagiratio0,
+			&(ddr_data_reg[nr]+i)->dt0giratio0);
+		writel(data->datafwsratio0,
+			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
+		writel(data->datawrsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
+	}
+}
+
+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
+{
+	if (!ioregs)
+		return;
+
+	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
+	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
+	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
+	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
+	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
+#ifdef CONFIG_AM43XX
+	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
+	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
+	writel(ioregs->emif_sdram_config_ext,
+	       &ioctrl_reg->emif_sdram_config_ext);
+#endif
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/emif4.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/emif4.c
new file mode 100644
index 000000000..2c67c322c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -0,0 +1,132 @@
+/*
+ * emif4.c
+ *
+ * AM33XX emif4 configuration file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size(
+			(void *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_MAX_RAM_BANK_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_TI81XX
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+				(struct dmm_lisa_map_regs *)DMM_BASE;
+#endif
+#ifndef CONFIG_TI816X
+static struct vtp_reg *vtpreg[2] = {
+				(struct vtp_reg *)VTP0_CTRL_ADDR,
+				(struct vtp_reg *)VTP1_CTRL_ADDR};
+#endif
+#ifdef CONFIG_AM33XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+#endif
+#ifdef CONFIG_AM43XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+static struct cm_device_inst *cm_device =
+				(struct cm_device_inst *)CM_DEVICE_INST;
+#endif
+
+#ifdef CONFIG_TI81XX
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+	enable_dmm_clocks();
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
+}
+#endif
+
+#ifndef CONFIG_TI816X
+static void config_vtp(int nr)
+{
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
+			&vtpreg[nr]->vtp0ctrlreg);
+
+	/* Poll for READY */
+	while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
+			VTP_CTRL_READY)
+		;
+}
+#endif
+
+void __weak ddr_pll_config(unsigned int ddrpll_m)
+{
+}
+
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
+		const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs, int nr)
+{
+	ddr_pll_config(pll);
+#ifndef CONFIG_TI816X
+	config_vtp(nr);
+#endif
+	config_cmd_ctrl(ctrl, nr);
+
+	config_ddr_data(data, nr);
+#ifdef CONFIG_AM33XX
+	config_io_ctrl(ioregs);
+
+	/* Set CKE to be controlled by EMIF/DDR PHY */
+	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+#endif
+#ifdef CONFIG_AM43XX
+	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
+	while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
+		;
+	writel(0x80000000, &ddrctrl->ddrioctrl);
+
+	config_io_ctrl(ioregs);
+
+	/* Set CKE to be controlled by EMIF/DDR PHY */
+	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+#endif
+
+	/* Program EMIF instance */
+	config_ddr_phy(regs, nr);
+	set_sdram_timings(regs, nr);
+	if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
+		config_sdram_emif4d5(regs, nr);
+	else
+		config_sdram(regs, nr);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/mem.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/mem.c
new file mode 100644
index 000000000..56c9e7dbc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/mem.c
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *     Manikandan Pillai <mani.pillai@ti.com>
+ *     Richard Woodruff <r-woodruff2@ti.com>
+ *     Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <command.h>
+
+struct gpmc *gpmc_cfg;
+
+
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+			u32 size)
+{
+	writel(0, &cs->config7);
+	sdelay(1000);
+	/* Delay for settling */
+	writel(gpmc_config[0], &cs->config1);
+	writel(gpmc_config[1], &cs->config2);
+	writel(gpmc_config[2], &cs->config3);
+	writel(gpmc_config[3], &cs->config4);
+	writel(gpmc_config[4], &cs->config5);
+	writel(gpmc_config[5], &cs->config6);
+	/* Enable the config */
+	writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+		(1 << 6)), &cs->config7);
+	sdelay(2000);
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+	/* putting a blanket check on GPMC based on ZeBu for now */
+	gpmc_cfg = (struct gpmc *)GPMC_BASE;
+#if defined(CONFIG_NOR)
+/* configure GPMC for NOR */
+	const u32 gpmc_regs[GPMC_MAX_REG] = {	STNOR_GPMC_CONFIG1,
+						STNOR_GPMC_CONFIG2,
+						STNOR_GPMC_CONFIG3,
+						STNOR_GPMC_CONFIG4,
+						STNOR_GPMC_CONFIG5,
+						STNOR_GPMC_CONFIG6,
+						STNOR_GPMC_CONFIG7
+						};
+	u32 size = GPMC_SIZE_16M;
+	u32 base = CONFIG_SYS_FLASH_BASE;
+#elif defined(CONFIG_NAND)
+/* configure GPMC for NAND */
+	const u32  gpmc_regs[GPMC_MAX_REG] = {	M_NAND_GPMC_CONFIG1,
+						M_NAND_GPMC_CONFIG2,
+						M_NAND_GPMC_CONFIG3,
+						M_NAND_GPMC_CONFIG4,
+						M_NAND_GPMC_CONFIG5,
+						M_NAND_GPMC_CONFIG6,
+						0
+						};
+	u32 size = GPMC_SIZE_256M;
+	u32 base = CONFIG_SYS_NAND_BASE;
+#else
+	const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
+	u32 size = 0;
+	u32 base = 0;
+#endif
+	/* global settings */
+	writel(0x00000008, &gpmc_cfg->sysconfig);
+	writel(0x00000000, &gpmc_cfg->irqstatus);
+	writel(0x00000000, &gpmc_cfg->irqenable);
+#ifdef CONFIG_NOR
+	writel(0x00000200, &gpmc_cfg->config);
+#else
+	writel(0x00000012, &gpmc_cfg->config);
+#endif
+	/*
+	 * Disable the GPMC0 config set by ROM code
+	 */
+	writel(0, &gpmc_cfg->cs[0].config7);
+	sdelay(1000);
+	/* enable chip-select specific configurations */
+	enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/mux.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/mux.c
new file mode 100644
index 000000000..2ded47228
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/mux.c
@@ -0,0 +1,33 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+{
+	int i;
+
+	if (!mod_pin_mux)
+		return;
+
+	for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+		MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/sys_info.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/sys_info.c
new file mode 100644
index 000000000..50eb598ff
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -0,0 +1,178 @@
+/*
+ * sys_info.c
+ *
+ * System information functions
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *      Richard Woodruff <r-woodruff2@ti.com>
+ *      Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <power/tps65910.h>
+
+struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
+
+/**
+ * get_cpu_rev(void) - extract rev info
+ */
+u32 get_cpu_rev(void)
+{
+	u32 id;
+	u32 rev;
+
+	id = readl(DEVICE_ID);
+	rev = (id >> 28) & 0xff;
+
+	return rev;
+}
+
+/**
+ * get_cpu_type(void) - extract cpu info
+ */
+u32 get_cpu_type(void)
+{
+	u32 id = 0;
+	u32 partnum;
+
+	id = readl(DEVICE_ID);
+	partnum = (id >> 12) & 0xffff;
+
+	return partnum;
+}
+
+/**
+ * get_board_rev() - setup to pass kernel board revision information
+ * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ */
+u32 get_board_rev(void)
+{
+	return BOARD_REV_ID;
+}
+
+/**
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+	int mode;
+	mode = readl(&cstat->statusreg) & (DEVICE_MASK);
+	return mode >>= 8;
+}
+
+/**
+ * get_sysboot_value(void) - return SYS_BOOT[4:0]
+ */
+u32 get_sysboot_value(void)
+{
+	int mode;
+	mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
+	return mode;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/**
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	char *cpu_s, *sec_s;
+
+	switch (get_cpu_type()) {
+	case AM335X:
+		cpu_s = "AM335X";
+		break;
+	case TI81XX:
+		cpu_s = "TI81XX";
+		break;
+	default:
+		cpu_s = "Unknown cpu type";
+		break;
+	}
+
+	switch (get_device_type()) {
+	case TST_DEVICE:
+		sec_s = "TST";
+		break;
+	case EMU_DEVICE:
+		sec_s = "EMU";
+		break;
+	case HS_DEVICE:
+		sec_s = "HS";
+		break;
+	case GP_DEVICE:
+		sec_s = "GP";
+		break;
+	default:
+		sec_s = "?";
+	}
+
+	printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev());
+
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_AM33XX
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
+{
+	int sil_rev;
+
+	sil_rev = readl(&cdev->deviceid) >> 28;
+
+	if (sil_rev == 1)
+		/* PG 2.0, efuse may not be set. */
+		return MPUPLL_M_800;
+	else if (sil_rev >= 2) {
+		/* Check what the efuse says our max speed is. */
+		int efuse_arm_mpu_max_freq;
+		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
+		case AM335X_ZCZ_1000:
+			return MPUPLL_M_1000;
+		case AM335X_ZCZ_800:
+			return MPUPLL_M_800;
+		case AM335X_ZCZ_720:
+			return MPUPLL_M_720;
+		case AM335X_ZCZ_600:
+		case AM335X_ZCE_600:
+			return MPUPLL_M_600;
+		case AM335X_ZCZ_300:
+		case AM335X_ZCE_300:
+			return MPUPLL_M_300;
+		}
+	}
+
+	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
+	return MPUPLL_M_720;
+}
+
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
+{
+	/* For PG2.1 and later, we have one set of values. */
+	if (sil_rev >= 2) {
+		switch (frequency) {
+		case MPUPLL_M_1000:
+			return TPS65910_OP_REG_SEL_1_3_2_5;
+		case MPUPLL_M_800:
+			return TPS65910_OP_REG_SEL_1_2_6;
+		case MPUPLL_M_720:
+			return TPS65910_OP_REG_SEL_1_2_0;
+		case MPUPLL_M_600:
+		case MPUPLL_M_300:
+			return TPS65910_OP_REG_SEL_1_1_3;
+		}
+	}
+
+	/* Default to PG1.0/PG2.0 values. */
+	return TPS65910_OP_REG_SEL_1_1_3;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
new file mode 100644
index 000000000..b1c28c944
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} >.sram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/arch_timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/arch_timer.c
new file mode 100644
index 000000000..0588e2bae
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/arch_timer.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int timer_init(void)
+{
+	gd->arch.tbl = 0;
+	gd->arch.tbu = 0;
+
+	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	ulong nowl, nowu;
+
+	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (nowl), "=r" (nowu));
+
+	gd->arch.tbl = nowl;
+	gd->arch.tbu = nowu;
+
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+
+ulong get_timer(ulong base)
+{
+	return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long endtime;
+
+	endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
+			1000UL);
+
+	endtime += get_ticks();
+
+	while (get_ticks() < endtime)
+		;
+}
+
+ulong get_tbclk(void)
+{
+	return gd->arch.timer_rate_hz;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/Makefile
new file mode 100644
index 000000000..0a2e48d04
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2013
+# Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SAMA5D3)	+= sama5d3_devices.o
+obj-y += clock.o
+obj-y += cpu.o
+obj-y += reset.o
+obj-y += timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/clock.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/clock.c
new file mode 100644
index 000000000..1588e0c8e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/clock.c
@@ -0,0 +1,122 @@
+/*
+ * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
+ *
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned long at91_css_to_rate(unsigned long css)
+{
+	switch (css) {
+	case AT91_PMC_MCKR_CSS_SLOW:
+		return CONFIG_SYS_AT91_SLOW_CLOCK;
+	case AT91_PMC_MCKR_CSS_MAIN:
+		return gd->arch.main_clk_rate_hz;
+	case AT91_PMC_MCKR_CSS_PLLA:
+		return gd->arch.plla_rate_hz;
+	}
+
+	return 0;
+}
+
+static u32 at91_pll_rate(u32 freq, u32 reg)
+{
+	unsigned mul, div;
+
+	div = reg & 0xff;
+	mul = (reg >> 18) & 0x7f;
+	if (div && mul) {
+		freq /= div;
+		freq *= mul + 1;
+	} else {
+		freq = 0;
+	}
+
+	return freq;
+}
+
+int at91_clock_init(unsigned long main_clock)
+{
+	unsigned freq, mckr;
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+	unsigned tmp;
+	/*
+	 * When the bootloader initialized the main oscillator correctly,
+	 * there's no problem using the cycle counter.  But if it didn't,
+	 * or when using oscillator bypass mode, we must be told the speed
+	 * of the main clock.
+	 */
+	if (!main_clock) {
+		do {
+			tmp = readl(&pmc->mcfr);
+		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
+		tmp &= AT91_PMC_MCFR_MAINF_MASK;
+		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+	}
+#endif
+	gd->arch.main_clk_rate_hz = main_clock;
+
+	/* report if PLLA is more than mildly overclocked */
+	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+
+	/*
+	 * MCK and CPU derive from one of those primary clocks.
+	 * For now, assume this parentage won't change.
+	 */
+	mckr = readl(&pmc->mckr);
+
+	/* plla divisor by 2 */
+	if (mckr & (1 << 12))
+		gd->arch.plla_rate_hz >>= 1;
+
+	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+	freq = gd->arch.mck_rate_hz;
+
+	/* prescale */
+	freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
+
+	switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
+	case AT91_PMC_MCKR_MDIV_2:
+		gd->arch.mck_rate_hz = freq / 2;
+		break;
+	case AT91_PMC_MCKR_MDIV_3:
+		gd->arch.mck_rate_hz = freq / 3;
+		break;
+	case AT91_PMC_MCKR_MDIV_4:
+		gd->arch.mck_rate_hz = freq / 4;
+		break;
+	default:
+		break;
+	}
+
+	gd->arch.cpu_clk_rate_hz = freq;
+
+	return 0;
+}
+
+void at91_periph_clk_enable(int id)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	if (id > 31)
+		writel(1 << (id - 32), &pmc->pcer1);
+	else
+		writel(1 << id, &pmc->pcer);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/cpu.c
new file mode 100644
index 000000000..2fbf60d54
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/cpu.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_dbu.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
+#include <asm/arch/clk.h>
+
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#endif
+
+int arch_cpu_init(void)
+{
+	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+}
+
+void arch_preboot_os(void)
+{
+	ulong cpiv;
+	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+	cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+	/*
+	 * Disable PITC
+	 * Add 0x1000 to current counter to stop it faster
+	 * without waiting for wrapping back to 0
+	 */
+	writel(cpiv + 0x1000, &pit->mr);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char buf[32];
+
+	printf("CPU: %s\n", get_cpu_name());
+	printf("Crystal frequency: %8s MHz\n",
+	       strmhz(buf, get_main_clk_rate()));
+	printf("CPU clock        : %8s MHz\n",
+	       strmhz(buf, get_cpu_clk_rate()));
+	printf("Master clock     : %8s MHz\n",
+	       strmhz(buf, get_mck_clk_rate()));
+
+	return 0;
+}
+#endif
+
+void enable_caches(void)
+{
+}
+
+unsigned int get_chip_id(void)
+{
+	return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+	return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/reset.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/reset.c
new file mode 100644
index 000000000..b30e79b60
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/reset.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_rstc.h>
+
+/* Reset the cpu by telling the reset controller to do so */
+void reset_cpu(ulong ignored)
+{
+	at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+	writel(AT91_RSTC_KEY
+		| AT91_RSTC_CR_PROCRST	/* Processor Reset */
+		| AT91_RSTC_CR_PERRST	/* Peripheral Reset */
+#ifdef CONFIG_AT91RESET_EXTRST
+		| AT91_RSTC_CR_EXTRST	/* External Reset (assert nRST pin) */
+#endif
+		, &rstc->cr);
+	/* never reached */
+	do { } while (1);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/sama5d3_devices.c
new file mode 100644
index 000000000..78ecfc882
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/sama5d3_devices.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2012-2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sama5d3.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+unsigned int has_emac()
+{
+	return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
+}
+
+unsigned int has_gmac()
+{
+	return !cpu_is_sama5d31();
+}
+
+unsigned int has_lcdc()
+{
+	return !cpu_is_sama5d35();
+}
+
+char *get_cpu_name()
+{
+	unsigned int extension_id = get_extension_chip_id();
+
+	if (cpu_is_sama5d3())
+		switch (extension_id) {
+		case ARCH_EXID_SAMA5D31:
+			return "SAMA5D31";
+		case ARCH_EXID_SAMA5D33:
+			return "SAMA5D33";
+		case ARCH_EXID_SAMA5D34:
+			return "SAMA5D34";
+		case ARCH_EXID_SAMA5D35:
+			return "SAMA5D35";
+		case ARCH_EXID_SAMA5D36:
+			return "SAMA5D36";
+		default:
+			return "Unknown CPU type";
+		}
+	else
+		return "Unknown CPU type";
+}
+
+void at91_serial0_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTD, 18, 1);	/* TXD0 */
+	at91_set_a_periph(AT91_PIO_PORTD, 17, 0);	/* RXD0 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART0);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTB, 29, 1);	/* TXD1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 28, 0);	/* RXD1 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART1);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_set_b_periph(AT91_PIO_PORTE, 26, 1);	/* TXD2 */
+	at91_set_b_periph(AT91_PIO_PORTE, 25, 0);	/* RXD2 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART2);
+}
+
+void at91_seriald_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTB, 31, 1);	/* DTXD */
+	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* DRXD */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_DBGU);
+}
+
+#if defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_set_a_periph(AT91_PIO_PORTD, 10, 0);       /* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTD, 11, 0);       /* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTD, 12, 0);       /* SPI0_SPCK */
+
+	if (cs_mask & (1 << 0))
+		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
+	if (cs_mask & (1 << 1))
+		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
+	if (cs_mask & (1 << 2))
+		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
+	if (cs_mask & (1 << 3))
+		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void at91_mci_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTD, 0, 0);	/* MCI0 CMD */
+	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);	/* MCI0 DA0 */
+	at91_set_a_periph(AT91_PIO_PORTD, 2, 0);	/* MCI0 DA1 */
+	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);        /* MCI0 DA2 */
+	at91_set_a_periph(AT91_PIO_PORTD, 4, 0);        /* MCI0 DA3 */
+#ifdef CONFIG_ATMEL_MCI_8BIT
+	at91_set_a_periph(AT91_PIO_PORTD, 5, 0);        /* MCI0 DA4 */
+	at91_set_a_periph(AT91_PIO_PORTD, 6, 0);        /* MCI0 DA5 */
+	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);        /* MCI0 DA6 */
+	at91_set_a_periph(AT91_PIO_PORTD, 8, 0);        /* MCI0 DA7 */
+#endif
+	at91_set_a_periph(AT91_PIO_PORTD, 9, 0);        /* MCI0 CLK */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* ETXCK_EREFCK */
+	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* ERXDV */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* ERX0 */
+	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* ERX1 */
+	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* ERXER */
+	at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* ETXEN */
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* ETX0 */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* ETX1 */
+	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* EMDIO */
+	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* EMDC */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+}
+
+void at91_gmac_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* GTX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* GTX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* GTX2 */
+	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* GTX3 */
+	at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* GRX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);	/* GRX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* GRX2 */
+	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* GRX3 */
+	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* GTXCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* GTXEN */
+
+	at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* GRXCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* GRXER */
+
+	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* GMDC */
+	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* GMDIO */
+	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* G125CK */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
+#endif
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTA, 24, 0);	/* LCDPWM */
+	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
+	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 29, 0);	/* LCDDEN */
+
+	/* The lower 16-bit of LCD only available on Port A */
+	at91_set_a_periph(AT91_PIO_PORTA,  0, 0);	/* LCDD0 */
+	at91_set_a_periph(AT91_PIO_PORTA,  1, 0);	/* LCDD1 */
+	at91_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
+	at91_set_a_periph(AT91_PIO_PORTA,  8, 0);	/* LCDD8 */
+	at91_set_a_periph(AT91_PIO_PORTA,  9, 0);	/* LCDD9 */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+void at91_udp_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable UPLL clock */
+	writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+	/* Enable UDPHS clock */
+	at91_periph_clk_enable(ATMEL_ID_UDPHS);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/timer.c
new file mode 100644
index 000000000..e3ebfe0c5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/at91/timer.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <div64.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * We're using the SAMA5D3x PITC in 32 bit mode, by
+ * setting the 20 bit counter period to its maximum (0xfffff).
+ * (See the relevant data sheets to understand that this really works)
+ *
+ * We do also mimic the typical powerpc way of incrementing
+ * two 32 bit registers called tbl and tbu.
+ *
+ * Those registers increment at 1/16 the main clock rate.
+ */
+
+#define TIMER_LOAD_VAL	0xfffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, gd->arch.timer_rate_hz);
+
+	return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+	usec *= gd->arch.timer_rate_hz;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+/*
+ * Use the PITC in full 32 bit incrementing mode
+ */
+int timer_init(void)
+{
+	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+	/* Enable PITC Clock */
+	at91_periph_clk_enable(ATMEL_ID_PIT);
+
+	/* Enable PITC */
+	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
+
+	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+	gd->arch.tbu = 0;
+	gd->arch.tbl = 0;
+
+	return 0;
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+	ulong now = readl(&pit->piir);
+
+	/* increment tbu if tbl has rolled over */
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long start;
+	ulong tmo;
+
+	start = get_ticks();		/* get current timestamp */
+	tmo = usec_to_tick(usec);	/* convert usecs to ticks */
+	while ((get_ticks() - start) < tmo)
+		;			/* loop till time has passed */
+}
+
+/*
+ * get_timer(base) can be used to check for timeouts or
+ * to measure elasped time relative to an event:
+ *
+ * ulong start_time = get_timer(0) sets start_time to the current
+ * time value.
+ * get_timer(start_time) returns the time elapsed since then.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
+ulong get_timer(ulong base)
+{
+	return tick_to_time(get_ticks()) - base;
+}
+
+/*
+ * Return the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return gd->arch.timer_rate_hz;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/Makefile
new file mode 100644
index 000000000..98f5aa59c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= reset.o
+obj-y	+= clk-core.o
+obj-y	+= clk-bcm281xx.o
+obj-y	+= clk-sdio.o
+obj-y	+= clk-bsc.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
new file mode 100644
index 000000000..bc8a170b4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
@@ -0,0 +1,523 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+/*
+ *
+ * bcm281xx-specific clock tables
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLOCK_1K		1000
+#define CLOCK_1M		(CLOCK_1K * 1000)
+
+/* declare a reference clock */
+#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
+static struct refclk clk_name = { \
+	.clk    =       { \
+		.name   =       #clk_name, \
+		.parent =       clk_parent, \
+		.rate   =       clk_rate, \
+		.div    =       clk_div, \
+		.ops    =       &ref_clk_ops, \
+	}, \
+}
+
+/*
+ * Reference clocks
+ */
+
+/* Declare a list of reference clocks */
+DECLARE_REF_CLK(ref_crystal,	0,		26  * CLOCK_1M,	1);
+DECLARE_REF_CLK(var_96m,	0,		96  * CLOCK_1M,	1);
+DECLARE_REF_CLK(ref_96m,	0,		96  * CLOCK_1M,	1);
+DECLARE_REF_CLK(ref_312m,	0,		312 * CLOCK_1M,	0);
+DECLARE_REF_CLK(ref_104m,	&ref_312m.clk,	104 * CLOCK_1M,	3);
+DECLARE_REF_CLK(ref_52m,	&ref_104m.clk,	52  * CLOCK_1M,	2);
+DECLARE_REF_CLK(ref_13m,	&ref_52m.clk,	13  * CLOCK_1M,	4);
+DECLARE_REF_CLK(var_312m,	0,		312 * CLOCK_1M,	0);
+DECLARE_REF_CLK(var_104m,	&var_312m.clk,	104 * CLOCK_1M,	3);
+DECLARE_REF_CLK(var_52m,	&var_104m.clk,	52  * CLOCK_1M,	2);
+DECLARE_REF_CLK(var_13m,	&var_52m.clk,	13  * CLOCK_1M,	4);
+
+struct refclk_lkup {
+	struct refclk *procclk;
+	const char *name;
+};
+
+/* Lookup table for string to clk tranlation */
+#define MKSTR(x) {&x, #x}
+static struct refclk_lkup refclk_str_tbl[] = {
+	MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
+	MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
+	MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
+	MKSTR(var_52m), MKSTR(var_13m),
+};
+
+int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
+
+/* convert ref clock string to clock structure pointer */
+struct refclk *refclk_str_to_clk(const char *name)
+{
+	int i;
+	struct refclk_lkup *tblp = refclk_str_tbl;
+	for (i = 0; i < refclk_entries; i++, tblp++) {
+		if (!(strcmp(name, tblp->name)))
+			return tblp->procclk;
+	}
+	return NULL;
+}
+
+/* frequency tables indexed by freq_id */
+unsigned long master_axi_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	208 * CLOCK_1M,
+	312 * CLOCK_1M,
+	312 * CLOCK_1M
+};
+
+unsigned long master_ahb_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M,
+	104 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M
+};
+
+unsigned long slave_axi_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M
+};
+
+unsigned long slave_apb_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	26 * CLOCK_1M,
+	39 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M
+};
+
+static struct bus_clk_data bsc1_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc2_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc3_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
+};
+
+/* * Master CCU clocks */
+static struct peri_clk_data sdio1_data = {
+	.gate		= HW_SW_GATE(0x0358, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a28, 0, 3),
+	.div		= DIVIDER(0x0a28, 4, 14),
+	.trig		= TRIGGER(0x0afc, 9),
+};
+
+static struct peri_clk_data sdio2_data = {
+	.gate		= HW_SW_GATE(0x035c, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a2c, 0, 3),
+	.div		= DIVIDER(0x0a2c, 4, 14),
+	.trig		= TRIGGER(0x0afc, 10),
+};
+
+static struct peri_clk_data sdio3_data = {
+	.gate		= HW_SW_GATE(0x0364, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a34, 0, 3),
+	.div		= DIVIDER(0x0a34, 4, 14),
+	.trig		= TRIGGER(0x0afc, 12),
+};
+
+static struct peri_clk_data sdio4_data = {
+	.gate		= HW_SW_GATE(0x0360, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a30, 0, 3),
+	.div		= DIVIDER(0x0a30, 4, 14),
+	.trig		= TRIGGER(0x0afc, 11),
+};
+
+static struct peri_clk_data sdio1_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0358, 20, 4),
+};
+
+static struct peri_clk_data sdio2_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x035c, 20, 4),
+};
+
+static struct peri_clk_data sdio3_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0364, 20, 4),
+};
+
+static struct peri_clk_data sdio4_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0360, 20, 4),
+};
+
+static struct bus_clk_data sdio1_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio2_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio3_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio4_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
+};
+
+/* * Slave CCU clocks */
+static struct peri_clk_data bsc1_data = {
+	.gate		= HW_SW_GATE(0x0458, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a64, 0, 3),
+	.trig		= TRIGGER(0x0afc, 23),
+};
+
+static struct peri_clk_data bsc2_data = {
+	.gate		= HW_SW_GATE(0x045c, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a68, 0, 3),
+	.trig		= TRIGGER(0x0afc, 24),
+};
+
+static struct peri_clk_data bsc3_data = {
+	.gate		= HW_SW_GATE(0x0484, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a84, 0, 3),
+	.trig		= TRIGGER(0x0b00, 2),
+};
+
+/*
+ * CCU clocks
+ */
+
+static struct ccu_clock kpm_ccu_clk = {
+	.clk = {
+		.name = "kpm_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 1,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = master_axi_freq_tbl,
+};
+
+static struct ccu_clock kps_ccu_clk = {
+	.clk = {
+		.name = "kps_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 2,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.policy0_mask2_offset = 0x00000048,
+	.policy1_mask2_offset = 0x0000004c,
+	.policy2_mask2_offset = 0x00000050,
+	.policy3_mask2_offset = 0x00000054,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = slave_axi_freq_tbl,
+};
+
+/*
+ * Bus clocks
+ */
+
+/* KPM bus clocks */
+static struct bus_clock sdio1_ahb_clk = {
+	.clk = {
+		.name = "sdio1_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio1_ahb_data,
+};
+
+static struct bus_clock sdio2_ahb_clk = {
+	.clk = {
+		.name = "sdio2_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio2_ahb_data,
+};
+
+static struct bus_clock sdio3_ahb_clk = {
+	.clk = {
+		.name = "sdio3_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio3_ahb_data,
+};
+
+static struct bus_clock sdio4_ahb_clk = {
+	.clk = {
+		.name = "sdio4_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio4_ahb_data,
+};
+
+static struct bus_clock bsc1_apb_clk = {
+	.clk = {
+		.name = "bsc1_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc1_apb_data,
+};
+
+static struct bus_clock bsc2_apb_clk = {
+	.clk = {
+		.name = "bsc2_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+		},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc2_apb_data,
+};
+
+static struct bus_clock bsc3_apb_clk = {
+	.clk = {
+		.name = "bsc3_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+		},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc3_apb_data,
+};
+
+/* KPM peripheral */
+static struct peri_clock sdio1_clk = {
+	.clk = {
+		.name = "sdio1_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio1_data,
+};
+
+static struct peri_clock sdio2_clk = {
+	.clk = {
+		.name = "sdio2_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio2_data,
+};
+
+static struct peri_clock sdio3_clk = {
+	.clk = {
+		.name = "sdio3_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio3_data,
+};
+
+static struct peri_clock sdio4_clk = {
+	.clk = {
+		.name = "sdio4_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio4_data,
+};
+
+static struct peri_clock sdio1_sleep_clk = {
+	.clk = {
+		.name = "sdio1_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio1_sleep_data,
+};
+
+static struct peri_clock sdio2_sleep_clk = {
+	.clk = {
+		.name = "sdio2_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio2_sleep_data,
+};
+
+static struct peri_clock sdio3_sleep_clk = {
+	.clk = {
+		.name = "sdio3_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio3_sleep_data,
+};
+
+static struct peri_clock sdio4_sleep_clk = {
+	.clk = {
+		.name = "sdio4_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio4_sleep_data,
+};
+
+/* KPS peripheral clock */
+static struct peri_clock bsc1_clk = {
+	.clk = {
+		.name = "bsc1_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc1_data,
+};
+
+static struct peri_clock bsc2_clk = {
+	.clk = {
+		.name = "bsc2_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc2_data,
+};
+
+static struct peri_clock bsc3_clk = {
+	.clk = {
+		.name = "bsc3_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc3_data,
+};
+
+/* public table for registering clocks */
+struct clk_lookup arch_clk_tbl[] = {
+	/* Peripheral clocks */
+	CLK_LK(sdio1),
+	CLK_LK(sdio2),
+	CLK_LK(sdio3),
+	CLK_LK(sdio4),
+	CLK_LK(sdio1_sleep),
+	CLK_LK(sdio2_sleep),
+	CLK_LK(sdio3_sleep),
+	CLK_LK(sdio4_sleep),
+	CLK_LK(bsc1),
+	CLK_LK(bsc2),
+	CLK_LK(bsc3),
+	/* Bus clocks */
+	CLK_LK(sdio1_ahb),
+	CLK_LK(sdio2_ahb),
+	CLK_LK(sdio3_ahb),
+	CLK_LK(sdio4_ahb),
+	CLK_LK(bsc1_apb),
+	CLK_LK(bsc2_apb),
+	CLK_LK(bsc3_apb),
+};
+
+/* public array size */
+unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c
new file mode 100644
index 000000000..ba55d0aeb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for a BSC/I2C port */
+int clk_bsc_enable(void *base)
+{
+	int ret;
+	char *bscstr, *apbstr;
+
+	switch ((u32) base) {
+	case PMU_BSC_BASE_ADDR:
+		/* PMU clock is always enabled */
+		return 0;
+	case BSC1_BASE_ADDR:
+		bscstr = "bsc1_clk";
+		apbstr = "bsc1_apb_clk";
+		break;
+	case BSC2_BASE_ADDR:
+		bscstr = "bsc2_clk";
+		apbstr = "bsc2_apb_clk";
+		break;
+	case BSC3_BASE_ADDR:
+		bscstr = "bsc3_clk";
+		apbstr = "bsc3_apb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	/* Note that the bus clock must be enabled first */
+
+	ret = clk_get_and_enable(apbstr);
+	if (ret)
+		return ret;
+
+	ret = clk_get_and_enable(bscstr);
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-core.c
new file mode 100644
index 000000000..d4425835a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-core.c
@@ -0,0 +1,513 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+/*
+ *
+ * bcm281xx architecture clock framework
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <bitfield.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLK_WR_ACCESS_PASSWORD	0x00a5a501
+#define WR_ACCESS_OFFSET	0	/* common to all clock blocks */
+#define POLICY_CTL_GO		1	/* Load and refresh policy masks */
+#define POLICY_CTL_GO_ATL	4	/* Active Load */
+
+/* Helper function */
+int clk_get_and_enable(char *clkstr)
+{
+	int ret = 0;
+	struct clk *c;
+
+	debug("%s: %s\n", __func__, clkstr);
+
+	c = clk_get(clkstr);
+	if (c) {
+		ret = clk_enable(c);
+		if (ret)
+			return ret;
+	} else {
+		printf("%s: Couldn't find %s\n", __func__, clkstr);
+		return -EINVAL;
+	}
+	return ret;
+}
+
+/*
+ * Poll a register in a CCU's address space, returning when the
+ * specified bit in that register's value is set (or clear).  Delay
+ * a microsecond after each read of the register.  Returns true if
+ * successful, or false if we gave up trying.
+ *
+ * Caller must ensure the CCU lock is held.
+ */
+#define CLK_GATE_DELAY_USEC 2000
+static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
+{
+	unsigned int tries;
+	u32 bit_mask = 1 << bit;
+
+	for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
+		u32 val;
+		bool bit_val;
+
+		val = readl(base + offset);
+		bit_val = (val & bit_mask) ? 1 : 0;
+		if (bit_val == want)
+			return 0;	/* success */
+		udelay(1);
+	}
+
+	debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
+	      __func__, base + offset, bit, want);
+
+	return -ETIMEDOUT;
+}
+
+/* Enable a peripheral clock */
+static int peri_clk_enable(struct clk *c, int enable)
+{
+	int ret = 0;
+	u32 reg;
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	struct bcm_clk_gate *gate = &cd->gate;
+	void *base = (void *)c->ccu_clk_mgr_base;
+
+
+	debug("%s: %s\n", __func__, c->name);
+
+	clk_get_rate(c);	/* Make sure rate and sel are filled in */
+
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	if (enable) {
+		debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
+		      __func__, c->name, c->rate, c->div, c->sel,
+		      c->parent->rate);
+
+		/*
+		 * clkgate - only software controllable gates are
+		 * supported by u-boot which includes all clocks
+		 * that matter. This avoids bringing in a lot of extra
+		 * complexity as done in the kernel framework.
+		 */
+		if (gate_exists(gate)) {
+			reg = readl(base + cd->gate.offset);
+			reg |= (1 << cd->gate.en_bit);
+			writel(reg, base + cd->gate.offset);
+		}
+
+		/* div and pll select */
+		if (divider_exists(&cd->div)) {
+			reg = readl(base + cd->div.offset);
+			bitfield_replace(reg, cd->div.shift, cd->div.width,
+					 c->div - 1);
+			writel(reg, base + cd->div.offset);
+		}
+
+		/* frequency selector */
+		if (selector_exists(&cd->sel)) {
+			reg = readl(base + cd->sel.offset);
+			bitfield_replace(reg, cd->sel.shift, cd->sel.width,
+					 c->sel);
+			writel(reg, base + cd->sel.offset);
+		}
+
+		/* trigger */
+		if (trigger_exists(&cd->trig)) {
+			writel((1 << cd->trig.bit), base + cd->trig.offset);
+
+			/* wait for trigger status bit to go to 0 */
+			ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
+			if (ret)
+				return ret;
+		}
+
+		/* wait for running (status_bit = 1) */
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
+		if (ret)
+			return ret;
+	} else {
+		debug("%s disable clock %s\n", __func__, c->name);
+
+		/* clkgate */
+		reg = readl(base + cd->gate.offset);
+		reg &= ~(1 << cd->gate.en_bit);
+		writel(reg, base + cd->gate.offset);
+
+		/* wait for stop (status_bit = 0) */
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
+	}
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Set the rate of a peripheral clock */
+static int peri_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret = 0;
+	int i;
+	unsigned long diff;
+	unsigned long new_rate = 0, div = 1;
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	const char **clock;
+
+	debug("%s: %s\n", __func__, c->name);
+	diff = rate;
+
+	i = 0;
+	for (clock = cd->clocks; *clock; clock++, i++) {
+		struct refclk *ref = refclk_str_to_clk(*clock);
+		if (!ref) {
+			printf("%s: Lookup of %s failed\n", __func__, *clock);
+			return -EINVAL;
+		}
+
+		/* round to the new rate */
+		div = ref->clk.rate / rate;
+		if (div == 0)
+			div = 1;
+
+		new_rate = ref->clk.rate / div;
+
+		/* get the min diff */
+		if (abs(new_rate - rate) < diff) {
+			diff = abs(new_rate - rate);
+			c->sel = i;
+			c->parent = &ref->clk;
+			c->rate = new_rate;
+			c->div = div;
+		}
+	}
+
+	debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
+	      c->name, c->rate, c->div, c->sel, c->parent->rate);
+	return ret;
+}
+
+/* Get the rate of a peripheral clock */
+static unsigned long peri_clk_get_rate(struct clk *c)
+{
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int div = 1;
+	const char **clock;
+	struct refclk *ref;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (selector_exists(&cd->sel)) {
+		reg = readl(base + cd->sel.offset);
+		c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
+	} else {
+		/*
+		 * For peri clocks that don't have a selector, the single
+		 * reference clock will always exist at index 0.
+		 */
+		c->sel = 0;
+	}
+
+	if (divider_exists(&cd->div)) {
+		reg = readl(base + cd->div.offset);
+		div = bitfield_extract(reg, cd->div.shift, cd->div.width);
+		div += 1;
+	}
+
+	clock = cd->clocks;
+	ref = refclk_str_to_clk(clock[c->sel]);
+	if (!ref) {
+		printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
+		return 0;
+	}
+
+	c->parent = &ref->clk;
+	c->div = div;
+	c->rate = c->parent->rate / c->div;
+	debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
+	      c->parent->rate, div, c->sel, c->rate);
+
+	return c->rate;
+}
+
+/* Peripheral clock operations */
+struct clk_ops peri_clk_ops = {
+	.enable = peri_clk_enable,
+	.set_rate = peri_clk_set_rate,
+	.get_rate = peri_clk_get_rate,
+};
+
+/* Enable a CCU clock */
+static int ccu_clk_enable(struct clk *c, int enable)
+{
+	struct ccu_clock *ccu_clk = to_ccu_clk(c);
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int ret = 0;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!enable)
+		return -EINVAL;	/* CCU clock cannot shutdown */
+
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	/* config enable for policy engine */
+	writel(1, base + ccu_clk->lvm_en_offset);
+
+	/* wait for bit to go to 0 */
+	ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
+	if (ret)
+		return ret;
+
+	/* freq ID */
+	if (!ccu_clk->freq_bit_shift)
+		ccu_clk->freq_bit_shift = 8;
+
+	/* Set frequency id for each of the 4 policies */
+	reg = ccu_clk->freq_id |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
+	writel(reg, base + ccu_clk->policy_freq_offset);
+
+	/* enable all clock mask */
+	writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
+
+	if (ccu_clk->num_policy_masks == 2) {
+		writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
+	}
+
+	/* start policy engine */
+	reg = readl(base + ccu_clk->policy_ctl_offset);
+	reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
+	writel(reg, base + ccu_clk->policy_ctl_offset);
+
+	/* wait till started */
+	ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
+	if (ret)
+		return ret;
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Get the CCU clock rate */
+static unsigned long ccu_clk_get_rate(struct clk *c)
+{
+	struct ccu_clock *ccu_clk = to_ccu_clk(c);
+	debug("%s: %s\n", __func__, c->name);
+	c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
+	return c->rate;
+}
+
+/* CCU clock operations */
+struct clk_ops ccu_clk_ops = {
+	.enable = ccu_clk_enable,
+	.get_rate = ccu_clk_get_rate,
+};
+
+/* Enable a bus clock */
+static int bus_clk_enable(struct clk *c, int enable)
+{
+	struct bus_clock *bus_clk = to_bus_clk(c);
+	struct bus_clk_data *cd = bus_clk->data;
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int ret = 0;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	/* enable gating */
+	reg = readl(base + cd->gate.offset);
+	if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
+		debug("%s already %s\n", c->name,
+		      enable ? "enabled" : "disabled");
+	else {
+		int want = (enable) ? 1 : 0;
+		reg |= (1 << cd->gate.hw_sw_sel_bit);
+
+		if (enable)
+			reg |= (1 << cd->gate.en_bit);
+		else
+			reg &= ~(1 << cd->gate.en_bit);
+
+		writel(reg, base + cd->gate.offset);
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
+			       want);
+		if (ret)
+			return ret;
+	}
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Get the rate of a bus clock */
+static unsigned long bus_clk_get_rate(struct clk *c)
+{
+	struct bus_clock *bus_clk = to_bus_clk(c);
+	struct ccu_clock *ccu_clk;
+
+	debug("%s: %s\n", __func__, c->name);
+	ccu_clk = to_ccu_clk(c->parent);
+
+	c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
+	c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
+	return c->rate;
+}
+
+/* Bus clock operations */
+struct clk_ops bus_clk_ops = {
+	.enable = bus_clk_enable,
+	.get_rate = bus_clk_get_rate,
+};
+
+/* Enable a reference clock */
+static int ref_clk_enable(struct clk *c, int enable)
+{
+	debug("%s: %s\n", __func__, c->name);
+	return 0;
+}
+
+/* Reference clock operations */
+struct clk_ops ref_clk_ops = {
+	.enable = ref_clk_enable,
+};
+
+/*
+ * clk.h implementation follows
+ */
+
+/* Initialize the clock framework */
+int clk_init(void)
+{
+	debug("%s:\n", __func__);
+	return 0;
+}
+
+/* Get a clock handle, give a name string */
+struct clk *clk_get(const char *con_id)
+{
+	int i;
+	struct clk_lookup *clk_tblp;
+
+	debug("%s: %s\n", __func__, con_id);
+
+	clk_tblp = arch_clk_tbl;
+	for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
+		if (clk_tblp->con_id) {
+			if (!con_id || strcmp(clk_tblp->con_id, con_id))
+				continue;
+			return clk_tblp->clk;
+		}
+	}
+	return NULL;
+}
+
+/* Enable a clock */
+int clk_enable(struct clk *c)
+{
+	int ret = 0;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!c->ops || !c->ops->enable)
+		return -1;
+
+	/* enable parent clock first */
+	if (c->parent)
+		ret = clk_enable(c->parent);
+
+	if (ret)
+		return ret;
+
+	if (!c->use_cnt) {
+		c->use_cnt++;
+		ret = c->ops->enable(c, 1);
+	}
+
+	return ret;
+}
+
+/* Disable a clock */
+void clk_disable(struct clk *c)
+{
+	debug("%s: %s\n", __func__, c->name);
+	if (!c->ops || !c->ops->enable)
+		return;
+
+	if (c->use_cnt) {
+		c->use_cnt--;
+		c->ops->enable(c, 0);
+	}
+
+	/* disable parent */
+	if (c->parent)
+		clk_disable(c->parent);
+}
+
+/* Get the clock rate */
+unsigned long clk_get_rate(struct clk *c)
+{
+	unsigned long rate;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!c || !c->ops || !c->ops->get_rate)
+		return 0;
+
+	rate = c->ops->get_rate(c);
+	debug("%s: rate = %ld\n", __func__, rate);
+	return rate;
+}
+
+/* Set the clock rate */
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret;
+
+	debug("%s: %s rate=%ld\n", __func__, c->name, rate);
+	if (!c || !c->ops || !c->ops->set_rate)
+		return -EINVAL;
+
+	if (c->use_cnt)
+		return -EINVAL;
+
+	ret = c->ops->set_rate(c, rate);
+
+	return ret;
+}
+
+/* Not required for this arch */
+/*
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+*/
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-core.h b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-core.h
new file mode 100644
index 000000000..882a29779
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-core.h
@@ -0,0 +1,495 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <linux/stddef.h>
+
+#ifdef CONFIG_CLK_DEBUG
+#undef writel
+#undef readl
+static inline void writel(u32 val, void *addr)
+{
+	printf("Write [0x%p] = 0x%08x\n", addr, val);
+	*(u32 *)addr = val;
+}
+
+static inline u32 readl(void *addr)
+{
+	u32 val = *(u32 *)addr;
+	printf("Read  [0x%p] = 0x%08x\n", addr, val);
+	return val;
+}
+#endif
+
+struct clk;
+
+struct clk_lookup {
+	const char *dev_id;
+	const char *con_id;
+	struct clk *clk;
+};
+
+extern struct clk_lookup arch_clk_tbl[];
+extern unsigned int arch_clk_tbl_array_size;
+
+/**
+ * struct clk_ops - standard clock operations
+ * @enable: enable/disable clock, see clk_enable() and clk_disable()
+ * @set_rate: set the clock rate, see clk_set_rate().
+ * @get_rate: get the clock rate, see clk_get_rate().
+ * @round_rate: round a given clock rate, see clk_round_rate().
+ * @set_parent: set the clock's parent, see clk_set_parent().
+ *
+ * Group the common clock implementations together so that we
+ * don't have to keep setting the same fiels again. We leave
+ * enable in struct clk.
+ *
+ */
+struct clk_ops {
+	int (*enable) (struct clk *c, int enable);
+	int (*set_rate) (struct clk *c, unsigned long rate);
+	unsigned long (*get_rate) (struct clk *c);
+	unsigned long (*round_rate) (struct clk *c, unsigned long rate);
+	int (*set_parent) (struct clk *c, struct clk *parent);
+};
+
+struct clk {
+	struct clk *parent;
+	const char *name;
+	int use_cnt;
+	unsigned long rate;	/* in HZ */
+
+	/* programmable divider. 0 means fixed ratio to parent clock */
+	unsigned long div;
+
+	struct clk_src *src;
+	struct clk_ops *ops;
+
+	unsigned long ccu_clk_mgr_base;
+	int sel;
+};
+
+struct refclk *refclk_str_to_clk(const char *name);
+
+#define U8_MAX	((u8)~0U)
+#define U32_MAX	((u32)~0U)
+#define U64_MAX	((u64)~0U)
+
+/* The common clock framework uses u8 to represent a parent index */
+#define PARENT_COUNT_MAX	((u32)U8_MAX)
+
+#define BAD_CLK_INDEX		U8_MAX	/* Can't ever be valid */
+#define BAD_CLK_NAME		((const char *)-1)
+
+#define BAD_SCALED_DIV_VALUE	U64_MAX
+
+/*
+ * Utility macros for object flag management.  If possible, flags
+ * should be defined such that 0 is the desired default value.
+ */
+#define FLAG(type, flag)		BCM_CLK_ ## type ## _FLAGS_ ## flag
+#define FLAG_SET(obj, type, flag)	((obj)->flags |= FLAG(type, flag))
+#define FLAG_CLEAR(obj, type, flag)	((obj)->flags &= ~(FLAG(type, flag)))
+#define FLAG_FLIP(obj, type, flag)	((obj)->flags ^= FLAG(type, flag))
+#define FLAG_TEST(obj, type, flag)	(!!((obj)->flags & FLAG(type, flag)))
+
+/* Clock field state tests */
+
+#define gate_exists(gate)		FLAG_TEST(gate, GATE, EXISTS)
+#define gate_is_enabled(gate)		FLAG_TEST(gate, GATE, ENABLED)
+#define gate_is_hw_controllable(gate)	FLAG_TEST(gate, GATE, HW)
+#define gate_is_sw_controllable(gate)	FLAG_TEST(gate, GATE, SW)
+#define gate_is_sw_managed(gate)	FLAG_TEST(gate, GATE, SW_MANAGED)
+#define gate_is_no_disable(gate)	FLAG_TEST(gate, GATE, NO_DISABLE)
+
+#define gate_flip_enabled(gate)		FLAG_FLIP(gate, GATE, ENABLED)
+
+#define divider_exists(div)		FLAG_TEST(div, DIV, EXISTS)
+#define divider_is_fixed(div)		FLAG_TEST(div, DIV, FIXED)
+#define divider_has_fraction(div)	(!divider_is_fixed(div) && \
+						(div)->frac_width > 0)
+
+#define selector_exists(sel)		((sel)->width != 0)
+#define trigger_exists(trig)		FLAG_TEST(trig, TRIG, EXISTS)
+
+/* Clock type, used to tell common block what it's part of */
+enum bcm_clk_type {
+	bcm_clk_none,		/* undefined clock type */
+	bcm_clk_bus,
+	bcm_clk_core,
+	bcm_clk_peri
+};
+
+/*
+ * Gating control and status is managed by a 32-bit gate register.
+ *
+ * There are several types of gating available:
+ * - (no gate)
+ *     A clock with no gate is assumed to be always enabled.
+ * - hardware-only gating (auto-gating)
+ *     Enabling or disabling clocks with this type of gate is
+ *     managed automatically by the hardware.  Such clocks can be
+ *     considered by the software to be enabled.  The current status
+ *     of auto-gated clocks can be read from the gate status bit.
+ * - software-only gating
+ *     Auto-gating is not available for this type of clock.
+ *     Instead, software manages whether it's enabled by setting or
+ *     clearing the enable bit.  The current gate status of a gate
+ *     under software control can be read from the gate status bit.
+ *     To ensure a change to the gating status is complete, the
+ *     status bit can be polled to verify that the gate has entered
+ *     the desired state.
+ * - selectable hardware or software gating
+ *     Gating for this type of clock can be configured to be either
+ *     under software or hardware control.  Which type is in use is
+ *     determined by the hw_sw_sel bit of the gate register.
+ */
+struct bcm_clk_gate {
+	u32 offset;		/* gate register offset */
+	u32 status_bit;		/* 0: gate is disabled; 0: gatge is enabled */
+	u32 en_bit;		/* 0: disable; 1: enable */
+	u32 hw_sw_sel_bit;	/* 0: hardware gating; 1: software gating */
+	u32 flags;		/* BCM_CLK_GATE_FLAGS_* below */
+};
+
+/*
+ * Gate flags:
+ *   HW         means this gate can be auto-gated
+ *   SW         means the state of this gate can be software controlled
+ *   NO_DISABLE means this gate is (only) enabled if under software control
+ *   SW_MANAGED means the status of this gate is under software control
+ *   ENABLED    means this software-managed gate is *supposed* to be enabled
+ */
+#define BCM_CLK_GATE_FLAGS_EXISTS	((u32)1 << 0)	/* Gate is valid */
+#define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
+#define BCM_CLK_GATE_FLAGS_SW		((u32)1 << 2)	/* Software control */
+#define BCM_CLK_GATE_FLAGS_NO_DISABLE	((u32)1 << 3)	/* HW or enabled */
+#define BCM_CLK_GATE_FLAGS_SW_MANAGED	((u32)1 << 4)	/* SW now in control */
+#define BCM_CLK_GATE_FLAGS_ENABLED	((u32)1 << 5)	/* If SW_MANAGED */
+
+/*
+ * Gate initialization macros.
+ *
+ * Any gate initially under software control will be enabled.
+ */
+
+/* A hardware/software gate initially under software control */
+#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)|	\
+			FLAG(GATE, EXISTS),				\
+	}
+
+/* A hardware/software gate initially under hardware control */
+#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, EXISTS),				\
+	}
+
+/* A hardware-or-enabled gate (enabled if not under hardware control) */
+#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS),	\
+	}
+
+/* A software-only gate */
+#define SW_ONLY_GATE(_offset, _status_bit, _en_bit)			\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)|		\
+			FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS),		\
+	}
+
+/* A hardware-only gate */
+#define HW_ONLY_GATE(_offset, _status_bit)				\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS),		\
+	}
+
+/*
+ * Each clock can have zero, one, or two dividers which change the
+ * output rate of the clock.  Each divider can be either fixed or
+ * variable.  If there are two dividers, they are the "pre-divider"
+ * and the "regular" or "downstream" divider.  If there is only one,
+ * there is no pre-divider.
+ *
+ * A fixed divider is any non-zero (positive) value, and it
+ * indicates how the input rate is affected by the divider.
+ *
+ * The value of a variable divider is maintained in a sub-field of a
+ * 32-bit divider register.  The position of the field in the
+ * register is defined by its offset and width.  The value recorded
+ * in this field is always 1 less than the value it represents.
+ *
+ * In addition, a variable divider can indicate that some subset
+ * of its bits represent a "fractional" part of the divider.  Such
+ * bits comprise the low-order portion of the divider field, and can
+ * be viewed as representing the portion of the divider that lies to
+ * the right of the decimal point.  Most variable dividers have zero
+ * fractional bits.  Variable dividers with non-zero fraction width
+ * still record a value 1 less than the value they represent; the
+ * added 1 does *not* affect the low-order bit in this case, it
+ * affects the bits above the fractional part only.  (Often in this
+ * code a divider field value is distinguished from the value it
+ * represents by referring to the latter as a "divisor".)
+ *
+ * In order to avoid dealing with fractions, divider arithmetic is
+ * performed using "scaled" values.  A scaled value is one that's
+ * been left-shifted by the fractional width of a divider.  Dividing
+ * a scaled value by a scaled divisor produces the desired quotient
+ * without loss of precision and without any other special handling
+ * for fractions.
+ *
+ * The recorded value of a variable divider can be modified.  To
+ * modify either divider (or both), a clock must be enabled (i.e.,
+ * using its gate).  In addition, a trigger register (described
+ * below) must be used to commit the change, and polled to verify
+ * the change is complete.
+ */
+struct bcm_clk_div {
+	union {
+		struct {	/* variable divider */
+			u32 offset;	/* divider register offset */
+			u32 shift;	/* field shift */
+			u32 width;	/* field width */
+			u32 frac_width;	/* field fraction width */
+
+			u64 scaled_div;	/* scaled divider value */
+		};
+		u32 fixed;	/* non-zero fixed divider value */
+	};
+	u32 flags;		/* BCM_CLK_DIV_FLAGS_* below */
+};
+
+/*
+ * Divider flags:
+ *   EXISTS means this divider exists
+ *   FIXED means it is a fixed-rate divider
+ */
+#define BCM_CLK_DIV_FLAGS_EXISTS	((u32)1 << 0)	/* Divider is valid */
+#define BCM_CLK_DIV_FLAGS_FIXED		((u32)1 << 1)	/* Fixed-value */
+
+/* Divider initialization macros */
+
+/* A fixed (non-zero) divider */
+#define FIXED_DIVIDER(_value)						\
+	{								\
+		.fixed = (_value),					\
+		.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED),		\
+	}
+
+/* A divider with an integral divisor */
+#define DIVIDER(_offset, _shift, _width)				\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.scaled_div = BAD_SCALED_DIV_VALUE,			\
+		.flags = FLAG(DIV, EXISTS),				\
+	}
+
+/* A divider whose divisor has an integer and fractional part */
+#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width)		\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.frac_width = (_frac_width),				\
+		.scaled_div = BAD_SCALED_DIV_VALUE,			\
+		.flags = FLAG(DIV, EXISTS),				\
+	}
+
+/*
+ * Clocks may have multiple "parent" clocks.  If there is more than
+ * one, a selector must be specified to define which of the parent
+ * clocks is currently in use.  The selected clock is indicated in a
+ * sub-field of a 32-bit selector register.  The range of
+ * representable selector values typically exceeds the number of
+ * available parent clocks.  Occasionally the reset value of a
+ * selector field is explicitly set to a (specific) value that does
+ * not correspond to a defined input clock.
+ *
+ * We register all known parent clocks with the common clock code
+ * using a packed array (i.e., no empty slots) of (parent) clock
+ * names, and refer to them later using indexes into that array.
+ * We maintain an array of selector values indexed by common clock
+ * index values in order to map between these common clock indexes
+ * and the selector values used by the hardware.
+ *
+ * Like dividers, a selector can be modified, but to do so a clock
+ * must be enabled, and a trigger must be used to commit the change.
+ */
+struct bcm_clk_sel {
+	u32 offset;		/* selector register offset */
+	u32 shift;		/* field shift */
+	u32 width;		/* field width */
+
+	u32 parent_count;	/* number of entries in parent_sel[] */
+	u32 *parent_sel;	/* array of parent selector values */
+	u8 clk_index;		/* current selected index in parent_sel[] */
+};
+
+/* Selector initialization macro */
+#define SELECTOR(_offset, _shift, _width)				\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.clk_index = BAD_CLK_INDEX,				\
+	}
+
+/*
+ * Making changes to a variable divider or a selector for a clock
+ * requires the use of a trigger.  A trigger is defined by a single
+ * bit within a register.  To signal a change, a 1 is written into
+ * that bit.  To determine when the change has been completed, that
+ * trigger bit is polled; the read value will be 1 while the change
+ * is in progress, and 0 when it is complete.
+ *
+ * Occasionally a clock will have more than one trigger.  In this
+ * case, the "pre-trigger" will be used when changing a clock's
+ * selector and/or its pre-divider.
+ */
+struct bcm_clk_trig {
+	u32 offset;		/* trigger register offset */
+	u32 bit;		/* trigger bit */
+	u32 flags;		/* BCM_CLK_TRIG_FLAGS_* below */
+};
+
+/*
+ * Trigger flags:
+ *   EXISTS means this trigger exists
+ */
+#define BCM_CLK_TRIG_FLAGS_EXISTS	((u32)1 << 0)	/* Trigger is valid */
+
+/* Trigger initialization macro */
+#define TRIGGER(_offset, _bit)						\
+	{								\
+		.offset = (_offset),					\
+		.bit = (_bit),						\
+		.flags = FLAG(TRIG, EXISTS),				\
+	}
+
+struct bus_clk_data {
+	struct bcm_clk_gate gate;
+};
+
+struct core_clk_data {
+	struct bcm_clk_gate gate;
+};
+
+struct peri_clk_data {
+	struct bcm_clk_gate gate;
+	struct bcm_clk_trig pre_trig;
+	struct bcm_clk_div pre_div;
+	struct bcm_clk_trig trig;
+	struct bcm_clk_div div;
+	struct bcm_clk_sel sel;
+	const char *clocks[];	/* must be last; use CLOCKS() to declare */
+};
+#define CLOCKS(...)	{ __VA_ARGS__, NULL, }
+#define NO_CLOCKS	{ NULL, }	/* Must use of no parent clocks */
+
+struct refclk {
+	struct clk clk;
+};
+
+struct peri_clock {
+	struct clk clk;
+	struct peri_clk_data *data;
+};
+
+struct ccu_clock {
+	struct clk clk;
+
+	int num_policy_masks;
+	unsigned long policy_freq_offset;
+	int freq_bit_shift;	/* 8 for most CCUs */
+	unsigned long policy_ctl_offset;
+	unsigned long policy0_mask_offset;
+	unsigned long policy1_mask_offset;
+	unsigned long policy2_mask_offset;
+	unsigned long policy3_mask_offset;
+	unsigned long policy0_mask2_offset;
+	unsigned long policy1_mask2_offset;
+	unsigned long policy2_mask2_offset;
+	unsigned long policy3_mask2_offset;
+	unsigned long lvm_en_offset;
+
+	int freq_id;
+	unsigned long *freq_tbl;
+};
+
+struct bus_clock {
+	struct clk clk;
+	struct bus_clk_data *data;
+	unsigned long *freq_tbl;
+};
+
+struct ref_clock {
+	struct clk clk;
+};
+
+static inline int is_same_clock(struct clk *a, struct clk *b)
+{
+	return (a == b);
+}
+
+#define to_clk(p) (&((p)->clk))
+#define name_to_clk(name) (&((name##_clk).clk))
+/* declare a struct clk_lookup */
+#define CLK_LK(name) \
+{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
+
+static inline struct refclk *to_refclk(struct clk *clock)
+{
+	return container_of(clock, struct refclk, clk);
+}
+
+static inline struct peri_clock *to_peri_clk(struct clk *clock)
+{
+	return container_of(clock, struct peri_clock, clk);
+}
+
+static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
+{
+	return container_of(clock, struct ccu_clock, clk);
+}
+
+static inline struct bus_clock *to_bus_clk(struct clk *clock)
+{
+	return container_of(clock, struct bus_clock, clk);
+}
+
+static inline struct ref_clock *to_ref_clk(struct clk *clock)
+{
+	return container_of(clock, struct ref_clock, clk);
+}
+
+extern struct clk_ops peri_clk_ops;
+extern struct clk_ops ccu_clk_ops;
+extern struct clk_ops bus_clk_ops;
+extern struct clk_ops ref_clk_ops;
+
+extern int clk_get_and_enable(char *clkstr);
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c
new file mode 100644
index 000000000..49badcbaa
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for an SDIO port */
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+	int ret;
+	struct clk *c;
+
+	char *clkstr;
+	char *slpstr;
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case CONFIG_SYS_SDIO_BASE0:
+		clkstr = CONFIG_SYS_SDIO0 "_clk";
+		ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE1:
+		clkstr = CONFIG_SYS_SDIO1 "_clk";
+		ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE2:
+		clkstr = CONFIG_SYS_SDIO2 "_clk";
+		ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE3:
+		clkstr = CONFIG_SYS_SDIO3 "_clk";
+		ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	ret = clk_get_and_enable(ahbstr);
+	if (ret)
+		return ret;
+
+	ret = clk_get_and_enable(slpstr);
+	if (ret)
+		return ret;
+
+	c = clk_get(clkstr);
+	if (c) {
+		ret = clk_set_rate(c, rate);
+		if (ret)
+			return ret;
+
+		ret = clk_enable(c);
+		if (ret)
+			return ret;
+	} else {
+		printf("%s: Couldn't find %s\n", __func__, clkstr);
+		return -EINVAL;
+	}
+	*actual_ratep = rate;
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c
new file mode 100644
index 000000000..3beb0ed9c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/bcm281xx/reset.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sysmap.h>
+
+#define EN_MASK		0x08000000	/* Enable timer */
+#define SRSTEN_MASK	0x04000000	/* Enable soft reset */
+#define CLKS_SHIFT	20		/* Clock period shift */
+#define LD_SHIFT	0		/* Reload value shift */
+
+void reset_cpu(ulong ignored)
+{
+	/*
+	 * Set WD enable, RST enable,
+	 * 3.9 msec clock period (8), reload value (8*3.9ms)
+	 */
+	u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT);
+	writel(reg, SECWD2_BASE_ADDR);
+
+	while (1)
+		;	/* loop forever till reset */
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/cache_v7.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/cache_v7.c
new file mode 100644
index 000000000..bc5fc423d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/cache_v7.c
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <linux/types.h>
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/utils.h>
+
+#define ARMV7_DCACHE_INVAL_ALL		1
+#define ARMV7_DCACHE_CLEAN_INVAL_ALL	2
+#define ARMV7_DCACHE_INVAL_RANGE	3
+#define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Write the level and type you want to Cache Size Selection Register(CSSELR)
+ * to get size details from Current Cache Size ID Register(CCSIDR)
+ */
+static void set_csselr(u32 level, u32 type)
+{	u32 csselr = level << 1 | type;
+
+	/* Write to Cache Size Selection Register(CSSELR) */
+	asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
+}
+
+static u32 get_ccsidr(void)
+{
+	u32 ccsidr;
+
+	/* Read current CP15 Cache Size ID Register */
+	asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
+	return ccsidr;
+}
+
+static u32 get_clidr(void)
+{
+	u32 clidr;
+
+	/* Read current CP15 Cache Level ID Register */
+	asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
+	return clidr;
+}
+
+static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
+					 u32 num_ways, u32 way_shift,
+					 u32 log2_line_len)
+{
+	int way, set, setway;
+
+	/*
+	 * For optimal assembly code:
+	 *	a. count down
+	 *	b. have bigger loop inside
+	 */
+	for (way = num_ways - 1; way >= 0 ; way--) {
+		for (set = num_sets - 1; set >= 0; set--) {
+			setway = (level << 1) | (set << log2_line_len) |
+				 (way << way_shift);
+			/* Invalidate data/unified cache line by set/way */
+			asm volatile ("	mcr p15, 0, %0, c7, c6, 2"
+					: : "r" (setway));
+		}
+	}
+	/* DSB to make sure the operation is complete */
+	CP15DSB;
+}
+
+static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
+					       u32 num_ways, u32 way_shift,
+					       u32 log2_line_len)
+{
+	int way, set, setway;
+
+	/*
+	 * For optimal assembly code:
+	 *	a. count down
+	 *	b. have bigger loop inside
+	 */
+	for (way = num_ways - 1; way >= 0 ; way--) {
+		for (set = num_sets - 1; set >= 0; set--) {
+			setway = (level << 1) | (set << log2_line_len) |
+				 (way << way_shift);
+			/*
+			 * Clean & Invalidate data/unified
+			 * cache line by set/way
+			 */
+			asm volatile ("	mcr p15, 0, %0, c7, c14, 2"
+					: : "r" (setway));
+		}
+	}
+	/* DSB to make sure the operation is complete */
+	CP15DSB;
+}
+
+static void v7_maint_dcache_level_setway(u32 level, u32 operation)
+{
+	u32 ccsidr;
+	u32 num_sets, num_ways, log2_line_len, log2_num_ways;
+	u32 way_shift;
+
+	set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
+
+	ccsidr = get_ccsidr();
+
+	log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
+				CCSIDR_LINE_SIZE_OFFSET) + 2;
+	/* Converting from words to bytes */
+	log2_line_len += 2;
+
+	num_ways  = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
+			CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
+	num_sets  = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
+			CCSIDR_NUM_SETS_OFFSET) + 1;
+	/*
+	 * According to ARMv7 ARM number of sets and number of ways need
+	 * not be a power of 2
+	 */
+	log2_num_ways = log_2_n_round_up(num_ways);
+
+	way_shift = (32 - log2_num_ways);
+	if (operation == ARMV7_DCACHE_INVAL_ALL) {
+		v7_inval_dcache_level_setway(level, num_sets, num_ways,
+				      way_shift, log2_line_len);
+	} else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
+		v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
+						   way_shift, log2_line_len);
+	}
+}
+
+static void v7_maint_dcache_all(u32 operation)
+{
+	u32 level, cache_type, level_start_bit = 0;
+
+	u32 clidr = get_clidr();
+
+	for (level = 0; level < 7; level++) {
+		cache_type = (clidr >> level_start_bit) & 0x7;
+		if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
+		    (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
+		    (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
+			v7_maint_dcache_level_setway(level, operation);
+		level_start_bit += 3;
+	}
+}
+
+static void v7_dcache_clean_inval_range(u32 start,
+					u32 stop, u32 line_len)
+{
+	u32 mva;
+
+	/* Align start to cache line boundary */
+	start &= ~(line_len - 1);
+	for (mva = start; mva < stop; mva = mva + line_len) {
+		/* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
+		asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
+	}
+}
+
+static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
+{
+	u32 mva;
+
+	/*
+	 * If start address is not aligned to cache-line do not
+	 * invalidate the first cache-line
+	 */
+	if (start & (line_len - 1)) {
+		printf("ERROR: %s - start address is not aligned - 0x%08x\n",
+			__func__, start);
+		/* move to next cache line */
+		start = (start + line_len - 1) & ~(line_len - 1);
+	}
+
+	/*
+	 * If stop address is not aligned to cache-line do not
+	 * invalidate the last cache-line
+	 */
+	if (stop & (line_len - 1)) {
+		printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
+			__func__, stop);
+		/* align to the beginning of this cache line */
+		stop &= ~(line_len - 1);
+	}
+
+	for (mva = start; mva < stop; mva = mva + line_len) {
+		/* DCIMVAC - Invalidate data cache by MVA to PoC */
+		asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
+	}
+}
+
+static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
+{
+	u32 line_len, ccsidr;
+
+	ccsidr = get_ccsidr();
+	line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
+			CCSIDR_LINE_SIZE_OFFSET) + 2;
+	/* Converting from words to bytes */
+	line_len += 2;
+	/* converting from log2(linelen) to linelen */
+	line_len = 1 << line_len;
+
+	switch (range_op) {
+	case ARMV7_DCACHE_CLEAN_INVAL_RANGE:
+		v7_dcache_clean_inval_range(start, stop, line_len);
+		break;
+	case ARMV7_DCACHE_INVAL_RANGE:
+		v7_dcache_inval_range(start, stop, line_len);
+		break;
+	}
+
+	/* DSB to make sure the operation is complete */
+	CP15DSB;
+}
+
+/* Invalidate TLB */
+static void v7_inval_tlb(void)
+{
+	/* Invalidate entire unified TLB */
+	asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
+	/* Invalidate entire data TLB */
+	asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
+	/* Invalidate entire instruction TLB */
+	asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
+	/* Full system DSB - make sure that the invalidation is complete */
+	CP15DSB;
+	/* Full system ISB - make sure the instruction stream sees it */
+	CP15ISB;
+}
+
+void invalidate_dcache_all(void)
+{
+	v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
+
+	v7_outer_cache_inval_all();
+}
+
+/*
+ * Performs a clean & invalidation of the entire data cache
+ * at all levels
+ */
+void flush_dcache_all(void)
+{
+	v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
+
+	v7_outer_cache_flush_all();
+}
+
+/*
+ * Invalidates range in all levels of D-cache/unified cache used:
+ * Affects the range [start, stop - 1]
+ */
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+
+	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
+
+	v7_outer_cache_inval_range(start, stop);
+}
+
+/*
+ * Flush range(clean & invalidate) from all levels of D-cache/unified
+ * cache used:
+ * Affects the range [start, stop - 1]
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
+
+	v7_outer_cache_flush_range(start, stop);
+}
+
+void arm_init_before_mmu(void)
+{
+	v7_outer_cache_enable();
+	invalidate_dcache_all();
+	v7_inval_tlb();
+}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+	flush_dcache_range(start, stop);
+	v7_inval_tlb();
+}
+
+/*
+ * Flush range from all levels of d-cache/unified-cache used:
+ * Affects the range [start, start + size - 1]
+ */
+void  flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void arm_init_before_mmu(void)
+{
+}
+
+void  flush_cache(unsigned long start, unsigned long size)
+{
+}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+}
+
+void arm_init_domains(void)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+/* Invalidate entire I-cache and branch predictor array */
+void invalidate_icache_all(void)
+{
+	/*
+	 * Invalidate all instruction caches to PoU.
+	 * Also flushes branch target cache.
+	 */
+	asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+
+	/* Invalidate entire branch predictor array */
+	asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
+
+	/* Full system DSB - make sure that the invalidation is complete */
+	CP15DSB;
+
+	/* ISB - make sure the instruction stream sees it */
+	CP15ISB;
+}
+#else
+void invalidate_icache_all(void)
+{
+}
+#endif
+
+/*
+ * Stub implementations for outer cache operations
+ */
+void __v7_outer_cache_enable(void)
+{
+}
+void v7_outer_cache_enable(void)
+	__attribute__((weak, alias("__v7_outer_cache_enable")));
+
+void __v7_outer_cache_disable(void)
+{
+}
+void v7_outer_cache_disable(void)
+	__attribute__((weak, alias("__v7_outer_cache_disable")));
+
+void __v7_outer_cache_flush_all(void)
+{
+}
+void v7_outer_cache_flush_all(void)
+	__attribute__((weak, alias("__v7_outer_cache_flush_all")));
+
+void __v7_outer_cache_inval_all(void)
+{
+}
+void v7_outer_cache_inval_all(void)
+	__attribute__((weak, alias("__v7_outer_cache_inval_all")));
+
+void __v7_outer_cache_flush_range(u32 start, u32 end)
+{
+}
+void v7_outer_cache_flush_range(u32 start, u32 end)
+	__attribute__((weak, alias("__v7_outer_cache_flush_range")));
+
+void __v7_outer_cache_inval_range(u32 start, u32 end)
+{
+}
+void v7_outer_cache_inval_range(u32 start, u32 end)
+	__attribute__((weak, alias("__v7_outer_cache_inval_range")));
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/config.mk b/qemu/roms/u-boot/arch/arm/cpu/armv7/config.mk
new file mode 100644
index 000000000..6c82c3b53
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/config.mk
@@ -0,0 +1,18 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# If armv7-a is not supported by GCC fall-back to armv5, which is
+# supported by more tool-chains
+PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
+
+# On supported platforms we set the bit which causes us to trap on unaligned
+# memory access.  This is the opposite of what the compiler expects to be
+# the default so we must pass in -mno-unaligned-access so that it is aware
+# of our decision.
+PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
+PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/cpu.c
new file mode 100644
index 000000000..01cdb7ee7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/cpu.c
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <asm/armv7.h>
+#include <linux/compiler.h>
+
+void __weak cpu_cache_initialization(void){}
+
+int cleanup_before_linux(void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+#ifndef CONFIG_SPL_BUILD
+	disable_interrupts();
+#endif
+
+	/*
+	 * Turn off I-cache and invalidate it
+	 */
+	icache_disable();
+	invalidate_icache_all();
+
+	/*
+	 * turn off D-cache
+	 * dcache_disable() in turn flushes the d-cache and disables MMU
+	 */
+	dcache_disable();
+	v7_outer_cache_disable();
+
+	/*
+	 * After D-cache is flushed and before it is disabled there may
+	 * be some new valid entries brought into the cache. We are sure
+	 * that these lines are not dirty and will not affect our execution.
+	 * (because unwinding the call-stack and setting a bit in CP15 SCTRL
+	 * is all we did during this. We have not pushed anything on to the
+	 * stack. Neither have we affected any static data)
+	 * So just invalidate the entire d-cache again to avoid coherency
+	 * problems for kernel
+	 */
+	invalidate_dcache_all();
+
+	/*
+	 * Some CPU need more cache attention before starting the kernel.
+	 */
+	cpu_cache_initialization();
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/Makefile
new file mode 100644
index 000000000..e207bd6af
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2009 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= clock.o power.o soc.o system.o pinmux.o tzpc.o
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_EXYNOS5)	+= clock_init_exynos5.o
+obj-$(CONFIG_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
+obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
+obj-y	+= spl_boot.o
+obj-y	+= lowlevel_init.o
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock.c
new file mode 100644
index 000000000..1fea4d666
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock.c
@@ -0,0 +1,1678 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/periph.h>
+
+#define PLL_DIV_1024	1024
+#define PLL_DIV_65535	65535
+#define PLL_DIV_65536	65536
+
+/* *
+ * This structure is to store the src bit, div bit and prediv bit
+ * positions of the peripheral clocks of the src and div registers
+ */
+struct clk_bit_info {
+	int8_t src_bit;
+	int8_t div_bit;
+	int8_t prediv_bit;
+};
+
+/* src_bit div_bit prediv_bit */
+static struct clk_bit_info clk_bit_info[] = {
+	{0,	0,	-1},
+	{4,	4,	-1},
+	{8,	8,	-1},
+	{12,	12,	-1},
+	{0,	0,	8},
+	{4,	16,	24},
+	{8,	0,	8},
+	{12,	16,	24},
+	{-1,	-1,	-1},
+	{16,	0,	8},
+	{20,	16,	24},
+	{24,	0,	8},
+	{0,	0,	4},
+	{4,	12,	16},
+	{-1,	-1,	-1},
+	{-1,	-1,	-1},
+	{-1,	24,	0},
+	{-1,	24,	0},
+	{-1,	24,	0},
+	{-1,	24,	0},
+	{-1,	24,	0},
+	{-1,	24,	0},
+	{-1,	24,	0},
+	{-1,	24,	0},
+	{24,	0,	-1},
+	{24,	0,	-1},
+	{24,	0,	-1},
+	{24,	0,	-1},
+	{24,	0,	-1},
+};
+
+/* Epll Clock division values to achive different frequency output */
+static struct set_epll_con_val exynos5_epll_div[] = {
+	{ 192000000, 0, 48, 3, 1, 0 },
+	{ 180000000, 0, 45, 3, 1, 0 },
+	{  73728000, 1, 73, 3, 3, 47710 },
+	{  67737600, 1, 90, 4, 3, 20762 },
+	{  49152000, 0, 49, 3, 3, 9961 },
+	{  45158400, 0, 45, 3, 3, 10381 },
+	{ 180633600, 0, 45, 3, 1, 10381 }
+};
+
+/* exynos: return pll clock frequency */
+static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
+{
+	unsigned long m, p, s = 0, mask, fout;
+	unsigned int div;
+	unsigned int freq;
+	/*
+	 * APLL_CON: MIDV [25:16]
+	 * MPLL_CON: MIDV [25:16]
+	 * EPLL_CON: MIDV [24:16]
+	 * VPLL_CON: MIDV [24:16]
+	 * BPLL_CON: MIDV [25:16]: Exynos5
+	 */
+	if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
+		mask = 0x3ff;
+	else
+		mask = 0x1ff;
+
+	m = (r >> 16) & mask;
+
+	/* PDIV [13:8] */
+	p = (r >> 8) & 0x3f;
+	/* SDIV [2:0] */
+	s = r & 0x7;
+
+	freq = CONFIG_SYS_CLK_FREQ;
+
+	if (pllreg == EPLL || pllreg == RPLL) {
+		k = k & 0xffff;
+		/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+		fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
+	} else if (pllreg == VPLL) {
+		k = k & 0xfff;
+
+		/*
+		 * Exynos4210
+		 * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos4412
+		 * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos5250
+		 * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+		 */
+		if (proid_is_exynos4210())
+			div = PLL_DIV_1024;
+		else if (proid_is_exynos4412())
+			div = PLL_DIV_65535;
+		else if (proid_is_exynos5250() || proid_is_exynos5420())
+			div = PLL_DIV_65536;
+		else
+			return 0;
+
+		fout = (m + k / div) * (freq / (p * (1 << s)));
+	} else {
+		/*
+		 * Exynos4412 / Exynos5250
+		 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+		 *
+		 * Exynos4210
+		 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+		 */
+		if (proid_is_exynos4210())
+			fout = m * (freq / (p * (1 << (s - 1))));
+		else
+			fout = m * (freq / (p * (1 << s)));
+	}
+	return fout;
+}
+
+/* exynos4: return pll clock frequency */
+static unsigned long exynos4_get_pll_clk(int pllreg)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long r, k = 0;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con0);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con0);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con0);
+		k = readl(&clk->epll_con1);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con0);
+		k = readl(&clk->vpll_con1);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	return exynos_get_pll_clk(pllreg, r, k);
+}
+
+/* exynos4x12: return pll clock frequency */
+static unsigned long exynos4x12_get_pll_clk(int pllreg)
+{
+	struct exynos4x12_clock *clk =
+		(struct exynos4x12_clock *)samsung_get_base_clock();
+	unsigned long r, k = 0;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con0);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con0);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con0);
+		k = readl(&clk->epll_con1);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con0);
+		k = readl(&clk->vpll_con1);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	return exynos_get_pll_clk(pllreg, r, k);
+}
+
+/* exynos5: return pll clock frequency */
+static unsigned long exynos5_get_pll_clk(int pllreg)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long r, k = 0, fout;
+	unsigned int pll_div2_sel, fout_sel;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con0);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con0);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con0);
+		k = readl(&clk->epll_con1);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con0);
+		k = readl(&clk->vpll_con1);
+		break;
+	case BPLL:
+		r = readl(&clk->bpll_con0);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	fout = exynos_get_pll_clk(pllreg, r, k);
+
+	/* According to the user manual, in EVT1 MPLL and BPLL always gives
+	 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+	if (pllreg == MPLL || pllreg == BPLL) {
+		pll_div2_sel = readl(&clk->pll_div2_sel);
+
+		switch (pllreg) {
+		case MPLL:
+			fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+					& MPLL_FOUT_SEL_MASK;
+			break;
+		case BPLL:
+			fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
+					& BPLL_FOUT_SEL_MASK;
+			break;
+		default:
+			fout_sel = -1;
+			break;
+		}
+
+		if (fout_sel == 0)
+			fout /= 2;
+	}
+
+	return fout;
+}
+
+static unsigned long exynos5_get_periph_rate(int peripheral)
+{
+	struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
+	unsigned long sclk, sub_clk;
+	unsigned int src, div, sub_div;
+	struct exynos5_clock *clk =
+			(struct exynos5_clock *)samsung_get_base_clock();
+
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+		src = readl(&clk->src_peric0);
+		div = readl(&clk->div_peric0);
+		break;
+	case PERIPH_ID_PWM0:
+	case PERIPH_ID_PWM1:
+	case PERIPH_ID_PWM2:
+	case PERIPH_ID_PWM3:
+	case PERIPH_ID_PWM4:
+		src = readl(&clk->src_peric0);
+		div = readl(&clk->div_peric3);
+		break;
+	case PERIPH_ID_I2S0:
+		src = readl(&clk->src_mau);
+		div = readl(&clk->div_mau);
+	case PERIPH_ID_SPI0:
+	case PERIPH_ID_SPI1:
+		src = readl(&clk->src_peric1);
+		div = readl(&clk->div_peric1);
+		break;
+	case PERIPH_ID_SPI2:
+		src = readl(&clk->src_peric1);
+		div = readl(&clk->div_peric2);
+		break;
+	case PERIPH_ID_SPI3:
+	case PERIPH_ID_SPI4:
+		src = readl(&clk->sclk_src_isp);
+		div = readl(&clk->sclk_div_isp);
+		break;
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC1:
+	case PERIPH_ID_SDMMC2:
+	case PERIPH_ID_SDMMC3:
+		src = readl(&clk->src_fsys);
+		div = readl(&clk->div_fsys1);
+		break;
+	case PERIPH_ID_I2C0:
+	case PERIPH_ID_I2C1:
+	case PERIPH_ID_I2C2:
+	case PERIPH_ID_I2C3:
+	case PERIPH_ID_I2C4:
+	case PERIPH_ID_I2C5:
+	case PERIPH_ID_I2C6:
+	case PERIPH_ID_I2C7:
+		sclk = exynos5_get_pll_clk(MPLL);
+		sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
+								& 0x7) + 1;
+		div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
+								& 0x7) + 1;
+		return (sclk / sub_div) / div;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	};
+
+	src = (src >> bit_info->src_bit) & 0xf;
+
+	switch (src) {
+	case EXYNOS_SRC_MPLL:
+		sclk = exynos5_get_pll_clk(MPLL);
+		break;
+	case EXYNOS_SRC_EPLL:
+		sclk = exynos5_get_pll_clk(EPLL);
+		break;
+	case EXYNOS_SRC_VPLL:
+		sclk = exynos5_get_pll_clk(VPLL);
+		break;
+	default:
+		return 0;
+	}
+
+	/* Ratio clock division for this peripheral */
+	sub_div = (div >> bit_info->div_bit) & 0xf;
+	sub_clk = sclk / (sub_div + 1);
+
+	/* Pre-ratio clock division for SDMMC0 and 2 */
+	if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
+		div = (div >> bit_info->prediv_bit) & 0xff;
+		return sub_clk / (div + 1);
+	}
+
+	return sub_clk;
+}
+
+unsigned long clock_get_periph_rate(int peripheral)
+{
+	if (cpu_is_exynos5())
+		return exynos5_get_periph_rate(peripheral);
+	else
+		return 0;
+}
+
+/* exynos5420: return pll clock frequency */
+static unsigned long exynos5420_get_pll_clk(int pllreg)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long r, k = 0;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con0);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con0);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con0);
+		k = readl(&clk->epll_con1);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con0);
+		k = readl(&clk->vpll_con1);
+		break;
+	case BPLL:
+		r = readl(&clk->bpll_con0);
+		break;
+	case RPLL:
+		r = readl(&clk->rpll_con0);
+		k = readl(&clk->rpll_con1);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	return exynos_get_pll_clk(pllreg, r, k);
+}
+
+/* exynos4: return ARM clock frequency */
+static unsigned long exynos4_get_arm_clk(void)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long div;
+	unsigned long armclk;
+	unsigned int core_ratio;
+	unsigned int core2_ratio;
+
+	div = readl(&clk->div_cpu0);
+
+	/* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
+	core_ratio = (div >> 0) & 0x7;
+	core2_ratio = (div >> 28) & 0x7;
+
+	armclk = get_pll_clk(APLL) / (core_ratio + 1);
+	armclk /= (core2_ratio + 1);
+
+	return armclk;
+}
+
+/* exynos4x12: return ARM clock frequency */
+static unsigned long exynos4x12_get_arm_clk(void)
+{
+	struct exynos4x12_clock *clk =
+		(struct exynos4x12_clock *)samsung_get_base_clock();
+	unsigned long div;
+	unsigned long armclk;
+	unsigned int core_ratio;
+	unsigned int core2_ratio;
+
+	div = readl(&clk->div_cpu0);
+
+	/* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
+	core_ratio = (div >> 0) & 0x7;
+	core2_ratio = (div >> 28) & 0x7;
+
+	armclk = get_pll_clk(APLL) / (core_ratio + 1);
+	armclk /= (core2_ratio + 1);
+
+	return armclk;
+}
+
+/* exynos5: return ARM clock frequency */
+static unsigned long exynos5_get_arm_clk(void)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long div;
+	unsigned long armclk;
+	unsigned int arm_ratio;
+	unsigned int arm2_ratio;
+
+	div = readl(&clk->div_cpu0);
+
+	/* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
+	arm_ratio = (div >> 0) & 0x7;
+	arm2_ratio = (div >> 28) & 0x7;
+
+	armclk = get_pll_clk(APLL) / (arm_ratio + 1);
+	armclk /= (arm2_ratio + 1);
+
+	return armclk;
+}
+
+/* exynos4: return pwm clock frequency */
+static unsigned long exynos4_get_pwm_clk(void)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	if (s5p_get_cpu_rev() == 0) {
+		/*
+		 * CLK_SRC_PERIL0
+		 * PWM_SEL [27:24]
+		 */
+		sel = readl(&clk->src_peril0);
+		sel = (sel >> 24) & 0xf;
+
+		if (sel == 0x6)
+			sclk = get_pll_clk(MPLL);
+		else if (sel == 0x7)
+			sclk = get_pll_clk(EPLL);
+		else if (sel == 0x8)
+			sclk = get_pll_clk(VPLL);
+		else
+			return 0;
+
+		/*
+		 * CLK_DIV_PERIL3
+		 * PWM_RATIO [3:0]
+		 */
+		ratio = readl(&clk->div_peril3);
+		ratio = ratio & 0xf;
+	} else if (s5p_get_cpu_rev() == 1) {
+		sclk = get_pll_clk(MPLL);
+		ratio = 8;
+	} else
+		return 0;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
+/* exynos4x12: return pwm clock frequency */
+static unsigned long exynos4x12_get_pwm_clk(void)
+{
+	unsigned long pclk, sclk;
+	unsigned int ratio;
+
+	sclk = get_pll_clk(MPLL);
+	ratio = 8;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
+/* exynos5420: return pwm clock frequency */
+static unsigned long exynos5420_get_pwm_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int ratio;
+
+	/*
+	 * CLK_DIV_PERIC0
+	 * PWM_RATIO [31:28]
+	 */
+	ratio = readl(&clk->div_peric0);
+	ratio = (ratio >> 28) & 0xf;
+	sclk = get_pll_clk(MPLL);
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
+/* exynos4: return uart clock frequency */
+static unsigned long exynos4_get_uart_clk(int dev_index)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_PERIL0
+	 * UART0_SEL [3:0]
+	 * UART1_SEL [7:4]
+	 * UART2_SEL [8:11]
+	 * UART3_SEL [12:15]
+	 * UART4_SEL [16:19]
+	 * UART5_SEL [23:20]
+	 */
+	sel = readl(&clk->src_peril0);
+	sel = (sel >> (dev_index << 2)) & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_PERIL0
+	 * UART0_RATIO [3:0]
+	 * UART1_RATIO [7:4]
+	 * UART2_RATIO [8:11]
+	 * UART3_RATIO [12:15]
+	 * UART4_RATIO [16:19]
+	 * UART5_RATIO [23:20]
+	 */
+	ratio = readl(&clk->div_peril0);
+	ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+	uclk = sclk / (ratio + 1);
+
+	return uclk;
+}
+
+/* exynos4x12: return uart clock frequency */
+static unsigned long exynos4x12_get_uart_clk(int dev_index)
+{
+	struct exynos4x12_clock *clk =
+		(struct exynos4x12_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_PERIL0
+	 * UART0_SEL [3:0]
+	 * UART1_SEL [7:4]
+	 * UART2_SEL [8:11]
+	 * UART3_SEL [12:15]
+	 * UART4_SEL [16:19]
+	 */
+	sel = readl(&clk->src_peril0);
+	sel = (sel >> (dev_index << 2)) & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_PERIL0
+	 * UART0_RATIO [3:0]
+	 * UART1_RATIO [7:4]
+	 * UART2_RATIO [8:11]
+	 * UART3_RATIO [12:15]
+	 * UART4_RATIO [16:19]
+	 */
+	ratio = readl(&clk->div_peril0);
+	ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+	uclk = sclk / (ratio + 1);
+
+	return uclk;
+}
+
+/* exynos5: return uart clock frequency */
+static unsigned long exynos5_get_uart_clk(int dev_index)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_PERIC0
+	 * UART0_SEL [3:0]
+	 * UART1_SEL [7:4]
+	 * UART2_SEL [8:11]
+	 * UART3_SEL [12:15]
+	 * UART4_SEL [16:19]
+	 * UART5_SEL [23:20]
+	 */
+	sel = readl(&clk->src_peric0);
+	sel = (sel >> (dev_index << 2)) & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_PERIC0
+	 * UART0_RATIO [3:0]
+	 * UART1_RATIO [7:4]
+	 * UART2_RATIO [8:11]
+	 * UART3_RATIO [12:15]
+	 * UART4_RATIO [16:19]
+	 * UART5_RATIO [23:20]
+	 */
+	ratio = readl(&clk->div_peric0);
+	ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+	uclk = sclk / (ratio + 1);
+
+	return uclk;
+}
+
+/* exynos5420: return uart clock frequency */
+static unsigned long exynos5420_get_uart_clk(int dev_index)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_PERIC0
+	 * UART0_SEL [6:4]
+	 * UART1_SEL [10:8]
+	 * UART2_SEL [14:12]
+	 * UART3_SEL [18:16]
+	 * generalised calculation as follows
+	 * sel = (sel >> ((dev_index * 4) + 4)) & mask;
+	 */
+	sel = readl(&clk->src_peric0);
+	sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
+
+	if (sel == 0x3)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x6)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(RPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_PERIC0
+	 * UART0_RATIO [11:8]
+	 * UART1_RATIO [15:12]
+	 * UART2_RATIO [19:16]
+	 * UART3_RATIO [23:20]
+	 * generalised calculation as follows
+	 * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
+	 */
+	ratio = readl(&clk->div_peric0);
+	ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
+
+	uclk = sclk / (ratio + 1);
+
+	return uclk;
+}
+
+static unsigned long exynos4_get_mmc_clk(int dev_index)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel, ratio, pre_ratio;
+	int shift = 0;
+
+	sel = readl(&clk->src_fsys);
+	sel = (sel >> (dev_index << 2)) & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	switch (dev_index) {
+	case 0:
+	case 1:
+		ratio = readl(&clk->div_fsys1);
+		pre_ratio = readl(&clk->div_fsys1);
+		break;
+	case 2:
+	case 3:
+		ratio = readl(&clk->div_fsys2);
+		pre_ratio = readl(&clk->div_fsys2);
+		break;
+	case 4:
+		ratio = readl(&clk->div_fsys3);
+		pre_ratio = readl(&clk->div_fsys3);
+		break;
+	default:
+		return 0;
+	}
+
+	if (dev_index == 1 || dev_index == 3)
+		shift = 16;
+
+	ratio = (ratio >> shift) & 0xf;
+	pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+	uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+	return uclk;
+}
+
+static unsigned long exynos5_get_mmc_clk(int dev_index)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel, ratio, pre_ratio;
+	int shift = 0;
+
+	sel = readl(&clk->src_fsys);
+	sel = (sel >> (dev_index << 2)) & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	switch (dev_index) {
+	case 0:
+	case 1:
+		ratio = readl(&clk->div_fsys1);
+		pre_ratio = readl(&clk->div_fsys1);
+		break;
+	case 2:
+	case 3:
+		ratio = readl(&clk->div_fsys2);
+		pre_ratio = readl(&clk->div_fsys2);
+		break;
+	default:
+		return 0;
+	}
+
+	if (dev_index == 1 || dev_index == 3)
+		shift = 16;
+
+	ratio = (ratio >> shift) & 0xf;
+	pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+	uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+	return uclk;
+}
+
+static unsigned long exynos5420_get_mmc_clk(int dev_index)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel, ratio;
+
+	/*
+	 * CLK_SRC_FSYS
+	 * MMC0_SEL [10:8]
+	 * MMC1_SEL [14:12]
+	 * MMC2_SEL [18:16]
+	 * generalised calculation as follows
+	 * sel = (sel >> ((dev_index * 4) + 8)) & mask
+	 */
+	sel = readl(&clk->src_fsys);
+	sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
+
+	if (sel == 0x3)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x6)
+		sclk = get_pll_clk(EPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_RATIO [9:0]
+	 * MMC1_RATIO [19:10]
+	 * MMC2_RATIO [29:20]
+	 * generalised calculation as follows
+	 * ratio = (ratio >> (dev_index * 10)) & mask
+	 */
+	ratio = readl(&clk->div_fsys1);
+	ratio = (ratio >> (dev_index * 10)) & 0x3ff;
+
+	uclk = (sclk / (ratio + 1));
+
+	return uclk;
+}
+
+/* exynos4: set the mmc clock */
+static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned int addr;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+	 * CLK_DIV_FSYS2
+	 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+	 * CLK_DIV_FSYS3
+	 * MMC4_PRE_RATIO [15:8]
+	 */
+	if (dev_index < 2) {
+		addr = (unsigned int)&clk->div_fsys1;
+	}  else if (dev_index == 4) {
+		addr = (unsigned int)&clk->div_fsys3;
+		dev_index -= 4;
+	} else {
+		addr = (unsigned int)&clk->div_fsys2;
+		dev_index -= 2;
+	}
+
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
+}
+
+/* exynos4x12: set the mmc clock */
+static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
+{
+	struct exynos4x12_clock *clk =
+		(struct exynos4x12_clock *)samsung_get_base_clock();
+	unsigned int addr;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+	 * CLK_DIV_FSYS2
+	 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+	 */
+	if (dev_index < 2) {
+		addr = (unsigned int)&clk->div_fsys1;
+	} else {
+		addr = (unsigned int)&clk->div_fsys2;
+		dev_index -= 2;
+	}
+
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
+}
+
+/* exynos5: set the mmc clock */
+static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned int addr;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+	 * CLK_DIV_FSYS2
+	 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+	 */
+	if (dev_index < 2) {
+		addr = (unsigned int)&clk->div_fsys1;
+	} else {
+		addr = (unsigned int)&clk->div_fsys2;
+		dev_index -= 2;
+	}
+
+	clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+			(div & 0xff) << ((dev_index << 4) + 8));
+}
+
+/* exynos5: set the mmc clock */
+static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned int addr;
+	unsigned int shift;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_RATIO [9:0]
+	 * MMC1_RATIO [19:10]
+	 * MMC2_RATIO [29:20]
+	 */
+	addr = (unsigned int)&clk->div_fsys1;
+	shift = dev_index * 10;
+
+	clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
+}
+
+/* get_lcd_clk: return lcd clock frequency */
+static unsigned long exynos4_get_lcd_clk(void)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_LCD0
+	 * FIMD0_SEL [3:0]
+	 */
+	sel = readl(&clk->src_lcd0);
+	sel = sel & 0xf;
+
+	/*
+	 * 0x6: SCLK_MPLL
+	 * 0x7: SCLK_EPLL
+	 * 0x8: SCLK_VPLL
+	 */
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_LCD0
+	 * FIMD0_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_lcd0);
+	ratio = ratio & 0xf;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
+/* get_lcd_clk: return lcd clock frequency */
+static unsigned long exynos5_get_lcd_clk(void)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_LCD0
+	 * FIMD0_SEL [3:0]
+	 */
+	sel = readl(&clk->src_disp1_0);
+	sel = sel & 0xf;
+
+	/*
+	 * 0x6: SCLK_MPLL
+	 * 0x7: SCLK_EPLL
+	 * 0x8: SCLK_VPLL
+	 */
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_LCD0
+	 * FIMD0_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_disp1_0);
+	ratio = ratio & 0xf;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
+void exynos4_set_lcd_clk(void)
+{
+	struct exynos4_clock *clk =
+	    (struct exynos4_clock *)samsung_get_base_clock();
+
+	/*
+	 * CLK_GATE_BLOCK
+	 * CLK_CAM	[0]
+	 * CLK_TV	[1]
+	 * CLK_MFC	[2]
+	 * CLK_G3D	[3]
+	 * CLK_LCD0	[4]
+	 * CLK_LCD1	[5]
+	 * CLK_GPS	[7]
+	 */
+	setbits_le32(&clk->gate_block, 1 << 4);
+
+	/*
+	 * CLK_SRC_LCD0
+	 * FIMD0_SEL		[3:0]
+	 * MDNIE0_SEL		[7:4]
+	 * MDNIE_PWM0_SEL	[8:11]
+	 * MIPI0_SEL		[12:15]
+	 * set lcd0 src clock 0x6: SCLK_MPLL
+	 */
+	clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
+
+	/*
+	 * CLK_GATE_IP_LCD0
+	 * CLK_FIMD0		[0]
+	 * CLK_MIE0		[1]
+	 * CLK_MDNIE0		[2]
+	 * CLK_DSIM0		[3]
+	 * CLK_SMMUFIMD0	[4]
+	 * CLK_PPMULCD0		[5]
+	 * Gating all clocks for FIMD0
+	 */
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
+
+	/*
+	 * CLK_DIV_LCD0
+	 * FIMD0_RATIO		[3:0]
+	 * MDNIE0_RATIO		[7:4]
+	 * MDNIE_PWM0_RATIO	[11:8]
+	 * MDNIE_PWM_PRE_RATIO	[15:12]
+	 * MIPI0_RATIO		[19:16]
+	 * MIPI0_PRE_RATIO	[23:20]
+	 * set fimd ratio
+	 */
+	clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
+}
+
+void exynos5_set_lcd_clk(void)
+{
+	struct exynos5_clock *clk =
+	    (struct exynos5_clock *)samsung_get_base_clock();
+
+	/*
+	 * CLK_GATE_BLOCK
+	 * CLK_CAM	[0]
+	 * CLK_TV	[1]
+	 * CLK_MFC	[2]
+	 * CLK_G3D	[3]
+	 * CLK_LCD0	[4]
+	 * CLK_LCD1	[5]
+	 * CLK_GPS	[7]
+	 */
+	setbits_le32(&clk->gate_block, 1 << 4);
+
+	/*
+	 * CLK_SRC_LCD0
+	 * FIMD0_SEL		[3:0]
+	 * MDNIE0_SEL		[7:4]
+	 * MDNIE_PWM0_SEL	[8:11]
+	 * MIPI0_SEL		[12:15]
+	 * set lcd0 src clock 0x6: SCLK_MPLL
+	 */
+	clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
+
+	/*
+	 * CLK_GATE_IP_LCD0
+	 * CLK_FIMD0		[0]
+	 * CLK_MIE0		[1]
+	 * CLK_MDNIE0		[2]
+	 * CLK_DSIM0		[3]
+	 * CLK_SMMUFIMD0	[4]
+	 * CLK_PPMULCD0		[5]
+	 * Gating all clocks for FIMD0
+	 */
+	setbits_le32(&clk->gate_ip_disp1, 1 << 0);
+
+	/*
+	 * CLK_DIV_LCD0
+	 * FIMD0_RATIO		[3:0]
+	 * MDNIE0_RATIO		[7:4]
+	 * MDNIE_PWM0_RATIO	[11:8]
+	 * MDNIE_PWM_PRE_RATIO	[15:12]
+	 * MIPI0_RATIO		[19:16]
+	 * MIPI0_PRE_RATIO	[23:20]
+	 * set fimd ratio
+	 */
+	clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
+}
+
+void exynos4_set_mipi_clk(void)
+{
+	struct exynos4_clock *clk =
+	    (struct exynos4_clock *)samsung_get_base_clock();
+
+	/*
+	 * CLK_SRC_LCD0
+	 * FIMD0_SEL		[3:0]
+	 * MDNIE0_SEL		[7:4]
+	 * MDNIE_PWM0_SEL	[8:11]
+	 * MIPI0_SEL		[12:15]
+	 * set mipi0 src clock 0x6: SCLK_MPLL
+	 */
+	clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
+
+	/*
+	 * CLK_SRC_MASK_LCD0
+	 * FIMD0_MASK		[0]
+	 * MDNIE0_MASK		[4]
+	 * MDNIE_PWM0_MASK	[8]
+	 * MIPI0_MASK		[12]
+	 * set src mask mipi0 0x1: Unmask
+	 */
+	setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
+
+	/*
+	 * CLK_GATE_IP_LCD0
+	 * CLK_FIMD0		[0]
+	 * CLK_MIE0		[1]
+	 * CLK_MDNIE0		[2]
+	 * CLK_DSIM0		[3]
+	 * CLK_SMMUFIMD0	[4]
+	 * CLK_PPMULCD0		[5]
+	 * Gating all clocks for MIPI0
+	 */
+	setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
+
+	/*
+	 * CLK_DIV_LCD0
+	 * FIMD0_RATIO		[3:0]
+	 * MDNIE0_RATIO		[7:4]
+	 * MDNIE_PWM0_RATIO	[11:8]
+	 * MDNIE_PWM_PRE_RATIO	[15:12]
+	 * MIPI0_RATIO		[19:16]
+	 * MIPI0_PRE_RATIO	[23:20]
+	 * set mipi ratio
+	 */
+	clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
+}
+
+/*
+ * I2C
+ *
+ * exynos5: obtaining the I2C clock
+ */
+static unsigned long exynos5_get_i2c_clk(void)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long aclk_66, aclk_66_pre, sclk;
+	unsigned int ratio;
+
+	sclk = get_pll_clk(MPLL);
+
+	ratio = (readl(&clk->div_top1)) >> 24;
+	ratio &= 0x7;
+	aclk_66_pre = sclk / (ratio + 1);
+	ratio = readl(&clk->div_top0);
+	ratio &= 0x7;
+	aclk_66 = aclk_66_pre / (ratio + 1);
+	return aclk_66;
+}
+
+int exynos5_set_epll_clk(unsigned long rate)
+{
+	unsigned int epll_con, epll_con_k;
+	unsigned int i;
+	unsigned int lockcnt;
+	unsigned int start;
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+
+	epll_con = readl(&clk->epll_con0);
+	epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
+			EPLL_CON0_LOCK_DET_EN_SHIFT) |
+		EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
+		EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
+		EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
+		if (exynos5_epll_div[i].freq_out == rate)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(exynos5_epll_div))
+		return -1;
+
+	epll_con_k = exynos5_epll_div[i].k_dsm << 0;
+	epll_con |= exynos5_epll_div[i].en_lock_det <<
+				EPLL_CON0_LOCK_DET_EN_SHIFT;
+	epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
+	epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
+	epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
+
+	/*
+	 * Required period ( in cycles) to genarate a stable clock output.
+	 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
+	 * frequency input (as per spec)
+	 */
+	lockcnt = 3000 * exynos5_epll_div[i].p_div;
+
+	writel(lockcnt, &clk->epll_lock);
+	writel(epll_con, &clk->epll_con0);
+	writel(epll_con_k, &clk->epll_con1);
+
+	start = get_timer(0);
+
+	 while (!(readl(&clk->epll_con0) &
+			(0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
+		if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
+			debug("%s: Timeout waiting for EPLL lock\n", __func__);
+			return -1;
+		}
+	}
+	return 0;
+}
+
+int exynos5_set_i2s_clk_source(unsigned int i2s_id)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass();
+
+	if (i2s_id == 0) {
+		setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
+		clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,
+				(CLK_SRC_SCLK_EPLL));
+		setbits_le32(audio_ass, AUDIO_CLKMUX_ASS);
+	} else if (i2s_id == 1) {
+		clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
+				(CLK_SRC_SCLK_EPLL));
+	} else {
+		return -1;
+	}
+	return 0;
+}
+
+int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
+				  unsigned int dst_frq,
+				  unsigned int i2s_id)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned int div;
+
+	if ((dst_frq == 0) || (src_frq == 0)) {
+		debug("%s: Invalid requency input for prescaler\n", __func__);
+		debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+		return -1;
+	}
+
+	div = (src_frq / dst_frq);
+	if (i2s_id == 0) {
+		if (div > AUDIO_0_RATIO_MASK) {
+			debug("%s: Frequency ratio is out of range\n",
+			      __func__);
+			debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+			return -1;
+		}
+		clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,
+				(div & AUDIO_0_RATIO_MASK));
+	} else if(i2s_id == 1) {
+		if (div > AUDIO_1_RATIO_MASK) {
+			debug("%s: Frequency ratio is out of range\n",
+			      __func__);
+			debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+			return -1;
+		}
+		clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
+				(div & AUDIO_1_RATIO_MASK));
+	} else {
+		return -1;
+	}
+	return 0;
+}
+
+/**
+ * Linearly searches for the most accurate main and fine stage clock scalars
+ * (divisors) for a specified target frequency and scalar bit sizes by checking
+ * all multiples of main_scalar_bits values. Will always return scalars up to or
+ * slower than target.
+ *
+ * @param main_scalar_bits	Number of main scalar bits, must be > 0 and < 32
+ * @param fine_scalar_bits	Number of fine scalar bits, must be > 0 and < 32
+ * @param input_freq		Clock frequency to be scaled in Hz
+ * @param target_freq		Desired clock frequency in Hz
+ * @param best_fine_scalar	Pointer to store the fine stage divisor
+ *
+ * @return best_main_scalar	Main scalar for desired frequency or -1 if none
+ * found
+ */
+static int clock_calc_best_scalar(unsigned int main_scaler_bits,
+	unsigned int fine_scalar_bits, unsigned int input_rate,
+	unsigned int target_rate, unsigned int *best_fine_scalar)
+{
+	int i;
+	int best_main_scalar = -1;
+	unsigned int best_error = target_rate;
+	const unsigned int cap = (1 << fine_scalar_bits) - 1;
+	const unsigned int loops = 1 << main_scaler_bits;
+
+	debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
+			target_rate, cap);
+
+	assert(best_fine_scalar != NULL);
+	assert(main_scaler_bits <= fine_scalar_bits);
+
+	*best_fine_scalar = 1;
+
+	if (input_rate == 0 || target_rate == 0)
+		return -1;
+
+	if (target_rate >= input_rate)
+		return 1;
+
+	for (i = 1; i <= loops; i++) {
+		const unsigned int effective_div = max(min(input_rate / i /
+							target_rate, cap), 1);
+		const unsigned int effective_rate = input_rate / i /
+							effective_div;
+		const int error = target_rate - effective_rate;
+
+		debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
+				effective_rate, error);
+
+		if (error >= 0 && error <= best_error) {
+			best_error = error;
+			best_main_scalar = i;
+			*best_fine_scalar = effective_div;
+		}
+	}
+
+	return best_main_scalar;
+}
+
+static int exynos5_set_spi_clk(enum periph_id periph_id,
+					unsigned int rate)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	int main;
+	unsigned int fine;
+	unsigned shift, pre_shift;
+	unsigned mask = 0xff;
+	u32 *reg;
+
+	main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+	if (main < 0) {
+		debug("%s: Cannot set clock rate for periph %d",
+				__func__, periph_id);
+		return -1;
+	}
+	main = main - 1;
+	fine = fine - 1;
+
+	switch (periph_id) {
+	case PERIPH_ID_SPI0:
+		reg = &clk->div_peric1;
+		shift = 0;
+		pre_shift = 8;
+		break;
+	case PERIPH_ID_SPI1:
+		reg = &clk->div_peric1;
+		shift = 16;
+		pre_shift = 24;
+		break;
+	case PERIPH_ID_SPI2:
+		reg = &clk->div_peric2;
+		shift = 0;
+		pre_shift = 8;
+		break;
+	case PERIPH_ID_SPI3:
+		reg = &clk->sclk_div_isp;
+		shift = 0;
+		pre_shift = 4;
+		break;
+	case PERIPH_ID_SPI4:
+		reg = &clk->sclk_div_isp;
+		shift = 12;
+		pre_shift = 16;
+		break;
+	default:
+		debug("%s: Unsupported peripheral ID %d\n", __func__,
+		      periph_id);
+		return -1;
+	}
+	clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
+	clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
+
+	return 0;
+}
+
+static int exynos5420_set_spi_clk(enum periph_id periph_id,
+					unsigned int rate)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	int main;
+	unsigned int fine;
+	unsigned shift, pre_shift;
+	unsigned div_mask = 0xf, pre_div_mask = 0xff;
+	u32 *reg;
+	u32 *pre_reg;
+
+	main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+	if (main < 0) {
+		debug("%s: Cannot set clock rate for periph %d",
+		      __func__, periph_id);
+		return -1;
+	}
+	main = main - 1;
+	fine = fine - 1;
+
+	switch (periph_id) {
+	case PERIPH_ID_SPI0:
+		reg = &clk->div_peric1;
+		shift = 20;
+		pre_reg = &clk->div_peric4;
+		pre_shift = 8;
+		break;
+	case PERIPH_ID_SPI1:
+		reg = &clk->div_peric1;
+		shift = 24;
+		pre_reg = &clk->div_peric4;
+		pre_shift = 16;
+		break;
+	case PERIPH_ID_SPI2:
+		reg = &clk->div_peric1;
+		shift = 28;
+		pre_reg = &clk->div_peric4;
+		pre_shift = 24;
+		break;
+	case PERIPH_ID_SPI3:
+		reg = &clk->div_isp1;
+		shift = 16;
+		pre_reg = &clk->div_isp1;
+		pre_shift = 0;
+		break;
+	case PERIPH_ID_SPI4:
+		reg = &clk->div_isp1;
+		shift = 20;
+		pre_reg = &clk->div_isp1;
+		pre_shift = 8;
+		break;
+	default:
+		debug("%s: Unsupported peripheral ID %d\n", __func__,
+		      periph_id);
+		return -1;
+	}
+
+	clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
+	clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
+			(fine & pre_div_mask) << pre_shift);
+
+	return 0;
+}
+
+static unsigned long exynos4_get_i2c_clk(void)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long sclk, aclk_100;
+	unsigned int ratio;
+
+	sclk = get_pll_clk(APLL);
+
+	ratio = (readl(&clk->div_top)) >> 4;
+	ratio &= 0xf;
+	aclk_100 = sclk / (ratio + 1);
+	return aclk_100;
+}
+
+unsigned long get_pll_clk(int pllreg)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_pll_clk(pllreg);
+		return exynos5_get_pll_clk(pllreg);
+	} else {
+		if (proid_is_exynos4412())
+			return exynos4x12_get_pll_clk(pllreg);
+		return exynos4_get_pll_clk(pllreg);
+	}
+}
+
+unsigned long get_arm_clk(void)
+{
+	if (cpu_is_exynos5())
+		return exynos5_get_arm_clk();
+	else {
+		if (proid_is_exynos4412())
+			return exynos4x12_get_arm_clk();
+		return exynos4_get_arm_clk();
+	}
+}
+
+unsigned long get_i2c_clk(void)
+{
+	if (cpu_is_exynos5()) {
+		return exynos5_get_i2c_clk();
+	} else if (cpu_is_exynos4()) {
+		return exynos4_get_i2c_clk();
+	} else {
+		debug("I2C clock is not set for this CPU\n");
+		return 0;
+	}
+}
+
+unsigned long get_pwm_clk(void)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_pwm_clk();
+		return clock_get_periph_rate(PERIPH_ID_PWM0);
+	} else {
+		if (proid_is_exynos4412())
+			return exynos4x12_get_pwm_clk();
+		return exynos4_get_pwm_clk();
+	}
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_uart_clk(dev_index);
+		return exynos5_get_uart_clk(dev_index);
+	} else {
+		if (proid_is_exynos4412())
+			return exynos4x12_get_uart_clk(dev_index);
+		return exynos4_get_uart_clk(dev_index);
+	}
+}
+
+unsigned long get_mmc_clk(int dev_index)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_get_mmc_clk(dev_index);
+		return exynos5_get_mmc_clk(dev_index);
+	} else {
+		return exynos4_get_mmc_clk(dev_index);
+	}
+}
+
+void set_mmc_clk(int dev_index, unsigned int div)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			exynos5420_set_mmc_clk(dev_index, div);
+		else
+			exynos5_set_mmc_clk(dev_index, div);
+	} else {
+		if (proid_is_exynos4412())
+			exynos4x12_set_mmc_clk(dev_index, div);
+		else
+			exynos4_set_mmc_clk(dev_index, div);
+	}
+}
+
+unsigned long get_lcd_clk(void)
+{
+	if (cpu_is_exynos4())
+		return exynos4_get_lcd_clk();
+	else
+		return exynos5_get_lcd_clk();
+}
+
+void set_lcd_clk(void)
+{
+	if (cpu_is_exynos4())
+		exynos4_set_lcd_clk();
+	else
+		exynos5_set_lcd_clk();
+}
+
+void set_mipi_clk(void)
+{
+	if (cpu_is_exynos4())
+		exynos4_set_mipi_clk();
+}
+
+int set_spi_clk(int periph_id, unsigned int rate)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_set_spi_clk(periph_id, rate);
+		return exynos5_set_spi_clk(periph_id, rate);
+	} else {
+		return 0;
+	}
+}
+
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
+			  unsigned int i2s_id)
+{
+	if (cpu_is_exynos5())
+		return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id);
+	else
+		return 0;
+}
+
+int set_i2s_clk_source(unsigned int i2s_id)
+{
+	if (cpu_is_exynos5())
+		return exynos5_set_i2s_clk_source(i2s_id);
+	else
+		return 0;
+}
+
+int set_epll_clk(unsigned long rate)
+{
+	if (cpu_is_exynos5())
+		return exynos5_set_epll_clk(rate);
+	else
+		return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock_init.h b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock_init.h
new file mode 100644
index 000000000..a875d0b48
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock_init.h
@@ -0,0 +1,155 @@
+/*
+ * Clock initialization routines
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __EXYNOS_CLOCK_INIT_H
+#define __EXYNOS_CLOCK_INIT_H
+
+enum {
+#ifdef CONFIG_EXYNOS5420
+	MEM_TIMINGS_MSR_COUNT	= 5,
+#else
+	MEM_TIMINGS_MSR_COUNT	= 4,
+#endif
+};
+
+/* These are the ratio's for configuring ARM clock */
+struct arm_clk_ratios {
+	unsigned arm_freq_mhz;		/* Frequency of ARM core in MHz */
+
+	unsigned apll_mdiv;
+	unsigned apll_pdiv;
+	unsigned apll_sdiv;
+
+	unsigned arm2_ratio;
+	unsigned apll_ratio;
+	unsigned pclk_dbg_ratio;
+	unsigned atb_ratio;
+	unsigned periph_ratio;
+	unsigned acp_ratio;
+	unsigned cpud_ratio;
+	unsigned arm_ratio;
+};
+
+/* These are the memory timings for a particular memory type and speed */
+struct mem_timings {
+	enum mem_manuf mem_manuf;	/* Memory manufacturer */
+	enum ddr_mode mem_type;		/* Memory type */
+	unsigned frequency_mhz;		/* Frequency of memory in MHz */
+
+	/* Here follow the timing parameters for the selected memory */
+	unsigned apll_mdiv;
+	unsigned apll_pdiv;
+	unsigned apll_sdiv;
+	unsigned mpll_mdiv;
+	unsigned mpll_pdiv;
+	unsigned mpll_sdiv;
+	unsigned cpll_mdiv;
+	unsigned cpll_pdiv;
+	unsigned cpll_sdiv;
+	unsigned gpll_mdiv;
+	unsigned gpll_pdiv;
+	unsigned gpll_sdiv;
+	unsigned epll_mdiv;
+	unsigned epll_pdiv;
+	unsigned epll_sdiv;
+	unsigned vpll_mdiv;
+	unsigned vpll_pdiv;
+	unsigned vpll_sdiv;
+	unsigned bpll_mdiv;
+	unsigned bpll_pdiv;
+	unsigned bpll_sdiv;
+	unsigned kpll_mdiv;
+	unsigned kpll_pdiv;
+	unsigned kpll_sdiv;
+	unsigned dpll_mdiv;
+	unsigned dpll_pdiv;
+	unsigned dpll_sdiv;
+	unsigned ipll_mdiv;
+	unsigned ipll_pdiv;
+	unsigned ipll_sdiv;
+	unsigned spll_mdiv;
+	unsigned spll_pdiv;
+	unsigned spll_sdiv;
+	unsigned pclk_cdrex_ratio;
+	unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
+
+	unsigned timing_ref;
+	unsigned timing_row;
+	unsigned timing_data;
+	unsigned timing_power;
+
+	/* DQS, DQ, DEBUG offsets */
+	unsigned phy0_dqs;
+	unsigned phy1_dqs;
+	unsigned phy0_dq;
+	unsigned phy1_dq;
+	unsigned phy0_tFS;
+	unsigned phy1_tFS;
+	unsigned phy0_pulld_dqs;
+	unsigned phy1_pulld_dqs;
+
+	unsigned lpddr3_ctrl_phy_reset;
+	unsigned ctrl_start_point;
+	unsigned ctrl_inc;
+	unsigned ctrl_start;
+	unsigned ctrl_dll_on;
+	unsigned ctrl_ref;
+
+	unsigned ctrl_force;
+	unsigned ctrl_rdlat;
+	unsigned ctrl_bstlen;
+
+	unsigned fp_resync;
+	unsigned iv_size;
+	unsigned dfi_init_start;
+	unsigned aref_en;
+
+	unsigned rd_fetch;
+
+	unsigned zq_mode_dds;
+	unsigned zq_mode_term;
+	unsigned zq_mode_noterm;	/* 1 to allow termination disable */
+
+	unsigned memcontrol;
+	unsigned memconfig;
+
+	unsigned membaseconfig0;
+	unsigned membaseconfig1;
+	unsigned prechconfig_tp_cnt;
+	unsigned dpwrdn_cyc;
+	unsigned dsref_cyc;
+	unsigned concontrol;
+	/* Channel and Chip Selection */
+	uint8_t dmc_channels;		/* number of memory channels */
+	uint8_t chips_per_channel;	/* number of chips per channel */
+	uint8_t chips_to_configure;	/* number of chips to configure */
+	uint8_t send_zq_init;		/* 1 to send this command */
+	unsigned impedance;		/* drive strength impedeance */
+	uint8_t gate_leveling_enable;	/* check gate leveling is enabled */
+	uint8_t read_leveling_enable;	/* check h/w read leveling is enabled */
+};
+
+/**
+ * Get the correct memory timings for our selected memory type and speed.
+ *
+ * This function can be called from SPL or the main U-Boot.
+ *
+ * @return pointer to the memory timings that we should use
+ */
+struct mem_timings *clock_get_mem_timings(void);
+
+/*
+ * Initialize clock for the device
+ */
+void system_clock_init(void);
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ */
+void emmc_boot_clk_div_set(void);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
new file mode 100644
index 000000000..31610909f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c
@@ -0,0 +1,95 @@
+/*
+ * Clock Initialization for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+void system_clock_init(void)
+{
+	struct exynos4_clock *clk =
+			(struct exynos4_clock *)samsung_get_base_clock();
+
+	writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+
+	sdelay(0x10000);
+
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
+	writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
+	writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
+	writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+	writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
+	writel(CLK_SRC_CAM_VAL, &clk->src_cam);
+	writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
+	writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
+	writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
+
+	sdelay(0x10000);
+
+	writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+	writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
+	writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
+	writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
+	writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
+	writel(CLK_DIV_TOP_VAL, &clk->div_top);
+	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+	writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+	writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
+	writel(CLK_DIV_CAM_VAL, &clk->div_cam);
+	writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
+	writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
+	writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
+
+	/* Set PLL locktime */
+	writel(PLL_LOCKTIME, &clk->apll_lock);
+	writel(PLL_LOCKTIME, &clk->mpll_lock);
+	writel(PLL_LOCKTIME, &clk->epll_lock);
+	writel(PLL_LOCKTIME, &clk->vpll_lock);
+
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	writel(APLL_CON0_VAL, &clk->apll_con0);
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	writel(MPLL_CON0_VAL, &clk->mpll_con0);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	writel(EPLL_CON0_VAL, &clk->epll_con0);
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	writel(VPLL_CON0_VAL, &clk->vpll_con0);
+
+	sdelay(0x30000);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
new file mode 100644
index 000000000..1d6977fa4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -0,0 +1,992 @@
+/*
+ * Clock setup for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/dwmmc.h>
+
+#include "clock_init.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
+
+#define FSYS1_MMC0_DIV_MASK	0xff0f
+#define FSYS1_MMC0_DIV_VAL	0x0701
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arm_clk_ratios arm_clk_ratios[] = {
+#ifdef CONFIG_EXYNOS5420
+	{
+		.arm_freq_mhz = 900,
+
+		.apll_mdiv = 0x96,
+		.apll_pdiv = 0x2,
+		.apll_sdiv = 0x1,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x6,
+		.atb_ratio = 0x6,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x0,
+		.cpud_ratio = 0x2,
+		.arm_ratio = 0x0,
+	}
+#else
+	{
+		.arm_freq_mhz = 600,
+
+		.apll_mdiv = 0xc8,
+		.apll_pdiv = 0x4,
+		.apll_sdiv = 0x1,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x1,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x2,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x1,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 800,
+
+		.apll_mdiv = 0x64,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x1,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x3,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x2,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1000,
+
+		.apll_mdiv = 0x7d,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x1,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x4,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x2,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1200,
+
+		.apll_mdiv = 0x96,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x5,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x3,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1400,
+
+		.apll_mdiv = 0xaf,
+		.apll_pdiv = 0x3,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x6,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x3,
+		.arm_ratio = 0x0,
+	}, {
+		.arm_freq_mhz = 1700,
+
+		.apll_mdiv = 0x1a9,
+		.apll_pdiv = 0x6,
+		.apll_sdiv = 0x0,
+
+		.arm2_ratio = 0x0,
+		.apll_ratio = 0x3,
+		.pclk_dbg_ratio = 0x1,
+		.atb_ratio = 0x6,
+		.periph_ratio = 0x7,
+		.acp_ratio = 0x7,
+		.cpud_ratio = 0x3,
+		.arm_ratio = 0x0,
+	}
+#endif
+};
+
+struct mem_timings mem_timings[] = {
+#ifdef CONFIG_EXYNOS5420
+	{
+		.mem_manuf = MEM_MANUF_SAMSUNG,
+		.mem_type = DDR_MODE_DDR3,
+		.frequency_mhz = 800,
+
+		/* MPLL @800MHz*/
+		.mpll_mdiv = 0xc8,
+		.mpll_pdiv = 0x3,
+		.mpll_sdiv = 0x1,
+		/* CPLL @666MHz */
+		.cpll_mdiv = 0xde,
+		.cpll_pdiv = 0x4,
+		.cpll_sdiv = 0x1,
+		/* EPLL @600MHz */
+		.epll_mdiv = 0x64,
+		.epll_pdiv = 0x2,
+		.epll_sdiv = 0x1,
+		/* VPLL @430MHz */
+		.vpll_mdiv = 0xd7,
+		.vpll_pdiv = 0x3,
+		.vpll_sdiv = 0x2,
+		/* BPLL @800MHz */
+		.bpll_mdiv = 0xc8,
+		.bpll_pdiv = 0x3,
+		.bpll_sdiv = 0x1,
+		/* KPLL @600MHz */
+		.kpll_mdiv = 0x190,
+		.kpll_pdiv = 0x4,
+		.kpll_sdiv = 0x2,
+		/* DPLL @600MHz */
+		.dpll_mdiv = 0x190,
+		.dpll_pdiv = 0x4,
+		.dpll_sdiv = 0x2,
+		/* IPLL @370MHz */
+		.ipll_mdiv = 0xb9,
+		.ipll_pdiv = 0x3,
+		.ipll_sdiv = 0x2,
+		/* SPLL @400MHz */
+		.spll_mdiv = 0xc8,
+		.spll_pdiv = 0x3,
+		.spll_sdiv = 0x2,
+
+		.direct_cmd_msr = {
+			0x00020018, 0x00030000, 0x00010046, 0x00000d70,
+			0x00000c70
+		},
+		.timing_ref = 0x000000bb,
+		.timing_row = 0x6836650f,
+		.timing_data = 0x3630580b,
+		.timing_power = 0x41000a26,
+		.phy0_dqs = 0x08080808,
+		.phy1_dqs = 0x08080808,
+		.phy0_dq = 0x08080808,
+		.phy1_dq = 0x08080808,
+		.phy0_tFS = 0x8,
+		.phy1_tFS = 0x8,
+		.phy0_pulld_dqs = 0xf,
+		.phy1_pulld_dqs = 0xf,
+
+		.lpddr3_ctrl_phy_reset = 0x1,
+		.ctrl_start_point = 0x10,
+		.ctrl_inc = 0x10,
+		.ctrl_start = 0x1,
+		.ctrl_dll_on = 0x1,
+		.ctrl_ref = 0x8,
+
+		.ctrl_force = 0x1a,
+		.ctrl_rdlat = 0x0b,
+		.ctrl_bstlen = 0x08,
+
+		.fp_resync = 0x8,
+		.iv_size = 0x7,
+		.dfi_init_start = 1,
+		.aref_en = 1,
+
+		.rd_fetch = 0x3,
+
+		.zq_mode_dds = 0x7,
+		.zq_mode_term = 0x1,
+		.zq_mode_noterm = 1,
+
+		/*
+		* Dynamic Clock: Always Running
+		* Memory Burst length: 8
+		* Number of chips: 1
+		* Memory Bus width: 32 bit
+		* Memory Type: DDR3
+		* Additional Latancy for PLL: 0 Cycle
+		*/
+		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+			DMC_MEMCONTROL_TP_DISABLE |
+			DMC_MEMCONTROL_DSREF_DISABLE |
+			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+			DMC_MEMCONTROL_NUM_CHIP_1 |
+			DMC_MEMCONTROL_BL_8 |
+			DMC_MEMCONTROL_PZQ_DISABLE |
+			DMC_MEMCONTROL_MRR_BYTE_7_0,
+		.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
+			DMC_MEMCONFIGX_CHIP_COL_10 |
+			DMC_MEMCONFIGX_CHIP_ROW_15 |
+			DMC_MEMCONFIGX_CHIP_BANK_8,
+		.prechconfig_tp_cnt = 0xff,
+		.dpwrdn_cyc = 0xff,
+		.dsref_cyc = 0xffff,
+		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+			DMC_CONCONTROL_RD_FETCH_DISABLE |
+			DMC_CONCONTROL_EMPTY_DISABLE |
+			DMC_CONCONTROL_AREF_EN_DISABLE |
+			DMC_CONCONTROL_IO_PD_CON_DISABLE,
+		.dmc_channels = 1,
+		.chips_per_channel = 1,
+		.chips_to_configure = 1,
+		.send_zq_init = 1,
+		.gate_leveling_enable = 1,
+		.read_leveling_enable = 0,
+	}
+#else
+	{
+		.mem_manuf = MEM_MANUF_ELPIDA,
+		.mem_type = DDR_MODE_DDR3,
+		.frequency_mhz = 800,
+		.mpll_mdiv = 0xc8,
+		.mpll_pdiv = 0x3,
+		.mpll_sdiv = 0x0,
+		.cpll_mdiv = 0xde,
+		.cpll_pdiv = 0x4,
+		.cpll_sdiv = 0x2,
+		.gpll_mdiv = 0x215,
+		.gpll_pdiv = 0xc,
+		.gpll_sdiv = 0x1,
+		.epll_mdiv = 0x60,
+		.epll_pdiv = 0x3,
+		.epll_sdiv = 0x3,
+		.vpll_mdiv = 0x96,
+		.vpll_pdiv = 0x3,
+		.vpll_sdiv = 0x2,
+
+		.bpll_mdiv = 0x64,
+		.bpll_pdiv = 0x3,
+		.bpll_sdiv = 0x0,
+		.pclk_cdrex_ratio = 0x5,
+		.direct_cmd_msr = {
+			0x00020018, 0x00030000, 0x00010042, 0x00000d70
+		},
+		.timing_ref = 0x000000bb,
+		.timing_row = 0x8c36650e,
+		.timing_data = 0x3630580b,
+		.timing_power = 0x41000a44,
+		.phy0_dqs = 0x08080808,
+		.phy1_dqs = 0x08080808,
+		.phy0_dq = 0x08080808,
+		.phy1_dq = 0x08080808,
+		.phy0_tFS = 0x4,
+		.phy1_tFS = 0x4,
+		.phy0_pulld_dqs = 0xf,
+		.phy1_pulld_dqs = 0xf,
+
+		.lpddr3_ctrl_phy_reset = 0x1,
+		.ctrl_start_point = 0x10,
+		.ctrl_inc = 0x10,
+		.ctrl_start = 0x1,
+		.ctrl_dll_on = 0x1,
+		.ctrl_ref = 0x8,
+
+		.ctrl_force = 0x1a,
+		.ctrl_rdlat = 0x0b,
+		.ctrl_bstlen = 0x08,
+
+		.fp_resync = 0x8,
+		.iv_size = 0x7,
+		.dfi_init_start = 1,
+		.aref_en = 1,
+
+		.rd_fetch = 0x3,
+
+		.zq_mode_dds = 0x7,
+		.zq_mode_term = 0x1,
+		.zq_mode_noterm = 0,
+
+		/*
+		* Dynamic Clock: Always Running
+		* Memory Burst length: 8
+		* Number of chips: 1
+		* Memory Bus width: 32 bit
+		* Memory Type: DDR3
+		* Additional Latancy for PLL: 0 Cycle
+		*/
+		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+			DMC_MEMCONTROL_TP_DISABLE |
+			DMC_MEMCONTROL_DSREF_ENABLE |
+			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+			DMC_MEMCONTROL_NUM_CHIP_1 |
+			DMC_MEMCONTROL_BL_8 |
+			DMC_MEMCONTROL_PZQ_DISABLE |
+			DMC_MEMCONTROL_MRR_BYTE_7_0,
+		.memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+			DMC_MEMCONFIGX_CHIP_COL_10 |
+			DMC_MEMCONFIGX_CHIP_ROW_15 |
+			DMC_MEMCONFIGX_CHIP_BANK_8,
+		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
+		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
+		.prechconfig_tp_cnt = 0xff,
+		.dpwrdn_cyc = 0xff,
+		.dsref_cyc = 0xffff,
+		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+			DMC_CONCONTROL_RD_FETCH_DISABLE |
+			DMC_CONCONTROL_EMPTY_DISABLE |
+			DMC_CONCONTROL_AREF_EN_DISABLE |
+			DMC_CONCONTROL_IO_PD_CON_DISABLE,
+		.dmc_channels = 2,
+		.chips_per_channel = 2,
+		.chips_to_configure = 1,
+		.send_zq_init = 1,
+		.impedance = IMP_OUTPUT_DRV_30_OHM,
+		.gate_leveling_enable = 0,
+	}, {
+		.mem_manuf = MEM_MANUF_SAMSUNG,
+		.mem_type = DDR_MODE_DDR3,
+		.frequency_mhz = 800,
+		.mpll_mdiv = 0xc8,
+		.mpll_pdiv = 0x3,
+		.mpll_sdiv = 0x0,
+		.cpll_mdiv = 0xde,
+		.cpll_pdiv = 0x4,
+		.cpll_sdiv = 0x2,
+		.gpll_mdiv = 0x215,
+		.gpll_pdiv = 0xc,
+		.gpll_sdiv = 0x1,
+		.epll_mdiv = 0x60,
+		.epll_pdiv = 0x3,
+		.epll_sdiv = 0x3,
+		.vpll_mdiv = 0x96,
+		.vpll_pdiv = 0x3,
+		.vpll_sdiv = 0x2,
+
+		.bpll_mdiv = 0x64,
+		.bpll_pdiv = 0x3,
+		.bpll_sdiv = 0x0,
+		.pclk_cdrex_ratio = 0x5,
+		.direct_cmd_msr = {
+			0x00020018, 0x00030000, 0x00010000, 0x00000d70
+		},
+		.timing_ref = 0x000000bb,
+		.timing_row = 0x8c36650e,
+		.timing_data = 0x3630580b,
+		.timing_power = 0x41000a44,
+		.phy0_dqs = 0x08080808,
+		.phy1_dqs = 0x08080808,
+		.phy0_dq = 0x08080808,
+		.phy1_dq = 0x08080808,
+		.phy0_tFS = 0x8,
+		.phy1_tFS = 0x8,
+		.phy0_pulld_dqs = 0xf,
+		.phy1_pulld_dqs = 0xf,
+
+		.lpddr3_ctrl_phy_reset = 0x1,
+		.ctrl_start_point = 0x10,
+		.ctrl_inc = 0x10,
+		.ctrl_start = 0x1,
+		.ctrl_dll_on = 0x1,
+		.ctrl_ref = 0x8,
+
+		.ctrl_force = 0x1a,
+		.ctrl_rdlat = 0x0b,
+		.ctrl_bstlen = 0x08,
+
+		.fp_resync = 0x8,
+		.iv_size = 0x7,
+		.dfi_init_start = 1,
+		.aref_en = 1,
+
+		.rd_fetch = 0x3,
+
+		.zq_mode_dds = 0x5,
+		.zq_mode_term = 0x1,
+		.zq_mode_noterm = 1,
+
+		/*
+		* Dynamic Clock: Always Running
+		* Memory Burst length: 8
+		* Number of chips: 1
+		* Memory Bus width: 32 bit
+		* Memory Type: DDR3
+		* Additional Latancy for PLL: 0 Cycle
+		*/
+		.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_DISABLE |
+			DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+			DMC_MEMCONTROL_TP_DISABLE |
+			DMC_MEMCONTROL_DSREF_ENABLE |
+			DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+			DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+			DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+			DMC_MEMCONTROL_NUM_CHIP_1 |
+			DMC_MEMCONTROL_BL_8 |
+			DMC_MEMCONTROL_PZQ_DISABLE |
+			DMC_MEMCONTROL_MRR_BYTE_7_0,
+		.memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
+			DMC_MEMCONFIGX_CHIP_COL_10 |
+			DMC_MEMCONFIGX_CHIP_ROW_15 |
+			DMC_MEMCONFIGX_CHIP_BANK_8,
+		.membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
+		.membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
+		.prechconfig_tp_cnt = 0xff,
+		.dpwrdn_cyc = 0xff,
+		.dsref_cyc = 0xffff,
+		.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+			DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+			DMC_CONCONTROL_RD_FETCH_DISABLE |
+			DMC_CONCONTROL_EMPTY_DISABLE |
+			DMC_CONCONTROL_AREF_EN_DISABLE |
+			DMC_CONCONTROL_IO_PD_CON_DISABLE,
+		.dmc_channels = 2,
+		.chips_per_channel = 2,
+		.chips_to_configure = 1,
+		.send_zq_init = 1,
+		.impedance = IMP_OUTPUT_DRV_40_OHM,
+		.gate_leveling_enable = 1,
+	}
+#endif
+};
+
+/**
+ * Get the required memory type and speed (SPL version).
+ *
+ * In SPL we have no device tree, so we use the machine parameters
+ *
+ * @param mem_type	Returns memory type
+ * @param frequency_mhz	Returns memory speed in MHz
+ * @param arm_freq	Returns ARM clock speed in MHz
+ * @param mem_manuf	Return Memory Manufacturer name
+ */
+static void clock_get_mem_selection(enum ddr_mode *mem_type,
+		unsigned *frequency_mhz, unsigned *arm_freq,
+		enum mem_manuf *mem_manuf)
+{
+	struct spl_machine_param *params;
+
+	params = spl_get_machine_params();
+	*mem_type = params->mem_type;
+	*frequency_mhz = params->frequency_mhz;
+	*arm_freq = params->arm_freq_mhz;
+	*mem_manuf = params->mem_manuf;
+}
+
+/* Get the ratios for setting ARM clock */
+struct arm_clk_ratios *get_arm_ratios(void)
+{
+	struct arm_clk_ratios *arm_ratio;
+	enum ddr_mode mem_type;
+	enum mem_manuf mem_manuf;
+	unsigned frequency_mhz, arm_freq;
+	int i;
+
+	clock_get_mem_selection(&mem_type, &frequency_mhz,
+				&arm_freq, &mem_manuf);
+
+	for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
+		i++, arm_ratio++) {
+		if (arm_ratio->arm_freq_mhz == arm_freq)
+			return arm_ratio;
+	}
+
+	/* will hang if failed to find clock ratio */
+	while (1)
+		;
+
+	return NULL;
+}
+
+struct mem_timings *clock_get_mem_timings(void)
+{
+	struct mem_timings *mem;
+	enum ddr_mode mem_type;
+	enum mem_manuf mem_manuf;
+	unsigned frequency_mhz, arm_freq;
+	int i;
+
+	clock_get_mem_selection(&mem_type, &frequency_mhz,
+				&arm_freq, &mem_manuf);
+	for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
+	     i++, mem++) {
+		if (mem->mem_type == mem_type &&
+		    mem->frequency_mhz == frequency_mhz &&
+		    mem->mem_manuf == mem_manuf)
+			return mem;
+	}
+
+	/* will hang if failed to find memory timings */
+	while (1)
+		;
+
+	return NULL;
+}
+
+static void exynos5250_system_clock_init(void)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	struct mem_timings *mem;
+	struct arm_clk_ratios *arm_clk_ratio;
+	u32 val, tmp;
+
+	mem = clock_get_mem_timings();
+	arm_clk_ratio = get_arm_ratios();
+
+	clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
+	do {
+		val = readl(&clk->mux_stat_cpu);
+	} while ((val | MUX_APLL_SEL_MASK) != val);
+
+	clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
+	do {
+		val = readl(&clk->mux_stat_core1);
+	} while ((val | MUX_MPLL_SEL_MASK) != val);
+
+	clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
+	clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
+	clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
+	clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
+	tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
+		| MUX_GPLL_SEL_MASK;
+	do {
+		val = readl(&clk->mux_stat_top2);
+	} while ((val | tmp) != val);
+
+	clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
+	do {
+		val = readl(&clk->mux_stat_cdrex);
+	} while ((val | MUX_BPLL_SEL_MASK) != val);
+
+	/* PLL locktime */
+	writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
+	writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
+	writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
+	writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
+	writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
+	writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
+	writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
+
+	writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
+
+	writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
+	do {
+		val = readl(&clk->mux_stat_cpu);
+	} while ((val | HPM_SEL_SCLK_MPLL) != val);
+
+	val = arm_clk_ratio->arm2_ratio << 28
+		| arm_clk_ratio->apll_ratio << 24
+		| arm_clk_ratio->pclk_dbg_ratio << 20
+		| arm_clk_ratio->atb_ratio << 16
+		| arm_clk_ratio->periph_ratio << 12
+		| arm_clk_ratio->acp_ratio << 8
+		| arm_clk_ratio->cpud_ratio << 4
+		| arm_clk_ratio->arm_ratio;
+	writel(val, &clk->div_cpu0);
+	do {
+		val = readl(&clk->div_stat_cpu0);
+	} while (0 != val);
+
+	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+	do {
+		val = readl(&clk->div_stat_cpu1);
+	} while (0 != val);
+
+	/* Set APLL */
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
+			arm_clk_ratio->apll_sdiv);
+	writel(val, &clk->apll_con0);
+	while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
+		;
+
+	/* Set MPLL */
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+	writel(val, &clk->mpll_con0);
+	while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
+		;
+
+	/* Set BPLL */
+	writel(BPLL_CON1_VAL, &clk->bpll_con1);
+	val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
+	writel(val, &clk->bpll_con0);
+	while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
+		;
+
+	/* Set CPLL */
+	writel(CPLL_CON1_VAL, &clk->cpll_con1);
+	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
+	writel(val, &clk->cpll_con0);
+	while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
+		;
+
+	/* Set GPLL */
+	writel(GPLL_CON1_VAL, &clk->gpll_con1);
+	val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
+	writel(val, &clk->gpll_con0);
+	while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
+		;
+
+	/* Set EPLL */
+	writel(EPLL_CON2_VAL, &clk->epll_con2);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+	writel(val, &clk->epll_con0);
+	while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
+		;
+
+	/* Set VPLL */
+	writel(VPLL_CON2_VAL, &clk->vpll_con2);
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
+	writel(val, &clk->vpll_con0);
+	while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
+		;
+
+	writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
+	writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
+	while (readl(&clk->div_stat_core0) != 0)
+		;
+
+	writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
+	while (readl(&clk->div_stat_core1) != 0)
+		;
+
+	writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
+	while (readl(&clk->div_stat_sysrgt) != 0)
+		;
+
+	writel(CLK_DIV_ACP_VAL, &clk->div_acp);
+	while (readl(&clk->div_stat_acp) != 0)
+		;
+
+	writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
+	while (readl(&clk->div_stat_syslft) != 0)
+		;
+
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	writel(TOP2_VAL, &clk->src_top2);
+	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+
+	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+	while (readl(&clk->div_stat_top0))
+		;
+
+	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+	while (readl(&clk->div_stat_top1))
+		;
+
+	writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+	while (1) {
+		val = readl(&clk->mux_stat_lex);
+		if (val == (val | 1))
+			break;
+	}
+
+	writel(CLK_DIV_LEX_VAL, &clk->div_lex);
+	while (readl(&clk->div_stat_lex))
+		;
+
+	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+	while (readl(&clk->div_stat_r0x))
+		;
+
+	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+	while (readl(&clk->div_stat_r0x))
+		;
+
+	writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
+	while (readl(&clk->div_stat_r1x))
+		;
+
+	writel(CLK_REG_DISABLE, &clk->src_cdrex);
+
+	writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
+	while (readl(&clk->div_stat_cdrex))
+		;
+
+	val = readl(&clk->src_cpu);
+	val |= CLK_SRC_CPU_VAL;
+	writel(val, &clk->src_cpu);
+
+	val = readl(&clk->src_top2);
+	val |= CLK_SRC_TOP2_VAL;
+	writel(val, &clk->src_top2);
+
+	val = readl(&clk->src_core1);
+	val |= CLK_SRC_CORE1_VAL;
+	writel(val, &clk->src_core1);
+
+	writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
+	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+	while (readl(&clk->div_stat_fsys0))
+		;
+
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
+	writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
+
+	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+
+	writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
+	writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
+	writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
+	writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+
+	writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
+	writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
+	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+	writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
+
+	/* FIMD1 SRC CLK SELECTION */
+	writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
+
+	val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
+		| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
+		| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
+		| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
+	writel(val, &clk->div_fsys2);
+}
+
+static void exynos5420_system_clock_init(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	struct mem_timings *mem;
+	struct arm_clk_ratios *arm_clk_ratio;
+	u32 val;
+
+	mem = clock_get_mem_timings();
+	arm_clk_ratio = get_arm_ratios();
+
+	/* PLL locktime */
+	writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
+	writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
+	writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
+	writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
+	writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
+	writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
+	writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
+	writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
+	writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
+	writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
+
+	setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
+
+	writel(0, &clk->src_top6);
+
+	writel(0, &clk->src_cdrex);
+	writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
+	writel(HPM_RATIO,  &clk->div_cpu1);
+	writel(CLK_DIV_CPU0_VAL,  &clk->div_cpu0);
+
+	/* switch A15 clock source to OSC clock before changing APLL */
+	clrbits_le32(&clk->src_cpu, APLL_FOUT);
+
+	/* Set APLL */
+	writel(APLL_CON1_VAL, &clk->apll_con1);
+	val = set_pll(arm_clk_ratio->apll_mdiv,
+		      arm_clk_ratio->apll_pdiv,
+		      arm_clk_ratio->apll_sdiv);
+	writel(val, &clk->apll_con0);
+	while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* now it is safe to switch to APLL */
+	setbits_le32(&clk->src_cpu, APLL_FOUT);
+
+	writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
+	writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
+
+	/* switch A7 clock source to OSC clock before changing KPLL */
+	clrbits_le32(&clk->src_kfc, KPLL_FOUT);
+
+	/* Set KPLL*/
+	writel(KPLL_CON1_VAL, &clk->kpll_con1);
+	val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
+	writel(val, &clk->kpll_con0);
+	while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* now it is safe to switch to KPLL */
+	setbits_le32(&clk->src_kfc, KPLL_FOUT);
+
+	/* Set MPLL */
+	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+	writel(val, &clk->mpll_con0);
+	while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set DPLL */
+	writel(DPLL_CON1_VAL, &clk->dpll_con1);
+	val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
+	writel(val, &clk->dpll_con0);
+	while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set EPLL */
+	writel(EPLL_CON2_VAL, &clk->epll_con2);
+	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+	writel(val, &clk->epll_con0);
+	while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set CPLL */
+	writel(CPLL_CON1_VAL, &clk->cpll_con1);
+	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
+	writel(val, &clk->cpll_con0);
+	while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set IPLL */
+	writel(IPLL_CON1_VAL, &clk->ipll_con1);
+	val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
+	writel(val, &clk->ipll_con0);
+	while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set VPLL */
+	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
+	writel(val, &clk->vpll_con0);
+	while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set BPLL */
+	writel(BPLL_CON1_VAL, &clk->bpll_con1);
+	val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
+	writel(val, &clk->bpll_con0);
+	while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
+		;
+
+	/* Set SPLL */
+	writel(SPLL_CON1_VAL, &clk->spll_con1);
+	val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
+	writel(val, &clk->spll_con0);
+	while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
+		;
+
+	writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
+	writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
+
+	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+	writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
+	writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
+
+	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+	writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
+
+	writel(0, &clk->src_top10);
+	writel(0, &clk->src_top11);
+	writel(0, &clk->src_top12);
+
+	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+	writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
+	writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
+
+	/* DISP1 BLK CLK SELECTION */
+	writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
+	writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
+
+	/* AUDIO BLK */
+	writel(AUDIO0_SEL_EPLL, &clk->src_mau);
+	writel(DIV_MAU_VAL, &clk->div_mau);
+
+	/* FSYS */
+	writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
+	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+	writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+	writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+
+	writel(CLK_SRC_ISP_VAL, &clk->src_isp);
+	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+
+	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+	writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
+
+	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+	writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
+	writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
+	writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+	writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
+
+	writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
+
+	writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
+	writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
+	writel(CLK_DIV_G2D, &clk->div_g2d);
+
+	writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
+	writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
+	writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
+}
+
+void system_clock_init(void)
+{
+	if (proid_is_exynos5420())
+		exynos5420_system_clock_init();
+	else
+		exynos5250_system_clock_init();
+}
+
+void clock_init_dp_clock(void)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+
+	/* DP clock enable */
+	setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
+
+	/* We run DP at 267 Mhz */
+	setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
+}
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
+ */
+void emmc_boot_clk_div_set(void)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned int div_mmc;
+
+	div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
+	div_mmc |= FSYS1_MMC0_DIV_VAL;
+	writel(div_mmc, (unsigned int) &clk->div_fsys1);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/common_setup.h b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/common_setup.h
new file mode 100644
index 000000000..e6318c036
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/common_setup.h
@@ -0,0 +1,45 @@
+/*
+ * Common APIs for EXYNOS based board
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define DMC_OFFSET	0x10000
+
+/*
+ * Memory initialization
+ *
+ * @param reset     Reset PHY during initialization.
+ */
+void mem_ctrl_init(int reset);
+
+ /* System Clock initialization */
+void system_clock_init(void);
+
+/*
+ * Init subsystems according to the reset status
+ *
+ * @return 0 for a normal boot, non-zero for a resume
+ */
+int do_lowlevel_init(void);
+
+void sdelay(unsigned long);
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/config.mk b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/config.mk
new file mode 100644
index 000000000..ee0d2dab7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (C) Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+SPL_OBJCFLAGS += -j .machine_param
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_common.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_common.c
new file mode 100644
index 000000000..cca925e42
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_common.c
@@ -0,0 +1,176 @@
+/*
+ * Mem setup common file for different types of DDR present on Exynos boards.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/spl.h>
+
+#include "clock_init.h"
+#include "common_setup.h"
+#include "exynos5_setup.h"
+
+#define ZQ_INIT_TIMEOUT	10000
+
+int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
+			uint32_t *phy1_con16, uint32_t *phy0_con17,
+			uint32_t *phy1_con17)
+{
+	unsigned long val = 0;
+	int i;
+
+	/*
+	 * ZQ Calibration:
+	 * Select Driver Strength,
+	 * long calibration for manual calibration
+	 */
+	val = PHY_CON16_RESET_VAL;
+	val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
+	val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
+	val |= ZQ_CLK_DIV_EN;
+	writel(val, phy0_con16);
+	writel(val, phy1_con16);
+
+	/* Disable termination */
+	if (mem->zq_mode_noterm)
+		val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
+	writel(val, phy0_con16);
+	writel(val, phy1_con16);
+
+	/* ZQ_MANUAL_START: Enable */
+	val |= ZQ_MANUAL_STR;
+	writel(val, phy0_con16);
+	writel(val, phy1_con16);
+
+	/* ZQ_MANUAL_START: Disable */
+	val &= ~ZQ_MANUAL_STR;
+
+	/*
+	 * Since we are manaully calibrating the ZQ values,
+	 * we are looping for the ZQ_init to complete.
+	 */
+	i = ZQ_INIT_TIMEOUT;
+	while ((readl(phy0_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+		sdelay(100);
+		i--;
+	}
+	if (!i)
+		return -1;
+	writel(val, phy0_con16);
+
+	i = ZQ_INIT_TIMEOUT;
+	while ((readl(phy1_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+		sdelay(100);
+		i--;
+	}
+	if (!i)
+		return -1;
+	writel(val, phy1_con16);
+
+	return 0;
+}
+
+void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode)
+{
+	unsigned long val;
+
+	if (mode == DDR_MODE_DDR3) {
+		val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
+		writel(val, phycontrol0);
+	}
+
+	/* Update DLL Information: Force DLL Resyncronization */
+	val = readl(phycontrol0);
+	val |= FP_RSYNC;
+	writel(val, phycontrol0);
+
+	/* Reset Force DLL Resyncronization */
+	val = readl(phycontrol0);
+	val &= ~FP_RSYNC;
+	writel(val, phycontrol0);
+}
+
+void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd)
+{
+	int channel, chip;
+
+	for (channel = 0; channel < mem->dmc_channels; channel++) {
+		unsigned long mask;
+
+		mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
+		for (chip = 0; chip < mem->chips_to_configure; chip++) {
+			int i;
+
+			mask |= chip << DIRECT_CMD_CHIP_SHIFT;
+
+			/* Sending NOP command */
+			writel(DIRECT_CMD_NOP | mask, directcmd);
+
+			/*
+			 * TODO(alim.akhtar@samsung.com): Do we need these
+			 * delays? This one and the next were not there for
+			 * DDR3.
+			 */
+			sdelay(0x10000);
+
+			/* Sending EMRS/MRS commands */
+			for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
+				writel(mem->direct_cmd_msr[i] | mask,
+				       directcmd);
+				sdelay(0x10000);
+			}
+
+			if (mem->send_zq_init) {
+				/* Sending ZQINIT command */
+				writel(DIRECT_CMD_ZQINIT | mask,
+				       directcmd);
+
+				sdelay(10000);
+			}
+		}
+	}
+}
+
+void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd)
+{
+	int channel, chip;
+
+	for (channel = 0; channel < mem->dmc_channels; channel++) {
+		unsigned long mask;
+
+		mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
+		for (chip = 0; chip < mem->chips_per_channel; chip++) {
+			mask |= chip << DIRECT_CMD_CHIP_SHIFT;
+
+			/* PALL (all banks precharge) CMD */
+			writel(DIRECT_CMD_PALL | mask, directcmd);
+			sdelay(0x10000);
+		}
+	}
+}
+
+void mem_ctrl_init(int reset)
+{
+	struct spl_machine_param *param = spl_get_machine_params();
+	struct mem_timings *mem;
+	int ret;
+
+	mem = clock_get_mem_timings();
+
+	/* If there are any other memory variant, add their init call below */
+	if (param->mem_type == DDR_MODE_DDR3) {
+		ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
+		if (ret) {
+			/* will hang if failed to init memory control */
+			while (1)
+				;
+		}
+	} else {
+		/* will hang if unknow memory type  */
+		while (1)
+			;
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
new file mode 100644
index 000000000..487e6f423
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -0,0 +1,636 @@
+/*
+ * DDR3 mem setup file for board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
+#include "common_setup.h"
+#include "exynos5_setup.h"
+#include "clock_init.h"
+
+#define TIMEOUT	10000
+
+#ifdef CONFIG_EXYNOS5250
+static void reset_phy_ctrl(void)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+
+	writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
+	writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
+}
+
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+		       int reset)
+{
+	unsigned int val;
+	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
+	struct exynos5_dmc *dmc;
+	int i;
+
+	phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
+	phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
+							+ DMC_OFFSET);
+	dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
+
+	if (reset)
+		reset_phy_ctrl();
+
+	/* Set Impedance Output Driver */
+	val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
+		(mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
+		(mem->impedance << CA_CS_DRVR_DS_OFFSET) |
+		(mem->impedance << CA_ADR_DRVR_DS_OFFSET);
+	writel(val, &phy0_ctrl->phy_con39);
+	writel(val, &phy1_ctrl->phy_con39);
+
+	/* Set Read Latency and Burst Length for PHY0 and PHY1 */
+	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
+		(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
+	writel(val, &phy0_ctrl->phy_con42);
+	writel(val, &phy1_ctrl->phy_con42);
+
+	/* ZQ Calibration */
+	if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
+			  &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
+		return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
+
+	/* DQ Signal */
+	writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
+	writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
+
+	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
+		| (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
+		&dmc->concontrol);
+
+	update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
+
+	/* DQS Signal */
+	writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
+	writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
+
+	writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
+	writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
+
+	writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
+	writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
+
+	val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
+		(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
+		(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
+		(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
+	writel(val, &phy0_ctrl->phy_con12);
+	writel(val, &phy1_ctrl->phy_con12);
+
+	/* Start DLL locking */
+	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
+	       &phy0_ctrl->phy_con12);
+	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
+	       &phy1_ctrl->phy_con12);
+
+	update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
+
+	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+	       &dmc->concontrol);
+
+	/* Memory Channel Inteleaving Size */
+	writel(mem->iv_size, &dmc->ivcontrol);
+
+	writel(mem->memconfig, &dmc->memconfig0);
+	writel(mem->memconfig, &dmc->memconfig1);
+	writel(mem->membaseconfig0, &dmc->membaseconfig0);
+	writel(mem->membaseconfig1, &dmc->membaseconfig1);
+
+	/* Precharge Configuration */
+	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+	       &dmc->prechconfig);
+
+	/* Power Down mode Configuration */
+	writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
+		mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
+		&dmc->pwrdnconfig);
+
+	/* TimingRow, TimingData, TimingPower and Timingaref
+	 * values as per Memory AC parameters
+	 */
+	writel(mem->timing_ref, &dmc->timingref);
+	writel(mem->timing_row, &dmc->timingrow);
+	writel(mem->timing_data, &dmc->timingdata);
+	writel(mem->timing_power, &dmc->timingpower);
+
+	/* Send PALL command */
+	dmc_config_prech(mem, &dmc->directcmd);
+
+	/* Send NOP, MRS and ZQINIT commands */
+	dmc_config_mrs(mem, &dmc->directcmd);
+
+	if (mem->gate_leveling_enable) {
+		val = PHY_CON0_RESET_VAL;
+		val |= P0_CMD_EN;
+		writel(val, &phy0_ctrl->phy_con0);
+		writel(val, &phy1_ctrl->phy_con0);
+
+		val = PHY_CON2_RESET_VAL;
+		val |= INIT_DESKEW_EN;
+		writel(val, &phy0_ctrl->phy_con2);
+		writel(val, &phy1_ctrl->phy_con2);
+
+		val = PHY_CON0_RESET_VAL;
+		val |= P0_CMD_EN;
+		val |= BYTE_RDLVL_EN;
+		writel(val, &phy0_ctrl->phy_con0);
+		writel(val, &phy1_ctrl->phy_con0);
+
+		val = (mem->ctrl_start_point <<
+				PHY_CON12_CTRL_START_POINT_SHIFT) |
+			(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
+			(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
+			(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
+			(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
+		writel(val, &phy0_ctrl->phy_con12);
+		writel(val, &phy1_ctrl->phy_con12);
+
+		val = PHY_CON2_RESET_VAL;
+		val |= INIT_DESKEW_EN;
+		val |= RDLVL_GATE_EN;
+		writel(val, &phy0_ctrl->phy_con2);
+		writel(val, &phy1_ctrl->phy_con2);
+
+		val = PHY_CON0_RESET_VAL;
+		val |= P0_CMD_EN;
+		val |= BYTE_RDLVL_EN;
+		val |= CTRL_SHGATE;
+		writel(val, &phy0_ctrl->phy_con0);
+		writel(val, &phy1_ctrl->phy_con0);
+
+		val = PHY_CON1_RESET_VAL;
+		val &= ~(CTRL_GATEDURADJ_MASK);
+		writel(val, &phy0_ctrl->phy_con1);
+		writel(val, &phy1_ctrl->phy_con1);
+
+		writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
+		i = TIMEOUT;
+		while ((readl(&dmc->phystatus) &
+			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
+			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
+			/*
+			 * TODO(waihong): Comment on how long this take to
+			 * timeout
+			 */
+			sdelay(100);
+			i--;
+		}
+		if (!i)
+			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+		writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
+
+		writel(0, &phy0_ctrl->phy_con14);
+		writel(0, &phy1_ctrl->phy_con14);
+
+		val = (mem->ctrl_start_point <<
+				PHY_CON12_CTRL_START_POINT_SHIFT) |
+			(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
+			(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
+			(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
+			(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
+			(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
+		writel(val, &phy0_ctrl->phy_con12);
+		writel(val, &phy1_ctrl->phy_con12);
+
+		update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
+	}
+
+	/* Send PALL command */
+	dmc_config_prech(mem, &dmc->directcmd);
+
+	writel(mem->memcontrol, &dmc->memcontrol);
+
+	/* Set DMC Concontrol and enable auto-refresh counter */
+	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
+		| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_EXYNOS5420
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+		       int reset)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	struct exynos5420_power *power =
+		(struct exynos5420_power *)samsung_get_base_power();
+	struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
+	struct exynos5420_dmc *drex0, *drex1;
+	struct exynos5420_tzasc *tzasc0, *tzasc1;
+	uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
+	int chip;
+	int i;
+
+	phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();
+	phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()
+							+ DMC_OFFSET);
+	drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();
+	drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()
+							+ DMC_OFFSET);
+	tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
+	tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
+							+ DMC_OFFSET);
+
+	/* Enable PAUSE for DREX */
+	setbits_le32(&clk->pause, ENABLE_BIT);
+
+	/* Enable BYPASS mode */
+	setbits_le32(&clk->bpll_con1, BYPASS_EN);
+
+	writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
+	do {
+		val = readl(&clk->mux_stat_cdrex);
+		val &= BPLL_SEL_MASK;
+	} while (val != FOUTBPLL);
+
+	clrbits_le32(&clk->bpll_con1, BYPASS_EN);
+
+	/* Specify the DDR memory type as DDR3 */
+	val = readl(&phy0_ctrl->phy_con0);
+	val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+	val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+	writel(val, &phy0_ctrl->phy_con0);
+
+	val = readl(&phy1_ctrl->phy_con0);
+	val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+	val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
+	writel(val, &phy1_ctrl->phy_con0);
+
+	/* Set Read Latency and Burst Length for PHY0 and PHY1 */
+	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
+		(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
+	writel(val, &phy0_ctrl->phy_con42);
+	writel(val, &phy1_ctrl->phy_con42);
+
+	val = readl(&phy0_ctrl->phy_con26);
+	val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
+	val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
+	writel(val, &phy0_ctrl->phy_con26);
+
+	val = readl(&phy1_ctrl->phy_con26);
+	val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
+	val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
+	writel(val, &phy1_ctrl->phy_con26);
+
+	/*
+	 * Set Driver strength for CK, CKE, CS & CA to 0x7
+	 * Set Driver strength for Data Slice 0~3 to 0x7
+	 */
+	val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
+		(0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
+	val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
+		(0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
+	writel(val, &phy0_ctrl->phy_con39);
+	writel(val, &phy1_ctrl->phy_con39);
+
+	/* ZQ Calibration */
+	if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
+			  &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
+		return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
+
+	clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
+	clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
+
+	/* DQ Signal */
+	val = readl(&phy0_ctrl->phy_con14);
+	val |= mem->phy0_pulld_dqs;
+	writel(val, &phy0_ctrl->phy_con14);
+	val = readl(&phy1_ctrl->phy_con14);
+	val |= mem->phy1_pulld_dqs;
+	writel(val, &phy1_ctrl->phy_con14);
+
+	val = MEM_TERM_EN | PHY_TERM_EN;
+	writel(val, &drex0->phycontrol0);
+	writel(val, &drex1->phycontrol0);
+
+	writel(mem->concontrol |
+		(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
+		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+		&drex0->concontrol);
+	writel(mem->concontrol |
+		(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
+		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+		&drex1->concontrol);
+
+	do {
+		val = readl(&drex0->phystatus);
+	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
+	do {
+		val = readl(&drex1->phystatus);
+	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
+
+	clrbits_le32(&drex0->concontrol, DFI_INIT_START);
+	clrbits_le32(&drex1->concontrol, DFI_INIT_START);
+
+	update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
+	update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
+
+	/*
+	 * Set Base Address:
+	 * 0x2000_0000 ~ 0x5FFF_FFFF
+	 * 0x6000_0000 ~ 0x9FFF_FFFF
+	 */
+	/* MEMBASECONFIG0 */
+	val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
+		DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
+	writel(val, &tzasc0->membaseconfig0);
+	writel(val, &tzasc1->membaseconfig0);
+
+	/* MEMBASECONFIG1 */
+	val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
+		DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
+	writel(val, &tzasc0->membaseconfig1);
+	writel(val, &tzasc1->membaseconfig1);
+
+	/*
+	 * Memory Channel Inteleaving Size
+	 * Ares Channel interleaving = 128 bytes
+	 */
+	/* MEMCONFIG0/1 */
+	writel(mem->memconfig, &tzasc0->memconfig0);
+	writel(mem->memconfig, &tzasc1->memconfig0);
+	writel(mem->memconfig, &tzasc0->memconfig1);
+	writel(mem->memconfig, &tzasc1->memconfig1);
+
+	/* Precharge Configuration */
+	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+	       &drex0->prechconfig0);
+	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+	       &drex1->prechconfig0);
+
+	/*
+	 * TimingRow, TimingData, TimingPower and Timingaref
+	 * values as per Memory AC parameters
+	 */
+	writel(mem->timing_ref, &drex0->timingref);
+	writel(mem->timing_ref, &drex1->timingref);
+	writel(mem->timing_row, &drex0->timingrow0);
+	writel(mem->timing_row, &drex1->timingrow0);
+	writel(mem->timing_data, &drex0->timingdata0);
+	writel(mem->timing_data, &drex1->timingdata0);
+	writel(mem->timing_power, &drex0->timingpower0);
+	writel(mem->timing_power, &drex1->timingpower0);
+
+	if (reset) {
+		/*
+		 * Send NOP, MRS and ZQINIT commands
+		 * Sending MRS command will reset the DRAM. We should not be
+		 * reseting the DRAM after resume, this will lead to memory
+		 * corruption as DRAM content is lost after DRAM reset
+		 */
+		dmc_config_mrs(mem, &drex0->directcmd);
+		dmc_config_mrs(mem, &drex1->directcmd);
+	} else {
+		/*
+		 * During Suspend-Resume & S/W-Reset, as soon as PMU releases
+		 * pad retention, CKE goes high. This causes memory contents
+		 * not to be retained during DRAM initialization. Therfore,
+		 * there is a new control register(0x100431e8[28]) which lets us
+		 * release pad retention and retain the memory content until the
+		 * initialization is complete.
+		 */
+		writel(PAD_RETENTION_DRAM_COREBLK_VAL,
+		       &power->pad_retention_dram_coreblk_option);
+		do {
+			val = readl(&power->pad_retention_dram_status);
+		} while (val != 0x1);
+
+		/*
+		 * CKE PAD retention disables DRAM self-refresh mode.
+		 * Send auto refresh command for DRAM refresh.
+		 */
+		for (i = 0; i < 128; i++) {
+			for (chip = 0; chip < mem->chips_to_configure; chip++) {
+				writel(DIRECT_CMD_REFA |
+				       (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex0->directcmd);
+				writel(DIRECT_CMD_REFA |
+				       (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex1->directcmd);
+			}
+		}
+	}
+
+	if (mem->gate_leveling_enable) {
+		writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
+		writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
+
+		setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
+		setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
+
+		val = PHY_CON2_RESET_VAL;
+		val |= INIT_DESKEW_EN;
+		writel(val, &phy0_ctrl->phy_con2);
+		writel(val, &phy1_ctrl->phy_con2);
+
+		val =  readl(&phy0_ctrl->phy_con1);
+		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
+		writel(val, &phy0_ctrl->phy_con1);
+
+		val =  readl(&phy1_ctrl->phy_con1);
+		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
+		writel(val, &phy1_ctrl->phy_con1);
+
+		n_lock_r = readl(&phy0_ctrl->phy_con13);
+		n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
+		n_lock_r = readl(&phy0_ctrl->phy_con12);
+		n_lock_r &= ~CTRL_DLL_ON;
+		n_lock_r |= n_lock_w_phy0;
+		writel(n_lock_r, &phy0_ctrl->phy_con12);
+
+		n_lock_r = readl(&phy1_ctrl->phy_con13);
+		n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
+		n_lock_r = readl(&phy1_ctrl->phy_con12);
+		n_lock_r &= ~CTRL_DLL_ON;
+		n_lock_r |= n_lock_w_phy1;
+		writel(n_lock_r, &phy1_ctrl->phy_con12);
+
+		val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
+		for (chip = 0; chip < mem->chips_to_configure; chip++) {
+			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+			       &drex0->directcmd);
+			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+			       &drex1->directcmd);
+		}
+
+		setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
+		setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
+
+		setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
+		setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
+
+		val = readl(&phy0_ctrl->phy_con1);
+		val &= ~(CTRL_GATEDURADJ_MASK);
+		writel(val, &phy0_ctrl->phy_con1);
+
+		val = readl(&phy1_ctrl->phy_con1);
+		val &= ~(CTRL_GATEDURADJ_MASK);
+		writel(val, &phy1_ctrl->phy_con1);
+
+		writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
+		i = TIMEOUT;
+		while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
+			RDLVL_COMPLETE_CHO) && (i > 0)) {
+			/*
+			 * TODO(waihong): Comment on how long this take to
+			 * timeout
+			 */
+			sdelay(100);
+			i--;
+		}
+		if (!i)
+			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+		writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
+
+		writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
+		i = TIMEOUT;
+		while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
+			RDLVL_COMPLETE_CHO) && (i > 0)) {
+			/*
+			 * TODO(waihong): Comment on how long this take to
+			 * timeout
+			 */
+			sdelay(100);
+			i--;
+		}
+		if (!i)
+			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+		writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
+
+		writel(0, &phy0_ctrl->phy_con14);
+		writel(0, &phy1_ctrl->phy_con14);
+
+		val = (0x3 << DIRECT_CMD_BANK_SHIFT);
+		for (chip = 0; chip < mem->chips_to_configure; chip++) {
+			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+			       &drex0->directcmd);
+			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+			       &drex1->directcmd);
+		}
+
+		if (mem->read_leveling_enable) {
+			/* Set Read DQ Calibration */
+			val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
+			for (chip = 0; chip < mem->chips_to_configure; chip++) {
+				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex0->directcmd);
+				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex1->directcmd);
+			}
+
+			val = readl(&phy0_ctrl->phy_con1);
+			val |= READ_LEVELLING_DDR3;
+			writel(val, &phy0_ctrl->phy_con1);
+			val = readl(&phy1_ctrl->phy_con1);
+			val |= READ_LEVELLING_DDR3;
+			writel(val, &phy1_ctrl->phy_con1);
+
+			val = readl(&phy0_ctrl->phy_con2);
+			val |= (RDLVL_EN | RDLVL_INCR_ADJ);
+			writel(val, &phy0_ctrl->phy_con2);
+			val = readl(&phy1_ctrl->phy_con2);
+			val |= (RDLVL_EN | RDLVL_INCR_ADJ);
+			writel(val, &phy1_ctrl->phy_con2);
+
+			setbits_le32(&drex0->rdlvl_config,
+				     CTRL_RDLVL_DATA_ENABLE);
+			i = TIMEOUT;
+			while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO)
+				 != RDLVL_COMPLETE_CHO) && (i > 0)) {
+				/*
+				 * TODO(waihong): Comment on how long this take
+				 * to timeout
+				 */
+				sdelay(100);
+				i--;
+			}
+			if (!i)
+				return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+
+			clrbits_le32(&drex0->rdlvl_config,
+				     CTRL_RDLVL_DATA_ENABLE);
+			setbits_le32(&drex1->rdlvl_config,
+				     CTRL_RDLVL_DATA_ENABLE);
+			i = TIMEOUT;
+			while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO)
+				 != RDLVL_COMPLETE_CHO) && (i > 0)) {
+				/*
+				 * TODO(waihong): Comment on how long this take
+				 * to timeout
+				 */
+				sdelay(100);
+				i--;
+			}
+			if (!i)
+				return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+
+			clrbits_le32(&drex1->rdlvl_config,
+				     CTRL_RDLVL_DATA_ENABLE);
+
+			val = (0x3 << DIRECT_CMD_BANK_SHIFT);
+			for (chip = 0; chip < mem->chips_to_configure; chip++) {
+				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex0->directcmd);
+				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+				       &drex1->directcmd);
+			}
+
+			update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
+			update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
+		}
+
+		/* Common Settings for Leveling */
+		val = PHY_CON12_RESET_VAL;
+		writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
+		writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
+
+		setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
+		setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
+	}
+
+	/* Send PALL command */
+	dmc_config_prech(mem, &drex0->directcmd);
+	dmc_config_prech(mem, &drex1->directcmd);
+
+	writel(mem->memcontrol, &drex0->memcontrol);
+	writel(mem->memcontrol, &drex1->memcontrol);
+
+	/*
+	 * Set DMC Concontrol: Enable auto-refresh counter, provide
+	 * read data fetch cycles and enable DREX auto set powerdown
+	 * for input buffer of I/O in none read memory state.
+	 */
+	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
+		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
+		DMC_CONCONTROL_IO_PD_CON(0x2),
+		&drex0->concontrol);
+	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
+		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
+		DMC_CONCONTROL_IO_PD_CON(0x2),
+		&drex1->concontrol);
+
+	/*
+	 * Enable Clock Gating Control for DMC
+	 * this saves around 25 mw dmc power as compared to the power
+	 * consumption without these bits enabled
+	 */
+	setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
+	setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
+
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c
new file mode 100644
index 000000000..ecddc7268
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c
@@ -0,0 +1,213 @@
+/*
+ * Memory setup for board based on EXYNOS4210
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/dmc.h>
+#include "common_setup.h"
+#include "exynos4_setup.h"
+
+struct mem_timings mem = {
+	.direct_cmd_msr = {
+		DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4
+	},
+	.timingref = TIMINGREF_VAL,
+	.timingrow = TIMINGROW_VAL,
+	.timingdata = TIMINGDATA_VAL,
+	.timingpower = TIMINGPOWER_VAL,
+	.zqcontrol = ZQ_CONTROL_VAL,
+	.control0 = CONTROL0_VAL,
+	.control1 = CONTROL1_VAL,
+	.control2 = CONTROL2_VAL,
+	.concontrol = CONCONTROL_VAL,
+	.prechconfig = PRECHCONFIG,
+	.memcontrol = MEMCONTROL_VAL,
+	.memconfig0 = MEMCONFIG0_VAL,
+	.memconfig1 = MEMCONFIG1_VAL,
+	.dll_resync = FORCE_DLL_RESYNC,
+	.dll_on = DLL_CONTROL_ON,
+};
+static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)
+{
+	if (ctrl_no) {
+		writel((mem.control1 | (1 << mem.dll_resync)),
+		       &dmc->phycontrol1);
+		writel((mem.control1 | (0 << mem.dll_resync)),
+		       &dmc->phycontrol1);
+	} else {
+		writel((mem.control0 | (0 << mem.dll_on)),
+		       &dmc->phycontrol0);
+		writel((mem.control0 | (1 << mem.dll_on)),
+		       &dmc->phycontrol0);
+	}
+}
+
+static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)
+{
+	int i;
+	unsigned long mask = 0;
+
+	if (chip)
+		mask = DIRECT_CMD_CHIP1_SHIFT;
+
+	for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
+		writel(mem.direct_cmd_msr[i] | mask,
+		       &dmc->directcmd);
+	}
+}
+
+static void dmc_init(struct exynos4_dmc *dmc)
+{
+	/*
+	 * DLL Parameter Setting:
+	 * Termination: Enable R/W
+	 * Phase Delay for DQS Cleaning: 180' Shift
+	 */
+	writel(mem.control1, &dmc->phycontrol1);
+
+	/*
+	 * ZQ Calibration
+	 * Termination: Disable
+	 * Auto Calibration Start: Enable
+	 */
+	writel(mem.zqcontrol, &dmc->phyzqcontrol);
+	sdelay(0x100000);
+
+	/*
+	 * Update DLL Information:
+	 * Force DLL Resyncronization
+	 */
+	phy_control_reset(1, dmc);
+	phy_control_reset(0, dmc);
+
+	/* Set DLL Parameters */
+	writel(mem.control1, &dmc->phycontrol1);
+
+	/* DLL Start */
+	writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0);
+
+	writel(mem.control2, &dmc->phycontrol2);
+
+	/* Set Clock Ratio of Bus clock to Memory Clock */
+	writel(mem.concontrol, &dmc->concontrol);
+
+	/*
+	 * Memor Burst length: 8
+	 * Number of chips: 2
+	 * Memory Bus width: 32 bit
+	 * Memory Type: DDR3
+	 * Additional Latancy for PLL: 1 Cycle
+	 */
+	writel(mem.memcontrol, &dmc->memcontrol);
+
+	writel(mem.memconfig0, &dmc->memconfig0);
+	writel(mem.memconfig1, &dmc->memconfig1);
+
+	/* Config Precharge Policy */
+	writel(mem.prechconfig, &dmc->prechconfig);
+	/*
+	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
+	 * Values as per Memory AC Parameters
+	 */
+	writel(mem.timingref, &dmc->timingref);
+	writel(mem.timingrow, &dmc->timingrow);
+	writel(mem.timingdata, &dmc->timingdata);
+	writel(mem.timingpower, &dmc->timingpower);
+
+	/* Chip0: NOP Command: Assert and Hold CKE to high level */
+	writel(DIRECT_CMD_NOP, &dmc->directcmd);
+	sdelay(0x100000);
+
+	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	dmc_config_mrs(dmc, 0);
+	sdelay(0x100000);
+
+	/* Chip0: ZQINIT */
+	writel(DIRECT_CMD_ZQ, &dmc->directcmd);
+	sdelay(0x100000);
+
+	writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
+	sdelay(0x100000);
+
+	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+	dmc_config_mrs(dmc, 1);
+	sdelay(0x100000);
+
+	/* Chip1: ZQINIT */
+	writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
+	sdelay(0x100000);
+
+	phy_control_reset(1, dmc);
+	sdelay(0x100000);
+
+	/* turn on DREX0, DREX1 */
+	writel((mem.concontrol | AREF_EN), &dmc->concontrol);
+}
+
+void mem_ctrl_init(int reset)
+{
+	struct exynos4_dmc *dmc;
+
+	/*
+	 * Async bridge configuration at CPU_core:
+	 * 1: half_sync
+	 * 0: full_sync
+	 */
+	writel(1, ASYNC_CONFIG);
+#ifdef CONFIG_ORIGEN
+	/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+	writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
+		APB_SFR_INTERLEAVE_CONF_OFFSET);
+	/* Update MIU Configuration */
+	writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +
+		APB_SFR_ARBRITATION_CONF_OFFSET);
+#else
+	writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
+		APB_SFR_INTERLEAVE_CONF_OFFSET);
+	writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET);
+	writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET);
+	writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
+#ifdef CONFIG_MIU_LINEAR
+	writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET);
+	writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET);
+	writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET);
+	writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET);
+	writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE +
+		ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
+#endif
+#endif
+	/* DREX0 */
+	dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl();
+	dmc_init(dmc);
+	dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl()
+					+ DMC_OFFSET);
+	dmc_init(dmc);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/exynos4_setup.h b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/exynos4_setup.h
new file mode 100644
index 000000000..b633e5660
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/exynos4_setup.h
@@ -0,0 +1,578 @@
+/*
+ * Machine Specific Values for EXYNOS4012 based board
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ORIGEN_SETUP_H
+#define _ORIGEN_SETUP_H
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200
+#endif
+#ifdef CONFIG_CLK_1000_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_400_200
+#define DRAM_CLK_400
+#endif
+
+/* Bus Configuration Register Address */
+#define ASYNC_CONFIG		0x10010350
+
+/* CLK_SRC_CPU */
+#define MUX_HPM_SEL_MOUTAPLL		0x0
+#define MUX_HPM_SEL_SCLKMPLL		0x1
+#define MUX_CORE_SEL_MOUTAPLL		0x0
+#define MUX_CORE_SEL_SCLKMPLL		0x1
+#define MUX_MPLL_SEL_FILPLL		0x0
+#define MUX_MPLL_SEL_MOUTMPLLFOUT	0x1
+#define MUX_APLL_SEL_FILPLL		0x0
+#define MUX_APLL_SEL_MOUTMPLLFOUT	0x1
+#define CLK_SRC_CPU_VAL			((MUX_HPM_SEL_MOUTAPLL << 20) \
+					| (MUX_CORE_SEL_MOUTAPLL << 16) \
+					| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
+					| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
+
+/* CLK_DIV_CPU0 */
+#define APLL_RATIO		0x0
+#define PCLK_DBG_RATIO		0x1
+#define ATB_RATIO		0x3
+#define PERIPH_RATIO		0x3
+#define COREM1_RATIO		0x7
+#define COREM0_RATIO		0x3
+#define CORE_RATIO		0x0
+#define CLK_DIV_CPU0_VAL	((APLL_RATIO << 24) \
+				| (PCLK_DBG_RATIO << 20) \
+				| (ATB_RATIO << 16) \
+				| (PERIPH_RATIO << 12) \
+				| (COREM1_RATIO << 8) \
+				| (COREM0_RATIO << 4) \
+				| (CORE_RATIO << 0))
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO		0x0
+#define COPY_RATIO		0x3
+#define CLK_DIV_CPU1_VAL	((HPM_RATIO << 4) | (COPY_RATIO))
+
+/* CLK_SRC_DMC */
+#define MUX_PWI_SEL_XXTI		0x0
+#define MUX_PWI_SEL_XUSBXTI		0x1
+#define MUX_PWI_SEL_SCLK_HDMI24M	0x2
+#define MUX_PWI_SEL_SCLK_USBPHY0	0x3
+#define MUX_PWI_SEL_SCLK_USBPHY1	0x4
+#define MUX_PWI_SEL_SCLK_HDMIPHY	0x5
+#define MUX_PWI_SEL_SCLKMPLL		0x6
+#define MUX_PWI_SEL_SCLKEPLL		0x7
+#define MUX_PWI_SEL_SCLKVPLL		0x8
+#define MUX_DPHY_SEL_SCLKMPLL		0x0
+#define MUX_DPHY_SEL_SCLKAPLL		0x1
+#define MUX_DMC_BUS_SEL_SCLKMPLL	0x0
+#define MUX_DMC_BUS_SEL_SCLKAPLL	0x1
+#define CLK_SRC_DMC_VAL			((MUX_PWI_SEL_XUSBXTI << 16) \
+					| (MUX_DPHY_SEL_SCLKMPLL << 8) \
+					| (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
+
+/* CLK_DIV_DMC0 */
+#define CORE_TIMERS_RATIO	0x1
+#define COPY2_RATIO		0x3
+#define DMCP_RATIO		0x1
+#define DMCD_RATIO		0x1
+#define DMC_RATIO		0x1
+#define DPHY_RATIO		0x1
+#define ACP_PCLK_RATIO		0x1
+#define ACP_RATIO		0x3
+#define CLK_DIV_DMC0_VAL	((CORE_TIMERS_RATIO << 28) \
+				| (COPY2_RATIO << 24) \
+				| (DMCP_RATIO << 20) \
+				| (DMCD_RATIO << 16) \
+				| (DMC_RATIO << 12) \
+				| (DPHY_RATIO << 8) \
+				| (ACP_PCLK_RATIO << 4)	\
+				| (ACP_RATIO << 0))
+
+/* CLK_DIV_DMC1 */
+#define DPM_RATIO		0x1
+#define DVSEM_RATIO		0x1
+#define PWI_RATIO		0x1
+#define CLK_DIV_DMC1_VAL	((DPM_RATIO << 24) \
+				| (DVSEM_RATIO << 16) \
+				| (PWI_RATIO << 8))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ONENAND_SEL_ACLK_133	0x0
+#define MUX_ONENAND_SEL_ACLK_160	0x1
+#define MUX_ACLK_133_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_133_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_160_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_160_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_100_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_100_SEL_SCLKAPLL	0x1
+#define MUX_ACLK_200_SEL_SCLKMPLL	0x0
+#define MUX_ACLK_200_SEL_SCLKAPLL	0x1
+#define MUX_VPLL_SEL_FINPLL		0x0
+#define MUX_VPLL_SEL_FOUTVPLL		0x1
+#define MUX_EPLL_SEL_FINPLL		0x0
+#define MUX_EPLL_SEL_FOUTEPLL		0x1
+#define MUX_ONENAND_1_SEL_MOUTONENAND	0x0
+#define MUX_ONENAND_1_SEL_SCLKVPLL	0x1
+#define CLK_SRC_TOP0_VAL		((MUX_ONENAND_SEL_ACLK_133 << 28) \
+					| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
+					| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
+					| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
+					| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
+					| (MUX_VPLL_SEL_FINPLL << 8) \
+					| (MUX_EPLL_SEL_FINPLL << 4)\
+					| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
+
+/* CLK_SRC_TOP1 */
+#define VPLLSRC_SEL_FINPLL	0x0
+#define VPLLSRC_SEL_SCLKHDMI24M	0x1
+#define CLK_SRC_TOP1_VAL	(VPLLSRC_SEL_FINPLL)
+
+/* CLK_DIV_TOP */
+#define ONENAND_RATIO		0x0
+#define ACLK_133_RATIO		0x5
+#define ACLK_160_RATIO		0x4
+#define ACLK_100_RATIO		0x7
+#define ACLK_200_RATIO		0x3
+#define CLK_DIV_TOP_VAL		((ONENAND_RATIO << 16)	\
+				| (ACLK_133_RATIO << 12)\
+				| (ACLK_160_RATIO << 8)	\
+				| (ACLK_100_RATIO << 4)	\
+				| (ACLK_200_RATIO << 0))
+
+/* CLK_SRC_LEFTBUS */
+#define MUX_GDL_SEL_SCLKMPLL	0x0
+#define MUX_GDL_SEL_SCLKAPLL	0x1
+#define CLK_SRC_LEFTBUS_VAL	(MUX_GDL_SEL_SCLKMPLL)
+
+/* CLK_DIV_LEFTBUS */
+#define GPL_RATIO		0x1
+#define GDL_RATIO		0x3
+#define CLK_DIV_LEFTBUS_VAL	((GPL_RATIO << 4) | (GDL_RATIO))
+
+/* CLK_SRC_RIGHTBUS */
+#define MUX_GDR_SEL_SCLKMPLL	0x0
+#define MUX_GDR_SEL_SCLKAPLL	0x1
+#define CLK_SRC_RIGHTBUS_VAL	(MUX_GDR_SEL_SCLKMPLL)
+
+/* CLK_DIV_RIGHTBUS */
+#define GPR_RATIO		0x1
+#define GDR_RATIO		0x3
+#define CLK_DIV_RIGHTBUS_VAL	((GPR_RATIO << 4) | (GDR_RATIO))
+
+/* CLK_SRS_FSYS: 6 = SCLKMPLL */
+#define SATA_SEL_SCLKMPLL	0
+#define SATA_SEL_SCLKAPLL	1
+
+#define MMC_SEL_XXTI		0
+#define MMC_SEL_XUSBXTI		1
+#define MMC_SEL_SCLK_HDMI24M	2
+#define MMC_SEL_SCLK_USBPHY0	3
+#define MMC_SEL_SCLK_USBPHY1	4
+#define MMC_SEL_SCLK_HDMIPHY	5
+#define MMC_SEL_SCLKMPLL	6
+#define MMC_SEL_SCLKEPLL	7
+#define MMC_SEL_SCLKVPLL	8
+
+#define MMCC0_SEL		MMC_SEL_SCLKMPLL
+#define MMCC1_SEL		MMC_SEL_SCLKMPLL
+#define MMCC2_SEL		MMC_SEL_SCLKMPLL
+#define MMCC3_SEL		MMC_SEL_SCLKMPLL
+#define MMCC4_SEL		MMC_SEL_SCLKMPLL
+#define CLK_SRC_FSYS_VAL	((SATA_SEL_SCLKMPLL << 24) \
+				| (MMCC4_SEL << 16) \
+				| (MMCC3_SEL << 12) \
+				| (MMCC2_SEL << 8) \
+				| (MMCC1_SEL << 4) \
+				| (MMCC0_SEL << 0))
+
+/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
+/* CLK_DIV_FSYS1 */
+#define MMC0_RATIO		0xF
+#define MMC0_PRE_RATIO		0x0
+#define MMC1_RATIO		0xF
+#define MMC1_PRE_RATIO		0x0
+#define CLK_DIV_FSYS1_VAL	((MMC1_PRE_RATIO << 24) \
+				| (MMC1_RATIO << 16) \
+				| (MMC0_PRE_RATIO << 8) \
+				| (MMC0_RATIO << 0))
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO		0xF
+#define MMC2_PRE_RATIO		0x0
+#define MMC3_RATIO		0xF
+#define MMC3_PRE_RATIO		0x0
+#define CLK_DIV_FSYS2_VAL	((MMC3_PRE_RATIO << 24) \
+				| (MMC3_RATIO << 16) \
+				| (MMC2_PRE_RATIO << 8) \
+				| (MMC2_RATIO << 0))
+
+/* CLK_DIV_FSYS3 */
+#define MMC4_RATIO		0xF
+#define MMC4_PRE_RATIO		0x0
+#define CLK_DIV_FSYS3_VAL	((MMC4_PRE_RATIO << 8) \
+				| (MMC4_RATIO << 0))
+
+/* CLK_SRC_PERIL0 */
+#define UART_SEL_XXTI		0
+#define UART_SEL_XUSBXTI	1
+#define UART_SEL_SCLK_HDMI24M	2
+#define UART_SEL_SCLK_USBPHY0	3
+#define UART_SEL_SCLK_USBPHY1	4
+#define UART_SEL_SCLK_HDMIPHY	5
+#define UART_SEL_SCLKMPLL	6
+#define UART_SEL_SCLKEPLL	7
+#define UART_SEL_SCLKVPLL	8
+
+#define UART0_SEL		UART_SEL_SCLKMPLL
+#define UART1_SEL		UART_SEL_SCLKMPLL
+#define UART2_SEL		UART_SEL_SCLKMPLL
+#define UART3_SEL		UART_SEL_SCLKMPLL
+#define UART4_SEL		UART_SEL_SCLKMPLL
+#define CLK_SRC_PERIL0_VAL	((UART4_SEL << 16) \
+				| (UART3_SEL << 12) \
+				| (UART2_SEL << 8) \
+				| (UART1_SEL << 4) \
+				| (UART0_SEL << 0))
+
+/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
+/* CLK_DIV_PERIL0 */
+#define UART0_RATIO		7
+#define UART1_RATIO		7
+#define UART2_RATIO		7
+#define UART3_RATIO		7
+#define UART4_RATIO		7
+#define CLK_DIV_PERIL0_VAL	((UART4_RATIO << 16) \
+				| (UART3_RATIO << 12) \
+				| (UART2_RATIO << 8) \
+				| (UART1_RATIO << 4) \
+				| (UART0_RATIO << 0))
+
+/* Clock Source CAM/FIMC */
+/* CLK_SRC_CAM */
+#define CAM0_SEL_XUSBXTI	1
+#define CAM1_SEL_XUSBXTI	1
+#define CSIS0_SEL_XUSBXTI	1
+#define CSIS1_SEL_XUSBXTI	1
+
+#define FIMC_SEL_SCLKMPLL	6
+#define FIMC0_LCLK_SEL		FIMC_SEL_SCLKMPLL
+#define FIMC1_LCLK_SEL		FIMC_SEL_SCLKMPLL
+#define FIMC2_LCLK_SEL		FIMC_SEL_SCLKMPLL
+#define FIMC3_LCLK_SEL		FIMC_SEL_SCLKMPLL
+
+#define CLK_SRC_CAM_VAL		((CSIS1_SEL_XUSBXTI << 28) \
+				| (CSIS0_SEL_XUSBXTI << 24) \
+				| (CAM1_SEL_XUSBXTI << 20) \
+				| (CAM0_SEL_XUSBXTI << 16) \
+				| (FIMC3_LCLK_SEL << 12) \
+				| (FIMC2_LCLK_SEL << 8) \
+				| (FIMC1_LCLK_SEL << 4) \
+				| (FIMC0_LCLK_SEL << 0))
+
+/* SCLK CAM */
+/* CLK_DIV_CAM */
+#define FIMC0_LCLK_RATIO	4
+#define FIMC1_LCLK_RATIO	4
+#define FIMC2_LCLK_RATIO	4
+#define FIMC3_LCLK_RATIO	4
+#define CLK_DIV_CAM_VAL		((FIMC3_LCLK_RATIO << 12) \
+				| (FIMC2_LCLK_RATIO << 8) \
+				| (FIMC1_LCLK_RATIO << 4) \
+				| (FIMC0_LCLK_RATIO << 0))
+
+/* SCLK MFC */
+/* CLK_SRC_MFC */
+#define MFC_SEL_MPLL		0
+#define MOUTMFC_0		0
+#define MFC_SEL			MOUTMFC_0
+#define MFC_0_SEL		MFC_SEL_MPLL
+#define CLK_SRC_MFC_VAL		((MFC_SEL << 8) | (MFC_0_SEL))
+
+
+/* CLK_DIV_MFC */
+#define MFC_RATIO		3
+#define CLK_DIV_MFC_VAL		(MFC_RATIO)
+
+/* SCLK G3D */
+/* CLK_SRC_G3D */
+#define G3D_SEL_MPLL		0
+#define MOUTG3D_0		0
+#define G3D_SEL			MOUTG3D_0
+#define G3D_0_SEL		G3D_SEL_MPLL
+#define CLK_SRC_G3D_VAL		((G3D_SEL << 8) | (G3D_0_SEL))
+
+/* CLK_DIV_G3D */
+#define G3D_RATIO		1
+#define CLK_DIV_G3D_VAL		(G3D_RATIO)
+
+/* SCLK LCD0 */
+/* CLK_SRC_LCD0 */
+#define FIMD_SEL_SCLKMPLL	6
+#define MDNIE0_SEL_XUSBXTI	1
+#define MDNIE_PWM0_SEL_XUSBXTI	1
+#define MIPI0_SEL_XUSBXTI	1
+#define CLK_SRC_LCD0_VAL	((MIPI0_SEL_XUSBXTI << 12) \
+				| (MDNIE_PWM0_SEL_XUSBXTI << 8) \
+				| (MDNIE0_SEL_XUSBXTI << 4) \
+				| (FIMD_SEL_SCLKMPLL << 0))
+
+/* CLK_DIV_LCD0 */
+#define FIMD0_RATIO		4
+#define CLK_DIV_LCD0_VAL	(FIMD0_RATIO)
+
+/* Required period to generate a stable clock output */
+/* PLL_LOCK_TIME */
+#define PLL_LOCKTIME		0x1C20
+
+/* PLL Values */
+#define DISABLE			0
+#define ENABLE			1
+#define SET_PLL(mdiv, pdiv, sdiv)	((ENABLE << 31)\
+					| (mdiv << 16) \
+					| (pdiv << 8) \
+					| (sdiv << 0))
+
+/* APLL_CON0 */
+#define APLL_MDIV		0xFA
+#define APLL_PDIV		0x6
+#define APLL_SDIV		0x1
+#define APLL_CON0_VAL		SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+
+/* APLL_CON1 */
+#define APLL_AFC_ENB		0x1
+#define APLL_AFC		0xC
+#define APLL_CON1_VAL		((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
+
+/* MPLL_CON0 */
+#define MPLL_MDIV		0xC8
+#define MPLL_PDIV		0x6
+#define MPLL_SDIV		0x1
+#define MPLL_CON0_VAL		SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+
+/* MPLL_CON1 */
+#define MPLL_AFC_ENB		0x0
+#define MPLL_AFC		0x1C
+#define MPLL_CON1_VAL		((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
+
+/* EPLL_CON0 */
+#define EPLL_MDIV		0x30
+#define EPLL_PDIV		0x3
+#define EPLL_SDIV		0x2
+#define EPLL_CON0_VAL		SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
+
+/* EPLL_CON1 */
+#define EPLL_K			0x0
+#define EPLL_CON1_VAL		(EPLL_K >> 0)
+
+/* VPLL_CON0 */
+#define VPLL_MDIV		0x35
+#define VPLL_PDIV		0x3
+#define VPLL_SDIV		0x2
+#define VPLL_CON0_VAL		SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
+
+/* VPLL_CON1 */
+#define VPLL_SSCG_EN		DISABLE
+#define VPLL_SEL_PF_DN_SPREAD	0x0
+#define VPLL_MRR		0x11
+#define VPLL_MFR		0x0
+#define VPLL_K			0x400
+#define VPLL_CON1_VAL		((VPLL_SSCG_EN << 31)\
+				| (VPLL_SEL_PF_DN_SPREAD << 29) \
+				| (VPLL_MRR << 24) \
+				| (VPLL_MFR << 16) \
+				| (VPLL_K << 0))
+
+/* DMC */
+#define DIRECT_CMD_NOP	0x07000000
+#define DIRECT_CMD_ZQ	0x0a000000
+#define DIRECT_CMD_CHIP1_SHIFT	(1 << 20)
+#define MEM_TIMINGS_MSR_COUNT	4
+#define CTRL_START	(1 << 0)
+#define CTRL_DLL_ON	(1 << 1)
+#define AREF_EN		(1 << 5)
+#define DRV_TYPE	(1 << 6)
+
+struct mem_timings {
+	unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
+	unsigned timingref;
+	unsigned timingrow;
+	unsigned timingdata;
+	unsigned timingpower;
+	unsigned zqcontrol;
+	unsigned control0;
+	unsigned control1;
+	unsigned control2;
+	unsigned concontrol;
+	unsigned prechconfig;
+	unsigned memcontrol;
+	unsigned memconfig0;
+	unsigned memconfig1;
+	unsigned dll_resync;
+	unsigned dll_on;
+};
+
+/* MIU */
+/* MIU Config Register Offsets*/
+#define APB_SFR_INTERLEAVE_CONF_OFFSET	0x400
+#define APB_SFR_ARBRITATION_CONF_OFFSET	0xC00
+#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET	0x800
+#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET	0x808
+#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET	0x810
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET	0x818
+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET	0x820
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET	0x828
+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET	0x830
+
+#ifdef CONFIG_ORIGEN
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
+#define APB_SFR_INTERLEAVE_CONF_VAL	0x20001507
+#define APB_SFR_ARBRITATION_CONF_VAL	0x00000001
+#endif
+
+#define INTERLEAVE_ADDR_MAP_START_ADDR	0x40000000
+#define INTERLEAVE_ADDR_MAP_END_ADDR	0xbfffffff
+#define INTERLEAVE_ADDR_MAP_EN		0x00000001
+
+#ifdef CONFIG_MIU_1BIT_INTERLEAVED
+/* Interleave_bit0: 0xC*/
+#define APB_SFR_INTERLEAVE_CONF_VAL	0x0000000c
+#endif
+#ifdef CONFIG_MIU_2BIT_INTERLEAVED
+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
+#define APB_SFR_INTERLEAVE_CONF_VAL	0x2000150c
+#endif
+#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR	0x40000000
+#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR		0x7fffffff
+#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR	0x80000000
+#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR		0xbfffffff
+/* Enable SME0 and SME1*/
+#define APB_SFR_SLV_ADDR_MAP_CONF_VAL		0x00000006
+
+#define FORCE_DLL_RESYNC	3
+#define DLL_CONTROL_ON		1
+
+#define DIRECT_CMD1	0x00020000
+#define DIRECT_CMD2	0x00030000
+#define DIRECT_CMD3	0x00010002
+#define DIRECT_CMD4	0x00000328
+
+#define CTRL_ZQ_MODE_NOTERM	(0x1 << 0)
+#define CTRL_ZQ_START		(0x1 << 1)
+#define CTRL_ZQ_DIV		(0 << 4)
+#define CTRL_ZQ_MODE_DDS	(0x7 << 8)
+#define CTRL_ZQ_MODE_TERM	(0x2 << 11)
+#define CTRL_ZQ_FORCE_IMPN	(0x5 << 14)
+#define CTRL_ZQ_FORCE_IMPP	(0x6 << 17)
+#define CTRL_DCC		(0xE38 << 20)
+#define ZQ_CONTROL_VAL		(CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
+				| CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
+				| CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
+				| CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
+
+#define ASYNC			(0 << 0)
+#define CLK_RATIO		(1 << 1)
+#define DIV_PIPE		(1 << 3)
+#define AWR_ON			(1 << 4)
+#define AREF_DISABLE		(0 << 5)
+#define DRV_TYPE_DISABLE	(0 << 6)
+#define CHIP0_NOT_EMPTY		(0 << 8)
+#define CHIP1_NOT_EMPTY		(0 << 9)
+#define DQ_SWAP_DISABLE		(0 << 10)
+#define QOS_FAST_DISABLE	(0 << 11)
+#define RD_FETCH		(0x3 << 12)
+#define TIMEOUT_LEVEL0		(0xFFF << 16)
+#define CONCONTROL_VAL		(ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
+				| AREF_DISABLE | DRV_TYPE_DISABLE\
+				| CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
+				| DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
+				| RD_FETCH | TIMEOUT_LEVEL0)
+
+#define CLK_STOP_DISABLE	(0 << 1)
+#define DPWRDN_DISABLE		(0 << 2)
+#define DPWRDN_TYPE		(0 << 3)
+#define TP_DISABLE		(0 << 4)
+#define DSREF_DIABLE		(0 << 5)
+#define ADD_LAT_PALL		(1 << 6)
+#define MEM_TYPE_DDR3		(0x6 << 8)
+#define MEM_WIDTH_32		(0x2 << 12)
+#define NUM_CHIP_2		(1 << 16)
+#define BL_8			(0x3 << 20)
+#define MEMCONTROL_VAL		(CLK_STOP_DISABLE | DPWRDN_DISABLE\
+				| DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
+				| ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
+				| NUM_CHIP_2 | BL_8)
+
+
+#define CHIP_BANK_8		(0x3 << 0)
+#define CHIP_ROW_14		(0x2 << 4)
+#define CHIP_COL_10		(0x3 << 8)
+#define CHIP_MAP_INTERLEAVED	(1 << 12)
+#define CHIP_MASK		(0xe0 << 16)
+#ifdef CONFIG_MIU_LINEAR
+#define CHIP0_BASE		(0x40 << 24)
+#define CHIP1_BASE		(0x60 << 24)
+#else
+#define CHIP0_BASE		(0x20 << 24)
+#define CHIP1_BASE		(0x40 << 24)
+#endif
+#define MEMCONFIG0_VAL		(CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
+				| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
+#define MEMCONFIG1_VAL		(CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
+				| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
+
+#define TP_CNT			(0xff << 24)
+#define PRECHCONFIG		TP_CNT
+
+#define CTRL_OFF		(0 << 0)
+#define CTRL_DLL_OFF		(0 << 1)
+#define CTRL_HALF		(0 << 2)
+#define CTRL_DFDQS		(1 << 3)
+#define DQS_DELAY		(0 << 4)
+#define CTRL_START_POINT	(0x10 << 8)
+#define CTRL_INC		(0x10 << 16)
+#define CTRL_FORCE		(0x71 << 24)
+#define CONTROL0_VAL		(CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
+				| CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
+				| CTRL_INC | CTRL_FORCE)
+
+#define CTRL_SHIFTC		(0x6 << 0)
+#define CTRL_REF		(8 << 4)
+#define CTRL_SHGATE		(1 << 29)
+#define TERM_READ_EN		(1 << 30)
+#define TERM_WRITE_EN		(1 << 31)
+#define CONTROL1_VAL		(CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
+				| TERM_READ_EN | TERM_WRITE_EN)
+
+#define CONTROL2_VAL		0x00000000
+
+#ifdef CONFIG_ORIGEN
+#define TIMINGREF_VAL		0x000000BB
+#define TIMINGROW_VAL		0x4046654f
+#define	TIMINGDATA_VAL		0x46400506
+#define	TIMINGPOWER_VAL		0x52000A3C
+#else
+#define TIMINGREF_VAL		0x000000BC
+#ifdef DRAM_CLK_330
+#define TIMINGROW_VAL		0x3545548d
+#define	TIMINGDATA_VAL		0x45430506
+#define	TIMINGPOWER_VAL		0x4439033c
+#endif
+#ifdef DRAM_CLK_400
+#define TIMINGROW_VAL		0x45430506
+#define	TIMINGDATA_VAL		0x56500506
+#define	TIMINGPOWER_VAL		0x5444033d
+#endif
+#endif
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/exynos5_setup.h
new file mode 100644
index 000000000..53b0ace6e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -0,0 +1,945 @@
+/*
+ * Machine Specific Values for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SMDK5250_SETUP_H
+#define _SMDK5250_SETUP_H
+
+#include <config.h>
+#include <asm/arch/dmc.h>
+
+#define NOT_AVAILABLE		0
+#define DATA_MASK		0xFFFFF
+
+#define ENABLE_BIT		0x1
+#define DISABLE_BIT		0x0
+#define CA_SWAP_EN		(1 << 0)
+
+/* Set PLL */
+#define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+/* MEMCONTROL register bit fields */
+#define DMC_MEMCONTROL_CLK_STOP_DISABLE	(0 << 0)
+#define DMC_MEMCONTROL_DPWRDN_DISABLE	(0 << 1)
+#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE	(0 << 2)
+#define DMC_MEMCONTROL_TP_DISABLE	(0 << 4)
+#define DMC_MEMCONTROL_DSREF_DISABLE	(0 << 5)
+#define DMC_MEMCONTROL_DSREF_ENABLE	(1 << 5)
+#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x)    (x << 6)
+
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3  (7 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_DDR3    (6 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2  (5 << 8)
+
+#define DMC_MEMCONTROL_MEM_WIDTH_32BIT  (2 << 12)
+
+#define DMC_MEMCONTROL_NUM_CHIP_1       (0 << 16)
+#define DMC_MEMCONTROL_NUM_CHIP_2       (1 << 16)
+
+#define DMC_MEMCONTROL_BL_8             (3 << 20)
+#define DMC_MEMCONTROL_BL_4             (2 << 20)
+
+#define DMC_MEMCONTROL_PZQ_DISABLE      (0 << 24)
+
+#define DMC_MEMCONTROL_MRR_BYTE_7_0     (0 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_15_8    (1 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_23_16   (2 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_31_24   (3 << 25)
+
+/* MEMCONFIG0 register bit fields */
+#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED     (1 << 12)
+#define DMC_MEMCONFIG_CHIP_MAP_SPLIT		(2 << 12)
+#define DMC_MEMCONFIGX_CHIP_COL_10              (3 << 8)
+#define DMC_MEMCONFIGX_CHIP_ROW_14              (2 << 4)
+#define DMC_MEMCONFIGX_CHIP_ROW_15              (3 << 4)
+#define DMC_MEMCONFIGX_CHIP_BANK_8              (3 << 0)
+
+#define DMC_MEMBASECONFIGX_CHIP_BASE(x)         (x << 16)
+#define DMC_MEMBASECONFIGX_CHIP_MASK(x)         (x << 0)
+#define DMC_MEMBASECONFIG_VAL(x)        (       \
+	DMC_MEMBASECONFIGX_CHIP_BASE(x) |       \
+	DMC_MEMBASECONFIGX_CHIP_MASK(0x780)     \
+)
+
+/*
+ * As we use channel interleaving, therefore value of the base address
+ * register must be set as half of the bus base address
+ * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
+ * we need to set half 0x10 to the membaseconfigx registers
+ * see exynos5420 UM section 17.17.3.21 for more.
+ */
+#define DMC_CHIP_BASE_0 0x10
+#define DMC_CHIP_BASE_1 0x50
+#define DMC_CHIP_MASK	0x7C0
+
+#define DMC_MEMBASECONFIG0_VAL  DMC_MEMBASECONFIG_VAL(0x40)
+#define DMC_MEMBASECONFIG1_VAL  DMC_MEMBASECONFIG_VAL(0x80)
+
+#define DMC_PRECHCONFIG_VAL             0xFF000000
+#define DMC_PWRDNCONFIG_VAL             0xFFFF00FF
+
+#define DMC_CONCONTROL_RESET_VAL	0x0FFF0000
+#define DFI_INIT_START		(1 << 28)
+#define EMPTY			(1 << 8)
+#define AREF_EN			(1 << 5)
+
+#define DFI_INIT_COMPLETE_CHO	(1 << 2)
+#define DFI_INIT_COMPLETE_CH1	(1 << 3)
+
+#define RDLVL_COMPLETE_CHO	(1 << 14)
+#define RDLVL_COMPLETE_CH1	(1 << 15)
+
+#define CLK_STOP_EN	(1 << 0)
+#define DPWRDN_EN	(1 << 1)
+#define DSREF_EN	(1 << 5)
+
+/* COJCONTROL register bit fields */
+#define DMC_CONCONTROL_IO_PD_CON_DISABLE	(0 << 3)
+#define DMC_CONCONTROL_IO_PD_CON_ENABLE		(1 << 3)
+#define DMC_CONCONTROL_AREF_EN_DISABLE		(0 << 5)
+#define DMC_CONCONTROL_AREF_EN_ENABLE		(1 << 5)
+#define DMC_CONCONTROL_EMPTY_DISABLE		(0 << 8)
+#define DMC_CONCONTROL_EMPTY_ENABLE		(1 << 8)
+#define DMC_CONCONTROL_RD_FETCH_DISABLE		(0x0 << 12)
+#define DMC_CONCONTROL_TIMEOUT_LEVEL0		(0xFFF << 16)
+#define DMC_CONCONTROL_DFI_INIT_START_DISABLE	(0 << 28)
+
+#define DMC_CONCONTROL_VAL	0x1FFF2101
+
+#define DREX_CONCONTROL_VAL	DMC_CONCONTROL_VAL			\
+				| DMC_CONCONTROL_AREF_EN_ENABLE		\
+				| DMC_CONCONTROL_IO_PD_CON_ENABLE
+
+#define DMC_CONCONTROL_IO_PD_CON(x)		(x << 6)
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO               0x2
+#define COPY_RATIO              0x0
+
+/* CLK_DIV_CPU1 = 0x00000003 */
+#define CLK_DIV_CPU1_VAL        ((HPM_RATIO << 4)		\
+				| (COPY_RATIO))
+
+/* CLK_SRC_CORE0 */
+#define CLK_SRC_CORE0_VAL       0x00000000
+
+/* CLK_SRC_CORE1 */
+#define CLK_SRC_CORE1_VAL       0x100
+
+/* CLK_DIV_CORE0 */
+#define CLK_DIV_CORE0_VAL       0x00120000
+
+/* CLK_DIV_CORE1 */
+#define CLK_DIV_CORE1_VAL       0x07070700
+
+/* CLK_DIV_SYSRGT */
+#define CLK_DIV_SYSRGT_VAL      0x00000111
+
+/* CLK_DIV_ACP */
+#define CLK_DIV_ACP_VAL         0x12
+
+/* CLK_DIV_SYSLFT */
+#define CLK_DIV_SYSLFT_VAL      0x00000311
+
+#define MUX_APLL_SEL_MASK	(1 << 0)
+#define MUX_MPLL_SEL_MASK	(1 << 8)
+#define MPLL_SEL_MOUT_MPLLFOUT	(2 << 8)
+#define MUX_CPLL_SEL_MASK	(1 << 8)
+#define MUX_EPLL_SEL_MASK	(1 << 12)
+#define MUX_VPLL_SEL_MASK	(1 << 16)
+#define MUX_GPLL_SEL_MASK	(1 << 28)
+#define MUX_BPLL_SEL_MASK	(1 << 0)
+#define MUX_HPM_SEL_MASK	(1 << 20)
+#define HPM_SEL_SCLK_MPLL	(1 << 21)
+#define PLL_LOCKED		(1 << 29)
+#define APLL_CON0_LOCKED	(1 << 29)
+#define MPLL_CON0_LOCKED	(1 << 29)
+#define BPLL_CON0_LOCKED	(1 << 29)
+#define CPLL_CON0_LOCKED	(1 << 29)
+#define EPLL_CON0_LOCKED	(1 << 29)
+#define GPLL_CON0_LOCKED	(1 << 29)
+#define VPLL_CON0_LOCKED	(1 << 29)
+#define CLK_REG_DISABLE		0x0
+#define TOP2_VAL		0x0110000
+
+/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
+#define SPI0_ISP_SEL		6
+#define SPI1_ISP_SEL		6
+#define SCLK_SRC_ISP_VAL	(SPI1_ISP_SEL << 4) \
+				| (SPI0_ISP_SEL << 0)
+
+/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
+#define SPI0_ISP_RATIO		0xf
+#define SPI1_ISP_RATIO		0xf
+#define SCLK_DIV_ISP_VAL	(SPI1_ISP_RATIO << 12) \
+				| (SPI0_ISP_RATIO << 0)
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO_MASK		0xf
+#define MMC2_RATIO_VAL		0x3
+#define MMC2_RATIO_OFFSET	0
+
+#define MMC2_PRE_RATIO_MASK	0xff
+#define MMC2_PRE_RATIO_VAL	0x9
+#define MMC2_PRE_RATIO_OFFSET	8
+
+#define MMC3_RATIO_MASK		0xf
+#define MMC3_RATIO_VAL		0x1
+#define MMC3_RATIO_OFFSET	16
+
+#define MMC3_PRE_RATIO_MASK	0xff
+#define MMC3_PRE_RATIO_VAL	0x0
+#define MMC3_PRE_RATIO_OFFSET	24
+
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL         0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL         0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL         0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL         0x10
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL        0x1
+
+/* CLK_SRC_KFC */
+#define SRC_KFC_HPM_SEL		(1 << 15)
+
+/* CLK_SRC_KFC */
+#define CLK_SRC_KFC_VAL		0x00008001
+
+/* CLK_DIV_KFC */
+#define CLK_DIV_KFC_VAL		0x03300110
+
+/* CLK_DIV2_RATIO */
+#define CLK_DIV2_RATIO		0x10111150
+
+/* CLK_DIV4_RATIO */
+#define CLK_DIV4_RATIO		0x00000003
+
+/* CLK_DIV_G2D */
+#define CLK_DIV_G2D		0x00000010
+
+/*
+ * DIV_DISP1_0
+ * For DP, divisor should be 2
+ */
+#define CLK_DIV_DISP1_0_FIMD1	(2 << 0)
+
+/* CLK_GATE_IP_DISP1 */
+#define CLK_GATE_DP1_ALLOW	(1 << 4)
+
+/* AUDIO CLK SEL */
+#define AUDIO0_SEL_EPLL		(0x6 << 28)
+#define AUDIO0_RATIO		0x5
+#define PCM0_RATIO		0x3
+#define DIV_MAU_VAL		(PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
+
+/* CLK_SRC_CDREX */
+#define MUX_MCLK_CDR_MSPLL	(1 << 4)
+#define MUX_BPLL_SEL_FOUTBPLL   (1 << 0)
+#define BPLL_SEL_MASK   0x7
+#define FOUTBPLL        2
+
+#define DDR3PHY_CTRL_PHY_RESET	(1 << 0)
+#define DDR3PHY_CTRL_PHY_RESET_OFF	(0 << 0)
+
+#define PHY_CON0_RESET_VAL	0x17020a40
+#define P0_CMD_EN		(1 << 14)
+#define BYTE_RDLVL_EN		(1 << 13)
+#define CTRL_SHGATE		(1 << 8)
+
+#define PHY_CON1_RESET_VAL	0x09210100
+#define RDLVL_PASS_ADJ_VAL	0x6
+#define RDLVL_PASS_ADJ_OFFSET	16
+#define CTRL_GATEDURADJ_MASK	(0xf << 20)
+#define READ_LEVELLING_DDR3	0x0100
+
+#define PHY_CON2_RESET_VAL	0x00010004
+#define INIT_DESKEW_EN		(1 << 6)
+#define DLL_DESKEW_EN		(1 << 12)
+#define RDLVL_GATE_EN		(1 << 24)
+#define RDLVL_EN		(1 << 25)
+#define RDLVL_INCR_ADJ		(0x1 << 16)
+
+/* DREX_PAUSE */
+#define DREX_PAUSE_EN	(1 << 0)
+
+#define BYPASS_EN	(1 << 22)
+
+/* MEMMORY VAL */
+#define PHY_CON0_VAL	0x17021A00
+
+#define PHY_CON12_RESET_VAL	0x10100070
+#define PHY_CON12_VAL		0x10107F50
+#define CTRL_START		(1 << 6)
+#define CTRL_DLL_ON		(1 << 5)
+#define CTRL_FORCE_MASK		(0x7F << 8)
+#define CTRL_LOCK_COARSE_MASK	(0x7F << 10)
+
+#define CTRL_OFFSETD_RESET_VAL	0x8
+#define CTRL_OFFSETD_VAL	0x7F
+
+#define CTRL_OFFSETR0		0x7F
+#define CTRL_OFFSETR1		0x7F
+#define CTRL_OFFSETR2		0x7F
+#define CTRL_OFFSETR3		0x7F
+#define PHY_CON4_VAL	(CTRL_OFFSETR0 << 0 | \
+				CTRL_OFFSETR1 << 8 | \
+				CTRL_OFFSETR2 << 16 | \
+				CTRL_OFFSETR3 << 24)
+#define PHY_CON4_RESET_VAL	0x08080808
+
+#define CTRL_OFFSETW0		0x7F
+#define CTRL_OFFSETW1		0x7F
+#define CTRL_OFFSETW2		0x7F
+#define CTRL_OFFSETW3		0x7F
+#define PHY_CON6_VAL	(CTRL_OFFSETW0 << 0 | \
+				CTRL_OFFSETW1 << 8 | \
+				CTRL_OFFSETW2 << 16 | \
+				CTRL_OFFSETW3 << 24)
+#define PHY_CON6_RESET_VAL	0x08080808
+
+#define PHY_CON14_RESET_VAL	0x001F0000
+#define CTRL_PULLD_DQS		0xF
+#define CTRL_PULLD_DQS_OFFSET	0
+
+/* ZQ Configurations */
+#define PHY_CON16_RESET_VAL	0x08000304
+
+#define ZQ_CLK_EN		(1 << 27)
+#define ZQ_CLK_DIV_EN		(1 << 18)
+#define ZQ_MANUAL_STR		(1 << 1)
+#define ZQ_DONE			(1 << 0)
+#define ZQ_MODE_DDS_OFFSET	24
+
+#define CTRL_RDLVL_GATE_ENABLE	1
+#define CTRL_RDLVL_GATE_DISABLE	0
+#define CTRL_RDLVL_DATA_ENABLE	2
+
+/* Direct Command */
+#define DIRECT_CMD_NOP			0x07000000
+#define DIRECT_CMD_PALL			0x01000000
+#define DIRECT_CMD_ZQINIT		0x0a000000
+#define DIRECT_CMD_CHANNEL_SHIFT	28
+#define DIRECT_CMD_CHIP_SHIFT		20
+#define DIRECT_CMD_BANK_SHIFT		16
+#define DIRECT_CMD_REFA		(5 << 24)
+#define DIRECT_CMD_MRS1		0x71C00
+#define DIRECT_CMD_MRS2		0x10BFC
+#define DIRECT_CMD_MRS3		0x0050C
+#define DIRECT_CMD_MRS4		0x00868
+#define DIRECT_CMD_MRS5		0x00C04
+
+/* Drive Strength */
+#define IMPEDANCE_48_OHM	4
+#define IMPEDANCE_40_OHM	5
+#define IMPEDANCE_34_OHM	6
+#define IMPEDANCE_30_OHM	7
+#define PHY_CON39_VAL_48_OHM	0x09240924
+#define PHY_CON39_VAL_40_OHM	0x0B6D0B6D
+#define PHY_CON39_VAL_34_OHM	0x0DB60DB6
+#define PHY_CON39_VAL_30_OHM	0x0FFF0FFF
+
+#define CTRL_BSTLEN_OFFSET	8
+#define CTRL_RDLAT_OFFSET	0
+
+#define CMD_DEFAULT_LPDDR3	0xF
+#define CMD_DEFUALT_OFFSET	0
+#define T_WRDATA_EN		0x7
+#define T_WRDATA_EN_DDR3	0x8
+#define T_WRDATA_EN_OFFSET	16
+#define T_WRDATA_EN_MASK	0x1f
+
+#define PHY_CON31_VAL	0x0C183060
+#define PHY_CON32_VAL	0x60C18306
+#define PHY_CON33_VAL	0x00000030
+
+#define PHY_CON31_RESET_VAL	0x0
+#define PHY_CON32_RESET_VAL	0x0
+#define PHY_CON33_RESET_VAL	0x0
+
+#define SL_DLL_DYN_CON_EN	(1 << 1)
+#define FP_RESYNC	(1 << 3)
+#define CTRL_START	(1 << 6)
+
+#define DMC_AREF_EN		(1 << 5)
+#define DMC_CONCONTROL_EMPTY	(1 << 8)
+#define DFI_INIT_START		(1 << 28)
+
+#define DMC_MEMCONTROL_VAL	0x00312700
+#define CLK_STOP_EN		(1 << 0)
+#define DPWRDN_EN		(1 << 1)
+#define DSREF_EN		(1 << 5)
+
+#define MEMBASECONFIG_CHIP_MASK_VAL	0x7E0
+#define MEMBASECONFIG_CHIP_MASK_OFFSET	0
+#define MEMBASECONFIG0_CHIP_BASE_VAL	0x20
+#define MEMBASECONFIG1_CHIP_BASE_VAL	0x40
+#define CHIP_BASE_OFFSET		16
+
+#define MEMCONFIG_VAL	0x1323
+#define PRECHCONFIG_DEFAULT_VAL	0xFF000000
+#define PWRDNCONFIG_DEFAULT_VAL	0xFFFF00FF
+
+#define TIMINGAREF_VAL	0x5d
+#define TIMINGROW_VAL	0x345A8692
+#define TIMINGDATA_VAL	0x3630065C
+#define TIMINGPOWER_VAL	0x50380336
+#define DFI_INIT_COMPLETE	(1 << 3)
+
+#define BRBRSVCONTROL_VAL	0x00000033
+#define BRBRSVCONFIG_VAL	0x88778877
+
+/* Clock Gating Control (CGCONTROL) register */
+#define MEMIF_CG_EN	(1 << 3) /* Memory interface clock gating */
+#define SCG_CG_EN	(1 << 2) /* Scheduler clock gating */
+#define BUSIF_WR_CG_EN	(1 << 1) /* Bus interface write channel clock gating */
+#define BUSIF_RD_CG_EN	(1 << 0) /* Bus interface read channel clock gating */
+#define DMC_INTERNAL_CG	(MEMIF_CG_EN | SCG_CG_EN | \
+				 BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
+
+/* DMC PHY Control0 register */
+#define PHY_CONTROL0_RESET_VAL	0x0
+#define MEM_TERM_EN	(1 << 31)	/* Termination enable for memory */
+#define PHY_TERM_EN	(1 << 30)	/* Termination enable for PHY */
+#define DMC_CTRL_SHGATE	(1 << 29)	/* Duration of DQS gating signal */
+#define FP_RSYNC	(1 << 3)	/* Force DLL resyncronization */
+
+/* Driver strength for CK, CKE, CS & CA */
+#define IMP_OUTPUT_DRV_40_OHM	0x5
+#define IMP_OUTPUT_DRV_30_OHM	0x7
+#define DA_3_DS_OFFSET		25
+#define DA_2_DS_OFFSET		22
+#define DA_1_DS_OFFSET		19
+#define DA_0_DS_OFFSET		16
+#define CA_CK_DRVR_DS_OFFSET	9
+#define CA_CKE_DRVR_DS_OFFSET	6
+#define CA_CS_DRVR_DS_OFFSET	3
+#define CA_ADR_DRVR_DS_OFFSET	0
+
+#define PHY_CON42_CTRL_BSTLEN_SHIFT	8
+#define PHY_CON42_CTRL_RDLAT_SHIFT	0
+
+/*
+ * Definitions that differ with SoC's.
+ * Below is the part defining macros for smdk5250.
+ * Else part introduces macros for smdk5420.
+ */
+#ifndef CONFIG_SMDK5420
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL	(0x00203800)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL   (0x00203800)
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL	(0x00203800)
+
+/* DPLL_CON1 */
+#define DPLL_CON1_VAL	(NOT_AVAILABLE)
+
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL	(0x00203800)
+
+/* EPLL_CON1, CON2 */
+#define EPLL_CON1_VAL	0x00000000
+#define EPLL_CON2_VAL	0x00000080
+
+/* VPLL_CON1, CON2 */
+#define VPLL_CON1_VAL	0x00000000
+#define VPLL_CON2_VAL	0x00000080
+
+/* RPLL_CON1, CON2 */
+#define RPLL_CON1_VAL	NOT_AVAILABLE
+#define RPLL_CON2_VAL	NOT_AVAILABLE
+
+/* BPLL_CON1 */
+#define BPLL_CON1_VAL	0x00203800
+
+/* SPLL_CON1 */
+#define SPLL_CON1_VAL	NOT_AVAILABLE
+
+/* IPLL_CON1 */
+#define IPLL_CON1_VAL	NOT_AVAILABLE
+
+/* KPLL_CON1 */
+#define KPLL_CON1_VAL	NOT_AVAILABLE
+
+/* CLK_SRC_ISP */
+#define CLK_SRC_ISP_VAL		NOT_AVAILABLE
+#define CLK_DIV_ISP0_VAL	0x31
+#define CLK_DIV_ISP1_VAL	0x0
+
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL              0x66666
+#define CLK_DIV_FSYS0_VAL	       0x0BB00000
+#define CLK_DIV_FSYS1_VAL	       NOT_AVAILABLE
+#define CLK_DIV_FSYS2_VAL	       NOT_AVAILABLE
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL,  1 = SCLKMPLL */
+#define MUX_HPM_SEL             0
+#define MUX_CPU_SEL             0
+#define MUX_APLL_SEL            1
+
+#define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20)    \
+				| (MUX_CPU_SEL << 16)  \
+				| (MUX_APLL_SEL))
+
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL       0x1
+
+/* CLK_DIV_CDREX */
+#define CLK_DIV_CDREX0_VAL	NOT_AVAILABLE
+#define CLK_DIV_CDREX1_VAL	NOT_AVAILABLE
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL	NOT_AVAILABLE
+
+#define MCLK_CDREX2_RATIO       0x0
+#define ACLK_EFCON_RATIO        0x1
+#define MCLK_DPHY_RATIO		0x1
+#define MCLK_CDREX_RATIO	0x1
+#define ACLK_C2C_200_RATIO	0x1
+#define C2C_CLK_400_RATIO	0x1
+#define PCLK_CDREX_RATIO	0x1
+#define ACLK_CDREX_RATIO	0x1
+
+#define CLK_DIV_CDREX_VAL	((MCLK_DPHY_RATIO << 24)        \
+				| (C2C_CLK_400_RATIO << 6)	\
+				| (PCLK_CDREX_RATIO << 4)	\
+				| (ACLK_CDREX_RATIO))
+
+/* CLK_SRC_TOP0	*/
+#define MUX_ACLK_300_GSCL_SEL           0x0
+#define MUX_ACLK_300_GSCL_MID_SEL       0x0
+#define MUX_ACLK_400_G3D_MID_SEL        0x0
+#define MUX_ACLK_333_SEL	        0x0
+#define MUX_ACLK_300_DISP1_SEL	        0x0
+#define MUX_ACLK_300_DISP1_MID_SEL      0x0
+#define MUX_ACLK_200_SEL	        0x0
+#define MUX_ACLK_166_SEL	        0x0
+#define CLK_SRC_TOP0_VAL	((MUX_ACLK_300_GSCL_SEL  << 25)		\
+				| (MUX_ACLK_300_GSCL_MID_SEL << 24)	\
+				| (MUX_ACLK_400_G3D_MID_SEL << 20)	\
+				| (MUX_ACLK_333_SEL << 16)		\
+				| (MUX_ACLK_300_DISP1_SEL << 15)	\
+				| (MUX_ACLK_300_DISP1_MID_SEL << 14)	\
+				| (MUX_ACLK_200_SEL << 12)		\
+				| (MUX_ACLK_166_SEL << 8))
+
+/* CLK_SRC_TOP1	*/
+#define MUX_ACLK_400_G3D_SEL            0x1
+#define MUX_ACLK_400_ISP_SEL            0x0
+#define MUX_ACLK_400_IOP_SEL            0x0
+#define MUX_ACLK_MIPI_HSI_TXBASE_SEL    0x0
+#define MUX_ACLK_300_GSCL_MID1_SEL      0x0
+#define MUX_ACLK_300_DISP1_MID1_SEL     0x0
+#define CLK_SRC_TOP1_VAL	((MUX_ACLK_400_G3D_SEL << 28)           \
+				|(MUX_ACLK_400_ISP_SEL << 24)           \
+				|(MUX_ACLK_400_IOP_SEL << 20)           \
+				|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16)   \
+				|(MUX_ACLK_300_GSCL_MID1_SEL << 12)     \
+				|(MUX_ACLK_300_DISP1_MID1_SEL << 8))
+
+/* CLK_SRC_TOP2 */
+#define MUX_GPLL_SEL                    0x1
+#define MUX_BPLL_USER_SEL               0x0
+#define MUX_MPLL_USER_SEL               0x0
+#define MUX_VPLL_SEL                    0x1
+#define MUX_EPLL_SEL                    0x1
+#define MUX_CPLL_SEL                    0x1
+#define VPLLSRC_SEL                     0x0
+#define CLK_SRC_TOP2_VAL	((MUX_GPLL_SEL << 28)		\
+				| (MUX_BPLL_USER_SEL << 24)	\
+				| (MUX_MPLL_USER_SEL << 20)	\
+				| (MUX_VPLL_SEL << 16)	        \
+				| (MUX_EPLL_SEL << 12)	        \
+				| (MUX_CPLL_SEL << 8)           \
+				| (VPLLSRC_SEL))
+/* CLK_SRC_TOP3 */
+#define MUX_ACLK_333_SUB_SEL            0x1
+#define MUX_ACLK_400_SUB_SEL            0x1
+#define MUX_ACLK_266_ISP_SUB_SEL        0x1
+#define MUX_ACLK_266_GPS_SUB_SEL        0x0
+#define MUX_ACLK_300_GSCL_SUB_SEL       0x1
+#define MUX_ACLK_266_GSCL_SUB_SEL       0x1
+#define MUX_ACLK_300_DISP1_SUB_SEL      0x1
+#define MUX_ACLK_200_DISP1_SUB_SEL      0x1
+#define CLK_SRC_TOP3_VAL	((MUX_ACLK_333_SUB_SEL << 24)	        \
+				| (MUX_ACLK_400_SUB_SEL << 20)	        \
+				| (MUX_ACLK_266_ISP_SUB_SEL << 16)	\
+				| (MUX_ACLK_266_GPS_SUB_SEL << 12)      \
+				| (MUX_ACLK_300_GSCL_SUB_SEL << 10)     \
+				| (MUX_ACLK_266_GSCL_SUB_SEL << 8)      \
+				| (MUX_ACLK_300_DISP1_SUB_SEL << 6)     \
+				| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
+
+#define CLK_SRC_TOP4_VAL	NOT_AVAILABLE
+#define CLK_SRC_TOP5_VAL	NOT_AVAILABLE
+#define CLK_SRC_TOP6_VAL	NOT_AVAILABLE
+#define CLK_SRC_TOP7_VAL	NOT_AVAILABLE
+
+/* CLK_DIV_TOP0	*/
+#define ACLK_300_DISP1_RATIO	0x2
+#define ACLK_400_G3D_RATIO	0x0
+#define ACLK_333_RATIO		0x0
+#define ACLK_266_RATIO		0x2
+#define ACLK_200_RATIO		0x3
+#define ACLK_166_RATIO		0x1
+#define ACLK_133_RATIO		0x1
+#define ACLK_66_RATIO		0x5
+
+#define CLK_DIV_TOP0_VAL	((ACLK_300_DISP1_RATIO << 28)	\
+				| (ACLK_400_G3D_RATIO << 24)	\
+				| (ACLK_333_RATIO  << 20)	\
+				| (ACLK_266_RATIO << 16)	\
+				| (ACLK_200_RATIO << 12)	\
+				| (ACLK_166_RATIO << 8)		\
+				| (ACLK_133_RATIO << 4)		\
+				| (ACLK_66_RATIO))
+
+/* CLK_DIV_TOP1	*/
+#define ACLK_MIPI_HSI_TX_BASE_RATIO     0x3
+#define ACLK_66_PRE_RATIO               0x1
+#define ACLK_400_ISP_RATIO              0x1
+#define ACLK_400_IOP_RATIO              0x1
+#define ACLK_300_GSCL_RATIO             0x2
+
+#define CLK_DIV_TOP1_VAL	((ACLK_MIPI_HSI_TX_BASE_RATIO << 28)	\
+				| (ACLK_66_PRE_RATIO << 24)		\
+				| (ACLK_400_ISP_RATIO  << 20)		\
+				| (ACLK_400_IOP_RATIO << 16)		\
+				| (ACLK_300_GSCL_RATIO << 12))
+
+#define CLK_DIV_TOP2_VAL	NOT_AVAILABLE
+
+/* PLL Lock Value Factor */
+#define PLL_LOCK_FACTOR		250
+#define PLL_X_LOCK_FACTOR	3000
+
+/* CLK_SRC_PERIC0 */
+#define PWM_SEL		6
+#define UART3_SEL	6
+#define UART2_SEL	6
+#define UART1_SEL	6
+#define UART0_SEL	6
+/* SRC_CLOCK = SCLK_MPLL */
+#define CLK_SRC_PERIC0_VAL	((PWM_SEL << 24)        \
+				| (UART3_SEL << 12)     \
+				| (UART2_SEL << 8)       \
+				| (UART1_SEL << 4)      \
+				| (UART0_SEL))
+
+/* CLK_SRC_PERIC1 */
+/* SRC_CLOCK = SCLK_MPLL */
+#define SPI0_SEL		6
+#define SPI1_SEL		6
+#define SPI2_SEL		6
+#define CLK_SRC_PERIC1_VAL	((SPI2_SEL << 24) \
+				| (SPI1_SEL << 20) \
+				| (SPI0_SEL << 16))
+
+/* CLK_DIV_PERIL0	*/
+#define UART5_RATIO	7
+#define UART4_RATIO	7
+#define UART3_RATIO	7
+#define UART2_RATIO	7
+#define UART1_RATIO	7
+#define UART0_RATIO	7
+
+#define CLK_DIV_PERIC0_VAL	((UART3_RATIO << 12)    \
+				| (UART2_RATIO << 8)    \
+				| (UART1_RATIO << 4)    \
+				| (UART0_RATIO))
+/* CLK_DIV_PERIC1 */
+#define SPI1_RATIO		0x7
+#define SPI0_RATIO		0xf
+#define SPI1_SUB_RATIO		0x0
+#define SPI0_SUB_RATIO		0x0
+#define CLK_DIV_PERIC1_VAL	((SPI1_SUB_RATIO << 24) \
+				| ((SPI1_RATIO << 16) \
+				| (SPI0_SUB_RATIO << 8) \
+				| (SPI0_RATIO << 0)))
+
+/* CLK_DIV_PERIC2 */
+#define SPI2_RATIO		0xf
+#define SPI2_SUB_RATIO		0x0
+#define CLK_DIV_PERIC2_VAL	((SPI2_SUB_RATIO << 8) \
+				| (SPI2_RATIO << 0))
+
+/* CLK_DIV_PERIC3 */
+#define PWM_RATIO		8
+#define CLK_DIV_PERIC3_VAL	(PWM_RATIO << 0)
+
+
+/* CLK_DIV_PERIC4 */
+#define CLK_DIV_PERIC4_VAL	NOT_AVAILABLE
+
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL	0x6
+#define CLK_DIV_DISP1_0_VAL	NOT_AVAILABLE
+
+#define APLL_FOUT		(1 << 0)
+#define KPLL_FOUT		NOT_AVAILABLE
+
+#define CLK_DIV_CPERI1_VAL	NOT_AVAILABLE
+
+#else
+#define PAD_RETENTION_DRAM_COREBLK_VAL	0x10000000
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL	(0x0020F300)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL   (0x0020F300)
+
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL	0x0020f300
+
+/* DPLL_CON1 */
+#define DPLL_CON1_VAL	(0x0020F300)
+
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL	(NOT_AVAILABLE)
+
+
+/* EPLL_CON1, CON2 */
+#define EPLL_CON1_VAL	0x00000000
+#define EPLL_CON2_VAL	0x00000080
+
+/* VPLL_CON1, CON2 */
+#define VPLL_CON1_VAL	0x0020f300
+#define VPLL_CON2_VAL	NOT_AVAILABLE
+
+/* RPLL_CON1, CON2 */
+#define RPLL_CON1_VAL	0x00000000
+#define RPLL_CON2_VAL	0x00000080
+
+/* BPLL_CON1 */
+#define BPLL_CON1_VAL	0x0020f300
+
+/* SPLL_CON1 */
+#define SPLL_CON1_VAL	0x0020f300
+
+/* IPLL_CON1 */
+#define IPLL_CON1_VAL	0x00000080
+
+/* KPLL_CON1 */
+#define KPLL_CON1_VAL	0x200000
+
+/* CLK_SRC_ISP */
+#define CLK_SRC_ISP_VAL		0x33366000
+#define CLK_DIV_ISP0_VAL	0x13131300
+#define CLK_DIV_ISP1_VAL	0xbb110202
+
+
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL              0x33033300
+#define CLK_DIV_FSYS0_VAL	       0x0
+#define CLK_DIV_FSYS1_VAL	       0x04f13c4f
+#define CLK_DIV_FSYS2_VAL	       0x041d0000
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL,  1 = SCLKMPLL */
+#define MUX_HPM_SEL             1
+#define MUX_CPU_SEL             0
+#define MUX_APLL_SEL            1
+
+#define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20)    \
+				| (MUX_CPU_SEL << 16)  \
+				| (MUX_APLL_SEL))
+
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL       0x00000011
+
+/* CLK_DIV_CDREX */
+#define CLK_DIV_CDREX0_VAL	0x30010100
+#define CLK_DIV_CDREX1_VAL	0x300
+
+#define CLK_DIV_CDREX_VAL       0x17010100
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL	0x01440020
+
+/* CLK_SRC_TOP */
+#define CLK_SRC_TOP0_VAL	0x12221222
+#define CLK_SRC_TOP1_VAL	0x00100200
+#define CLK_SRC_TOP2_VAL	0x11101000
+#define CLK_SRC_TOP3_VAL	0x11111111
+#define CLK_SRC_TOP4_VAL	0x11110111
+#define CLK_SRC_TOP5_VAL	0x11111100
+#define CLK_SRC_TOP6_VAL	0x11110111
+#define CLK_SRC_TOP7_VAL	0x00022200
+
+/* CLK_DIV_TOP */
+#define CLK_DIV_TOP0_VAL	0x23712311
+#define CLK_DIV_TOP1_VAL	0x13100B00
+#define CLK_DIV_TOP2_VAL	0x11101100
+
+/* PLL Lock Value Factor */
+#define PLL_LOCK_FACTOR		200
+#define PLL_X_LOCK_FACTOR	3000
+
+/* CLK_SRC_PERIC0 */
+#define SPDIF_SEL	1
+#define PWM_SEL		3
+#define UART4_SEL	3
+#define UART3_SEL	3
+#define UART2_SEL	3
+#define UART1_SEL	3
+#define UART0_SEL	3
+/* SRC_CLOCK = SCLK_RPLL */
+#define CLK_SRC_PERIC0_VAL	((SPDIF_SEL << 28)	\
+				| (PWM_SEL << 24)	\
+				| (UART4_SEL << 20)	\
+				| (UART3_SEL << 16)	\
+				| (UART2_SEL << 12)	\
+				| (UART1_SEL << 8)	\
+				| (UART0_SEL << 4))
+
+/* CLK_SRC_PERIC1 */
+/* SRC_CLOCK = SCLK_EPLL */
+#define SPI0_SEL		6
+#define SPI1_SEL		6
+#define SPI2_SEL		6
+#define AUDIO0_SEL		6
+#define AUDIO1_SEL		6
+#define AUDIO2_SEL		6
+#define CLK_SRC_PERIC1_VAL	((SPI2_SEL << 28)	\
+				| (SPI1_SEL << 24)	\
+				| (SPI0_SEL << 20)	\
+				| (AUDIO2_SEL << 16)	\
+				| (AUDIO2_SEL << 12)	\
+				| (AUDIO2_SEL << 8))
+
+/* CLK_DIV_PERIC0 */
+#define PWM_RATIO	8
+#define UART4_RATIO	9
+#define UART3_RATIO	9
+#define UART2_RATIO	9
+#define UART1_RATIO	9
+#define UART0_RATIO	9
+
+#define CLK_DIV_PERIC0_VAL	((PWM_RATIO << 28)	\
+				| (UART4_RATIO << 24)	\
+				| (UART3_RATIO << 20)    \
+				| (UART2_RATIO << 16)    \
+				| (UART1_RATIO << 12)    \
+				| (UART0_RATIO << 8))
+/* CLK_DIV_PERIC1 */
+#define SPI2_RATIO		0x1
+#define SPI1_RATIO		0x1
+#define SPI0_RATIO		0x1
+#define CLK_DIV_PERIC1_VAL	((SPI2_RATIO << 28)	\
+				| (SPI1_RATIO << 24)	\
+				| (SPI0_RATIO << 20))
+
+/* CLK_DIV_PERIC2 */
+#define PCM2_RATIO		0x3
+#define PCM1_RATIO		0x3
+#define CLK_DIV_PERIC2_VAL	((PCM2_RATIO << 24) \
+				| (PCM1_RATIO << 16))
+
+/* CLK_DIV_PERIC3 */
+#define AUDIO2_RATIO		0x5
+#define AUDIO1_RATIO		0x5
+#define AUDIO0_RATIO		0x5
+#define CLK_DIV_PERIC3_VAL	((AUDIO2_RATIO << 28)	\
+				| (AUDIO1_RATIO << 24)	\
+				| (AUDIO0_RATIO << 20))
+
+/* CLK_DIV_PERIC4 */
+#define SPI2_PRE_RATIO		0x2
+#define SPI1_PRE_RATIO		0x2
+#define SPI0_PRE_RATIO		0x2
+#define CLK_DIV_PERIC4_VAL	((SPI2_PRE_RATIO << 24)	\
+				| (SPI1_PRE_RATIO << 16) \
+				| (SPI0_PRE_RATIO << 8))
+
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL	0x10666600
+#define CLK_DIV_DISP1_0_VAL	0x01050211
+
+#define APLL_FOUT		(1 << 0)
+#define KPLL_FOUT		(1 << 0)
+
+#define CLK_DIV_CPERI1_VAL	0x3f3f0000
+#endif
+
+struct mem_timings;
+
+/* Errors that we can encourter in low-level setup */
+enum {
+	SETUP_ERR_OK,
+	SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
+	SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
+};
+
+/*
+ * Memory variant specific initialization code for DDR3
+ *
+ * @param mem		Memory timings for this memory type.
+ * @param mem_iv_size	Memory interleaving size is a configurable parameter
+ *			which the DMC uses to decide how to split a memory
+ *			chunk into smaller chunks to support concurrent
+ *			accesses; may vary across boards.
+ * @param reset         Reset DDR PHY during initialization.
+ * @return 0 if ok, SETUP_ERR_... if there is a problem
+ */
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+			int reset);
+
+/* Memory variant specific initialization code for LPDDR3 */
+void lpddr3_mem_ctrl_init(void);
+
+/*
+ * Configure ZQ I/O interface
+ *
+ * @param mem		Memory timings for this memory type.
+ * @param phy0_con16	Register address for dmc_phy0->phy_con16
+ * @param phy1_con16	Register address for dmc_phy1->phy_con16
+ * @param phy0_con17	Register address for dmc_phy0->phy_con17
+ * @param phy1_con17	Register address for dmc_phy1->phy_con17
+ * @return 0 if ok, -1 on error
+ */
+int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
+			uint32_t *phy1_con16, uint32_t *phy0_con17,
+			uint32_t *phy1_con17);
+/*
+ * Send NOP and MRS/EMRS Direct commands
+ *
+ * @param mem		Memory timings for this memory type.
+ * @param directcmd	Register address for dmc_phy->directcmd
+ */
+void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
+
+/*
+ * Send PALL Direct commands
+ *
+ * @param mem		Memory timings for this memory type.
+ * @param directcmd	Register address for dmc_phy->directcmd
+ */
+void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
+
+/*
+ * Reset the DLL. This function is common between DDR3 and LPDDR2.
+ * However, the reset value is different. So we are passing a flag
+ * ddr_mode to distinguish between LPDDR2 and DDR3.
+ *
+ * @param phycontrol0	Register address for dmc_phy->phycontrol0
+ * @param ddr_mode	Type of DDR memory
+ */
+void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/lowlevel_init.c
new file mode 100644
index 000000000..11fe5b8d0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -0,0 +1,73 @@
+/*
+ * Lowlevel setup for EXYNOS5 based board
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/power.h>
+#include <asm/arch/tzpc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include "common_setup.h"
+
+/* These are the things we can do during low-level init */
+enum {
+	DO_WAKEUP	= 1 << 0,
+	DO_CLOCKS	= 1 << 1,
+	DO_MEM_RESET	= 1 << 2,
+	DO_UART		= 1 << 3,
+};
+
+int do_lowlevel_init(void)
+{
+	uint32_t reset_status;
+	int actions = 0;
+
+	arch_cpu_init();
+
+	reset_status = get_reset_status();
+
+	switch (reset_status) {
+	case S5P_CHECK_SLEEP:
+		actions = DO_CLOCKS | DO_WAKEUP;
+		break;
+	case S5P_CHECK_DIDLE:
+	case S5P_CHECK_LPA:
+		actions = DO_WAKEUP;
+		break;
+	default:
+		/* This is a normal boot (not a wake from sleep) */
+		actions = DO_CLOCKS | DO_MEM_RESET;
+	}
+
+	if (actions & DO_CLOCKS) {
+		system_clock_init();
+		mem_ctrl_init(actions & DO_MEM_RESET);
+		tzpc_init();
+	}
+
+	return actions & DO_WAKEUP;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/pinmux.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/pinmux.c
new file mode 100644
index 000000000..9edb47502
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -0,0 +1,793 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics.
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sromc.h>
+
+static void exynos5_uart_config(int peripheral)
+{
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+	struct s5p_gpio_bank *bank;
+	int i, start, count;
+
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+		bank = &gpio1->a0;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART1:
+		bank = &gpio1->d0;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART2:
+		bank = &gpio1->a1;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART3:
+		bank = &gpio1->a1;
+		start = 4;
+		count = 2;
+		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return;
+	}
+	for (i = start; i < start + count; i++) {
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+	}
+}
+
+static void exynos5420_uart_config(int peripheral)
+{
+	struct exynos5420_gpio_part1 *gpio1 =
+		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+	struct s5p_gpio_bank *bank;
+	int i, start, count;
+
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+		bank = &gpio1->a0;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART1:
+		bank = &gpio1->a0;
+		start = 4;
+		count = 4;
+		break;
+	case PERIPH_ID_UART2:
+		bank = &gpio1->a1;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART3:
+		bank = &gpio1->a1;
+		start = 4;
+		count = 2;
+		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return;
+	}
+
+	for (i = start; i < start + count; i++) {
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+	}
+}
+
+static int exynos5_mmc_config(int peripheral, int flags)
+{
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+	struct s5p_gpio_bank *bank, *bank_ext;
+	int i, start = 0, gpio_func = 0;
+
+	switch (peripheral) {
+	case PERIPH_ID_SDMMC0:
+		bank = &gpio1->c0;
+		bank_ext = &gpio1->c1;
+		start = 0;
+		gpio_func = GPIO_FUNC(0x2);
+		break;
+	case PERIPH_ID_SDMMC1:
+		bank = &gpio1->c2;
+		bank_ext = NULL;
+		break;
+	case PERIPH_ID_SDMMC2:
+		bank = &gpio1->c3;
+		bank_ext = &gpio1->c4;
+		start = 3;
+		gpio_func = GPIO_FUNC(0x3);
+		break;
+	case PERIPH_ID_SDMMC3:
+		bank = &gpio1->c4;
+		bank_ext = NULL;
+		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	}
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+		debug("SDMMC device %d does not support 8bit mode",
+				peripheral);
+		return -1;
+	}
+	if (flags & PINMUX_FLAG_8BIT_MODE) {
+		for (i = start; i <= (start + 3); i++) {
+			s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
+			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		}
+	}
+	for (i = 0; i < 2; i++) {
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	}
+	for (i = 3; i <= 6; i++) {
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	}
+
+	return 0;
+}
+
+static int exynos5420_mmc_config(int peripheral, int flags)
+{
+	struct exynos5420_gpio_part3 *gpio3 =
+		(struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
+	struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
+	int i, start;
+
+	switch (peripheral) {
+	case PERIPH_ID_SDMMC0:
+		bank = &gpio3->c0;
+		bank_ext = &gpio3->c3;
+		start = 0;
+		break;
+	case PERIPH_ID_SDMMC1:
+		bank = &gpio3->c1;
+		bank_ext = &gpio3->d1;
+		start = 4;
+		break;
+	case PERIPH_ID_SDMMC2:
+		bank = &gpio3->c2;
+		bank_ext = NULL;
+		start = 0;
+		break;
+	default:
+		start = 0;
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	}
+
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+		debug("SDMMC device %d does not support 8bit mode",
+		      peripheral);
+		return -1;
+	}
+
+	if (flags & PINMUX_FLAG_8BIT_MODE) {
+		for (i = start; i <= (start + 3); i++) {
+			s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
+			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		}
+	}
+
+	for (i = 0; i < 3; i++) {
+		/*
+		 * MMC0 is intended to be used for eMMC. The
+		 * card detect pin is used as a VDDEN signal to
+		 * power on the eMMC. The 5420 iROM makes
+		 * this same assumption.
+		 */
+		if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
+			s5p_gpio_set_value(bank, i, 1);
+			s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
+		} else {
+			s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		}
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	}
+
+	for (i = 3; i <= 6; i++) {
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	}
+
+	return 0;
+}
+
+static void exynos5_sromc_config(int flags)
+{
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+	int i;
+
+	/*
+	 * SROM:CS1 and EBI
+	 *
+	 * GPY0[0]	SROM_CSn[0]
+	 * GPY0[1]	SROM_CSn[1](2)
+	 * GPY0[2]	SROM_CSn[2]
+	 * GPY0[3]	SROM_CSn[3]
+	 * GPY0[4]	EBI_OEn(2)
+	 * GPY0[5]	EBI_EEn(2)
+	 *
+	 * GPY1[0]	EBI_BEn[0](2)
+	 * GPY1[1]	EBI_BEn[1](2)
+	 * GPY1[2]	SROM_WAIT(2)
+	 * GPY1[3]	EBI_DATA_RDn(2)
+	 */
+	s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
+				GPIO_FUNC(2));
+	s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
+	s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+
+	for (i = 0; i < 4; i++)
+		s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+
+	/*
+	 * EBI: 8 Addrss Lines
+	 *
+	 * GPY3[0]	EBI_ADDR[0](2)
+	 * GPY3[1]	EBI_ADDR[1](2)
+	 * GPY3[2]	EBI_ADDR[2](2)
+	 * GPY3[3]	EBI_ADDR[3](2)
+	 * GPY3[4]	EBI_ADDR[4](2)
+	 * GPY3[5]	EBI_ADDR[5](2)
+	 * GPY3[6]	EBI_ADDR[6](2)
+	 * GPY3[7]	EBI_ADDR[7](2)
+	 *
+	 * EBI: 16 Data Lines
+	 *
+	 * GPY5[0]	EBI_DATA[0](2)
+	 * GPY5[1]	EBI_DATA[1](2)
+	 * GPY5[2]	EBI_DATA[2](2)
+	 * GPY5[3]	EBI_DATA[3](2)
+	 * GPY5[4]	EBI_DATA[4](2)
+	 * GPY5[5]	EBI_DATA[5](2)
+	 * GPY5[6]	EBI_DATA[6](2)
+	 * GPY5[7]	EBI_DATA[7](2)
+	 *
+	 * GPY6[0]	EBI_DATA[8](2)
+	 * GPY6[1]	EBI_DATA[9](2)
+	 * GPY6[2]	EBI_DATA[10](2)
+	 * GPY6[3]	EBI_DATA[11](2)
+	 * GPY6[4]	EBI_DATA[12](2)
+	 * GPY6[5]	EBI_DATA[13](2)
+	 * GPY6[6]	EBI_DATA[14](2)
+	 * GPY6[7]	EBI_DATA[15](2)
+	 */
+	for (i = 0; i < 8; i++) {
+		s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
+		s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+
+		s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
+		s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+
+		s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
+		s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+	}
+}
+
+static void exynos5_i2c_config(int peripheral, int flags)
+{
+
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+	switch (peripheral) {
+	case PERIPH_ID_I2C0:
+		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C1:
+		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C2:
+		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C3:
+		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C4:
+		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C5:
+		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C6:
+		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
+		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		break;
+	case PERIPH_ID_I2C7:
+		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		break;
+	}
+}
+
+static void exynos5420_i2c_config(int peripheral)
+{
+	struct exynos5420_gpio_part1 *gpio1 =
+		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+
+	switch (peripheral) {
+	case PERIPH_ID_I2C0:
+		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C1:
+		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C2:
+		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C3:
+		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C4:
+		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C5:
+		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C6:
+		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
+		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		break;
+	case PERIPH_ID_I2C7:
+		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C8:
+		s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C9:
+		s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C10:
+		s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
+		break;
+	}
+}
+
+static void exynos5_i2s_config(int peripheral)
+{
+	int i;
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
+	struct exynos5_gpio_part4 *gpio4 =
+		(struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
+
+	switch (peripheral) {
+	case PERIPH_ID_I2S0:
+		for (i = 0; i < 5; i++)
+			s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
+		break;
+	case PERIPH_ID_I2S1:
+		for (i = 0; i < 5; i++)
+			s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+		break;
+	}
+}
+
+void exynos5_spi_config(int peripheral)
+{
+	int cfg = 0, pin = 0, i;
+	struct s5p_gpio_bank *bank = NULL;
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+	struct exynos5_gpio_part2 *gpio2 =
+		(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
+
+	switch (peripheral) {
+	case PERIPH_ID_SPI0:
+		bank = &gpio1->a2;
+		cfg = GPIO_FUNC(0x2);
+		pin = 0;
+		break;
+	case PERIPH_ID_SPI1:
+		bank = &gpio1->a2;
+		cfg = GPIO_FUNC(0x2);
+		pin = 4;
+		break;
+	case PERIPH_ID_SPI2:
+		bank = &gpio1->b1;
+		cfg = GPIO_FUNC(0x5);
+		pin = 1;
+		break;
+	case PERIPH_ID_SPI3:
+		bank = &gpio2->f1;
+		cfg = GPIO_FUNC(0x2);
+		pin = 0;
+		break;
+	case PERIPH_ID_SPI4:
+		for (i = 0; i < 2; i++) {
+			s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
+			s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+		}
+		break;
+	}
+	if (peripheral != PERIPH_ID_SPI4) {
+		for (i = pin; i < pin + 4; i++)
+			s5p_gpio_cfg_pin(bank, i, cfg);
+	}
+}
+
+void exynos5420_spi_config(int peripheral)
+{
+	int cfg, pin, i;
+	struct s5p_gpio_bank *bank = NULL;
+	struct exynos5420_gpio_part1 *gpio1 =
+		(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+	struct exynos5420_gpio_part4 *gpio4 =
+		(struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
+
+	switch (peripheral) {
+	case PERIPH_ID_SPI0:
+		bank = &gpio1->a2;
+		cfg = GPIO_FUNC(0x2);
+		pin = 0;
+		break;
+	case PERIPH_ID_SPI1:
+		bank = &gpio1->a2;
+		cfg = GPIO_FUNC(0x2);
+		pin = 4;
+		break;
+	case PERIPH_ID_SPI2:
+		bank = &gpio1->b1;
+		cfg = GPIO_FUNC(0x5);
+		pin = 1;
+		break;
+	case PERIPH_ID_SPI3:
+		bank = &gpio4->f1;
+		cfg = GPIO_FUNC(0x2);
+		pin = 0;
+		break;
+	case PERIPH_ID_SPI4:
+		cfg = 0;
+		pin = 0;
+		break;
+	default:
+		cfg = 0;
+		pin = 0;
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return;
+	}
+
+	if (peripheral != PERIPH_ID_SPI4) {
+		for (i = pin; i < pin + 4; i++)
+			s5p_gpio_cfg_pin(bank, i, cfg);
+	} else {
+		for (i = 0; i < 2; i++) {
+			s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
+			s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
+		}
+	}
+}
+
+static int exynos5_pinmux_config(int peripheral, int flags)
+{
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+		exynos5_uart_config(peripheral);
+		break;
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC1:
+	case PERIPH_ID_SDMMC2:
+	case PERIPH_ID_SDMMC3:
+		return exynos5_mmc_config(peripheral, flags);
+	case PERIPH_ID_SROMC:
+		exynos5_sromc_config(flags);
+		break;
+	case PERIPH_ID_I2C0:
+	case PERIPH_ID_I2C1:
+	case PERIPH_ID_I2C2:
+	case PERIPH_ID_I2C3:
+	case PERIPH_ID_I2C4:
+	case PERIPH_ID_I2C5:
+	case PERIPH_ID_I2C6:
+	case PERIPH_ID_I2C7:
+		exynos5_i2c_config(peripheral, flags);
+		break;
+	case PERIPH_ID_I2S0:
+	case PERIPH_ID_I2S1:
+		exynos5_i2s_config(peripheral);
+		break;
+	case PERIPH_ID_SPI0:
+	case PERIPH_ID_SPI1:
+	case PERIPH_ID_SPI2:
+	case PERIPH_ID_SPI3:
+	case PERIPH_ID_SPI4:
+		exynos5_spi_config(peripheral);
+		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int exynos5420_pinmux_config(int peripheral, int flags)
+{
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+		exynos5420_uart_config(peripheral);
+		break;
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC1:
+	case PERIPH_ID_SDMMC2:
+	case PERIPH_ID_SDMMC3:
+		return exynos5420_mmc_config(peripheral, flags);
+	case PERIPH_ID_SPI0:
+	case PERIPH_ID_SPI1:
+	case PERIPH_ID_SPI2:
+	case PERIPH_ID_SPI3:
+	case PERIPH_ID_SPI4:
+		exynos5420_spi_config(peripheral);
+		break;
+	case PERIPH_ID_I2C0:
+	case PERIPH_ID_I2C1:
+	case PERIPH_ID_I2C2:
+	case PERIPH_ID_I2C3:
+	case PERIPH_ID_I2C4:
+	case PERIPH_ID_I2C5:
+	case PERIPH_ID_I2C6:
+	case PERIPH_ID_I2C7:
+	case PERIPH_ID_I2C8:
+	case PERIPH_ID_I2C9:
+	case PERIPH_ID_I2C10:
+		exynos5420_i2c_config(peripheral);
+		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	}
+
+	return 0;
+}
+
+static void exynos4_i2c_config(int peripheral, int flags)
+{
+	struct exynos4_gpio_part1 *gpio1 =
+		(struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+
+	switch (peripheral) {
+	case PERIPH_ID_I2C0:
+		s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C1:
+		s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
+		s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+		break;
+	case PERIPH_ID_I2C2:
+		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C3:
+		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C4:
+		s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C5:
+		s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+		break;
+	case PERIPH_ID_I2C6:
+		s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
+		s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+		break;
+	case PERIPH_ID_I2C7:
+		s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
+		s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+		break;
+	}
+}
+
+static int exynos4_mmc_config(int peripheral, int flags)
+{
+	struct exynos4_gpio_part2 *gpio2 =
+		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+	struct s5p_gpio_bank *bank, *bank_ext;
+	int i;
+
+	switch (peripheral) {
+	case PERIPH_ID_SDMMC0:
+		bank = &gpio2->k0;
+		bank_ext = &gpio2->k1;
+		break;
+	case PERIPH_ID_SDMMC2:
+		bank = &gpio2->k2;
+		bank_ext = &gpio2->k3;
+		break;
+	default:
+		return -1;
+	}
+	for (i = 0; i < 7; i++) {
+		if (i == 2)
+			continue;
+		s5p_gpio_cfg_pin(bank, i,  GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	}
+	if (flags & PINMUX_FLAG_8BIT_MODE) {
+		for (i = 3; i < 7; i++) {
+			s5p_gpio_cfg_pin(bank_ext, i,  GPIO_FUNC(0x3));
+			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
+			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		}
+	}
+
+	return 0;
+}
+
+static void exynos4_uart_config(int peripheral)
+{
+	struct exynos4_gpio_part1 *gpio1 =
+		(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
+	struct s5p_gpio_bank *bank;
+	int i, start, count;
+
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+		bank = &gpio1->a0;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART1:
+		bank = &gpio1->a0;
+		start = 4;
+		count = 4;
+		break;
+	case PERIPH_ID_UART2:
+		bank = &gpio1->a1;
+		start = 0;
+		count = 4;
+		break;
+	case PERIPH_ID_UART3:
+		bank = &gpio1->a1;
+		start = 4;
+		count = 2;
+		break;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return;
+	}
+	for (i = start; i < start + count; i++) {
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+	}
+}
+static int exynos4_pinmux_config(int peripheral, int flags)
+{
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+		exynos4_uart_config(peripheral);
+		break;
+	case PERIPH_ID_I2C0:
+	case PERIPH_ID_I2C1:
+	case PERIPH_ID_I2C2:
+	case PERIPH_ID_I2C3:
+	case PERIPH_ID_I2C4:
+	case PERIPH_ID_I2C5:
+	case PERIPH_ID_I2C6:
+	case PERIPH_ID_I2C7:
+		exynos4_i2c_config(peripheral, flags);
+		break;
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC2:
+		return exynos4_mmc_config(peripheral, flags);
+	case PERIPH_ID_SDMMC1:
+	case PERIPH_ID_SDMMC3:
+	case PERIPH_ID_SDMMC4:
+		debug("SDMMC device %d not implemented\n", peripheral);
+		return -1;
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	}
+
+	return 0;
+}
+
+int exynos_pinmux_config(int peripheral, int flags)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_pinmux_config(peripheral, flags);
+		else if (proid_is_exynos5250())
+			return exynos5_pinmux_config(peripheral, flags);
+	} else if (cpu_is_exynos4()) {
+		return exynos4_pinmux_config(peripheral, flags);
+	} else {
+		debug("pinmux functionality not supported\n");
+	}
+
+	return -1;
+}
+
+#ifdef CONFIG_OF_CONTROL
+static int exynos4_pinmux_decode_periph_id(const void *blob, int node)
+{
+	int err;
+	u32 cell[3];
+
+	err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+					ARRAY_SIZE(cell));
+	if (err) {
+		debug(" invalid peripheral id\n");
+		return PERIPH_ID_NONE;
+	}
+
+	return cell[1];
+}
+
+static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
+{
+	int err;
+	u32 cell[3];
+
+	err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+					ARRAY_SIZE(cell));
+	if (err)
+		return PERIPH_ID_NONE;
+
+	return cell[1];
+}
+
+int pinmux_decode_periph_id(const void *blob, int node)
+{
+	if (cpu_is_exynos5())
+		return  exynos5_pinmux_decode_periph_id(blob, node);
+	else if (cpu_is_exynos4())
+		return  exynos4_pinmux_decode_periph_id(blob, node);
+	else
+		return PERIPH_ID_NONE;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/power.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/power.c
new file mode 100644
index 000000000..563abd750
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/power.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/power.h>
+
+static void exynos4_mipi_phy_control(unsigned int dev_index,
+					unsigned int enable)
+{
+	struct exynos4_power *pmu =
+	    (struct exynos4_power *)samsung_get_base_power();
+	unsigned int addr, cfg = 0;
+
+	if (dev_index == 0)
+		addr = (unsigned int)&pmu->mipi_phy0_control;
+	else
+		addr = (unsigned int)&pmu->mipi_phy1_control;
+
+
+	cfg = readl(addr);
+	if (enable)
+		cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
+	else
+		cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
+
+	writel(cfg, addr);
+}
+
+void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
+{
+	if (cpu_is_exynos4())
+		exynos4_mipi_phy_control(dev_index, enable);
+}
+
+void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	if (enable) {
+		/* Enabling USBHOST_PHY */
+		setbits_le32(&power->usbhost_phy_control,
+				POWER_USB_HOST_PHY_CTRL_EN);
+	} else {
+		/* Disabling USBHOST_PHY */
+		clrbits_le32(&power->usbhost_phy_control,
+				POWER_USB_HOST_PHY_CTRL_EN);
+	}
+}
+
+void set_usbhost_phy_ctrl(unsigned int enable)
+{
+	if (cpu_is_exynos5())
+		exynos5_set_usbhost_phy_ctrl(enable);
+}
+
+static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	if (enable) {
+		/* Enabling USBDRD_PHY */
+		setbits_le32(&power->usbdrd_phy_control,
+				POWER_USB_DRD_PHY_CTRL_EN);
+	} else {
+		/* Disabling USBDRD_PHY */
+		clrbits_le32(&power->usbdrd_phy_control,
+				POWER_USB_DRD_PHY_CTRL_EN);
+	}
+}
+
+void set_usbdrd_phy_ctrl(unsigned int enable)
+{
+	if (cpu_is_exynos5())
+		exynos5_set_usbdrd_phy_ctrl(enable);
+}
+
+static void exynos5_dp_phy_control(unsigned int enable)
+{
+	unsigned int cfg;
+	struct exynos5_power *power =
+	    (struct exynos5_power *)samsung_get_base_power();
+
+	cfg = readl(&power->dptx_phy_control);
+	if (enable)
+		cfg |= EXYNOS_DP_PHY_ENABLE;
+	else
+		cfg &= ~EXYNOS_DP_PHY_ENABLE;
+
+	writel(cfg, &power->dptx_phy_control);
+}
+
+void set_dp_phy_ctrl(unsigned int enable)
+{
+	if (cpu_is_exynos5())
+		exynos5_dp_phy_control(enable);
+}
+
+static void exynos5_set_ps_hold_ctrl(void)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	/* Set PS-Hold high */
+	setbits_le32(&power->ps_hold_control,
+			EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
+}
+
+void set_ps_hold_ctrl(void)
+{
+	if (cpu_is_exynos5())
+		exynos5_set_ps_hold_ctrl();
+}
+
+
+static void exynos5_set_xclkout(void)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	/* use xxti for xclk out */
+	clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
+				PMU_DEBUG_XXTI);
+}
+
+void set_xclkout(void)
+{
+	if (cpu_is_exynos5())
+		exynos5_set_xclkout();
+}
+
+/* Enables hardware tripping to power off the system when TMU fails */
+void set_hw_thermal_trip(void)
+{
+	if (cpu_is_exynos5()) {
+		struct exynos5_power *power =
+			(struct exynos5_power *)samsung_get_base_power();
+
+		/* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
+		setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
+	}
+}
+
+static uint32_t exynos5_get_reset_status(void)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	return power->inform1;
+}
+
+static uint32_t exynos4_get_reset_status(void)
+{
+	struct exynos4_power *power =
+		(struct exynos4_power *)samsung_get_base_power();
+
+	return power->inform1;
+}
+
+uint32_t get_reset_status(void)
+{
+	if (cpu_is_exynos5())
+		return exynos5_get_reset_status();
+	else
+		return  exynos4_get_reset_status();
+}
+
+static void exynos5_power_exit_wakeup(void)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+	typedef void (*resume_func)(void);
+
+	((resume_func)power->inform0)();
+}
+
+static void exynos4_power_exit_wakeup(void)
+{
+	struct exynos4_power *power =
+		(struct exynos4_power *)samsung_get_base_power();
+	typedef void (*resume_func)(void);
+
+	((resume_func)power->inform0)();
+}
+
+void power_exit_wakeup(void)
+{
+	if (cpu_is_exynos5())
+		exynos5_power_exit_wakeup();
+	else
+		exynos4_power_exit_wakeup();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c
new file mode 100644
index 000000000..8c7d7d893
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
+
+enum l2_cache_params {
+	CACHE_TAG_RAM_SETUP = (1 << 9),
+	CACHE_DATA_RAM_SETUP = (1 << 5),
+	CACHE_TAG_RAM_LATENCY = (2 << 6),
+	CACHE_DATA_RAM_LATENCY = (2 << 0)
+};
+
+void reset_cpu(ulong addr)
+{
+	writel(0x1, samsung_get_base_swreset());
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Set L2 cache parameters
+ */
+static void exynos5_set_l2cache_params(void)
+{
+	unsigned int val = 0;
+
+	asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
+
+	val |= CACHE_TAG_RAM_SETUP |
+		CACHE_DATA_RAM_SETUP |
+		CACHE_TAG_RAM_LATENCY |
+		CACHE_DATA_RAM_LATENCY;
+
+	asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
+}
+
+/*
+ * Sets L2 cache related parameters before enabling data cache
+ */
+void v7_outer_cache_enable(void)
+{
+	if (cpu_is_exynos5())
+		exynos5_set_l2cache_params();
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/spl_boot.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/spl_boot.c
new file mode 100644
index 000000000..ade45fd5d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include<common.h>
+#include<config.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/spi.h>
+
+#include "common_setup.h"
+#include "clock_init.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+#define OM_STAT         (0x1f << 1)
+
+/* Index into irom ptr table */
+enum index {
+	MMC_INDEX,
+	EMMC44_INDEX,
+	EMMC44_END_INDEX,
+	SPI_INDEX,
+	USB_INDEX,
+};
+
+/* IROM Function Pointers Table */
+u32 irom_ptr_table[] = {
+	[MMC_INDEX] = 0x02020030,	/* iROM Function Pointer-SDMMC boot */
+	[EMMC44_INDEX] = 0x02020044,	/* iROM Function Pointer-EMMC4.4 boot*/
+	[EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
+						-EMMC4.4 end boot operation */
+	[SPI_INDEX] = 0x02020058,	/* iROM Function Pointer-SPI boot */
+	[USB_INDEX] = 0x02020070,	/* iROM Function Pointer-USB boot*/
+	};
+
+void *get_irom_func(int index)
+{
+	return (void *)*(u32 *)irom_ptr_table[index];
+}
+
+#ifdef CONFIG_USB_BOOTING
+/*
+ * Set/clear program flow prediction and return the previous state.
+ */
+static int config_branch_prediction(int set_cr_z)
+{
+	unsigned int cr;
+
+	/* System Control Register: 11th bit Z Branch prediction enable */
+	cr = get_cr();
+	set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
+
+	return cr & CR_Z;
+}
+#endif
+
+#ifdef CONFIG_SPI_BOOTING
+static void spi_rx_tx(struct exynos_spi *regs, int todo,
+			void *dinp, void const *doutp, int i)
+{
+	uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
+	int rx_lvl, tx_lvl;
+	uint out_bytes, in_bytes;
+
+	out_bytes = todo;
+	in_bytes = todo;
+	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+
+	while (in_bytes) {
+		uint32_t spi_sts;
+		int temp;
+
+		spi_sts = readl(&regs->spi_sts);
+		rx_lvl = ((spi_sts >> 15) & 0x7f);
+		tx_lvl = ((spi_sts >> 6) & 0x7f);
+		while (tx_lvl < 32 && out_bytes) {
+			temp = 0xffffffff;
+			writel(temp, &regs->tx_data);
+			out_bytes -= 4;
+			tx_lvl += 4;
+		}
+		while (rx_lvl >= 4 && in_bytes) {
+			temp = readl(&regs->rx_data);
+			if (rxp)
+				*rxp++ = temp;
+			in_bytes -= 4;
+			rx_lvl -= 4;
+		}
+	}
+}
+
+/*
+ * Copy uboot from spi flash to RAM
+ *
+ * @parma uboot_size	size of u-boot to copy
+ * @param uboot_addr	address in u-boot to copy
+ */
+static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
+{
+	int upto, todo;
+	int i, timeout = 100;
+	struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
+
+	set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
+	/* set the spi1 GPIO */
+	exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
+
+	/* set pktcnt and enable it */
+	writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+	/* set FB_CLK_SEL */
+	writel(SPI_FB_DELAY_180, &regs->fb_clk);
+	/* set CH_WIDTH and BUS_WIDTH as word */
+	setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
+					SPI_MODE_BUS_WIDTH_WORD);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
+
+	/* clear rx and tx channel if set priveously */
+	clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
+
+	setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
+			SPI_RX_BYTE_SWAP |
+			SPI_RX_HWORD_SWAP);
+
+	/* do a soft reset */
+	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+
+	/* now set rx and tx channel ON */
+	setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
+	clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
+
+	/* Send read instruction (0x3h) followed by a 24 bit addr */
+	writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
+
+	/* waiting for TX done */
+	while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
+		if (!timeout) {
+			debug("SPI TIMEOUT\n");
+			break;
+		}
+		timeout--;
+	}
+
+	for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
+		todo = min(uboot_size - upto, (1 << 15));
+		spi_rx_tx(regs, todo, (void *)(uboot_addr),
+			  (void *)(SPI_FLASH_UBOOT_POS), i);
+	}
+
+	setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
+
+	/*
+	 * Let put controller mode to BYTE as
+	 * SPI driver does not support WORD mode yet
+	 */
+	clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
+					SPI_MODE_BUS_WIDTH_WORD);
+	writel(0, &regs->swap_cfg);
+
+	/*
+	 * Flush spi tx, rx fifos and reset the SPI controller
+	 * and clear rx/tx channel
+	 */
+	clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
+}
+#endif
+
+/*
+* Copy U-boot from mmc to RAM:
+* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
+* Pointer to API (Data transfer from mmc to ram)
+*/
+void copy_uboot_to_ram(void)
+{
+	enum boot_mode bootmode = BOOT_MODE_OM;
+
+	u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
+	u32 offset = 0, size = 0;
+#ifdef CONFIG_SPI_BOOTING
+	struct spl_machine_param *param = spl_get_machine_params();
+#endif
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
+	void (*end_bootop_from_emmc)(void);
+#endif
+#ifdef CONFIG_USB_BOOTING
+	u32 (*usb_copy)(void);
+	int is_cr_z_set;
+	unsigned int sec_boot_check;
+
+	/* Read iRAM location to check for secondary USB boot mode */
+	sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
+	if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
+		bootmode = BOOT_MODE_USB;
+#endif
+
+	if (bootmode == BOOT_MODE_OM)
+		bootmode = readl(samsung_get_base_power()) & OM_STAT;
+
+	switch (bootmode) {
+#ifdef CONFIG_SPI_BOOTING
+	case BOOT_MODE_SERIAL:
+		/* Customised function to copy u-boot from SF */
+		exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
+		break;
+#endif
+	case BOOT_MODE_MMC:
+		offset = BL2_START_OFFSET;
+		size = BL2_SIZE_BLOC_COUNT;
+		copy_bl2 = get_irom_func(MMC_INDEX);
+		break;
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	case BOOT_MODE_EMMC:
+		/* Set the FSYS1 clock divisor value for EMMC boot */
+		emmc_boot_clk_div_set();
+
+		copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
+		end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
+
+		copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
+		end_bootop_from_emmc();
+		break;
+#endif
+#ifdef CONFIG_USB_BOOTING
+	case BOOT_MODE_USB:
+		/*
+		 * iROM needs program flow prediction to be disabled
+		 * before copy from USB device to RAM
+		 */
+		is_cr_z_set = config_branch_prediction(0);
+		usb_copy = get_irom_func(USB_INDEX);
+		usb_copy();
+		config_branch_prediction(is_cr_z_set);
+		break;
+#endif
+	default:
+		break;
+	}
+
+	if (copy_bl2)
+		copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
+}
+
+void memzero(void *s, size_t n)
+{
+	char *ptr = s;
+	size_t i;
+
+	for (i = 0; i < n; i++)
+		*ptr++ = '\0';
+}
+
+/**
+ * Set up the U-Boot global_data pointer
+ *
+ * This sets the address of the global data, and sets up basic values.
+ *
+ * @param gdp   Value to give to gd
+ */
+static void setup_global_data(gd_t *gdp)
+{
+	gd = gdp;
+	memzero((void *)gd, sizeof(gd_t));
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	gd->have_console = 1;
+}
+
+void board_init_f(unsigned long bootflag)
+{
+	__aligned(8) gd_t local_gd;
+	__attribute__((noreturn)) void (*uboot)(void);
+
+	setup_global_data(&local_gd);
+
+	if (do_lowlevel_init())
+		power_exit_wakeup();
+
+	copy_uboot_to_ram();
+
+	/* Jump to U-Boot image */
+	uboot = (void *)CONFIG_SYS_TEXT_BASE;
+	(*uboot)();
+	/* Never returns Here */
+}
+
+/* Place Holders */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	/* Function attribute is no-return */
+	/* This Function never executes */
+	while (1)
+		;
+}
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/system.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/system.c
new file mode 100644
index 000000000..ad1244583
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/system.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system.h>
+
+static void exynos5_set_usbhost_mode(unsigned int mode)
+{
+	struct exynos5_sysreg *sysreg =
+		(struct exynos5_sysreg *)samsung_get_base_sysreg();
+
+	/* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
+	if (mode == USB20_PHY_CFG_HOST_LINK_EN) {
+		setbits_le32(&sysreg->usb20phy_cfg,
+				USB20_PHY_CFG_HOST_LINK_EN);
+	} else {
+		clrbits_le32(&sysreg->usb20phy_cfg,
+				USB20_PHY_CFG_HOST_LINK_EN);
+	}
+}
+
+void set_usbhost_mode(unsigned int mode)
+{
+	if (cpu_is_exynos5())
+		exynos5_set_usbhost_mode(mode);
+}
+
+static void exynos4_set_system_display(void)
+{
+	struct exynos4_sysreg *sysreg =
+	    (struct exynos4_sysreg *)samsung_get_base_sysreg();
+	unsigned int cfg = 0;
+
+	/*
+	 * system register path set
+	 * 0: MIE/MDNIE
+	 * 1: FIMD Bypass
+	 */
+	cfg = readl(&sysreg->display_ctrl);
+	cfg |= (1 << 1);
+	writel(cfg, &sysreg->display_ctrl);
+}
+
+static void exynos5_set_system_display(void)
+{
+	struct exynos5_sysreg *sysreg =
+	    (struct exynos5_sysreg *)samsung_get_base_sysreg();
+	unsigned int cfg = 0;
+
+	/*
+	 * system register path set
+	 * 0: MIE/MDNIE
+	 * 1: FIMD Bypass
+	 */
+	cfg = readl(&sysreg->disp1blk_cfg);
+	cfg |= (1 << 15);
+	writel(cfg, &sysreg->disp1blk_cfg);
+}
+
+void set_system_display_ctrl(void)
+{
+	if (cpu_is_exynos4())
+		exynos4_set_system_display();
+	else
+		exynos5_set_system_display();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/tzpc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/tzpc.c
new file mode 100644
index 000000000..395077cf2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/tzpc.c
@@ -0,0 +1,41 @@
+/*
+ * Lowlevel setup for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/tzpc.h>
+#include <asm/io.h>
+
+/* Setting TZPC[TrustZone Protection Controller] */
+void tzpc_init(void)
+{
+	struct exynos_tzpc *tzpc;
+	unsigned int addr, start = 0, end = 0;
+
+	start = samsung_get_base_tzpc();
+
+	if (cpu_is_exynos5())
+		end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+	else if (cpu_is_exynos4())
+		end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+
+	for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) {
+		tzpc = (struct exynos_tzpc *)addr;
+
+		if (addr == start)
+			writel(R0SIZE, &tzpc->r0size);
+
+		writel(DECPROTXSET, &tzpc->decprot0set);
+		writel(DECPROTXSET, &tzpc->decprot1set);
+
+		if (cpu_is_exynos5() && (addr == end))
+			break;
+
+		writel(DECPROTXSET, &tzpc->decprot2set);
+		writel(DECPROTXSET, &tzpc->decprot3set);
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/highbank/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/highbank/Makefile
new file mode 100644
index 000000000..876099d9a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/highbank/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/highbank/timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/highbank/timer.c
new file mode 100644
index 000000000..d56bf2113
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/highbank/timer.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * Based on arm926ejs/mx27/timer.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-armv7/systimer.h>
+
+#undef SYSTIMER_BASE
+#define SYSTIMER_BASE		0xFFF34000	/* Timer 0 and 1 base	*/
+
+static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
+
+/*
+ * Start the timer
+ */
+int timer_init(void)
+{
+	/*
+	 * Setup timer0
+	 */
+	writel(0, &systimer_base->timer0control);
+	writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
+	writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
+	writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
+		&systimer_base->timer0control);
+
+	return 0;
+
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/Makefile
new file mode 100644
index 000000000..b1bd0224e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/Makefile
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2012-2014
+#     Texas Instruments Incorporated, <www.ti.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= aemif.o
+obj-y	+= init.o
+obj-y	+= psc.o
+obj-y	+= clock.o
+obj-y	+= cmd_clock.o
+obj-y	+= cmd_mon.o
+obj-y	+= keystone_nav.o
+obj-y	+= msmc.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
+obj-y	+= ddr3.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/aemif.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/aemif.c
new file mode 100644
index 000000000..9b26886db
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/aemif.c
@@ -0,0 +1,71 @@
+/*
+ * Keystone2: Asynchronous EMIF Configuration
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/emif_defs.h>
+
+#define AEMIF_CFG_SELECT_STROBE(v)	((v) ? 1 << 31 : 0)
+#define AEMIF_CFG_EXTEND_WAIT(v)	((v) ? 1 << 30 : 0)
+#define AEMIF_CFG_WR_SETUP(v)		(((v) & 0x0f) << 26)
+#define AEMIF_CFG_WR_STROBE(v)		(((v) & 0x3f) << 20)
+#define AEMIF_CFG_WR_HOLD(v)		(((v) & 0x07) << 17)
+#define AEMIF_CFG_RD_SETUP(v)		(((v) & 0x0f) << 13)
+#define AEMIF_CFG_RD_STROBE(v)		(((v) & 0x3f) << 7)
+#define AEMIF_CFG_RD_HOLD(v)		(((v) & 0x07) << 4)
+#define AEMIF_CFG_TURN_AROUND(v)	(((v) & 0x03) << 2)
+#define AEMIF_CFG_WIDTH(v)		(((v) & 0x03) << 0)
+
+#define set_config_field(reg, field, val)			\
+	do {							\
+		if (val != -1) {				\
+			reg &= ~AEMIF_CFG_##field(0xffffffff);	\
+			reg |=	AEMIF_CFG_##field(val);		\
+		}						\
+	} while (0)
+
+void configure_async_emif(int cs, struct async_emif_config *cfg)
+{
+	unsigned long tmp;
+
+	if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
+		tmp = __raw_readl(&davinci_emif_regs->nandfcr);
+		tmp |= (1 << cs);
+		__raw_writel(tmp, &davinci_emif_regs->nandfcr);
+
+	} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
+		tmp = __raw_readl(&davinci_emif_regs->one_nand_cr);
+		tmp |= (1 << cs);
+		__raw_writel(tmp, &davinci_emif_regs->one_nand_cr);
+	}
+
+	tmp = __raw_readl(&davinci_emif_regs->abncr[cs]);
+
+	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
+	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
+	set_config_field(tmp, WR_SETUP,		cfg->wr_setup);
+	set_config_field(tmp, WR_STROBE,	cfg->wr_strobe);
+	set_config_field(tmp, WR_HOLD,		cfg->wr_hold);
+	set_config_field(tmp, RD_SETUP,		cfg->rd_setup);
+	set_config_field(tmp, RD_STROBE,	cfg->rd_strobe);
+	set_config_field(tmp, RD_HOLD,		cfg->rd_hold);
+	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
+	set_config_field(tmp, WIDTH,		cfg->width);
+
+	__raw_writel(tmp, &davinci_emif_regs->abncr[cs]);
+}
+
+void init_async_emif(int num_cs, struct async_emif_config *config)
+{
+	int cs;
+
+	for (cs = 0; cs < num_cs; cs++)
+		configure_async_emif(cs, config + cs);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/clock.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/clock.c
new file mode 100644
index 000000000..bfa4c9d8f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/clock.c
@@ -0,0 +1,318 @@
+/*
+ * Keystone2: pll initialization
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+static void wait_for_completion(const struct pll_init_data *data)
+{
+	int i;
+	for (i = 0; i < 100; i++) {
+		sdelay(450);
+		if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
+			break;
+	}
+}
+
+struct pll_regs {
+	u32	reg0, reg1;
+};
+
+static const struct pll_regs pll_regs[] = {
+	[CORE_PLL]	= { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
+	[PASS_PLL]	= { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
+	[TETRIS_PLL]	= { K2HK_ARMPLLCTL0,  K2HK_ARMPLLCTL1},
+	[DDR3A_PLL]	= { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
+	[DDR3B_PLL]	= { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
+};
+
+/* Fout = Fref * NF(mult) / NR(prediv) / OD */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == CORE_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+			/* PLL mode */
+			tmp = __raw_readl(K2HK_MAINPLLCTL0);
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+				(pllctl_reg_read(pll, mult) &
+				 PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) >>
+				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = K2HK_PASSPLLCTL0;
+			break;
+		case TETRIS_PLL:
+			ret = external_clk[tetris_clk];
+			reg = K2HK_ARMPLLCTL0;
+			break;
+		case DDR3A_PLL:
+			ret = external_clk[ddr3a_clk];
+			reg = K2HK_DDR3APLLCTL0;
+			break;
+		case DDR3B_PLL:
+			ret = external_clk[ddr3b_clk];
+			reg = K2HK_DDR3BPLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+
+		if (!(tmp & PLLCTL_BYPASS)) {
+			/* Bypass disabled */
+			prediv = (tmp & PLL_DIV_MASK) + 1;
+			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+				      PLL_CLKOD_MASK) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	switch (clk) {
+	case core_pll_clk:	return pll_freq_get(CORE_PLL);
+	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
+	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
+	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
+	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
+	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
+	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
+	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
+	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
+	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
+	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
+	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
+	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
+	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
+	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
+	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
+	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
+	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
+	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
+	default:
+		break;
+	}
+	return 0;
+}
+
+void init_pll(const struct pll_init_data *data)
+{
+	u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
+
+	pllm = data->pll_m - 1;
+	plld = (data->pll_d - 1) & PLL_DIV_MASK;
+	pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
+
+	if (data->pll == MAIN_PLL) {
+		/* The requered delay before main PLL configuration */
+		sdelay(210000);
+
+		tmp = pllctl_reg_read(data->pll, secctl);
+
+		if (tmp & (PLLCTL_BYPASS)) {
+			setbits_le32(pll_regs[data->pll].reg1,
+				     BIT(MAIN_ENSAT_OFFSET));
+
+			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
+					   PLLCTL_PLLENSRC);
+			sdelay(340);
+
+			pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
+			pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+			sdelay(21000);
+
+			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+		} else {
+			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
+					   PLLCTL_PLLENSRC);
+			sdelay(340);
+		}
+
+		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
+
+		clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
+				(pllm << 6));
+
+		/* Set the BWADJ     (12 bit field)  */
+		tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
+		clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
+				(tmp_ctl << PLL_BWADJ_LO_SHIFT));
+		clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
+				(tmp_ctl >> 8));
+
+		/*
+		 * Set the pll divider (6 bit field) *
+		 * PLLD[5:0] is located in MAINPLLCTL0
+		 */
+		clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
+
+		/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
+		pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
+			       (pllod << PLL_CLKOD_SHIFT));
+		wait_for_completion(data);
+
+		pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
+		pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
+		pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
+		pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
+		pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
+
+		pllctl_reg_setbits(data->pll, alnctl, 0x1f);
+
+		/*
+		 * Set GOSET bit in PLLCMD to initiate the GO operation
+		 * to change the divide
+		 */
+		pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
+		sdelay(1500); /* wait for the phase adj */
+		wait_for_completion(data);
+
+		/* Reset PLL */
+		pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
+		sdelay(21000);	/* Wait for a minimum of 7 us*/
+		pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
+		sdelay(105000);	/* Wait for PLL Lock time (min 50 us) */
+
+		pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
+
+		tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+
+	} else if (data->pll == TETRIS_PLL) {
+		bwadj = pllm >> 1;
+		/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
+		setbits_le32(pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
+		/*
+		 * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
+		 * only applicable for Kepler
+		 */
+		clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+		/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
+		setbits_le32(pll_regs[data->pll].reg1 ,
+			     PLL_PLLRST | PLLCTL_ENSAT);
+
+		/*
+		 * 3 Program PLLM and PLLD in PLLCTL0 register
+		 * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
+		 * PLLCTL1 register. BWADJ value must be set
+		 * to ((PLLM + 1) >> 1) – 1)
+		 */
+		tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
+			(pllm << 6) |
+			(plld & PLL_DIV_MASK) |
+			(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
+		__raw_writel(tmp, pll_regs[data->pll].reg0);
+
+		/* Set BWADJ[11:8] bits */
+		tmp = __raw_readl(pll_regs[data->pll].reg1);
+		tmp &= ~(PLL_BWADJ_HI_MASK);
+		tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
+		__raw_writel(tmp, pll_regs[data->pll].reg1);
+		/*
+		 * 5 Wait for at least 5 us based on the reference
+		 * clock (PLL reset time)
+		 */
+		sdelay(21000);	/* Wait for a minimum of 7 us*/
+
+		/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
+		clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
+		/*
+		 * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
+		 * (PLL lock time)
+		 */
+		sdelay(105000);
+		/* 8 disable bypass */
+		clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+		/*
+		 * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
+		 * only applicable for Kepler
+		 */
+		setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+	} else {
+		setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
+		/*
+		 * process keeps state of Bypass bit while programming
+		 * all other DDR PLL settings
+		 */
+		tmp = __raw_readl(pll_regs[data->pll].reg0);
+		tmp &= PLLCTL_BYPASS;	/* clear everything except Bypass */
+
+		/*
+		 * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
+		 * bypass disabled
+		 */
+		bwadj = pllm >> 1;
+		tmp |= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) |
+			(pllm << PLL_MULT_SHIFT) |
+			(plld & PLL_DIV_MASK) |
+			(pllod << PLL_CLKOD_SHIFT);
+		__raw_writel(tmp, pll_regs[data->pll].reg0);
+
+		/* Set BWADJ[11:8] bits */
+		tmp = __raw_readl(pll_regs[data->pll].reg1);
+		tmp &= ~(PLL_BWADJ_HI_MASK);
+		tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
+
+		/* set PLL Select (bit 13) for PASS PLL */
+		if (data->pll == PASS_PLL)
+			tmp |= PLLCTL_PAPLL;
+
+		__raw_writel(tmp, pll_regs[data->pll].reg1);
+
+		/* Reset bit: bit 14 for both DDR3 & PASS PLL */
+		tmp = PLL_PLLRST;
+		/* Set RESET bit = 1 */
+		setbits_le32(pll_regs[data->pll].reg1, tmp);
+		/* Wait for a minimum of 7 us*/
+		sdelay(21000);
+		/* Clear RESET bit */
+		clrbits_le32(pll_regs[data->pll].reg1, tmp);
+		sdelay(105000);
+
+		/* clear BYPASS (Enable PLL Mode) */
+		clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
+		sdelay(21000);	/* Wait for a minimum of 7 us*/
+	}
+
+	/*
+	 * This is required to provide a delay between multiple
+	 * consequent PPL configurations
+	 */
+	sdelay(210000);
+}
+
+void init_plls(int num_pll, struct pll_init_data *config)
+{
+	int i;
+
+	for (i = 0; i < num_pll; i++)
+		init_pll(&config[i]);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/cmd_clock.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/cmd_clock.c
new file mode 100644
index 000000000..afd30f385
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/cmd_clock.c
@@ -0,0 +1,124 @@
+/*
+ * keystone2: commands for clocks
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/psc_defs.h>
+
+struct pll_init_data cmd_pll_data = {
+	.pll			= MAIN_PLL,
+	.pll_m			= 16,
+	.pll_d			= 1,
+	.pll_od			= 2,
+};
+
+int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 5)
+		goto pll_cmd_usage;
+
+	if (strncmp(argv[1], "pa", 2) == 0)
+		cmd_pll_data.pll = PASS_PLL;
+	else if (strncmp(argv[1], "arm", 3) == 0)
+		cmd_pll_data.pll = TETRIS_PLL;
+	else if (strncmp(argv[1], "ddr3a", 5) == 0)
+		cmd_pll_data.pll = DDR3A_PLL;
+	else if (strncmp(argv[1], "ddr3b", 5) == 0)
+		cmd_pll_data.pll = DDR3B_PLL;
+	else
+		goto pll_cmd_usage;
+
+	cmd_pll_data.pll_m   = simple_strtoul(argv[2], NULL, 10);
+	cmd_pll_data.pll_d   = simple_strtoul(argv[3], NULL, 10);
+	cmd_pll_data.pll_od  = simple_strtoul(argv[4], NULL, 10);
+
+	printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
+	       cmd_pll_data.pll, cmd_pll_data.pll_m,
+	       cmd_pll_data.pll_d, cmd_pll_data.pll_od);
+	init_pll(&cmd_pll_data);
+
+	return 0;
+
+pll_cmd_usage:
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	pllset,	5,	0,	do_pll_cmd,
+	"set pll multiplier and pre divider",
+	"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
+);
+
+int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int clk;
+	unsigned int freq;
+
+	if (argc != 2)
+		goto getclk_cmd_usage;
+
+	clk = simple_strtoul(argv[1], NULL, 10);
+
+	freq = clk_get_rate(clk);
+	printf("clock index [%d] - frequency %u\n", clk, freq);
+	return 0;
+
+getclk_cmd_usage:
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	getclk,	2,	0,	do_getclk_cmd,
+	"get clock rate",
+	"<clk index>\n"
+	"See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
+);
+
+int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int	psc_module;
+	int	res;
+
+	if (argc != 3)
+		goto psc_cmd_usage;
+
+	psc_module = simple_strtoul(argv[1], NULL, 10);
+	if (strcmp(argv[2], "en") == 0) {
+		res = psc_enable_module(psc_module);
+		printf("psc_enable_module(%d) - %s\n", psc_module,
+		       (res) ? "ERROR" : "OK");
+		return 0;
+	}
+
+	if (strcmp(argv[2], "di") == 0) {
+		res = psc_disable_module(psc_module);
+		printf("psc_disable_module(%d) - %s\n", psc_module,
+		       (res) ? "ERROR" : "OK");
+		return 0;
+	}
+
+	if (strcmp(argv[2], "domain") == 0) {
+		res = psc_disable_domain(psc_module);
+		printf("psc_disable_domain(%d) - %s\n", psc_module,
+		       (res) ? "ERROR" : "OK");
+		return 0;
+	}
+
+psc_cmd_usage:
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+	psc,	3,	0,	do_psc_cmd,
+	"<enable/disable psc module os disable domain>",
+	"<mod/domain index> <en|di|domain>\n"
+	"See the hardware.h for Power and Sleep Controller (PSC) Domains\n"
+);
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/cmd_mon.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/cmd_mon.c
new file mode 100644
index 000000000..f9f58a37d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/cmd_mon.c
@@ -0,0 +1,131 @@
+/*
+ * K2HK: secure kernel command file
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+asm(".arch_extension sec\n\t");
+
+static int mon_install(u32 addr, u32 dpsc, u32 freq)
+{
+	int result;
+
+	__asm__ __volatile__ (
+		"stmfd r13!, {lr}\n"
+		"mov r0, %1\n"
+		"mov r1, %2\n"
+		"mov r2, %3\n"
+		"blx r0\n"
+		"ldmfd r13!, {lr}\n"
+		: "=&r" (result)
+		: "r" (addr), "r" (dpsc), "r" (freq)
+		: "cc", "r0", "r1", "r2", "memory");
+	return result;
+}
+
+static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[])
+{
+	u32 addr, dpsc_base = 0x1E80000, freq;
+	int     rcode = 0;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	freq = clk_get_rate(sys_clk0_6_clk);
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+	rcode = mon_install(addr, dpsc_base, freq);
+	printf("## installed monitor, freq [%d], status %d\n",
+	       freq, rcode);
+
+	return 0;
+}
+
+U_BOOT_CMD(mon_install, 2, 0, do_mon_install,
+	   "Install boot kernel at 'addr'",
+	   ""
+);
+
+static void core_spin(void)
+{
+	while (1)
+		; /* forever */;
+}
+
+int mon_power_on(int core_id, void *ep)
+{
+	int result;
+
+	asm volatile (
+		"stmfd  r13!, {lr}\n"
+		"mov r1, %1\n"
+		"mov r2, %2\n"
+		"mov r0, #0\n"
+		"smc	#0\n"
+		"ldmfd  r13!, {lr}\n"
+		: "=&r" (result)
+		: "r" (core_id), "r" (ep)
+		: "cc", "r0", "r1", "r2", "memory");
+	return  result;
+}
+
+int mon_power_off(int core_id)
+{
+	int result;
+
+	asm volatile (
+		"stmfd  r13!, {lr}\n"
+		"mov r1, %1\n"
+		"mov r0, #1\n"
+		"smc	#1\n"
+		"ldmfd  r13!, {lr}\n"
+		: "=&r" (result)
+		: "r" (core_id)
+		: "cc", "r0", "r1", "memory");
+	return  result;
+}
+
+int do_mon_power(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
+{
+	int     rcode = 0, core_id, on;
+	void (*fn)(void);
+
+	fn = core_spin;
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	core_id = simple_strtoul(argv[1], NULL, 16);
+	on = simple_strtoul(argv[2], NULL, 16);
+
+	if (on)
+		rcode = mon_power_on(core_id, fn);
+	else
+		rcode = mon_power_off(core_id);
+
+	if (on) {
+		if (!rcode)
+			printf("core %d powered on successfully\n", core_id);
+		else
+			printf("core %d power on failure\n", core_id);
+	} else {
+		printf("core %d powered off successfully\n", core_id);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(mon_power, 3, 0, do_mon_power,
+	   "Power On/Off secondary core",
+	   "mon_power <coreid> <oper>\n"
+	   "- coreid (1-3) and oper (1 - ON, 0 - OFF)\n"
+	   ""
+);
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/ddr3.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/ddr3.c
new file mode 100644
index 000000000..4875db76a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -0,0 +1,69 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
+{
+	unsigned int tmp;
+
+	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
+		 & 0x00000001) != 0x00000001)
+		;
+
+	__raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
+
+	tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
+	tmp &= ~(phy_cfg->pgcr1_mask);
+	tmp |= phy_cfg->pgcr1_val;
+	__raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
+
+	__raw_writel(phy_cfg->ptr0,   base + KS2_DDRPHY_PTR0_OFFSET);
+	__raw_writel(phy_cfg->ptr1,   base + KS2_DDRPHY_PTR1_OFFSET);
+	__raw_writel(phy_cfg->ptr3,  base + KS2_DDRPHY_PTR3_OFFSET);
+	__raw_writel(phy_cfg->ptr4,  base + KS2_DDRPHY_PTR4_OFFSET);
+
+	tmp =  __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
+	tmp &= ~(phy_cfg->dcr_mask);
+	tmp |= phy_cfg->dcr_val;
+	__raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
+
+	__raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
+	__raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
+	__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
+	__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
+	__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
+	__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
+	__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
+	__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
+
+	__raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
+	__raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
+	__raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
+
+	__raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
+	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
+		;
+
+	__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
+	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
+		;
+}
+
+void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
+{
+	__raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
+	__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
+	__raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
+	__raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
+	__raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
+	__raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
+	__raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/init.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/init.c
new file mode 100644
index 000000000..044015aed
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/init.c
@@ -0,0 +1,56 @@
+/*
+ * Keystone2: Architecture initialization
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+
+void chip_configuration_unlock(void)
+{
+	__raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
+	__raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+}
+
+int arch_cpu_init(void)
+{
+	chip_configuration_unlock();
+	icache_enable();
+
+#ifdef CONFIG_SOC_K2HK
+	share_all_segments(8);
+	share_all_segments(9);
+	share_all_segments(10); /* QM PDSP */
+	share_all_segments(11); /* PCIE */
+#endif
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
+	u32 tmp;
+
+	tmp = *rstctrl & KS2_RSTCTRL_MASK;
+	*rstctrl = tmp | KS2_RSTCTRL_KEY;
+
+	*rstctrl &= KS2_RSTCTRL_SWRST;
+
+	for (;;)
+		;
+}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+#endif
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/keystone_nav.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/keystone_nav.c
new file mode 100644
index 000000000..39d6f995f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/keystone_nav.c
@@ -0,0 +1,376 @@
+/*
+ * Multicore Navigator driver for TI Keystone 2 devices.
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/keystone_nav.h>
+
+static int soc_type =
+#ifdef CONFIG_SOC_K2HK
+	k2hk;
+#endif
+
+struct qm_config k2hk_qm_memmap = {
+	.stat_cfg	= 0x02a40000,
+	.queue		= (struct qm_reg_queue *)0x02a80000,
+	.mngr_vbusm	= 0x23a80000,
+	.i_lram		= 0x00100000,
+	.proxy		= (struct qm_reg_queue *)0x02ac0000,
+	.status_ram	= 0x02a06000,
+	.mngr_cfg	= (struct qm_cfg_reg *)0x02a02000,
+	.intd_cfg	= 0x02a0c000,
+	.desc_mem	= (struct descr_mem_setup_reg *)0x02a03000,
+	.region_num	= 64,
+	.pdsp_cmd	= 0x02a20000,
+	.pdsp_ctl	= 0x02a0f000,
+	.pdsp_iram	= 0x02a10000,
+	.qpool_num	= 4000,
+};
+
+/*
+ * We are going to use only one type of descriptors - host packet
+ * descriptors. We staticaly allocate memory for them here
+ */
+struct qm_host_desc desc_pool[HDESC_NUM] __aligned(sizeof(struct qm_host_desc));
+
+static struct qm_config *qm_cfg;
+
+inline int num_of_desc_to_reg(int num_descr)
+{
+	int j, num;
+
+	for (j = 0, num = 32; j < 15; j++, num *= 2) {
+		if (num_descr <= num)
+			return j;
+	}
+
+	return 15;
+}
+
+static int _qm_init(struct qm_config *cfg)
+{
+	u32	j;
+
+	if (cfg == NULL)
+		return QM_ERR;
+
+	qm_cfg = cfg;
+
+	qm_cfg->mngr_cfg->link_ram_base0	= qm_cfg->i_lram;
+	qm_cfg->mngr_cfg->link_ram_size0	= HDESC_NUM * 8;
+	qm_cfg->mngr_cfg->link_ram_base1	= 0;
+	qm_cfg->mngr_cfg->link_ram_size1	= 0;
+	qm_cfg->mngr_cfg->link_ram_base2	= 0;
+
+	qm_cfg->desc_mem[0].base_addr = (u32)desc_pool;
+	qm_cfg->desc_mem[0].start_idx = 0;
+	qm_cfg->desc_mem[0].desc_reg_size =
+		(((sizeof(struct qm_host_desc) >> 4) - 1) << 16) |
+		num_of_desc_to_reg(HDESC_NUM);
+
+	memset(desc_pool, 0, sizeof(desc_pool));
+	for (j = 0; j < HDESC_NUM; j++)
+		qm_push(&desc_pool[j], qm_cfg->qpool_num);
+
+	return QM_OK;
+}
+
+int qm_init(void)
+{
+	switch (soc_type) {
+	case k2hk:
+		return _qm_init(&k2hk_qm_memmap);
+	}
+
+	return QM_ERR;
+}
+
+void qm_close(void)
+{
+	u32	j;
+
+	if (qm_cfg == NULL)
+		return;
+
+	queue_close(qm_cfg->qpool_num);
+
+	qm_cfg->mngr_cfg->link_ram_base0	= 0;
+	qm_cfg->mngr_cfg->link_ram_size0	= 0;
+	qm_cfg->mngr_cfg->link_ram_base1	= 0;
+	qm_cfg->mngr_cfg->link_ram_size1	= 0;
+	qm_cfg->mngr_cfg->link_ram_base2	= 0;
+
+	for (j = 0; j < qm_cfg->region_num; j++) {
+		qm_cfg->desc_mem[j].base_addr = 0;
+		qm_cfg->desc_mem[j].start_idx = 0;
+		qm_cfg->desc_mem[j].desc_reg_size = 0;
+	}
+
+	qm_cfg = NULL;
+}
+
+void qm_push(struct qm_host_desc *hd, u32 qnum)
+{
+	u32 regd;
+
+	if (!qm_cfg)
+		return;
+
+	cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
+	regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
+	writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
+}
+
+void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
+		    void *buff_ptr, u32 buff_len)
+{
+	hd->orig_buff_len = buff_len;
+	hd->buff_len = buff_len;
+	hd->orig_buff_ptr = (u32)buff_ptr;
+	hd->buff_ptr = (u32)buff_ptr;
+	qm_push(hd, qnum);
+}
+
+struct qm_host_desc *qm_pop(u32 qnum)
+{
+	u32 uhd;
+
+	if (!qm_cfg)
+		return NULL;
+
+	uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
+	if (uhd)
+		cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
+
+	return (struct qm_host_desc *)uhd;
+}
+
+struct qm_host_desc *qm_pop_from_free_pool(void)
+{
+	if (!qm_cfg)
+		return NULL;
+
+	return qm_pop(qm_cfg->qpool_num);
+}
+
+void queue_close(u32 qnum)
+{
+	struct qm_host_desc *hd;
+
+	while ((hd = qm_pop(qnum)))
+		;
+}
+
+/*
+ * DMA API
+ */
+
+struct pktdma_cfg k2hk_netcp_pktdma = {
+	.global		= (struct global_ctl_regs *)0x02004000,
+	.tx_ch		= (struct tx_chan_regs *)0x02004400,
+	.tx_ch_num	= 9,
+	.rx_ch		= (struct rx_chan_regs *)0x02004800,
+	.rx_ch_num	= 26,
+	.tx_sched	= (u32 *)0x02004c00,
+	.rx_flows	= (struct rx_flow_regs *)0x02005000,
+	.rx_flow_num	= 32,
+	.rx_free_q	= 4001,
+	.rx_rcv_q	= 4002,
+	.tx_snd_q	= 648,
+};
+
+struct pktdma_cfg *netcp;
+
+static int netcp_rx_disable(void)
+{
+	u32 j, v, k;
+
+	for (j = 0; j < netcp->rx_ch_num; j++) {
+		v = readl(&netcp->rx_ch[j].cfg_a);
+		if (!(v & CPDMA_CHAN_A_ENABLE))
+			continue;
+
+		writel(v | CPDMA_CHAN_A_TDOWN, &netcp->rx_ch[j].cfg_a);
+		for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
+			udelay(100);
+			v = readl(&netcp->rx_ch[j].cfg_a);
+			if (!(v & CPDMA_CHAN_A_ENABLE))
+				continue;
+		}
+		/* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
+	}
+
+	/* Clear all of the flow registers */
+	for (j = 0; j < netcp->rx_flow_num; j++) {
+		writel(0, &netcp->rx_flows[j].control);
+		writel(0, &netcp->rx_flows[j].tags);
+		writel(0, &netcp->rx_flows[j].tag_sel);
+		writel(0, &netcp->rx_flows[j].fdq_sel[0]);
+		writel(0, &netcp->rx_flows[j].fdq_sel[1]);
+		writel(0, &netcp->rx_flows[j].thresh[0]);
+		writel(0, &netcp->rx_flows[j].thresh[1]);
+		writel(0, &netcp->rx_flows[j].thresh[2]);
+	}
+
+	return QM_OK;
+}
+
+static int netcp_tx_disable(void)
+{
+	u32 j, v, k;
+
+	for (j = 0; j < netcp->tx_ch_num; j++) {
+		v = readl(&netcp->tx_ch[j].cfg_a);
+		if (!(v & CPDMA_CHAN_A_ENABLE))
+			continue;
+
+		writel(v | CPDMA_CHAN_A_TDOWN, &netcp->tx_ch[j].cfg_a);
+		for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
+			udelay(100);
+			v = readl(&netcp->tx_ch[j].cfg_a);
+			if (!(v & CPDMA_CHAN_A_ENABLE))
+				continue;
+		}
+		/* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
+	}
+
+	return QM_OK;
+}
+
+static int _netcp_init(struct pktdma_cfg *netcp_cfg,
+		       struct rx_buff_desc *rx_buffers)
+{
+	u32 j, v;
+	struct qm_host_desc *hd;
+	u8 *rx_ptr;
+
+	if (netcp_cfg == NULL || rx_buffers == NULL ||
+	    rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
+		return QM_ERR;
+
+	netcp = netcp_cfg;
+	netcp->rx_flow = rx_buffers->rx_flow;
+
+	/* init rx queue */
+	rx_ptr = rx_buffers->buff_ptr;
+
+	for (j = 0; j < rx_buffers->num_buffs; j++) {
+		hd = qm_pop(qm_cfg->qpool_num);
+		if (hd == NULL)
+			return QM_ERR;
+
+		qm_buff_push(hd, netcp->rx_free_q,
+			     rx_ptr, rx_buffers->buff_len);
+
+		rx_ptr += rx_buffers->buff_len;
+	}
+
+	netcp_rx_disable();
+
+	/* configure rx channels */
+	v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, netcp->rx_rcv_q);
+	writel(v, &netcp->rx_flows[netcp->rx_flow].control);
+	writel(0, &netcp->rx_flows[netcp->rx_flow].tags);
+	writel(0, &netcp->rx_flows[netcp->rx_flow].tag_sel);
+
+	v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, netcp->rx_free_q, 0,
+					 netcp->rx_free_q);
+
+	writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[0]);
+	writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[1]);
+	writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[0]);
+	writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[1]);
+	writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[2]);
+
+	for (j = 0; j < netcp->rx_ch_num; j++)
+		writel(CPDMA_CHAN_A_ENABLE, &netcp->rx_ch[j].cfg_a);
+
+	/* configure tx channels */
+	/* Disable loopback in the tx direction */
+	writel(0, &netcp->global->emulation_control);
+
+/* TODO: make it dependend on a soc type variable */
+#ifdef CONFIG_SOC_K2HK
+	/* Set QM base address, only for K2x devices */
+	writel(0x23a80000, &netcp->global->qm_base_addr[0]);
+#endif
+
+	/* Enable all channels. The current state isn't important */
+	for (j = 0; j < netcp->tx_ch_num; j++)  {
+		writel(0, &netcp->tx_ch[j].cfg_b);
+		writel(CPDMA_CHAN_A_ENABLE, &netcp->tx_ch[j].cfg_a);
+	}
+
+	return QM_OK;
+}
+
+int netcp_init(struct rx_buff_desc *rx_buffers)
+{
+	switch (soc_type) {
+	case k2hk:
+		_netcp_init(&k2hk_netcp_pktdma, rx_buffers);
+		return QM_OK;
+	}
+	return QM_ERR;
+}
+
+int netcp_close(void)
+{
+	if (!netcp)
+		return QM_ERR;
+
+	netcp_tx_disable();
+	netcp_rx_disable();
+
+	queue_close(netcp->rx_free_q);
+	queue_close(netcp->rx_rcv_q);
+	queue_close(netcp->tx_snd_q);
+
+	return QM_OK;
+}
+
+int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
+{
+	struct qm_host_desc *hd;
+
+	hd = qm_pop(qm_cfg->qpool_num);
+	if (hd == NULL)
+		return QM_ERR;
+
+	hd->desc_info	= num_bytes;
+	hd->swinfo[2]	= swinfo2;
+	hd->packet_info = qm_cfg->qpool_num;
+
+	qm_buff_push(hd, netcp->tx_snd_q, pkt, num_bytes);
+
+	return QM_OK;
+}
+
+void *netcp_recv(u32 **pkt, int *num_bytes)
+{
+	struct qm_host_desc *hd;
+
+	hd = qm_pop(netcp->rx_rcv_q);
+	if (!hd)
+		return NULL;
+
+	*pkt = (u32 *)hd->buff_ptr;
+	*num_bytes = hd->desc_info & 0x3fffff;
+
+	return hd;
+}
+
+void netcp_release_rxhd(void *hd)
+{
+	struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
+
+	_hd->buff_len = _hd->orig_buff_len;
+	_hd->buff_ptr = _hd->orig_buff_ptr;
+
+	qm_push(_hd, netcp->rx_free_q);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/msmc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/msmc.c
new file mode 100644
index 000000000..f3f1621d2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/msmc.c
@@ -0,0 +1,68 @@
+/*
+ * MSMC controller utilities
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+struct mpax {
+	u32	mpaxl;
+	u32	mpaxh;
+};
+
+struct msms_regs {
+	u32	pid;
+	u32	_res_04;
+	u32	smcerrar;
+	u32	smcerrxr;
+	u32	smedcc;
+	u32	smcea;
+	u32	smsecc;
+	u32	smpfar;
+	u32	smpfxr;
+	u32	smpfr;
+	u32	smpfcr;
+	u32	_res_2c;
+	u32	sbndc[8];
+	u32	sbndm;
+	u32	sbnde;
+	u32	_res_58;
+	u32	cfglck;
+	u32	cfgulck;
+	u32	cfglckstat;
+	u32	sms_mpax_lck;
+	u32	sms_mpax_ulck;
+	u32	sms_mpax_lckstat;
+	u32	ses_mpax_lck;
+	u32	ses_mpax_ulck;
+	u32	ses_mpax_lckstat;
+	u32	smestat;
+	u32	smirstat;
+	u32	smirc;
+	u32	smiestat;
+	u32	smiec;
+	u32	_res_94_c0[12];
+	u32	smncerrar;
+	u32	smncerrxr;
+	u32	smncea;
+	u32	_res_d0_1fc[76];
+	struct mpax sms[16][8];
+	struct mpax ses[16][8];
+};
+
+
+void share_all_segments(int priv_id)
+{
+	struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
+	int j;
+
+	for (j = 0; j < 8; j++) {
+		msmc->sms[priv_id][j].mpaxh &= 0xffffff7ful;
+		msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/psc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/psc.c
new file mode 100644
index 000000000..c844dc84d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/psc.c
@@ -0,0 +1,237 @@
+/*
+ * Keystone: PSC configuration module
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/psc_defs.h>
+
+#define DEVICE_REG32_R(addr)			__raw_readl((u32 *)(addr))
+#define DEVICE_REG32_W(addr, val)		__raw_writel(val, (u32 *)(addr))
+
+#ifdef CONFIG_SOC_K2HK
+#define DEVICE_PSC_BASE				K2HK_PSC_BASE
+#endif
+
+int psc_delay(void)
+{
+	udelay(10);
+	return 10;
+}
+
+/*
+ * FUNCTION PURPOSE: Wait for end of transitional state
+ *
+ * DESCRIPTION: Polls pstat for the selected domain and waits for transitions
+ *              to be complete.
+ *
+ *              Since this is boot loader code it is *ASSUMED* that interrupts
+ *              are disabled and no other core is mucking around with the psc
+ *              at the same time.
+ *
+ *              Returns 0 when the domain is free. Returns -1 if a timeout
+ *              occurred waiting for the completion.
+ */
+int psc_wait(u32 domain_num)
+{
+	u32 retry;
+	u32 ptstat;
+
+	/*
+	 * Do nothing if the power domain is in transition. This should never
+	 * happen since the boot code is the only software accesses psc.
+	 * It's still remotely possible that the hardware state machines
+	 * initiate transitions.
+	 * Don't trap if the domain (or a module in this domain) is
+	 * stuck in transition.
+	 */
+	retry = 0;
+
+	do {
+		ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
+		ptstat = ptstat & (1 << domain_num);
+	} while ((ptstat != 0) && ((retry += psc_delay()) <
+		 PSC_PTSTAT_TIMEOUT_LIMIT));
+
+	if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT)
+		return -1;
+
+	return 0;
+}
+
+u32 psc_get_domain_num(u32 mod_num)
+{
+	u32 domain_num;
+
+	/* Get the power domain associated with the module number */
+	domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
+				    PSC_REG_MDCFG(mod_num));
+	domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
+
+	return domain_num;
+}
+
+/*
+ * FUNCTION PURPOSE: Power up/down a module
+ *
+ * DESCRIPTION: Powers up/down the requested module and the associated power
+ *		domain if required. No action is taken it the module is
+ *		already powered up/down.
+ *
+ *              This only controls modules. The domain in which the module
+ *              resides will be left in the power on state. Multiple modules
+ *              can exist in a power domain, so powering down the domain based
+ *              on a single module is not done.
+ *
+ *              Returns 0 on success, -1 if the module can't be powered up, or
+ *              if there is a timeout waiting for the transition.
+ */
+int psc_set_state(u32 mod_num, u32 state)
+{
+	u32 domain_num;
+	u32 pdctl;
+	u32 mdctl;
+	u32 ptcmd;
+	u32 reset_iso;
+	u32 v;
+
+	/*
+	 * Get the power domain associated with the module number, and reset
+	 * isolation functionality
+	 */
+	v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+	domain_num = PSC_REG_MDCFG_GET_PD(v);
+	reset_iso  = PSC_REG_MDCFG_GET_RESET_ISO(v);
+
+	/* Wait for the status of the domain/module to be non-transitional */
+	if (psc_wait(domain_num) != 0)
+		return -1;
+
+	/*
+	 * Perform configuration even if the current status matches the
+	 * existing state
+	 *
+	 * Set the next state of the power domain to on. It's OK if the domain
+	 * is always on. This code will not ever power down a domain, so no
+	 * change is made if the new state is power down.
+	 */
+	if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
+		pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
+				       PSC_REG_PDCTL(domain_num));
+		pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
+					       PSC_REG_VAL_PDCTL_NEXT_ON);
+		DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
+			       pdctl);
+	}
+
+	/* Set the next state for the module to enabled/disabled */
+	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
+	mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
+	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+
+	/* Trigger the enable */
+	ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+	ptcmd |= (u32)(1<<domain_num);
+	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+
+	/* Wait on the complete */
+	return psc_wait(domain_num);
+}
+
+/*
+ * FUNCTION PURPOSE: Power up a module
+ *
+ * DESCRIPTION: Powers up the requested module and the associated power domain
+ *              if required. No action is taken it the module is already
+ *              powered up.
+ *
+ *              Returns 0 on success, -1 if the module can't be powered up, or
+ *              if there is a timeout waiting for the transition.
+ */
+int psc_enable_module(u32 mod_num)
+{
+	u32 mdctl;
+
+	/* Set the bit to apply reset */
+	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
+		return 0;
+
+	return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
+}
+
+/*
+ * FUNCTION PURPOSE: Power down a module
+ *
+ * DESCRIPTION: Powers down the requested module.
+ *
+ *              Returns 0 on success, -1 on failure or timeout.
+ */
+int psc_disable_module(u32 mod_num)
+{
+	u32 mdctl;
+
+	/* Set the bit to apply reset */
+	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	if ((mdctl & 0x3f) == 0)
+		return 0;
+	mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
+	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+
+	return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
+}
+
+/*
+ * FUNCTION PURPOSE: Set the reset isolation bit in mdctl
+ *
+ * DESCRIPTION: The reset isolation enable bit is set. The state of the module
+ *              is not changed. Returns 0 if the module config showed that
+ *              reset isolation is supported. Returns 1 otherwise. This is not
+ *              an error, but setting the bit in mdctl has no effect.
+ */
+int psc_set_reset_iso(u32 mod_num)
+{
+	u32 v;
+	u32 mdctl;
+
+	/* Set the reset isolation bit */
+	mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
+	mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
+	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
+
+	v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
+	if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
+		return 0;
+
+	return 1;
+}
+
+/*
+ * FUNCTION PURPOSE: Disable a power domain
+ *
+ * DESCRIPTION: The power domain is disabled
+ */
+int psc_disable_domain(u32 domain_num)
+{
+	u32 pdctl;
+	u32 ptcmd;
+
+	pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
+	pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
+	pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
+	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
+
+	ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
+	ptcmd |= (u32)(1 << domain_num);
+	DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
+
+	return psc_wait(domain_num);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/spl.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/spl.c
new file mode 100644
index 000000000..e07b64db9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/keystone/spl.c
@@ -0,0 +1,45 @@
+/*
+ * common spl init code
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <spl.h>
+#include <spi_flash.h>
+
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pll_init_data spl_pll_config[] = {
+	CORE_PLL_799,
+	TETRIS_PLL_500,
+};
+
+void spl_init_keystone_plls(void)
+{
+	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+
+void spl_board_init(void)
+{
+	spl_init_keystone_plls();
+	preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+	return BOOT_DEVICE_SPI;
+#else
+	puts("Unknown boot device\n");
+	hang();
+#endif
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/Makefile
new file mode 100644
index 000000000..da225cb4f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= s_init.o
+obj-y	+= hwinit-common.o
+obj-y	+= clk-stubs.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/clk-stubs.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/clk-stubs.c
new file mode 100644
index 000000000..338e0e496
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/clk-stubs.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+
+/*
+ * These weak functions are available to kona architectures that don't
+ * require clock enables from the driver code.
+ */
+int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+	return 0;
+}
+
+int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/hwinit-common.c
new file mode 100644
index 000000000..2b3a84051
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/hwinit-common.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/s_init.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/s_init.c
new file mode 100644
index 000000000..6066a73c5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/kona-common/s_init.c
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Early system init. Currently empty.
+ */
+void s_init(void)
+{
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/lowlevel_init.S
new file mode 100644
index 000000000..f1aea05c9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/lowlevel_init.S
@@ -0,0 +1,41 @@
+/*
+ * A lowlevel_init function that sets up the stack to call a C function to
+ * perform further init.
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Aneesh V	<aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	/*
+	 * Setup a temporary stack
+	 */
+	ldr	sp, =CONFIG_SYS_INIT_SP_ADDR
+	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
+#ifdef CONFIG_SPL_BUILD
+	ldr	r9, =gdata
+#else
+	sub	sp, sp, #GD_SIZE
+	bic	sp, sp, #7
+	mov	r9, sp
+#endif
+	/*
+	 * Save the old lr(passed in ip) and the current lr to stack
+	 */
+	push	{ip, lr}
+
+	/*
+	 * go setup pll, mux, memory
+	 */
+	bl	s_init
+	pop	{ip, pc}
+ENDPROC(lowlevel_init)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/Makefile
new file mode 100644
index 000000000..d021842f6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := soc.o clock.o
+obj-y += lowlevel_init.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/clock.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/clock.c
new file mode 100644
index 000000000..bf52f0d19
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/clock.c
@@ -0,0 +1,949 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <div64.h>
+#include <asm/arch/sys_proto.h>
+
+enum pll_clocks {
+	PLL1_CLOCK = 0,
+	PLL2_CLOCK,
+	PLL3_CLOCK,
+#ifdef CONFIG_MX53
+	PLL4_CLOCK,
+#endif
+	PLL_CLOCKS,
+};
+
+struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
+	[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
+	[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
+	[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
+#ifdef	CONFIG_MX53
+	[PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
+#endif
+};
+
+#define AHB_CLK_ROOT    133333333
+#define SZ_DEC_1M       1000000
+#define PLL_PD_MAX      16      /* Actual pd+1 */
+#define PLL_MFI_MAX     15
+#define PLL_MFI_MIN     5
+#define ARM_DIV_MAX     8
+#define IPG_DIV_MAX     4
+#define AHB_DIV_MAX     8
+#define EMI_DIV_MAX     8
+#define NFC_DIV_MAX     8
+
+#define MX5_CBCMR	0x00015154
+#define MX5_CBCDR	0x02888945
+
+struct fixed_pll_mfd {
+	u32 ref_clk_hz;
+	u32 mfd;
+};
+
+const struct fixed_pll_mfd fixed_mfd[] = {
+	{MXC_HCLK, 24 * 16},
+};
+
+struct pll_param {
+	u32 pd;
+	u32 mfi;
+	u32 mfn;
+	u32 mfd;
+};
+
+#define PLL_FREQ_MAX(ref_clk)  (4 * (ref_clk) * PLL_MFI_MAX)
+#define PLL_FREQ_MIN(ref_clk) \
+		((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define MAX_DDR_CLK     420000000
+#define NFC_CLK_MAX     34000000
+
+struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+void set_usboh3_clk(void)
+{
+	clrsetbits_le32(&mxc_ccm->cscmr1,
+			MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
+			MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
+	clrsetbits_le32(&mxc_ccm->cscdr1,
+			MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
+			MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
+			MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
+			MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
+}
+
+void enable_usboh3_clk(bool enable)
+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR2,
+			MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR2_USBOH3_60M(cg));
+}
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+	u32 mask;
+
+#if defined(CONFIG_MX51)
+	if (i2c_num > 1)
+#elif defined(CONFIG_MX53)
+	if (i2c_num > 2)
+#endif
+		return -EINVAL;
+	mask = MXC_CCM_CCGR_CG_MASK <<
+			(MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
+	if (enable)
+		setbits_le32(&mxc_ccm->CCGR1, mask);
+	else
+		clrbits_le32(&mxc_ccm->CCGR1, mask);
+	return 0;
+}
+#endif
+
+void set_usb_phy_clk(void)
+{
+	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
+}
+
+#if defined(CONFIG_MX51)
+void enable_usb_phy1_clk(bool enable)
+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR2,
+			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR2_USB_PHY(cg));
+}
+
+void enable_usb_phy2_clk(bool enable)
+{
+	/* i.MX51 has a single USB PHY clock, so do nothing here. */
+}
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(bool enable)
+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR4,
+			MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR4_USB_PHY1(cg));
+}
+
+void enable_usb_phy2_clk(bool enable)
+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR4,
+			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR4_USB_PHY2(cg));
+}
+#endif
+
+/*
+ * Calculate the frequency of PLLn.
+ */
+static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
+{
+	uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
+	uint64_t refclk, temp;
+	int32_t mfn_abs;
+
+	ctrl = readl(&pll->ctrl);
+
+	if (ctrl & MXC_DPLLC_CTL_HFSM) {
+		mfn = readl(&pll->hfs_mfn);
+		mfd = readl(&pll->hfs_mfd);
+		op = readl(&pll->hfs_op);
+	} else {
+		mfn = readl(&pll->mfn);
+		mfd = readl(&pll->mfd);
+		op = readl(&pll->op);
+	}
+
+	mfd &= MXC_DPLLC_MFD_MFD_MASK;
+	mfn &= MXC_DPLLC_MFN_MFN_MASK;
+	pdf = op & MXC_DPLLC_OP_PDF_MASK;
+	mfi = MXC_DPLLC_OP_MFI_RD(op);
+
+	/* 21.2.3 */
+	if (mfi < 5)
+		mfi = 5;
+
+	/* Sign extend */
+	if (mfn >= 0x04000000) {
+		mfn |= 0xfc000000;
+		mfn_abs = -mfn;
+	} else
+		mfn_abs = mfn;
+
+	refclk = infreq * 2;
+	if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
+		refclk *= 2;
+
+	do_div(refclk, pdf + 1);
+	temp = refclk * mfn_abs;
+	do_div(temp, mfd + 1);
+	ret = refclk * mfi;
+
+	if ((int)mfn < 0)
+		ret -= temp;
+	else
+		ret += temp;
+
+	return ret;
+}
+
+#ifdef CONFIG_MX51
+/*
+ * This function returns the Frequency Pre-Multiplier clock.
+ */
+static u32 get_fpm(void)
+{
+	u32 mult;
+	u32 ccr = readl(&mxc_ccm->ccr);
+
+	if (ccr & MXC_CCM_CCR_FPM_MULT)
+		mult = 1024;
+	else
+		mult = 512;
+
+	return MXC_CLK32 * mult;
+}
+#endif
+
+/*
+ * This function returns the low power audio clock.
+ */
+static u32 get_lp_apm(void)
+{
+	u32 ret_val = 0;
+	u32 ccsr = readl(&mxc_ccm->ccsr);
+
+	if (ccsr & MXC_CCM_CCSR_LP_APM)
+#if defined(CONFIG_MX51)
+		ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+#endif
+	else
+		ret_val = MXC_HCLK;
+
+	return ret_val;
+}
+
+/*
+ * Get mcu main rate
+ */
+u32 get_mcu_main_clk(void)
+{
+	u32 reg, freq;
+
+	reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
+	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+	return freq / (reg + 1);
+}
+
+/*
+ * Get the rate of peripheral's root clock.
+ */
+u32 get_periph_clk(void)
+{
+	u32 reg;
+
+	reg = readl(&mxc_ccm->cbcdr);
+	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
+		return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
+	reg = readl(&mxc_ccm->cbcmr);
+	switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
+	case 0:
+		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+	case 1:
+		return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+	case 2:
+		return get_lp_apm();
+	default:
+		return 0;
+	}
+	/* NOTREACHED */
+}
+
+/*
+ * Get the rate of ipg clock.
+ */
+static u32 get_ipg_clk(void)
+{
+	uint32_t freq, reg, div;
+
+	freq = get_ahb_clk();
+
+	reg = readl(&mxc_ccm->cbcdr);
+	div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
+
+	return freq / div;
+}
+
+/*
+ * Get the rate of ipg_per clock.
+ */
+static u32 get_ipg_per_clk(void)
+{
+	u32 freq, pred1, pred2, podf;
+
+	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+		return get_ipg_clk();
+
+	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
+		freq = get_lp_apm();
+	else
+		freq = get_periph_clk();
+	podf = readl(&mxc_ccm->cbcdr);
+	pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
+	pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
+	podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
+	return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+}
+
+/* Get the output clock rate of a standard PLL MUX for peripherals. */
+static u32 get_standard_pll_sel_clk(u32 clk_sel)
+{
+	u32 freq = 0;
+
+	switch (clk_sel & 0x3) {
+	case 0:
+		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+		break;
+	case 1:
+		freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
+		break;
+	case 2:
+		freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+		break;
+	case 3:
+		freq = get_lp_apm();
+		break;
+	}
+
+	return freq;
+}
+
+/*
+ * Get the rate of uart clk.
+ */
+static u32 get_uart_clk(void)
+{
+	unsigned int clk_sel, freq, reg, pred, podf;
+
+	reg = readl(&mxc_ccm->cscmr1);
+	clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
+	freq = get_standard_pll_sel_clk(clk_sel);
+
+	reg = readl(&mxc_ccm->cscdr1);
+	pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
+	podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
+	freq /= (pred + 1) * (podf + 1);
+
+	return freq;
+}
+
+/*
+ * get cspi clock rate.
+ */
+static u32 imx_get_cspiclk(void)
+{
+	u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
+	u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+	u32 cscdr2 = readl(&mxc_ccm->cscdr2);
+
+	pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
+	pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
+	clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
+	freq = get_standard_pll_sel_clk(clk_sel);
+	ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
+	return ret_val;
+}
+
+/*
+ * get esdhc clock rate.
+ */
+static u32 get_esdhc_clk(u32 port)
+{
+	u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
+	u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+	u32 cscdr1 = readl(&mxc_ccm->cscdr1);
+
+	switch (port) {
+	case 0:
+		clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
+		pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
+		podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
+		break;
+	case 1:
+		clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
+		pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
+		podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
+		break;
+	case 2:
+		if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
+			return get_esdhc_clk(1);
+		else
+			return get_esdhc_clk(0);
+	case 3:
+		if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
+			return get_esdhc_clk(1);
+		else
+			return get_esdhc_clk(0);
+	default:
+		break;
+	}
+
+	freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
+	return freq;
+}
+
+static u32 get_axi_a_clk(void)
+{
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
+	u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
+
+	return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_axi_b_clk(void)
+{
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
+	u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
+
+	return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_emi_slow_clk(void)
+{
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
+	u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
+	u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
+
+	if (emi_clk_sel)
+		return  get_ahb_clk() / (pdf + 1);
+
+	return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_ddr_clk(void)
+{
+	u32 ret_val = 0;
+	u32 cbcmr = readl(&mxc_ccm->cbcmr);
+	u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
+#ifdef CONFIG_MX51
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
+	if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
+		u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
+
+		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+		ret_val /= ddr_clk_podf + 1;
+
+		return ret_val;
+	}
+#endif
+	switch (ddr_clk_sel) {
+	case 0:
+		ret_val = get_axi_a_clk();
+		break;
+	case 1:
+		ret_val = get_axi_b_clk();
+		break;
+	case 2:
+		ret_val = get_emi_slow_clk();
+		break;
+	case 3:
+		ret_val = get_ahb_clk();
+		break;
+	default:
+		break;
+	}
+
+	return ret_val;
+}
+
+/*
+ * The API of get mxc clocks.
+ */
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return get_mcu_main_clk();
+	case MXC_AHB_CLK:
+		return get_ahb_clk();
+	case MXC_IPG_CLK:
+		return get_ipg_clk();
+	case MXC_IPG_PERCLK:
+	case MXC_I2C_CLK:
+		return get_ipg_per_clk();
+	case MXC_UART_CLK:
+		return get_uart_clk();
+	case MXC_CSPI_CLK:
+		return imx_get_cspiclk();
+	case MXC_ESDHC_CLK:
+		return get_esdhc_clk(0);
+	case MXC_ESDHC2_CLK:
+		return get_esdhc_clk(1);
+	case MXC_ESDHC3_CLK:
+		return get_esdhc_clk(2);
+	case MXC_ESDHC4_CLK:
+		return get_esdhc_clk(3);
+	case MXC_FEC_CLK:
+		return get_ipg_clk();
+	case MXC_SATA_CLK:
+		return get_ahb_clk();
+	case MXC_DDR_CLK:
+		return get_ddr_clk();
+	default:
+		break;
+	}
+	return -EINVAL;
+}
+
+u32 imx_get_uartclk(void)
+{
+	return get_uart_clk();
+}
+
+u32 imx_get_fecclk(void)
+{
+	return get_ipg_clk();
+}
+
+static int gcd(int m, int n)
+{
+	int t;
+	while (m > 0) {
+		if (n > m) {
+			t = m;
+			m = n;
+			n = t;
+		} /* swap */
+		m -= n;
+	}
+	return n;
+}
+
+/*
+ * This is to calculate various parameters based on reference clock and
+ * targeted clock based on the equation:
+ *      t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
+ * This calculation is based on a fixed MFD value for simplicity.
+ */
+static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
+{
+	u64 pd, mfi = 1, mfn, mfd, t1;
+	u32 n_target = target;
+	u32 n_ref = ref, i;
+
+	/*
+	 * Make sure targeted freq is in the valid range.
+	 * Otherwise the following calculation might be wrong!!!
+	 */
+	if (n_target < PLL_FREQ_MIN(ref) ||
+		n_target > PLL_FREQ_MAX(ref)) {
+		printf("Targeted peripheral clock should be"
+			"within [%d - %d]\n",
+			PLL_FREQ_MIN(ref) / SZ_DEC_1M,
+			PLL_FREQ_MAX(ref) / SZ_DEC_1M);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
+		if (fixed_mfd[i].ref_clk_hz == ref) {
+			mfd = fixed_mfd[i].mfd;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(fixed_mfd))
+		return -EINVAL;
+
+	/* Use n_target and n_ref to avoid overflow */
+	for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+		t1 = n_target * pd;
+		do_div(t1, (4 * n_ref));
+		mfi = t1;
+		if (mfi > PLL_MFI_MAX)
+			return -EINVAL;
+		else if (mfi < 5)
+			continue;
+		break;
+	}
+	/*
+	 * Now got pd and mfi already
+	 *
+	 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
+	 */
+	t1 = n_target * pd;
+	do_div(t1, 4);
+	t1 -= n_ref * mfi;
+	t1 *= mfd;
+	do_div(t1, n_ref);
+	mfn = t1;
+	debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
+		ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
+	i = 1;
+	if (mfn != 0)
+		i = gcd(mfd, mfn);
+	pll->pd = (u32)pd;
+	pll->mfi = (u32)mfi;
+	do_div(mfn, i);
+	pll->mfn = (u32)mfn;
+	do_div(mfd, i);
+	pll->mfd = (u32)mfd;
+
+	return 0;
+}
+
+#define calc_div(tgt_clk, src_clk, limit) ({		\
+		u32 v = 0;				\
+		if (((src_clk) % (tgt_clk)) <= 100)	\
+			v = (src_clk) / (tgt_clk);	\
+		else					\
+			v = ((src_clk) / (tgt_clk)) + 1;\
+		if (v > limit)				\
+			v = limit;			\
+		(v - 1);				\
+	})
+
+#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
+	{	\
+		writel(0x1232, &pll->ctrl);		\
+		writel(0x2, &pll->config);		\
+		writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->op);			\
+		writel(fn, &(pll->mfn));		\
+		writel((fd) - 1, &pll->mfd);		\
+		writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->hfs_op);			\
+		writel(fn, &pll->hfs_mfn);		\
+		writel((fd) - 1, &pll->hfs_mfd);	\
+		writel(0x1232, &pll->ctrl);		\
+		while (!readl(&pll->ctrl) & 0x1)	\
+			;\
+	}
+
+static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
+{
+	u32 ccsr = readl(&mxc_ccm->ccsr);
+	struct mxc_pll_reg *pll = mxc_plls[index];
+
+	switch (index) {
+	case PLL1_CLOCK:
+		/* Switch ARM to PLL2 clock */
+		writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
+		break;
+	case PLL2_CLOCK:
+		/* Switch to pll2 bypass clock */
+		writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
+		break;
+	case PLL3_CLOCK:
+		/* Switch to pll3 bypass clock */
+		writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
+		break;
+#ifdef CONFIG_MX53
+	case PLL4_CLOCK:
+		/* Switch to pll4 bypass clock */
+		writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+				&mxc_ccm->ccsr);
+		break;
+#endif
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* Config CPU clock */
+static int config_core_clk(u32 ref, u32 freq)
+{
+	int ret = 0;
+	struct pll_param pll_param;
+
+	memset(&pll_param, 0, sizeof(struct pll_param));
+
+	/* The case that periph uses PLL1 is not considered here */
+	ret = calc_pll_params(ref, freq, &pll_param);
+	if (ret != 0) {
+		printf("Error:Can't find pll parameters: %d\n", ret);
+		return ret;
+	}
+
+	return config_pll_clk(PLL1_CLOCK, &pll_param);
+}
+
+static int config_nfc_clk(u32 nfc_clk)
+{
+	u32 parent_rate = get_emi_slow_clk();
+	u32 div;
+
+	if (nfc_clk == 0)
+		return -EINVAL;
+	div = parent_rate / nfc_clk;
+	if (div == 0)
+		div++;
+	if (parent_rate / div > NFC_CLK_MAX)
+		div++;
+	clrsetbits_le32(&mxc_ccm->cbcdr,
+			MXC_CCM_CBCDR_NFC_PODF_MASK,
+			MXC_CCM_CBCDR_NFC_PODF(div - 1));
+	while (readl(&mxc_ccm->cdhipr) != 0)
+		;
+	return 0;
+}
+
+void enable_nfc_clk(unsigned char enable)
+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR5,
+		MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
+		MXC_CCM_CCGR5_EMI_ENFC(cg));
+}
+
+#ifdef CONFIG_FSL_IIM
+void enable_efuse_prog_supply(bool enable)
+{
+	if (enable)
+		setbits_le32(&mxc_ccm->cgpr,
+			     MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+	else
+		clrbits_le32(&mxc_ccm->cgpr,
+			     MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+}
+#endif
+
+/* Config main_bus_clock for periphs */
+static int config_periph_clk(u32 ref, u32 freq)
+{
+	int ret = 0;
+	struct pll_param pll_param;
+
+	memset(&pll_param, 0, sizeof(struct pll_param));
+
+	if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+		ret = calc_pll_params(ref, freq, &pll_param);
+		if (ret != 0) {
+			printf("Error:Can't find pll parameters: %d\n",
+				ret);
+			return ret;
+		}
+		switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
+				readl(&mxc_ccm->cbcmr))) {
+		case 0:
+			return config_pll_clk(PLL1_CLOCK, &pll_param);
+			break;
+		case 1:
+			return config_pll_clk(PLL3_CLOCK, &pll_param);
+			break;
+		default:
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int config_ddr_clk(u32 emi_clk)
+{
+	u32 clk_src;
+	s32 shift = 0, clk_sel, div = 1;
+	u32 cbcmr = readl(&mxc_ccm->cbcmr);
+
+	if (emi_clk > MAX_DDR_CLK) {
+		printf("Warning:DDR clock should not exceed %d MHz\n",
+			MAX_DDR_CLK / SZ_DEC_1M);
+		emi_clk = MAX_DDR_CLK;
+	}
+
+	clk_src = get_periph_clk();
+	/* Find DDR clock input */
+	clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
+	switch (clk_sel) {
+	case 0:
+		shift = 16;
+		break;
+	case 1:
+		shift = 19;
+		break;
+	case 2:
+		shift = 22;
+		break;
+	case 3:
+		shift = 10;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if ((clk_src % emi_clk) < 10000000)
+		div = clk_src / emi_clk;
+	else
+		div = (clk_src / emi_clk) + 1;
+	if (div > 8)
+		div = 8;
+
+	clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
+	while (readl(&mxc_ccm->cdhipr) != 0)
+		;
+	writel(0x0, &mxc_ccm->ccdr);
+
+	return 0;
+}
+
+/*
+ * This function assumes the expected core clock has to be changed by
+ * modifying the PLL. This is NOT true always but for most of the times,
+ * it is. So it assumes the PLL output freq is the same as the expected
+ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+ * In the latter case, it will try to increase the presc value until
+ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * it sets the register based on these values along with the dividers.
+ * Note 1) There is no value checking for the passed-in divider values
+ *         so the caller has to make sure those values are sensible.
+ *      2) Also adjust the NFC divider such that the NFC clock doesn't
+ *         exceed NFC_CLK_MAX.
+ *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ *         177MHz for higher voltage, this function fixes the max to 133MHz.
+ *      4) This function should not have allowed diag_printf() calls since
+ *         the serial driver has been stoped. But leave then here to allow
+ *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
+ */
+int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
+{
+	freq *= SZ_DEC_1M;
+
+	switch (clk) {
+	case MXC_ARM_CLK:
+		if (config_core_clk(ref, freq))
+			return -EINVAL;
+		break;
+	case MXC_PERIPH_CLK:
+		if (config_periph_clk(ref, freq))
+			return -EINVAL;
+		break;
+	case MXC_DDR_CLK:
+		if (config_ddr_clk(freq))
+			return -EINVAL;
+		break;
+	case MXC_NFC_CLK:
+		if (config_nfc_clk(freq))
+			return -EINVAL;
+		break;
+	default:
+		printf("Warning:Unsupported or invalid clock type\n");
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_MX53
+/*
+ * The clock for the external interface can be set to use internal clock
+ * if fuse bank 4, row 3, bit 2 is set.
+ * This is an undocumented feature and it was confirmed by Freescale's support:
+ * Fuses (but not pins) may be used to configure SATA clocks.
+ * Particularly the i.MX53 Fuse_Map contains the next information
+ * about configuring SATA clocks :  SATA_ALT_REF_CLK[1:0] (offset 0x180C)
+ * '00' - 100MHz (External)
+ * '01' - 50MHz (External)
+ * '10' - 120MHz, internal (USB PHY)
+ * '11' - Reserved
+*/
+void mxc_set_sata_internal_clock(void)
+{
+	u32 *tmp_base =
+		(u32 *)(IIM_BASE_ADDR + 0x180c);
+
+	set_usb_phy_clk();
+
+	clrsetbits_le32(tmp_base, 0x6, 0x4);
+}
+#endif
+
+/*
+ * Dump some core clockes.
+ */
+int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 freq;
+
+	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+	printf("PLL1       %8d MHz\n", freq / 1000000);
+	freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
+	printf("PLL2       %8d MHz\n", freq / 1000000);
+	freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+	printf("PLL3       %8d MHz\n", freq / 1000000);
+#ifdef	CONFIG_MX53
+	freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+	printf("PLL4       %8d MHz\n", freq / 1000000);
+#endif
+
+	printf("\n");
+	printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
+	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
+	printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
+	return 0;
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
+	"display clocks",
+	""
+);
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/lowlevel_init.S
new file mode 100644
index 000000000..f5bc6728b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -0,0 +1,429 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+#include <linux/linkage.h>
+
+.section ".text.init", "x"
+
+.macro init_arm_erratum
+	/* ARM erratum ID #468414 */
+	mrc 15, 0, r1, c1, c0, 1
+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr 15, 0, r1, c1, c0, 1
+.endm
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+	/* explicitly disable L2 cache */
+	mrc 15, 0, r0, c1, c0, 1
+	bic r0, r0, #0x2
+	mcr 15, 0, r0, c1, c0, 1
+
+	/* reconfigure L2 cache aux control reg */
+	ldr r0, =0xC0 |			/* tag RAM */ \
+		 0x4 |			/* data RAM */ \
+		 1 << 24 |		/* disable write allocate delay */ \
+		 1 << 23 |		/* disable write allocate combine */ \
+		 1 << 22		/* disable write allocate */
+
+#if defined(CONFIG_MX51)
+	ldr r3, [r4, #ROM_SI_REV]
+	cmp r3, #0x10
+
+	/* disable write combine for TO 2 and lower revs */
+	orrls r0, r0, #1 << 25
+#endif
+
+	mcr 15, 1, r0, c9, c0, 2
+
+	/* enable L2 cache */
+	mrc 15, 0, r0, c1, c0, 1
+	orr r0, r0, #2
+	mcr 15, 0, r0, c1, c0, 1
+
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+.endm /* init_aips */
+
+/* M4IF setup */
+.macro init_m4if
+#ifdef CONFIG_MX51
+	/* VPU and IPU given higher priority (0x4)
+	 * IPU accesses with ID=0x1 given highest priority (=0xA)
+	 */
+	ldr r0, =M4IF_BASE_ADDR
+
+	ldr r1, =0x00000203
+	str r1, [r0, #0x40]
+
+	str r4, [r0, #0x44]
+
+	ldr r1, =0x00120125
+	str r1, [r0, #0x9C]
+
+	ldr r1, =0x001901A3
+	str r1, [r0, #0x48]
+
+#endif
+.endm /* init_m4if */
+
+.macro setup_pll pll, freq
+	ldr r0, =\pll
+	adr r2, W_DP_\freq
+	bl setup_pll_func
+.endm
+
+#define W_DP_OP		0
+#define W_DP_MFD	4
+#define W_DP_MFN	8
+
+setup_pll_func:
+	ldr r1, =0x00001232
+	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+	mov r1, #0x2
+	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+	ldr r1, [r2, #W_DP_OP]
+	str r1, [r0, #PLL_DP_OP]
+	str r1, [r0, #PLL_DP_HFS_OP]
+
+	ldr r1, [r2, #W_DP_MFD]
+	str r1, [r0, #PLL_DP_MFD]
+	str r1, [r0, #PLL_DP_HFS_MFD]
+
+	ldr r1, [r2, #W_DP_MFN]
+	str r1, [r0, #PLL_DP_MFN]
+	str r1, [r0, #PLL_DP_HFS_MFN]
+
+	ldr r1, =0x00001232
+	str r1, [r0, #PLL_DP_CTL]
+1:	ldr r1, [r0, #PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+
+	/* r10 saved upper lr */
+	mov pc, lr
+
+.macro setup_pll_errata pll, freq
+	ldr r2, =\pll
+	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+	ldr r1, =0x00001236
+	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
+1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
+	ands r1, r1, #0x1
+	beq 1b
+
+	ldr r5, \freq
+	str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
+	str r5, [r2, #PLL_DP_HFS_MFN]
+
+	mov r1, #0x1
+	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
+
+2:	ldr r1, [r2, #PLL_DP_CONFIG]
+	tst r1, #1
+	bne 2b
+
+	ldr r1, =100		     /* Wait at least 4 us */
+3:	subs r1, r1, #1
+	bge 3b
+
+	mov r1, #0x2
+	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+.endm
+
+.macro init_clock
+#if defined (CONFIG_MX51)
+	ldr r0, =CCM_BASE_ADDR
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r4, [r0, #CLKCTL_CCGR1]
+	str r4, [r0, #CLKCTL_CCGR2]
+	str r4, [r0, #CLKCTL_CCGR3]
+
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x00000300
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Disable IPU and HSC dividers */
+	mov r1, #0x60000
+	str r1, [r0, #CLKCTL_CCDR]
+
+	/* Make sure to switch the DDR away from PLL 1 */
+	ldr r1, =0x19239145
+	str r1, [r0, #CLKCTL_CBCDR]
+	/* make sure divider effective */
+1:	ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #CLKCTL_CCSR]
+
+#if defined(CONFIG_MX51_PLL_ERRATA)
+	setup_pll PLL1_BASE_ADDR, 864
+	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
+#else
+	setup_pll PLL1_BASE_ADDR, 800
+#endif
+
+	setup_pll PLL3_BASE_ADDR, 665
+
+	/* Switch peripheral to PLL 3 */
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
+	str r1, [r0, #CLKCTL_CBCMR]
+	ldr r1, =0x13239145
+	str r1, [r0, #CLKCTL_CBCDR]
+	setup_pll PLL2_BASE_ADDR, 665
+
+	/* Switch peripheral to PLL2 */
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x19239145
+	str r1, [r0, #CLKCTL_CBCDR]
+	ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	setup_pll PLL3_BASE_ADDR, 216
+
+	/* Set the platform clock dividers */
+	ldr r0, =ARM_BASE_ADDR
+	ldr r1, =0x00000725
+	str r1, [r0, #0x14]
+
+	ldr r0, =CCM_BASE_ADDR
+
+	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+	ldr r3, [r4, #ROM_SI_REV]
+	cmp r3, #0x10
+	movls r1, #0x1
+	movhi r1, #0
+
+	str r1, [r0, #CLKCTL_CACRR]
+
+	/* Switch ARM back to PLL 1 */
+	str r4, [r0, #CLKCTL_CCSR]
+
+	/* setup the rest */
+	/* Use lp_apm (24MHz) source for perclk */
+	ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
+	str r1, [r0, #CLKCTL_CBCMR]
+	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
+	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Use PLL 2 for UART's, get 66.5MHz from it */
+	ldr r1, =0xA5A2A020
+	str r1, [r0, #CLKCTL_CSCMR1]
+	ldr r1, =0x00C30321
+	str r1, [r0, #CLKCTL_CSCDR1]
+	/* make sure divider effective */
+1:	ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+	str r4, [r0, #CLKCTL_CCDR]
+
+	/* for cko - for ARM div by 8 */
+	mov r1, #0x000A0000
+	add r1, r1, #0x00000F0
+	str r1, [r0, #CLKCTL_CCOSR]
+#else	/* CONFIG_MX53 */
+	ldr r0, =CCM_BASE_ADDR
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r4, [r0, #CLKCTL_CCGR1]
+	str r4, [r0, #CLKCTL_CCGR2]
+	str r4, [r0, #CLKCTL_CCGR3]
+	str r4, [r0, #CLKCTL_CCGR7]
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x0F00030F
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #CLKCTL_CCSR]
+
+	setup_pll PLL1_BASE_ADDR, 800
+
+	setup_pll PLL3_BASE_ADDR, 400
+
+	/* Switch peripheral to PLL3 */
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x00015154
+	str r1, [r0, #CLKCTL_CBCMR]
+	ldr r1, =0x02898945
+	str r1, [r0, #CLKCTL_CBCDR]
+	/* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+	setup_pll PLL2_BASE_ADDR, 400
+
+	/* Switch peripheral to PLL2 */
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x00888945
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	ldr r1, =0x00016154
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	/*change uart clk parent to pll2*/
+	ldr r1, [r0, #CLKCTL_CSCMR1]
+	and r1, r1, #0xfcffffff
+	orr r1, r1, #0x01000000
+	str r1, [r0, #CLKCTL_CSCMR1]
+
+	/* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+	setup_pll PLL3_BASE_ADDR, 216
+
+	setup_pll PLL4_BASE_ADDR, 455
+
+	/* Set the platform clock dividers */
+	ldr r0, =ARM_BASE_ADDR
+	ldr r1, =0x00000124
+	str r1, [r0, #0x14]
+
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0
+	str r1, [r0, #CLKCTL_CACRR]
+
+	/* Switch ARM back to PLL 1. */
+	mov r1, #0x0
+	str r1, [r0, #CLKCTL_CCSR]
+
+	/* make uart div=6 */
+	ldr r1, [r0, #CLKCTL_CSCDR1]
+	and r1, r1, #0xffffffc0
+	orr r1, r1, #0x0a
+	str r1, [r0, #CLKCTL_CSCDR1]
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+	mov r1, #0x00000
+	str r1, [r0, #CLKCTL_CCDR]
+
+	/* for cko - for ARM div by 8 */
+	mov r1, #0x000A0000
+	add r1, r1, #0x00000F0
+	str r1, [r0, #CLKCTL_CCOSR]
+
+#endif	/* CONFIG_MX53 */
+.endm
+
+ENTRY(lowlevel_init)
+	mov r10, lr
+	mov r4, #0	/* Fix R4 to 0 */
+
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
+	ldr r0, =GPIO1_BASE_ADDR
+	ldr r1, [r0, #0x0]
+	orr r1, r1, #1 << 23
+	str r1, [r0, #0x0]
+	ldr r1, [r0, #0x4]
+	orr r1, r1, #1 << 23
+	str r1, [r0, #0x4]
+#endif
+
+	init_arm_erratum
+
+	init_l2cc
+
+	init_aips
+
+	init_m4if
+
+	init_clock
+
+	mov pc, r10
+ENDPROC(lowlevel_init)
+
+/* Board level setting value */
+#if defined(CONFIG_MX51_PLL_ERRATA)
+W_DP_864:		.word DP_OP_864
+			.word DP_MFD_864
+			.word DP_MFN_864
+W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
+#else
+W_DP_800:		.word DP_OP_800
+			.word DP_MFD_800
+			.word DP_MFN_800
+#endif
+#if defined(CONFIG_MX51)
+W_DP_665:		.word DP_OP_665
+			.word DP_MFD_665
+			.word DP_MFN_665
+#endif
+W_DP_216:		.word DP_OP_216
+			.word DP_MFD_216
+			.word DP_MFN_216
+W_DP_400:               .word DP_OP_400
+			.word DP_MFD_400
+			.word DP_MFN_400
+W_DP_455:               .word DP_OP_455
+			.word DP_MFD_455
+			.word DP_MFN_455
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/soc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/soc.c
new file mode 100644
index 000000000..2d53669c8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx5/soc.c
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/imx-common/boot_mode.h>
+
+#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
+#error "CPU_TYPE not defined"
+#endif
+
+u32 get_cpu_rev(void)
+{
+#ifdef CONFIG_MX51
+	int system_rev = 0x51000;
+#else
+	int system_rev = 0x53000;
+#endif
+	int reg = __raw_readl(ROM_SI_REV);
+
+#if defined(CONFIG_MX51)
+	switch (reg) {
+	case 0x02:
+		system_rev |= CHIP_REV_1_1;
+		break;
+	case 0x10:
+		if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
+			system_rev |= CHIP_REV_2_5;
+		else
+			system_rev |= CHIP_REV_2_0;
+		break;
+	case 0x20:
+		system_rev |= CHIP_REV_3_0;
+		break;
+	default:
+		system_rev |= CHIP_REV_1_0;
+		break;
+	}
+#else
+	if (reg < 0x20)
+		system_rev |= CHIP_REV_1_0;
+	else
+		system_rev |= reg;
+#endif
+	return system_rev;
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	int i;
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[1];
+	struct fuse_bank1_regs *fuse =
+			(struct fuse_bank1_regs *)bank->fuse_regs;
+
+	for (i = 0; i < 6; i++)
+		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
+#endif
+
+void set_chipselect_size(int const cs_size)
+{
+	unsigned int reg;
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	reg = readl(&iomuxc_regs->gpr1);
+
+	switch (cs_size) {
+	case CS0_128:
+		reg &= ~0x7;	/* CS0=128MB, CS1=0, CS2=0, CS3=0 */
+		reg |= 0x5;
+		break;
+	case CS0_64M_CS1_64M:
+		reg &= ~0x3F;	/* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
+		reg |= 0x1B;
+		break;
+	case CS0_64M_CS1_32M_CS2_32M:
+		reg &= ~0x1FF;	/* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
+		reg |= 0x4B;
+		break;
+	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
+		reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
+		reg |= 0x249;
+		break;
+	default:
+		printf("Unknown chip select size: %d\n", cs_size);
+		break;
+	}
+
+	writel(reg, &iomuxc_regs->gpr1);
+}
+
+#ifdef CONFIG_MX53
+void boot_mode_apply(unsigned cfg_val)
+{
+	writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
+}
+/*
+ * cfg_val will be used for
+ * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ *
+ * If bit 28 of LPGR is set upon watchdog reset,
+ * bits[25:0] of LPGR will move to SBMR.
+ */
+const struct boot_mode soc_boot_modes[] = {
+	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+	/* usb or serial download */
+	{"usb",		MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
+	{"sata",	MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
+	{"escpi1:0",	MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
+	{"escpi1:1",	MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
+	{"escpi1:2",	MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
+	{"escpi1:3",	MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
+	/* 4 bit bus width */
+	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
+	{"esdhc2",	MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
+	{"esdhc3",	MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
+	{"esdhc4",	MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
+	{NULL,		0},
+};
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/Makefile
new file mode 100644
index 000000000..d7285fc2c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= soc.o clock.o
+obj-$(CONFIG_SECURE_BOOT)    += hab.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/clock.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/clock.c
new file mode 100644
index 000000000..bd65a08ba
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/clock.c
@@ -0,0 +1,590 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+enum pll_clocks {
+	PLL_SYS,	/* System PLL */
+	PLL_BUS,	/* System Bus PLL*/
+	PLL_USBOTG,	/* OTG USB PLL */
+	PLL_ENET,	/* ENET PLL */
+};
+
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+	u32 reg;
+
+	reg = __raw_readl(&imx_ccm->CCGR2);
+	if (enable)
+		reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+	else
+		reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+	__raw_writel(reg, &imx_ccm->CCGR2);
+}
+#endif
+
+void enable_usboh3_clk(unsigned char enable)
+{
+	u32 reg;
+
+	reg = __raw_readl(&imx_ccm->CCGR6);
+	if (enable)
+		reg |= MXC_CCM_CCGR6_USBOH3_MASK;
+	else
+		reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
+	__raw_writel(reg, &imx_ccm->CCGR6);
+
+}
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be from 0 - 2 */
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+	u32 reg;
+	u32 mask;
+
+	if (i2c_num > 2)
+		return -EINVAL;
+
+	mask = MXC_CCM_CCGR_CG_MASK
+		<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
+	reg = __raw_readl(&imx_ccm->CCGR2);
+	if (enable)
+		reg |= mask;
+	else
+		reg &= ~mask;
+	__raw_writel(reg, &imx_ccm->CCGR2);
+	return 0;
+}
+#endif
+
+static u32 decode_pll(enum pll_clocks pll, u32 infreq)
+{
+	u32 div;
+
+	switch (pll) {
+	case PLL_SYS:
+		div = __raw_readl(&imx_ccm->analog_pll_sys);
+		div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
+
+		return infreq * (div >> 1);
+	case PLL_BUS:
+		div = __raw_readl(&imx_ccm->analog_pll_528);
+		div &= BM_ANADIG_PLL_528_DIV_SELECT;
+
+		return infreq * (20 + (div << 1));
+	case PLL_USBOTG:
+		div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
+		div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
+
+		return infreq * (20 + (div << 1));
+	case PLL_ENET:
+		div = __raw_readl(&imx_ccm->analog_pll_enet);
+		div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
+
+		return 25000000 * (div + (div >> 1) + 1);
+	default:
+		return 0;
+	}
+	/* NOTREACHED */
+}
+static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
+{
+	u32 div;
+	u64 freq;
+
+	switch (pll) {
+	case PLL_BUS:
+		if (pfd_num == 3) {
+			/* No PFD3 on PPL2 */
+			return 0;
+		}
+		div = __raw_readl(&imx_ccm->analog_pfd_528);
+		freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
+		break;
+	case PLL_USBOTG:
+		div = __raw_readl(&imx_ccm->analog_pfd_480);
+		freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
+		break;
+	default:
+		/* No PFD on other PLL					     */
+		return 0;
+	}
+
+	return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
+			      ANATOP_PFD_FRAC_SHIFT(pfd_num));
+}
+
+static u32 get_mcu_main_clk(void)
+{
+	u32 reg, freq;
+
+	reg = __raw_readl(&imx_ccm->cacrr);
+	reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
+	reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
+	freq = decode_pll(PLL_SYS, MXC_HCLK);
+
+	return freq / (reg + 1);
+}
+
+u32 get_periph_clk(void)
+{
+	u32 reg, freq = 0;
+
+	reg = __raw_readl(&imx_ccm->cbcdr);
+	if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+		reg = __raw_readl(&imx_ccm->cbcmr);
+		reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
+		reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
+
+		switch (reg) {
+		case 0:
+			freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+			break;
+		case 1:
+		case 2:
+			freq = MXC_HCLK;
+			break;
+		default:
+			break;
+		}
+	} else {
+		reg = __raw_readl(&imx_ccm->cbcmr);
+		reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
+		reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
+
+		switch (reg) {
+		case 0:
+			freq = decode_pll(PLL_BUS, MXC_HCLK);
+			break;
+		case 1:
+			freq = mxc_get_pll_pfd(PLL_BUS, 2);
+			break;
+		case 2:
+			freq = mxc_get_pll_pfd(PLL_BUS, 0);
+			break;
+		case 3:
+			/* static / 2 divider */
+			freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+			break;
+		default:
+			break;
+		}
+	}
+
+	return freq;
+}
+
+static u32 get_ipg_clk(void)
+{
+	u32 reg, ipg_podf;
+
+	reg = __raw_readl(&imx_ccm->cbcdr);
+	reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
+	ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
+
+	return get_ahb_clk() / (ipg_podf + 1);
+}
+
+static u32 get_ipg_per_clk(void)
+{
+	u32 reg, perclk_podf;
+
+	reg = __raw_readl(&imx_ccm->cscmr1);
+	perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
+
+	return get_ipg_clk() / (perclk_podf + 1);
+}
+
+static u32 get_uart_clk(void)
+{
+	u32 reg, uart_podf;
+	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
+	reg = __raw_readl(&imx_ccm->cscdr1);
+#ifdef CONFIG_MX6SL
+	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+		freq = MXC_HCLK;
+#endif
+	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
+	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+
+	return freq / (uart_podf + 1);
+}
+
+static u32 get_cspi_clk(void)
+{
+	u32 reg, cspi_podf;
+
+	reg = __raw_readl(&imx_ccm->cscdr2);
+	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
+	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+	return	decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
+}
+
+static u32 get_axi_clk(void)
+{
+	u32 root_freq, axi_podf;
+	u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
+
+	axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
+	axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
+
+	if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
+		if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
+			root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
+		else
+			root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
+	} else
+		root_freq = get_periph_clk();
+
+	return  root_freq / (axi_podf + 1);
+}
+
+static u32 get_emi_slow_clk(void)
+{
+	u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
+
+	cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
+	emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
+	emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
+	emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
+	emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
+
+	switch (emi_clk_sel) {
+	case 0:
+		root_freq = get_axi_clk();
+		break;
+	case 1:
+		root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+		break;
+	case 2:
+		root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
+		break;
+	case 3:
+		root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
+		break;
+	}
+
+	return root_freq / (emi_slow_podf + 1);
+}
+
+#ifdef CONFIG_MX6SL
+static u32 get_mmdc_ch0_clk(void)
+{
+	u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
+	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+	u32 freq, podf;
+
+	podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
+			>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+
+	switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+		MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+	case 0:
+		freq = decode_pll(PLL_BUS, MXC_HCLK);
+		break;
+	case 1:
+		freq = mxc_get_pll_pfd(PLL_BUS, 2);
+		break;
+	case 2:
+		freq = mxc_get_pll_pfd(PLL_BUS, 0);
+		break;
+	case 3:
+		/* static / 2 divider */
+		freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+	}
+
+	return freq / (podf + 1);
+
+}
+#else
+static u32 get_mmdc_ch0_clk(void)
+{
+	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+				MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+
+	return get_periph_clk() / (mmdc_ch0_podf + 1);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int enable_fec_anatop_clock(enum enet_freq freq)
+{
+	u32 reg = 0;
+	s32 timeout = 100000;
+
+	struct anatop_regs __iomem *anatop =
+		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+	if (freq < ENET_25MHz || freq > ENET_125MHz)
+		return -EINVAL;
+
+	reg = readl(&anatop->pll_enet);
+	reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+	reg |= freq;
+
+	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
+	    (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
+		reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
+		writel(reg, &anatop->pll_enet);
+		while (timeout--) {
+			if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
+				break;
+		}
+		if (timeout < 0)
+			return -ETIMEDOUT;
+	}
+
+	/* Enable FEC clock */
+	reg |= BM_ANADIG_PLL_ENET_ENABLE;
+	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
+	writel(reg, &anatop->pll_enet);
+
+	return 0;
+}
+#endif
+
+static u32 get_usdhc_clk(u32 port)
+{
+	u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
+	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
+	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+
+	switch (port) {
+	case 0:
+		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
+					MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
+		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
+
+		break;
+	case 1:
+		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
+					MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
+		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
+
+		break;
+	case 2:
+		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
+					MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
+		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
+
+		break;
+	case 3:
+		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
+					MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
+		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
+
+		break;
+	default:
+		break;
+	}
+
+	if (clk_sel)
+		root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
+	else
+		root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
+
+	return root_freq / (usdhc_podf + 1);
+}
+
+u32 imx_get_uartclk(void)
+{
+	return get_uart_clk();
+}
+
+u32 imx_get_fecclk(void)
+{
+	return mxc_get_clock(MXC_IPG_CLK);
+}
+
+static int enable_enet_pll(uint32_t en)
+{
+	struct mxc_ccm_reg *const imx_ccm
+		= (struct mxc_ccm_reg *) CCM_BASE_ADDR;
+	s32 timeout = 100000;
+	u32 reg = 0;
+
+	/* Enable PLLs */
+	reg = readl(&imx_ccm->analog_pll_enet);
+	reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
+	writel(reg, &imx_ccm->analog_pll_enet);
+	reg |= BM_ANADIG_PLL_SYS_ENABLE;
+	while (timeout--) {
+		if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
+			break;
+	}
+	if (timeout <= 0)
+		return -EIO;
+	reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
+	writel(reg, &imx_ccm->analog_pll_enet);
+	reg |= en;
+	writel(reg, &imx_ccm->analog_pll_enet);
+	return 0;
+}
+
+static void ungate_sata_clock(void)
+{
+	struct mxc_ccm_reg *const imx_ccm =
+		(struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Enable SATA clock. */
+	setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
+
+static void ungate_pcie_clock(void)
+{
+	struct mxc_ccm_reg *const imx_ccm =
+		(struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Enable PCIe clock. */
+	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
+}
+
+int enable_sata_clock(void)
+{
+	ungate_sata_clock();
+	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
+}
+
+int enable_pcie_clock(void)
+{
+	struct anatop_regs *anatop_regs =
+		(struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/*
+	 * Here be dragons!
+	 *
+	 * The register ANATOP_MISC1 is not documented in the Freescale
+	 * MX6RM. The register that is mapped in the ANATOP space and
+	 * marked as ANATOP_MISC1 is actually documented in the PMU section
+	 * of the datasheet as PMU_MISC1.
+	 *
+	 * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
+	 * enable clock OUTPUT. This is important for PCI express link that
+	 * is clocked from the i.MX6.
+	 */
+#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN		(1 << 12)
+#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN		(1 << 10)
+#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK	0x0000001F
+	clrsetbits_le32(&anatop_regs->ana_misc1,
+			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
+			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
+			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
+
+	/* PCIe reference clock sourced from AXI. */
+	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
+
+	/* Party time! Ungate the clock to the PCIe. */
+	ungate_sata_clock();
+	ungate_pcie_clock();
+
+	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
+			       BM_ANADIG_PLL_ENET_ENABLE_PCIE);
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return get_mcu_main_clk();
+	case MXC_PER_CLK:
+		return get_periph_clk();
+	case MXC_AHB_CLK:
+		return get_ahb_clk();
+	case MXC_IPG_CLK:
+		return get_ipg_clk();
+	case MXC_IPG_PERCLK:
+	case MXC_I2C_CLK:
+		return get_ipg_per_clk();
+	case MXC_UART_CLK:
+		return get_uart_clk();
+	case MXC_CSPI_CLK:
+		return get_cspi_clk();
+	case MXC_AXI_CLK:
+		return get_axi_clk();
+	case MXC_EMI_SLOW_CLK:
+		return get_emi_slow_clk();
+	case MXC_DDR_CLK:
+		return get_mmdc_ch0_clk();
+	case MXC_ESDHC_CLK:
+		return get_usdhc_clk(0);
+	case MXC_ESDHC2_CLK:
+		return get_usdhc_clk(1);
+	case MXC_ESDHC3_CLK:
+		return get_usdhc_clk(2);
+	case MXC_ESDHC4_CLK:
+		return get_usdhc_clk(3);
+	case MXC_SATA_CLK:
+		return get_ahb_clk();
+	default:
+		break;
+	}
+
+	return -1;
+}
+
+/*
+ * Dump some core clockes.
+ */
+int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 freq;
+	freq = decode_pll(PLL_SYS, MXC_HCLK);
+	printf("PLL_SYS    %8d MHz\n", freq / 1000000);
+	freq = decode_pll(PLL_BUS, MXC_HCLK);
+	printf("PLL_BUS    %8d MHz\n", freq / 1000000);
+	freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+	printf("PLL_OTG    %8d MHz\n", freq / 1000000);
+	freq = decode_pll(PLL_ENET, MXC_HCLK);
+	printf("PLL_NET    %8d MHz\n", freq / 1000000);
+
+	printf("\n");
+	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+	printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
+	printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
+	printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+	printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
+	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+	printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
+	printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
+	printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
+	printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
+	printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
+	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
+
+	return 0;
+}
+
+void enable_ipu_clock(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+}
+/***************************************************/
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
+	"display clocks",
+	""
+);
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/hab.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/hab.c
new file mode 100644
index 000000000..518777536
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/hab.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hab.h>
+
+/* -------- start of HAB API updates ------------*/
+#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)
+#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)
+#define hab_rvt_authenticate_image \
+	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)
+#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY)
+#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT)
+#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT
+
+bool is_hab_enabled(void)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[0];
+	struct fuse_bank0_regs *fuse =
+		(struct fuse_bank0_regs *)bank->fuse_regs;
+	uint32_t reg = readl(&fuse->cfg5);
+
+	return (reg & 0x2) == 0x2;
+}
+
+void display_event(uint8_t *event_data, size_t bytes)
+{
+	uint32_t i;
+
+	if (!(event_data && bytes > 0))
+		return;
+
+	for (i = 0; i < bytes; i++) {
+		if (i == 0)
+			printf("\t0x%02x", event_data[i]);
+		else if ((i % 8) == 0)
+			printf("\n\t0x%02x", event_data[i]);
+		else
+			printf(" 0x%02x", event_data[i]);
+	}
+}
+
+int get_hab_status(void)
+{
+	uint32_t index = 0; /* Loop index */
+	uint8_t event_data[128]; /* Event data buffer */
+	size_t bytes = sizeof(event_data); /* Event size in bytes */
+	enum hab_config config = 0;
+	enum hab_state state = 0;
+
+	if (is_hab_enabled())
+		puts("\nSecure boot enabled\n");
+	else
+		puts("\nSecure boot disabled\n");
+
+	/* Check HAB status */
+	if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
+		printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
+		       config, state);
+
+		/* Display HAB Error events */
+		while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
+					&bytes) == HAB_SUCCESS) {
+			puts("\n");
+			printf("--------- HAB Event %d -----------------\n",
+			       index + 1);
+			puts("event data:\n");
+			display_event(event_data, bytes);
+			puts("\n");
+			bytes = sizeof(event_data);
+			index++;
+		}
+	}
+	/* Display message if no HAB events are found */
+	else {
+		printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
+		       config, state);
+		puts("No HAB Events Found!\n\n");
+	}
+	return 0;
+}
+
+int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if ((argc != 1)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	get_hab_status();
+
+	return 0;
+}
+
+U_BOOT_CMD(
+		hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
+		"display HAB status",
+		""
+	  );
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/soc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/soc.c
new file mode 100644
index 000000000..172527987
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/mx6/soc.c
@@ -0,0 +1,435 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/dma.h>
+#include <stdbool.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+
+enum ldo_reg {
+	LDO_ARM,
+	LDO_SOC,
+	LDO_PU,
+};
+
+struct scu_regs {
+	u32	ctrl;
+	u32	config;
+	u32	status;
+	u32	invalidate;
+	u32	fpga_rev;
+};
+
+u32 get_cpu_rev(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	u32 reg = readl(&anatop->digprog_sololite);
+	u32 type = ((reg >> 16) & 0xff);
+
+	if (type != MXC_CPU_MX6SL) {
+		reg = readl(&anatop->digprog);
+		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+		u32 cfg = readl(&scu->config) & 3;
+		type = ((reg >> 16) & 0xff);
+		if (type == MXC_CPU_MX6DL) {
+			if (!cfg)
+				type = MXC_CPU_MX6SOLO;
+		}
+
+		if (type == MXC_CPU_MX6Q) {
+			if (cfg == 1)
+				type = MXC_CPU_MX6D;
+		}
+
+	}
+	reg &= 0xff;		/* mx6 silicon revision */
+	return (type << 12) | (reg + 0x10);
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+	u32 cpurev = get_cpu_rev();
+	u32 type = ((cpurev >> 12) & 0xff);
+	if (type == MXC_CPU_MX6SOLO)
+		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
+
+	if (type == MXC_CPU_MX6D)
+		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
+
+	return cpurev;
+}
+#endif
+
+void init_aips(void)
+{
+	struct aipstz_regs *aips1, *aips2;
+
+	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
+	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
+
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	writel(0x77777777, &aips1->mprot0);
+	writel(0x77777777, &aips1->mprot1);
+	writel(0x77777777, &aips2->mprot0);
+	writel(0x77777777, &aips2->mprot1);
+
+	/*
+	 * Set all OPACRx to be non-bufferable, not require
+	 * supervisor privilege level for access,allow for
+	 * write access and untrusted master access.
+	 */
+	writel(0x00000000, &aips1->opacr0);
+	writel(0x00000000, &aips1->opacr1);
+	writel(0x00000000, &aips1->opacr2);
+	writel(0x00000000, &aips1->opacr3);
+	writel(0x00000000, &aips1->opacr4);
+	writel(0x00000000, &aips2->opacr0);
+	writel(0x00000000, &aips2->opacr1);
+	writel(0x00000000, &aips2->opacr2);
+	writel(0x00000000, &aips2->opacr3);
+	writel(0x00000000, &aips2->opacr4);
+}
+
+static void clear_ldo_ramp(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int reg;
+
+	/* ROM may modify LDO ramp up time according to fuse setting, so in
+	 * order to be in the safe side we neeed to reset these settings to
+	 * match the reset value: 0'b00
+	 */
+	reg = readl(&anatop->ana_misc2);
+	reg &= ~(0x3f << 24);
+	writel(reg, &anatop->ana_misc2);
+}
+
+/*
+ * Set the VDDSOC
+ *
+ * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
+ * them to the specified millivolt level.
+ * Possible values are from 0.725V to 1.450V in steps of
+ * 0.025V (25mV).
+ */
+static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	u32 val, step, old, reg = readl(&anatop->reg_core);
+	u8 shift;
+
+	if (mv < 725)
+		val = 0x00;	/* Power gated off */
+	else if (mv > 1450)
+		val = 0x1F;	/* Power FET switched full on. No regulation */
+	else
+		val = (mv - 700) / 25;
+
+	clear_ldo_ramp();
+
+	switch (ldo) {
+	case LDO_SOC:
+		shift = 18;
+		break;
+	case LDO_PU:
+		shift = 9;
+		break;
+	case LDO_ARM:
+		shift = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	old = (reg & (0x1F << shift)) >> shift;
+	step = abs(val - old);
+	if (step == 0)
+		return 0;
+
+	reg = (reg & ~(0x1F << shift)) | (val << shift);
+	writel(reg, &anatop->reg_core);
+
+	/*
+	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
+	 * step
+	 */
+	udelay(3 * step);
+
+	return 0;
+}
+
+static void imx_set_wdog_powerdown(bool enable)
+{
+	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+
+	/* Write to the PDE (Power Down Enable) bit */
+	writew(enable, &wdog1->wmcr);
+	writew(enable, &wdog2->wmcr);
+}
+
+static void set_ahb_rate(u32 val)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg, div;
+
+	div = get_periph_clk() / val - 1;
+	reg = readl(&mxc_ccm->cbcdr);
+
+	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
+		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
+}
+
+static void clear_mmdc_ch_mask(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Clear MMDC channel mask */
+	writel(0, &mxc_ccm->ccdr);
+}
+
+int arch_cpu_init(void)
+{
+	init_aips();
+
+	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
+	clear_mmdc_ch_mask();
+
+	/*
+	 * When low freq boot is enabled, ROM will not set AHB
+	 * freq, so we need to ensure AHB freq is 132MHz in such
+	 * scenario.
+	 */
+	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
+		set_ahb_rate(132000000);
+
+	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+
+#ifdef CONFIG_APBH_DMA
+	/* Start APBH DMA */
+	mxs_dma_init();
+#endif
+
+	return 0;
+}
+
+int board_postclk_init(void)
+{
+	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Avoid random hang when download by usb */
+	invalidate_dcache_all();
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[4];
+	struct fuse_bank4_regs *fuse =
+			(struct fuse_bank4_regs *)bank->fuse_regs;
+
+	u32 value = readl(&fuse->mac_addr_high);
+	mac[0] = (value >> 8);
+	mac[1] = value ;
+
+	value = readl(&fuse->mac_addr_low);
+	mac[2] = value >> 24 ;
+	mac[3] = value >> 16 ;
+	mac[4] = value >> 8 ;
+	mac[5] = value ;
+
+}
+#endif
+
+void boot_mode_apply(unsigned cfg_val)
+{
+	unsigned reg;
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	writel(cfg_val, &psrc->gpr9);
+	reg = readl(&psrc->gpr10);
+	if (cfg_val)
+		reg |= 1 << 28;
+	else
+		reg &= ~(1 << 28);
+	writel(reg, &psrc->gpr10);
+}
+/*
+ * cfg_val will be used for
+ * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
+ * to SBMR1, which will determine the boot device.
+ */
+const struct boot_mode soc_boot_modes[] = {
+	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+	/* reserved value should start rom usb */
+	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
+	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
+	{"escpi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
+	{"escpi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
+	{"escpi1:2",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
+	{"escpi1:3",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
+	/* 4 bit bus width */
+	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{"esdhc2",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"esdhc3",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"esdhc4",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,		0},
+};
+
+void s_init(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int is_6q = is_cpu_type(MXC_CPU_MX6Q);
+	u32 mask480;
+	u32 mask528;
+
+	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
+	 * to make sure PFD is working right, otherwise, PFDs may
+	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
+	 * workaround in ROM code, as bus clock need it
+	 */
+
+	mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
+		ANATOP_PFD_CLKGATE_MASK(1) |
+		ANATOP_PFD_CLKGATE_MASK(2) |
+		ANATOP_PFD_CLKGATE_MASK(3);
+	mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
+		ANATOP_PFD_CLKGATE_MASK(1) |
+		ANATOP_PFD_CLKGATE_MASK(3);
+
+	/*
+	 * Don't reset PFD2 on DL/S
+	 */
+	if (is_6q)
+		mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
+	writel(mask480, &anatop->pfd_480_set);
+	writel(mask528, &anatop->pfd_528_set);
+	writel(mask480, &anatop->pfd_480_clr);
+	writel(mask528, &anatop->pfd_528_clr);
+}
+
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void)
+{
+	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	u8 reg;
+	reg = readb(&hdmi->phy_conf0);
+	reg |= HDMI_PHY_CONF0_PDZ_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+}
+
+void imx_setup_hdmi(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	int reg;
+
+	/* Turn on HDMI PHY clock */
+	reg = readl(&mxc_ccm->CCGR2);
+	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
+		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+	writel(reg, &mxc_ccm->CCGR2);
+	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+	reg = readl(&mxc_ccm->chsccdr);
+	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
+		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
+		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
+		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
+		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+}
+#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
+void v7_outer_cache_enable(void)
+{
+	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+	unsigned int val;
+
+#if defined CONFIG_MX6SL
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	val = readl(&iomux->gpr[11]);
+	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+		/* L2 cache configured as OCRAM, reset it */
+		val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+		writel(val, &iomux->gpr[11]);
+	}
+#endif
+
+	writel(0x132, &pl310->pl310_tag_latency_ctrl);
+	writel(0x132, &pl310->pl310_data_latency_ctrl);
+
+	val = readl(&pl310->pl310_prefetch_ctrl);
+
+	/* Turn on the L2 I/D prefetch */
+	val |= 0x30000000;
+
+	/*
+	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+	 * But according to ARM PL310 errata: 752271
+	 * ID: 752271: Double linefill feature can cause data corruption
+	 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+	 * Workaround: The only workaround to this erratum is to disable the
+	 * double linefill feature. This is the default behavior.
+	 */
+
+#ifndef CONFIG_MX6Q
+	val |= 0x40800000;
+#endif
+	writel(val, &pl310->pl310_prefetch_ctrl);
+
+	val = readl(&pl310->pl310_power_ctrl);
+	val |= L2X0_DYNAMIC_CLK_GATING_EN;
+	val |= L2X0_STNDBY_MODE_EN;
+	writel(val, &pl310->pl310_power_ctrl);
+
+	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/nonsec_virt.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/nonsec_virt.S
new file mode 100644
index 000000000..6367e0961
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/nonsec_virt.S
@@ -0,0 +1,192 @@
+/*
+ * code for switching cores into non-secure state and into HYP mode
+ *
+ * Copyright (c) 2013	Andre Przywara <andre.przywara@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/gic.h>
+#include <asm/armv7.h>
+
+.arch_extension sec
+.arch_extension virt
+
+	.align	5
+/* the vector table for secure state and HYP mode */
+_monitor_vectors:
+	.word 0	/* reset */
+	.word 0 /* undef */
+	adr pc, _secure_monitor
+	.word 0
+	.word 0
+	adr pc, _hyp_trap
+	.word 0
+	.word 0
+
+/*
+ * secure monitor handler
+ * U-boot calls this "software interrupt" in start.S
+ * This is executed on a "smc" instruction, we use a "smc #0" to switch
+ * to non-secure state.
+ * We use only r0 and r1 here, due to constraints in the caller.
+ */
+_secure_monitor:
+	mrc	p15, 0, r1, c1, c1, 0		@ read SCR
+	bic	r1, r1, #0x4e			@ clear IRQ, FIQ, EA, nET bits
+	orr	r1, r1, #0x31			@ enable NS, AW, FW bits
+
+#ifdef CONFIG_ARMV7_VIRT
+	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
+	and	r0, r0, #CPUID_ARM_VIRT_MASK	@ mask virtualization bits
+	cmp	r0, #(1 << CPUID_ARM_VIRT_SHIFT)
+	orreq	r1, r1, #0x100			@ allow HVC instruction
+#endif
+
+	mcr	p15, 0, r1, c1, c1, 0		@ write SCR (with NS bit set)
+
+#ifdef CONFIG_ARMV7_VIRT
+	mrceq	p15, 0, r0, c12, c0, 1		@ get MVBAR value
+	mcreq	p15, 4, r0, c12, c0, 0		@ write HVBAR
+#endif
+
+	movs	pc, lr				@ return to non-secure SVC
+
+_hyp_trap:
+	mrs	lr, elr_hyp	@ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
+	mov pc, lr				@ do no switch modes, but
+						@ return to caller
+
+/*
+ * Secondary CPUs start here and call the code for the core specific parts
+ * of the non-secure and HYP mode transition. The GIC distributor specific
+ * code has already been executed by a C function before.
+ * Then they go back to wfi and wait to be woken up by the kernel again.
+ */
+ENTRY(_smp_pen)
+	mrs	r0, cpsr
+	orr	r0, r0, #0xc0
+	msr	cpsr, r0			@ disable interrupts
+	ldr	r1, =_start
+	mcr	p15, 0, r1, c12, c0, 0		@ set VBAR
+
+	bl	_nonsec_init
+	mov	r12, r0				@ save GICC address
+#ifdef CONFIG_ARMV7_VIRT
+	bl	_switch_to_hyp
+#endif
+
+	ldr	r1, [r12, #GICC_IAR]		@ acknowledge IPI
+	str	r1, [r12, #GICC_EOIR]		@ signal end of interrupt
+
+	adr	r0, _smp_pen			@ do not use this address again
+	b	smp_waitloop			@ wait for IPIs, board specific
+ENDPROC(_smp_pen)
+
+/*
+ * Switch a core to non-secure state.
+ *
+ *  1. initialize the GIC per-core interface
+ *  2. allow coprocessor access in non-secure modes
+ *  3. switch the cpu mode (by calling "smc #0")
+ *
+ * Called from smp_pen by secondary cores and directly by the BSP.
+ * Do not assume that the stack is available and only use registers
+ * r0-r3 and r12.
+ *
+ * PERIPHBASE is used to get the GIC address. This could be 40 bits long,
+ * though, but we check this in C before calling this function.
+ */
+ENTRY(_nonsec_init)
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+	ldr	r2, =CONFIG_ARM_GIC_BASE_ADDRESS
+#else
+	mrc	p15, 4, r2, c15, c0, 0		@ read CBAR
+	bfc	r2, #0, #15			@ clear reserved bits
+#endif
+	add	r3, r2, #GIC_DIST_OFFSET	@ GIC dist i/f offset
+	mvn	r1, #0				@ all bits to 1
+	str	r1, [r3, #GICD_IGROUPRn]	@ allow private interrupts
+
+	mrc	p15, 0, r0, c0, c0, 0		@ read MIDR
+	ldr	r1, =MIDR_PRIMARY_PART_MASK
+	and	r0, r0, r1			@ mask out variant and revision
+
+	ldr	r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
+	cmp	r0, r1				@ check for Cortex-A7
+
+	ldr	r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
+	cmpne	r0, r1				@ check for Cortex-A15
+
+	movne	r1, #GIC_CPU_OFFSET_A9		@ GIC CPU offset for A9
+	moveq	r1, #GIC_CPU_OFFSET_A15		@ GIC CPU offset for A15/A7
+	add	r3, r2, r1			@ r3 = GIC CPU i/f addr
+
+	mov	r1, #1				@ set GICC_CTLR[enable]
+	str	r1, [r3, #GICC_CTLR]		@ and clear all other bits
+	mov	r1, #0xff
+	str	r1, [r3, #GICC_PMR]		@ set priority mask register
+
+	movw	r1, #0x3fff
+	movt	r1, #0x0006
+	mcr	p15, 0, r1, c1, c1, 2		@ NSACR = all copros to non-sec
+
+/* The CNTFRQ register of the generic timer needs to be
+ * programmed in secure state. Some primary bootloaders / firmware
+ * omit this, so if the frequency is provided in the configuration,
+ * we do this here instead.
+ * But first check if we have the generic timer.
+ */
+#ifdef CONFIG_SYS_CLK_FREQ
+	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
+	and	r0, r0, #CPUID_ARM_GENTIMER_MASK	@ mask arch timer bits
+	cmp	r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
+	ldreq	r1, =CONFIG_SYS_CLK_FREQ
+	mcreq	p15, 0, r1, c14, c0, 0		@ write CNTFRQ
+#endif
+
+	adr	r1, _monitor_vectors
+	mcr	p15, 0, r1, c12, c0, 1		@ set MVBAR to secure vectors
+
+	mrc	p15, 0, ip, c12, c0, 0		@ save secure copy of VBAR
+
+	isb
+	smc	#0				@ call into MONITOR mode
+
+	mcr	p15, 0, ip, c12, c0, 0		@ write non-secure copy of VBAR
+
+	mov	r1, #1
+	str	r1, [r3, #GICC_CTLR]		@ enable non-secure CPU i/f
+	add	r2, r2, #GIC_DIST_OFFSET
+	str	r1, [r2, #GICD_CTLR]		@ allow private interrupts
+
+	mov	r0, r3				@ return GICC address
+
+	bx	lr
+ENDPROC(_nonsec_init)
+
+#ifdef CONFIG_SMP_PEN_ADDR
+/* void __weak smp_waitloop(unsigned previous_address); */
+ENTRY(smp_waitloop)
+	wfi
+	ldr	r1, =CONFIG_SMP_PEN_ADDR	@ load start address
+	ldr	r1, [r1]
+	cmp	r0, r1			@ make sure we dont execute this code
+	beq	smp_waitloop		@ again (due to a spurious wakeup)
+	mov	pc, r1
+ENDPROC(smp_waitloop)
+.weak smp_waitloop
+#endif
+
+ENTRY(_switch_to_hyp)
+	mov	r0, lr
+	mov	r1, sp				@ save SVC copy of LR and SP
+	isb
+	hvc #0			 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
+	mov	sp, r1
+	mov	lr, r0				@ restore SVC copy of LR and SP
+
+	bx	lr
+ENDPROC(_switch_to_hyp)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/Makefile
new file mode 100644
index 000000000..59f5352b2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/Makefile
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= reset.o
+obj-y	+= timer.o
+obj-y	+= utils.o
+
+ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+obj-y	+= hwinit-common.o
+obj-y	+= clocks-common.o
+obj-y	+= emif-common.o
+obj-y	+= vc.o
+obj-y	+= abb.o
+endif
+
+ifneq ($(CONFIG_OMAP54XX),)
+obj-y	+= pipe3-phy.o
+obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
+endif
+
+ifeq ($(CONFIG_OMAP34XX),)
+obj-y	+= boot-common.o
+obj-y	+= lowlevel_init.o
+endif
+
+ifndef CONFIG_SPL_BUILD
+ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+obj-y	+= mem-common.o
+endif
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/abb.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/abb.c
new file mode 100644
index 000000000..423aeb980
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/abb.c
@@ -0,0 +1,121 @@
+/*
+ * Adaptive Body Bias programming sequence for OMAP family
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
+{
+	return -1;
+}
+
+static void abb_setup_timings(u32 setup)
+{
+	u32 sys_rate, sr2_cnt, clk_cycles;
+
+	/*
+	 * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a
+	 * transition and must be programmed with the correct time at boot.
+	 * The value programmed into the register is the number of SYS_CLK
+	 * clock cycles that match a given wall time profiled for the ldo.
+	 * This value depends on:
+	 * settling time of ldo in micro-seconds (varies per OMAP family),
+	 * of clock cycles per SYS_CLK period (varies per OMAP family),
+	 * the SYS_CLK frequency in MHz (varies per board)
+	 * The formula is:
+	 *
+	 *		       ldo settling time (in micro-seconds)
+	 * SR2_WTCNT_VALUE = ------------------------------------------
+	 *		    (# system clock cycles) * (sys_clk period)
+	 *
+	 * Put another way:
+	 *
+	 * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate))
+	 *
+	 * To avoid dividing by zero multiply both "# clock cycles" and
+	 * "settling time" by 10 such that the final result is the one we want.
+	 */
+
+	/* calculate SR2_WTCNT_VALUE */
+	sys_rate = DIV_ROUND(V_OSCK, 1000000);
+	clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
+	sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
+
+	setbits_le32(setup,
+		     sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));
+}
+
+void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
+	       u32 txdone, u32 txdone_mask, u32 opp)
+{
+	u32 abb_type_mask, opp_sel_mask;
+
+	/* sanity check */
+	if (!setup || !control || !txdone)
+		return;
+
+	/* setup ABB only in case of Fast or Slow OPP */
+	switch (opp) {
+	case OMAP_ABB_FAST_OPP:
+		abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK;
+		opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK;
+		break;
+	case OMAP_ABB_SLOW_OPP:
+		abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK;
+		opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK;
+		break;
+	default:
+	       return;
+	}
+
+	/*
+	 * For some OMAP silicons additional setup for LDOVBB register is
+	 * required. This is determined by data retrieved from corresponding
+	 * OPP EFUSE register. Data, which is retrieved from EFUSE - is
+	 * ABB enable/disable flag and VSET value, which must be copied
+	 * to LDOVBB register. If function call fails - return quietly,
+	 * it means no ABB is required for such silicon.
+	 *
+	 * For silicons, which don't require LDOVBB setup "fuse" and
+	 * "ldovbb" offsets are not defined. ABB will be initialized in
+	 * the common way for them.
+	 */
+	if (fuse && ldovbb) {
+		if (abb_setup_ldovbb(fuse, ldovbb))
+			return;
+	}
+
+	/* clear ABB registers */
+	writel(0, setup);
+	writel(0, control);
+
+	/* configure timings, based on oscillator value */
+	abb_setup_timings(setup);
+
+	/* clear pending interrupts before setup */
+	setbits_le32(txdone, txdone_mask);
+
+	/* select ABB type */
+	setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK);
+
+	/* initiate ABB ldo change */
+	setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK);
+
+	/* wait until transition complete */
+	if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY))
+		puts("Error: ABB txdone is not set\n");
+
+	/* clear ABB tranxdone */
+	setbits_le32(txdone, txdone_mask);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/boot-common.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/boot-common.c
new file mode 100644
index 000000000..303356476
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -0,0 +1,134 @@
+/*
+ * boot-common.c
+ *
+ * Common bootmode functions for omap based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/omap_common.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void save_omap_boot_params(void)
+{
+	u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+	u8 boot_device;
+	u32 dev_desc, dev_data;
+
+	if ((rom_params <  NON_SECURE_SRAM_START) ||
+	    (rom_params > NON_SECURE_SRAM_END))
+		return;
+
+	/*
+	 * rom_params can be type casted to omap_boot_parameters and
+	 * used. But it not correct to assume that romcode structure
+	 * encoding would be same as u-boot. So use the defined offsets.
+	 */
+	gd->arch.omap_boot_params.omap_bootdevice = boot_device =
+				   *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+	gd->arch.omap_boot_params.ch_flags =
+				*((u8 *)(rom_params + CH_FLAGS_OFFSET));
+
+	if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+	    (boot_device <= MMC_BOOT_DEVICES_END)) {
+#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) && \
+	!defined(CONFIG_AM43XX)
+		if ((omap_hw_init_context() ==
+				      OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
+			gd->arch.omap_boot_params.omap_bootmode =
+			*((u8 *)(rom_params + BOOT_MODE_OFFSET));
+		} else
+#endif
+		{
+			dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
+			dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
+			gd->arch.omap_boot_params.omap_bootmode =
+					*((u32 *)(dev_data + BOOT_MODE_OFFSET));
+		}
+	}
+
+#ifdef CONFIG_DRA7XX
+	/*
+	 * We get different values for QSPI_1 and QSPI_4 being used, but
+	 * don't actually care about this difference.  Rather than
+	 * mangle the later code, if we're coming in as QSPI_4 just
+	 * change to the QSPI_1 value.
+	 */
+	if (gd->arch.omap_boot_params.omap_bootdevice == 11)
+		gd->arch.omap_boot_params.omap_bootdevice = BOOT_DEVICE_SPI;
+#endif
+}
+
+#ifdef CONFIG_SPL_BUILD
+u32 spl_boot_device(void)
+{
+	return (u32) (gd->arch.omap_boot_params.omap_bootdevice);
+}
+
+u32 spl_boot_mode(void)
+{
+	u32 val = gd->arch.omap_boot_params.omap_bootmode;
+
+	if (val == MMCSD_MODE_RAW)
+		return MMCSD_MODE_RAW;
+	else if (val == MMCSD_MODE_FAT)
+		return MMCSD_MODE_FAT;
+	else
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+		return MMCSD_MODE_EMMCBOOT;
+#else
+		return MMCSD_MODE_UNDEFINED;
+#endif
+}
+
+void spl_board_init(void)
+{
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	gpmc_init();
+#endif
+#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
+	arch_misc_init();
+#endif
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+#ifdef CONFIG_AM33XX
+	am33xx_spl_board_init();
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0, 0, 0, -1, -1);
+		break;
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		omap_mmc_init(1, 0, 0, -1, -1);
+		break;
+	}
+	return 0;
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	typedef void __noreturn (*image_entry_noargs_t)(u32 *);
+	image_entry_noargs_t image_entry =
+			(image_entry_noargs_t) spl_image->entry_point;
+
+	debug("image entry point: 0x%X\n", spl_image->entry_point);
+	/* Pass the saved boot_params from rom code */
+	image_entry((u32 *)&gd->arch.omap_boot_params);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/clocks-common.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/clocks-common.c
new file mode 100644
index 000000000..8e7411d43
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -0,0 +1,733 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * Based on previous work by:
+ *	Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *	Rajendra Nayak <rnayak@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+#include <asm/omap_common.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+#include <asm/omap_gpio.h>
+#include <asm/emif.h>
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * printing to console doesn't work unless
+ * this code is executed from SPL
+ */
+#define printf(fmt, args...)
+#define puts(s)
+#endif
+
+const u32 sys_clk_array[8] = {
+	12000000,	       /* 12 MHz */
+	20000000,		/* 20 MHz */
+	16800000,	       /* 16.8 MHz */
+	19200000,	       /* 19.2 MHz */
+	26000000,	       /* 26 MHz */
+	27000000,	       /* 27 MHz */
+	38400000,	       /* 38.4 MHz */
+};
+
+static inline u32 __get_sys_clk_index(void)
+{
+	s8 ind;
+	/*
+	 * For ES1 the ROM code calibration of sys clock is not reliable
+	 * due to hw issue. So, use hard-coded value. If this value is not
+	 * correct for any board over-ride this function in board file
+	 * From ES2.0 onwards you will get this information from
+	 * CM_SYS_CLKSEL
+	 */
+	if (omap_revision() == OMAP4430_ES1_0)
+		ind = OMAP_SYS_CLK_IND_38_4_MHZ;
+	else {
+		/* SYS_CLKSEL - 1 to match the dpll param array indices */
+		ind = (readl((*prcm)->cm_sys_clksel) &
+			CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+	}
+	return ind;
+}
+
+u32 get_sys_clk_index(void)
+	__attribute__ ((weak, alias("__get_sys_clk_index")));
+
+u32 get_sys_clk_freq(void)
+{
+	u8 index = get_sys_clk_index();
+	return sys_clk_array[index];
+}
+
+void setup_post_dividers(u32 const base, const struct dpll_params *params)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	/* Setup post-dividers */
+	if (params->m2 >= 0)
+		writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+	if (params->m3 >= 0)
+		writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+	if (params->m4_h11 >= 0)
+		writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
+	if (params->m5_h12 >= 0)
+		writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
+	if (params->m6_h13 >= 0)
+		writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
+	if (params->m7_h14 >= 0)
+		writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
+	if (params->h21 >= 0)
+		writel(params->h21, &dpll_regs->cm_div_h21_dpll);
+	if (params->h22 >= 0)
+		writel(params->h22, &dpll_regs->cm_div_h22_dpll);
+	if (params->h23 >= 0)
+		writel(params->h23, &dpll_regs->cm_div_h23_dpll);
+	if (params->h24 >= 0)
+		writel(params->h24, &dpll_regs->cm_div_h24_dpll);
+}
+
+static inline void do_bypass_dpll(u32 const base)
+{
+	struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
+
+	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+			CM_CLKMODE_DPLL_DPLL_EN_MASK,
+			DPLL_EN_FAST_RELOCK_BYPASS <<
+			CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_bypass(u32 const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
+				LDELAY)) {
+		printf("Bypassing DPLL failed %x\n", base);
+	}
+}
+
+static inline void do_lock_dpll(u32 const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
+		      CM_CLKMODE_DPLL_DPLL_EN_MASK,
+		      DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+}
+
+static inline void wait_for_lock(u32 const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+		&dpll_regs->cm_idlest_dpll, LDELAY)) {
+		printf("DPLL locking failed for %x\n", base);
+		hang();
+	}
+}
+
+inline u32 check_for_lock(u32 const base)
+{
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+	u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
+
+	return lock;
+}
+
+const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+	return &dpll_data->mpu[sysclk_ind];
+}
+
+const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+	return &dpll_data->core[sysclk_ind];
+}
+
+const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+	return &dpll_data->per[sysclk_ind];
+}
+
+const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+	return &dpll_data->iva[sysclk_ind];
+}
+
+const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+	return &dpll_data->usb[sysclk_ind];
+}
+
+const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
+{
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	u32 sysclk_ind = get_sys_clk_index();
+	return &dpll_data->abe[sysclk_ind];
+#else
+	return dpll_data->abe;
+#endif
+}
+
+static const struct dpll_params *get_ddr_dpll_params
+			(struct dplls const *dpll_data)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+
+	if (!dpll_data->ddr)
+		return NULL;
+	return &dpll_data->ddr[sysclk_ind];
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static const struct dpll_params *get_gmac_dpll_params
+			(struct dplls const *dpll_data)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+
+	if (!dpll_data->gmac)
+		return NULL;
+	return &dpll_data->gmac[sysclk_ind];
+}
+#endif
+
+static void do_setup_dpll(u32 const base, const struct dpll_params *params,
+				u8 lock, char *dpll)
+{
+	u32 temp, M, N;
+	struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+	if (!params)
+		return;
+
+	temp = readl(&dpll_regs->cm_clksel_dpll);
+
+	if (check_for_lock(base)) {
+		/*
+		 * The Dpll has already been locked by rom code using CH.
+		 * Check if M,N are matching with Ideal nominal opp values.
+		 * If matches, skip the rest otherwise relock.
+		 */
+		M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
+		N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
+		if ((M != (params->m)) || (N != (params->n))) {
+			debug("\n %s Dpll locked, but not for ideal M = %d,"
+				"N = %d values, current values are M = %d,"
+				"N= %d" , dpll, params->m, params->n,
+				M, N);
+		} else {
+			/* Dpll locked with ideal values for nominal opps. */
+			debug("\n %s Dpll already locked with ideal"
+						"nominal opp values", dpll);
+			goto setup_post_dividers;
+		}
+	}
+
+	bypass_dpll(base);
+
+	/* Set M & N */
+	temp &= ~CM_CLKSEL_DPLL_M_MASK;
+	temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
+
+	temp &= ~CM_CLKSEL_DPLL_N_MASK;
+	temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
+
+	writel(temp, &dpll_regs->cm_clksel_dpll);
+
+	/* Lock */
+	if (lock)
+		do_lock_dpll(base);
+
+setup_post_dividers:
+	setup_post_dividers(base, params);
+
+	/* Wait till the DPLL locks */
+	if (lock)
+		wait_for_lock(base);
+}
+
+u32 omap_ddr_clk(void)
+{
+	u32 ddr_clk, sys_clk_khz, omap_rev, divider;
+	const struct dpll_params *core_dpll_params;
+
+	omap_rev = omap_revision();
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	core_dpll_params = get_core_dpll_params(*dplls_data);
+
+	debug("sys_clk %d\n ", sys_clk_khz * 1000);
+
+	/* Find Core DPLL locked frequency first */
+	ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
+			(core_dpll_params->n + 1);
+
+	if (omap_rev < OMAP5430_ES1_0) {
+		/*
+		 * DDR frequency is PHY_ROOT_CLK/2
+		 * PHY_ROOT_CLK = Fdpll/2/M2
+		 */
+		divider = 4;
+	} else {
+		/*
+		 * DDR frequency is PHY_ROOT_CLK
+		 * PHY_ROOT_CLK = Fdpll/2/M2
+		 */
+		divider = 2;
+	}
+
+	ddr_clk = ddr_clk / divider / core_dpll_params->m2;
+	ddr_clk *= 1000;	/* convert to Hz */
+	debug("ddr_clk %d\n ", ddr_clk);
+
+	return ddr_clk;
+}
+
+/*
+ * Lock MPU dpll
+ *
+ * Resulting MPU frequencies:
+ * 4430 ES1.0	: 600 MHz
+ * 4430 ES2.x	: 792 MHz (OPP Turbo)
+ * 4460		: 920 MHz (OPP Turbo) - DCC disabled
+ */
+void configure_mpu_dpll(void)
+{
+	const struct dpll_params *params;
+	struct dpll_regs *mpu_dpll_regs;
+	u32 omap_rev;
+	omap_rev = omap_revision();
+
+	/*
+	 * DCC and clock divider settings for 4460.
+	 * DCC is required, if more than a certain frequency is required.
+	 * For, 4460 > 1GHZ.
+	 *     5430 > 1.4GHZ.
+	 */
+	if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
+		mpu_dpll_regs =
+			(struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
+		bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
+		clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
+			MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
+		setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
+			MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
+		clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
+			CM_CLKSEL_DCC_EN_MASK);
+	}
+
+	params = get_mpu_dpll_params(*dplls_data);
+
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
+	debug("MPU DPLL locked\n");
+}
+
+#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
+static void setup_usb_dpll(void)
+{
+	const struct dpll_params *params;
+	u32 sys_clk_khz, sd_div, num, den;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+	/*
+	 * USB:
+	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+	 *      - where CLKINP is sys_clk in MHz
+	 * Use CLKINP in KHz and adjust the denominator accordingly so
+	 * that we have enough accuracy and at the same time no overflow
+	 */
+	params = get_usb_dpll_params(*dplls_data);
+	num = params->m * sys_clk_khz;
+	den = (params->n + 1) * 250 * 1000;
+	num += den - 1;
+	sd_div = num / den;
+	clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
+			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
+			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
+
+	/* Now setup the dpll with the regular function */
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
+}
+#endif
+
+static void setup_dplls(void)
+{
+	u32 temp;
+	const struct dpll_params *params;
+
+	debug("setup_dplls\n");
+
+	/* CORE dpll */
+	params = get_core_dpll_params(*dplls_data);	/* default - safest */
+	/*
+	 * Do not lock the core DPLL now. Just set it up.
+	 * Core DPLL will be locked after setting up EMIF
+	 * using the FREQ_UPDATE method(freq_update_core())
+	 */
+	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+		do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
+							DPLL_NO_LOCK, "core");
+	else
+		do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
+							DPLL_LOCK, "core");
+	/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
+	temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
+	    (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
+	    (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
+	writel(temp, (*prcm)->cm_clksel_core);
+	debug("Core DPLL configured\n");
+
+	/* lock PER dpll */
+	params = get_per_dpll_params(*dplls_data);
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
+			params, DPLL_LOCK, "per");
+	debug("PER DPLL locked\n");
+
+	/* MPU dpll */
+	configure_mpu_dpll();
+
+#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
+	setup_usb_dpll();
+#endif
+	params = get_ddr_dpll_params(*dplls_data);
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
+		      params, DPLL_LOCK, "ddr");
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+	params = get_gmac_dpll_params(*dplls_data);
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
+		      DPLL_LOCK, "gmac");
+#endif
+}
+
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
+{
+	u32 offset_code;
+
+	volt_offset -= pmic->base_offset;
+
+	offset_code = (volt_offset + pmic->step - 1) / pmic->step;
+
+	/*
+	 * Offset codes 1-6 all give the base voltage in Palmas
+	 * Offset code 0 switches OFF the SMPS
+	 */
+	return offset_code + pmic->start_code;
+}
+
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
+{
+	u32 offset_code;
+	u32 offset = volt_mv;
+	int ret = 0;
+
+	if (!volt_mv)
+		return;
+
+	pmic->pmic_bus_init();
+	/* See if we can first get the GPIO if needed */
+	if (pmic->gpio_en)
+		ret = gpio_request(pmic->gpio, "PMIC_GPIO");
+
+	if (ret < 0) {
+		printf("%s: gpio %d request failed %d\n", __func__,
+							pmic->gpio, ret);
+		return;
+	}
+
+	/* Pull the GPIO low to select SET0 register, while we program SET1 */
+	if (pmic->gpio_en)
+		gpio_direction_output(pmic->gpio, 0);
+
+	/* convert to uV for better accuracy in the calculations */
+	offset *= 1000;
+
+	offset_code = get_offset_code(offset, pmic);
+
+	debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
+		offset_code);
+
+	if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
+		printf("Scaling voltage failed for 0x%x\n", vcore_reg);
+
+	if (pmic->gpio_en)
+		gpio_direction_output(pmic->gpio, 1);
+}
+
+static u32 optimize_vcore_voltage(struct volts const *v)
+{
+	u32 val;
+	if (!v->value)
+		return 0;
+	if (!v->efuse.reg)
+		return v->value;
+
+	switch (v->efuse.reg_bits) {
+	case 16:
+		val = readw(v->efuse.reg);
+		break;
+	case 32:
+		val = readl(v->efuse.reg);
+		break;
+	default:
+		printf("Error: efuse 0x%08x bits=%d unknown\n",
+		       v->efuse.reg, v->efuse.reg_bits);
+		return v->value;
+	}
+
+	if (!val) {
+		printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
+		       v->efuse.reg, v->efuse.reg_bits, v->value);
+		return v->value;
+	}
+
+	debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
+	      __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
+	return val;
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+void scale_vcores(struct vcores_data const *vcores)
+{
+	u32 val;
+
+	val = optimize_vcore_voltage(&vcores->core);
+	do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
+
+	val = optimize_vcore_voltage(&vcores->mpu);
+	do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
+
+	/* Configure MPU ABB LDO after scale */
+	abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+		  (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
+		  (*prcm)->prm_abbldo_mpu_setup,
+		  (*prcm)->prm_abbldo_mpu_ctrl,
+		  (*prcm)->prm_irqstatus_mpu_2,
+		  OMAP_ABB_MPU_TXDONE_MASK,
+		  OMAP_ABB_FAST_OPP);
+
+	val = optimize_vcore_voltage(&vcores->mm);
+	do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
+
+	val = optimize_vcore_voltage(&vcores->gpu);
+	do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
+
+	val = optimize_vcore_voltage(&vcores->eve);
+	do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
+
+	val = optimize_vcore_voltage(&vcores->iva);
+	do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
+}
+
+static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
+{
+	clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
+			enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
+	debug("Enable clock domain - %x\n", clkctrl_reg);
+}
+
+static inline void wait_for_clk_enable(u32 clkctrl_addr)
+{
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+	u32 bound = LDELAY;
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+
+		clkctrl = readl(clkctrl_addr);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+		if (--bound == 0) {
+			printf("Clock enable failed for 0x%x idlest 0x%x\n",
+				clkctrl_addr, clkctrl);
+			return;
+		}
+	}
+}
+
+static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
+				u32 wait_for_enable)
+{
+	clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
+			enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
+	debug("Enable clock module - %x\n", clkctrl_addr);
+	if (wait_for_enable)
+		wait_for_clk_enable(clkctrl_addr);
+}
+
+void freq_update_core(void)
+{
+	u32 freq_config1 = 0;
+	const struct dpll_params *core_dpll_params;
+	u32 omap_rev = omap_revision();
+
+	core_dpll_params = get_core_dpll_params(*dplls_data);
+	/* Put EMIF clock domain in sw wakeup mode */
+	enable_clock_domain((*prcm)->cm_memif_clkstctrl,
+				CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
+	wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
+
+	freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
+	    SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
+
+	freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
+				SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
+
+	freq_config1 |= (core_dpll_params->m2 <<
+			SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
+			SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
+
+	writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
+	if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
+			(u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
+		puts("FREQ UPDATE procedure failed!!");
+		hang();
+	}
+
+	/*
+	 * Putting EMIF in HW_AUTO is seen to be causing issues with
+	 * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
+	 * in OMAP5430 ES1.0 silicon
+	 */
+	if (omap_rev != OMAP5430_ES1_0) {
+		/* Put EMIF clock domain back in hw auto mode */
+		enable_clock_domain((*prcm)->cm_memif_clkstctrl,
+					CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+		wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
+		wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
+	}
+}
+
+void bypass_dpll(u32 const base)
+{
+	do_bypass_dpll(base);
+	wait_for_bypass(base);
+}
+
+void lock_dpll(u32 const base)
+{
+	do_lock_dpll(base);
+	wait_for_lock(base);
+}
+
+void setup_clocks_for_console(void)
+{
+	/* Do not add any spl_debug prints in this function */
+	clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+
+	/* Enable all UARTs - console will be on one of them */
+	clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
+			MODULE_CLKCTRL_MODULEMODE_MASK,
+			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
+			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+			CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
+			CD_CLKCTRL_CLKTRCTRL_SHIFT);
+}
+
+void do_enable_clocks(u32 const *clk_domains,
+			    u32 const *clk_modules_hw_auto,
+			    u32 const *clk_modules_explicit_en,
+			    u8 wait_for_enable)
+{
+	u32 i, max = 100;
+
+	/* Put the clock domains in SW_WKUP mode */
+	for (i = 0; (i < max) && clk_domains[i]; i++) {
+		enable_clock_domain(clk_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
+	}
+
+	/* Clock modules that need to be put in HW_AUTO */
+	for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
+		enable_clock_module(clk_modules_hw_auto[i],
+				    MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
+				    wait_for_enable);
+	};
+
+	/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
+	for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+		enable_clock_module(clk_modules_explicit_en[i],
+				    MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
+				    wait_for_enable);
+	};
+
+	/* Put the clock domains in HW_AUTO mode now */
+	for (i = 0; (i < max) && clk_domains[i]; i++) {
+		enable_clock_domain(clk_domains[i],
+				    CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+	}
+}
+
+void prcm_init(void)
+{
+	switch (omap_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		enable_basic_clocks();
+		timer_init();
+		scale_vcores(*omap_vcores);
+		setup_dplls();
+		setup_warmreset_time();
+		break;
+	default:
+		break;
+	}
+
+	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
+		enable_basic_uboot_clocks();
+}
+
+void gpi2c_init(void)
+{
+	static int gpi2c = 1;
+
+	if (gpi2c) {
+		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE);
+		gpi2c = 0;
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/emif-common.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/emif-common.c
new file mode 100644
index 000000000..429c4becf
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -0,0 +1,1392 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/emif.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/utils.h>
+#include <linux/compiler.h>
+
+static int emif1_enabled = -1, emif2_enabled = -1;
+
+void set_lpmode_selfrefresh(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 reg;
+
+	reg = readl(&emif->emif_pwr_mgmt_ctrl);
+	reg &= ~EMIF_REG_LP_MODE_MASK;
+	reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
+	reg &= ~EMIF_REG_SR_TIM_MASK;
+	writel(reg, &emif->emif_pwr_mgmt_ctrl);
+
+	/* dummy read for the new SR_TIM to be loaded */
+	readl(&emif->emif_pwr_mgmt_ctrl);
+}
+
+void force_emif_self_refresh()
+{
+	set_lpmode_selfrefresh(EMIF1_BASE);
+	set_lpmode_selfrefresh(EMIF2_BASE);
+}
+
+inline u32 emif_num(u32 base)
+{
+	if (base == EMIF1_BASE)
+		return 1;
+	else if (base == EMIF2_BASE)
+		return 2;
+	else
+		return 0;
+}
+
+static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	if (omap_revision() == OMAP4430_ES2_0)
+		mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
+	else
+		mr = readl(&emif->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
+	      cs, mr_addr, mr);
+	if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
+	    ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+	    ((mr & 0xff000000) >> 24) == (mr & 0xff))
+		return mr & 0xff;
+	else
+		return mr;
+}
+
+static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
+}
+
+void emif_reset_phy(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 iodft;
+
+	iodft = readl(&emif->emif_iodft_tlgc);
+	iodft |= EMIF_REG_RESET_PHY_MASK;
+	writel(iodft, &emif->emif_iodft_tlgc);
+}
+
+static void do_lpddr2_init(u32 base, u32 cs)
+{
+	u32 mr_addr;
+	const struct lpddr2_mr_regs *mr_regs;
+
+	get_lpddr2_mr_regs(&mr_regs);
+	/* Wait till device auto initialization is complete */
+	while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
+	/*
+	 * tZQINIT = 1 us
+	 * Enough loops assuming a maximum of 2GHz
+	 */
+
+	sdelay(2000);
+
+	set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
+	set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
+
+	/*
+	 * Enable refresh along with writing MR2
+	 * Encoding of RL in MR2 is (RL - 2)
+	 */
+	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+	set_mr(base, cs, mr_addr, mr_regs->mr2);
+
+	if (mr_regs->mr3 > 0)
+		set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
+}
+
+static void lpddr2_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/* Not NVM */
+	clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
+
+	/*
+	 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
+	 * when EMIF_SDRAM_CONFIG register is written
+	 */
+	setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
+
+	/*
+	 * Set the SDRAM_CONFIG and PHY_CTRL for the
+	 * un-locked frequency & default RL
+	 */
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+	do_ext_phy_settings(base, regs);
+
+	do_lpddr2_init(base, CS0);
+	if (regs->sdram_config & EMIF_REG_EBANK_MASK)
+		do_lpddr2_init(base, CS1);
+
+	writel(regs->sdram_config, &emif->emif_sdram_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+
+	/* Enable refresh now */
+	clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
+
+	}
+
+__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+}
+
+void emif_update_timings(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
+	if (omap_revision() == OMAP4430_ES1_0) {
+		/* ES1 bug EMIF should be in force idle during freq_update */
+		writel(0, &emif->emif_pwr_mgmt_ctrl);
+	} else {
+		writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
+		writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
+	}
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
+	writel(regs->zq_config, &emif->emif_zq_config);
+	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+
+	if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
+			&emif->emif_l3_config);
+	} else if (omap_revision() >= OMAP4460_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+			&emif->emif_l3_config);
+	} else {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
+			&emif->emif_l3_config);
+	}
+}
+
+static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/* keep sdram in self-refresh */
+	writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
+		& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+	__udelay(130);
+
+	/*
+	 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
+	 * Invert clock adds an additional half cycle delay on the
+	 * command interface.  The additional half cycle, is usually
+	 * meant to enable leveling in the situation that DQS is later
+	 * than CK on the board.It also helps provide some additional
+	 * margin for leveling.
+	 */
+	writel(regs->emif_ddr_phy_ctlr_1,
+	       &emif->emif_ddr_phy_ctrl_1);
+
+	writel(regs->emif_ddr_phy_ctlr_1,
+	       &emif->emif_ddr_phy_ctrl_1_shdw);
+	__udelay(130);
+
+	writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
+	       & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+
+	/* Launch Full leveling */
+	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+	/* Wait till full leveling is complete */
+	readl(&emif->emif_rd_wr_lvl_ctl);
+	      __udelay(130);
+
+	/* Read data eye leveling no of samples */
+	config_data_eye_leveling_samples(base);
+
+	/*
+	 * Launch 8 incremental WR_LVL- to compensate for
+	 * PHY limitation.
+	 */
+	writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
+	       &emif->emif_rd_wr_lvl_ctl);
+
+	__udelay(130);
+
+	/* Launch Incremental leveling */
+	writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
+	       __udelay(130);
+}
+
+static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	u32 fifo_reg;
+
+	fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
+	writel(fifo_reg | 0x00000100,
+	       &emif->emif_ddr_fifo_misaligned_clear_1);
+
+	fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
+	writel(fifo_reg | 0x00000100,
+	       &emif->emif_ddr_fifo_misaligned_clear_2);
+
+	/* Launch Full leveling */
+	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+	/* Wait till full leveling is complete */
+	readl(&emif->emif_rd_wr_lvl_ctl);
+	      __udelay(130);
+
+	/* Read data eye leveling no of samples */
+	config_data_eye_leveling_samples(base);
+
+	/*
+	 * Disable leveling. This is because if leveling is kept
+	 * enabled, then PHY triggers a false leveling during
+	 * EMIF-idle scenario which results in wrong delay
+	 * values getting updated. After this the EMIF becomes
+	 * unaccessible. So disable it after the first time
+	 */
+	writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
+}
+
+static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+	if (is_omap54xx())
+		omap5_ddr3_leveling(base, regs);
+	else
+		dra7_ddr3_leveling(base, regs);
+}
+
+static void ddr3_init(u32 base, const struct emif_regs *regs)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	/*
+	 * Set SDRAM_CONFIG and PHY control registers to locked frequency
+	 * and RL =7. As the default values of the Mode Registers are not
+	 * defined, contents of mode Registers must be fully initialized.
+	 * H/W takes care of this initialization
+	 */
+	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+	/* Update timing registers */
+	writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
+	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
+	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
+
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+
+	/*
+	 * The same sequence should work on OMAP5432 as well. But strange that
+	 * it is not working
+	 */
+	if (is_dra7xx()) {
+		do_ext_phy_settings(base, regs);
+		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+		writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	} else {
+		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+		writel(regs->sdram_config_init, &emif->emif_sdram_config);
+		do_ext_phy_settings(base, regs);
+	}
+
+	/* enable leveling */
+	writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+
+	ddr3_leveling(base, regs);
+}
+
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+
+/*
+ * Organization and refresh requirements for LPDDR2 devices of different
+ * types and densities. Derived from JESD209-2 section 2.4
+ */
+const struct lpddr2_addressing addressing_table[] = {
+	/* Banks tREFIx10     rowx32,rowx16      colx32,colx16	density */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
+	{BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
+	{BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
+	{BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
+	{BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
+	{BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
+	{BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
+	{BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
+};
+
+static const u32 lpddr2_density_2_size_in_mbytes[] = {
+	8,			/* 64Mb */
+	16,			/* 128Mb */
+	32,			/* 256Mb */
+	64,			/* 512Mb */
+	128,			/* 1Gb   */
+	256,			/* 2Gb   */
+	512,			/* 4Gb   */
+	1024,			/* 8Gb   */
+	2048,			/* 16Gb  */
+	4096			/* 32Gb  */
+};
+
+/*
+ * Calculate the period of DDR clock from frequency value and set the
+ * denominator and numerator in global variables for easy access later
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+	/*
+	 * period = 1/freq
+	 * period_in_ns = 10^9/freq
+	 */
+	*T_num = 1000000000;
+	*T_den = freq;
+	cancel_out(T_num, T_den, 200);
+
+}
+
+/*
+ * Convert time in nano seconds to number of cycles of DDR clock
+ */
+static inline u32 ns_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
+}
+
+/*
+ * ns_2_cycles with the difference that the time passed is 2 times the actual
+ * value(to avoid fractions). The cycles returned is for the original value of
+ * the timing parameter
+ */
+static inline u32 ns_x2_2_cycles(u32 ns)
+{
+	return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
+}
+
+/*
+ * Find addressing table index based on the device's type(S2 or S4) and
+ * density
+ */
+s8 addressing_table_index(u8 type, u8 density, u8 width)
+{
+	u8 index;
+	if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
+		return -1;
+
+	/*
+	 * Look at the way ADDR_TABLE_INDEX* values have been defined
+	 * in emif.h compared to LPDDR2_DENSITY_* values
+	 * The table is layed out in the increasing order of density
+	 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
+	 * at the end
+	 */
+	if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
+		index = ADDR_TABLE_INDEX1GS2;
+	else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
+		index = ADDR_TABLE_INDEX2GS2;
+	else
+		index = density;
+
+	debug("emif: addressing table index %d\n", index);
+
+	return index;
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_ac_timings *get_timings_table(const struct
+			lpddr2_ac_timings const *const *device_timings,
+			u32 freq)
+{
+	u32 i, temp, freq_nearest;
+	const struct lpddr2_ac_timings *timings = 0;
+
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+	emif_assert(device_timings);
+
+	/*
+	 * Start with the maximum allowed frequency - that is always safe
+	 */
+	freq_nearest = MAX_LPDDR2_FREQ;
+	/*
+	 * Find the timings table that has the max frequency value:
+	 *   i.  Above or equal to the DDR frequency - safe
+	 *   ii. The lowest that satisfies condition (i) - optimal
+	 */
+	for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
+		temp = device_timings[i]->max_freq;
+		if ((temp >= freq) && (temp <= freq_nearest)) {
+			freq_nearest = temp;
+			timings = device_timings[i];
+		}
+	}
+	debug("emif: timings table: %d\n", freq_nearest);
+	return timings;
+}
+
+/*
+ * Finds the value of emif_sdram_config_reg
+ * All parameters are programmed based on the device on CS0.
+ * If there is a device on CS1, it will be same as that on CS0 or
+ * it will be NVM. We don't support NVM yet.
+ * If cs1_device pointer is NULL it is assumed that there is no device
+ * on CS1
+ */
+static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
+				const struct lpddr2_device_details *cs1_device,
+				const struct lpddr2_addressing *addressing,
+				u8 RL)
+{
+	u32 config_reg = 0;
+
+	config_reg |=  (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
+	config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
+			EMIF_REG_IBANK_POS_SHIFT;
+
+	config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
+
+	config_reg |= RL << EMIF_REG_CL_SHIFT;
+
+	config_reg |= addressing->row_sz[cs0_device->io_width] <<
+			EMIF_REG_ROWSIZE_SHIFT;
+
+	config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
+
+	config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
+			EMIF_REG_EBANK_SHIFT;
+
+	config_reg |= addressing->col_sz[cs0_device->io_width] <<
+			EMIF_REG_PAGESIZE_SHIFT;
+
+	return config_reg;
+}
+
+static u32 get_sdram_ref_ctrl(u32 freq,
+			      const struct lpddr2_addressing *addressing)
+{
+	u32 ref_ctrl = 0, val = 0, freq_khz;
+	freq_khz = freq / 1000;
+	/*
+	 * refresh rate to be set is 'tREFI * freq in MHz
+	 * division by 10000 to account for khz and x10 in t_REFI_us_x10
+	 */
+	val = addressing->t_REFI_us_x10 * freq_khz / 10000;
+	ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
+
+	return ref_ctrl;
+}
+
+static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+	val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
+	tim1 |= val << EMIF_REG_T_WTR_SHIFT;
+
+	if (addressing->num_banks == BANKS8)
+		val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
+							(4 * (*T_num)) - 1;
+	else
+		val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
+
+	tim1 |= val << EMIF_REG_T_RRD_SHIFT;
+
+	val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
+	tim1 |= val << EMIF_REG_T_RC_SHIFT;
+
+	val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
+	tim1 |= val << EMIF_REG_T_RAS_SHIFT;
+
+	val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
+	tim1 |= val << EMIF_REG_T_WR_SHIFT;
+
+	val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
+	tim1 |= val << EMIF_REG_T_RCD_SHIFT;
+
+	val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
+	tim1 |= val << EMIF_REG_T_RP_SHIFT;
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck)
+{
+	u32 tim2 = 0, val = 0;
+	val = max(min_tck->tCKE, timings->tCKE) - 1;
+	tim2 |= val << EMIF_REG_T_CKE_SHIFT;
+
+	val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
+	tim2 |= val << EMIF_REG_T_RTP_SHIFT;
+
+	/*
+	 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
+	 * same value
+	 */
+	val = ns_2_cycles(timings->tXSR) - 1;
+	tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
+	tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
+
+	val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
+	tim2 |= val << EMIF_REG_T_XP_SHIFT;
+
+	return tim2;
+}
+
+static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
+			       const struct lpddr2_min_tck *min_tck,
+			       const struct lpddr2_addressing *addressing)
+{
+	u32 tim3 = 0, val = 0;
+	val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
+	tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
+
+	val = ns_2_cycles(timings->tRFCab) - 1;
+	tim3 |= val << EMIF_REG_T_RFC_SHIFT;
+
+	val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
+	tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
+
+	val = ns_2_cycles(timings->tZQCS) - 1;
+	tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
+
+	val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
+	tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
+
+	return tim3;
+}
+
+static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
+			     const struct lpddr2_addressing *addressing,
+			     u8 volt_ramp)
+{
+	u32 zq = 0, val = 0;
+	if (volt_ramp)
+		val =
+		    EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	else
+		val =
+		    EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
+		    addressing->t_REFI_us_x10;
+	zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
+
+	zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
+
+	zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
+
+	zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
+
+	/*
+	 * Assuming that two chipselects have a single calibration resistor
+	 * If there are indeed two calibration resistors, then this flag should
+	 * be enabled to take advantage of dual calibration feature.
+	 * This data should ideally come from board files. But considering
+	 * that none of the boards today have calibration resistors per CS,
+	 * it would be an unnecessary overhead.
+	 */
+	zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
+
+	zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
+
+	zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
+
+	return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
+				 const struct lpddr2_addressing *addressing,
+				 u8 is_derated)
+{
+	u32 alert = 0, interval;
+	interval =
+	    TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
+	if (is_derated)
+		interval *= 4;
+	alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
+
+	alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
+
+	alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
+
+	alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
+
+	alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
+
+	alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
+
+	return alert;
+}
+
+static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
+{
+	u32 idle = 0, val = 0;
+	if (volt_ramp)
+		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
+	else
+		/*Maximum value in normal conditions - suggested by hw team */
+		val = 0x1FF;
+	idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
+
+	idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
+
+	return idle;
+}
+
+static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
+{
+	u32 phy = 0, val = 0;
+
+	phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
+
+	if (freq <= 100000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
+	else if (freq <= 200000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
+	else
+		val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
+	phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
+
+	/* Other fields are constant magic values. Hardcode them together */
+	phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
+		EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
+
+	return phy;
+}
+
+static u32 get_emif_mem_size(u32 base)
+{
+	u32 size_mbytes = 0, temp;
+	struct emif_device_details dev_details;
+	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+	u32 emif_nr = emif_num(base);
+
+	emif_reset_phy(base);
+	dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
+						&cs0_dev_details);
+	dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
+						&cs1_dev_details);
+	emif_reset_phy(base);
+
+	if (dev_details.cs0_device_details) {
+		temp = dev_details.cs0_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+
+	if (dev_details.cs1_device_details) {
+		temp = dev_details.cs1_device_details->density;
+		size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
+	}
+	/* convert to bytes */
+	return size_mbytes << 20;
+}
+
+/* Gets the encoding corresponding to a given DMM section size */
+u32 get_dmm_section_size_map(u32 section_size)
+{
+	/*
+	 * Section size mapping:
+	 * 0x0: 16-MiB section
+	 * 0x1: 32-MiB section
+	 * 0x2: 64-MiB section
+	 * 0x3: 128-MiB section
+	 * 0x4: 256-MiB section
+	 * 0x5: 512-MiB section
+	 * 0x6: 1-GiB section
+	 * 0x7: 2-GiB section
+	 */
+	section_size >>= 24; /* divide by 16 MB */
+	return log_2_n_round_down(section_size);
+}
+
+static void emif_calculate_regs(
+		const struct emif_device_details *emif_dev_details,
+		u32 freq, struct emif_regs *regs)
+{
+	u32 temp, sys_freq;
+	const struct lpddr2_addressing *addressing;
+	const struct lpddr2_ac_timings *timings;
+	const struct lpddr2_min_tck *min_tck;
+	const struct lpddr2_device_details *cs0_dev_details =
+					emif_dev_details->cs0_device_details;
+	const struct lpddr2_device_details *cs1_dev_details =
+					emif_dev_details->cs1_device_details;
+	const struct lpddr2_device_timings *cs0_dev_timings =
+					emif_dev_details->cs0_device_timings;
+
+	emif_assert(emif_dev_details);
+	emif_assert(regs);
+	/*
+	 * You can not have a device on CS1 without one on CS0
+	 * So configuring EMIF without a device on CS0 doesn't
+	 * make sense
+	 */
+	emif_assert(cs0_dev_details);
+	emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
+	/*
+	 * If there is a device on CS1 it should be same type as CS0
+	 * (or NVM. But NVM is not supported in this driver yet)
+	 */
+	emif_assert((cs1_dev_details == NULL) ||
+		    (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
+		    (cs0_dev_details->type == cs1_dev_details->type));
+	emif_assert(freq <= MAX_LPDDR2_FREQ);
+
+	set_ddr_clk_period(freq);
+
+	/*
+	 * The device on CS0 is used for all timing calculations
+	 * There is only one set of registers for timings per EMIF. So, if the
+	 * second CS(CS1) has a device, it should have the same timings as the
+	 * device on CS0
+	 */
+	timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
+	emif_assert(timings);
+	min_tck = cs0_dev_timings->min_tck;
+
+	temp = addressing_table_index(cs0_dev_details->type,
+				      cs0_dev_details->density,
+				      cs0_dev_details->io_width);
+
+	emif_assert((temp >= 0));
+	addressing = &(addressing_table[temp]);
+	emif_assert(addressing);
+
+	sys_freq = get_sys_clk_freq();
+
+	regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
+							cs1_dev_details,
+							addressing, RL_BOOT);
+
+	regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
+						cs1_dev_details,
+						addressing, RL_FINAL);
+
+	regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
+
+	regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
+
+	regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
+
+	regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
+
+	regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
+
+	regs->temp_alert_config =
+	    get_temp_alert_config(cs1_dev_details, addressing, 0);
+
+	regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
+					    LPDDR2_VOLTAGE_STABLE);
+
+	regs->emif_ddr_phy_ctlr_1_init =
+			get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
+
+	regs->emif_ddr_phy_ctlr_1 =
+			get_ddr_phy_ctrl_1(freq, RL_FINAL);
+
+	regs->freq = freq;
+
+	print_timing_reg(regs->sdram_config_init);
+	print_timing_reg(regs->sdram_config);
+	print_timing_reg(regs->ref_ctrl);
+	print_timing_reg(regs->sdram_tim1);
+	print_timing_reg(regs->sdram_tim2);
+	print_timing_reg(regs->sdram_tim3);
+	print_timing_reg(regs->read_idle_ctrl);
+	print_timing_reg(regs->temp_alert_config);
+	print_timing_reg(regs->zq_config);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1);
+	print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
+}
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+const char *get_lpddr2_type(u8 type_id)
+{
+	switch (type_id) {
+	case LPDDR2_TYPE_S4:
+		return "LPDDR2-S4";
+	case LPDDR2_TYPE_S2:
+		return "LPDDR2-S2";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_io_width(u8 width_id)
+{
+	switch (width_id) {
+	case LPDDR2_IO_WIDTH_8:
+		return "x8";
+	case LPDDR2_IO_WIDTH_16:
+		return "x16";
+	case LPDDR2_IO_WIDTH_32:
+		return "x32";
+	default:
+		return NULL;
+	}
+}
+
+const char *get_lpddr2_manufacturer(u32 manufacturer)
+{
+	switch (manufacturer) {
+	case LPDDR2_MANUFACTURER_SAMSUNG:
+		return "Samsung";
+	case LPDDR2_MANUFACTURER_QIMONDA:
+		return "Qimonda";
+	case LPDDR2_MANUFACTURER_ELPIDA:
+		return "Elpida";
+	case LPDDR2_MANUFACTURER_ETRON:
+		return "Etron";
+	case LPDDR2_MANUFACTURER_NANYA:
+		return "Nanya";
+	case LPDDR2_MANUFACTURER_HYNIX:
+		return "Hynix";
+	case LPDDR2_MANUFACTURER_MOSEL:
+		return "Mosel";
+	case LPDDR2_MANUFACTURER_WINBOND:
+		return "Winbond";
+	case LPDDR2_MANUFACTURER_ESMT:
+		return "ESMT";
+	case LPDDR2_MANUFACTURER_SPANSION:
+		return "Spansion";
+	case LPDDR2_MANUFACTURER_SST:
+		return "SST";
+	case LPDDR2_MANUFACTURER_ZMOS:
+		return "ZMOS";
+	case LPDDR2_MANUFACTURER_INTEL:
+		return "Intel";
+	case LPDDR2_MANUFACTURER_NUMONYX:
+		return "Numonyx";
+	case LPDDR2_MANUFACTURER_MICRON:
+		return "Micron";
+	default:
+		return NULL;
+	}
+}
+
+static void display_sdram_details(u32 emif_nr, u32 cs,
+				  struct lpddr2_device_details *device)
+{
+	const char *mfg_str;
+	const char *type_str;
+	char density_str[10];
+	u32 density;
+
+	debug("EMIF%d CS%d\t", emif_nr, cs);
+
+	if (!device) {
+		debug("None\n");
+		return;
+	}
+
+	mfg_str = get_lpddr2_manufacturer(device->manufacturer);
+	type_str = get_lpddr2_type(device->type);
+
+	density = lpddr2_density_2_size_in_mbytes[device->density];
+	if ((density / 1024 * 1024) == density) {
+		density /= 1024;
+		sprintf(density_str, "%d GB", density);
+	} else
+		sprintf(density_str, "%d MB", density);
+	if (mfg_str && type_str)
+		debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+}
+
+static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
+				  struct lpddr2_device_details *lpddr2_device)
+{
+	u32 mr = 0, temp;
+
+	mr = get_mr(base, cs, LPDDR2_MR0);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
+	if (temp) {
+		/* Not SDRAM */
+		return 0;
+	}
+	temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
+
+	if (temp) {
+		/* DNV supported - But DNV is only supported for NVM */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR4);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR5);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	if (!get_lpddr2_manufacturer(mr)) {
+		/* Manufacturer not identified */
+		return 0;
+	}
+	lpddr2_device->manufacturer = mr;
+
+	mr = get_mr(base, cs, LPDDR2_MR6);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR7);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR8);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
+	if (!get_lpddr2_type(temp)) {
+		/* Not SDRAM */
+		return 0;
+	}
+	lpddr2_device->type = temp;
+
+	temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
+	if (temp > LPDDR2_DENSITY_32Gb) {
+		/* Density not supported */
+		return 0;
+	}
+	lpddr2_device->density = temp;
+
+	temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
+	if (!get_lpddr2_io_width(temp)) {
+		/* IO width unsupported value */
+		return 0;
+	}
+	lpddr2_device->io_width = temp;
+
+	/*
+	 * If all the above tests pass we should
+	 * have a device on this chip-select
+	 */
+	return 1;
+}
+
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
+{
+	u32 phy;
+	u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
+
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	if (!lpddr2_dev_details)
+		return NULL;
+
+	/* Do the minimum init for mode register accesses */
+	if (!(running_from_sdram() || warm_reset())) {
+		phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
+		writel(phy, &emif->emif_ddr_phy_ctrl_1);
+	}
+
+	if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
+		return NULL;
+
+	display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
+
+	return lpddr2_dev_details;
+}
+#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
+
+static void do_sdram_init(u32 base)
+{
+	const struct emif_regs *regs;
+	u32 in_sdram, emif_nr;
+
+	debug(">>do_sdram_init() %x\n", base);
+
+	in_sdram = running_from_sdram();
+	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+	emif_get_reg_dump(emif_nr, &regs);
+	if (!regs) {
+		debug("EMIF: reg dump not provided\n");
+		return;
+	}
+#else
+	/*
+	 * The user has not provided the register values. We need to
+	 * calculate it based on the timings and the DDR frequency
+	 */
+	struct emif_device_details dev_details;
+	struct emif_regs calculated_regs;
+
+	/*
+	 * Get device details:
+	 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
+	 * - Obtained from user otherwise
+	 */
+	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+	emif_reset_phy(base);
+	dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
+						&cs0_dev_details);
+	dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
+						&cs1_dev_details);
+	emif_reset_phy(base);
+
+	/* Return if no devices on this EMIF */
+	if (!dev_details.cs0_device_details &&
+	    !dev_details.cs1_device_details) {
+		return;
+	}
+
+	/*
+	 * Get device timings:
+	 * - Default timings specified by JESD209-2 if
+	 *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
+	 * - Obtained from user otherwise
+	 */
+	emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
+				&dev_details.cs1_device_timings);
+
+	/* Calculate the register values */
+	emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
+	regs = &calculated_regs;
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+	/*
+	 * Initializing the LPDDR2 device can not happen from SDRAM.
+	 * Changing the timing registers in EMIF can happen(going from one
+	 * OPP to another)
+	 */
+	if (!(in_sdram || warm_reset())) {
+		if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+			lpddr2_init(base, regs);
+		else
+			ddr3_init(base, regs);
+	}
+	if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+		set_lpmode_selfrefresh(base);
+		emif_reset_phy(base);
+		ddr3_leveling(base, regs);
+	}
+
+	/* Write to the shadow registers */
+	emif_update_timings(base, regs);
+
+	debug("<<do_sdram_init() %x\n", base);
+}
+
+void emif_post_init_config(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 omap_rev = omap_revision();
+
+	/* reset phy on ES2.0 */
+	if (omap_rev == OMAP4430_ES2_0)
+		emif_reset_phy(base);
+
+	/* Put EMIF back in smart idle on ES1.0 */
+	if (omap_rev == OMAP4430_ES1_0)
+		writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
+}
+
+void dmm_init(u32 base)
+{
+	const struct dmm_lisa_map_regs *lisa_map_regs;
+	u32 i, section, valid;
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+	emif_get_dmm_regs(&lisa_map_regs);
+#else
+	u32 emif1_size, emif2_size, mapped_size, section_map = 0;
+	u32 section_cnt, sys_addr;
+	struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
+
+	mapped_size = 0;
+	section_cnt = 3;
+	sys_addr = CONFIG_SYS_SDRAM_BASE;
+	emif1_size = get_emif_mem_size(EMIF1_BASE);
+	emif2_size = get_emif_mem_size(EMIF2_BASE);
+	debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
+
+	if (!emif1_size && !emif2_size)
+		return;
+
+	/* symmetric interleaved section */
+	if (emif1_size && emif2_size) {
+		mapped_size = min(emif1_size, emif2_size);
+		section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
+		section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= (sys_addr >> 24) <<
+				EMIF_SYS_ADDR_SHIFT;
+		section_map |= get_dmm_section_size_map(mapped_size * 2)
+				<< EMIF_SYS_SIZE_SHIFT;
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		emif1_size -= mapped_size;
+		emif2_size -= mapped_size;
+		sys_addr += (mapped_size * 2);
+		section_cnt--;
+	}
+
+	/*
+	 * Single EMIF section(we can have a maximum of 1 single EMIF
+	 * section- either EMIF1 or EMIF2 or none, but not both)
+	 */
+	if (emif1_size) {
+		section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
+		section_map |= get_dmm_section_size_map(emif1_size)
+				<< EMIF_SYS_SIZE_SHIFT;
+		/* only MSB */
+		section_map |= (mapped_size >> 24) <<
+				EMIF_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
+		section_cnt--;
+	}
+	if (emif2_size) {
+		section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
+		section_map |= get_dmm_section_size_map(emif2_size) <<
+				EMIF_SYS_SIZE_SHIFT;
+		/* only MSB */
+		section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
+		/* only MSB */
+		section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
+		section_cnt--;
+	}
+
+	if (section_cnt == 2) {
+		/* Only 1 section - either symmetric or single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_2 = 0;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	} else {
+		/* 2 sections - 1 symmetric, 1 single EMIF */
+		lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
+		lis_map_regs_calculated.dmm_lisa_map_1 = 0;
+	}
+
+	/* TRAP for invalid TILER mappings in section 0 */
+	lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
+
+	if (omap_revision() >= OMAP4460_ES1_0)
+		lis_map_regs_calculated.is_ma_present = 1;
+
+	lisa_map_regs = &lis_map_regs_calculated;
+#endif
+	struct dmm_lisa_map_regs *hw_lisa_map_regs =
+	    (struct dmm_lisa_map_regs *)base;
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(lisa_map_regs->dmm_lisa_map_3,
+		&hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(lisa_map_regs->dmm_lisa_map_2,
+		&hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(lisa_map_regs->dmm_lisa_map_1,
+		&hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(lisa_map_regs->dmm_lisa_map_0,
+		&hw_lisa_map_regs->dmm_lisa_map_0);
+
+	if (lisa_map_regs->is_ma_present) {
+		hw_lisa_map_regs =
+		    (struct dmm_lisa_map_regs *)MA_BASE;
+
+		writel(lisa_map_regs->dmm_lisa_map_3,
+			&hw_lisa_map_regs->dmm_lisa_map_3);
+		writel(lisa_map_regs->dmm_lisa_map_2,
+			&hw_lisa_map_regs->dmm_lisa_map_2);
+		writel(lisa_map_regs->dmm_lisa_map_1,
+			&hw_lisa_map_regs->dmm_lisa_map_1);
+		writel(lisa_map_regs->dmm_lisa_map_0,
+			&hw_lisa_map_regs->dmm_lisa_map_0);
+	}
+
+	/*
+	 * EMIF should be configured only when
+	 * memory is mapped on it. Using emif1_enabled
+	 * and emif2_enabled variables for this.
+	 */
+	emif1_enabled = 0;
+	emif2_enabled = 0;
+	for (i = 0; i < 4; i++) {
+		section	= __raw_readl(DMM_BASE + i*4);
+		valid = (section & EMIF_SDRC_MAP_MASK) >>
+			(EMIF_SDRC_MAP_SHIFT);
+		if (valid == 3) {
+			emif1_enabled = 1;
+			emif2_enabled = 1;
+			break;
+		} else if (valid == 1) {
+			emif1_enabled = 1;
+		} else if (valid == 2) {
+			emif2_enabled = 1;
+		}
+	}
+
+}
+
+static void do_bug0039_workaround(u32 base)
+{
+	u32 val, i, clkctrl;
+	struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
+	const struct read_write_regs *bug_00339_regs;
+	u32 iterations;
+	u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
+	u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
+
+	if (is_dra7xx())
+		phy_status_base++;
+
+	bug_00339_regs = get_bug_regs(&iterations);
+
+	/* Put EMIF in to idle */
+	clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
+	__raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
+
+	/* Copy the phy status registers in to phy ctrl shadow registers */
+	for (i = 0; i < iterations; i++) {
+		val = __raw_readl(phy_status_base +
+				  bug_00339_regs[i].read_reg - 1);
+
+		__raw_writel(val, phy_ctrl_base +
+			     ((bug_00339_regs[i].write_reg - 1) << 1));
+
+		__raw_writel(val, phy_ctrl_base +
+			     (bug_00339_regs[i].write_reg << 1) - 1);
+	}
+
+	/* Disable leveling */
+	writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
+
+	__raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
+}
+
+/*
+ * SDRAM initialization:
+ * SDRAM initialization has two parts:
+ * 1. Configuring the SDRAM device
+ * 2. Update the AC timings related parameters in the EMIF module
+ * (1) should be done only once and should not be done while we are
+ * running from SDRAM.
+ * (2) can and should be done more than once if OPP changes.
+ * Particularly, this may be needed when we boot without SPL and
+ * and using Configuration Header(CH). ROM code supports only at 50% OPP
+ * at boot (low power boot). So u-boot has to switch to OPP100 and update
+ * the frequency. So,
+ * Doing (1) and (2) makes sense - first time initialization
+ * Doing (2) and not (1) makes sense - OPP change (when using CH)
+ * Doing (1) and not (2) doen't make sense
+ * See do_sdram_init() for the details
+ */
+void sdram_init(void)
+{
+	u32 in_sdram, size_prog, size_detect;
+	u32 sdram_type = emif_sdram_type();
+
+	debug(">>sdram_init()\n");
+
+	if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+		return;
+
+	in_sdram = running_from_sdram();
+	debug("in_sdram = %d\n", in_sdram);
+
+	if (!in_sdram) {
+		if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
+			bypass_dpll((*prcm)->cm_clkmode_dpll_core);
+		else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
+			writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
+	}
+
+	if (!in_sdram)
+		dmm_init(DMM_BASE);
+
+	if (emif1_enabled)
+		do_sdram_init(EMIF1_BASE);
+
+	if (emif2_enabled)
+		do_sdram_init(EMIF2_BASE);
+
+	if (!(in_sdram || warm_reset())) {
+		if (emif1_enabled)
+			emif_post_init_config(EMIF1_BASE);
+		if (emif2_enabled)
+			emif_post_init_config(EMIF2_BASE);
+	}
+
+	/* for the shadow registers to take effect */
+	if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+		freq_update_core();
+
+	/* Do some testing after the init */
+	if (!in_sdram) {
+		size_prog = omap_sdram_size();
+		size_prog = log_2_n_round_down(size_prog);
+		size_prog = (1 << size_prog);
+
+		size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+						size_prog);
+		/* Compare with the size programmed */
+		if (size_detect != size_prog) {
+			printf("SDRAM: identified size not same as expected"
+				" size identified: %x expected: %x\n",
+				size_detect,
+				size_prog);
+		} else
+			debug("get_ram_size() successful");
+	}
+
+	if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
+	    (!in_sdram && !warm_reset())) {
+		do_bug0039_workaround(EMIF1_BASE);
+		do_bug0039_workaround(EMIF2_BASE);
+	}
+
+	debug("<<sdram_init()\n");
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/hwinit-common.c
new file mode 100644
index 000000000..8ebc0ce25
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -0,0 +1,299 @@
+/*
+ *
+ * Common functions for OMAP4/5 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Aneesh V	<aneesh@ti.com>
+ *	Steve Sakoman	<steve@sakoman.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/sizes.h>
+#include <asm/emif.h>
+#include <asm/omap_common.h>
+#include <linux/compiler.h>
+#include <asm/cache.h>
+#include <asm/system.h>
+
+#define ARMV7_DCACHE_WRITEBACK  0xe
+#define	ARMV7_DOMAIN_CLIENT	1
+#define ARMV7_DOMAIN_MASK	(0x3 << 0)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+static void set_mux_conf_regs(void)
+{
+	switch (omap_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+		set_muxconf_regs_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		set_muxconf_regs_essential();
+		break;
+	}
+}
+
+u32 cortex_rev(void)
+{
+
+	unsigned int rev;
+
+	/* Read Main ID Register (MIDR) */
+	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
+
+	return rev;
+}
+
+static void omap_rev_string(void)
+{
+	u32 omap_rev = omap_revision();
+	u32 soc_variant	= (omap_rev & 0xF0000000) >> 28;
+	u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
+	u32 major_rev = (omap_rev & 0x00000F00) >> 8;
+	u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
+
+	if (soc_variant)
+		printf("OMAP");
+	else
+		printf("DRA");
+	printf("%x ES%x.%x\n", omap_variant, major_rev,
+	       minor_rev);
+}
+
+#ifdef CONFIG_SPL_BUILD
+void spl_display_print(void)
+{
+	omap_rev_string();
+}
+#endif
+
+void __weak srcomp_enable(void)
+{
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+/*
+ * SOC specific cpu init
+ */
+int arch_cpu_init(void)
+{
+	save_omap_boot_params();
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * Routine: s_init
+ * Description: Does early system init of watchdog, muxing,  andclocks
+ * Watchdog disable is done always. For the rest what gets done
+ * depends on the boot mode in which this function is executed
+ *   1. s_init of SPL running from SRAM
+ *   2. s_init of U-Boot running from FLASH
+ *   3. s_init of U-Boot loaded to SDRAM by SPL
+ *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
+ *	Configuration Header feature
+ * Please have a look at the respective functions to see what gets
+ * done in each of these cases
+ * This function is called with SRAM stack.
+ */
+void s_init(void)
+{
+	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	save_omap_boot_params();
+#endif
+	init_omap_revision();
+	hw_data_init();
+
+#ifdef CONFIG_SPL_BUILD
+	if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
+		force_emif_self_refresh();
+#endif
+	watchdog_init();
+	set_mux_conf_regs();
+#ifdef CONFIG_SPL_BUILD
+	srcomp_enable();
+	setup_clocks_for_console();
+
+	gd = &gdata;
+
+	preloader_console_init();
+	do_io_settings();
+#endif
+	prcm_init();
+#ifdef CONFIG_SPL_BUILD
+	/* For regular u-boot sdram_init() is called from dram_init() */
+	sdram_init();
+#endif
+}
+
+/*
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ */
+void wait_for_command_complete(struct watchdog *wd_base)
+{
+	int pending = 1;
+	do {
+		pending = readl(&wd_base->wwps);
+	} while (pending);
+}
+
+/*
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ */
+void watchdog_init(void)
+{
+	struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
+
+	writel(WD_UNLOCK1, &wd2_base->wspr);
+	wait_for_command_complete(wd2_base);
+	writel(WD_UNLOCK2, &wd2_base->wspr);
+}
+
+
+/*
+ * This function finds the SDRAM size available in the system
+ * based on DMM section configurations
+ * This is needed because the size of memory installed may be
+ * different on different versions of the board
+ */
+u32 omap_sdram_size(void)
+{
+	u32 section, i, valid;
+	u64 sdram_start = 0, sdram_end = 0, addr,
+	    size, total_size = 0, trap_size = 0;
+
+	for (i = 0; i < 4; i++) {
+		section	= __raw_readl(DMM_BASE + i*4);
+		valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
+			(EMIF_SDRC_ADDRSPC_SHIFT);
+		addr = section & EMIF_SYS_ADDR_MASK;
+
+		/* See if the address is valid */
+		if ((addr >= DRAM_ADDR_SPACE_START) &&
+		    (addr < DRAM_ADDR_SPACE_END)) {
+			size = ((section & EMIF_SYS_SIZE_MASK) >>
+				   EMIF_SYS_SIZE_SHIFT);
+			size = 1 << size;
+			size *= SZ_16M;
+
+			if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
+				if (!sdram_start || (addr < sdram_start))
+					sdram_start = addr;
+				if (!sdram_end || ((addr + size) > sdram_end))
+					sdram_end = addr + size;
+			} else {
+				trap_size = size;
+			}
+
+		}
+
+	}
+	total_size = (sdram_end - sdram_start) - (trap_size);
+
+	return total_size;
+}
+
+
+/*
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	sdram_init();
+	gd->ram_size = omap_sdram_size();
+	return 0;
+}
+
+/*
+ * Print board information
+ */
+int checkboard(void)
+{
+	puts(sysinfo.board_string);
+	return 0;
+}
+
+/*
+ *  get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+	return (readl((*ctrl)->control_status) &
+				      (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	puts("CPU  : ");
+	omap_rev_string();
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+	bd_t *bd = gd->bd;
+	int	i;
+
+	u32 start = bd->bi_dram[bank].start >> 20;
+	u32 size = bd->bi_dram[bank].size >> 20;
+	u32 end = start + size;
+
+	debug("%s: bank: %d\n", __func__, bank);
+	for (i = start; i < end; i++)
+		set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+
+}
+
+void arm_init_domains(void)
+{
+	u32 reg;
+
+	reg = get_dacr();
+	/*
+	* Set DOMAIN to client access so that all permissions
+	* set in pagetables are validated by the mmu.
+	*/
+	reg &= ~ARMV7_DOMAIN_MASK;
+	reg |= ARMV7_DOMAIN_CLIENT;
+	set_dacr(reg);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
new file mode 100644
index 000000000..86c0e4217
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -0,0 +1,32 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Aneesh V	<aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+#include <asm/arch/spl.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+	ldr	r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
+	str	r0, [r1]
+	bx	lr
+ENDPROC(save_boot_params)
+
+ENTRY(set_pl310_ctrl_reg)
+	PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
+				@ our registers
+	LDR	r12, =0x102	@ Set PL310 control register - value in R0
+	.word	0xe1600070	@ SMC #0 - hand assembled because -march=armv5
+				@ call ROM Code API to set control register
+	POP	{r4-r11, pc}
+ENDPROC(set_pl310_ctrl_reg)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/mem-common.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/mem-common.c
new file mode 100644
index 000000000..afc1bc185
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+struct gpmc *gpmc_cfg;
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+	gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+	/* global settings */
+	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
+	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
+
+	/*
+	 * Disable the GPMC0 config set by ROM code
+	 * It conflicts with our MPDB (both at 0x08000000)
+	 */
+	writel(0, &gpmc_cfg->cs[0].config7);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
new file mode 100644
index 000000000..b71d76941
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
@@ -0,0 +1,231 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <sata.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include "pipe3-phy.h"
+
+/* PLLCTRL Registers */
+#define PLL_STATUS              0x00000004
+#define PLL_GO                  0x00000008
+#define PLL_CONFIGURATION1      0x0000000C
+#define PLL_CONFIGURATION2      0x00000010
+#define PLL_CONFIGURATION3      0x00000014
+#define PLL_CONFIGURATION4      0x00000020
+
+#define PLL_REGM_MASK           0x001FFE00
+#define PLL_REGM_SHIFT          9
+#define PLL_REGM_F_MASK         0x0003FFFF
+#define PLL_REGM_F_SHIFT        0
+#define PLL_REGN_MASK           0x000001FE
+#define PLL_REGN_SHIFT          1
+#define PLL_SELFREQDCO_MASK     0x0000000E
+#define PLL_SELFREQDCO_SHIFT    1
+#define PLL_SD_MASK             0x0003FC00
+#define PLL_SD_SHIFT            10
+#define SET_PLL_GO              0x1
+#define PLL_TICOPWDN            BIT(16)
+#define PLL_LDOPWDN             BIT(15)
+#define PLL_LOCK                0x2
+#define PLL_IDLE                0x1
+
+/* PHY POWER CONTROL Register */
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK         0x003FC000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT        0xE
+
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK        0xFFC00000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT       0x16
+
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON       0x3
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF      0x0
+
+
+#define PLL_IDLE_TIME   100     /* in milliseconds */
+#define PLL_LOCK_TIME   100     /* in milliseconds */
+
+static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
+{
+	return __raw_readl(addr + offset);
+}
+
+static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
+		u32 data)
+{
+	__raw_writel(data, addr + offset);
+}
+
+static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
+									*pipe3)
+{
+	u32 rate;
+	struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
+
+	rate = get_sys_clk_freq();
+
+	for (; dpll_map->rate; dpll_map++) {
+		if (rate == dpll_map->rate)
+			return &dpll_map->params;
+	}
+
+	printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
+	       __func__, rate);
+	return NULL;
+}
+
+
+static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
+{
+	u32 val;
+	int timeout = PLL_LOCK_TIME;
+
+	do {
+		mdelay(1);
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+		if (val & PLL_LOCK)
+			break;
+	} while (--timeout);
+
+	if (!(val & PLL_LOCK)) {
+		printf("%s: DPLL failed to lock\n", __func__);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
+{
+	u32                     val;
+	struct pipe3_dpll_params *dpll_params;
+
+	dpll_params = omap_pipe3_get_dpll_params(phy);
+	if (!dpll_params) {
+		printf("%s: Invalid DPLL parameters\n", __func__);
+		return -EINVAL;
+	}
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+	val &= ~PLL_REGN_MASK;
+	val |= dpll_params->n << PLL_REGN_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+	val &= ~PLL_SELFREQDCO_MASK;
+	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+	val &= ~PLL_REGM_MASK;
+	val |= dpll_params->m << PLL_REGM_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
+	val &= ~PLL_REGM_F_MASK;
+	val |= dpll_params->mf << PLL_REGM_F_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
+	val &= ~PLL_SD_MASK;
+	val |= dpll_params->sd << PLL_SD_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
+
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
+
+	return omap_pipe3_wait_lock(phy);
+}
+
+static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
+{
+	u32 val, rate;
+
+	val = readl(phy->power_reg);
+
+	rate = get_sys_clk_freq();
+	rate = rate/1000000;
+
+	if (on) {
+		val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
+		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+		val |= rate <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+	} else {
+		val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
+		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+	}
+
+	writel(val, phy->power_reg);
+}
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy)
+{
+	int ret;
+	u32 val;
+
+	/* Program the DPLL only if not locked */
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+	if (!(val & PLL_LOCK)) {
+		ret = omap_pipe3_dpll_program(phy);
+		if (ret)
+			return ret;
+	} else {
+		/* else just bring it out of IDLE mode */
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+		if (val & PLL_IDLE) {
+			val &= ~PLL_IDLE;
+			omap_pipe3_writel(phy->pll_ctrl_base,
+					  PLL_CONFIGURATION2, val);
+			ret = omap_pipe3_wait_lock(phy);
+			if (ret)
+				return ret;
+		}
+	}
+
+	/* Power up the PHY */
+	omap_control_phy_power(phy, 1);
+
+	return 0;
+}
+
+int phy_pipe3_power_off(struct omap_pipe3 *phy)
+{
+	u32 val;
+	int timeout = PLL_IDLE_TIME;
+
+	/* Power down the PHY */
+	omap_control_phy_power(phy, 0);
+
+	/* Put DPLL in IDLE mode */
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+	val |= PLL_IDLE;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+	/* wait for LDO and Oscillator to power down */
+	do {
+		mdelay(1);
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
+			break;
+	} while (--timeout);
+
+	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
+		printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
+		       __func__, val);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
new file mode 100644
index 000000000..441f49a3f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
@@ -0,0 +1,36 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __OMAP_PIPE3_PHY_H
+#define __OMAP_PIPE3_PHY_H
+
+struct pipe3_dpll_params {
+	u16     m;
+	u8      n;
+	u8      freq:3;
+	u8      sd;
+	u32     mf;
+};
+
+struct pipe3_dpll_map {
+	unsigned long rate;
+	struct pipe3_dpll_params params;
+};
+
+struct omap_pipe3 {
+	void __iomem            *pll_ctrl_base;
+	void __iomem		*power_reg;
+	struct pipe3_dpll_map   *dpll_map;
+};
+
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy);
+int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
+
+#endif /* __OMAP_PIPE3_PHY_H */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/reset.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/reset.c
new file mode 100644
index 000000000..91ad031dd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/reset.c
@@ -0,0 +1,29 @@
+/*
+ *
+ * Common layer for reset related functionality of OMAP based socs.
+ *
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <linux/compiler.h>
+
+void __weak reset_cpu(unsigned long ignored)
+{
+	writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
+}
+
+u32 __weak warm_reset(void)
+{
+	return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
+}
+
+void __weak setup_warmreset_time(void)
+{
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/sata.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/sata.c
new file mode 100644
index 000000000..cad4feed0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/sata.c
@@ -0,0 +1,76 @@
+/*
+ * TI SATA platform driver
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sata.h>
+#include <sata.h>
+#include <asm/io.h>
+#include "pipe3-phy.h"
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+	{12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
+	{16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
+	{19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
+	{20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
+	{26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
+	{38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
+	{ },                                    /* Terminator */
+};
+
+struct omap_pipe3 sata_phy = {
+	.pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
+	/* .power_reg is updated at runtime */
+	.dpll_map = dpll_map_sata,
+};
+
+int init_sata(int dev)
+{
+	int ret;
+	u32 val;
+
+	u32 const clk_domains_sata[] = {
+		0
+	};
+
+	u32 const clk_modules_hw_auto_sata[] = {
+		(*prcm)->cm_l3init_ocp2scp3_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_sata[] = {
+		(*prcm)->cm_l3init_sata_clkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains_sata,
+			 clk_modules_hw_auto_sata,
+			 clk_modules_explicit_en_sata,
+			 0);
+
+	/* Enable optional functional clock for SATA */
+	setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
+		     SATA_CLKCTRL_OPTFCLKEN_MASK);
+
+	sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
+
+	/* Power up the PHY */
+	phy_pipe3_power_on(&sata_phy);
+
+	/* Enable SATA module, No Idle, No Standby */
+	val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
+	writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
+
+	ret = ahci_init(DWC_AHSATA_BASE);
+	scsi_scan(1);
+
+	return ret;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/timer.c
new file mode 100644
index 000000000..7c9924dc3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/timer.c
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Moahmmed Khasim <khasim@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Nothing really to do with interrupts, just starts up a counter.
+ */
+
+#define TIMER_CLOCK		(V_SCLK / (2 << CONFIG_SYS_PTV))
+#define TIMER_OVERFLOW_VAL	0xffffffff
+#define TIMER_LOAD_VAL		0
+
+int timer_init(void)
+{
+	/* start the counter ticking up, reload value on overflow */
+	writel(TIMER_LOAD_VAL, &timer_base->tldr);
+	/* enable timer */
+	writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
+		&timer_base->tclr);
+
+	/* reset time, capture current incrementer value time */
+	gd->arch.lastinc = readl(&timer_base->tcrr) /
+					(TIMER_CLOCK / CONFIG_SYS_HZ);
+	gd->arch.tbl = 0;	/* start "advancing" time stamp from 0 */
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	unsigned long now, last = readl(&timer_base->tcrr);
+
+	while (tmo > 0) {
+		now = readl(&timer_base->tcrr);
+		if (last > now) /* count up timer overflow */
+			tmo -= TIMER_OVERFLOW_VAL - last + now + 1;
+		else
+			tmo -= now - last;
+		last = now;
+	}
+}
+
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+
+	if (now >= gd->arch.lastinc) {	/* normal mode (non roll) */
+		/* move stamp fordward with absoulte diff ticks */
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	} else {	/* we have rollover of incrementer */
+		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
+				CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
+	}
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
new file mode 100644
index 000000000..745603d0f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text*)
+		*(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*_i2c_*)));
+	} >.sram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/utils.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/utils.c
new file mode 100644
index 000000000..1696c2dbd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/utils.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2011 Linaro Limited
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+static void do_cancel_out(u32 *num, u32 *den, u32 factor)
+{
+	while (1) {
+		if (((*num)/factor*factor == (*num)) &&
+		   ((*den)/factor*factor == (*den))) {
+			(*num) /= factor;
+			(*den) /= factor;
+		} else
+			break;
+	}
+}
+
+/*
+ * Cancel out the denominator and numerator of a fraction
+ * to get smaller numerator and denominator.
+ */
+void cancel_out(u32 *num, u32 *den, u32 den_limit)
+{
+	do_cancel_out(num, den, 2);
+	do_cancel_out(num, den, 3);
+	do_cancel_out(num, den, 5);
+	do_cancel_out(num, den, 7);
+	do_cancel_out(num, den, 11);
+	do_cancel_out(num, den, 13);
+	do_cancel_out(num, den, 17);
+	while ((*den) > den_limit) {
+		*num /= 2;
+		/*
+		 * Round up the denominator so that the final fraction
+		 * (num/den) is always <= the desired value
+		 */
+		*den = (*den + 1) / 2;
+	}
+}
+
+void __weak usb_fake_mac_from_die_id(u32 *id)
+{
+	uint8_t device_mac[6];
+
+	if (!getenv("usbethaddr")) {
+		/*
+		 * create a fake MAC address from the processor ID code.
+		 * first byte is 0x02 to signify locally administered.
+		 */
+		device_mac[0] = 0x02;
+		device_mac[1] = id[3] & 0xff;
+		device_mac[2] = id[2] & 0xff;
+		device_mac[3] = id[1] & 0xff;
+		device_mac[4] = id[0] & 0xff;
+		device_mac[5] = (id[0] >> 8) & 0xff;
+
+		eth_setenv_enetaddr("usbethaddr", device_mac);
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/vc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/vc.c
new file mode 100644
index 000000000..a68f1d145
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap-common/vc.c
@@ -0,0 +1,151 @@
+/*
+ * Voltage Controller implementation for OMAP
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *	Nishanth Menon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+
+/*
+ * Define Master code if there are multiple masters on the I2C_SR bus.
+ * Normally not required
+ */
+#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE
+#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0
+#endif
+
+/* Register defines and masks for VC IP Block */
+/* PRM_VC_CFG_I2C_MODE */
+#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT	(0x1 << 6)
+#define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT	(0x1 << 4)
+#define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT	(0x1 << 3)
+#define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT	0x0
+#define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK	0x3
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT		24
+#define PRM_VC_CFG_I2C_CLK_HSCLL_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT		16
+#define PRM_VC_CFG_I2C_CLK_HSCLH_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_VAL_BYPASS_VALID_BIT		(0x1 << 24)
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
+#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
+
+/**
+ * omap_vc_init() - Initialization for Voltage controller
+ * @speed_khz: I2C buspeed in KHz
+ */
+static void omap_vc_init(u16 speed_khz)
+{
+	u32 val;
+	u32 sys_clk_khz, cycles_hi, cycles_low;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	if (speed_khz > 400) {
+		puts("higher speed requested - throttle to 400Khz\n");
+		speed_khz = 400;
+	}
+
+	/*
+	 * Setup the dedicated I2C controller for Voltage Control
+	 * I2C clk - high period 40% low period 60%
+	 */
+	speed_khz /= 10;
+	cycles_hi = sys_clk_khz * 4 / speed_khz;
+	cycles_low = sys_clk_khz * 6 / speed_khz;
+	/* values to be set in register - less by 5 & 7 respectively */
+	cycles_hi -= 5;
+	cycles_low -= 7;
+	val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
+	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
+	writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
+
+	val = CONFIG_OMAP_VC_I2C_HS_MCODE <<
+		PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
+	/* No HS mode for now */
+	val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
+	writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
+}
+
+/**
+ * omap_vc_bypass_send_value() - Send a data using VC Bypass command
+ * @sa:		7 bit I2C slave address of the PMIC
+ * @reg_addr:	I2C register address(8 bit) address in PMIC
+ * @reg_data:	what 8 bit data to write
+ */
+int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
+{
+	/*
+	 * Unfortunately we need to loop here instead of a defined time
+	 * use arbitary large value
+	 */
+	u32 timeout = 0xFFFF;
+	u32 reg_val;
+
+	sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK;
+	reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK;
+	reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK;
+
+	/* program VC to send data */
+	reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
+	    reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
+	    reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
+	writel(reg_val, (*prcm)->prm_vc_val_bypass);
+
+	/* Signal VC to send data */
+	writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT,
+				(*prcm)->prm_vc_val_bypass);
+
+	/* Wait on VC to complete transmission */
+	do {
+		reg_val = readl((*prcm)->prm_vc_val_bypass) &
+				PRM_VC_VAL_BYPASS_VALID_BIT;
+		if (!reg_val)
+			break;
+
+		sdelay(100);
+	} while (--timeout);
+
+	/* Optional: cleanup PRM_IRQSTATUS_Ax */
+	/* In case we can do something about it in future.. */
+	if (!timeout)
+		return -1;
+
+	/* All good.. */
+	return 0;
+}
+
+void sri2c_init(void)
+{
+	static int sri2c = 1;
+
+	if (sri2c) {
+		omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+		sri2c = 0;
+	}
+	return;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/Makefile
new file mode 100644
index 000000000..39ff2575b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/Makefile
@@ -0,0 +1,21 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= lowlevel_init.o
+
+obj-y	+= board.o
+obj-y	+= clock.o
+obj-y	+= mem.o
+obj-y	+= sys_info.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_OMAP3_ID_NAND)	+= spl_id_nand.o
+endif
+
+obj-$(CONFIG_DRIVER_TI_EMAC)	+= emac.o
+obj-$(CONFIG_EMIF4)	+= emif4.o
+obj-$(CONFIG_SDRC)	+= sdrc.o
+obj-$(CONFIG_USB_MUSB_AM35X)	+= am35x_musb.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/am35x_musb.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/am35x_musb.c
new file mode 100644
index 000000000..74dd105eb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/am35x_musb.c
@@ -0,0 +1,61 @@
+/*
+ * This file configures the internal USB PHY in AM35X.
+ *
+ * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
+ *
+ * Based on omap_phy_internal.c code from Linux by
+ * Hema HK <hemahk@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/am35x_def.h>
+
+void am35x_musb_reset(void)
+{
+	/* Reset the musb interface */
+	clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
+			0, USBOTGSS_SW_RST);
+	clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
+			USBOTGSS_SW_RST, 0);
+}
+
+void am35x_musb_phy_power(u8 on)
+{
+	unsigned long start = get_timer(0);
+
+	if (on) {
+		/*
+		 * Start the on-chip PHY and its PLL.
+		 */
+		clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+				CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
+				CONF2_PHY_PLLON);
+
+		debug("Waiting for PHY clock good...\n");
+		while (!(readl(&am35x_scm_general_regs->devconf2)
+				& CONF2_PHYCLKGD)) {
+
+			if (get_timer(start) > CONFIG_SYS_HZ / 10) {
+				printf("musb PHY clock good timed out\n");
+				break;
+			}
+		}
+	} else {
+		/*
+		 * Power down the on-chip PHY.
+		 */
+		clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+				CONF2_PHY_PLLON,
+				CONF2_PHYPWRDN | CONF2_OTGPWRDN);
+	}
+}
+
+void am35x_musb_clear_irq(void)
+{
+	clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
+			0, USBOTGSS_INT_CLR);
+	readl(&am35x_scm_general_regs->lvl_intr_clr);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/board.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/board.c
new file mode 100644
index 000000000..9bb1a1c8f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/board.c
@@ -0,0 +1,488 @@
+/*
+ *
+ * Common board functions for OMAP3 based boards.
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *      Sunil Kumar <sunilsaini05@gmail.com>
+ *      Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *      Richard Woodruff <r-woodruff2@ti.com>
+ *      Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/cache.h>
+#include <asm/armv7.h>
+#include <asm/arch/gpio.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Declarations */
+extern omap3_sysinfo sysinfo;
+static void omap3_setup_aux_cr(void);
+#ifndef CONFIG_SYS_L2CACHE_OFF
+static void omap3_invalidate_l2_cache_secure(void);
+#endif
+
+static const struct gpio_bank gpio_bank_34xx[6] = {
+	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
+
+#ifdef CONFIG_SPL_BUILD
+/*
+* We use static variables because global data is not ready yet.
+* Initialized data is available in SPL right from the beginning.
+* We would not typically need to save these parameters in regular
+* U-Boot. This is needed only in SPL at the moment.
+*/
+u32 omap3_boot_device = BOOT_DEVICE_NAND;
+
+/* auto boot mode detection is not possible for OMAP3 - hard code */
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC2:
+		return MMCSD_MODE_RAW;
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_FAT;
+		break;
+	default:
+		puts("spl: ERROR:  unknown device - can't select boot mode\n");
+		hang();
+	}
+}
+
+u32 spl_boot_device(void)
+{
+	return omap3_boot_device;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0, 0, 0, -1, -1);
+		break;
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		omap_mmc_init(1, 0, 0, -1, -1);
+		break;
+	}
+	return 0;
+}
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
+	gpmc_init();
+#endif
+#ifdef CONFIG_SPL_I2C_SUPPORT
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+#endif
+}
+#endif /* CONFIG_SPL_BUILD */
+
+
+/******************************************************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ *              (GP Device only)
+ *****************************************************************************/
+void secure_unlock_mem(void)
+{
+	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
+	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
+	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
+	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
+	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
+
+	/* Protection Module Register Target APE (PM_RT) */
+	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
+	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
+	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
+	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
+
+	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
+	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
+	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
+
+	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
+	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
+	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
+	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
+
+	/* IVA Changes */
+	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
+	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
+	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
+
+	/* SDRC region 0 public */
+	writel(UNLOCK_1, &sms_base->rg_att0);
+}
+
+/******************************************************************************
+ * Routine: secureworld_exit()
+ * Description: If chip is EMU and boot type is external
+ *		configure secure registers and exit secure world
+ *              general use.
+ *****************************************************************************/
+void secureworld_exit()
+{
+	unsigned long i;
+
+	/* configure non-secure access control register */
+	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
+	/* enabling co-processor CP10 and CP11 accesses in NS world */
+	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
+	/*
+	 * allow allocation of locked TLBs and L2 lines in NS world
+	 * allow use of PLE registers in NS world also
+	 */
+	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
+	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
+
+	/* Enable ASA in ACR register */
+	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
+	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+
+	/* Exiting secure world */
+	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
+	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
+	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
+}
+
+/******************************************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP/EMU(special) type, unlock the SRAM for
+ *              general use.
+ *****************************************************************************/
+void try_unlock_memory()
+{
+	int mode;
+	int in_sdram = is_running_in_sdram();
+
+	/*
+	 * if GP device unlock device SRAM for general use
+	 * secure code breaks for Secure/Emulation device - HS/E/T
+	 */
+	mode = get_device_type();
+	if (mode == GP_DEVICE)
+		secure_unlock_mem();
+
+	/*
+	 * If device is EMU and boot is XIP external booting
+	 * Unlock firewalls and disable L2 and put chip
+	 * out of secure world
+	 *
+	 * Assuming memories are unlocked by the demon who put us in SDRAM
+	 */
+	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
+	    && (!in_sdram)) {
+		secure_unlock_mem();
+		secureworld_exit();
+	}
+
+	return;
+}
+
+/******************************************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ *              - Called path is with SRAM stack.
+ *****************************************************************************/
+void s_init(void)
+{
+	int in_sdram = is_running_in_sdram();
+
+	watchdog_init();
+
+	try_unlock_memory();
+
+	/* Errata workarounds */
+	omap3_setup_aux_cr();
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+	/* Invalidate L2-cache from secure mode */
+	omap3_invalidate_l2_cache_secure();
+#endif
+
+	set_muxconf_regs();
+	sdelay(100);
+
+	prcm_init();
+
+	per_clocks_enable();
+
+#ifdef CONFIG_USB_EHCI_OMAP
+	ehci_clocks_enable();
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+	gd = &gdata;
+
+	preloader_console_init();
+
+	timer_init();
+#endif
+
+	if (!in_sdram)
+		mem_init();
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: A basic misc_init_r that just displays the die ID
+ */
+int __weak misc_init_r(void)
+{
+	dieid_num_r();
+
+	return 0;
+}
+
+/******************************************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ *****************************************************************************/
+void wait_for_command_complete(struct watchdog *wd_base)
+{
+	int pending = 1;
+	do {
+		pending = readl(&wd_base->wwps);
+	} while (pending);
+}
+
+/******************************************************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************************************************/
+void watchdog_init(void)
+{
+	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+	/*
+	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
+	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
+	 * should not be running and does not generate a PRCM reset.
+	 */
+
+	setbits_le32(&prcm_base->fclken_wkup, 0x20);
+	setbits_le32(&prcm_base->iclken_wkup, 0x20);
+	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
+
+	writel(WD_UNLOCK1, &wd2_base->wspr);
+	wait_for_command_complete(wd2_base);
+	writel(WD_UNLOCK2, &wd2_base->wspr);
+}
+
+/******************************************************************************
+ * Dummy function to handle errors for EABI incompatibility
+ *****************************************************************************/
+void abort(void)
+{
+}
+
+#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
+/******************************************************************************
+ * OMAP3 specific command to switch between NAND HW and SW ecc
+ *****************************************************************************/
+static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2 || argc > 3)
+		goto usage;
+
+	if (strncmp(argv[1], "hw", 2) == 0) {
+		if (argc == 2) {
+			omap_nand_switch_ecc(1, 1);
+		} else {
+			if (strncmp(argv[2], "hamming", 7) == 0)
+				omap_nand_switch_ecc(1, 1);
+			else if (strncmp(argv[2], "bch8", 4) == 0)
+				omap_nand_switch_ecc(1, 8);
+			else
+				goto usage;
+		}
+	} else if (strncmp(argv[1], "sw", 2) == 0) {
+		omap_nand_switch_ecc(0, 0);
+	} else {
+		goto usage;
+	}
+
+	return 0;
+
+usage:
+	printf ("Usage: nandecc %s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	nandecc, 3, 1,	do_switch_ecc,
+	"switch OMAP3 NAND ECC calculation algorithm",
+	"hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
+	" 8-bit BCH\n"
+	"                           ecc calculation (second parameter may"
+	" be omitted).\n"
+	"nandecc sw               - Switch to NAND software ecc algorithm."
+);
+
+#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+/**
+ * Print board information
+ */
+int checkboard (void)
+{
+	char *mem_s ;
+
+	if (is_mem_sdr())
+		mem_s = "mSDR";
+	else
+		mem_s = "LPDDR";
+
+	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
+			sysinfo.nand_string);
+
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_BOARDINFO */
+
+static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
+{
+	u32 i, num_params = *parameters;
+	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
+
+	/*
+	 * copy the parameters to an un-cached area to avoid coherency
+	 * issues
+	 */
+	for (i = 0; i < num_params; i++) {
+		__raw_writel(*parameters, sram_scratch_space);
+		parameters++;
+		sram_scratch_space++;
+	}
+
+	/* Now make the PPA call */
+	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
+}
+
+static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
+{
+	u32 acr;
+
+	/* Read ACR */
+	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+	acr &= ~clear_bits;
+	acr |= set_bits;
+
+	if (get_device_type() == GP_DEVICE) {
+		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
+				       acr);
+	} else {
+		struct emu_hal_params emu_romcode_params;
+		emu_romcode_params.num_params = 1;
+		emu_romcode_params.param1 = acr;
+		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+				       (u32 *)&emu_romcode_params);
+	}
+}
+
+static void omap3_setup_aux_cr(void)
+{
+	/* Workaround for Cortex-A8 errata: #454179 #430973
+	 *	Set "IBE" bit
+	 *	Set "Disable Branch Size Mispredicts" bit
+	 * Workaround for erratum #621766
+	 *	Enable L1NEON bit
+	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
+	 */
+	omap3_update_aux_cr_secure(0xE0, 0);
+}
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
+{
+	u32 acr;
+
+	/* Read ACR */
+	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+	acr &= ~clear_bits;
+	acr |= set_bits;
+
+	/* Write ACR - affects non-secure banked bits */
+	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
+}
+
+/* Invalidate the entire L2 cache from secure mode */
+static void omap3_invalidate_l2_cache_secure(void)
+{
+	if (get_device_type() == GP_DEVICE) {
+		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
+				      0);
+	} else {
+		struct emu_hal_params emu_romcode_params;
+		emu_romcode_params.num_params = 1;
+		emu_romcode_params.param1 = 0;
+		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
+				       (u32 *)&emu_romcode_params);
+	}
+}
+
+void v7_outer_cache_enable(void)
+{
+	/* Set L2EN */
+	omap3_update_aux_cr_secure(0x2, 0);
+
+	/*
+	 * On some revisions L2EN bit is banked on some revisions it's not
+	 * No harm in setting both banked bits(in fact this is required
+	 * by an erratum)
+	 */
+	omap3_update_aux_cr(0x2, 0);
+}
+
+void omap3_outer_cache_disable(void)
+{
+	/* Clear L2EN */
+	omap3_update_aux_cr_secure(0, 0x2);
+
+	/*
+	 * On some revisions L2EN bit is banked on some revisions it's not
+	 * No harm in clearing both banked bits(in fact this is required
+	 * by an erratum)
+	 */
+	omap3_update_aux_cr(0, 0x2);
+}
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif /* !CONFIG_SYS_DCACHE_OFF */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/clock.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/clock.c
new file mode 100644
index 000000000..529ad9a94
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/clock.c
@@ -0,0 +1,790 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *      Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and OMAP3 SDP code by
+ *      Richard Woodruff <r-woodruff2@ti.com>
+ *      Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clocks_omap3.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <environment.h>
+#include <command.h>
+
+/******************************************************************************
+ * get_sys_clk_speed() - determine reference oscillator speed
+ *                       based on known 32kHz clock and gptimer.
+ *****************************************************************************/
+u32 get_osc_clk_speed(void)
+{
+	u32 start, cstart, cend, cdiff, cdiv, val;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	struct prm *prm_base = (struct prm *)PRM_BASE;
+	struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
+	struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
+
+	val = readl(&prm_base->clksrc_ctrl);
+
+	if (val & SYSCLKDIV_2)
+		cdiv = 2;
+	else
+		cdiv = 1;
+
+	/* enable timer2 */
+	val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
+
+	/* select sys_clk for GPT1 */
+	writel(val, &prcm_base->clksel_wkup);
+
+	/* Enable I and F Clocks for GPT1 */
+	val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
+	writel(val, &prcm_base->iclken_wkup);
+
+	val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
+	writel(val, &prcm_base->fclken_wkup);
+
+	writel(0, &gpt1_base->tldr);		/* start counting at 0 */
+	writel(GPT_EN, &gpt1_base->tclr);	/* enable clock */
+
+	/* enable 32kHz source, determine sys_clk via gauging */
+
+	/* start time in 20 cycles */
+	start = 20 + readl(&s32k_base->s32k_cr);
+
+	/* dead loop till start time */
+	while (readl(&s32k_base->s32k_cr) < start);
+
+	/* get start sys_clk count */
+	cstart = readl(&gpt1_base->tcrr);
+
+	/* wait for 40 cycles */
+	while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
+	cend = readl(&gpt1_base->tcrr);		/* get end sys_clk count */
+	cdiff = cend - cstart;			/* get elapsed ticks */
+	cdiff *= cdiv;
+
+	/* based on number of ticks assign speed */
+	if (cdiff > 19000)
+		return S38_4M;
+	else if (cdiff > 15200)
+		return S26M;
+	else if (cdiff > 13000)
+		return S24M;
+	else if (cdiff > 9000)
+		return S19_2M;
+	else if (cdiff > 7600)
+		return S13M;
+	else
+		return S12M;
+}
+
+/******************************************************************************
+ * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
+ *                       input oscillator clock frequency.
+ *****************************************************************************/
+void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
+{
+	switch(osc_clk) {
+	case S38_4M:
+		*sys_clkin_sel = 4;
+		break;
+	case S26M:
+		*sys_clkin_sel = 3;
+		break;
+	case S19_2M:
+		*sys_clkin_sel = 2;
+		break;
+	case S13M:
+		*sys_clkin_sel = 1;
+		break;
+	case S12M:
+	default:
+		*sys_clkin_sel = 0;
+	}
+}
+
+/*
+ * OMAP34XX/35XX specific functions
+ */
+
+static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *) get_core_dpll_param();
+	void (*f_lock_pll) (u32, u32, u32, u32);
+	int xip_safe, p0, p1, p2, p3;
+
+	xip_safe = is_running_in_sram();
+
+	/* Moving to the right sysclk and ES rev base */
+	ptr = ptr + (3 * clk_index) + sil_index;
+
+	if (xip_safe) {
+		/*
+		 * CORE DPLL
+		 */
+		clrsetbits_le32(&prcm_base->clken_pll,
+				0x00000007, PLL_FAST_RELOCK_BYPASS);
+		wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
+				LDELAY);
+
+		/*
+		 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
+		 * work. write another value and then default value.
+		 */
+
+		/* CM_CLKSEL1_EMU[DIV_DPLL3] */
+		clrsetbits_le32(&prcm_base->clksel1_emu,
+				0x001F0000, (CORE_M3X2 + 1) << 16) ;
+		clrsetbits_le32(&prcm_base->clksel1_emu,
+				0x001F0000, CORE_M3X2 << 16);
+
+		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+		clrsetbits_le32(&prcm_base->clksel1_pll,
+				0xF8000000, ptr->m2 << 27);
+
+		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+		clrsetbits_le32(&prcm_base->clksel1_pll,
+				0x07FF0000, ptr->m << 16);
+
+		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+		clrsetbits_le32(&prcm_base->clksel1_pll,
+				0x00007F00, ptr->n << 8);
+
+		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+		clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
+
+		/* SSI */
+		clrsetbits_le32(&prcm_base->clksel_core,
+				0x00000F00, CORE_SSI_DIV << 8);
+		/* FSUSB */
+		clrsetbits_le32(&prcm_base->clksel_core,
+				0x00000030, CORE_FUSB_DIV << 4);
+		/* L4 */
+		clrsetbits_le32(&prcm_base->clksel_core,
+				0x0000000C, CORE_L4_DIV << 2);
+		/* L3 */
+		clrsetbits_le32(&prcm_base->clksel_core,
+				0x00000003, CORE_L3_DIV);
+		/* GFX */
+		clrsetbits_le32(&prcm_base->clksel_gfx,
+				0x00000007, GFX_DIV);
+		/* RESET MGR */
+		clrsetbits_le32(&prcm_base->clksel_wkup,
+				0x00000006, WKUP_RSM << 1);
+		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+		clrsetbits_le32(&prcm_base->clken_pll,
+				0x000000F0, ptr->fsel << 4);
+		/* LOCK MODE */
+		clrsetbits_le32(&prcm_base->clken_pll,
+				0x00000007, PLL_LOCK);
+
+		wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
+				LDELAY);
+	} else if (is_running_in_flash()) {
+		/*
+		 * if running from flash, jump to small relocated code
+		 * area in SRAM.
+		 */
+		f_lock_pll = (void *) (SRAM_CLK_CODE);
+
+		p0 = readl(&prcm_base->clken_pll);
+		clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
+		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+		clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
+
+		p1 = readl(&prcm_base->clksel1_pll);
+		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+		clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
+		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+		clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
+		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+		clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
+		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+		clrbits_le32(&p1, 0x00000040);
+
+		p2 = readl(&prcm_base->clksel_core);
+		/* SSI */
+		clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
+		/* FSUSB */
+		clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
+		/* L4 */
+		clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
+		/* L3 */
+		clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
+
+		p3 = (u32)&prcm_base->idlest_ckgen;
+
+		(*f_lock_pll) (p0, p1, p2, p3);
+	}
+}
+
+static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *) get_per_dpll_param();
+
+	/* Moving it to the right sysclk base */
+	ptr = ptr + clk_index;
+
+	/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+	clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
+	wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
+
+	/*
+	 * Errata 1.50 Workaround for OMAP3 ES1.0 only
+	 * If using default divisors, write default divisor + 1
+	 * and then the actual divisor value
+	 */
+	/* M6 */
+	clrsetbits_le32(&prcm_base->clksel1_emu,
+			0x1F000000, (PER_M6X2 + 1) << 24);
+	clrsetbits_le32(&prcm_base->clksel1_emu,
+			0x1F000000, PER_M6X2 << 24);
+	/* M5 */
+	clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
+	clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
+	/* M4 */
+	clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
+	clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
+	/* M3 */
+	clrsetbits_le32(&prcm_base->clksel_dss,
+			0x00001F00, (PER_M3X2 + 1) << 8);
+	clrsetbits_le32(&prcm_base->clksel_dss,
+			0x00001F00, PER_M3X2 << 8);
+	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+	clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
+	clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
+	/* Workaround end */
+
+	/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
+	clrsetbits_le32(&prcm_base->clksel2_pll,
+			0x0007FF00, ptr->m << 8);
+
+	/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+	clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
+
+	/* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
+	clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
+
+	/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
+	clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
+	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
+}
+
+static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
+
+	/* Moving it to the right sysclk base */
+	ptr = ptr + clk_index;
+
+	/* PER2 DPLL (DPLL5) */
+	clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
+	wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
+	/* set M2 (usbtll_fck) */
+	clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
+	/* set m (11-bit multiplier) */
+	clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
+	/* set n (7-bit divider)*/
+	clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
+	/* FREQSEL */
+	clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
+	/* lock mode */
+	clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
+	wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
+}
+
+static void mpu_init_34xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
+
+	/* Moving to the right sysclk and ES rev base */
+	ptr = ptr + (3 * clk_index) + sil_index;
+
+	/* MPU DPLL (unlocked already) */
+
+	/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+	clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
+			0x0000001F, ptr->m2);
+
+	/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+	clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
+			0x0007FF00, ptr->m << 8);
+
+	/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+	clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
+			0x0000007F, ptr->n);
+
+	/* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
+	clrsetbits_le32(&prcm_base->clken_pll_mpu,
+			0x000000F0, ptr->fsel << 4);
+}
+
+static void iva_init_34xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
+
+	/* Moving to the right sysclk and ES rev base */
+	ptr = ptr + (3 * clk_index) + sil_index;
+
+	/* IVA DPLL */
+	/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+	clrsetbits_le32(&prcm_base->clken_pll_iva2,
+			0x00000007, PLL_STOP);
+	wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
+
+	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+	clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
+			0x0000001F, ptr->m2);
+
+	/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+	clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
+			0x0007FF00, ptr->m << 8);
+
+	/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+	clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
+			0x0000007F, ptr->n);
+
+	/* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
+	clrsetbits_le32(&prcm_base->clken_pll_iva2,
+			0x000000F0, ptr->fsel << 4);
+
+	/* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+	clrsetbits_le32(&prcm_base->clken_pll_iva2,
+			0x00000007, PLL_LOCK);
+
+	wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
+}
+
+/*
+ * OMAP3630 specific functions
+ */
+
+static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
+	void (*f_lock_pll) (u32, u32, u32, u32);
+	int xip_safe, p0, p1, p2, p3;
+
+	xip_safe = is_running_in_sram();
+
+	/* Moving it to the right sysclk base */
+	ptr += clk_index;
+
+	if (xip_safe) {
+		/* CORE DPLL */
+
+		/* Select relock bypass: CM_CLKEN_PLL[0:2] */
+		clrsetbits_le32(&prcm_base->clken_pll,
+				0x00000007, PLL_FAST_RELOCK_BYPASS);
+		wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
+				LDELAY);
+
+		/* CM_CLKSEL1_EMU[DIV_DPLL3] */
+		clrsetbits_le32(&prcm_base->clksel1_emu,
+				0x001F0000, CORE_M3X2 << 16);
+
+		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+		clrsetbits_le32(&prcm_base->clksel1_pll,
+				0xF8000000, ptr->m2 << 27);
+
+		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+		clrsetbits_le32(&prcm_base->clksel1_pll,
+				0x07FF0000, ptr->m << 16);
+
+		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+		clrsetbits_le32(&prcm_base->clksel1_pll,
+				0x00007F00, ptr->n << 8);
+
+		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+		clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
+
+		/* SSI */
+		clrsetbits_le32(&prcm_base->clksel_core,
+				0x00000F00, CORE_SSI_DIV << 8);
+		/* FSUSB */
+		clrsetbits_le32(&prcm_base->clksel_core,
+				0x00000030, CORE_FUSB_DIV << 4);
+		/* L4 */
+		clrsetbits_le32(&prcm_base->clksel_core,
+				0x0000000C, CORE_L4_DIV << 2);
+		/* L3 */
+		clrsetbits_le32(&prcm_base->clksel_core,
+				0x00000003, CORE_L3_DIV);
+		/* GFX */
+		clrsetbits_le32(&prcm_base->clksel_gfx,
+				0x00000007, GFX_DIV_36X);
+		/* RESET MGR */
+		clrsetbits_le32(&prcm_base->clksel_wkup,
+				0x00000006, WKUP_RSM << 1);
+		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+		clrsetbits_le32(&prcm_base->clken_pll,
+				0x000000F0, ptr->fsel << 4);
+		/* LOCK MODE */
+		clrsetbits_le32(&prcm_base->clken_pll,
+				0x00000007, PLL_LOCK);
+
+		wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
+				LDELAY);
+	} else if (is_running_in_flash()) {
+		/*
+		 * if running from flash, jump to small relocated code
+		 * area in SRAM.
+		 */
+		f_lock_pll = (void *) (SRAM_CLK_CODE);
+
+		p0 = readl(&prcm_base->clken_pll);
+		clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
+		/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+		clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
+
+		p1 = readl(&prcm_base->clksel1_pll);
+		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+		clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
+		/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+		clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
+		/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+		clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
+		/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+		clrbits_le32(&p1, 0x00000040);
+
+		p2 = readl(&prcm_base->clksel_core);
+		/* SSI */
+		clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
+		/* FSUSB */
+		clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
+		/* L4 */
+		clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
+		/* L3 */
+		clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
+
+		p3 = (u32)&prcm_base->idlest_ckgen;
+
+		(*f_lock_pll) (p0, p1, p2, p3);
+	}
+}
+
+static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	struct dpll_per_36x_param *ptr;
+
+	ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
+
+	/* Moving it to the right sysclk base */
+	ptr += clk_index;
+
+	/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+	clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
+	wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
+
+	/* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
+	clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
+
+	/* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
+	clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
+
+	/* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
+	clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
+
+	/* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
+	clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
+
+	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+	clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
+
+	/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
+	clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
+
+	/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+	clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
+
+	/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
+	clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
+
+	/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
+	clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
+	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
+}
+
+static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
+
+	/* Moving it to the right sysclk base */
+	ptr = ptr + clk_index;
+
+	/* PER2 DPLL (DPLL5) */
+	clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
+	wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
+	/* set M2 (usbtll_fck) */
+	clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
+	/* set m (11-bit multiplier) */
+	clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
+	/* set n (7-bit divider)*/
+	clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
+	/* lock mode */
+	clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
+	wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
+}
+
+static void mpu_init_36xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
+
+	/* Moving to the right sysclk */
+	ptr += clk_index;
+
+	/* MPU DPLL (unlocked already */
+
+	/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+	clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
+
+	/* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+	clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
+
+	/* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+	clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
+}
+
+static void iva_init_36xx(u32 sil_index, u32 clk_index)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
+
+	/* Moving to the right sysclk */
+	ptr += clk_index;
+
+	/* IVA DPLL */
+	/* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+	clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
+	wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
+
+	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+	clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
+
+	/* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+	clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
+
+	/* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+	clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
+
+	/* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+	clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
+
+	wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
+}
+
+/******************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ *               called from SRAM, or Flash (using temp SRAM stack).
+ *****************************************************************************/
+void prcm_init(void)
+{
+	u32 osc_clk = 0, sys_clkin_sel;
+	u32 clk_index, sil_index = 0;
+	struct prm *prm_base = (struct prm *)PRM_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+	/*
+	 * Gauge the input clock speed and find out the sys_clkin_sel
+	 * value corresponding to the input clock.
+	 */
+	osc_clk = get_osc_clk_speed();
+	get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+
+	/* set input crystal speed */
+	clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
+
+	/* If the input clock is greater than 19.2M always divide/2 */
+	if (sys_clkin_sel > 2) {
+		/* input clock divider */
+		clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
+		clk_index = sys_clkin_sel / 2;
+	} else {
+		/* input clock divider */
+		clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
+		clk_index = sys_clkin_sel;
+	}
+
+	if (get_cpu_family() == CPU_OMAP36XX) {
+		/*
+		 * In warm reset conditions on OMAP36xx/AM/DM37xx
+		 * the rom code incorrectly sets the DPLL4 clock
+		 * input divider to /6.5. Section 3.5.3.3.3.2.1 of
+		 * the AM/DM37x TRM explains that the /6.5 divider
+		 * is used only when the input clock is 13MHz.
+		 *
+		 * If the part is in this cpu family *and* the input
+		 * clock *is not* 13 MHz, then reset the DPLL4 clock
+		 * input divider to /1 as it should never set to /6.5
+		 * in this case.
+		 */
+		if (sys_clkin_sel != 1) {	/* 13 MHz */
+			/* Bit 8: DPLL4_CLKINP_DIV */
+			clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
+		}
+
+		/* Unlock MPU DPLL (slows things down, and needed later) */
+		clrsetbits_le32(&prcm_base->clken_pll_mpu,
+				0x00000007, PLL_LOW_POWER_BYPASS);
+		wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
+				LDELAY);
+
+		dpll3_init_36xx(0, clk_index);
+		dpll4_init_36xx(0, clk_index);
+		dpll5_init_36xx(0, clk_index);
+		iva_init_36xx(0, clk_index);
+		mpu_init_36xx(0, clk_index);
+
+		/* Lock MPU DPLL to set frequency */
+		clrsetbits_le32(&prcm_base->clken_pll_mpu,
+				0x00000007, PLL_LOCK);
+		wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
+				LDELAY);
+	} else {
+		/*
+		 * The DPLL tables are defined according to sysclk value and
+		 * silicon revision. The clk_index value will be used to get
+		 * the values for that input sysclk from the DPLL param table
+		 * and sil_index will get the values for that SysClk for the
+		 * appropriate silicon rev.
+		 */
+		if (((get_cpu_family() == CPU_OMAP34XX)
+				&& (get_cpu_rev() >= CPU_3XX_ES20)) ||
+			(get_cpu_family() == CPU_AM35XX))
+			sil_index = 1;
+
+		/* Unlock MPU DPLL (slows things down, and needed later) */
+		clrsetbits_le32(&prcm_base->clken_pll_mpu,
+				0x00000007, PLL_LOW_POWER_BYPASS);
+		wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
+				LDELAY);
+
+		dpll3_init_34xx(sil_index, clk_index);
+		dpll4_init_34xx(sil_index, clk_index);
+		dpll5_init_34xx(sil_index, clk_index);
+		if (get_cpu_family() != CPU_AM35XX)
+			iva_init_34xx(sil_index, clk_index);
+
+		mpu_init_34xx(sil_index, clk_index);
+
+		/* Lock MPU DPLL to set frequency */
+		clrsetbits_le32(&prcm_base->clken_pll_mpu,
+				0x00000007, PLL_LOCK);
+		wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
+				LDELAY);
+	}
+
+	/* Set up GPTimers to sys_clk source only */
+	setbits_le32(&prcm_base->clksel_per, 0x000000FF);
+	setbits_le32(&prcm_base->clksel_wkup, 1);
+
+	sdelay(5000);
+}
+
+/*
+ * Enable usb ehci uhh, tll clocks
+ */
+void ehci_clocks_enable(void)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+	/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
+	setbits_le32(&prcm_base->iclken_usbhost, 1);
+	/*
+	 * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
+	 * and USBHOST_120M_FCLK (USBHOST_FCLK2)
+	 */
+	setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
+	/* Enable USBTTL_ICLK */
+	setbits_le32(&prcm_base->iclken3_core, 0x00000004);
+	/* Enable USBTTL_FCLK */
+	setbits_le32(&prcm_base->fclken3_core, 0x00000004);
+}
+
+/******************************************************************************
+ * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
+ *****************************************************************************/
+void per_clocks_enable(void)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+	/* Enable GP2 timer. */
+	setbits_le32(&prcm_base->clksel_per, 0x01);	/* GPT2 = sys clk */
+	setbits_le32(&prcm_base->iclken_per, 0x08);	/* ICKen GPT2 */
+	setbits_le32(&prcm_base->fclken_per, 0x08);	/* FCKen GPT2 */
+
+#ifdef CONFIG_SYS_NS16550
+	/* Enable UART1 clocks */
+	setbits_le32(&prcm_base->fclken1_core, 0x00002000);
+	setbits_le32(&prcm_base->iclken1_core, 0x00002000);
+
+	/* UART 3 Clocks */
+	setbits_le32(&prcm_base->fclken_per, 0x00000800);
+	setbits_le32(&prcm_base->iclken_per, 0x00000800);
+#endif
+
+#ifdef CONFIG_OMAP3_GPIO_2
+	setbits_le32(&prcm_base->fclken_per, 0x00002000);
+	setbits_le32(&prcm_base->iclken_per, 0x00002000);
+#endif
+#ifdef CONFIG_OMAP3_GPIO_3
+	setbits_le32(&prcm_base->fclken_per, 0x00004000);
+	setbits_le32(&prcm_base->iclken_per, 0x00004000);
+#endif
+#ifdef CONFIG_OMAP3_GPIO_4
+	setbits_le32(&prcm_base->fclken_per, 0x00008000);
+	setbits_le32(&prcm_base->iclken_per, 0x00008000);
+#endif
+#ifdef CONFIG_OMAP3_GPIO_5
+	setbits_le32(&prcm_base->fclken_per, 0x00010000);
+	setbits_le32(&prcm_base->iclken_per, 0x00010000);
+#endif
+#ifdef CONFIG_OMAP3_GPIO_6
+	setbits_le32(&prcm_base->fclken_per, 0x00020000);
+	setbits_le32(&prcm_base->iclken_per, 0x00020000);
+#endif
+
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+	/* Turn on all 3 I2C clocks */
+	setbits_le32(&prcm_base->fclken1_core, 0x00038000);
+	setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
+#endif
+	/* Enable the ICLK for 32K Sync Timer as its used in udelay */
+	setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
+
+	if (get_cpu_family() != CPU_AM35XX)
+		out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
+
+	out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
+	out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
+	out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
+	out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
+	out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
+	out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
+	out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
+	if (get_cpu_family() != CPU_AM35XX) {
+		out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
+		out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
+	}
+
+	sdelay(1000);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/config.mk b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/config.mk
new file mode 100644
index 000000000..ad44d6384
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/config.mk
@@ -0,0 +1,15 @@
+#
+# Copyright 2011 Linaro Limited
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+#
+# Aneesh V <aneesh@ti.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= MLO
+else
+ALL-y	+= u-boot.img
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/emac.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/emac.c
new file mode 100644
index 000000000..37f4b8b49
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/emac.c
@@ -0,0 +1,29 @@
+/*
+ *
+ * DaVinci EMAC initialization.
+ *
+ * (C) Copyright 2011, Ilya Yanok, Emcraft Systems
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/am35x_def.h>
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+	u32 reset;
+
+	/* ensure that the module is out of reset */
+	reset = readl(&am35x_scm_general_regs->ip_sw_reset);
+	reset &= ~CPGMACSS_SW_RST;
+	writel(reset, &am35x_scm_general_regs->ip_sw_reset);
+
+	return davinci_emac_initialize();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/emif4.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/emif4.c
new file mode 100644
index 000000000..6c7330a0c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/emif4.c
@@ -0,0 +1,165 @@
+/*
+ * Author :
+ *     Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on mem.c and sdrc.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/emif4.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+extern omap3_sysinfo sysinfo;
+
+static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
+
+/*
+ * is_mem_sdr -
+ *  - Return 1 if mem type in use is SDR
+ */
+u32 is_mem_sdr(void)
+{
+	return 0;
+}
+
+/*
+ * get_sdr_cs_size -
+ *  - Get size of chip select 0/1
+ */
+u32 get_sdr_cs_size(u32 cs)
+{
+	u32 size = 0;
+
+	/* TODO: Calculate the size based on EMIF4 configuration */
+	if (cs == CS0)
+		size = CONFIG_SYS_CS0_SIZE;
+
+	return size;
+}
+
+/*
+ * get_sdr_cs_offset -
+ *  - Get offset of cs from cs0 start
+ */
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset = 0;
+
+	return offset;
+}
+
+/*
+ * do_emif4_init -
+ *  - Init the emif4 module for DDR access
+ *  - Early init routines, called from flash or SRAM.
+ */
+void do_emif4_init(void)
+{
+	unsigned int regval;
+	/* Set the DDR PHY parameters in PHY ctrl registers */
+	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
+		EMIF4_DDR1_EXT_STRB_DIS);
+	writel(regval, &emif4_base->ddr_phyctrl1);
+	writel(regval, &emif4_base->ddr_phyctrl1_shdw);
+	writel(0, &emif4_base->ddr_phyctrl2);
+
+	/* Reset the DDR PHY and wait till completed */
+	regval = readl(&emif4_base->sdram_iodft_tlgc);
+	regval |= (1<<10);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+	/*Wait till that bit clears*/
+	while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
+	/*Re-verify the DDR PHY status*/
+	while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
+
+	regval |= (1<<0);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+	/* Set SDR timing registers */
+	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
+		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
+		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
+		EMIF4_TIM1_T_RP);
+	writel(regval, &emif4_base->sdram_time1);
+	writel(regval, &emif4_base->sdram_time1_shdw);
+
+	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
+		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
+		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
+	writel(regval, &emif4_base->sdram_time2);
+	writel(regval, &emif4_base->sdram_time2_shdw);
+
+	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
+	writel(regval, &emif4_base->sdram_time3);
+	writel(regval, &emif4_base->sdram_time3_shdw);
+
+	/* Set the PWR control register */
+	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
+		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
+	writel(regval, &emif4_base->sdram_pwr_mgmt);
+	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
+
+	/* Set the DDR refresh rate control register */
+	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
+	writel(regval, &emif4_base->sdram_refresh_ctrl);
+	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
+
+	/* set the SDRAM configuration register */
+	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
+		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
+		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
+		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
+		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
+		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
+	writel(regval, &emif4_base->sdram_config);
+}
+
+/*
+ * dram_init -
+ *  - Sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	/*
+	 * If a second bank of DDR is attached to CS1 this is
+	 * where it can be started.  Early init code will init
+	 * memory on CS0.
+	 */
+	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
+		size1 = get_sdr_cs_size(CS1);
+
+	gd->ram_size = size0 + size1;
+	return 0;
+}
+
+void dram_init_banksize (void)
+{
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	size1 = get_sdr_cs_size(CS1);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+	gd->bd->bi_dram[1].size = size1;
+}
+
+/*
+ * mem_init() -
+ *  - Initialize memory subsystem
+ */
+void mem_init(void)
+{
+	do_emif4_init();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/lowlevel_init.S
new file mode 100644
index 000000000..78577b1d1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -0,0 +1,498 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Initial Code by:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks_omap3.h>
+#include <linux/linkage.h>
+
+#ifdef CONFIG_SPL_BUILD
+ENTRY(save_boot_params)
+	ldr	r4, =omap3_boot_device
+	ldr	r5, [r0, #0x4]
+	and	r5, r5, #0xff
+	str	r5, [r4]
+	bx	lr
+ENDPROC(save_boot_params)
+#endif
+
+ENTRY(omap3_gp_romcode_call)
+	PUSH {r4-r12, lr} @ Save all registers from ROM code!
+	MOV r12, r0	@ Copy the Service ID in R12
+	MOV r0, r1	@ Copy parameter to R0
+	mcr     p15, 0, r0, c7, c10, 4	@ DSB
+	mcr     p15, 0, r0, c7, c10, 5	@ DMB
+	.word	0xe1600070	@ SMC #0 to enter monitor - hand assembled
+				@ because we use -march=armv5
+	POP {r4-r12, pc}
+ENDPROC(omap3_gp_romcode_call)
+
+/*
+ * Funtion for making PPA HAL API calls in secure devices
+ * Input:
+ *	R0 - Service ID
+ *	R1 - paramer list
+ */
+ENTRY(do_omap3_emu_romcode_call)
+	PUSH {r4-r12, lr} @ Save all registers from ROM code!
+	MOV r12, r0	@ Copy the Secure Service ID in R12
+	MOV r3, r1	@ Copy the pointer to va_list in R3
+	MOV r1, #0	@ Process ID - 0
+	MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL	@ Copy the pointer
+							@ to va_list in R3
+	MOV r6, #0xFF	@ Indicate new Task call
+	mcr     p15, 0, r0, c7, c10, 4	@ DSB
+	mcr     p15, 0, r0, c7, c10, 5	@ DMB
+	.word	0xe1600071	@ SMC #1 to call PPA service - hand assembled
+				@ because we use -march=armv5
+	POP {r4-r12, pc}
+ENDPROC(do_omap3_emu_romcode_call)
+
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+ENTRY(cpy_clk_code)
+	/* Copy DPLL code into SRAM */
+	adr	r0, go_to_speed		/* copy from start of go_to_speed... */
+	adr	r2, lowlevel_init	/* ... up to start of low_level_init */
+next2:
+	ldmia	r0!, {r3 - r10}		/* copy from source address [r0] */
+	stmia	r1!, {r3 - r10}		/* copy to   target address [r1] */
+	cmp	r0, r2			/* until source end address [r2] */
+	blo	next2
+	mov	pc, lr			/* back to caller */
+ENDPROC(cpy_clk_code)
+
+/* ***************************************************************************
+ *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ *               -executed from SRAM.
+ *  R0 = CM_CLKEN_PLL-bypass value
+ *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ *  R2 = CM_CLKSEL_CORE-divider values
+ *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ *        confused.  A reset of the controller gets it back.  Taking away its
+ *        L3 when its not in self refresh seems bad for it.  Normally, this
+ *	  code runs from flash before SDR is init so that should be ok.
+ ****************************************************************************/
+ENTRY(go_to_speed)
+	stmfd sp!, {r4 - r6}
+
+	/* move into fast relock bypass */
+	ldr	r4, pll_ctl_add
+	str	r0, [r4]
+wait1:
+	ldr	r5, [r3]		/* get status */
+	and	r5, r5, #0x1		/* isolate core status */
+	cmp	r5, #0x1		/* still locked? */
+	beq	wait1			/* if lock, loop */
+
+	/* set new dpll dividers _after_ in bypass */
+	ldr	r5, pll_div_add1
+	str	r1, [r5]		/* set m, n, m2 */
+	ldr	r5, pll_div_add2
+	str	r2, [r5]		/* set l3/l4/.. dividers*/
+	ldr	r5, pll_div_add3	/* wkup */
+	ldr	r2, pll_div_val3	/* rsm val */
+	str	r2, [r5]
+	ldr	r5, pll_div_add4	/* gfx */
+	ldr	r2, pll_div_val4
+	str	r2, [r5]
+	ldr	r5, pll_div_add5	/* emu */
+	ldr	r2, pll_div_val5
+	str	r2, [r5]
+
+	/* now prepare GPMC (flash) for new dpll speed */
+	/* flash needs to be stable when we jump back to it */
+	ldr	r5, flash_cfg3_addr
+	ldr	r2, flash_cfg3_val
+	str	r2, [r5]
+	ldr	r5, flash_cfg4_addr
+	ldr	r2, flash_cfg4_val
+	str	r2, [r5]
+	ldr	r5, flash_cfg5_addr
+	ldr	r2, flash_cfg5_val
+	str	r2, [r5]
+	ldr	r5, flash_cfg1_addr
+	ldr	r2, [r5]
+	orr	r2, r2, #0x3		/* up gpmc divider */
+	str	r2, [r5]
+
+	/* lock DPLL3 and wait a bit */
+	orr	r0, r0, #0x7	/* set up for lock mode */
+	str	r0, [r4]	/* lock */
+	nop			/* ARM slow at this point working at sys_clk */
+	nop
+	nop
+	nop
+wait2:
+	ldr	r5, [r3]	/* get status */
+	and	r5, r5, #0x1	/* isolate core status */
+	cmp	r5, #0x1	/* still locked? */
+	bne	wait2		/* if lock, loop */
+	nop
+	nop
+	nop
+	nop
+	ldmfd	sp!, {r4 - r6}
+	mov	pc, lr		/* back to caller, locked */
+ENDPROC(go_to_speed)
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
+flash_cfg3_addr:
+	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
+flash_cfg3_val:
+	.word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
+flash_cfg4_val:
+	.word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+	.word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
+pll_ctl_add:
+	.word CM_CLKEN_PLL
+pll_div_add1:
+	.word CM_CLKSEL1_PLL
+pll_div_add2:
+	.word CM_CLKSEL_CORE
+pll_div_add3:
+	.word CM_CLKSEL_WKUP
+pll_div_val3:
+	.word (WKUP_RSM << 1)
+pll_div_add4:
+	.word CM_CLKSEL_GFX
+pll_div_val4:
+	.word (GFX_DIV << 0)
+pll_div_add5:
+	.word CM_CLKSEL1_EMU
+pll_div_val5:
+	.word CLSEL1_EMU_VAL
+
+#endif
+
+ENTRY(lowlevel_init)
+	ldr	sp, SRAM_STACK
+	str	ip, [sp]	/* stash ip register */
+	mov	ip, lr		/* save link reg across call */
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
+/*
+ * No need to copy/exec the clock code - DPLL adjust already done
+ * in NAND/oneNAND Boot.
+ */
+	ldr	r1, =SRAM_CLK_CODE
+	bl	cpy_clk_code
+#endif /* NAND Boot */
+	mov	lr, ip		/* restore link reg */
+	ldr	ip, [sp]	/* restore save ip */
+	/* tail-call s_init to setup pll, mux, memory */
+	b	s_init
+
+ENDPROC(lowlevel_init)
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_CONTROL_STATUS:
+	.word CONTROL_STATUS
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
+
+/* DPLL(1-4) PARAM TABLES */
+
+/*
+ * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
+/* ES2 */
+.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
+/* 3410 */
+.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
+
+/* 13MHz */
+/* ES1 */
+.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
+/* ES2 */
+.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
+/* 3410 */
+.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
+/* ES2 */
+.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
+/* 3410 */
+.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
+
+/* 26MHz */
+/* ES1 */
+.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
+/* ES2 */
+.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
+/* 3410 */
+.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
+/* ES2 */
+.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
+/* 3410 */
+.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+	adr	r0, mpu_dpll_param
+	mov	pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
+/* ES2 */
+.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
+/* 3410 */
+.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
+
+/* 13MHz */
+/* ES1 */
+.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
+/* ES2 */
+.word IVA_M_13_ES2, IVA_N_13_ES2,  IVA_FSEL_13_ES2, IVA_M2_13_ES2
+/* 3410 */
+.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
+/* ES2 */
+.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
+/* 3410 */
+.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
+
+/* 26MHz */
+/* ES1 */
+.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
+/* ES2 */
+.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
+/* 3410 */
+.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
+/* ES2 */
+.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
+/* 3410 */
+.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+	adr	r0, iva_dpll_param
+	mov	pc, lr
+
+/* Core DPLL targets for L3 at 166 & L133 */
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
+/* ES2 */
+.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
+/* 3410 */
+.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
+
+/* 13MHz */
+/* ES1 */
+.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
+/* ES2 */
+.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
+/* 3410 */
+.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
+/* ES2 */
+.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
+/* 3410 */
+.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
+
+/* 26MHz */
+/* ES1 */
+.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
+/* ES2 */
+.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
+/* 3410 */
+.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
+/* ES2 */
+.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
+/* 3410 */
+.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+	adr	r0, core_dpll_param
+	mov	pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
+
+/* 13MHz */
+.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
+
+/* 19.2MHz */
+.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
+
+/* 26MHz */
+.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
+
+/* 38.4MHz */
+.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+	adr	r0, per_dpll_param
+	mov	pc, lr
+
+/* PER2 DPLL values */
+per2_dpll_param:
+/* 12MHz */
+.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
+
+/* 13MHz */
+.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
+
+/* 19.2MHz */
+.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
+
+/* 26MHz */
+.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
+
+/* 38.4MHz */
+.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
+
+.globl get_per2_dpll_param
+get_per2_dpll_param:
+	adr	r0, per2_dpll_param
+	mov	pc, lr
+
+/*
+ * Tables for 36XX/37XX devices
+ *
+ */
+mpu_36x_dpll_param:
+/* 12MHz */
+.word 50, 0, 0, 1
+/* 13MHz */
+.word 600, 12, 0, 1
+/* 19.2MHz */
+.word 125, 3, 0, 1
+/* 26MHz */
+.word 300, 12, 0, 1
+/* 38.4MHz */
+.word 125, 7, 0, 1
+
+iva_36x_dpll_param:
+/* 12MHz */
+.word 130, 2, 0, 1
+/* 13MHz */
+.word 20, 0, 0, 1
+/* 19.2MHz */
+.word 325, 11, 0, 1
+/* 26MHz */
+.word 10, 0, 0, 1
+/* 38.4MHz */
+.word 325, 23, 0, 1
+
+core_36x_dpll_param:
+/* 12MHz */
+.word 100, 2, 0, 1
+/* 13MHz */
+.word 400, 12, 0, 1
+/* 19.2MHz */
+.word 375, 17, 0, 1
+/* 26MHz */
+.word 200, 12, 0, 1
+/* 38.4MHz */
+.word 375, 35, 0, 1
+
+per_36x_dpll_param:
+/*    SYSCLK    M       N      M2      M3      M4     M5      M6      m2DIV */
+.word 12000,    360,    4,     9,      16,     5,     4,      3,      1
+.word 13000,    864,   12,     9,      16,     9,     4,      3,      1
+.word 19200,    360,    7,     9,      16,     5,     4,      3,      1
+.word 26000,    432,   12,     9,      16,     9,     4,      3,      1
+.word 38400,    360,   15,     9,      16,     5,     4,      3,      1
+
+per2_36x_dpll_param:
+/* 12MHz */
+.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
+/* 13MHz */
+.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
+/* 19.2MHz */
+.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
+/* 26MHz */
+.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
+/* 38.4MHz */
+.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
+
+
+ENTRY(get_36x_mpu_dpll_param)
+	adr	r0, mpu_36x_dpll_param
+	mov	pc, lr
+ENDPROC(get_36x_mpu_dpll_param)
+
+ENTRY(get_36x_iva_dpll_param)
+	adr	r0, iva_36x_dpll_param
+	mov	pc, lr
+ENDPROC(get_36x_iva_dpll_param)
+
+ENTRY(get_36x_core_dpll_param)
+	adr	r0, core_36x_dpll_param
+	mov	pc, lr
+ENDPROC(get_36x_core_dpll_param)
+
+ENTRY(get_36x_per_dpll_param)
+	adr	r0, per_36x_dpll_param
+	mov	pc, lr
+ENDPROC(get_36x_per_dpll_param)
+
+ENTRY(get_36x_per2_dpll_param)
+	adr	r0, per2_36x_dpll_param
+	mov	pc, lr
+ENDPROC(get_36x_per2_dpll_param)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/mem.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/mem.c
new file mode 100644
index 000000000..e64940965
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/mem.c
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Initial Code from:
+ *     Richard Woodruff <r-woodruff2@ti.com>
+ *     Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <command.h>
+
+struct gpmc *gpmc_cfg;
+
+#if defined(CONFIG_CMD_NAND)
+#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
+	SMNAND_GPMC_CONFIG1,
+	SMNAND_GPMC_CONFIG2,
+	SMNAND_GPMC_CONFIG3,
+	SMNAND_GPMC_CONFIG4,
+	SMNAND_GPMC_CONFIG5,
+	SMNAND_GPMC_CONFIG6,
+	0,
+};
+#else
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
+	M_NAND_GPMC_CONFIG1,
+	M_NAND_GPMC_CONFIG2,
+	M_NAND_GPMC_CONFIG3,
+	M_NAND_GPMC_CONFIG4,
+	M_NAND_GPMC_CONFIG5,
+	M_NAND_GPMC_CONFIG6, 0
+};
+#endif
+#endif /* CONFIG_CMD_NAND */
+
+#if defined(CONFIG_CMD_ONENAND)
+static const u32 gpmc_onenand[GPMC_MAX_REG] = {
+	ONENAND_GPMC_CONFIG1,
+	ONENAND_GPMC_CONFIG2,
+	ONENAND_GPMC_CONFIG3,
+	ONENAND_GPMC_CONFIG4,
+	ONENAND_GPMC_CONFIG5,
+	ONENAND_GPMC_CONFIG6, 0
+};
+#endif /* CONFIG_CMD_ONENAND */
+
+/********************************************************
+ *  mem_ok() - test used to see if timings are correct
+ *             for a part. Helps in guessing which part
+ *             we are currently using.
+ *******************************************************/
+u32 mem_ok(u32 cs)
+{
+	u32 val1, val2, addr;
+	u32 pattern = 0x12345678;
+
+	addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
+
+	writel(0x0, addr + 0x400);	/* clear pos A */
+	writel(pattern, addr);		/* pattern to pos B */
+	writel(0x0, addr + 4);		/* remove pattern off the bus */
+	val1 = readl(addr + 0x400);	/* get pos A value */
+	val2 = readl(addr);		/* get val2 */
+	writel(0x0, addr + 0x400);	/* clear pos A */
+
+	if ((val1 != 0) || (val2 != pattern))	/* see if pos A val changed */
+		return 0;
+	else
+		return 1;
+}
+
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+			u32 size)
+{
+	writel(0, &cs->config7);
+	sdelay(1000);
+	/* Delay for settling */
+	writel(gpmc_config[0], &cs->config1);
+	writel(gpmc_config[1], &cs->config2);
+	writel(gpmc_config[2], &cs->config3);
+	writel(gpmc_config[3], &cs->config4);
+	writel(gpmc_config[4], &cs->config5);
+	writel(gpmc_config[5], &cs->config6);
+
+	/*
+	 * Enable the config.  size is the CS size and goes in
+	 * bits 11:8.  We set bit 6 to enable this CS and the base
+	 * address goes into bits 5:0.
+	 */
+	 writel((size << 8) | (GPMC_CS_ENABLE << 6) |
+				 ((base >> 24) & GPMC_BASEADDR_MASK),
+				 &cs->config7);
+	sdelay(2000);
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+	/* putting a blanket check on GPMC based on ZeBu for now */
+	gpmc_cfg = (struct gpmc *)GPMC_BASE;
+#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
+	const u32 *gpmc_config = NULL;
+	u32 base = 0;
+	u32 size = 0;
+#endif
+	u32 config = 0;
+
+	/* global settings */
+	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
+	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
+
+	config = readl(&gpmc_cfg->config);
+	config &= (~0xf00);
+	writel(config, &gpmc_cfg->config);
+
+	/*
+	 * Disable the GPMC0 config set by ROM code
+	 * It conflicts with our MPDB (both at 0x08000000)
+	 */
+	writel(0, &gpmc_cfg->cs[0].config7);
+	sdelay(1000);
+
+#if defined(CONFIG_CMD_NAND)	/* CS 0 */
+	gpmc_config = gpmc_m_nand;
+
+	base = PISMO1_NAND_BASE;
+	size = PISMO1_NAND_SIZE;
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+	gpmc_config = gpmc_onenand;
+	base = PISMO1_ONEN_BASE;
+	size = PISMO1_ONEN_SIZE;
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
+#endif
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/sdrc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/sdrc.c
new file mode 100644
index 000000000..7a291318a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -0,0 +1,237 @@
+/*
+ * Functions related to OMAP3 SDRC.
+ *
+ * This file has been created after exctracting and consolidating
+ * the SDRC related content from mem.c and board.c, also created
+ * generic init function (mem_init).
+ *
+ * Copyright (C) 2004-2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * Author :
+ *     Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Original implementation by (mem.c, board.c) :
+ *      Sunil Kumar <sunilsaini05@gmail.com>
+ *      Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *      Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+extern omap3_sysinfo sysinfo;
+
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+
+/*
+ * is_mem_sdr -
+ *  - Return 1 if mem type in use is SDR
+ */
+u32 is_mem_sdr(void)
+{
+	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
+		return 1;
+	return 0;
+}
+
+/*
+ * make_cs1_contiguous -
+ * - When we have CS1 populated we want to have it mapped after cs0 to allow
+ *   command line mem=xyz use all memory with out discontinuous support
+ *   compiled in.  We could do it in the ATAG, but there really is two banks...
+ */
+void make_cs1_contiguous(void)
+{
+	u32 size, a_add_low, a_add_high;
+
+	size = get_sdr_cs_size(CS0);
+	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
+	a_add_high = (size & 3) << 8;	/* set up low field */
+	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
+	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
+
+}
+
+
+/*
+ * get_sdr_cs_size -
+ *  - Get size of chip select 0/1
+ */
+u32 get_sdr_cs_size(u32 cs)
+{
+	u32 size;
+
+	/* get ram size field */
+	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
+	size &= 0x3FF;		/* remove unwanted bits */
+	size <<= 21;		/* multiply by 2 MiB to find size in MB */
+	return size;
+}
+
+/*
+ * get_sdr_cs_offset -
+ *  - Get offset of cs from cs0 start
+ */
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset;
+
+	if (!cs)
+		return 0;
+
+	offset = readl(&sdrc_base->cs_cfg);
+	offset = (offset & 15) << 27 | (offset & 0x300) << 17;
+
+	return offset;
+}
+
+/*
+ * write_sdrc_timings -
+ *  - Takes CS and associated timings and initalize SDRAM
+ *  - Test CS to make sure it's OK for use
+ */
+static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
+			struct board_sdrc_timings *timings)
+{
+	/* Setup timings we got from the board. */
+	writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
+	writel(timings->ctrla, &sdrc_actim_base->ctrla);
+	writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
+	writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
+	writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+	writel(timings->mr, &sdrc_base->cs[cs].mr);
+
+	/*
+	 * Test ram in this bank
+	 * Disable if bad or not present
+	 */
+	if (!mem_ok(cs))
+		writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
+/*
+ * do_sdrc_init -
+ *  - Code called once in C-Stack only context for CS0 and with early being
+ *    true and a possible 2nd time depending on memory configuration from
+ *    stack+global context.
+ */
+void do_sdrc_init(u32 cs, u32 early)
+{
+	struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
+	struct board_sdrc_timings timings;
+
+	sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+	sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+
+	/*
+	 * When called in the early context this may be SPL and we will
+	 * need to set all of the timings.  This ends up being board
+	 * specific so we call a helper function to take care of this
+	 * for us.  Otherwise, to be safe, we need to copy the settings
+	 * from the first bank to the second.  We will setup CS0,
+	 * then set cs_cfg to the appropriate value then try and
+	 * setup CS1.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	get_board_mem_timings(&timings);
+#endif
+	if (early) {
+		/* reset sdrc controller */
+		writel(SOFTRESET, &sdrc_base->sysconfig);
+		wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
+				12000000);
+		writel(0, &sdrc_base->sysconfig);
+
+		/* setup sdrc to ball mux */
+		writel(SDRC_SHARING, &sdrc_base->sharing);
+
+		/* Disable Power Down of CKE because of 1 CKE on combo part */
+		writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
+				&sdrc_base->power);
+
+		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
+		sdelay(0x20000);
+#ifdef CONFIG_SPL_BUILD
+		write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
+		make_cs1_contiguous();
+		write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
+#endif
+
+	}
+
+	/*
+	 * If we aren't using SPL we have been loaded by some
+	 * other means which may not have correctly initialized
+	 * both CS0 and CS1 (such as some older versions of x-loader)
+	 * so we may be asked now to setup CS1.
+	 */
+	if (cs == CS1) {
+		timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
+		timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
+		timings.ctrla = readl(&sdrc_actim_base0->ctrla);
+		timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
+		timings.mr = readl(&sdrc_base->cs[CS0].mr);
+		write_sdrc_timings(cs, sdrc_actim_base1, &timings);
+	}
+}
+
+/*
+ * dram_init -
+ *  - Sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	/*
+	 * We always need to have cs_cfg point at where the second
+	 * bank would be, if present.  Failure to do so can lead to
+	 * strange situations where memory isn't detected and
+	 * configured correctly.  CS0 will already have been setup
+	 * at this point.
+	 */
+	make_cs1_contiguous();
+	do_sdrc_init(CS1, NOT_EARLY);
+	size1 = get_sdr_cs_size(CS1);
+
+	gd->ram_size = size0 + size1;
+
+	return 0;
+}
+
+void dram_init_banksize (void)
+{
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	size1 = get_sdr_cs_size(CS1);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+	gd->bd->bi_dram[1].size = size1;
+}
+
+/*
+ * mem_init -
+ *  - Init the sdrc chip,
+ *  - Selects CS0 and CS1,
+ */
+void mem_init(void)
+{
+	/* only init up first bank here */
+	do_sdrc_init(CS0, EARLY_INIT);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/spl_id_nand.c
new file mode 100644
index 000000000..db6de0911
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/spl_id_nand.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Tom Rini <trini@ti.com>
+ *
+ * Initial Code from:
+ *     Richard Woodruff <r-woodruff2@ti.com>
+ *     Jian Zhang <jzhang@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/mtd/nand.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+
+static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
+
+/* nand_command: Send a flash command to the flash chip */
+static void nand_command(u8 command)
+{
+	writeb(command, &gpmc_config->cs[0].nand_cmd);
+
+	if (command == NAND_CMD_RESET) {
+		unsigned char ret_val;
+		writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
+		do {
+			/* Wait until ready */
+			ret_val = readl(&gpmc_config->cs[0].nand_dat);
+		} while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY);
+	}
+}
+
+/*
+ * Many boards will want to know the results of the NAND_CMD_READID command
+ * in order to decide what to do about DDR initialization.  This function
+ * allows us to do that very early and to pass those results back to the
+ * board so it can make whatever decisions need to be made.
+ */
+void identify_nand_chip(int *mfr, int *id)
+{
+	/* Make sure that we have setup GPMC for NAND correctly. */
+	writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
+	writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
+	writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
+	writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
+	writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
+	writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
+
+	/*
+	 * Enable the config.  The CS size goes in bits 11:8.  We set
+	 * bit 6 to enable the CS and the base address goes into bits 5:0.
+	 */
+	writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) |
+				((NAND_BASE >> 24) & GPMC_BASEADDR_MASK),
+			&gpmc_config->cs[0].config7);
+
+	sdelay(2000);
+
+	/* Issue a RESET and then READID */
+	nand_command(NAND_CMD_RESET);
+	nand_command(NAND_CMD_READID);
+
+	/* Set the address to read to 0x0 */
+	writeb(0x0, &gpmc_config->cs[0].nand_adr);
+
+	/* Read off the manufacturer and device id. */
+	*mfr = readb(&gpmc_config->cs[0].nand_dat);
+	*id = readb(&gpmc_config->cs[0].nand_dat);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/sys_info.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/sys_info.c
new file mode 100644
index 000000000..bef5f05ea
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -0,0 +1,364 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *      Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *      Richard Woodruff <r-woodruff2@ti.com>
+ *      Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>	/* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <linux/compiler.h>
+
+extern omap3_sysinfo sysinfo;
+static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+static char *rev_s[CPU_3XX_MAX_REV] = {
+				"1.0",
+				"2.0",
+				"2.1",
+				"3.0",
+				"3.1",
+				"UNKNOWN",
+				"UNKNOWN",
+				"3.1.2"};
+
+/* this is the revision table for 37xx CPUs */
+static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
+				"1.0",
+				"1.1",
+				"1.2"};
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*****************************************************************
+ * get_dieid(u32 *id) - read die ID
+ *****************************************************************/
+void get_dieid(u32 *id)
+{
+	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+
+	id[3] = readl(&id_base->die_id_0);
+	id[2] = readl(&id_base->die_id_1);
+	id[1] = readl(&id_base->die_id_2);
+	id[0] = readl(&id_base->die_id_3);
+}
+
+/*****************************************************************
+ * dieid_num_r(void) - read and set die ID
+ *****************************************************************/
+void dieid_num_r(void)
+{
+	char *uid_s, die_id[34];
+	u32 id[4];
+
+	memset(die_id, 0, sizeof(die_id));
+
+	uid_s = getenv("dieid#");
+
+	if (uid_s == NULL) {
+		get_dieid(id);
+		sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
+		setenv("dieid#", die_id);
+		uid_s = die_id;
+	}
+
+	printf("Die ID #%s\n", uid_s);
+}
+
+/******************************************
+ * get_cpu_type(void) - extract cpu info
+ ******************************************/
+u32 get_cpu_type(void)
+{
+	return readl(&ctrl_base->ctrl_omap_stat);
+}
+
+/******************************************
+ * get_cpu_id(void) - extract cpu id
+ * returns 0 for ES1.0, cpuid otherwise
+ ******************************************/
+u32 get_cpu_id(void)
+{
+	struct ctrl_id *id_base;
+	u32 cpuid = 0;
+
+	/*
+	 * On ES1.0 the IDCODE register is not exposed on L4
+	 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
+	 */
+	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
+	if ((cpuid & 0xf) == 0x0) {
+		return 0;
+	} else {
+		/* Decode the IDs on > ES1.0 */
+		id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
+
+		cpuid = readl(&id_base->idcode);
+	}
+
+	return cpuid;
+}
+
+/******************************************
+ * get_cpu_family(void) - extract cpu info
+ ******************************************/
+u32 get_cpu_family(void)
+{
+	u16 hawkeye;
+	u32 cpu_family;
+	u32 cpuid = get_cpu_id();
+
+	if (cpuid == 0)
+		return CPU_OMAP34XX;
+
+	hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
+	switch (hawkeye) {
+	case HAWKEYE_OMAP34XX:
+		cpu_family = CPU_OMAP34XX;
+		break;
+	case HAWKEYE_AM35XX:
+		cpu_family = CPU_AM35XX;
+		break;
+	case HAWKEYE_OMAP36XX:
+		cpu_family = CPU_OMAP36XX;
+		break;
+	default:
+		cpu_family = CPU_OMAP34XX;
+	}
+
+	return cpu_family;
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+	u32 cpuid = get_cpu_id();
+
+	if (cpuid == 0)
+		return CPU_3XX_ES10;
+	else
+		return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
+}
+
+/*****************************************************************
+ * get_sku_id(void) - read sku_id to get info on max clock rate
+ *****************************************************************/
+u32 get_sku_id(void)
+{
+	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+	return readl(&id_base->sku_id) & SKUID_CLK_MASK;
+}
+
+/***************************************************************************
+ *  get_gpmc0_base() - Return current address hardware will be
+ *     fetching from. The below effectively gives what is correct, its a bit
+ *   mis-leading compared to the TRM.  For the most general case the mask
+ *   needs to be also taken into account this does work in practice.
+ *   - for u-boot we currently map:
+ *       -- 0 to nothing,
+ *       -- 4 to flash
+ *       -- 8 to enent
+ *       -- c to wifi
+ ****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+	u32 b;
+
+	b = readl(&gpmc_cfg->cs[0].config7);
+	b &= 0x1F;		/* keep base [5:0] */
+	b = b << 24;		/* ret 0x0b000000 */
+	return b;
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+	return WIDTH_16BIT;
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ *************************************************************************/
+u32 __weak get_board_rev(void)
+{
+	return 0x20;
+}
+
+/********************************************************
+ *  get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+	u32 val;
+
+	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+	val &= 0xF0000000;
+	val >>= 28;
+	return val;
+}
+
+/********************************************************
+ *  is_running_in_flash() - tell if currently running in
+ *  FLASH.
+ *******************************************************/
+u32 is_running_in_flash(void)
+{
+	if (get_base() < 4)
+		return 1;	/* in FLASH */
+
+	return 0;		/* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ *  is_running_in_sram() - tell if currently running in
+ *  SRAM.
+ *******************************************************/
+u32 is_running_in_sram(void)
+{
+	if (get_base() == 4)
+		return 1;	/* in SRAM */
+
+	return 0;		/* running in FLASH or SDRAM */
+}
+
+/********************************************************
+ *  is_running_in_sdram() - tell if currently running in
+ *  SDRAM.
+ *******************************************************/
+u32 is_running_in_sdram(void)
+{
+	if (get_base() > 4)
+		return 1;	/* in SDRAM */
+
+	return 0;		/* running in SRAM or FLASH */
+}
+
+/***************************************************************
+ *  get_boot_type() - Is this an XIP type device or a stream one
+ *  bits 4-0 specify type. Bit 5 says mem/perif
+ ***************************************************************/
+u32 get_boot_type(void)
+{
+	return (readl(&ctrl_base->status) & SYSBOOT_MASK);
+}
+
+/*************************************************************
+ *  get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/**
+ * Print CPU information
+ */
+int print_cpuinfo (void)
+{
+	char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
+
+	switch (get_cpu_family()) {
+	case CPU_OMAP34XX:
+		cpu_family_s = "OMAP";
+		switch (get_cpu_type()) {
+		case OMAP3503:
+			cpu_s = "3503";
+			break;
+		case OMAP3515:
+			cpu_s = "3515";
+			break;
+		case OMAP3525:
+			cpu_s = "3525";
+			break;
+		case OMAP3530:
+			cpu_s = "3530";
+			break;
+		default:
+			cpu_s = "35XX";
+			break;
+		}
+		if ((get_cpu_rev() >= CPU_3XX_ES31) &&
+		    (get_sku_id() == SKUID_CLK_720MHZ))
+			max_clk = "720 MHz";
+		else
+			max_clk = "600 MHz";
+
+		break;
+	case CPU_AM35XX:
+		cpu_family_s = "AM";
+		switch (get_cpu_type()) {
+		case AM3505:
+			cpu_s = "3505";
+			break;
+		case AM3517:
+			cpu_s = "3517";
+			break;
+		default:
+			cpu_s = "35XX";
+			break;
+		}
+		max_clk = "600 Mhz";
+		break;
+	case CPU_OMAP36XX:
+		cpu_family_s = "OMAP";
+		switch (get_cpu_type()) {
+		case OMAP3730:
+			cpu_s = "3630/3730";
+			break;
+		default:
+			cpu_s = "36XX/37XX";
+			break;
+		}
+		max_clk = "1 Ghz";
+		break;
+	default:
+		cpu_family_s = "OMAP";
+		cpu_s = "35XX";
+		max_clk = "600 Mhz";
+	}
+
+	switch (get_device_type()) {
+	case TST_DEVICE:
+		sec_s = "TST";
+		break;
+	case EMU_DEVICE:
+		sec_s = "EMU";
+		break;
+	case HS_DEVICE:
+		sec_s = "HS";
+		break;
+	case GP_DEVICE:
+		sec_s = "GP";
+		break;
+	default:
+		sec_s = "?";
+	}
+
+	if (CPU_OMAP36XX == get_cpu_family())
+		printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
+		       cpu_family_s, cpu_s, sec_s,
+		       rev_s_37xx[get_cpu_rev()], max_clk);
+	else
+		printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
+			cpu_family_s, cpu_s, sec_s,
+			rev_s[get_cpu_rev()], max_clk);
+
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_CPUINFO */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/Makefile
new file mode 100644
index 000000000..76a032a2d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= sdram_elpida.o
+obj-y	+= hwinit.o
+obj-y	+= emif.o
+obj-y	+= prcm-regs.o
+obj-y	+= hw_data.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/config.mk b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/config.mk
new file mode 100644
index 000000000..ad44d6384
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/config.mk
@@ -0,0 +1,15 @@
+#
+# Copyright 2011 Linaro Limited
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+#
+# Aneesh V <aneesh@ti.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= MLO
+else
+ALL-y	+= u-boot.img
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/emif.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/emif.c
new file mode 100644
index 000000000..e89032be7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/emif.c
@@ -0,0 +1,112 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/emif.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
+u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
+#endif
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+/* Base AC Timing values specified by JESD209-2 for 400MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_400_mhz = {
+	.max_freq = 400000000,
+	.RL = 6,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_200_mhz = {
+	.max_freq = 200000000,
+	.RL = 3,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 20,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/*
+ * Min tCK values specified by JESD209-2
+ * Min tCK specifies the minimum duration of some AC timing parameters in terms
+ * of the number of cycles. If the calculated number of cycles based on the
+ * absolute time value is less than the min tCK value, min tCK value should
+ * be used instead. This typically happens at low frequencies.
+ */
+static const struct lpddr2_min_tck min_tck_jedec = {
+	.tRL = 3,
+	.tRP_AB = 3,
+	.tRCD = 3,
+	.tWR = 3,
+	.tRAS_MIN = 3,
+	.tRRD = 2,
+	.tWTR = 2,
+	.tXP = 2,
+	.tRTP = 2,
+	.tCKE = 3,
+	.tCKESR = 3,
+	.tFAW = 8
+};
+
+static const struct lpddr2_ac_timings const*
+			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+	&timings_jedec_200_mhz,
+	&timings_jedec_400_mhz
+};
+
+static const struct lpddr2_device_timings jedec_default_timings = {
+	.ac_timings = jedec_ac_timings,
+	.min_tck = &min_tck_jedec
+};
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	/* Assume Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &jedec_default_timings;
+	*cs1_device_timings = &jedec_default_timings;
+}
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/hw_data.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/hw_data.c
new file mode 100644
index 000000000..029533c85
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -0,0 +1,457 @@
+/*
+ *
+ * HW data initialization for OMAP4
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clock.h>
+#include <asm/omap_gpio.h>
+#include <asm/io.h>
+
+struct prcm_regs const **prcm =
+			(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
+struct dplls const **dplls_data =
+			(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
+struct vcores_data const **omap_vcores =
+		(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
+struct omap_sys_ctrl_regs const **ctrl =
+	(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
+
+/*
+ * The M & N values in the following tables are created using the
+ * following tool:
+ * tools/omap/clocks_get_m_n.c
+ * Please use this tool for creating the table for any new frequency.
+ */
+
+/*
+ * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
+ * OMAP4460 OPP_NOM frequency
+ */
+static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
+	{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/*
+ * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
+ * OMAP4430 OPP_TURBO frequency
+ * OMAP4470 OPP_NOM frequency
+ */
+static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+/*
+ * dpll locked at 1200 MHz - MPU clk at 600 MHz
+ * OMAP4430 OPP_NOM frequency
+ */
+static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
+	{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+/* OMAP4460 OPP_NOM frequency */
+/* OMAP4470 OPP_NOM (Low Power) frequency */
+static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+	{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
+	{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
+	{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
+	{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
+	{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
+	{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
+	{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* OMAP4430 ES1 OPP_NOM frequency */
+static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
+	{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
+	{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
+	{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
+	{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
+	{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
+	{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
+	{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* OMAP4430 ES2.X OPP_NOM frequency */
+static const struct dpll_params
+		core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
+	{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
+	{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
+	{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
+	{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
+	{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
+	{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
+	{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
+	{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 12 MHz   */
+	{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 13 MHz   */
+	{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 16.8 MHz */
+	{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 19.2 MHz */
+	{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 26 MHz   */
+	{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 27 MHz   */
+	{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
+	{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+	{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+	{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+struct dplls omap4430_dplls_es1 = {
+	.mpu = mpu_dpll_params_1200mhz,
+	.core = core_dpll_params_es1_1524mhz,
+	.per = per_dpll_params_1536mhz,
+	.iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	.abe = abe_dpll_params_sysclk_196608khz,
+#else
+	.abe = &abe_dpll_params_32k_196608khz,
+#endif
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = NULL
+};
+
+struct dplls omap4430_dplls_es20 = {
+	.mpu = mpu_dpll_params_1200mhz,
+	.core = core_dpll_params_es2_1600mhz_ddr200mhz,
+	.per = per_dpll_params_1536mhz,
+	.iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	.abe = abe_dpll_params_sysclk_196608khz,
+#else
+	.abe = &abe_dpll_params_32k_196608khz,
+#endif
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = NULL
+};
+
+struct dplls omap4430_dplls = {
+	.mpu = mpu_dpll_params_1200mhz,
+	.core = core_dpll_params_1600mhz,
+	.per = per_dpll_params_1536mhz,
+	.iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	.abe = abe_dpll_params_sysclk_196608khz,
+#else
+	.abe = &abe_dpll_params_32k_196608khz,
+#endif
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = NULL
+};
+
+struct dplls omap4460_dplls = {
+	.mpu = mpu_dpll_params_1400mhz,
+	.core = core_dpll_params_1600mhz,
+	.per = per_dpll_params_1536mhz,
+	.iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	.abe = abe_dpll_params_sysclk_196608khz,
+#else
+	.abe = &abe_dpll_params_32k_196608khz,
+#endif
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = NULL
+};
+
+struct dplls omap4470_dplls = {
+	.mpu = mpu_dpll_params_1600mhz,
+	.core = core_dpll_params_1600mhz,
+	.per = per_dpll_params_1536mhz,
+	.iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	.abe = abe_dpll_params_sysclk_196608khz,
+#else
+	.abe = &abe_dpll_params_32k_196608khz,
+#endif
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = NULL
+};
+
+struct pmic_data twl6030_4430es1 = {
+	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
+	.step = 12660, /* 12.66 mV represented in uV */
+	/* The code starts at 1 not 0 */
+	.start_code = 1,
+	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
+	.pmic_bus_init	= sri2c_init,
+	.pmic_write	= omap_vc_bypass_send_value,
+};
+
+/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
+struct pmic_data twl6030 = {
+	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
+	.step = 12660, /* 12.66 mV represented in uV */
+	/* The code starts at 1 not 0 */
+	.start_code = 1,
+	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
+	.pmic_bus_init	= sri2c_init,
+	.pmic_write	= omap_vc_bypass_send_value,
+};
+
+struct pmic_data tps62361 = {
+	.base_offset = TPS62361_BASE_VOLT_MV,
+	.step = 10000, /* 10 mV represented in uV */
+	.start_code = 0,
+	.gpio = TPS62361_VSEL0_GPIO,
+	.gpio_en = 1,
+	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
+	.pmic_bus_init	= sri2c_init,
+	.pmic_write	= omap_vc_bypass_send_value,
+};
+
+struct vcores_data omap4430_volts_es1 = {
+	.mpu.value = 1325,
+	.mpu.addr = SMPS_REG_ADDR_VCORE1,
+	.mpu.pmic = &twl6030_4430es1,
+
+	.core.value = 1200,
+	.core.addr = SMPS_REG_ADDR_VCORE3,
+	.core.pmic = &twl6030_4430es1,
+
+	.mm.value = 1200,
+	.mm.addr = SMPS_REG_ADDR_VCORE2,
+	.mm.pmic = &twl6030_4430es1,
+};
+
+struct vcores_data omap4430_volts = {
+	.mpu.value = 1325,
+	.mpu.addr = SMPS_REG_ADDR_VCORE1,
+	.mpu.pmic = &twl6030,
+
+	.core.value = 1200,
+	.core.addr = SMPS_REG_ADDR_VCORE3,
+	.core.pmic = &twl6030,
+
+	.mm.value = 1200,
+	.mm.addr = SMPS_REG_ADDR_VCORE2,
+	.mm.pmic = &twl6030,
+};
+
+struct vcores_data omap4460_volts = {
+	.mpu.value = 1203,
+	.mpu.addr = TPS62361_REG_ADDR_SET1,
+	.mpu.pmic = &tps62361,
+
+	.core.value = 1200,
+	.core.addr = SMPS_REG_ADDR_VCORE1,
+	.core.pmic = &twl6030,
+
+	.mm.value = 1200,
+	.mm.addr = SMPS_REG_ADDR_VCORE2,
+	.mm.pmic = &twl6030,
+};
+
+/*
+ * Take closest integer part of the mV value corresponding to a TWL6032 SMPS
+ * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
+ */
+struct vcores_data omap4470_volts = {
+	.mpu.value = 1202,
+	.mpu.addr = SMPS_REG_ADDR_SMPS1,
+	.mpu.pmic = &twl6030,
+
+	.core.value = 1126,
+	.core.addr = SMPS_REG_ADDR_SMPS2,
+	.core.pmic = &twl6030,
+
+	.mm.value = 1139,
+	.mm.addr = SMPS_REG_ADDR_SMPS5,
+	.mm.pmic = &twl6030,
+};
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+	u32 const clk_domains_essential[] = {
+		(*prcm)->cm_l4per_clkstctrl,
+		(*prcm)->cm_l3init_clkstctrl,
+		(*prcm)->cm_memif_clkstctrl,
+		(*prcm)->cm_l4cfg_clkstctrl,
+		0
+	};
+
+	u32 const clk_modules_hw_auto_essential[] = {
+		(*prcm)->cm_l3_gpmc_clkctrl,
+		(*prcm)->cm_memif_emif_1_clkctrl,
+		(*prcm)->cm_memif_emif_2_clkctrl,
+		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
+		(*prcm)->cm_wkup_gpio1_clkctrl,
+		(*prcm)->cm_l4per_gpio2_clkctrl,
+		(*prcm)->cm_l4per_gpio3_clkctrl,
+		(*prcm)->cm_l4per_gpio4_clkctrl,
+		(*prcm)->cm_l4per_gpio5_clkctrl,
+		(*prcm)->cm_l4per_gpio6_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_essential[] = {
+		(*prcm)->cm_wkup_gptimer1_clkctrl,
+		(*prcm)->cm_l3init_hsmmc1_clkctrl,
+		(*prcm)->cm_l3init_hsmmc2_clkctrl,
+		(*prcm)->cm_l4per_gptimer2_clkctrl,
+		(*prcm)->cm_wkup_wdtimer2_clkctrl,
+		(*prcm)->cm_l4per_uart3_clkctrl,
+		0
+	};
+
+	/* Enable optional additional functional clock for GPIO4 */
+	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
+			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+	/* Enable 96 MHz clock for MMC1 & MMC2 */
+	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+
+	/* Select 32KHz clock as the source of GPTIMER1 */
+	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
+			GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+	/* Enable optional 48M functional clock for USB  PHY */
+	setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
+			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
+
+	do_enable_clocks(clk_domains_essential,
+			 clk_modules_hw_auto_essential,
+			 clk_modules_explicit_en_essential,
+			 1);
+}
+
+void enable_basic_uboot_clocks(void)
+{
+	u32 const clk_domains_essential[] = {
+		0
+	};
+
+	u32 const clk_modules_hw_auto_essential[] = {
+		(*prcm)->cm_l3init_hsusbotg_clkctrl,
+		(*prcm)->cm_l3init_usbphy_clkctrl,
+		(*prcm)->cm_l3init_usbphy_clkctrl,
+		(*prcm)->cm_clksel_usb_60mhz,
+		(*prcm)->cm_l3init_hsusbtll_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_essential[] = {
+		(*prcm)->cm_l4per_mcspi1_clkctrl,
+		(*prcm)->cm_l4per_i2c1_clkctrl,
+		(*prcm)->cm_l4per_i2c2_clkctrl,
+		(*prcm)->cm_l4per_i2c3_clkctrl,
+		(*prcm)->cm_l4per_i2c4_clkctrl,
+		(*prcm)->cm_l3init_hsusbhost_clkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains_essential,
+			 clk_modules_hw_auto_essential,
+			 clk_modules_explicit_en_essential,
+			 1);
+}
+
+void hw_data_init(void)
+{
+	u32 omap_rev = omap_revision();
+
+	(*prcm) = &omap4_prcm;
+
+	switch (omap_rev) {
+
+	case OMAP4430_ES1_0:
+	*dplls_data = &omap4430_dplls_es1;
+	*omap_vcores = &omap4430_volts_es1;
+	break;
+
+	case OMAP4430_ES2_0:
+	*dplls_data = &omap4430_dplls_es20;
+	*omap_vcores = &omap4430_volts;
+	break;
+
+	case OMAP4430_ES2_1:
+	case OMAP4430_ES2_2:
+	case OMAP4430_ES2_3:
+	*dplls_data = &omap4430_dplls;
+	*omap_vcores = &omap4430_volts;
+	break;
+
+	case OMAP4460_ES1_0:
+	case OMAP4460_ES1_1:
+	*dplls_data = &omap4460_dplls;
+	*omap_vcores = &omap4460_volts;
+	break;
+
+	case OMAP4470_ES1_0:
+	*dplls_data = &omap4470_dplls;
+	*omap_vcores = &omap4470_volts;
+	break;
+
+	default:
+		printf("\n INVALID OMAP REVISION ");
+	}
+
+	*ctrl = &omap4_ctrl;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/hwinit.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/hwinit.c
new file mode 100644
index 000000000..db16548fa
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -0,0 +1,169 @@
+/*
+ *
+ * Common functions for OMAP4 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Aneesh V	<aneesh@ti.com>
+ *	Steve Sakoman	<steve@sakoman.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/sizes.h>
+#include <asm/emif.h>
+#include <asm/arch/gpio.h>
+#include <asm/omap_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
+
+static const struct gpio_bank gpio_bank_44xx[6] = {
+	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+void do_io_settings(void)
+{
+	u32 lpddr2io;
+
+	u32 omap4_rev = omap_revision();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
+	else
+		lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
+
+	/* EMIF1 */
+	writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
+	writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
+	/* No pull for GR10 as per hw team's recommendation */
+	writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+		(*ctrl)->control_lpddr2io1_2);
+	writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
+
+	/* EMIF2 */
+	writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
+	writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
+	/* No pull for GR10 as per hw team's recommendation */
+	writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
+		(*ctrl)->control_lpddr2io2_2);
+	writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
+
+	/*
+	 * Some of these settings (TRIM values) come from eFuse and are
+	 * in turn programmed in the eFuse at manufacturing time after
+	 * calibration of the device. Do the software over-ride only if
+	 * the device is not correctly trimmed
+	 */
+	if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
+
+		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+			(*ctrl)->control_ldosram_iva_voltage_ctrl);
+
+		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+			(*ctrl)->control_ldosram_mpu_voltage_ctrl);
+
+		writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
+			(*ctrl)->control_ldosram_core_voltage_ctrl);
+	}
+
+	/*
+	 * Over-ride the register
+	 *	i. unconditionally for all 4430
+	 *	ii. only if un-trimmed for 4460
+	 */
+	if (!readl((*ctrl)->control_efuse_1))
+		writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
+
+	if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
+		writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/* dummy fuction for omap4 */
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+}
+
+void init_omap_revision(void)
+{
+	/*
+	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
+	 * Also, ES1 and ES2 have different ARM revisions
+	 * So use ARM revision for identification
+	 */
+	unsigned int arm_rev = cortex_rev();
+
+	switch (arm_rev) {
+	case MIDR_CORTEX_A9_R0P1:
+		*omap_si_rev = OMAP4430_ES1_0;
+		break;
+	case MIDR_CORTEX_A9_R1P2:
+		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP4_CONTROL_ID_CODE_ES2_0:
+			*omap_si_rev = OMAP4430_ES2_0;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_1:
+			*omap_si_rev = OMAP4430_ES2_1;
+			break;
+		case OMAP4_CONTROL_ID_CODE_ES2_2:
+			*omap_si_rev = OMAP4430_ES2_2;
+			break;
+		default:
+			*omap_si_rev = OMAP4430_ES2_0;
+			break;
+		}
+		break;
+	case MIDR_CORTEX_A9_R1P3:
+		*omap_si_rev = OMAP4430_ES2_3;
+		break;
+	case MIDR_CORTEX_A9_R2P10:
+		switch (readl(CONTROL_ID_CODE)) {
+		case OMAP4470_CONTROL_ID_CODE_ES1_0:
+			*omap_si_rev = OMAP4470_ES1_0;
+			break;
+		case OMAP4460_CONTROL_ID_CODE_ES1_1:
+			*omap_si_rev = OMAP4460_ES1_1;
+			break;
+		case OMAP4460_CONTROL_ID_CODE_ES1_0:
+		default:
+			*omap_si_rev = OMAP4460_ES1_0;
+			break;
+		}
+		break;
+	default:
+		*omap_si_rev = OMAP4430_SILICON_ID_INVALID;
+		break;
+	}
+}
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+void v7_outer_cache_enable(void)
+{
+	set_pl310_ctrl_reg(1);
+}
+
+void v7_outer_cache_disable(void)
+{
+	set_pl310_ctrl_reg(0);
+}
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/prcm-regs.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/prcm-regs.c
new file mode 100644
index 000000000..1ed146b44
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -0,0 +1,302 @@
+/*
+ *
+ * HW regs data for OMAP4
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/omap_common.h>
+
+struct prcm_regs const omap4_prcm = {
+	/* cm1.ckgen */
+	.cm_clksel_core  = 0x4a004100,
+	.cm_clksel_abe = 0x4a004108,
+	.cm_dll_ctrl = 0x4a004110,
+	.cm_clkmode_dpll_core = 0x4a004120,
+	.cm_idlest_dpll_core = 0x4a004124,
+	.cm_autoidle_dpll_core = 0x4a004128,
+	.cm_clksel_dpll_core = 0x4a00412c,
+	.cm_div_m2_dpll_core = 0x4a004130,
+	.cm_div_m3_dpll_core = 0x4a004134,
+	.cm_div_m4_dpll_core = 0x4a004138,
+	.cm_div_m5_dpll_core = 0x4a00413c,
+	.cm_div_m6_dpll_core = 0x4a004140,
+	.cm_div_m7_dpll_core = 0x4a004144,
+	.cm_ssc_deltamstep_dpll_core = 0x4a004148,
+	.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+	.cm_emu_override_dpll_core = 0x4a004150,
+	.cm_clkmode_dpll_mpu = 0x4a004160,
+	.cm_idlest_dpll_mpu = 0x4a004164,
+	.cm_autoidle_dpll_mpu = 0x4a004168,
+	.cm_clksel_dpll_mpu = 0x4a00416c,
+	.cm_div_m2_dpll_mpu = 0x4a004170,
+	.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+	.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+	.cm_bypclk_dpll_mpu = 0x4a00419c,
+	.cm_clkmode_dpll_iva = 0x4a0041a0,
+	.cm_idlest_dpll_iva = 0x4a0041a4,
+	.cm_autoidle_dpll_iva = 0x4a0041a8,
+	.cm_clksel_dpll_iva = 0x4a0041ac,
+	.cm_div_m4_dpll_iva = 0x4a0041b8,
+	.cm_div_m5_dpll_iva = 0x4a0041bc,
+	.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+	.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+	.cm_bypclk_dpll_iva = 0x4a0041dc,
+	.cm_clkmode_dpll_abe = 0x4a0041e0,
+	.cm_idlest_dpll_abe = 0x4a0041e4,
+	.cm_autoidle_dpll_abe = 0x4a0041e8,
+	.cm_clksel_dpll_abe = 0x4a0041ec,
+	.cm_div_m2_dpll_abe = 0x4a0041f0,
+	.cm_div_m3_dpll_abe = 0x4a0041f4,
+	.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+	.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+	.cm_clkmode_dpll_ddrphy = 0x4a004220,
+	.cm_idlest_dpll_ddrphy = 0x4a004224,
+	.cm_autoidle_dpll_ddrphy = 0x4a004228,
+	.cm_clksel_dpll_ddrphy = 0x4a00422c,
+	.cm_div_m2_dpll_ddrphy = 0x4a004230,
+	.cm_div_m4_dpll_ddrphy = 0x4a004238,
+	.cm_div_m5_dpll_ddrphy = 0x4a00423c,
+	.cm_div_m6_dpll_ddrphy = 0x4a004240,
+	.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+	.cm_shadow_freq_config1 = 0x4a004260,
+	.cm_mpu_mpu_clkctrl = 0x4a004320,
+
+	/* cm1.dsp */
+	.cm_dsp_clkstctrl = 0x4a004400,
+	.cm_dsp_dsp_clkctrl = 0x4a004420,
+
+	/* cm1.abe */
+	.cm1_abe_clkstctrl = 0x4a004500,
+	.cm1_abe_l4abe_clkctrl = 0x4a004520,
+	.cm1_abe_aess_clkctrl = 0x4a004528,
+	.cm1_abe_pdm_clkctrl = 0x4a004530,
+	.cm1_abe_dmic_clkctrl = 0x4a004538,
+	.cm1_abe_mcasp_clkctrl = 0x4a004540,
+	.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+	.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+	.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+	.cm1_abe_slimbus_clkctrl = 0x4a004560,
+	.cm1_abe_timer5_clkctrl = 0x4a004568,
+	.cm1_abe_timer6_clkctrl = 0x4a004570,
+	.cm1_abe_timer7_clkctrl = 0x4a004578,
+	.cm1_abe_timer8_clkctrl = 0x4a004580,
+	.cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+	/* cm2.ckgen */
+	.cm_clksel_mpu_m3_iss_root = 0x4a008100,
+	.cm_clksel_usb_60mhz = 0x4a008104,
+	.cm_scale_fclk = 0x4a008108,
+	.cm_core_dvfs_perf1 = 0x4a008110,
+	.cm_core_dvfs_perf2 = 0x4a008114,
+	.cm_core_dvfs_perf3 = 0x4a008118,
+	.cm_core_dvfs_perf4 = 0x4a00811c,
+	.cm_core_dvfs_current = 0x4a008124,
+	.cm_iva_dvfs_perf_tesla = 0x4a008128,
+	.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+	.cm_iva_dvfs_perf_abe = 0x4a008130,
+	.cm_iva_dvfs_current = 0x4a008138,
+	.cm_clkmode_dpll_per = 0x4a008140,
+	.cm_idlest_dpll_per = 0x4a008144,
+	.cm_autoidle_dpll_per = 0x4a008148,
+	.cm_clksel_dpll_per = 0x4a00814c,
+	.cm_div_m2_dpll_per = 0x4a008150,
+	.cm_div_m3_dpll_per = 0x4a008154,
+	.cm_div_m4_dpll_per = 0x4a008158,
+	.cm_div_m5_dpll_per = 0x4a00815c,
+	.cm_div_m6_dpll_per = 0x4a008160,
+	.cm_div_m7_dpll_per = 0x4a008164,
+	.cm_ssc_deltamstep_dpll_per = 0x4a008168,
+	.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+	.cm_emu_override_dpll_per = 0x4a008170,
+	.cm_clkmode_dpll_usb = 0x4a008180,
+	.cm_idlest_dpll_usb = 0x4a008184,
+	.cm_autoidle_dpll_usb = 0x4a008188,
+	.cm_clksel_dpll_usb = 0x4a00818c,
+	.cm_div_m2_dpll_usb = 0x4a008190,
+	.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+	.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+	.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+	.cm_clkmode_dpll_unipro = 0x4a0081c0,
+	.cm_idlest_dpll_unipro = 0x4a0081c4,
+	.cm_autoidle_dpll_unipro = 0x4a0081c8,
+	.cm_clksel_dpll_unipro = 0x4a0081cc,
+	.cm_div_m2_dpll_unipro = 0x4a0081d0,
+	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+
+	/* cm2.core */
+	.cm_l3_1_clkstctrl = 0x4a008700,
+	.cm_l3_1_dynamicdep = 0x4a008708,
+	.cm_l3_1_l3_1_clkctrl = 0x4a008720,
+	.cm_l3_2_clkstctrl = 0x4a008800,
+	.cm_l3_2_dynamicdep = 0x4a008808,
+	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
+	.cm_l3_gpmc_clkctrl = 0x4a008828,
+	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+	.cm_mpu_m3_clkstctrl = 0x4a008900,
+	.cm_mpu_m3_staticdep = 0x4a008904,
+	.cm_mpu_m3_dynamicdep = 0x4a008908,
+	.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+	.cm_sdma_clkstctrl = 0x4a008a00,
+	.cm_sdma_staticdep = 0x4a008a04,
+	.cm_sdma_dynamicdep = 0x4a008a08,
+	.cm_sdma_sdma_clkctrl = 0x4a008a20,
+	.cm_memif_clkstctrl = 0x4a008b00,
+	.cm_memif_dmm_clkctrl = 0x4a008b20,
+	.cm_memif_emif_fw_clkctrl = 0x4a008b28,
+	.cm_memif_emif_1_clkctrl = 0x4a008b30,
+	.cm_memif_emif_2_clkctrl = 0x4a008b38,
+	.cm_memif_dll_clkctrl = 0x4a008b40,
+	.cm_memif_emif_h1_clkctrl = 0x4a008b50,
+	.cm_memif_emif_h2_clkctrl = 0x4a008b58,
+	.cm_memif_dll_h_clkctrl = 0x4a008b60,
+	.cm_c2c_clkstctrl = 0x4a008c00,
+	.cm_c2c_staticdep = 0x4a008c04,
+	.cm_c2c_dynamicdep = 0x4a008c08,
+	.cm_c2c_sad2d_clkctrl = 0x4a008c20,
+	.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+	.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+	.cm_l4cfg_clkstctrl = 0x4a008d00,
+	.cm_l4cfg_dynamicdep = 0x4a008d08,
+	.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+	.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+	.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+	.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+	.cm_l3instr_clkstctrl = 0x4a008e00,
+	.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+	.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+	.cm_l3instr_intrconn_wp1_clkct = 0x4a008e40,
+	.cm_ivahd_clkstctrl = 0x4a008f00,
+
+	/* cm2.ivahd */
+	.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
+	.cm_ivahd_sl2_clkctrl = 0x4a008f28,
+
+	/* cm2.cam */
+	.cm_cam_clkstctrl = 0x4a009000,
+	.cm_cam_iss_clkctrl = 0x4a009020,
+	.cm_cam_fdif_clkctrl = 0x4a009028,
+
+	/* cm2.dss */
+	.cm_dss_clkstctrl = 0x4a009100,
+	.cm_dss_dss_clkctrl = 0x4a009120,
+
+	/* cm2.sgx */
+	.cm_sgx_clkstctrl = 0x4a009200,
+	.cm_sgx_sgx_clkctrl = 0x4a009220,
+
+	/* cm2.l3init */
+	.cm_l3init_clkstctrl = 0x4a009300,
+	.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
+	.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
+	.cm_l3init_hsi_clkctrl = 0x4a009338,
+	.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
+	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
+	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
+	.cm_l3init_p1500_clkctrl = 0x4a009378,
+	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
+	.cm_l3init_usbphy_clkctrl = 0x4a0093e0,
+
+	/* cm2.l4per */
+	.cm_l4per_clkstctrl = 0x4a009400,
+	.cm_l4per_dynamicdep = 0x4a009408,
+	.cm_l4per_adc_clkctrl = 0x4a009420,
+	.cm_l4per_gptimer10_clkctrl = 0x4a009428,
+	.cm_l4per_gptimer11_clkctrl = 0x4a009430,
+	.cm_l4per_gptimer2_clkctrl = 0x4a009438,
+	.cm_l4per_gptimer3_clkctrl = 0x4a009440,
+	.cm_l4per_gptimer4_clkctrl = 0x4a009448,
+	.cm_l4per_gptimer9_clkctrl = 0x4a009450,
+	.cm_l4per_elm_clkctrl = 0x4a009458,
+	.cm_l4per_gpio2_clkctrl = 0x4a009460,
+	.cm_l4per_gpio3_clkctrl = 0x4a009468,
+	.cm_l4per_gpio4_clkctrl = 0x4a009470,
+	.cm_l4per_gpio5_clkctrl = 0x4a009478,
+	.cm_l4per_gpio6_clkctrl = 0x4a009480,
+	.cm_l4per_hdq1w_clkctrl = 0x4a009488,
+	.cm_l4per_hecc1_clkctrl = 0x4a009490,
+	.cm_l4per_hecc2_clkctrl = 0x4a009498,
+	.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
+	.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
+	.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
+	.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
+	.cm_l4per_l4per_clkctrl = 0x4a0094c0,
+	.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
+	.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
+	.cm_l4per_mcbsp4_clkctrl = 0x4a0094e0,
+	.cm_l4per_mgate_clkctrl = 0x4a0094e8,
+	.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
+	.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
+	.cm_l4per_mcspi3_clkctrl = 0x4a009500,
+	.cm_l4per_mcspi4_clkctrl = 0x4a009508,
+	.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
+	.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
+	.cm_l4per_msprohg_clkctrl = 0x4a009530,
+	.cm_l4per_slimbus2_clkctrl = 0x4a009538,
+	.cm_l4per_uart1_clkctrl = 0x4a009540,
+	.cm_l4per_uart2_clkctrl = 0x4a009548,
+	.cm_l4per_uart3_clkctrl = 0x4a009550,
+	.cm_l4per_uart4_clkctrl = 0x4a009558,
+	.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
+	.cm_l4per_i2c5_clkctrl = 0x4a009568,
+	.cm_l4sec_clkstctrl = 0x4a009580,
+	.cm_l4sec_staticdep = 0x4a009584,
+	.cm_l4sec_dynamicdep = 0x4a009588,
+	.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
+	.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
+	.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
+	.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
+	.cm_l4sec_rng_clkctrl = 0x4a0095c0,
+	.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
+	.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
+
+	/* l4 wkup regs */
+	.cm_abe_pll_ref_clksel = 0x4a30610c,
+	.cm_sys_clksel = 0x4a306110,
+	.cm_wkup_clkstctrl = 0x4a307800,
+	.cm_wkup_l4wkup_clkctrl = 0x4a307820,
+	.cm_wkup_wdtimer1_clkctrl = 0x4a307828,
+	.cm_wkup_wdtimer2_clkctrl = 0x4a307830,
+	.cm_wkup_gpio1_clkctrl = 0x4a307838,
+	.cm_wkup_gptimer1_clkctrl = 0x4a307840,
+	.cm_wkup_gptimer12_clkctrl = 0x4a307848,
+	.cm_wkup_synctimer_clkctrl = 0x4a307850,
+	.cm_wkup_usim_clkctrl = 0x4a307858,
+	.cm_wkup_sarram_clkctrl = 0x4a307860,
+	.cm_wkup_keyboard_clkctrl = 0x4a307878,
+	.cm_wkup_rtc_clkctrl = 0x4a307880,
+	.cm_wkup_bandgap_clkctrl = 0x4a307888,
+	.prm_vc_val_bypass = 0x4a307ba0,
+	.prm_vc_cfg_channel = 0x4a307ba4,
+	.prm_vc_cfg_i2c_mode = 0x4a307ba8,
+	.prm_vc_cfg_i2c_clk = 0x4a307bac,
+};
+
+struct omap_sys_ctrl_regs const omap4_ctrl = {
+	.control_id_code			= 0x4A002204,
+	.control_std_fuse_opp_bgap		= 0x4a002260,
+	.control_status				= 0x4a0022c4,
+	.control_ldosram_iva_voltage_ctrl	= 0x4A002320,
+	.control_ldosram_mpu_voltage_ctrl	= 0x4A002324,
+	.control_ldosram_core_voltage_ctrl	= 0x4A002328,
+	.control_usbotghs_ctrl			= 0x4A00233C,
+	.control_padconf_core_base		= 0x4A100000,
+	.control_pbiaslite			= 0x4A100600,
+	.control_lpddr2io1_0			= 0x4A100638,
+	.control_lpddr2io1_1			= 0x4A10063C,
+	.control_lpddr2io1_2			= 0x4A100640,
+	.control_lpddr2io1_3			= 0x4A100644,
+	.control_lpddr2io2_0			= 0x4A100648,
+	.control_lpddr2io2_1			= 0x4A10064C,
+	.control_lpddr2io2_2			= 0x4A100650,
+	.control_lpddr2io2_3			= 0x4A100654,
+	.control_efuse_1			= 0x4A100700,
+	.control_efuse_2			= 0x4A100704,
+	.control_padconf_wkup_base		= 0x4A31E000,
+};
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/sdram_elpida.c
new file mode 100644
index 000000000..6903696e1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -0,0 +1,328 @@
+/*
+ * Timing and Organization details of the Elpida parts used in OMAP4
+ * SDPs and Panda
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/emif.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
+ * SDP and Panda. Since the parts used and geometry are identical for
+ * SDP and Panda for a given OMAP4 revision, this information is kept
+ * here instead of being in board directory. However the key functions
+ * exported are weakly linked so that they can be over-ridden in the board
+ * directory if there is a OMAP4 board in the future that uses a different
+ * memory device or geometry.
+ *
+ * For any new board with different memory devices over-ride one or more
+ * of the following functions as per the CONFIG flags you intend to enable:
+ * - emif_get_reg_dump()
+ * - emif_get_dmm_regs()
+ * - emif_get_device_details()
+ * - emif_get_device_timings()
+ */
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
+const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x0000030c,
+	.sdram_tim1			= 0x08648311,
+	.sdram_tim2			= 0x101b06ca,
+	.sdram_tim3			= 0x0048a19f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff808
+};
+
+const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+	.sdram_config_init		= 0x80000eb1,
+	.sdram_config			= 0x80001ab1,
+	.ref_ctrl			= 0x000005cd,
+	.sdram_tim1			= 0x10cb0622,
+	.sdram_tim2			= 0x20350d52,
+	.sdram_tim3			= 0x00b1431f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
+	.sdram_config_init		= 0x80800eb2,
+	.sdram_config			= 0x80801ab2,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3215,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0xd00b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80540300,
+	.is_ma_present	= 0x0
+};
+
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80640300,
+	.is_ma_present	= 0x0
+};
+
+const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0xFF020100,
+	.dmm_lisa_map_1 = 0,
+	.dmm_lisa_map_2 = 0,
+	.dmm_lisa_map_3 = 0x80640300,
+	.is_ma_present	= 0x1
+};
+
+static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
+{
+	u32 omap4_rev = omap_revision();
+
+	/* Same devices and geometry on both EMIFs */
+	if (omap4_rev == OMAP4430_ES1_0)
+		*regs = &emif_regs_elpida_380_mhz_1cs;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		*regs = &emif_regs_elpida_200_mhz_2cs;
+	else if (omap4_rev == OMAP4430_ES2_3)
+		*regs = &emif_regs_elpida_400_mhz_1cs;
+	else if (omap4_rev < OMAP4470_ES1_0)
+		*regs = &emif_regs_elpida_400_mhz_2cs;
+	else
+		*regs = &emif_regs_elpida_400_mhz_1cs;
+}
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
+{
+	u32 omap_rev = omap_revision();
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+	else if (omap_rev == OMAP4430_ES2_3)
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+	else if (omap_rev < OMAP4460_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+	else
+		*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+
+#else
+
+static const struct lpddr2_device_details elpida_2G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_2Gb,
+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+};
+
+static const struct lpddr2_device_details elpida_4G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_4Gb,
+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+};
+
+struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
+{
+	u32 omap_rev = omap_revision();
+
+	/* EMIF1 & EMIF2 have identical configuration */
+	if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
+		&& (cs == CS1)) {
+		/* Nothing connected on CS1 for 4430/4470 ES1.0 */
+		return NULL;
+	} else if (omap_rev < OMAP4470_ES1_0) {
+		/* In all other 4430/4460 cases Elpida 2G device */
+		*lpddr2_dev_details = elpida_2G_S4_details;
+	} else {
+		/* 4470: 4G device */
+		*lpddr2_dev_details = elpida_4G_S4_details;
+	}
+	return lpddr2_dev_details;
+}
+
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
+	__attribute__((weak, alias("emif_get_device_details_sdp")));
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
+	.max_freq	= 400000000,
+	.RL		= 6,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
+	.max_freq	= 333000000,
+	.RL		= 5,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
+	.max_freq	= 200000000,
+	.RL		= 3,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 20,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_min_tck min_tck_elpida = {
+	.tRL		= 3,
+	.tRP_AB		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRAS_MIN	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+
+static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
+		&timings_elpida_200_mhz,
+		&timings_elpida_333_mhz,
+		&timings_elpida_400_mhz
+};
+
+static const struct lpddr2_device_timings elpida_2G_S4_timings = {
+	.ac_timings	= elpida_ac_timings,
+	.min_tck	= &min_tck_elpida,
+};
+
+void emif_get_device_timings_sdp(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	u32 omap_rev = omap_revision();
+
+	/* Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &elpida_2G_S4_timings;
+
+	if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
+		*cs1_device_timings = NULL;
+	else
+		*cs1_device_timings = &elpida_2G_S4_timings;
+}
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+	__attribute__((weak, alias("emif_get_device_timings_sdp")));
+
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+
+const struct lpddr2_mr_regs mr_regs = {
+	.mr1	= MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
+	.mr2	= 0x4,
+	.mr3	= -1,
+	.mr10	= MR10_ZQ_ZQINIT,
+	.mr16	= MR16_REF_FULL_ARRAY
+};
+
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
+{
+	*regs = &mr_regs;
+}
+
+__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/Makefile
new file mode 100644
index 000000000..64c68791f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= hwinit.o
+obj-y	+= emif.o
+obj-y	+= sdram.o
+obj-y	+= prcm-regs.o
+obj-y	+= hw_data.o
+obj-y	+= abb.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/abb.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/abb.c
new file mode 100644
index 000000000..3bf88979e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/abb.c
@@ -0,0 +1,57 @@
+/*
+ * Adaptive Body Bias programming sequence for OMAP5 family
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/io.h>
+
+/*
+ * Setup LDOVBB for OMAP5.
+ * On OMAP5+ some ABB settings are fused. They are handled
+ * in the following way:
+ *
+ * 1. corresponding EFUSE register contains ABB enable bit
+ *    and VSET value
+ * 2. If ABB enable bit is set to 1, than ABB should be
+ *    enabled, otherwise ABB should be disabled
+ * 3. If ABB is enabled, than VSET value should be copied
+ *    to corresponding MUX control register
+ */
+s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
+{
+	u32 vset;
+	u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
+	u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
+
+	if (!is_omap54xx()) {
+		/* DRA7 */
+		fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
+		fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
+	}
+	/*
+	 * ABB parameters must be properly fused
+	 * otherwise ABB should be disabled
+	 */
+	vset = readl(fuse);
+	if (!(vset & fuse_enable_mask))
+		return -1;
+
+	/* prepare VSET value for LDOVBB mux register */
+	vset &= fuse_vset_mask;
+	vset >>= ffs(fuse_vset_mask) - 1;
+	vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
+	vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
+
+	/* setup LDOVBB using fused value */
+	clrsetbits_le32(ldovbb,  OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset);
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/config.mk b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/config.mk
new file mode 100644
index 000000000..ef2725aff
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/config.mk
@@ -0,0 +1,13 @@
+#
+# Copyright 2011 Linaro Limited
+#
+# Aneesh V <annesh@ti.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= MLO
+else
+ALL-y	+= u-boot.img
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/emif.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/emif.c
new file mode 100644
index 000000000..b1203a37a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/emif.c
@@ -0,0 +1,88 @@
+/*
+ * EMIF programming
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com> for OMAP4
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/emif.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/utils.h>
+
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
+static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
+#endif
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+/* Base AC Timing values specified by JESD209-2 for 532MHz operation */
+static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
+	.max_freq = 532000000,
+	.RL = 8,
+	.tRPab = 21,
+	.tRCD = 18,
+	.tWR = 15,
+	.tRASmin = 42,
+	.tRRD = 10,
+	.tWTRx2 = 15,
+	.tXSR = 140,
+	.tXPx2 = 15,
+	.tRFCab = 130,
+	.tRTPx2 = 15,
+	.tCKE = 3,
+	.tCKESR = 15,
+	.tZQCS = 90,
+	.tZQCL = 360,
+	.tZQINIT = 1000,
+	.tDQSCKMAXx2 = 11,
+	.tRASmax = 70,
+	.tFAW = 50
+};
+
+/*
+ * Min tCK values specified by JESD209-2
+ * Min tCK specifies the minimum duration of some AC timing parameters in terms
+ * of the number of cycles. If the calculated number of cycles based on the
+ * absolute time value is less than the min tCK value, min tCK value should
+ * be used instead. This typically happens at low frequencies.
+ */
+static const struct lpddr2_min_tck min_tck_jedec = {
+	.tRL = 3,
+	.tRP_AB = 3,
+	.tRCD = 3,
+	.tWR = 3,
+	.tRAS_MIN = 3,
+	.tRRD = 2,
+	.tWTR = 2,
+	.tXP = 2,
+	.tRTP = 2,
+	.tCKE = 3,
+	.tCKESR = 3,
+	.tFAW = 8
+};
+
+static const struct lpddr2_ac_timings const*
+			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+	&timings_jedec_532_mhz
+};
+
+static const struct lpddr2_device_timings jedec_default_timings = {
+	.ac_timings = jedec_ac_timings,
+	.min_tck = &min_tck_jedec
+};
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	/* Assume Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &jedec_default_timings;
+	*cs1_device_timings = NULL;
+}
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/hw_data.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/hw_data.c
new file mode 100644
index 000000000..ad971327b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -0,0 +1,589 @@
+/*
+ *
+ * HW data initialization for OMAP5
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <palmas.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clock.h>
+#include <asm/omap_gpio.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+struct prcm_regs const **prcm =
+			(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
+struct dplls const **dplls_data =
+			(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
+struct vcores_data const **omap_vcores =
+		(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
+struct omap_sys_ctrl_regs const **ctrl =
+	(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
+
+/* OPP HIGH FREQUENCY for ES2.0 */
+static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
+	{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* OPP NOM FREQUENCY for ES1.0 */
+static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
+	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* OPP LOW FREQUENCY for ES1.0 */
+static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
+	{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* OPP LOW FREQUENCY for ES2.0 */
+static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
+	{499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
+static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
+	{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
+	{119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
+};
+
+static const struct dpll_params
+			core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
+	{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 16.8 MHz */
+	{277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 19.2 MHz */
+	{368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params
+			core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
+	{266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 16.8 MHz */
+	{277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 19.2 MHz */
+	{368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}		/* 38.4 MHz */
+};
+
+static const struct dpll_params
+		core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
+	{266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 12 MHz   */
+	{266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 20 MHz   */
+	{443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 16.8 MHz */
+	{277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 19.2 MHz */
+	{368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 38.4 MHz */
+};
+
+static const struct dpll_params
+			core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
+	{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 16.8 MHz */
+	{277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 19.2 MHz */
+	{368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params
+			core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
+	{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 16.8 MHz */
+	{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 19.2 MHz */
+	{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}		/* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
+	{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 16.8 MHz */
+	{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 19.2 MHz */
+	{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
+	{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 16.8 MHz */
+	{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 19.2 MHz */
+	{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
+	{32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 12 MHz   */
+	{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 16.8 MHz */
+	{20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 19.2 MHz */
+	{192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
+	{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
+	{1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz */
+	{208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+	{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+/* ABE M & N values with sysclk2(22.5792 MHz) as input */
+static const struct dpll_params
+		abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+	{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 20 MHz   */
+	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
+};
+
+static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
+	{266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
+	{190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
+};
+
+static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
+	{250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 20 MHz   */
+	{119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 38.4 MHz */
+};
+
+struct dplls omap5_dplls_es1 = {
+	.mpu = mpu_dpll_params_800mhz,
+	.core = core_dpll_params_2128mhz_ddr532,
+	.per = per_dpll_params_768mhz,
+	.iva = iva_dpll_params_2330mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	.abe = abe_dpll_params_sysclk_196608khz,
+#else
+	.abe = &abe_dpll_params_32k_196608khz,
+#endif
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = NULL
+};
+
+struct dplls omap5_dplls_es2 = {
+	.mpu = mpu_dpll_params_1ghz,
+	.core = core_dpll_params_2128mhz_ddr532_es2,
+	.per = per_dpll_params_768mhz_es2,
+	.iva = iva_dpll_params_2330mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	.abe = abe_dpll_params_sysclk_196608khz,
+#else
+	.abe = &abe_dpll_params_32k_196608khz,
+#endif
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = NULL
+};
+
+struct dplls dra7xx_dplls = {
+	.mpu = mpu_dpll_params_1ghz,
+	.core = core_dpll_params_2128mhz_dra7xx,
+	.per = per_dpll_params_768mhz_dra7xx,
+	.abe = abe_dpll_params_sysclk2_361267khz,
+	.iva = iva_dpll_params_2330mhz_dra7xx,
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = ddr_dpll_params_2128mhz,
+	.gmac = gmac_dpll_params_2000mhz,
+};
+
+struct pmic_data palmas = {
+	.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+	.step = 10000, /* 10 mV represented in uV */
+	/*
+	 * Offset codes 1-6 all give the base voltage in Palmas
+	 * Offset code 0 switches OFF the SMPS
+	 */
+	.start_code = 6,
+	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
+	.pmic_bus_init	= sri2c_init,
+	.pmic_write	= omap_vc_bypass_send_value,
+};
+
+struct pmic_data tps659038 = {
+	.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+	.step = 10000, /* 10 mV represented in uV */
+	/*
+	 * Offset codes 1-6 all give the base voltage in Palmas
+	 * Offset code 0 switches OFF the SMPS
+	 */
+	.start_code = 6,
+	.i2c_slave_addr	= TPS659038_I2C_SLAVE_ADDR,
+	.pmic_bus_init	= gpi2c_init,
+	.pmic_write	= palmas_i2c_write_u8,
+};
+
+struct vcores_data omap5430_volts = {
+	.mpu.value = VDD_MPU,
+	.mpu.addr = SMPS_REG_ADDR_12_MPU,
+	.mpu.pmic = &palmas,
+
+	.core.value = VDD_CORE,
+	.core.addr = SMPS_REG_ADDR_8_CORE,
+	.core.pmic = &palmas,
+
+	.mm.value = VDD_MM,
+	.mm.addr = SMPS_REG_ADDR_45_IVA,
+	.mm.pmic = &palmas,
+};
+
+struct vcores_data omap5430_volts_es2 = {
+	.mpu.value = VDD_MPU_ES2,
+	.mpu.addr = SMPS_REG_ADDR_12_MPU,
+	.mpu.pmic = &palmas,
+
+	.core.value = VDD_CORE_ES2,
+	.core.addr = SMPS_REG_ADDR_8_CORE,
+	.core.pmic = &palmas,
+
+	.mm.value = VDD_MM_ES2,
+	.mm.addr = SMPS_REG_ADDR_45_IVA,
+	.mm.pmic = &palmas,
+};
+
+struct vcores_data dra752_volts = {
+	.mpu.value	= VDD_MPU_DRA752,
+	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.mpu.addr	= TPS659038_REG_ADDR_SMPS12_MPU,
+	.mpu.pmic	= &tps659038,
+
+	.eve.value	= VDD_EVE_DRA752,
+	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr	= TPS659038_REG_ADDR_SMPS45_EVE,
+	.eve.pmic	= &tps659038,
+
+	.gpu.value	= VDD_GPU_DRA752,
+	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr	= TPS659038_REG_ADDR_SMPS6_GPU,
+	.gpu.pmic	= &tps659038,
+
+	.core.value	= VDD_CORE_DRA752,
+	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= TPS659038_REG_ADDR_SMPS7_CORE,
+	.core.pmic	= &tps659038,
+
+	.iva.value	= VDD_IVA_DRA752,
+	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr	= TPS659038_REG_ADDR_SMPS8_IVA,
+	.iva.pmic	= &tps659038,
+};
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+	u32 const clk_domains_essential[] = {
+		(*prcm)->cm_l4per_clkstctrl,
+		(*prcm)->cm_l3init_clkstctrl,
+		(*prcm)->cm_memif_clkstctrl,
+		(*prcm)->cm_l4cfg_clkstctrl,
+#ifdef CONFIG_DRIVER_TI_CPSW
+		(*prcm)->cm_gmac_clkstctrl,
+#endif
+		0
+	};
+
+	u32 const clk_modules_hw_auto_essential[] = {
+		(*prcm)->cm_l3_gpmc_clkctrl,
+		(*prcm)->cm_memif_emif_1_clkctrl,
+		(*prcm)->cm_memif_emif_2_clkctrl,
+		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
+		(*prcm)->cm_wkup_gpio1_clkctrl,
+		(*prcm)->cm_l4per_gpio2_clkctrl,
+		(*prcm)->cm_l4per_gpio3_clkctrl,
+		(*prcm)->cm_l4per_gpio4_clkctrl,
+		(*prcm)->cm_l4per_gpio5_clkctrl,
+		(*prcm)->cm_l4per_gpio6_clkctrl,
+		(*prcm)->cm_l4per_gpio7_clkctrl,
+		(*prcm)->cm_l4per_gpio8_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_essential[] = {
+		(*prcm)->cm_wkup_gptimer1_clkctrl,
+		(*prcm)->cm_l3init_hsmmc1_clkctrl,
+		(*prcm)->cm_l3init_hsmmc2_clkctrl,
+		(*prcm)->cm_l4per_gptimer2_clkctrl,
+		(*prcm)->cm_wkup_wdtimer2_clkctrl,
+		(*prcm)->cm_l4per_uart3_clkctrl,
+		(*prcm)->cm_l4per_i2c1_clkctrl,
+#ifdef CONFIG_DRIVER_TI_CPSW
+		(*prcm)->cm_gmac_gmac_clkctrl,
+#endif
+
+#ifdef CONFIG_TI_QSPI
+		(*prcm)->cm_l4per_qspi_clkctrl,
+#endif
+		0
+	};
+
+	/* Enable optional additional functional clock for GPIO4 */
+	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
+			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+	/* Enable 96 MHz clock for MMC1 & MMC2 */
+	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_MASK);
+
+	/* Set the correct clock dividers for mmc */
+	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+
+	/* Select 32KHz clock as the source of GPTIMER1 */
+	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
+			GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+	do_enable_clocks(clk_domains_essential,
+			 clk_modules_hw_auto_essential,
+			 clk_modules_explicit_en_essential,
+			 1);
+
+#ifdef CONFIG_TI_QSPI
+	setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
+	/* Enable SCRM OPT clocks for PER and CORE dpll */
+	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
+			OPTFCLKEN_SCRM_PER_MASK);
+	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
+			OPTFCLKEN_SCRM_CORE_MASK);
+}
+
+void enable_basic_uboot_clocks(void)
+{
+	u32 const clk_domains_essential[] = {
+		0
+	};
+
+	u32 const clk_modules_hw_auto_essential[] = {
+		(*prcm)->cm_l3init_hsusbtll_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_essential[] = {
+		(*prcm)->cm_l4per_mcspi1_clkctrl,
+		(*prcm)->cm_l4per_i2c2_clkctrl,
+		(*prcm)->cm_l4per_i2c3_clkctrl,
+		(*prcm)->cm_l4per_i2c4_clkctrl,
+		(*prcm)->cm_l4per_i2c5_clkctrl,
+		(*prcm)->cm_l3init_hsusbhost_clkctrl,
+		(*prcm)->cm_l3init_fsusb_clkctrl,
+		0
+	};
+	do_enable_clocks(clk_domains_essential,
+			 clk_modules_hw_auto_essential,
+			 clk_modules_explicit_en_essential,
+			 1);
+}
+
+const struct ctrl_ioregs ioregs_omap5430 = {
+	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+	.ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+	.ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+	.ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es1 = {
+	.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+	.ctrl_lpddr2ch = 0x0,
+	.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+	.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+	.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es2 = {
+	.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+	.ctrl_lpddr2ch = 0x0,
+	.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+	.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
+	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
+	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
+	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+	.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+};
+
+const struct ctrl_ioregs ioregs_dra7xx_es1 = {
+	.ctrl_ddrch = 0x40404040,
+	.ctrl_lpddr2ch = 0x40404040,
+	.ctrl_ddr3ch = 0x80808080,
+	.ctrl_ddrio_0 = 0xA2084210,
+	.ctrl_ddrio_1 = 0x84210840,
+	.ctrl_ddrio_2 = 0x84210000,
+	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
+	.ctrl_emif_sdram_config_ext_final = 0x000101A7,
+	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+
+void hw_data_init(void)
+{
+	u32 omap_rev = omap_revision();
+
+	switch (omap_rev) {
+
+	case OMAP5430_ES1_0:
+	case OMAP5432_ES1_0:
+	*prcm = &omap5_es1_prcm;
+	*dplls_data = &omap5_dplls_es1;
+	*omap_vcores = &omap5430_volts;
+	*ctrl = &omap5_ctrl;
+	break;
+
+	case OMAP5430_ES2_0:
+	case OMAP5432_ES2_0:
+	*prcm = &omap5_es2_prcm;
+	*dplls_data = &omap5_dplls_es2;
+	*omap_vcores = &omap5430_volts_es2;
+	*ctrl = &omap5_ctrl;
+	break;
+
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+	*prcm = &dra7xx_prcm;
+	*dplls_data = &dra7xx_dplls;
+	*omap_vcores = &dra752_volts;
+	*ctrl = &dra7xx_ctrl;
+	break;
+
+	default:
+		printf("\n INVALID OMAP REVISION ");
+	}
+}
+
+void get_ioregs(const struct ctrl_ioregs **regs)
+{
+	u32 omap_rev = omap_revision();
+
+	switch (omap_rev) {
+	case OMAP5430_ES1_0:
+	case OMAP5430_ES2_0:
+		*regs = &ioregs_omap5430;
+		break;
+	case OMAP5432_ES1_0:
+		*regs = &ioregs_omap5432_es1;
+		break;
+	case OMAP5432_ES2_0:
+		*regs = &ioregs_omap5432_es2;
+		break;
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+		*regs = &ioregs_dra7xx_es1;
+		break;
+
+	default:
+		printf("\n INVALID OMAP REVISION ");
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/hwinit.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/hwinit.c
new file mode 100644
index 000000000..93feb1623
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -0,0 +1,380 @@
+/*
+ *
+ * Functions for omap5 based boards.
+ *
+ * (C) Copyright 2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Aneesh V	<aneesh@ti.com>
+ *	Steve Sakoman	<steve@sakoman.com>
+ *	Sricharan	<r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <linux/sizes.h>
+#include <asm/utils.h>
+#include <asm/arch/gpio.h>
+#include <asm/emif.h>
+#include <asm/omap_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
+
+static struct gpio_bank gpio_bank_54xx[8] = {
+	{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
+
+#ifdef CONFIG_SPL_BUILD
+/* LPDDR2 specific IO settings */
+static void io_settings_lpddr2(void)
+{
+	const struct ctrl_ioregs *ioregs;
+
+	get_ioregs(&ioregs);
+	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
+	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
+	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
+	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
+	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
+	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
+	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
+	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+}
+
+/* DDR3 specific IO settings */
+static void io_settings_ddr3(void)
+{
+	u32 io_settings = 0;
+	const struct ctrl_ioregs *ioregs;
+
+	get_ioregs(&ioregs);
+	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
+	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
+	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
+
+	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
+	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
+	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
+
+	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
+	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
+	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
+
+	/* omap5432 does not use lpddr2 */
+	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
+	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+
+	writel(ioregs->ctrl_emif_sdram_config_ext,
+	       (*ctrl)->control_emif1_sdram_config_ext);
+	writel(ioregs->ctrl_emif_sdram_config_ext,
+	       (*ctrl)->control_emif2_sdram_config_ext);
+
+	if (is_omap54xx()) {
+		/* Disable DLL select */
+		io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
+							& 0xFFEFFFFF);
+		writel(io_settings,
+			(*ctrl)->control_port_emif1_sdram_config);
+
+		io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
+							& 0xFFEFFFFF);
+		writel(io_settings,
+			(*ctrl)->control_port_emif2_sdram_config);
+	} else {
+		writel(ioregs->ctrl_ddr_ctrl_ext_0,
+				(*ctrl)->control_ddr_control_ext_0);
+	}
+}
+
+/*
+ * Some tuning of IOs for optimal power and performance
+ */
+void do_io_settings(void)
+{
+	u32 io_settings = 0, mask = 0;
+
+	/* Impedance settings EMMC, C2C 1,2, hsi2 */
+	mask = (ds_mask << 2) | (ds_mask << 8) |
+		(ds_mask << 16) | (ds_mask << 18);
+	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
+				(~mask);
+	io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
+			(ds_45_ohm << 18) | (ds_60_ohm << 2);
+	writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
+
+	/* Impedance settings Mcspi2 */
+	mask = (ds_mask << 30);
+	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
+			(~mask);
+	io_settings |= (ds_60_ohm << 30);
+	writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
+
+	/* Impedance settings C2C 3,4 */
+	mask = (ds_mask << 14) | (ds_mask << 16);
+	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
+			(~mask);
+	io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
+	writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
+
+	/* Slew rate settings EMMC, C2C 1,2 */
+	mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
+	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
+			(~mask);
+	io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
+	writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
+
+	/* Slew rate settings hsi2, Mcspi2 */
+	mask = (sc_mask << 24) | (sc_mask << 28);
+	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
+			(~mask);
+	io_settings |= (sc_fast << 28) | (sc_fast << 24);
+	writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
+
+	/* Slew rate settings C2C 3,4 */
+	mask = (sc_mask << 16) | (sc_mask << 18);
+	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
+			(~mask);
+	io_settings |= (sc_na << 16) | (sc_na << 18);
+	writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
+
+	/* impedance and slew rate settings for usb */
+	mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
+		(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
+	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
+			(~mask);
+	io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
+		       (ds_60_ohm << 23) | (sc_fast << 20) |
+		       (sc_fast << 17) | (sc_fast << 14);
+	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
+
+	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+		io_settings_lpddr2();
+	else
+		io_settings_ddr3();
+}
+
+static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
+	{0x45, 0x1},	/* 12 MHz   */
+	{-1, -1},	/* 13 MHz   */
+	{0x63, 0x2},	/* 16.8 MHz */
+	{0x57, 0x2},	/* 19.2 MHz */
+	{0x20, 0x1},	/* 26 MHz   */
+	{-1, -1},	/* 27 MHz   */
+	{0x41, 0x3}	/* 38.4 MHz */
+};
+
+void srcomp_enable(void)
+{
+	u32 srcomp_value, mul_factor, div_factor, clk_val, i;
+	u32 sysclk_ind	= get_sys_clk_index();
+	u32 omap_rev	= omap_revision();
+
+	if (!is_omap54xx())
+		return;
+
+	mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
+	div_factor = srcomp_parameters[sysclk_ind].divide_factor;
+
+	for (i = 0; i < 4; i++) {
+		srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
+		srcomp_value &=
+			~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
+		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
+			(div_factor << DIVIDE_FACTOR_XS_SHIFT);
+		writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
+	}
+
+	if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
+		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
+		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
+
+		for (i = 0; i < 4; i++) {
+			srcomp_value =
+				readl((*ctrl)->control_srcomp_north_side + i*4);
+			srcomp_value &= ~PWRDWN_XS_MASK;
+			writel(srcomp_value,
+			       (*ctrl)->control_srcomp_north_side + i*4);
+
+			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
+				& SRCODE_READ_XS_MASK) >>
+				SRCODE_READ_XS_SHIFT) == 0)
+				;
+
+			srcomp_value =
+				readl((*ctrl)->control_srcomp_north_side + i*4);
+			srcomp_value &= ~OVERRIDE_XS_MASK;
+			writel(srcomp_value,
+			       (*ctrl)->control_srcomp_north_side + i*4);
+		}
+	} else {
+		srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
+		srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
+				  DIVIDE_FACTOR_XS_MASK);
+		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
+				(div_factor << DIVIDE_FACTOR_XS_SHIFT);
+		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+		for (i = 0; i < 4; i++) {
+			srcomp_value =
+				readl((*ctrl)->control_srcomp_north_side + i*4);
+			srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
+			writel(srcomp_value,
+			       (*ctrl)->control_srcomp_north_side + i*4);
+
+			srcomp_value =
+				readl((*ctrl)->control_srcomp_north_side + i*4);
+			srcomp_value &= ~OVERRIDE_XS_MASK;
+			writel(srcomp_value,
+			       (*ctrl)->control_srcomp_north_side + i*4);
+		}
+
+		srcomp_value =
+			readl((*ctrl)->control_srcomp_east_side_wkup);
+		srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
+		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+		srcomp_value =
+			readl((*ctrl)->control_srcomp_east_side_wkup);
+		srcomp_value &= ~OVERRIDE_XS_MASK;
+		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
+		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
+
+		clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
+		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+		writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
+
+		for (i = 0; i < 4; i++) {
+			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
+				& SRCODE_READ_XS_MASK) >>
+				SRCODE_READ_XS_SHIFT) == 0)
+				;
+
+			srcomp_value =
+				readl((*ctrl)->control_srcomp_north_side + i*4);
+			srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
+			writel(srcomp_value,
+			       (*ctrl)->control_srcomp_north_side + i*4);
+		}
+
+		while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
+			SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
+			;
+
+		srcomp_value =
+			readl((*ctrl)->control_srcomp_east_side_wkup);
+		srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
+		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+	}
+}
+#endif
+
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+	const struct ctrl_ioregs *ioregs;
+
+	get_ioregs(&ioregs);
+
+	/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
+	if (emif_base == EMIF1_BASE)
+		writel(ioregs->ctrl_emif_sdram_config_ext_final,
+		       (*ctrl)->control_emif1_sdram_config_ext);
+	else if (emif_base == EMIF2_BASE)
+		writel(ioregs->ctrl_emif_sdram_config_ext_final,
+		       (*ctrl)->control_emif2_sdram_config_ext);
+}
+
+void init_omap_revision(void)
+{
+	/*
+	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
+	 * Also, ES1 and ES2 have different ARM revisions
+	 * So use ARM revision for identification
+	 */
+	unsigned int rev = cortex_rev();
+
+	switch (readl(CONTROL_ID_CODE)) {
+	case OMAP5430_CONTROL_ID_CODE_ES1_0:
+		*omap_si_rev = OMAP5430_ES1_0;
+		if (rev == MIDR_CORTEX_A15_R2P2)
+			*omap_si_rev = OMAP5430_ES2_0;
+		break;
+	case OMAP5432_CONTROL_ID_CODE_ES1_0:
+		*omap_si_rev = OMAP5432_ES1_0;
+		if (rev == MIDR_CORTEX_A15_R2P2)
+			*omap_si_rev = OMAP5432_ES2_0;
+		break;
+	case OMAP5430_CONTROL_ID_CODE_ES2_0:
+		*omap_si_rev = OMAP5430_ES2_0;
+		break;
+	case OMAP5432_CONTROL_ID_CODE_ES2_0:
+		*omap_si_rev = OMAP5432_ES2_0;
+		break;
+	case DRA752_CONTROL_ID_CODE_ES1_0:
+		*omap_si_rev = DRA752_ES1_0;
+		break;
+	case DRA752_CONTROL_ID_CODE_ES1_1:
+		*omap_si_rev = DRA752_ES1_1;
+		break;
+	default:
+		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
+	}
+}
+
+void reset_cpu(ulong ignored)
+{
+	u32 omap_rev = omap_revision();
+
+	/*
+	 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
+	 * So use cold reset in case instead.
+	 */
+	if (omap_rev == OMAP5430_ES1_0)
+		writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
+	else
+		writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
+}
+
+u32 warm_reset(void)
+{
+	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
+}
+
+void setup_warmreset_time(void)
+{
+	u32 rst_time, rst_val;
+
+#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+	rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
+#else
+	rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
+#endif
+	rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
+
+	if (rst_time > RSTTIME1_MASK)
+		rst_time = RSTTIME1_MASK;
+
+	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
+	rst_val |= rst_time;
+	writel(rst_val, (*prcm)->prm_rsttime);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/prcm-regs.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/prcm-regs.c
new file mode 100644
index 000000000..7292161f3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -0,0 +1,978 @@
+/*
+ *
+ * HW regs data for OMAP5 Soc
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/omap_common.h>
+
+struct prcm_regs const omap5_es1_prcm = {
+	/* cm1.ckgen */
+	.cm_clksel_core = 0x4a004100,
+	.cm_clksel_abe = 0x4a004108,
+	.cm_dll_ctrl = 0x4a004110,
+	.cm_clkmode_dpll_core = 0x4a004120,
+	.cm_idlest_dpll_core = 0x4a004124,
+	.cm_autoidle_dpll_core = 0x4a004128,
+	.cm_clksel_dpll_core = 0x4a00412c,
+	.cm_div_m2_dpll_core = 0x4a004130,
+	.cm_div_m3_dpll_core = 0x4a004134,
+	.cm_div_h11_dpll_core = 0x4a004138,
+	.cm_div_h12_dpll_core = 0x4a00413c,
+	.cm_div_h13_dpll_core = 0x4a004140,
+	.cm_div_h14_dpll_core = 0x4a004144,
+	.cm_ssc_deltamstep_dpll_core = 0x4a004148,
+	.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+	.cm_emu_override_dpll_core = 0x4a004150,
+	.cm_div_h22_dpllcore = 0x4a004154,
+	.cm_div_h23_dpll_core = 0x4a004158,
+	.cm_clkmode_dpll_mpu = 0x4a004160,
+	.cm_idlest_dpll_mpu = 0x4a004164,
+	.cm_autoidle_dpll_mpu = 0x4a004168,
+	.cm_clksel_dpll_mpu = 0x4a00416c,
+	.cm_div_m2_dpll_mpu = 0x4a004170,
+	.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+	.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+	.cm_bypclk_dpll_mpu = 0x4a00419c,
+	.cm_clkmode_dpll_iva = 0x4a0041a0,
+	.cm_idlest_dpll_iva = 0x4a0041a4,
+	.cm_autoidle_dpll_iva = 0x4a0041a8,
+	.cm_clksel_dpll_iva = 0x4a0041ac,
+	.cm_div_h11_dpll_iva = 0x4a0041b8,
+	.cm_div_h12_dpll_iva = 0x4a0041bc,
+	.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+	.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+	.cm_bypclk_dpll_iva = 0x4a0041dc,
+	.cm_clkmode_dpll_abe = 0x4a0041e0,
+	.cm_idlest_dpll_abe = 0x4a0041e4,
+	.cm_autoidle_dpll_abe = 0x4a0041e8,
+	.cm_clksel_dpll_abe = 0x4a0041ec,
+	.cm_div_m2_dpll_abe = 0x4a0041f0,
+	.cm_div_m3_dpll_abe = 0x4a0041f4,
+	.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+	.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+	.cm_clkmode_dpll_ddrphy = 0x4a004220,
+	.cm_idlest_dpll_ddrphy = 0x4a004224,
+	.cm_autoidle_dpll_ddrphy = 0x4a004228,
+	.cm_clksel_dpll_ddrphy = 0x4a00422c,
+	.cm_div_m2_dpll_ddrphy = 0x4a004230,
+	.cm_div_h11_dpll_ddrphy = 0x4a004238,
+	.cm_div_h12_dpll_ddrphy = 0x4a00423c,
+	.cm_div_h13_dpll_ddrphy = 0x4a004240,
+	.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+	.cm_shadow_freq_config1 = 0x4a004260,
+	.cm_mpu_mpu_clkctrl = 0x4a004320,
+
+	/* cm1.dsp */
+	.cm_dsp_clkstctrl = 0x4a004400,
+	.cm_dsp_dsp_clkctrl = 0x4a004420,
+
+	/* cm1.abe */
+	.cm1_abe_clkstctrl = 0x4a004500,
+	.cm1_abe_l4abe_clkctrl = 0x4a004520,
+	.cm1_abe_aess_clkctrl = 0x4a004528,
+	.cm1_abe_pdm_clkctrl = 0x4a004530,
+	.cm1_abe_dmic_clkctrl = 0x4a004538,
+	.cm1_abe_mcasp_clkctrl = 0x4a004540,
+	.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+	.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+	.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+	.cm1_abe_slimbus_clkctrl = 0x4a004560,
+	.cm1_abe_timer5_clkctrl = 0x4a004568,
+	.cm1_abe_timer6_clkctrl = 0x4a004570,
+	.cm1_abe_timer7_clkctrl = 0x4a004578,
+	.cm1_abe_timer8_clkctrl = 0x4a004580,
+	.cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+	/* cm2.ckgen */
+	.cm_clksel_mpu_m3_iss_root = 0x4a008100,
+	.cm_clksel_usb_60mhz = 0x4a008104,
+	.cm_scale_fclk = 0x4a008108,
+	.cm_core_dvfs_perf1 = 0x4a008110,
+	.cm_core_dvfs_perf2 = 0x4a008114,
+	.cm_core_dvfs_perf3 = 0x4a008118,
+	.cm_core_dvfs_perf4 = 0x4a00811c,
+	.cm_core_dvfs_current = 0x4a008124,
+	.cm_iva_dvfs_perf_tesla = 0x4a008128,
+	.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+	.cm_iva_dvfs_perf_abe = 0x4a008130,
+	.cm_iva_dvfs_current = 0x4a008138,
+	.cm_clkmode_dpll_per = 0x4a008140,
+	.cm_idlest_dpll_per = 0x4a008144,
+	.cm_autoidle_dpll_per = 0x4a008148,
+	.cm_clksel_dpll_per = 0x4a00814c,
+	.cm_div_m2_dpll_per = 0x4a008150,
+	.cm_div_m3_dpll_per = 0x4a008154,
+	.cm_div_h11_dpll_per = 0x4a008158,
+	.cm_div_h12_dpll_per = 0x4a00815c,
+	.cm_div_h14_dpll_per = 0x4a008164,
+	.cm_ssc_deltamstep_dpll_per = 0x4a008168,
+	.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+	.cm_emu_override_dpll_per = 0x4a008170,
+	.cm_clkmode_dpll_usb = 0x4a008180,
+	.cm_idlest_dpll_usb = 0x4a008184,
+	.cm_autoidle_dpll_usb = 0x4a008188,
+	.cm_clksel_dpll_usb = 0x4a00818c,
+	.cm_div_m2_dpll_usb = 0x4a008190,
+	.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+	.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+	.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+	.cm_clkmode_dpll_unipro = 0x4a0081c0,
+	.cm_idlest_dpll_unipro = 0x4a0081c4,
+	.cm_autoidle_dpll_unipro = 0x4a0081c8,
+	.cm_clksel_dpll_unipro = 0x4a0081cc,
+	.cm_div_m2_dpll_unipro = 0x4a0081d0,
+	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+
+	/* cm2.core */
+	.cm_coreaon_bandgap_clkctrl = 0x4a008648,
+	.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
+	.cm_l3_1_clkstctrl = 0x4a008700,
+	.cm_l3_1_dynamicdep = 0x4a008708,
+	.cm_l3_1_l3_1_clkctrl = 0x4a008720,
+	.cm_l3_2_clkstctrl = 0x4a008800,
+	.cm_l3_2_dynamicdep = 0x4a008808,
+	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
+	.cm_l3_gpmc_clkctrl = 0x4a008828,
+	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+	.cm_mpu_m3_clkstctrl = 0x4a008900,
+	.cm_mpu_m3_staticdep = 0x4a008904,
+	.cm_mpu_m3_dynamicdep = 0x4a008908,
+	.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+	.cm_sdma_clkstctrl = 0x4a008a00,
+	.cm_sdma_staticdep = 0x4a008a04,
+	.cm_sdma_dynamicdep = 0x4a008a08,
+	.cm_sdma_sdma_clkctrl = 0x4a008a20,
+	.cm_memif_clkstctrl = 0x4a008b00,
+	.cm_memif_dmm_clkctrl = 0x4a008b20,
+	.cm_memif_emif_fw_clkctrl = 0x4a008b28,
+	.cm_memif_emif_1_clkctrl = 0x4a008b30,
+	.cm_memif_emif_2_clkctrl = 0x4a008b38,
+	.cm_memif_dll_clkctrl = 0x4a008b40,
+	.cm_memif_emif_h1_clkctrl = 0x4a008b50,
+	.cm_memif_emif_h2_clkctrl = 0x4a008b58,
+	.cm_memif_dll_h_clkctrl = 0x4a008b60,
+	.cm_c2c_clkstctrl = 0x4a008c00,
+	.cm_c2c_staticdep = 0x4a008c04,
+	.cm_c2c_dynamicdep = 0x4a008c08,
+	.cm_c2c_sad2d_clkctrl = 0x4a008c20,
+	.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+	.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+	.cm_l4cfg_clkstctrl = 0x4a008d00,
+	.cm_l4cfg_dynamicdep = 0x4a008d08,
+	.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+	.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+	.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+	.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+	.cm_l3instr_clkstctrl = 0x4a008e00,
+	.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+	.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+	.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
+
+	/* cm2.ivahd */
+	.cm_ivahd_clkstctrl = 0x4a008f00,
+	.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
+	.cm_ivahd_sl2_clkctrl = 0x4a008f28,
+
+	/* cm2.cam */
+	.cm_cam_clkstctrl = 0x4a009000,
+	.cm_cam_iss_clkctrl = 0x4a009020,
+	.cm_cam_fdif_clkctrl = 0x4a009028,
+
+	/* cm2.dss */
+	.cm_dss_clkstctrl = 0x4a009100,
+	.cm_dss_dss_clkctrl = 0x4a009120,
+
+	/* cm2.sgx */
+	.cm_sgx_clkstctrl = 0x4a009200,
+	.cm_sgx_sgx_clkctrl = 0x4a009220,
+
+	/* cm2.l3init */
+	.cm_l3init_clkstctrl = 0x4a009300,
+	.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
+	.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
+	.cm_l3init_hsi_clkctrl = 0x4a009338,
+	.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
+	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
+	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
+	.cm_l3init_p1500_clkctrl = 0x4a009378,
+	.cm_l3init_sata_clkctrl = 0x4a009388,
+	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
+	.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+	.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
+
+	/* cm2.l4per */
+	.cm_l4per_clkstctrl = 0x4a009400,
+	.cm_l4per_dynamicdep = 0x4a009408,
+	.cm_l4per_adc_clkctrl = 0x4a009420,
+	.cm_l4per_gptimer10_clkctrl = 0x4a009428,
+	.cm_l4per_gptimer11_clkctrl = 0x4a009430,
+	.cm_l4per_gptimer2_clkctrl = 0x4a009438,
+	.cm_l4per_gptimer3_clkctrl = 0x4a009440,
+	.cm_l4per_gptimer4_clkctrl = 0x4a009448,
+	.cm_l4per_gptimer9_clkctrl = 0x4a009450,
+	.cm_l4per_elm_clkctrl = 0x4a009458,
+	.cm_l4per_gpio2_clkctrl = 0x4a009460,
+	.cm_l4per_gpio3_clkctrl = 0x4a009468,
+	.cm_l4per_gpio4_clkctrl = 0x4a009470,
+	.cm_l4per_gpio5_clkctrl = 0x4a009478,
+	.cm_l4per_gpio6_clkctrl = 0x4a009480,
+	.cm_l4per_hdq1w_clkctrl = 0x4a009488,
+	.cm_l4per_hecc1_clkctrl = 0x4a009490,
+	.cm_l4per_hecc2_clkctrl = 0x4a009498,
+	.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
+	.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
+	.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
+	.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
+	.cm_l4per_l4per_clkctrl = 0x4a0094c0,
+	.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
+	.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
+	.cm_l4per_mgate_clkctrl = 0x4a0094e8,
+	.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
+	.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
+	.cm_l4per_mcspi3_clkctrl = 0x4a009500,
+	.cm_l4per_mcspi4_clkctrl = 0x4a009508,
+	.cm_l4per_gpio7_clkctrl = 0x4a009510,
+	.cm_l4per_gpio8_clkctrl = 0x4a009518,
+	.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
+	.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
+	.cm_l4per_msprohg_clkctrl = 0x4a009530,
+	.cm_l4per_slimbus2_clkctrl = 0x4a009538,
+	.cm_l4per_uart1_clkctrl = 0x4a009540,
+	.cm_l4per_uart2_clkctrl = 0x4a009548,
+	.cm_l4per_uart3_clkctrl = 0x4a009550,
+	.cm_l4per_uart4_clkctrl = 0x4a009558,
+	.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
+	.cm_l4per_i2c5_clkctrl = 0x4a009568,
+	.cm_l4per_uart5_clkctrl = 0x4a009570,
+	.cm_l4per_uart6_clkctrl = 0x4a009578,
+	.cm_l4sec_clkstctrl = 0x4a009580,
+	.cm_l4sec_staticdep = 0x4a009584,
+	.cm_l4sec_dynamicdep = 0x4a009588,
+	.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
+	.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
+	.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
+	.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
+	.cm_l4sec_rng_clkctrl = 0x4a0095c0,
+	.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
+	.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
+
+	/* l4 wkup regs */
+	.cm_abe_pll_ref_clksel = 0x4ae0610c,
+	.cm_sys_clksel = 0x4ae06110,
+	.cm_wkup_clkstctrl = 0x4ae07800,
+	.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
+	.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
+	.cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
+	.cm_wkup_gpio1_clkctrl = 0x4ae07838,
+	.cm_wkup_gptimer1_clkctrl = 0x4ae07840,
+	.cm_wkup_gptimer12_clkctrl = 0x4ae07848,
+	.cm_wkup_synctimer_clkctrl = 0x4ae07850,
+	.cm_wkup_usim_clkctrl = 0x4ae07858,
+	.cm_wkup_sarram_clkctrl = 0x4ae07860,
+	.cm_wkup_keyboard_clkctrl = 0x4ae07878,
+	.cm_wkup_rtc_clkctrl = 0x4ae07880,
+	.cm_wkup_bandgap_clkctrl = 0x4ae07888,
+	.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
+	.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
+	.prm_rstctrl = 0x4ae07b00,
+	.prm_rstst = 0x4ae07b04,
+	.prm_rsttime = 0x4ae07b08,
+	.prm_vc_val_bypass = 0x4ae07ba0,
+	.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
+	.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
+
+	/* SCRM stuff, used by some boards */
+	.scrm_auxclk0 = 0x4ae0a310,
+	.scrm_auxclk1 = 0x4ae0a314,
+};
+
+struct omap_sys_ctrl_regs const omap5_ctrl = {
+	.control_status				= 0x4A002134,
+	.control_std_fuse_opp_vdd_mpu_2		= 0x4A0021B4,
+	.control_phy_power_usb 			= 0x4A002370,
+	.control_phy_power_sata			= 0x4A002374,
+	.control_padconf_core_base		= 0x4A002800,
+	.control_paconf_global			= 0x4A002DA0,
+	.control_paconf_mode			= 0x4A002DA4,
+	.control_smart1io_padconf_0		= 0x4A002DA8,
+	.control_smart1io_padconf_1		= 0x4A002DAC,
+	.control_smart1io_padconf_2		= 0x4A002DB0,
+	.control_smart2io_padconf_0		= 0x4A002DB4,
+	.control_smart2io_padconf_1		= 0x4A002DB8,
+	.control_smart2io_padconf_2		= 0x4A002DBC,
+	.control_smart3io_padconf_0		= 0x4A002DC0,
+	.control_smart3io_padconf_1		= 0x4A002DC4,
+	.control_pbias				= 0x4A002E00,
+	.control_i2c_0				= 0x4A002E04,
+	.control_camera_rx			= 0x4A002E08,
+	.control_hdmi_tx_phy			= 0x4A002E0C,
+	.control_uniportm			= 0x4A002E10,
+	.control_dsiphy				= 0x4A002E14,
+	.control_mcbsplp			= 0x4A002E18,
+	.control_usb2phycore			= 0x4A002E1C,
+	.control_hdmi_1				= 0x4A002E20,
+	.control_hsi				= 0x4A002E24,
+	.control_ddr3ch1_0			= 0x4A002E30,
+	.control_ddr3ch2_0			= 0x4A002E34,
+	.control_ddrch1_0			= 0x4A002E38,
+	.control_ddrch1_1			= 0x4A002E3C,
+	.control_ddrch2_0			= 0x4A002E40,
+	.control_ddrch2_1			= 0x4A002E44,
+	.control_lpddr2ch1_0			= 0x4A002E48,
+	.control_lpddr2ch1_1			= 0x4A002E4C,
+	.control_ddrio_0			= 0x4A002E50,
+	.control_ddrio_1			= 0x4A002E54,
+	.control_ddrio_2			= 0x4A002E58,
+	.control_hyst_1				= 0x4A002E5C,
+	.control_usbb_hsic_control		= 0x4A002E60,
+	.control_c2c				= 0x4A002E64,
+	.control_core_control_spare_rw		= 0x4A002E68,
+	.control_core_control_spare_r		= 0x4A002E6C,
+	.control_core_control_spare_r_c0	= 0x4A002E70,
+	.control_srcomp_north_side		= 0x4A002E74,
+	.control_srcomp_south_side		= 0x4A002E78,
+	.control_srcomp_east_side		= 0x4A002E7C,
+	.control_srcomp_west_side		= 0x4A002E80,
+	.control_srcomp_code_latch		= 0x4A002E84,
+	.control_port_emif1_sdram_config	= 0x4AE0C110,
+	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
+	.control_port_emif2_sdram_config	= 0x4AE0C118,
+	.control_emif1_sdram_config_ext		= 0x4AE0C144,
+	.control_emif2_sdram_config_ext		= 0x4AE0C148,
+	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C318,
+	.control_padconf_wkup_base		= 0x4AE0C800,
+	.control_smart1nopmio_padconf_0		= 0x4AE0CDA0,
+	.control_smart1nopmio_padconf_1		= 0x4AE0CDA4,
+	.control_padconf_mode			= 0x4AE0CDA8,
+	.control_xtal_oscillator		= 0x4AE0CDAC,
+	.control_i2c_2				= 0x4AE0CDB0,
+	.control_ckobuffer			= 0x4AE0CDB4,
+	.control_wkup_control_spare_rw		= 0x4AE0CDB8,
+	.control_wkup_control_spare_r		= 0x4AE0CDBC,
+	.control_wkup_control_spare_r_c0	= 0x4AE0CDC0,
+	.control_srcomp_east_side_wkup		= 0x4AE0CDC4,
+	.control_efuse_1			= 0x4AE0CDC8,
+	.control_efuse_2			= 0x4AE0CDCC,
+	.control_efuse_3			= 0x4AE0CDD0,
+	.control_efuse_4			= 0x4AE0CDD4,
+	.control_efuse_5			= 0x4AE0CDD8,
+	.control_efuse_6			= 0x4AE0CDDC,
+	.control_efuse_7			= 0x4AE0CDE0,
+	.control_efuse_8			= 0x4AE0CDE4,
+	.control_efuse_9			= 0x4AE0CDE8,
+	.control_efuse_10			= 0x4AE0CDEC,
+	.control_efuse_11			= 0x4AE0CDF0,
+	.control_efuse_12			= 0x4AE0CDF4,
+	.control_efuse_13			= 0x4AE0CDF8,
+};
+
+struct omap_sys_ctrl_regs const dra7xx_ctrl = {
+	.control_status				= 0x4A002134,
+	.control_phy_power_sata			= 0x4A002374,
+	.control_core_mac_id_0_lo		= 0x4A002514,
+	.control_core_mac_id_0_hi		= 0x4A002518,
+	.control_core_mac_id_1_lo		= 0x4A00251C,
+	.control_core_mac_id_1_hi		= 0x4A002520,
+	.control_core_mmr_lock1			= 0x4A002540,
+	.control_core_mmr_lock2			= 0x4A002544,
+	.control_core_mmr_lock3			= 0x4A002548,
+	.control_core_mmr_lock4			= 0x4A00254C,
+	.control_core_mmr_lock5			= 0x4A002550,
+	.control_core_control_io1		= 0x4A002554,
+	.control_core_control_io2		= 0x4A002558,
+	.control_paconf_global			= 0x4A002DA0,
+	.control_paconf_mode			= 0x4A002DA4,
+	.control_smart1io_padconf_0		= 0x4A002DA8,
+	.control_smart1io_padconf_1		= 0x4A002DAC,
+	.control_smart1io_padconf_2		= 0x4A002DB0,
+	.control_smart2io_padconf_0		= 0x4A002DB4,
+	.control_smart2io_padconf_1		= 0x4A002DB8,
+	.control_smart2io_padconf_2		= 0x4A002DBC,
+	.control_smart3io_padconf_0		= 0x4A002DC0,
+	.control_smart3io_padconf_1		= 0x4A002DC4,
+	.control_pbias				= 0x4A002E00,
+	.control_i2c_0				= 0x4A002E04,
+	.control_camera_rx			= 0x4A002E08,
+	.control_hdmi_tx_phy			= 0x4A002E0C,
+	.control_uniportm			= 0x4A002E10,
+	.control_dsiphy				= 0x4A002E14,
+	.control_mcbsplp			= 0x4A002E18,
+	.control_usb2phycore			= 0x4A002E1C,
+	.control_hdmi_1				= 0x4A002E20,
+	.control_hsi				= 0x4A002E24,
+	.control_ddr3ch1_0			= 0x4A002E30,
+	.control_ddr3ch2_0			= 0x4A002E34,
+	.control_ddrch1_0			= 0x4A002E38,
+	.control_ddrch1_1			= 0x4A002E3C,
+	.control_ddrch2_0			= 0x4A002E40,
+	.control_ddrch2_1			= 0x4A002E44,
+	.control_lpddr2ch1_0			= 0x4A002E48,
+	.control_lpddr2ch1_1			= 0x4A002E4C,
+	.control_ddrio_0			= 0x4A002E50,
+	.control_ddrio_1			= 0x4A002E54,
+	.control_ddrio_2			= 0x4A002E58,
+	.control_hyst_1				= 0x4A002E5C,
+	.control_usbb_hsic_control		= 0x4A002E60,
+	.control_c2c				= 0x4A002E64,
+	.control_core_control_spare_rw		= 0x4A002E68,
+	.control_core_control_spare_r		= 0x4A002E6C,
+	.control_core_control_spare_r_c0	= 0x4A002E70,
+	.control_srcomp_north_side		= 0x4A002E74,
+	.control_srcomp_south_side		= 0x4A002E78,
+	.control_srcomp_east_side		= 0x4A002E7C,
+	.control_srcomp_west_side		= 0x4A002E80,
+	.control_srcomp_code_latch		= 0x4A002E84,
+	.control_ddr_control_ext_0		= 0x4A002E88,
+	.control_padconf_core_base		= 0x4A003400,
+	.control_std_fuse_opp_vdd_mpu_2		= 0x4A003B20,
+	.control_port_emif1_sdram_config	= 0x4AE0C110,
+	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
+	.control_port_emif2_sdram_config	= 0x4AE0C118,
+	.control_emif1_sdram_config_ext		= 0x4AE0C144,
+	.control_emif2_sdram_config_ext		= 0x4AE0C148,
+	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C158,
+	.control_padconf_mode			= 0x4AE0C5A0,
+	.control_xtal_oscillator		= 0x4AE0C5A4,
+	.control_i2c_2				= 0x4AE0C5A8,
+	.control_ckobuffer			= 0x4AE0C5AC,
+	.control_wkup_control_spare_rw		= 0x4AE0C5B0,
+	.control_wkup_control_spare_r		= 0x4AE0C5B4,
+	.control_wkup_control_spare_r_c0	= 0x4AE0C5B8,
+	.control_srcomp_east_side_wkup		= 0x4AE0C5BC,
+	.control_efuse_1			= 0x4AE0C5C0,
+	.control_efuse_2			= 0x4AE0C5C4,
+	.control_efuse_3			= 0x4AE0C5C8,
+	.control_efuse_4			= 0x4AE0C5CC,
+	.control_efuse_13			= 0x4AE0C5F0,
+};
+
+struct prcm_regs const omap5_es2_prcm = {
+	/* cm1.ckgen */
+	.cm_clksel_core = 0x4a004100,
+	.cm_clksel_abe = 0x4a004108,
+	.cm_dll_ctrl = 0x4a004110,
+	.cm_clkmode_dpll_core = 0x4a004120,
+	.cm_idlest_dpll_core = 0x4a004124,
+	.cm_autoidle_dpll_core = 0x4a004128,
+	.cm_clksel_dpll_core = 0x4a00412c,
+	.cm_div_m2_dpll_core = 0x4a004130,
+	.cm_div_m3_dpll_core = 0x4a004134,
+	.cm_div_h11_dpll_core = 0x4a004138,
+	.cm_div_h12_dpll_core = 0x4a00413c,
+	.cm_div_h13_dpll_core = 0x4a004140,
+	.cm_div_h14_dpll_core = 0x4a004144,
+	.cm_ssc_deltamstep_dpll_core = 0x4a004148,
+	.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+	.cm_div_h21_dpll_core = 0x4a004150,
+	.cm_div_h22_dpllcore = 0x4a004154,
+	.cm_div_h23_dpll_core = 0x4a004158,
+	.cm_div_h24_dpll_core = 0x4a00415c,
+	.cm_clkmode_dpll_mpu = 0x4a004160,
+	.cm_idlest_dpll_mpu = 0x4a004164,
+	.cm_autoidle_dpll_mpu = 0x4a004168,
+	.cm_clksel_dpll_mpu = 0x4a00416c,
+	.cm_div_m2_dpll_mpu = 0x4a004170,
+	.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+	.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+	.cm_bypclk_dpll_mpu = 0x4a00419c,
+	.cm_clkmode_dpll_iva = 0x4a0041a0,
+	.cm_idlest_dpll_iva = 0x4a0041a4,
+	.cm_autoidle_dpll_iva = 0x4a0041a8,
+	.cm_clksel_dpll_iva = 0x4a0041ac,
+	.cm_div_h11_dpll_iva = 0x4a0041b8,
+	.cm_div_h12_dpll_iva = 0x4a0041bc,
+	.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+	.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+	.cm_bypclk_dpll_iva = 0x4a0041dc,
+	.cm_clkmode_dpll_abe = 0x4a0041e0,
+	.cm_idlest_dpll_abe = 0x4a0041e4,
+	.cm_autoidle_dpll_abe = 0x4a0041e8,
+	.cm_clksel_dpll_abe = 0x4a0041ec,
+	.cm_div_m2_dpll_abe = 0x4a0041f0,
+	.cm_div_m3_dpll_abe = 0x4a0041f4,
+	.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+	.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+	.cm_clkmode_dpll_ddrphy = 0x4a004220,
+	.cm_idlest_dpll_ddrphy = 0x4a004224,
+	.cm_autoidle_dpll_ddrphy = 0x4a004228,
+	.cm_clksel_dpll_ddrphy = 0x4a00422c,
+	.cm_div_m2_dpll_ddrphy = 0x4a004230,
+	.cm_div_h11_dpll_ddrphy = 0x4a004238,
+	.cm_div_h12_dpll_ddrphy = 0x4a00423c,
+	.cm_div_h13_dpll_ddrphy = 0x4a004240,
+	.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+	.cm_shadow_freq_config1 = 0x4a004260,
+	.cm_mpu_mpu_clkctrl = 0x4a004320,
+
+	/* cm1.dsp */
+	.cm_dsp_clkstctrl = 0x4a004400,
+	.cm_dsp_dsp_clkctrl = 0x4a004420,
+
+	/* cm1.abe */
+	.cm1_abe_clkstctrl = 0x4a004500,
+	.cm1_abe_l4abe_clkctrl = 0x4a004520,
+	.cm1_abe_aess_clkctrl = 0x4a004528,
+	.cm1_abe_pdm_clkctrl = 0x4a004530,
+	.cm1_abe_dmic_clkctrl = 0x4a004538,
+	.cm1_abe_mcasp_clkctrl = 0x4a004540,
+	.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+	.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+	.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+	.cm1_abe_slimbus_clkctrl = 0x4a004560,
+	.cm1_abe_timer5_clkctrl = 0x4a004568,
+	.cm1_abe_timer6_clkctrl = 0x4a004570,
+	.cm1_abe_timer7_clkctrl = 0x4a004578,
+	.cm1_abe_timer8_clkctrl = 0x4a004580,
+	.cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+	/* cm2.ckgen */
+	.cm_clksel_mpu_m3_iss_root = 0x4a008100,
+	.cm_clksel_usb_60mhz = 0x4a008104,
+	.cm_scale_fclk = 0x4a008108,
+	.cm_core_dvfs_perf1 = 0x4a008110,
+	.cm_core_dvfs_perf2 = 0x4a008114,
+	.cm_core_dvfs_perf3 = 0x4a008118,
+	.cm_core_dvfs_perf4 = 0x4a00811c,
+	.cm_core_dvfs_current = 0x4a008124,
+	.cm_iva_dvfs_perf_tesla = 0x4a008128,
+	.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+	.cm_iva_dvfs_perf_abe = 0x4a008130,
+	.cm_iva_dvfs_current = 0x4a008138,
+	.cm_clkmode_dpll_per = 0x4a008140,
+	.cm_idlest_dpll_per = 0x4a008144,
+	.cm_autoidle_dpll_per = 0x4a008148,
+	.cm_clksel_dpll_per = 0x4a00814c,
+	.cm_div_m2_dpll_per = 0x4a008150,
+	.cm_div_m3_dpll_per = 0x4a008154,
+	.cm_div_h11_dpll_per = 0x4a008158,
+	.cm_div_h12_dpll_per = 0x4a00815c,
+	.cm_div_h13_dpll_per = 0x4a008160,
+	.cm_div_h14_dpll_per = 0x4a008164,
+	.cm_ssc_deltamstep_dpll_per = 0x4a008168,
+	.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+	.cm_emu_override_dpll_per = 0x4a008170,
+	.cm_clkmode_dpll_usb = 0x4a008180,
+	.cm_idlest_dpll_usb = 0x4a008184,
+	.cm_autoidle_dpll_usb = 0x4a008188,
+	.cm_clksel_dpll_usb = 0x4a00818c,
+	.cm_div_m2_dpll_usb = 0x4a008190,
+	.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+	.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+	.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+	.cm_clkmode_dpll_unipro = 0x4a0081c0,
+	.cm_idlest_dpll_unipro = 0x4a0081c4,
+	.cm_autoidle_dpll_unipro = 0x4a0081c8,
+	.cm_clksel_dpll_unipro = 0x4a0081cc,
+	.cm_div_m2_dpll_unipro = 0x4a0081d0,
+	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+	.cm_coreaon_usb_phy_core_clkctrl = 0x4A008640,
+	.cm_coreaon_bandgap_clkctrl = 0x4a008648,
+	.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
+
+	/* cm2.core */
+	.cm_l3_1_clkstctrl = 0x4a008700,
+	.cm_l3_1_dynamicdep = 0x4a008708,
+	.cm_l3_1_l3_1_clkctrl = 0x4a008720,
+	.cm_l3_2_clkstctrl = 0x4a008800,
+	.cm_l3_2_dynamicdep = 0x4a008808,
+	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
+	.cm_l3_gpmc_clkctrl = 0x4a008828,
+	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+	.cm_mpu_m3_clkstctrl = 0x4a008900,
+	.cm_mpu_m3_staticdep = 0x4a008904,
+	.cm_mpu_m3_dynamicdep = 0x4a008908,
+	.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+	.cm_sdma_clkstctrl = 0x4a008a00,
+	.cm_sdma_staticdep = 0x4a008a04,
+	.cm_sdma_dynamicdep = 0x4a008a08,
+	.cm_sdma_sdma_clkctrl = 0x4a008a20,
+	.cm_memif_clkstctrl = 0x4a008b00,
+	.cm_memif_dmm_clkctrl = 0x4a008b20,
+	.cm_memif_emif_fw_clkctrl = 0x4a008b28,
+	.cm_memif_emif_1_clkctrl = 0x4a008b30,
+	.cm_memif_emif_2_clkctrl = 0x4a008b38,
+	.cm_memif_dll_clkctrl = 0x4a008b40,
+	.cm_memif_emif_h1_clkctrl = 0x4a008b50,
+	.cm_memif_emif_h2_clkctrl = 0x4a008b58,
+	.cm_memif_dll_h_clkctrl = 0x4a008b60,
+	.cm_c2c_clkstctrl = 0x4a008c00,
+	.cm_c2c_staticdep = 0x4a008c04,
+	.cm_c2c_dynamicdep = 0x4a008c08,
+	.cm_c2c_sad2d_clkctrl = 0x4a008c20,
+	.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+	.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+	.cm_l4cfg_clkstctrl = 0x4a008d00,
+	.cm_l4cfg_dynamicdep = 0x4a008d08,
+	.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+	.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+	.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+	.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+	.cm_l3instr_clkstctrl = 0x4a008e00,
+	.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+	.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+	.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
+	.cm_l4per_clkstctrl = 0x4a009000,
+	.cm_l4per_dynamicdep = 0x4a009008,
+	.cm_l4per_adc_clkctrl = 0x4a009020,
+	.cm_l4per_gptimer10_clkctrl = 0x4a009028,
+	.cm_l4per_gptimer11_clkctrl = 0x4a009030,
+	.cm_l4per_gptimer2_clkctrl = 0x4a009038,
+	.cm_l4per_gptimer3_clkctrl = 0x4a009040,
+	.cm_l4per_gptimer4_clkctrl = 0x4a009048,
+	.cm_l4per_gptimer9_clkctrl = 0x4a009050,
+	.cm_l4per_elm_clkctrl = 0x4a009058,
+	.cm_l4per_gpio2_clkctrl = 0x4a009060,
+	.cm_l4per_gpio3_clkctrl = 0x4a009068,
+	.cm_l4per_gpio4_clkctrl = 0x4a009070,
+	.cm_l4per_gpio5_clkctrl = 0x4a009078,
+	.cm_l4per_gpio6_clkctrl = 0x4a009080,
+	.cm_l4per_hdq1w_clkctrl = 0x4a009088,
+	.cm_l4per_hecc1_clkctrl = 0x4a009090,
+	.cm_l4per_hecc2_clkctrl = 0x4a009098,
+	.cm_l4per_i2c1_clkctrl = 0x4a0090a0,
+	.cm_l4per_i2c2_clkctrl = 0x4a0090a8,
+	.cm_l4per_i2c3_clkctrl = 0x4a0090b0,
+	.cm_l4per_i2c4_clkctrl = 0x4a0090b8,
+	.cm_l4per_l4per_clkctrl = 0x4a0090c0,
+	.cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
+	.cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
+	.cm_l4per_mgate_clkctrl = 0x4a0090e8,
+	.cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
+	.cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
+	.cm_l4per_mcspi3_clkctrl = 0x4a009100,
+	.cm_l4per_mcspi4_clkctrl = 0x4a009108,
+	.cm_l4per_gpio7_clkctrl = 0x4a009110,
+	.cm_l4per_gpio8_clkctrl = 0x4a009118,
+	.cm_l4per_mmcsd3_clkctrl = 0x4a009120,
+	.cm_l4per_mmcsd4_clkctrl = 0x4a009128,
+	.cm_l4per_msprohg_clkctrl = 0x4a009130,
+	.cm_l4per_slimbus2_clkctrl = 0x4a009138,
+	.cm_l4per_uart1_clkctrl = 0x4a009140,
+	.cm_l4per_uart2_clkctrl = 0x4a009148,
+	.cm_l4per_uart3_clkctrl = 0x4a009150,
+	.cm_l4per_uart4_clkctrl = 0x4a009158,
+	.cm_l4per_mmcsd5_clkctrl = 0x4a009160,
+	.cm_l4per_i2c5_clkctrl = 0x4a009168,
+	.cm_l4per_uart5_clkctrl = 0x4a009170,
+	.cm_l4per_uart6_clkctrl = 0x4a009178,
+	.cm_l4sec_clkstctrl = 0x4a009180,
+	.cm_l4sec_staticdep = 0x4a009184,
+	.cm_l4sec_dynamicdep = 0x4a009188,
+	.cm_l4sec_aes1_clkctrl = 0x4a0091a0,
+	.cm_l4sec_aes2_clkctrl = 0x4a0091a8,
+	.cm_l4sec_des3des_clkctrl = 0x4a0091b0,
+	.cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
+	.cm_l4sec_rng_clkctrl = 0x4a0091c0,
+	.cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
+	.cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
+
+	/* cm2.ivahd */
+	.cm_ivahd_clkstctrl = 0x4a009200,
+	.cm_ivahd_ivahd_clkctrl = 0x4a009220,
+	.cm_ivahd_sl2_clkctrl = 0x4a009228,
+
+	/* cm2.cam */
+	.cm_cam_clkstctrl = 0x4a009300,
+	.cm_cam_iss_clkctrl = 0x4a009320,
+	.cm_cam_fdif_clkctrl = 0x4a009328,
+
+	/* cm2.dss */
+	.cm_dss_clkstctrl = 0x4a009400,
+	.cm_dss_dss_clkctrl = 0x4a009420,
+
+	/* cm2.sgx */
+	.cm_sgx_clkstctrl = 0x4a009500,
+	.cm_sgx_sgx_clkctrl = 0x4a009520,
+
+	/* cm2.l3init */
+	.cm_l3init_clkstctrl = 0x4a009600,
+
+	/* cm2.l3init */
+	.cm_l3init_hsmmc1_clkctrl = 0x4a009628,
+	.cm_l3init_hsmmc2_clkctrl = 0x4a009630,
+	.cm_l3init_hsi_clkctrl = 0x4a009638,
+	.cm_l3init_hsusbhost_clkctrl = 0x4a009658,
+	.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
+	.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
+	.cm_l3init_p1500_clkctrl = 0x4a009678,
+	.cm_l3init_sata_clkctrl = 0x4a009688,
+	.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
+	.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
+	.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
+	.cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0,
+
+	/* prm irqstatus regs */
+	.prm_irqstatus_mpu_2 = 0x4ae06014,
+
+	/* l4 wkup regs */
+	.cm_abe_pll_ref_clksel = 0x4ae0610c,
+	.cm_sys_clksel = 0x4ae06110,
+	.cm_wkup_clkstctrl = 0x4ae07900,
+	.cm_wkup_l4wkup_clkctrl = 0x4ae07920,
+	.cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
+	.cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
+	.cm_wkup_gpio1_clkctrl = 0x4ae07938,
+	.cm_wkup_gptimer1_clkctrl = 0x4ae07940,
+	.cm_wkup_gptimer12_clkctrl = 0x4ae07948,
+	.cm_wkup_synctimer_clkctrl = 0x4ae07950,
+	.cm_wkup_usim_clkctrl = 0x4ae07958,
+	.cm_wkup_sarram_clkctrl = 0x4ae07960,
+	.cm_wkup_keyboard_clkctrl = 0x4ae07978,
+	.cm_wkup_rtc_clkctrl = 0x4ae07980,
+	.cm_wkup_bandgap_clkctrl = 0x4ae07988,
+	.cm_wkupaon_scrm_clkctrl = 0x4ae07990,
+	.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
+	.prm_rstctrl = 0x4ae07c00,
+	.prm_rstst = 0x4ae07c04,
+	.prm_rsttime = 0x4ae07c08,
+	.prm_vc_val_bypass = 0x4ae07ca0,
+	.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
+	.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
+
+	.prm_abbldo_mpu_setup = 0x4ae07cdc,
+	.prm_abbldo_mpu_ctrl = 0x4ae07ce0,
+
+	/* SCRM stuff, used by some boards */
+	.scrm_auxclk0 = 0x4ae0a310,
+	.scrm_auxclk1 = 0x4ae0a314,
+};
+
+struct prcm_regs const dra7xx_prcm = {
+	/* cm1.ckgen */
+	.cm_clksel_core				= 0x4a005100,
+	.cm_clksel_abe				= 0x4a005108,
+	.cm_dll_ctrl				= 0x4a005110,
+	.cm_clkmode_dpll_core			= 0x4a005120,
+	.cm_idlest_dpll_core			= 0x4a005124,
+	.cm_autoidle_dpll_core			= 0x4a005128,
+	.cm_clksel_dpll_core			= 0x4a00512c,
+	.cm_div_m2_dpll_core			= 0x4a005130,
+	.cm_div_m3_dpll_core			= 0x4a005134,
+	.cm_div_h11_dpll_core			= 0x4a005138,
+	.cm_div_h12_dpll_core			= 0x4a00513c,
+	.cm_div_h13_dpll_core			= 0x4a005140,
+	.cm_div_h14_dpll_core			= 0x4a005144,
+	.cm_ssc_deltamstep_dpll_core		= 0x4a005148,
+	.cm_ssc_modfreqdiv_dpll_core		= 0x4a00514c,
+	.cm_div_h21_dpll_core			= 0x4a005150,
+	.cm_div_h22_dpllcore			= 0x4a005154,
+	.cm_div_h23_dpll_core			= 0x4a005158,
+	.cm_div_h24_dpll_core			= 0x4a00515c,
+	.cm_clkmode_dpll_mpu			= 0x4a005160,
+	.cm_idlest_dpll_mpu			= 0x4a005164,
+	.cm_autoidle_dpll_mpu			= 0x4a005168,
+	.cm_clksel_dpll_mpu			= 0x4a00516c,
+	.cm_div_m2_dpll_mpu			= 0x4a005170,
+	.cm_ssc_deltamstep_dpll_mpu		= 0x4a005188,
+	.cm_ssc_modfreqdiv_dpll_mpu		= 0x4a00518c,
+	.cm_bypclk_dpll_mpu			= 0x4a00519c,
+	.cm_clkmode_dpll_iva			= 0x4a0051a0,
+	.cm_idlest_dpll_iva			= 0x4a0051a4,
+	.cm_autoidle_dpll_iva			= 0x4a0051a8,
+	.cm_clksel_dpll_iva			= 0x4a0051ac,
+	.cm_ssc_deltamstep_dpll_iva		= 0x4a0051c8,
+	.cm_ssc_modfreqdiv_dpll_iva		= 0x4a0051cc,
+	.cm_bypclk_dpll_iva			= 0x4a0051dc,
+	.cm_clkmode_dpll_abe			= 0x4a0051e0,
+	.cm_idlest_dpll_abe			= 0x4a0051e4,
+	.cm_autoidle_dpll_abe			= 0x4a0051e8,
+	.cm_clksel_dpll_abe			= 0x4a0051ec,
+	.cm_div_m2_dpll_abe			= 0x4a0051f0,
+	.cm_div_m3_dpll_abe			= 0x4a0051f4,
+	.cm_ssc_deltamstep_dpll_abe		= 0x4a005208,
+	.cm_ssc_modfreqdiv_dpll_abe		= 0x4a00520c,
+	.cm_clkmode_dpll_ddrphy			= 0x4a005210,
+	.cm_idlest_dpll_ddrphy			= 0x4a005214,
+	.cm_autoidle_dpll_ddrphy		= 0x4a005218,
+	.cm_clksel_dpll_ddrphy			= 0x4a00521c,
+	.cm_div_m2_dpll_ddrphy			= 0x4a005220,
+	.cm_div_h11_dpll_ddrphy			= 0x4a005228,
+	.cm_ssc_deltamstep_dpll_ddrphy		= 0x4a00522c,
+	.cm_clkmode_dpll_dsp			= 0x4a005234,
+	.cm_shadow_freq_config1			= 0x4a005260,
+	.cm_clkmode_dpll_gmac			= 0x4a0052a8,
+	.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
+
+	/* cm1.mpu */
+	.cm_mpu_mpu_clkctrl			= 0x4a005320,
+
+	/* cm1.dsp */
+	.cm_dsp_clkstctrl			= 0x4a005400,
+	.cm_dsp_dsp_clkctrl			= 0x4a005420,
+
+	/* prm irqstatus regs */
+	.prm_irqstatus_mpu_2			= 0x4ae06014,
+
+	/* cm2.ckgen */
+	.cm_clksel_usb_60mhz			= 0x4a008104,
+	.cm_clkmode_dpll_per			= 0x4a008140,
+	.cm_idlest_dpll_per			= 0x4a008144,
+	.cm_autoidle_dpll_per			= 0x4a008148,
+	.cm_clksel_dpll_per			= 0x4a00814c,
+	.cm_div_m2_dpll_per			= 0x4a008150,
+	.cm_div_m3_dpll_per			= 0x4a008154,
+	.cm_div_h11_dpll_per			= 0x4a008158,
+	.cm_div_h12_dpll_per			= 0x4a00815c,
+	.cm_div_h13_dpll_per			= 0x4a008160,
+	.cm_div_h14_dpll_per			= 0x4a008164,
+	.cm_ssc_deltamstep_dpll_per		= 0x4a008168,
+	.cm_ssc_modfreqdiv_dpll_per		= 0x4a00816c,
+	.cm_clkmode_dpll_usb			= 0x4a008180,
+	.cm_idlest_dpll_usb			= 0x4a008184,
+	.cm_autoidle_dpll_usb			= 0x4a008188,
+	.cm_clksel_dpll_usb			= 0x4a00818c,
+	.cm_div_m2_dpll_usb			= 0x4a008190,
+	.cm_ssc_deltamstep_dpll_usb		= 0x4a0081a8,
+	.cm_ssc_modfreqdiv_dpll_usb		= 0x4a0081ac,
+	.cm_clkdcoldo_dpll_usb			= 0x4a0081b4,
+	.cm_clkmode_dpll_pcie_ref		= 0x4a008200,
+	.cm_clkmode_apll_pcie			= 0x4a00821c,
+	.cm_idlest_apll_pcie			= 0x4a008220,
+	.cm_div_m2_apll_pcie			= 0x4a008224,
+	.cm_clkvcoldo_apll_pcie			= 0x4a008228,
+
+	/* cm2.core */
+	.cm_l3_1_clkstctrl			= 0x4a008700,
+	.cm_l3_1_dynamicdep			= 0x4a008708,
+	.cm_l3_1_l3_1_clkctrl			= 0x4a008720,
+	.cm_l3_gpmc_clkctrl			= 0x4a008728,
+	.cm_mpu_m3_clkstctrl			= 0x4a008900,
+	.cm_mpu_m3_staticdep			= 0x4a008904,
+	.cm_mpu_m3_dynamicdep			= 0x4a008908,
+	.cm_mpu_m3_mpu_m3_clkctrl		= 0x4a008920,
+	.cm_sdma_clkstctrl			= 0x4a008a00,
+	.cm_sdma_staticdep			= 0x4a008a04,
+	.cm_sdma_dynamicdep			= 0x4a008a08,
+	.cm_sdma_sdma_clkctrl			= 0x4a008a20,
+	.cm_memif_clkstctrl			= 0x4a008b00,
+	.cm_memif_dmm_clkctrl			= 0x4a008b20,
+	.cm_memif_emif_fw_clkctrl		= 0x4a008b28,
+	.cm_memif_emif_1_clkctrl		= 0x4a008b30,
+	.cm_memif_emif_2_clkctrl		= 0x4a008b38,
+	.cm_memif_dll_clkctrl			= 0x4a008b40,
+	.cm_l4cfg_clkstctrl			= 0x4a008d00,
+	.cm_l4cfg_dynamicdep			= 0x4a008d08,
+	.cm_l4cfg_l4_cfg_clkctrl		= 0x4a008d20,
+	.cm_l4cfg_hw_sem_clkctrl		= 0x4a008d28,
+	.cm_l4cfg_mailbox_clkctrl		= 0x4a008d30,
+	.cm_l4cfg_sar_rom_clkctrl		= 0x4a008d38,
+	.cm_l3instr_clkstctrl			= 0x4a008e00,
+	.cm_l3instr_l3_3_clkctrl		= 0x4a008e20,
+	.cm_l3instr_l3_instr_clkctrl		= 0x4a008e28,
+	.cm_l3instr_intrconn_wp1_clkctrl	= 0x4a008e40,
+
+	/* cm2.ivahd */
+	.cm_ivahd_clkstctrl			= 0x4a008f00,
+	.cm_ivahd_ivahd_clkctrl			= 0x4a008f20,
+	.cm_ivahd_sl2_clkctrl			= 0x4a008f28,
+
+	/* cm2.cam */
+	.cm_cam_clkstctrl			= 0x4a009000,
+	.cm_cam_vip1_clkctrl			= 0x4a009020,
+	.cm_cam_vip2_clkctrl			= 0x4a009028,
+	.cm_cam_vip3_clkctrl			= 0x4a009030,
+	.cm_cam_lvdsrx_clkctrl			= 0x4a009038,
+	.cm_cam_csi1_clkctrl			= 0x4a009040,
+	.cm_cam_csi2_clkctrl			= 0x4a009048,
+
+	/* cm2.dss */
+	.cm_dss_clkstctrl			= 0x4a009100,
+	.cm_dss_dss_clkctrl			= 0x4a009120,
+
+	/* cm2.sgx */
+	.cm_sgx_clkstctrl			= 0x4a009200,
+	.cm_sgx_sgx_clkctrl			= 0x4a009220,
+
+	/* cm2.l3init */
+	.cm_l3init_clkstctrl			= 0x4a009300,
+
+	/* cm2.l3init */
+	.cm_l3init_hsmmc1_clkctrl		= 0x4a009328,
+	.cm_l3init_hsmmc2_clkctrl		= 0x4a009330,
+	.cm_l3init_hsusbhost_clkctrl		= 0x4a009340,
+	.cm_l3init_hsusbotg_clkctrl		= 0x4a009348,
+	.cm_l3init_hsusbtll_clkctrl		= 0x4a009350,
+	.cm_l3init_sata_clkctrl			= 0x4a009388,
+	.cm_gmac_clkstctrl			= 0x4a0093c0,
+	.cm_gmac_gmac_clkctrl			= 0x4a0093d0,
+	.cm_l3init_ocp2scp1_clkctrl		= 0x4a0093e0,
+	.cm_l3init_ocp2scp3_clkctrl		= 0x4a0093e8,
+
+	/* cm2.l4per */
+	.cm_l4per_clkstctrl			= 0x4a009700,
+	.cm_l4per_dynamicdep			= 0x4a009708,
+	.cm_l4per_gptimer10_clkctrl		= 0x4a009728,
+	.cm_l4per_gptimer11_clkctrl		= 0x4a009730,
+	.cm_l4per_gptimer2_clkctrl		= 0x4a009738,
+	.cm_l4per_gptimer3_clkctrl		= 0x4a009740,
+	.cm_l4per_gptimer4_clkctrl		= 0x4a009748,
+	.cm_l4per_gptimer9_clkctrl		= 0x4a009750,
+	.cm_l4per_elm_clkctrl			= 0x4a009758,
+	.cm_l4per_gpio2_clkctrl			= 0x4a009760,
+	.cm_l4per_gpio3_clkctrl			= 0x4a009768,
+	.cm_l4per_gpio4_clkctrl			= 0x4a009770,
+	.cm_l4per_gpio5_clkctrl			= 0x4a009778,
+	.cm_l4per_gpio6_clkctrl			= 0x4a009780,
+	.cm_l4per_hdq1w_clkctrl			= 0x4a009788,
+	.cm_l4per_i2c1_clkctrl			= 0x4a0097a0,
+	.cm_l4per_i2c2_clkctrl			= 0x4a0097a8,
+	.cm_l4per_i2c3_clkctrl			= 0x4a0097b0,
+	.cm_l4per_i2c4_clkctrl			= 0x4a0097b8,
+	.cm_l4per_l4per_clkctrl			= 0x4a0097c0,
+	.cm_l4per_mcspi1_clkctrl		= 0x4a0097f0,
+	.cm_l4per_mcspi2_clkctrl		= 0x4a0097f8,
+	.cm_l4per_mcspi3_clkctrl		= 0x4a009800,
+	.cm_l4per_mcspi4_clkctrl		= 0x4a009808,
+	.cm_l4per_gpio7_clkctrl			= 0x4a009810,
+	.cm_l4per_gpio8_clkctrl			= 0x4a009818,
+	.cm_l4per_mmcsd3_clkctrl		= 0x4a009820,
+	.cm_l4per_mmcsd4_clkctrl		= 0x4a009828,
+	.cm_l4per_qspi_clkctrl			= 0x4a009838,
+	.cm_l4per_uart1_clkctrl			= 0x4a009840,
+	.cm_l4per_uart2_clkctrl			= 0x4a009848,
+	.cm_l4per_uart3_clkctrl			= 0x4a009850,
+	.cm_l4per_uart4_clkctrl			= 0x4a009858,
+	.cm_l4per_uart5_clkctrl			= 0x4a009870,
+	.cm_l4sec_clkstctrl			= 0x4a009880,
+	.cm_l4sec_staticdep			= 0x4a009884,
+	.cm_l4sec_dynamicdep			= 0x4a009888,
+	.cm_l4sec_aes1_clkctrl			= 0x4a0098a0,
+	.cm_l4sec_aes2_clkctrl			= 0x4a0098a8,
+	.cm_l4sec_des3des_clkctrl		= 0x4a0098b0,
+	.cm_l4sec_rng_clkctrl			= 0x4a0098c0,
+	.cm_l4sec_sha2md51_clkctrl		= 0x4a0098c8,
+	.cm_l4sec_cryptodma_clkctrl		= 0x4a0098d8,
+
+	/* l4 wkup regs */
+	.cm_abe_pll_ref_clksel			= 0x4ae0610c,
+	.cm_sys_clksel				= 0x4ae06110,
+	.cm_abe_pll_sys_clksel			= 0x4ae06118,
+	.cm_wkup_clkstctrl			= 0x4ae07800,
+	.cm_wkup_l4wkup_clkctrl			= 0x4ae07820,
+	.cm_wkup_wdtimer1_clkctrl		= 0x4ae07828,
+	.cm_wkup_wdtimer2_clkctrl		= 0x4ae07830,
+	.cm_wkup_gpio1_clkctrl			= 0x4ae07838,
+	.cm_wkup_gptimer1_clkctrl		= 0x4ae07840,
+	.cm_wkup_gptimer12_clkctrl		= 0x4ae07848,
+	.cm_wkup_sarram_clkctrl			= 0x4ae07860,
+	.cm_wkup_keyboard_clkctrl		= 0x4ae07878,
+	.cm_wkupaon_scrm_clkctrl		= 0x4ae07890,
+	.prm_rstctrl				= 0x4ae07d00,
+	.prm_rstst				= 0x4ae07d04,
+	.prm_rsttime				= 0x4ae07d08,
+	.prm_vc_val_bypass			= 0x4ae07da0,
+	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
+	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,
+
+	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
+	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
+};
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/sdram.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/sdram.c
new file mode 100644
index 000000000..16a91f911
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/omap5/sdram.c
@@ -0,0 +1,658 @@
+/*
+ * Timing and Organization details of the ddr device parts used in OMAP5
+ * EVM
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/emif.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
+ * EVM. Since the parts used and geometry are identical for
+ * evm for a given OMAP5 revision, this information is kept
+ * here instead of being in board directory. However the key functions
+ * exported are weakly linked so that they can be over-ridden in the board
+ * directory if there is a OMAP5 board in the future that uses a different
+ * memory device or geometry.
+ *
+ * For any new board with different memory devices over-ride one or more
+ * of the following functions as per the CONFIG flags you intend to enable:
+ * - emif_get_reg_dump()
+ * - emif_get_dmm_regs()
+ * - emif_get_device_details()
+ * - emif_get_device_timings()
+ */
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+const struct emif_regs emif_regs_532_mhz_2cs = {
+	.sdram_config_init		= 0x80800EBA,
+	.sdram_config			= 0x808022BA,
+	.ref_ctrl			= 0x0000081A,
+	.sdram_tim1			= 0x772F6873,
+	.sdram_tim2			= 0x304a129a,
+	.sdram_tim3			= 0x02f7e45f,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x000b3215,
+	.temp_alert_config		= 0x08000a05,
+	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
+	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x28C518A3,
+	.emif_ddr_ext_phy_ctrl_3	= 0x518A3146,
+	.emif_ddr_ext_phy_ctrl_4	= 0x0014628C,
+	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
+};
+
+const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
+	.sdram_config_init		= 0x80800EBA,
+	.sdram_config			= 0x808022BA,
+	.ref_ctrl			= 0x0000081A,
+	.sdram_tim1			= 0x772F6873,
+	.sdram_tim2			= 0x304a129a,
+	.sdram_tim3			= 0x02f7e45f,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x100b3215,
+	.temp_alert_config		= 0x08000a05,
+	.emif_ddr_phy_ctlr_1_init	= 0x0E30400d,
+	.emif_ddr_phy_ctlr_1		= 0x0E30400d,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x28C518A3,
+	.emif_ddr_ext_phy_ctrl_3	= 0x518A3146,
+	.emif_ddr_ext_phy_ctrl_4	= 0x0014628C,
+	.emif_ddr_ext_phy_ctrl_5	= 0xC330CC33,
+};
+
+const struct emif_regs emif_regs_266_mhz_2cs = {
+	.sdram_config_init		= 0x80800EBA,
+	.sdram_config			= 0x808022BA,
+	.ref_ctrl			= 0x0000040D,
+	.sdram_tim1			= 0x2A86B419,
+	.sdram_tim2			= 0x1025094A,
+	.sdram_tim3			= 0x026BA22F,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x000b3215,
+	.temp_alert_config		= 0x08000a05,
+	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
+	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x0A414829,
+	.emif_ddr_ext_phy_ctrl_3	= 0x14829052,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000520A4,
+	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
+};
+
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
+	.sdram_config_init		= 0x61851B32,
+	.sdram_config			= 0x61851B32,
+	.sdram_config2			= 0x0,
+	.ref_ctrl			= 0x00001035,
+	.sdram_tim1			= 0xCCCF36B3,
+	.sdram_tim2			= 0x308F7FDA,
+	.sdram_tim3			= 0x027F88A8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x0007190B,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init	= 0x0020420A,
+	.emif_ddr_phy_ctlr_1		= 0x0024420A,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00000000,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00000000,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00000000,
+	.emif_ddr_ext_phy_ctrl_5	= 0x04010040,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305
+};
+
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
+	.sdram_config_init              = 0x61851B32,
+	.sdram_config                   = 0x61851B32,
+	.sdram_config2			= 0x0,
+	.ref_ctrl                       = 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x308F7FDA,
+	.sdram_tim3                     = 0x027F88A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x1007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0030400A,
+	.emif_ddr_phy_ctlr_1            = 0x0034400A,
+	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00000000,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00000000,
+	.emif_ddr_ext_phy_ctrl_4        = 0x00000000,
+	.emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x40000305
+};
+
+const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
+	.sdram_config_init              = 0x61851ab2,
+	.sdram_config                   = 0x61851ab2,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x308F7FDA,
+	.sdram_tim3                     = 0x027F88A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x0007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400A,
+	.emif_ddr_phy_ctlr_1            = 0x0024400A,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
+	.sdram_config_init              = 0x61851B32,
+	.sdram_config                   = 0x61851B32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl                       = 0x00001035,
+	.sdram_tim1                     = 0xCCCF36B3,
+	.sdram_tim2                     = 0x308F7FDA,
+	.sdram_tim3                     = 0x027F88A8,
+	.read_idle_ctrl                 = 0x00050000,
+	.zq_config                      = 0x0007190B,
+	.temp_alert_config              = 0x00000000,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400A,
+	.emif_ddr_phy_ctlr_1            = 0x0024400A,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+	.emif_rd_wr_lvl_ctl             = 0x00000000,
+	.emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80740300,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
+/*
+ * DRA752 EVM board has 1.5 GB of memory
+ * EMIF1 --> 2Gb * 2 =  512MB
+ * EMIF2 --> 2Gb * 4 =  1GB
+ * so mapping 1GB interleaved and 512MB non-interleaved
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x80640300,
+	.dmm_lisa_map_2 = 0xC0500220,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
+/*
+ * DRA752 EVM EMIF1 ONLY CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80500100,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
+/*
+ * DRA752 EVM EMIF2 ONLY CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80600200,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1
+};
+
+static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
+{
+	switch (omap_revision()) {
+	case OMAP5430_ES1_0:
+		*regs = &emif_regs_532_mhz_2cs;
+		break;
+	case OMAP5432_ES1_0:
+		*regs = &emif_regs_ddr3_532_mhz_1cs;
+		break;
+	case OMAP5430_ES2_0:
+		*regs = &emif_regs_532_mhz_2cs_es2;
+		break;
+	case OMAP5432_ES2_0:
+		*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
+		break;
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+		switch (emif_nr) {
+		case 1:
+			*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
+			break;
+		case 2:
+			*regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
+			break;
+		}
+		break;
+	default:
+		*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
+	}
+}
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
+{
+	switch (omap_revision()) {
+	case OMAP5430_ES1_0:
+	case OMAP5430_ES2_0:
+	case OMAP5432_ES1_0:
+	case OMAP5432_ES2_0:
+		*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
+		break;
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+	default:
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
+	}
+
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+#else
+
+static const struct lpddr2_device_details dev_4G_S4_details = {
+	.type		= LPDDR2_TYPE_S4,
+	.density	= LPDDR2_DENSITY_4Gb,
+	.io_width	= LPDDR2_IO_WIDTH_32,
+	.manufacturer	= LPDDR2_MANUFACTURER_SAMSUNG
+};
+
+static void emif_get_device_details_sdp(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+{
+	/* EMIF1 & EMIF2 have identical configuration */
+	*cs0_device_details = dev_4G_S4_details;
+	*cs1_device_details = dev_4G_S4_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+		struct lpddr2_device_details *cs0_device_details,
+		struct lpddr2_device_details *cs1_device_details)
+	__attribute__((weak, alias("emif_get_device_details_sdp")));
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
+const u32 ext_phy_ctrl_const_base[] = {
+	0x01004010,
+	0x00001004,
+	0x04010040,
+	0x01004010,
+	0x00001004,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x80080080,
+	0x00800800,
+	0x08102040,
+	0x00000001,
+	0x540A8150,
+	0xA81502a0,
+	0x002A0540,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000077,
+	0x0
+};
+
+const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
+	0x01004010,
+	0x00001004,
+	0x04010040,
+	0x01004010,
+	0x00001004,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x80080080,
+	0x00800800,
+	0x08102040,
+	0x00000002,
+	0x0,
+	0x0,
+	0x0,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000057,
+	0x0
+};
+
+const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
+	0x50D4350D,
+	0x00000D43,
+	0x04010040,
+	0x01004010,
+	0x00001004,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x80080080,
+	0x00800800,
+	0x08102040,
+	0x00000002,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000057,
+	0x0
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
+	0x00B000B0,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00800080,
+	0x00800080,
+	0x00800080,
+	0x00800080,
+	0x00800080,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00800080,
+	0x00800080,
+	0x40010080,
+	0x08102040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
+	0x00BB00BB,
+	0x00440044,
+	0x00440044,
+	0x00440044,
+	0x00440044,
+	0x00440044,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x0,
+	0x00600020,
+	0x40010080,
+	0x08102040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
+};
+
+const struct lpddr2_mr_regs mr_regs = {
+	.mr1	= MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
+	.mr2	= 0x6,
+	.mr3	= 0x1,
+	.mr10	= MR10_ZQ_ZQINIT,
+	.mr16	= MR16_REF_FULL_ARRAY
+};
+
+static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+					     const u32 **regs,
+					     u32 *size)
+{
+	switch (omap_revision()) {
+	case OMAP5430_ES1_0:
+	case OMAP5430_ES2_0:
+		*regs = ext_phy_ctrl_const_base;
+		*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
+		break;
+	case OMAP5432_ES1_0:
+		*regs = ddr3_ext_phy_ctrl_const_base_es1;
+		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
+		break;
+	case OMAP5432_ES2_0:
+		*regs = ddr3_ext_phy_ctrl_const_base_es2;
+		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
+		break;
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+		if (emif_nr == 1) {
+			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
+			*size =
+			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
+		} else {
+			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
+			*size =
+			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
+		}
+		break;
+	default:
+		*regs = ddr3_ext_phy_ctrl_const_base_es2;
+		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
+
+	}
+}
+
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
+{
+	*regs = &mr_regs;
+}
+
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	u32 emif_nr;
+	const u32 *ext_phy_ctrl_const_regs;
+	u32 i = 0;
+	u32 size;
+
+	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+	/*
+	 * external phy 6-24 registers do not change with
+	 * ddr frequency
+	 */
+	emif_get_ext_phy_ctrl_const_regs(emif_nr,
+					 &ext_phy_ctrl_const_regs, &size);
+
+	for (i = 0; i < size; i++) {
+		writel(ext_phy_ctrl_const_regs[i],
+		       emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ext_phy_ctrl_const_regs[i],
+		       emif_ext_phy_ctrl_base++);
+	}
+}
+
+#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
+	.max_freq	= 532000000,
+	.RL		= 8,
+	.tRPab		= 21,
+	.tRCD		= 18,
+	.tWR		= 15,
+	.tRASmin	= 42,
+	.tRRD		= 10,
+	.tWTRx2		= 15,
+	.tXSR		= 140,
+	.tXPx2		= 15,
+	.tRFCab		= 130,
+	.tRTPx2		= 15,
+	.tCKE		= 3,
+	.tCKESR		= 15,
+	.tZQCS		= 90,
+	.tZQCL		= 360,
+	.tZQINIT	= 1000,
+	.tDQSCKMAXx2	= 11,
+	.tRASmax	= 70,
+	.tFAW		= 50
+};
+
+static const struct lpddr2_min_tck min_tck = {
+	.tRL		= 3,
+	.tRP_AB		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRAS_MIN	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+
+static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
+	&timings_jedec_532_mhz
+};
+
+static const struct lpddr2_device_timings dev_4G_S4_timings = {
+	.ac_timings	= ac_timings,
+	.min_tck	= &min_tck,
+};
+
+/*
+ * List of status registers to be controlled back to control registers
+ * after initial leveling
+ * readreg, writereg
+ */
+const struct read_write_regs omap5_bug_00339_regs[] = {
+	{ 8,  5 },
+	{ 9,  6 },
+	{ 10, 7 },
+	{ 14, 8 },
+	{ 15, 9 },
+	{ 16, 10 },
+	{ 11, 2 },
+	{ 12, 3 },
+	{ 13, 4 },
+	{ 17, 11 },
+	{ 18, 12 },
+	{ 19, 13 },
+};
+
+const struct read_write_regs dra_bug_00339_regs[] = {
+	{ 7,  7 },
+	{ 8,  8 },
+	{ 9,  9 },
+	{ 10, 10 },
+	{ 11, 11 },
+	{ 12, 2 },
+	{ 13, 3 },
+	{ 14, 4 },
+	{ 15, 5 },
+	{ 16, 6 },
+	{ 17, 12 },
+	{ 18, 13 },
+	{ 19, 14 },
+	{ 20, 15 },
+	{ 21, 16 },
+	{ 22, 17 },
+	{ 23, 18 },
+	{ 24, 19 },
+	{ 25, 20 },
+	{ 26, 21}
+};
+
+const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+	const struct read_write_regs *bug_00339_regs_ptr = NULL;
+
+	switch (omap_revision()) {
+	case OMAP5430_ES1_0:
+	case OMAP5430_ES2_0:
+	case OMAP5432_ES1_0:
+	case OMAP5432_ES2_0:
+		bug_00339_regs_ptr = omap5_bug_00339_regs;
+		*iterations = sizeof(omap5_bug_00339_regs)/
+			     sizeof(omap5_bug_00339_regs[0]);
+		break;
+	case DRA752_ES1_0:
+	case DRA752_ES1_1:
+		bug_00339_regs_ptr = dra_bug_00339_regs;
+		*iterations = sizeof(dra_bug_00339_regs)/
+			     sizeof(dra_bug_00339_regs[0]);
+		break;
+	default:
+		printf("\n Error: UnKnown SOC");
+	}
+
+	return bug_00339_regs_ptr;
+}
+
+void emif_get_device_timings_sdp(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+{
+	/* Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &dev_4G_S4_timings;
+	*cs1_device_timings = &dev_4G_S4_timings;
+}
+
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings)
+	__attribute__((weak, alias("emif_get_device_timings_sdp")));
+
+#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/Makefile
new file mode 100644
index 000000000..22219990d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/Makefile
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y = cpu_info.o
+obj-y += emac.o
+
+obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+obj-$(CONFIG_GLOBAL_TIMER) += timer.o
+obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
+obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
+obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
+obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
+obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/board.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/board.c
new file mode 100644
index 000000000..d91bc2670
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/board.c
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+int checkboard(void)
+{
+	printf("Board: %s\n", sysinfo.board_string);
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c
new file mode 100644
index 000000000..dfe8950ae
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+
+u32 rmobile_get_cpu_type(void)
+{
+	u32 id;
+	u32 type;
+	struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
+
+	id = readl(hpb->cccr);
+	type = (id >> 8) & 0xFF;
+
+	return type;
+}
+
+u32 rmobile_get_cpu_rev(void)
+{
+	u32 id;
+	u32 rev;
+	struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
+
+	id = readl(hpb->cccr);
+	rev = (id >> 4) & 0xF;
+
+	return rev;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
new file mode 100644
index 000000000..7232e2377
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
+ *     This file is r8a7790 processor support.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#define PRR 0xFF000044
+
+u32 rmobile_get_cpu_type(void)
+{
+	return (readl(PRR) & 0x00007F00) >> 8;
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+	return (readl(PRR) & 0x000000F0) >> 4;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
new file mode 100644
index 000000000..2de58ed27
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#define PRR 0xFF000044
+
+u32 rmobile_get_cpu_type(void)
+{
+	u32 product;
+
+	product = readl(PRR);
+
+	return (u32)((product & 0x00007F00) >> 8);
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+	u32 product;
+
+	product = readl(PRR);
+
+	return (u32)((product & 0x000000F0) >> 4);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
new file mode 100644
index 000000000..186b4b5cb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+
+u32 rmobile_get_cpu_type(void)
+{
+	u32 id;
+	u32 type;
+	struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+	id = readl(&hpb->cccr);
+	type = (id >> 8) & 0xFF;
+
+	return type;
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+	u32 id;
+	u32 rev;
+	struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+	id = readl(&hpb->cccr);
+	rev = ((id >> 4) & 0xF) + 1;
+
+	return rev;
+}
+
+u32 rmobile_get_cpu_rev_fraction(void)
+{
+	u32 id;
+	u32 rev;
+	struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+	id = readl(&hpb->cccr);
+	rev = id & 0xF;
+
+	return rev;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info.c
new file mode 100644
index 000000000..83d5282e3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/cpu_info.c
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	icache_enable();
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	dcache_enable();
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+static u32 __rmobile_get_cpu_type(void)
+{
+	return 0x0;
+}
+u32 rmobile_get_cpu_type(void)
+		__attribute__((weak, alias("__rmobile_get_cpu_type")));
+
+static u32 __rmobile_get_cpu_rev_integer(void)
+{
+	return 0;
+}
+u32 rmobile_get_cpu_rev_integer(void)
+		__attribute__((weak, alias("__rmobile_get_cpu_rev_integer")));
+
+static u32 __rmobile_get_cpu_rev_fraction(void)
+{
+	return 0;
+}
+u32 rmobile_get_cpu_rev_fraction(void)
+		__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
+
+int print_cpuinfo(void)
+{
+	switch (rmobile_get_cpu_type()) {
+	case 0x37:
+		printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n",
+		       rmobile_get_cpu_rev_integer(),
+		       rmobile_get_cpu_rev_fraction());
+		break;
+	case 0x40:
+		printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n",
+		       rmobile_get_cpu_rev_integer(),
+		       rmobile_get_cpu_rev_fraction());
+		break;
+
+	case 0x45:
+		printf("CPU: Renesas Electronics R8A7790 rev %d\n",
+		       rmobile_get_cpu_rev_integer());
+		break;
+
+	case 0x47:
+		printf("CPU: Renesas Electronics R8A7791 rev %d\n",
+			rmobile_get_cpu_rev_integer());
+		break;
+
+	default:
+		printf("CPU: Renesas Electronics CPU rev %d.%d\n",
+		       rmobile_get_cpu_rev_integer(),
+		       rmobile_get_cpu_rev_fraction());
+		break;
+	}
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/emac.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/emac.c
new file mode 100644
index 000000000..0710cfd3c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/emac.c
@@ -0,0 +1,21 @@
+/*
+ * RMOBILE EtherMAC initialization.
+ *
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <netdev.h>
+
+int cpu_eth_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+#ifdef CONFIG_SH_ETHER
+	ret = sh_eth_initialize(bis);
+#endif
+	return ret;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
new file mode 100644
index 000000000..0d654403e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	ldr		r0, =MERAM_BASE
+	mov		r1, #0x0
+	str		r1, [r0]
+
+	mrc		p15, 0, r0, c0, c0, 5
+	ands	r0, r0, #0xF
+	beq		lowlevel_init__
+	b		wait_interrupt
+
+	.pool
+	.align 4
+
+wait_interrupt:
+#ifdef ICCICR
+	ldr     r1, =ICCICR
+	mov     r2, #0x0
+	str     r2, [r1]
+	mov     r2, #0xF0
+	adds    r1, r1, #4 /* ICCPMR */
+	str     r2, [r1]
+	ldr     r1, =ICCICR
+	mov     r2, #0x1
+	str     r2, [r1]
+#endif
+
+wait_loop:
+	.long	0xE320F003 /* wfi */
+
+	ldr		r2, [r1, #0xC]
+	str		r2, [r1, #0x10]
+
+	ldr		r0, =MERAM_BASE
+	ldr		r2, [r0]
+	cmp		r2, #0
+	movne	pc, r2
+
+	b		wait_loop
+
+wait_loop_end:
+	.pool
+	.align 4
+
+lowlevel_init__:
+
+	mov r0, #0x200000
+
+loop0:
+	subs r0, r0, #1
+	bne  loop0
+
+	ldr sp, MERAM_STACK
+	b s_init
+
+	.pool
+	.align 4
+
+ENDPROC(lowlevel_init)
+	.ltorg
+
+MERAM_STACK:
+	.word LOW_LEVEL_MERAM_STACK
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
new file mode 100644
index 000000000..e07cc8093
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+ *     This file is lager low level initialize.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	mrc	p15, 0, r4, c0, c0, 5 /* mpidr */
+	orr	r4, r4, r4, lsr #6
+	and	r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
+
+	b do_lowlevel_init
+
+	.pool
+
+/*
+ * CPU ID #1-#3 come here
+ */
+	.align  4
+do_cpu_waiting:
+	ldr	r1, =0xe6180000 /* sysc */
+1:	ldr	r0, [r1, #0x20] /* sbar */
+	tst	r0, r0
+	beq	1b
+	bx	r0
+
+/*
+ * Only CPU ID #0 comes here
+ */
+	.align  4
+do_lowlevel_init:
+	/* surpress wfe if ca15 */
+	tst	r4, #4
+	mrceq p15, 0, r0, c1, c0, 1	/* actlr */
+	orreq r0, r0, #(1<<7)
+	mcreq p15, 0, r0, c1, c0, 1
+	/* and set l2 latency */
+	mrceq p15, 1, r0, c9, c0, 2	/* l2ctlr */
+	orreq r0, r0, #0x00000800
+	orreq r0, r0, #0x00000003
+	mcreq p15, 1, r0, c9, c0, 2
+
+	ldr	r3, =(CONFIG_SYS_INIT_SP_ADDR)
+	sub	sp, r3, #4
+	str	lr, [sp]
+
+	/* initialize system */
+	bl s_init
+
+	ldr	lr, [sp]
+	mov	pc, lr
+	nop
+ENDPROC(lowlevel_init)
+	.ltorg
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c
new file mode 100644
index 000000000..5d42a6826
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c
@@ -0,0 +1,2612 @@
+/*
+ * R8A7740 processor support
+ *
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include <asm/arch/irqs.h>
+
+#define CPU_ALL_PORT(fn, pfx, sfx)					\
+	PORT_10(fn, pfx, sfx),		PORT_90(fn, pfx, sfx),		\
+	PORT_10(fn, pfx##10, sfx),	PORT_90(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##20, sfx),					\
+	PORT_1(fn, pfx##210, sfx),	PORT_1(fn, pfx##211, sfx)
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	/* PORT0_DATA -> PORT211_DATA */
+	PINMUX_DATA_BEGIN,
+	PORT_ALL(DATA),
+	PINMUX_DATA_END,
+
+	/* PORT0_IN -> PORT211_IN */
+	PINMUX_INPUT_BEGIN,
+	PORT_ALL(IN),
+	PINMUX_INPUT_END,
+
+	/* PORT0_IN_PU -> PORT211_IN_PU */
+	PINMUX_INPUT_PULLUP_BEGIN,
+	PORT_ALL(IN_PU),
+	PINMUX_INPUT_PULLUP_END,
+
+	/* PORT0_IN_PD -> PORT211_IN_PD */
+	PINMUX_INPUT_PULLDOWN_BEGIN,
+	PORT_ALL(IN_PD),
+	PINMUX_INPUT_PULLDOWN_END,
+
+	/* PORT0_OUT -> PORT211_OUT */
+	PINMUX_OUTPUT_BEGIN,
+	PORT_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	PORT_ALL(FN_IN),	/* PORT0_FN_IN -> PORT211_FN_IN */
+	PORT_ALL(FN_OUT),	/* PORT0_FN_OUT -> PORT211_FN_OUT */
+	PORT_ALL(FN0),		/* PORT0_FN0 -> PORT211_FN0 */
+	PORT_ALL(FN1),		/* PORT0_FN1 -> PORT211_FN1 */
+	PORT_ALL(FN2),		/* PORT0_FN2 -> PORT211_FN2 */
+	PORT_ALL(FN3),		/* PORT0_FN3 -> PORT211_FN3 */
+	PORT_ALL(FN4),		/* PORT0_FN4 -> PORT211_FN4 */
+	PORT_ALL(FN5),		/* PORT0_FN5 -> PORT211_FN5 */
+	PORT_ALL(FN6),		/* PORT0_FN6 -> PORT211_FN6 */
+	PORT_ALL(FN7),		/* PORT0_FN7 -> PORT211_FN7 */
+
+	MSEL1CR_31_0,	MSEL1CR_31_1,
+	MSEL1CR_30_0,	MSEL1CR_30_1,
+	MSEL1CR_29_0,	MSEL1CR_29_1,
+	MSEL1CR_28_0,	MSEL1CR_28_1,
+	MSEL1CR_27_0,	MSEL1CR_27_1,
+	MSEL1CR_26_0,	MSEL1CR_26_1,
+	MSEL1CR_16_0,	MSEL1CR_16_1,
+	MSEL1CR_15_0,	MSEL1CR_15_1,
+	MSEL1CR_14_0,	MSEL1CR_14_1,
+	MSEL1CR_13_0,	MSEL1CR_13_1,
+	MSEL1CR_12_0,	MSEL1CR_12_1,
+	MSEL1CR_9_0,	MSEL1CR_9_1,
+	MSEL1CR_7_0,	MSEL1CR_7_1,
+	MSEL1CR_6_0,	MSEL1CR_6_1,
+	MSEL1CR_5_0,	MSEL1CR_5_1,
+	MSEL1CR_4_0,	MSEL1CR_4_1,
+	MSEL1CR_3_0,	MSEL1CR_3_1,
+	MSEL1CR_2_0,	MSEL1CR_2_1,
+	MSEL1CR_0_0,	MSEL1CR_0_1,
+
+	MSEL3CR_15_0,	MSEL3CR_15_1, /* Trace / Debug ? */
+	MSEL3CR_6_0,	MSEL3CR_6_1,
+
+	MSEL4CR_19_0,	MSEL4CR_19_1,
+	MSEL4CR_18_0,	MSEL4CR_18_1,
+	MSEL4CR_15_0,	MSEL4CR_15_1,
+	MSEL4CR_10_0,	MSEL4CR_10_1,
+	MSEL4CR_6_0,	MSEL4CR_6_1,
+	MSEL4CR_4_0,	MSEL4CR_4_1,
+	MSEL4CR_1_0,	MSEL4CR_1_1,
+
+	MSEL5CR_31_0,	MSEL5CR_31_1, /* irq/fiq output */
+	MSEL5CR_30_0,	MSEL5CR_30_1,
+	MSEL5CR_29_0,	MSEL5CR_29_1,
+	MSEL5CR_27_0,	MSEL5CR_27_1,
+	MSEL5CR_25_0,	MSEL5CR_25_1,
+	MSEL5CR_23_0,	MSEL5CR_23_1,
+	MSEL5CR_21_0,	MSEL5CR_21_1,
+	MSEL5CR_19_0,	MSEL5CR_19_1,
+	MSEL5CR_17_0,	MSEL5CR_17_1,
+	MSEL5CR_15_0,	MSEL5CR_15_1,
+	MSEL5CR_14_0,	MSEL5CR_14_1,
+	MSEL5CR_13_0,	MSEL5CR_13_1,
+	MSEL5CR_12_0,	MSEL5CR_12_1,
+	MSEL5CR_11_0,	MSEL5CR_11_1,
+	MSEL5CR_10_0,	MSEL5CR_10_1,
+	MSEL5CR_8_0,	MSEL5CR_8_1,
+	MSEL5CR_7_0,	MSEL5CR_7_1,
+	MSEL5CR_6_0,	MSEL5CR_6_1,
+	MSEL5CR_5_0,	MSEL5CR_5_1,
+	MSEL5CR_4_0,	MSEL5CR_4_1,
+	MSEL5CR_3_0,	MSEL5CR_3_1,
+	MSEL5CR_2_0,	MSEL5CR_2_1,
+	MSEL5CR_0_0,	MSEL5CR_0_1,
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+	/* IRQ */
+	IRQ0_PORT2_MARK,	IRQ0_PORT13_MARK,
+	IRQ1_MARK,
+	IRQ2_PORT11_MARK,	IRQ2_PORT12_MARK,
+	IRQ3_PORT10_MARK,	IRQ3_PORT14_MARK,
+	IRQ4_PORT15_MARK,	IRQ4_PORT172_MARK,
+	IRQ5_PORT0_MARK,	IRQ5_PORT1_MARK,
+	IRQ6_PORT121_MARK,	IRQ6_PORT173_MARK,
+	IRQ7_PORT120_MARK,	IRQ7_PORT209_MARK,
+	IRQ8_MARK,
+	IRQ9_PORT118_MARK,	IRQ9_PORT210_MARK,
+	IRQ10_MARK,
+	IRQ11_MARK,
+	IRQ12_PORT42_MARK,	IRQ12_PORT97_MARK,
+	IRQ13_PORT64_MARK,	IRQ13_PORT98_MARK,
+	IRQ14_PORT63_MARK,	IRQ14_PORT99_MARK,
+	IRQ15_PORT62_MARK,	IRQ15_PORT100_MARK,
+	IRQ16_PORT68_MARK,	IRQ16_PORT211_MARK,
+	IRQ17_MARK,
+	IRQ18_MARK,
+	IRQ19_MARK,
+	IRQ20_MARK,
+	IRQ21_MARK,
+	IRQ22_MARK,
+	IRQ23_MARK,
+	IRQ24_MARK,
+	IRQ25_MARK,
+	IRQ26_PORT58_MARK,	IRQ26_PORT81_MARK,
+	IRQ27_PORT57_MARK,	IRQ27_PORT168_MARK,
+	IRQ28_PORT56_MARK,	IRQ28_PORT169_MARK,
+	IRQ29_PORT50_MARK,	IRQ29_PORT170_MARK,
+	IRQ30_PORT49_MARK,	IRQ30_PORT171_MARK,
+	IRQ31_PORT41_MARK,	IRQ31_PORT167_MARK,
+
+	/* Function */
+
+	/* DBGT */
+	DBGMDT2_MARK,	DBGMDT1_MARK,	DBGMDT0_MARK,
+	DBGMD10_MARK,	DBGMD11_MARK,	DBGMD20_MARK,
+	DBGMD21_MARK,
+
+	/* FSI */
+	FSIAISLD_PORT0_MARK,	/* FSIAISLD Port 0/5 */
+	FSIAISLD_PORT5_MARK,
+	FSIASPDIF_PORT9_MARK,	/* FSIASPDIF Port 9/18 */
+	FSIASPDIF_PORT18_MARK,
+	FSIAOSLD1_MARK,	FSIAOSLD2_MARK,	FSIAOLR_MARK,
+	FSIAOBT_MARK,	FSIAOSLD_MARK,	FSIAOMC_MARK,
+	FSIACK_MARK,	FSIAILR_MARK,	FSIAIBT_MARK,
+
+	/* FMSI */
+	FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
+	FMSISLD_PORT6_MARK,
+	FMSIILR_MARK,	FMSIIBT_MARK,	FMSIOLR_MARK,	FMSIOBT_MARK,
+	FMSICK_MARK,	FMSOILR_MARK,	FMSOIBT_MARK,	FMSOOLR_MARK,
+	FMSOOBT_MARK,	FMSOSLD_MARK,	FMSOCK_MARK,
+
+	/* SCIFA0 */
+	SCIFA0_SCK_MARK,	SCIFA0_CTS_MARK,	SCIFA0_RTS_MARK,
+	SCIFA0_RXD_MARK,	SCIFA0_TXD_MARK,
+
+	/* SCIFA1 */
+	SCIFA1_CTS_MARK,	SCIFA1_SCK_MARK,	SCIFA1_RXD_MARK,
+	SCIFA1_TXD_MARK,	SCIFA1_RTS_MARK,
+
+	/* SCIFA2 */
+	SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
+	SCIFA2_SCK_PORT199_MARK,
+	SCIFA2_RXD_MARK,	SCIFA2_TXD_MARK,
+	SCIFA2_CTS_MARK,	SCIFA2_RTS_MARK,
+
+	/* SCIFA3 */
+	SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
+	SCIFA3_SCK_PORT116_MARK,
+	SCIFA3_CTS_PORT117_MARK,
+	SCIFA3_RXD_PORT174_MARK,
+	SCIFA3_TXD_PORT175_MARK,
+
+	SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
+	SCIFA3_SCK_PORT158_MARK,
+	SCIFA3_CTS_PORT162_MARK,
+	SCIFA3_RXD_PORT159_MARK,
+	SCIFA3_TXD_PORT160_MARK,
+
+	/* SCIFA4 */
+	SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
+	SCIFA4_TXD_PORT13_MARK,
+
+	SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
+	SCIFA4_TXD_PORT203_MARK,
+
+	SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
+	SCIFA4_TXD_PORT93_MARK,
+
+	SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
+	SCIFA4_SCK_PORT205_MARK,
+
+	/* SCIFA5 */
+	SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
+	SCIFA5_RXD_PORT10_MARK,
+
+	SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
+	SCIFA5_TXD_PORT208_MARK,
+
+	SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
+	SCIFA5_RXD_PORT92_MARK,
+
+	SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
+	SCIFA5_SCK_PORT206_MARK,
+
+	/* SCIFA6 */
+	SCIFA6_SCK_MARK,	SCIFA6_RXD_MARK,	SCIFA6_TXD_MARK,
+
+	/* SCIFA7 */
+	SCIFA7_TXD_MARK,	SCIFA7_RXD_MARK,
+
+	/* SCIFAB */
+	SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
+	SCIFB_RXD_PORT191_MARK,
+	SCIFB_TXD_PORT192_MARK,
+	SCIFB_RTS_PORT186_MARK,
+	SCIFB_CTS_PORT187_MARK,
+
+	SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
+	SCIFB_RXD_PORT3_MARK,
+	SCIFB_TXD_PORT4_MARK,
+	SCIFB_RTS_PORT172_MARK,
+	SCIFB_CTS_PORT173_MARK,
+
+	/* LCD0 */
+	LCDC0_SELECT_MARK,
+
+	LCD0_D0_MARK,	LCD0_D1_MARK,	LCD0_D2_MARK,	LCD0_D3_MARK,
+	LCD0_D4_MARK,	LCD0_D5_MARK,	LCD0_D6_MARK,	LCD0_D7_MARK,
+	LCD0_D8_MARK,	LCD0_D9_MARK,	LCD0_D10_MARK,	LCD0_D11_MARK,
+	LCD0_D12_MARK,	LCD0_D13_MARK,	LCD0_D14_MARK,	LCD0_D15_MARK,
+	LCD0_D16_MARK,	LCD0_D17_MARK,
+	LCD0_DON_MARK,	LCD0_VCPWC_MARK,	LCD0_VEPWC_MARK,
+	LCD0_DCK_MARK,	LCD0_VSYN_MARK,	/* for RGB */
+	LCD0_HSYN_MARK,	LCD0_DISP_MARK,	/* for RGB */
+	LCD0_WR_MARK,	LCD0_RD_MARK,	/* for SYS */
+	LCD0_CS_MARK,	LCD0_RS_MARK,	/* for SYS */
+
+	LCD0_D21_PORT158_MARK,	LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
+	LCD0_D22_PORT160_MARK,	LCD0_D20_PORT161_MARK,
+	LCD0_D19_PORT162_MARK,	LCD0_D18_PORT163_MARK,
+	LCD0_LCLK_PORT165_MARK,
+
+	LCD0_D18_PORT40_MARK,	LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
+	LCD0_D23_PORT1_MARK,	LCD0_D21_PORT2_MARK,
+	LCD0_D20_PORT3_MARK,	LCD0_D19_PORT4_MARK,
+	LCD0_LCLK_PORT102_MARK,
+
+	/* LCD1 */
+	LCDC1_SELECT_MARK,
+
+	LCD1_D0_MARK,	LCD1_D1_MARK,	LCD1_D2_MARK,	LCD1_D3_MARK,
+	LCD1_D4_MARK,	LCD1_D5_MARK,	LCD1_D6_MARK,	LCD1_D7_MARK,
+	LCD1_D8_MARK,	LCD1_D9_MARK,	LCD1_D10_MARK,	LCD1_D11_MARK,
+	LCD1_D12_MARK,	LCD1_D13_MARK,	LCD1_D14_MARK,	LCD1_D15_MARK,
+	LCD1_D16_MARK,	LCD1_D17_MARK,	LCD1_D18_MARK,	LCD1_D19_MARK,
+	LCD1_D20_MARK,	LCD1_D21_MARK,	LCD1_D22_MARK,	LCD1_D23_MARK,
+	LCD1_DON_MARK,	LCD1_VCPWC_MARK,
+	LCD1_LCLK_MARK,	LCD1_VEPWC_MARK,
+
+	LCD1_DCK_MARK,	LCD1_VSYN_MARK,	/* for RGB */
+	LCD1_HSYN_MARK,	LCD1_DISP_MARK,	/* for RGB */
+	LCD1_RS_MARK,	LCD1_CS_MARK,	/* for SYS */
+	LCD1_RD_MARK,	LCD1_WR_MARK,	/* for SYS */
+
+	/* RSPI */
+	RSPI_SSL0_A_MARK,	RSPI_SSL1_A_MARK,	RSPI_SSL2_A_MARK,
+	RSPI_SSL3_A_MARK,	RSPI_CK_A_MARK,		RSPI_MOSI_A_MARK,
+	RSPI_MISO_A_MARK,
+
+	/* VIO CKO */
+	VIO_CKO1_MARK, /* needs fixup */
+	VIO_CKO2_MARK,
+	VIO_CKO_1_MARK,
+	VIO_CKO_MARK,
+
+	/* VIO0 */
+	VIO0_D0_MARK,	VIO0_D1_MARK,	VIO0_D2_MARK,	VIO0_D3_MARK,
+	VIO0_D4_MARK,	VIO0_D5_MARK,	VIO0_D6_MARK,	VIO0_D7_MARK,
+	VIO0_D8_MARK,	VIO0_D9_MARK,	VIO0_D10_MARK,	VIO0_D11_MARK,
+	VIO0_D12_MARK,	VIO0_VD_MARK,	VIO0_HD_MARK,	VIO0_CLK_MARK,
+	VIO0_FIELD_MARK,
+
+	VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
+	VIO0_D14_PORT25_MARK,
+	VIO0_D15_PORT24_MARK,
+
+	VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
+	VIO0_D14_PORT95_MARK,
+	VIO0_D15_PORT96_MARK,
+
+	/* VIO1 */
+	VIO1_D0_MARK,	VIO1_D1_MARK,	VIO1_D2_MARK,	VIO1_D3_MARK,
+	VIO1_D4_MARK,	VIO1_D5_MARK,	VIO1_D6_MARK,	VIO1_D7_MARK,
+	VIO1_VD_MARK,	VIO1_HD_MARK,	VIO1_CLK_MARK,	VIO1_FIELD_MARK,
+
+	/* TPU0 */
+	TPU0TO0_MARK,	TPU0TO1_MARK,	TPU0TO3_MARK,
+	TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
+	TPU0TO2_PORT202_MARK,
+
+	/* SSP1 0 */
+	STP0_IPD0_MARK,	STP0_IPD1_MARK,	STP0_IPD2_MARK,	STP0_IPD3_MARK,
+	STP0_IPD4_MARK,	STP0_IPD5_MARK,	STP0_IPD6_MARK,	STP0_IPD7_MARK,
+	STP0_IPEN_MARK,	STP0_IPCLK_MARK,	STP0_IPSYNC_MARK,
+
+	/* SSP1 1 */
+	STP1_IPD1_MARK,	STP1_IPD2_MARK,	STP1_IPD3_MARK,	STP1_IPD4_MARK,
+	STP1_IPD5_MARK,	STP1_IPD6_MARK,	STP1_IPD7_MARK,	STP1_IPCLK_MARK,
+	STP1_IPSYNC_MARK,
+
+	STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
+	STP1_IPEN_PORT187_MARK,
+
+	STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
+	STP1_IPEN_PORT193_MARK,
+
+	/* SIM */
+	SIM_RST_MARK,	SIM_CLK_MARK,
+	SIM_D_PORT22_MARK, /* SIM_D  Port 22/199 */
+	SIM_D_PORT199_MARK,
+
+	/* SDHI0 */
+	SDHI0_D0_MARK,	SDHI0_D1_MARK,	SDHI0_D2_MARK,	SDHI0_D3_MARK,
+	SDHI0_CD_MARK,	SDHI0_WP_MARK,	SDHI0_CMD_MARK,	SDHI0_CLK_MARK,
+
+	/* SDHI1 */
+	SDHI1_D0_MARK,	SDHI1_D1_MARK,	SDHI1_D2_MARK,	SDHI1_D3_MARK,
+	SDHI1_CD_MARK,	SDHI1_WP_MARK,	SDHI1_CMD_MARK,	SDHI1_CLK_MARK,
+
+	/* SDHI2 */
+	SDHI2_D0_MARK,	SDHI2_D1_MARK,	SDHI2_D2_MARK,	SDHI2_D3_MARK,
+	SDHI2_CLK_MARK,	SDHI2_CMD_MARK,
+
+	SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
+	SDHI2_WP_PORT25_MARK,
+
+	SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
+	SDHI2_CD_PORT202_MARK,
+
+	/* MSIOF2 */
+	MSIOF2_TXD_MARK,	MSIOF2_RXD_MARK,	MSIOF2_TSCK_MARK,
+	MSIOF2_SS2_MARK,	MSIOF2_TSYNC_MARK,	MSIOF2_SS1_MARK,
+	MSIOF2_MCK1_MARK,	MSIOF2_MCK0_MARK,	MSIOF2_RSYNC_MARK,
+	MSIOF2_RSCK_MARK,
+
+	/* KEYSC */
+	KEYIN4_MARK,	KEYIN5_MARK,	KEYIN6_MARK,	KEYIN7_MARK,
+	KEYOUT0_MARK,	KEYOUT1_MARK,	KEYOUT2_MARK,	KEYOUT3_MARK,
+	KEYOUT4_MARK,	KEYOUT5_MARK,	KEYOUT6_MARK,	KEYOUT7_MARK,
+
+	KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
+	KEYIN1_PORT44_MARK,
+	KEYIN2_PORT45_MARK,
+	KEYIN3_PORT46_MARK,
+
+	KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
+	KEYIN1_PORT57_MARK,
+	KEYIN2_PORT56_MARK,
+	KEYIN3_PORT55_MARK,
+
+	/* VOU */
+	DV_D0_MARK,	DV_D1_MARK,	DV_D2_MARK,	DV_D3_MARK,
+	DV_D4_MARK,	DV_D5_MARK,	DV_D6_MARK,	DV_D7_MARK,
+	DV_D8_MARK,	DV_D9_MARK,	DV_D10_MARK,	DV_D11_MARK,
+	DV_D12_MARK,	DV_D13_MARK,	DV_D14_MARK,	DV_D15_MARK,
+	DV_CLK_MARK,	DV_VSYNC_MARK,	DV_HSYNC_MARK,
+
+	/* MEMC */
+	MEMC_AD0_MARK,	MEMC_AD1_MARK,	MEMC_AD2_MARK,	MEMC_AD3_MARK,
+	MEMC_AD4_MARK,	MEMC_AD5_MARK,	MEMC_AD6_MARK,	MEMC_AD7_MARK,
+	MEMC_AD8_MARK,	MEMC_AD9_MARK,	MEMC_AD10_MARK,	MEMC_AD11_MARK,
+	MEMC_AD12_MARK,	MEMC_AD13_MARK,	MEMC_AD14_MARK,	MEMC_AD15_MARK,
+	MEMC_CS0_MARK,	MEMC_INT_MARK,	MEMC_NWE_MARK,	MEMC_NOE_MARK,
+
+	MEMC_CS1_MARK, /* MSEL4CR_6_0 */
+	MEMC_ADV_MARK,
+	MEMC_WAIT_MARK,
+	MEMC_BUSCLK_MARK,
+
+	MEMC_A1_MARK, /* MSEL4CR_6_1 */
+	MEMC_DREQ0_MARK,
+	MEMC_DREQ1_MARK,
+	MEMC_A0_MARK,
+
+	/* MMC */
+	MMC0_D0_PORT68_MARK,	MMC0_D1_PORT69_MARK,	MMC0_D2_PORT70_MARK,
+	MMC0_D3_PORT71_MARK,	MMC0_D4_PORT72_MARK,	MMC0_D5_PORT73_MARK,
+	MMC0_D6_PORT74_MARK,	MMC0_D7_PORT75_MARK,	MMC0_CLK_PORT66_MARK,
+	MMC0_CMD_PORT67_MARK,	/* MSEL4CR_15_0 */
+
+	MMC1_D0_PORT149_MARK,	MMC1_D1_PORT148_MARK,	MMC1_D2_PORT147_MARK,
+	MMC1_D3_PORT146_MARK,	MMC1_D4_PORT145_MARK,	MMC1_D5_PORT144_MARK,
+	MMC1_D6_PORT143_MARK,	MMC1_D7_PORT142_MARK,	MMC1_CLK_PORT103_MARK,
+	MMC1_CMD_PORT104_MARK,	/* MSEL4CR_15_1 */
+
+	/* MSIOF0 */
+	MSIOF0_SS1_MARK,	MSIOF0_SS2_MARK,	MSIOF0_RXD_MARK,
+	MSIOF0_TXD_MARK,	MSIOF0_MCK0_MARK,	MSIOF0_MCK1_MARK,
+	MSIOF0_RSYNC_MARK,	MSIOF0_RSCK_MARK,	MSIOF0_TSCK_MARK,
+	MSIOF0_TSYNC_MARK,
+
+	/* MSIOF1 */
+	MSIOF1_RSCK_MARK,	MSIOF1_RSYNC_MARK,
+	MSIOF1_MCK0_MARK,	MSIOF1_MCK1_MARK,
+
+	MSIOF1_SS2_PORT116_MARK,	MSIOF1_SS1_PORT117_MARK,
+	MSIOF1_RXD_PORT118_MARK,	MSIOF1_TXD_PORT119_MARK,
+	MSIOF1_TSYNC_PORT120_MARK,
+	MSIOF1_TSCK_PORT121_MARK,	/* MSEL4CR_10_0 */
+
+	MSIOF1_SS1_PORT67_MARK,		MSIOF1_TSCK_PORT72_MARK,
+	MSIOF1_TSYNC_PORT73_MARK,	MSIOF1_TXD_PORT74_MARK,
+	MSIOF1_RXD_PORT75_MARK,
+	MSIOF1_SS2_PORT202_MARK,	/* MSEL4CR_10_1 */
+
+	/* GPIO */
+	GPO0_MARK,	GPI0_MARK,	GPO1_MARK,	GPI1_MARK,
+
+	/* USB0 */
+	USB0_OCI_MARK,	USB0_PPON_MARK,	VBUS_MARK,
+
+	/* USB1 */
+	USB1_OCI_MARK,	USB1_PPON_MARK,
+
+	/* BBIF1 */
+	BBIF1_RXD_MARK,		BBIF1_TXD_MARK,		BBIF1_TSYNC_MARK,
+	BBIF1_TSCK_MARK,	BBIF1_RSCK_MARK,	BBIF1_RSYNC_MARK,
+	BBIF1_FLOW_MARK,	BBIF1_RX_FLOW_N_MARK,
+
+	/* BBIF2 */
+	BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
+	BBIF2_RXD2_PORT60_MARK,
+	BBIF2_TSYNC2_PORT6_MARK,
+	BBIF2_TSCK2_PORT59_MARK,
+
+	BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
+	BBIF2_TXD2_PORT183_MARK,
+	BBIF2_TSCK2_PORT89_MARK,
+	BBIF2_TSYNC2_PORT184_MARK,
+
+	/* BSC / FLCTL / PCMCIA */
+	CS0_MARK,	CS2_MARK,	CS4_MARK,
+	CS5B_MARK,	CS6A_MARK,
+	CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
+	CS5A_PORT19_MARK,
+	IOIS16_MARK, /* ? */
+
+	A0_MARK,	A1_MARK,	A2_MARK,	A3_MARK,
+	A4_FOE_MARK,	/* share with FLCTL */
+	A5_FCDE_MARK,	/* share with FLCTL */
+	A6_MARK,	A7_MARK,	A8_MARK,	A9_MARK,
+	A10_MARK,	A11_MARK,	A12_MARK,	A13_MARK,
+	A14_MARK,	A15_MARK,	A16_MARK,	A17_MARK,
+	A18_MARK,	A19_MARK,	A20_MARK,	A21_MARK,
+	A22_MARK,	A23_MARK,	A24_MARK,	A25_MARK,
+	A26_MARK,
+
+	D0_NAF0_MARK,	D1_NAF1_MARK,	D2_NAF2_MARK,	/* share with FLCTL */
+	D3_NAF3_MARK,	D4_NAF4_MARK,	D5_NAF5_MARK,	/* share with FLCTL */
+	D6_NAF6_MARK,	D7_NAF7_MARK,	D8_NAF8_MARK,	/* share with FLCTL */
+	D9_NAF9_MARK,	D10_NAF10_MARK,	D11_NAF11_MARK,	/* share with FLCTL */
+	D12_NAF12_MARK,	D13_NAF13_MARK,	D14_NAF14_MARK,	/* share with FLCTL */
+	D15_NAF15_MARK,					/* share with FLCTL */
+	D16_MARK,	D17_MARK,	D18_MARK,	D19_MARK,
+	D20_MARK,	D21_MARK,	D22_MARK,	D23_MARK,
+	D24_MARK,	D25_MARK,	D26_MARK,	D27_MARK,
+	D28_MARK,	D29_MARK,	D30_MARK,	D31_MARK,
+
+	WE0_FWE_MARK,	/* share with FLCTL */
+	WE1_MARK,
+	WE2_ICIORD_MARK,	/* share with PCMCIA */
+	WE3_ICIOWR_MARK,	/* share with PCMCIA */
+	CKO_MARK,	BS_MARK,	RDWR_MARK,
+	RD_FSC_MARK,	/* share with FLCTL */
+	WAIT_PORT177_MARK, /* WAIT Port 90/177 */
+	WAIT_PORT90_MARK,
+
+	FCE0_MARK,	FCE1_MARK,	FRB_MARK, /* FLCTL */
+
+	/* IRDA */
+	IRDA_FIRSEL_MARK,	IRDA_IN_MARK,	IRDA_OUT_MARK,
+
+	/* ATAPI */
+	IDE_D0_MARK,	IDE_D1_MARK,	IDE_D2_MARK,	IDE_D3_MARK,
+	IDE_D4_MARK,	IDE_D5_MARK,	IDE_D6_MARK,	IDE_D7_MARK,
+	IDE_D8_MARK,	IDE_D9_MARK,	IDE_D10_MARK,	IDE_D11_MARK,
+	IDE_D12_MARK,	IDE_D13_MARK,	IDE_D14_MARK,	IDE_D15_MARK,
+	IDE_A0_MARK,	IDE_A1_MARK,	IDE_A2_MARK,	IDE_CS0_MARK,
+	IDE_CS1_MARK,	IDE_IOWR_MARK,	IDE_IORD_MARK,	IDE_IORDY_MARK,
+	IDE_INT_MARK,		IDE_RST_MARK,		IDE_DIRECTION_MARK,
+	IDE_EXBUF_ENB_MARK,	IDE_IODACK_MARK,	IDE_IODREQ_MARK,
+
+	/* RMII */
+	RMII_CRS_DV_MARK,	RMII_RX_ER_MARK,	RMII_RXD0_MARK,
+	RMII_RXD1_MARK,		RMII_TX_EN_MARK,	RMII_TXD0_MARK,
+	RMII_MDC_MARK,		RMII_TXD1_MARK,		RMII_MDIO_MARK,
+	RMII_REF50CK_MARK,	/* for RMII */
+	RMII_REF125CK_MARK,	/* for GMII */
+
+	/* GEther */
+	ET_TX_CLK_MARK,	ET_TX_EN_MARK,	ET_ETXD0_MARK,	ET_ETXD1_MARK,
+	ET_ETXD2_MARK,	ET_ETXD3_MARK,
+	ET_ETXD4_MARK,	ET_ETXD5_MARK, /* for GEther */
+	ET_ETXD6_MARK,	ET_ETXD7_MARK, /* for GEther */
+	ET_COL_MARK,	ET_TX_ER_MARK,	ET_RX_CLK_MARK,	ET_RX_DV_MARK,
+	ET_ERXD0_MARK,	ET_ERXD1_MARK,	ET_ERXD2_MARK,	ET_ERXD3_MARK,
+	ET_ERXD4_MARK,	ET_ERXD5_MARK, /* for GEther */
+	ET_ERXD6_MARK,	ET_ERXD7_MARK, /* for GEther */
+	ET_RX_ER_MARK,	ET_CRS_MARK,		ET_MDC_MARK,	ET_MDIO_MARK,
+	ET_LINK_MARK,	ET_PHY_INT_MARK,	ET_WOL_MARK,	ET_GTX_CLK_MARK,
+
+	/* DMA0 */
+	DREQ0_MARK,	DACK0_MARK,
+
+	/* DMA1 */
+	DREQ1_MARK,	DACK1_MARK,
+
+	/* SYSC */
+	RESETOUTS_MARK,		RESETP_PULLUP_MARK,	RESETP_PLAIN_MARK,
+
+	/* IRREM */
+	IROUT_MARK,
+
+	/* SDENC */
+	SDENC_CPG_MARK,		SDENC_DV_CLKI_MARK,
+
+	/* DEBUG */
+	EDEBGREQ_PULLUP_MARK,	/* for JTAG */
+	EDEBGREQ_PULLDOWN_MARK,
+
+	TRACEAUD_FROM_VIO_MARK,	/* for TRACE/AUD */
+	TRACEAUD_FROM_LCDC0_MARK,
+	TRACEAUD_FROM_MEMC_MARK,
+
+	PINMUX_MARK_END,
+};
+
+static unsigned short pinmux_data[] = {
+	/* specify valid pin states for each pin in GPIO mode */
+
+	/* I/O and Pull U/D */
+	PORT_DATA_IO_PD(0),		PORT_DATA_IO_PD(1),
+	PORT_DATA_IO_PD(2),		PORT_DATA_IO_PD(3),
+	PORT_DATA_IO_PD(4),		PORT_DATA_IO_PD(5),
+	PORT_DATA_IO_PD(6),		PORT_DATA_IO(7),
+	PORT_DATA_IO(8),		PORT_DATA_IO(9),
+
+	PORT_DATA_IO_PD(10),		PORT_DATA_IO_PD(11),
+	PORT_DATA_IO_PD(12),		PORT_DATA_IO_PU_PD(13),
+	PORT_DATA_IO_PD(14),		PORT_DATA_IO_PD(15),
+	PORT_DATA_IO_PD(16),		PORT_DATA_IO_PD(17),
+	PORT_DATA_IO(18),		PORT_DATA_IO_PU(19),
+
+	PORT_DATA_IO_PU_PD(20),		PORT_DATA_IO_PD(21),
+	PORT_DATA_IO_PU_PD(22),		PORT_DATA_IO(23),
+	PORT_DATA_IO_PU(24),		PORT_DATA_IO_PU(25),
+	PORT_DATA_IO_PU(26),		PORT_DATA_IO_PU(27),
+	PORT_DATA_IO_PU(28),		PORT_DATA_IO_PU(29),
+
+	PORT_DATA_IO_PU(30),		PORT_DATA_IO_PD(31),
+	PORT_DATA_IO_PD(32),		PORT_DATA_IO_PD(33),
+	PORT_DATA_IO_PD(34),		PORT_DATA_IO_PU(35),
+	PORT_DATA_IO_PU(36),		PORT_DATA_IO_PD(37),
+	PORT_DATA_IO_PU(38),		PORT_DATA_IO_PD(39),
+
+	PORT_DATA_IO_PU_PD(40),		PORT_DATA_IO_PD(41),
+	PORT_DATA_IO_PD(42),		PORT_DATA_IO_PU_PD(43),
+	PORT_DATA_IO_PU_PD(44),		PORT_DATA_IO_PU_PD(45),
+	PORT_DATA_IO_PU_PD(46),		PORT_DATA_IO_PU_PD(47),
+	PORT_DATA_IO_PU_PD(48),		PORT_DATA_IO_PU_PD(49),
+
+	PORT_DATA_IO_PU_PD(50),		PORT_DATA_IO_PD(51),
+	PORT_DATA_IO_PD(52),		PORT_DATA_IO_PD(53),
+	PORT_DATA_IO_PD(54),		PORT_DATA_IO_PU_PD(55),
+	PORT_DATA_IO_PU_PD(56),		PORT_DATA_IO_PU_PD(57),
+	PORT_DATA_IO_PU_PD(58),		PORT_DATA_IO_PU_PD(59),
+
+	PORT_DATA_IO_PU_PD(60),		PORT_DATA_IO_PD(61),
+	PORT_DATA_IO_PD(62),		PORT_DATA_IO_PD(63),
+	PORT_DATA_IO_PD(64),		PORT_DATA_IO_PD(65),
+	PORT_DATA_IO_PU_PD(66),		PORT_DATA_IO_PU_PD(67),
+	PORT_DATA_IO_PU_PD(68),		PORT_DATA_IO_PU_PD(69),
+
+	PORT_DATA_IO_PU_PD(70),		PORT_DATA_IO_PU_PD(71),
+	PORT_DATA_IO_PU_PD(72),		PORT_DATA_IO_PU_PD(73),
+	PORT_DATA_IO_PU_PD(74),		PORT_DATA_IO_PU_PD(75),
+	PORT_DATA_IO_PU_PD(76),		PORT_DATA_IO_PU_PD(77),
+	PORT_DATA_IO_PU_PD(78),		PORT_DATA_IO_PU_PD(79),
+
+	PORT_DATA_IO_PU_PD(80),		PORT_DATA_IO_PU_PD(81),
+	PORT_DATA_IO(82),		PORT_DATA_IO_PU_PD(83),
+	PORT_DATA_IO(84),		PORT_DATA_IO_PD(85),
+	PORT_DATA_IO_PD(86),		PORT_DATA_IO_PD(87),
+	PORT_DATA_IO_PD(88),		PORT_DATA_IO_PD(89),
+
+	PORT_DATA_IO_PD(90),		PORT_DATA_IO_PU_PD(91),
+	PORT_DATA_IO_PU_PD(92),		PORT_DATA_IO_PU_PD(93),
+	PORT_DATA_IO_PU_PD(94),		PORT_DATA_IO_PU_PD(95),
+	PORT_DATA_IO_PU_PD(96),		PORT_DATA_IO_PU_PD(97),
+	PORT_DATA_IO_PU_PD(98),		PORT_DATA_IO_PU_PD(99),
+
+	PORT_DATA_IO_PU_PD(100),	PORT_DATA_IO(101),
+	PORT_DATA_IO_PU(102),		PORT_DATA_IO_PU_PD(103),
+	PORT_DATA_IO_PU(104),		PORT_DATA_IO_PU(105),
+	PORT_DATA_IO_PU_PD(106),	PORT_DATA_IO(107),
+	PORT_DATA_IO(108),		PORT_DATA_IO(109),
+
+	PORT_DATA_IO(110),		PORT_DATA_IO(111),
+	PORT_DATA_IO(112),		PORT_DATA_IO(113),
+	PORT_DATA_IO_PU_PD(114),	PORT_DATA_IO(115),
+	PORT_DATA_IO_PD(116),		PORT_DATA_IO_PD(117),
+	PORT_DATA_IO_PD(118),		PORT_DATA_IO_PD(119),
+
+	PORT_DATA_IO_PD(120),		PORT_DATA_IO_PD(121),
+	PORT_DATA_IO_PD(122),		PORT_DATA_IO_PD(123),
+	PORT_DATA_IO_PD(124),		PORT_DATA_IO(125),
+	PORT_DATA_IO(126),		PORT_DATA_IO(127),
+	PORT_DATA_IO(128),		PORT_DATA_IO(129),
+
+	PORT_DATA_IO(130),		PORT_DATA_IO(131),
+	PORT_DATA_IO(132),		PORT_DATA_IO(133),
+	PORT_DATA_IO(134),		PORT_DATA_IO(135),
+	PORT_DATA_IO(136),		PORT_DATA_IO(137),
+	PORT_DATA_IO(138),		PORT_DATA_IO(139),
+
+	PORT_DATA_IO(140),		PORT_DATA_IO(141),
+	PORT_DATA_IO_PU(142),		PORT_DATA_IO_PU(143),
+	PORT_DATA_IO_PU(144),		PORT_DATA_IO_PU(145),
+	PORT_DATA_IO_PU(146),		PORT_DATA_IO_PU(147),
+	PORT_DATA_IO_PU(148),		PORT_DATA_IO_PU(149),
+
+	PORT_DATA_IO_PU(150),		PORT_DATA_IO_PU(151),
+	PORT_DATA_IO_PU(152),		PORT_DATA_IO_PU(153),
+	PORT_DATA_IO_PU(154),		PORT_DATA_IO_PU(155),
+	PORT_DATA_IO_PU(156),		PORT_DATA_IO_PU(157),
+	PORT_DATA_IO_PD(158),		PORT_DATA_IO_PD(159),
+
+	PORT_DATA_IO_PU_PD(160),	PORT_DATA_IO_PD(161),
+	PORT_DATA_IO_PD(162),		PORT_DATA_IO_PD(163),
+	PORT_DATA_IO_PD(164),		PORT_DATA_IO_PD(165),
+	PORT_DATA_IO_PU(166),		PORT_DATA_IO_PU(167),
+	PORT_DATA_IO_PU(168),		PORT_DATA_IO_PU(169),
+
+	PORT_DATA_IO_PU(170),		PORT_DATA_IO_PU(171),
+	PORT_DATA_IO_PD(172),		PORT_DATA_IO_PD(173),
+	PORT_DATA_IO_PD(174),		PORT_DATA_IO_PD(175),
+	PORT_DATA_IO_PU(176),		PORT_DATA_IO_PU_PD(177),
+	PORT_DATA_IO_PU(178),		PORT_DATA_IO_PD(179),
+
+	PORT_DATA_IO_PD(180),		PORT_DATA_IO_PU(181),
+	PORT_DATA_IO_PU(182),		PORT_DATA_IO(183),
+	PORT_DATA_IO_PD(184),		PORT_DATA_IO_PD(185),
+	PORT_DATA_IO_PD(186),		PORT_DATA_IO_PD(187),
+	PORT_DATA_IO_PD(188),		PORT_DATA_IO_PD(189),
+
+	PORT_DATA_IO_PD(190),		PORT_DATA_IO_PD(191),
+	PORT_DATA_IO_PD(192),		PORT_DATA_IO_PU_PD(193),
+	PORT_DATA_IO_PU_PD(194),	PORT_DATA_IO_PD(195),
+	PORT_DATA_IO_PU_PD(196),	PORT_DATA_IO_PD(197),
+	PORT_DATA_IO_PU_PD(198),	PORT_DATA_IO_PU_PD(199),
+
+	PORT_DATA_IO_PU_PD(200),	PORT_DATA_IO_PU(201),
+	PORT_DATA_IO_PU_PD(202),	PORT_DATA_IO(203),
+	PORT_DATA_IO_PU_PD(204),	PORT_DATA_IO_PU_PD(205),
+	PORT_DATA_IO_PU_PD(206),	PORT_DATA_IO_PU_PD(207),
+	PORT_DATA_IO_PU_PD(208),	PORT_DATA_IO_PD(209),
+
+	PORT_DATA_IO_PD(210),		PORT_DATA_IO_PD(211),
+
+	/* Port0 */
+	PINMUX_DATA(DBGMDT2_MARK,		PORT0_FN1),
+	PINMUX_DATA(FSIAISLD_PORT0_MARK,	PORT0_FN2,	MSEL5CR_3_0),
+	PINMUX_DATA(FSIAOSLD1_MARK,		PORT0_FN3),
+	PINMUX_DATA(LCD0_D22_PORT0_MARK,	PORT0_FN4,	MSEL5CR_6_0),
+	PINMUX_DATA(SCIFA7_RXD_MARK,		PORT0_FN6),
+	PINMUX_DATA(LCD1_D4_MARK,		PORT0_FN7),
+	PINMUX_DATA(IRQ5_PORT0_MARK,		PORT0_FN0,	MSEL1CR_5_0),
+
+	/* Port1 */
+	PINMUX_DATA(DBGMDT1_MARK,		PORT1_FN1),
+	PINMUX_DATA(FMSISLD_PORT1_MARK,		PORT1_FN2,	MSEL5CR_5_0),
+	PINMUX_DATA(FSIAOSLD2_MARK,		PORT1_FN3),
+	PINMUX_DATA(LCD0_D23_PORT1_MARK,	PORT1_FN4,	MSEL5CR_6_0),
+	PINMUX_DATA(SCIFA7_TXD_MARK,		PORT1_FN6),
+	PINMUX_DATA(LCD1_D3_MARK,		PORT1_FN7),
+	PINMUX_DATA(IRQ5_PORT1_MARK,		PORT1_FN0,	MSEL1CR_5_1),
+
+	/* Port2 */
+	PINMUX_DATA(DBGMDT0_MARK,		PORT2_FN1),
+	PINMUX_DATA(SCIFB_SCK_PORT2_MARK,	PORT2_FN2,	MSEL5CR_17_1),
+	PINMUX_DATA(LCD0_D21_PORT2_MARK,	PORT2_FN4,	MSEL5CR_6_0),
+	PINMUX_DATA(LCD1_D2_MARK,		PORT2_FN7),
+	PINMUX_DATA(IRQ0_PORT2_MARK,		PORT2_FN0,	MSEL1CR_0_1),
+
+	/* Port3 */
+	PINMUX_DATA(DBGMD21_MARK,		PORT3_FN1),
+	PINMUX_DATA(SCIFB_RXD_PORT3_MARK,	PORT3_FN2,	MSEL5CR_17_1),
+	PINMUX_DATA(LCD0_D20_PORT3_MARK,	PORT3_FN4,	MSEL5CR_6_0),
+	PINMUX_DATA(LCD1_D1_MARK,		PORT3_FN7),
+
+	/* Port4 */
+	PINMUX_DATA(DBGMD20_MARK,		PORT4_FN1),
+	PINMUX_DATA(SCIFB_TXD_PORT4_MARK,	PORT4_FN2,	MSEL5CR_17_1),
+	PINMUX_DATA(LCD0_D19_PORT4_MARK,	PORT4_FN4,	MSEL5CR_6_0),
+	PINMUX_DATA(LCD1_D0_MARK,		PORT4_FN7),
+
+	/* Port5 */
+	PINMUX_DATA(DBGMD11_MARK,		PORT5_FN1),
+	PINMUX_DATA(BBIF2_TXD2_PORT5_MARK,	PORT5_FN2,	MSEL5CR_0_0),
+	PINMUX_DATA(FSIAISLD_PORT5_MARK,	PORT5_FN4,	MSEL5CR_3_1),
+	PINMUX_DATA(RSPI_SSL0_A_MARK,		PORT5_FN6),
+	PINMUX_DATA(LCD1_VCPWC_MARK,		PORT5_FN7),
+
+	/* Port6 */
+	PINMUX_DATA(DBGMD10_MARK,		PORT6_FN1),
+	PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK,	PORT6_FN2,	MSEL5CR_0_0),
+	PINMUX_DATA(FMSISLD_PORT6_MARK,		PORT6_FN4,	MSEL5CR_5_1),
+	PINMUX_DATA(RSPI_SSL1_A_MARK,		PORT6_FN6),
+	PINMUX_DATA(LCD1_VEPWC_MARK,		PORT6_FN7),
+
+	/* Port7 */
+	PINMUX_DATA(FSIAOLR_MARK,		PORT7_FN1),
+
+	/* Port8 */
+	PINMUX_DATA(FSIAOBT_MARK,		PORT8_FN1),
+
+	/* Port9 */
+	PINMUX_DATA(FSIAOSLD_MARK,		PORT9_FN1),
+	PINMUX_DATA(FSIASPDIF_PORT9_MARK,	PORT9_FN2,	MSEL5CR_4_0),
+
+	/* Port10 */
+	PINMUX_DATA(FSIAOMC_MARK,		PORT10_FN1),
+	PINMUX_DATA(SCIFA5_RXD_PORT10_MARK,	PORT10_FN3,	MSEL5CR_14_0,
+			MSEL5CR_15_0),
+	PINMUX_DATA(IRQ3_PORT10_MARK,		PORT10_FN0,	MSEL1CR_3_0),
+
+	/* Port11 */
+	PINMUX_DATA(FSIACK_MARK,		PORT11_FN1),
+	PINMUX_DATA(IRQ2_PORT11_MARK,		PORT11_FN0,	MSEL1CR_2_0),
+
+	/* Port12 */
+	PINMUX_DATA(FSIAILR_MARK,		PORT12_FN1),
+	PINMUX_DATA(SCIFA4_RXD_PORT12_MARK,	PORT12_FN2,	MSEL5CR_12_0,
+			MSEL5CR_11_0),
+	PINMUX_DATA(LCD1_RS_MARK,		PORT12_FN6),
+	PINMUX_DATA(LCD1_DISP_MARK,		PORT12_FN7),
+	PINMUX_DATA(IRQ2_PORT12_MARK,		PORT12_FN0,	MSEL1CR_2_1),
+
+	/* Port13 */
+	PINMUX_DATA(FSIAIBT_MARK,		PORT13_FN1),
+	PINMUX_DATA(SCIFA4_TXD_PORT13_MARK,	PORT13_FN2,	MSEL5CR_12_0,
+			MSEL5CR_11_0),
+	PINMUX_DATA(LCD1_RD_MARK,		PORT13_FN7),
+	PINMUX_DATA(IRQ0_PORT13_MARK,		PORT13_FN0,	MSEL1CR_0_0),
+
+	/* Port14 */
+	PINMUX_DATA(FMSOILR_MARK,		PORT14_FN1),
+	PINMUX_DATA(FMSIILR_MARK,		PORT14_FN2),
+	PINMUX_DATA(VIO_CKO1_MARK,		PORT14_FN3),
+	PINMUX_DATA(LCD1_D23_MARK,		PORT14_FN7),
+	PINMUX_DATA(IRQ3_PORT14_MARK,		PORT14_FN0,	MSEL1CR_3_1),
+
+	/* Port15 */
+	PINMUX_DATA(FMSOIBT_MARK,		PORT15_FN1),
+	PINMUX_DATA(FMSIIBT_MARK,		PORT15_FN2),
+	PINMUX_DATA(VIO_CKO2_MARK,		PORT15_FN3),
+	PINMUX_DATA(LCD1_D22_MARK,		PORT15_FN7),
+	PINMUX_DATA(IRQ4_PORT15_MARK,		PORT15_FN0,	MSEL1CR_4_0),
+
+	/* Port16 */
+	PINMUX_DATA(FMSOOLR_MARK,		PORT16_FN1),
+	PINMUX_DATA(FMSIOLR_MARK,		PORT16_FN2),
+
+	/* Port17 */
+	PINMUX_DATA(FMSOOBT_MARK,		PORT17_FN1),
+	PINMUX_DATA(FMSIOBT_MARK,		PORT17_FN2),
+
+	/* Port18 */
+	PINMUX_DATA(FMSOSLD_MARK,		PORT18_FN1),
+	PINMUX_DATA(FSIASPDIF_PORT18_MARK,	PORT18_FN2,	MSEL5CR_4_1),
+
+	/* Port19 */
+	PINMUX_DATA(FMSICK_MARK,		PORT19_FN1),
+	PINMUX_DATA(CS5A_PORT19_MARK,		PORT19_FN7,	MSEL5CR_2_1),
+	PINMUX_DATA(IRQ10_MARK,			PORT19_FN0),
+
+	/* Port20 */
+	PINMUX_DATA(FMSOCK_MARK,		PORT20_FN1),
+	PINMUX_DATA(SCIFA5_TXD_PORT20_MARK,	PORT20_FN3,	MSEL5CR_15_0,
+			MSEL5CR_14_0),
+	PINMUX_DATA(IRQ1_MARK,			PORT20_FN0),
+
+	/* Port21 */
+	PINMUX_DATA(SCIFA1_CTS_MARK,		PORT21_FN1),
+	PINMUX_DATA(SCIFA4_SCK_PORT21_MARK,	PORT21_FN2,	MSEL5CR_10_0),
+	PINMUX_DATA(TPU0TO1_MARK,		PORT21_FN4),
+	PINMUX_DATA(VIO1_FIELD_MARK,		PORT21_FN5),
+	PINMUX_DATA(STP0_IPD5_MARK,		PORT21_FN6),
+	PINMUX_DATA(LCD1_D10_MARK,		PORT21_FN7),
+
+	/* Port22 */
+	PINMUX_DATA(SCIFA2_SCK_PORT22_MARK,	PORT22_FN1,	MSEL5CR_7_0),
+	PINMUX_DATA(SIM_D_PORT22_MARK,		PORT22_FN4,	MSEL5CR_21_0),
+	PINMUX_DATA(VIO0_D13_PORT22_MARK,	PORT22_FN7,	MSEL5CR_27_1),
+
+	/* Port23 */
+	PINMUX_DATA(SCIFA1_RTS_MARK,		PORT23_FN1),
+	PINMUX_DATA(SCIFA5_SCK_PORT23_MARK,	PORT23_FN3,	MSEL5CR_13_0),
+	PINMUX_DATA(TPU0TO0_MARK,		PORT23_FN4),
+	PINMUX_DATA(VIO_CKO_1_MARK,		PORT23_FN5),
+	PINMUX_DATA(STP0_IPD2_MARK,		PORT23_FN6),
+	PINMUX_DATA(LCD1_D7_MARK,		PORT23_FN7),
+
+	/* Port24 */
+	PINMUX_DATA(VIO0_D15_PORT24_MARK,	PORT24_FN1,	MSEL5CR_27_0),
+	PINMUX_DATA(VIO1_D7_MARK,		PORT24_FN5),
+	PINMUX_DATA(SCIFA6_SCK_MARK,		PORT24_FN6),
+	PINMUX_DATA(SDHI2_CD_PORT24_MARK,	PORT24_FN7,	MSEL5CR_19_0),
+
+	/* Port25 */
+	PINMUX_DATA(VIO0_D14_PORT25_MARK,	PORT25_FN1,	MSEL5CR_27_0),
+	PINMUX_DATA(VIO1_D6_MARK,		PORT25_FN5),
+	PINMUX_DATA(SCIFA6_RXD_MARK,		PORT25_FN6),
+	PINMUX_DATA(SDHI2_WP_PORT25_MARK,	PORT25_FN7,	MSEL5CR_19_0),
+
+	/* Port26 */
+	PINMUX_DATA(VIO0_D13_PORT26_MARK,	PORT26_FN1,	MSEL5CR_27_0),
+	PINMUX_DATA(VIO1_D5_MARK,		PORT26_FN5),
+	PINMUX_DATA(SCIFA6_TXD_MARK,		PORT26_FN6),
+
+	/* Port27 - Port39 Function */
+	PINMUX_DATA(VIO0_D7_MARK,		PORT27_FN1),
+	PINMUX_DATA(VIO0_D6_MARK,		PORT28_FN1),
+	PINMUX_DATA(VIO0_D5_MARK,		PORT29_FN1),
+	PINMUX_DATA(VIO0_D4_MARK,		PORT30_FN1),
+	PINMUX_DATA(VIO0_D3_MARK,		PORT31_FN1),
+	PINMUX_DATA(VIO0_D2_MARK,		PORT32_FN1),
+	PINMUX_DATA(VIO0_D1_MARK,		PORT33_FN1),
+	PINMUX_DATA(VIO0_D0_MARK,		PORT34_FN1),
+	PINMUX_DATA(VIO0_CLK_MARK,		PORT35_FN1),
+	PINMUX_DATA(VIO_CKO_MARK,		PORT36_FN1),
+	PINMUX_DATA(VIO0_HD_MARK,		PORT37_FN1),
+	PINMUX_DATA(VIO0_FIELD_MARK,		PORT38_FN1),
+	PINMUX_DATA(VIO0_VD_MARK,		PORT39_FN1),
+
+	/* Port38 IRQ */
+	PINMUX_DATA(IRQ25_MARK,			PORT38_FN0),
+
+	/* Port40 */
+	PINMUX_DATA(LCD0_D18_PORT40_MARK,	PORT40_FN4,	MSEL5CR_6_0),
+	PINMUX_DATA(RSPI_CK_A_MARK,		PORT40_FN6),
+	PINMUX_DATA(LCD1_LCLK_MARK,		PORT40_FN7),
+
+	/* Port41 */
+	PINMUX_DATA(LCD0_D17_MARK,		PORT41_FN1),
+	PINMUX_DATA(MSIOF2_SS1_MARK,		PORT41_FN2),
+	PINMUX_DATA(IRQ31_PORT41_MARK,		PORT41_FN0,	MSEL1CR_31_1),
+
+	/* Port42 */
+	PINMUX_DATA(LCD0_D16_MARK,		PORT42_FN1),
+	PINMUX_DATA(MSIOF2_MCK1_MARK,		PORT42_FN2),
+	PINMUX_DATA(IRQ12_PORT42_MARK,		PORT42_FN0,	MSEL1CR_12_1),
+
+	/* Port43 */
+	PINMUX_DATA(LCD0_D15_MARK,		PORT43_FN1),
+	PINMUX_DATA(MSIOF2_MCK0_MARK,		PORT43_FN2),
+	PINMUX_DATA(KEYIN0_PORT43_MARK,		PORT43_FN3,	MSEL4CR_18_0),
+	PINMUX_DATA(DV_D15_MARK,		PORT43_FN6),
+
+	/* Port44 */
+	PINMUX_DATA(LCD0_D14_MARK,		PORT44_FN1),
+	PINMUX_DATA(MSIOF2_RSYNC_MARK,		PORT44_FN2),
+	PINMUX_DATA(KEYIN1_PORT44_MARK,		PORT44_FN3,	MSEL4CR_18_0),
+	PINMUX_DATA(DV_D14_MARK,		PORT44_FN6),
+
+	/* Port45 */
+	PINMUX_DATA(LCD0_D13_MARK,		PORT45_FN1),
+	PINMUX_DATA(MSIOF2_RSCK_MARK,		PORT45_FN2),
+	PINMUX_DATA(KEYIN2_PORT45_MARK,		PORT45_FN3,	MSEL4CR_18_0),
+	PINMUX_DATA(DV_D13_MARK,		PORT45_FN6),
+
+	/* Port46 */
+	PINMUX_DATA(LCD0_D12_MARK,		PORT46_FN1),
+	PINMUX_DATA(KEYIN3_PORT46_MARK,		PORT46_FN3,	MSEL4CR_18_0),
+	PINMUX_DATA(DV_D12_MARK,		PORT46_FN6),
+
+	/* Port47 */
+	PINMUX_DATA(LCD0_D11_MARK,		PORT47_FN1),
+	PINMUX_DATA(KEYIN4_MARK,		PORT47_FN3),
+	PINMUX_DATA(DV_D11_MARK,		PORT47_FN6),
+
+	/* Port48 */
+	PINMUX_DATA(LCD0_D10_MARK,		PORT48_FN1),
+	PINMUX_DATA(KEYIN5_MARK,		PORT48_FN3),
+	PINMUX_DATA(DV_D10_MARK,		PORT48_FN6),
+
+	/* Port49 */
+	PINMUX_DATA(LCD0_D9_MARK,		PORT49_FN1),
+	PINMUX_DATA(KEYIN6_MARK,		PORT49_FN3),
+	PINMUX_DATA(DV_D9_MARK,			PORT49_FN6),
+	PINMUX_DATA(IRQ30_PORT49_MARK,		PORT49_FN0,	MSEL1CR_30_1),
+
+	/* Port50 */
+	PINMUX_DATA(LCD0_D8_MARK,		PORT50_FN1),
+	PINMUX_DATA(KEYIN7_MARK,		PORT50_FN3),
+	PINMUX_DATA(DV_D8_MARK,			PORT50_FN6),
+	PINMUX_DATA(IRQ29_PORT50_MARK,		PORT50_FN0,	MSEL1CR_29_1),
+
+	/* Port51 */
+	PINMUX_DATA(LCD0_D7_MARK,		PORT51_FN1),
+	PINMUX_DATA(KEYOUT0_MARK,		PORT51_FN3),
+	PINMUX_DATA(DV_D7_MARK,			PORT51_FN6),
+
+	/* Port52 */
+	PINMUX_DATA(LCD0_D6_MARK,		PORT52_FN1),
+	PINMUX_DATA(KEYOUT1_MARK,		PORT52_FN3),
+	PINMUX_DATA(DV_D6_MARK,			PORT52_FN6),
+
+	/* Port53 */
+	PINMUX_DATA(LCD0_D5_MARK,		PORT53_FN1),
+	PINMUX_DATA(KEYOUT2_MARK,		PORT53_FN3),
+	PINMUX_DATA(DV_D5_MARK,			PORT53_FN6),
+
+	/* Port54 */
+	PINMUX_DATA(LCD0_D4_MARK,		PORT54_FN1),
+	PINMUX_DATA(KEYOUT3_MARK,		PORT54_FN3),
+	PINMUX_DATA(DV_D4_MARK,			PORT54_FN6),
+
+	/* Port55 */
+	PINMUX_DATA(LCD0_D3_MARK,		PORT55_FN1),
+	PINMUX_DATA(KEYOUT4_MARK,		PORT55_FN3),
+	PINMUX_DATA(KEYIN3_PORT55_MARK,		PORT55_FN4,	MSEL4CR_18_1),
+	PINMUX_DATA(DV_D3_MARK,			PORT55_FN6),
+
+	/* Port56 */
+	PINMUX_DATA(LCD0_D2_MARK,		PORT56_FN1),
+	PINMUX_DATA(KEYOUT5_MARK,		PORT56_FN3),
+	PINMUX_DATA(KEYIN2_PORT56_MARK,		PORT56_FN4,	MSEL4CR_18_1),
+	PINMUX_DATA(DV_D2_MARK,			PORT56_FN6),
+	PINMUX_DATA(IRQ28_PORT56_MARK,		PORT56_FN0,	MSEL1CR_28_1),
+
+	/* Port57 */
+	PINMUX_DATA(LCD0_D1_MARK,		PORT57_FN1),
+	PINMUX_DATA(KEYOUT6_MARK,		PORT57_FN3),
+	PINMUX_DATA(KEYIN1_PORT57_MARK,		PORT57_FN4,	MSEL4CR_18_1),
+	PINMUX_DATA(DV_D1_MARK,			PORT57_FN6),
+	PINMUX_DATA(IRQ27_PORT57_MARK,		PORT57_FN0,	MSEL1CR_27_1),
+
+	/* Port58 */
+	PINMUX_DATA(LCD0_D0_MARK,		PORT58_FN1),
+	PINMUX_DATA(KEYOUT7_MARK,		PORT58_FN3),
+	PINMUX_DATA(KEYIN0_PORT58_MARK,		PORT58_FN4,	MSEL4CR_18_1),
+	PINMUX_DATA(DV_D0_MARK,			PORT58_FN6),
+	PINMUX_DATA(IRQ26_PORT58_MARK,		PORT58_FN0,	MSEL1CR_26_1),
+
+	/* Port59 */
+	PINMUX_DATA(LCD0_VCPWC_MARK,		PORT59_FN1),
+	PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK,	PORT59_FN2,	MSEL5CR_0_0),
+	PINMUX_DATA(RSPI_MOSI_A_MARK,		PORT59_FN6),
+
+	/* Port60 */
+	PINMUX_DATA(LCD0_VEPWC_MARK,		PORT60_FN1),
+	PINMUX_DATA(BBIF2_RXD2_PORT60_MARK,	PORT60_FN2,	MSEL5CR_0_0),
+	PINMUX_DATA(RSPI_MISO_A_MARK,		PORT60_FN6),
+
+	/* Port61 */
+	PINMUX_DATA(LCD0_DON_MARK,		PORT61_FN1),
+	PINMUX_DATA(MSIOF2_TXD_MARK,		PORT61_FN2),
+
+	/* Port62 */
+	PINMUX_DATA(LCD0_DCK_MARK,		PORT62_FN1),
+	PINMUX_DATA(LCD0_WR_MARK,		PORT62_FN4),
+	PINMUX_DATA(DV_CLK_MARK,		PORT62_FN6),
+	PINMUX_DATA(IRQ15_PORT62_MARK,		PORT62_FN0,	MSEL1CR_15_1),
+
+	/* Port63 */
+	PINMUX_DATA(LCD0_VSYN_MARK,		PORT63_FN1),
+	PINMUX_DATA(DV_VSYNC_MARK,		PORT63_FN6),
+	PINMUX_DATA(IRQ14_PORT63_MARK,		PORT63_FN0,	MSEL1CR_14_1),
+
+	/* Port64 */
+	PINMUX_DATA(LCD0_HSYN_MARK,		PORT64_FN1),
+	PINMUX_DATA(LCD0_CS_MARK,		PORT64_FN4),
+	PINMUX_DATA(DV_HSYNC_MARK,		PORT64_FN6),
+	PINMUX_DATA(IRQ13_PORT64_MARK,		PORT64_FN0,	MSEL1CR_13_1),
+
+	/* Port65 */
+	PINMUX_DATA(LCD0_DISP_MARK,		PORT65_FN1),
+	PINMUX_DATA(MSIOF2_TSCK_MARK,		PORT65_FN2),
+	PINMUX_DATA(LCD0_RS_MARK,		PORT65_FN4),
+
+	/* Port66 */
+	PINMUX_DATA(MEMC_INT_MARK,		PORT66_FN1),
+	PINMUX_DATA(TPU0TO2_PORT66_MARK,	PORT66_FN3,	MSEL5CR_25_0),
+	PINMUX_DATA(MMC0_CLK_PORT66_MARK,	PORT66_FN4,	MSEL4CR_15_0),
+	PINMUX_DATA(SDHI1_CLK_MARK,		PORT66_FN6),
+
+	/* Port67 - Port73 Function1 */
+	PINMUX_DATA(MEMC_CS0_MARK,		PORT67_FN1),
+	PINMUX_DATA(MEMC_AD8_MARK,		PORT68_FN1),
+	PINMUX_DATA(MEMC_AD9_MARK,		PORT69_FN1),
+	PINMUX_DATA(MEMC_AD10_MARK,		PORT70_FN1),
+	PINMUX_DATA(MEMC_AD11_MARK,		PORT71_FN1),
+	PINMUX_DATA(MEMC_AD12_MARK,		PORT72_FN1),
+	PINMUX_DATA(MEMC_AD13_MARK,		PORT73_FN1),
+
+	/* Port67 - Port73 Function2 */
+	PINMUX_DATA(MSIOF1_SS1_PORT67_MARK,	PORT67_FN2,	MSEL4CR_10_1),
+	PINMUX_DATA(MSIOF1_RSCK_MARK,		PORT68_FN2),
+	PINMUX_DATA(MSIOF1_RSYNC_MARK,		PORT69_FN2),
+	PINMUX_DATA(MSIOF1_MCK0_MARK,		PORT70_FN2),
+	PINMUX_DATA(MSIOF1_MCK1_MARK,		PORT71_FN2),
+	PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK,	PORT72_FN2,	MSEL4CR_10_1),
+	PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK,	PORT73_FN2,	MSEL4CR_10_1),
+
+	/* Port67 - Port73 Function4 */
+	PINMUX_DATA(MMC0_CMD_PORT67_MARK,	PORT67_FN4,	MSEL4CR_15_0),
+	PINMUX_DATA(MMC0_D0_PORT68_MARK,	PORT68_FN4,	MSEL4CR_15_0),
+	PINMUX_DATA(MMC0_D1_PORT69_MARK,	PORT69_FN4,	MSEL4CR_15_0),
+	PINMUX_DATA(MMC0_D2_PORT70_MARK,	PORT70_FN4,	MSEL4CR_15_0),
+	PINMUX_DATA(MMC0_D3_PORT71_MARK,	PORT71_FN4,	MSEL4CR_15_0),
+	PINMUX_DATA(MMC0_D4_PORT72_MARK,	PORT72_FN4,	MSEL4CR_15_0),
+	PINMUX_DATA(MMC0_D5_PORT73_MARK,	PORT73_FN4,	MSEL4CR_15_0),
+
+	/* Port67 - Port73 Function6 */
+	PINMUX_DATA(SDHI1_CMD_MARK,		PORT67_FN6),
+	PINMUX_DATA(SDHI1_D0_MARK,		PORT68_FN6),
+	PINMUX_DATA(SDHI1_D1_MARK,		PORT69_FN6),
+	PINMUX_DATA(SDHI1_D2_MARK,		PORT70_FN6),
+	PINMUX_DATA(SDHI1_D3_MARK,		PORT71_FN6),
+	PINMUX_DATA(SDHI1_CD_MARK,		PORT72_FN6),
+	PINMUX_DATA(SDHI1_WP_MARK,		PORT73_FN6),
+
+	/* Port67 - Port71 IRQ */
+	PINMUX_DATA(IRQ20_MARK,			PORT67_FN0),
+	PINMUX_DATA(IRQ16_PORT68_MARK,		PORT68_FN0,	MSEL1CR_16_0),
+	PINMUX_DATA(IRQ17_MARK,			PORT69_FN0),
+	PINMUX_DATA(IRQ18_MARK,			PORT70_FN0),
+	PINMUX_DATA(IRQ19_MARK,			PORT71_FN0),
+
+	/* Port74 */
+	PINMUX_DATA(MEMC_AD14_MARK,		PORT74_FN1),
+	PINMUX_DATA(MSIOF1_TXD_PORT74_MARK,	PORT74_FN2,	MSEL4CR_10_1),
+	PINMUX_DATA(MMC0_D6_PORT74_MARK,	PORT74_FN4,	MSEL4CR_15_0),
+	PINMUX_DATA(STP1_IPD7_MARK,		PORT74_FN6),
+	PINMUX_DATA(LCD1_D21_MARK,		PORT74_FN7),
+
+	/* Port75 */
+	PINMUX_DATA(MEMC_AD15_MARK,		PORT75_FN1),
+	PINMUX_DATA(MSIOF1_RXD_PORT75_MARK,	PORT75_FN2,	MSEL4CR_10_1),
+	PINMUX_DATA(MMC0_D7_PORT75_MARK,	PORT75_FN4,	MSEL4CR_15_0),
+	PINMUX_DATA(STP1_IPD6_MARK,		PORT75_FN6),
+	PINMUX_DATA(LCD1_D20_MARK,		PORT75_FN7),
+
+	/* Port76 - Port80 Function */
+	PINMUX_DATA(SDHI0_CMD_MARK,		PORT76_FN1),
+	PINMUX_DATA(SDHI0_D0_MARK,		PORT77_FN1),
+	PINMUX_DATA(SDHI0_D1_MARK,		PORT78_FN1),
+	PINMUX_DATA(SDHI0_D2_MARK,		PORT79_FN1),
+	PINMUX_DATA(SDHI0_D3_MARK,		PORT80_FN1),
+
+	/* Port81 */
+	PINMUX_DATA(SDHI0_CD_MARK,		PORT81_FN1),
+	PINMUX_DATA(IRQ26_PORT81_MARK,		PORT81_FN0,	MSEL1CR_26_0),
+
+	/* Port82 - Port88 Function */
+	PINMUX_DATA(SDHI0_CLK_MARK,		PORT82_FN1),
+	PINMUX_DATA(SDHI0_WP_MARK,		PORT83_FN1),
+	PINMUX_DATA(RESETOUTS_MARK,		PORT84_FN1),
+	PINMUX_DATA(USB0_PPON_MARK,		PORT85_FN1),
+	PINMUX_DATA(USB0_OCI_MARK,		PORT86_FN1),
+	PINMUX_DATA(USB1_PPON_MARK,		PORT87_FN1),
+	PINMUX_DATA(USB1_OCI_MARK,		PORT88_FN1),
+
+	/* Port89 */
+	PINMUX_DATA(DREQ0_MARK,			PORT89_FN1),
+	PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK,	PORT89_FN2,	MSEL5CR_0_1),
+	PINMUX_DATA(RSPI_SSL3_A_MARK,		PORT89_FN6),
+
+	/* Port90 */
+	PINMUX_DATA(DACK0_MARK,			PORT90_FN1),
+	PINMUX_DATA(BBIF2_RXD2_PORT90_MARK,	PORT90_FN2,	MSEL5CR_0_1),
+	PINMUX_DATA(RSPI_SSL2_A_MARK,		PORT90_FN6),
+	PINMUX_DATA(WAIT_PORT90_MARK,		PORT90_FN7,	MSEL5CR_2_1),
+
+	/* Port91 */
+	PINMUX_DATA(MEMC_AD0_MARK,		PORT91_FN1),
+	PINMUX_DATA(BBIF1_RXD_MARK,		PORT91_FN2),
+	PINMUX_DATA(SCIFA5_TXD_PORT91_MARK,	PORT91_FN3,	MSEL5CR_15_1,
+			MSEL5CR_14_0),
+	PINMUX_DATA(LCD1_D5_MARK,		PORT91_FN7),
+
+	/* Port92 */
+	PINMUX_DATA(MEMC_AD1_MARK,		PORT92_FN1),
+	PINMUX_DATA(BBIF1_TSYNC_MARK,		PORT92_FN2),
+	PINMUX_DATA(SCIFA5_RXD_PORT92_MARK,	PORT92_FN3,	MSEL5CR_15_1,
+			MSEL5CR_14_0),
+	PINMUX_DATA(STP0_IPD1_MARK,		PORT92_FN6),
+	PINMUX_DATA(LCD1_D6_MARK,		PORT92_FN7),
+
+	/* Port93 */
+	PINMUX_DATA(MEMC_AD2_MARK,		PORT93_FN1),
+	PINMUX_DATA(BBIF1_TSCK_MARK,		PORT93_FN2),
+	PINMUX_DATA(SCIFA4_TXD_PORT93_MARK,	PORT93_FN3,	MSEL5CR_12_1,
+			MSEL5CR_11_0),
+	PINMUX_DATA(STP0_IPD3_MARK,		PORT93_FN6),
+	PINMUX_DATA(LCD1_D8_MARK,		PORT93_FN7),
+
+	/* Port94 */
+	PINMUX_DATA(MEMC_AD3_MARK,		PORT94_FN1),
+	PINMUX_DATA(BBIF1_TXD_MARK,		PORT94_FN2),
+	PINMUX_DATA(SCIFA4_RXD_PORT94_MARK,	PORT94_FN3,	MSEL5CR_12_1,
+			MSEL5CR_11_0),
+	PINMUX_DATA(STP0_IPD4_MARK,		PORT94_FN6),
+	PINMUX_DATA(LCD1_D9_MARK,		PORT94_FN7),
+
+	/* Port95 */
+	PINMUX_DATA(MEMC_CS1_MARK,		PORT95_FN1,	MSEL4CR_6_0),
+	PINMUX_DATA(MEMC_A1_MARK,		PORT95_FN1,	MSEL4CR_6_1),
+
+	PINMUX_DATA(SCIFA2_CTS_MARK,		PORT95_FN2),
+	PINMUX_DATA(SIM_RST_MARK,		PORT95_FN4),
+	PINMUX_DATA(VIO0_D14_PORT95_MARK,	PORT95_FN7,	MSEL5CR_27_1),
+	PINMUX_DATA(IRQ22_MARK,			PORT95_FN0),
+
+	/* Port96 */
+	PINMUX_DATA(MEMC_ADV_MARK,		PORT96_FN1,	MSEL4CR_6_0),
+	PINMUX_DATA(MEMC_DREQ0_MARK,		PORT96_FN1,	MSEL4CR_6_1),
+
+	PINMUX_DATA(SCIFA2_RTS_MARK,		PORT96_FN2),
+	PINMUX_DATA(SIM_CLK_MARK,		PORT96_FN4),
+	PINMUX_DATA(VIO0_D15_PORT96_MARK,	PORT96_FN7,	MSEL5CR_27_1),
+	PINMUX_DATA(IRQ23_MARK,			PORT96_FN0),
+
+	/* Port97 */
+	PINMUX_DATA(MEMC_AD4_MARK,		PORT97_FN1),
+	PINMUX_DATA(BBIF1_RSCK_MARK,		PORT97_FN2),
+	PINMUX_DATA(LCD1_CS_MARK,		PORT97_FN6),
+	PINMUX_DATA(LCD1_HSYN_MARK,		PORT97_FN7),
+	PINMUX_DATA(IRQ12_PORT97_MARK,		PORT97_FN0,	MSEL1CR_12_0),
+
+	/* Port98 */
+	PINMUX_DATA(MEMC_AD5_MARK,		PORT98_FN1),
+	PINMUX_DATA(BBIF1_RSYNC_MARK,		PORT98_FN2),
+	PINMUX_DATA(LCD1_VSYN_MARK,		PORT98_FN7),
+	PINMUX_DATA(IRQ13_PORT98_MARK,		PORT98_FN0,	MSEL1CR_13_0),
+
+	/* Port99 */
+	PINMUX_DATA(MEMC_AD6_MARK,		PORT99_FN1),
+	PINMUX_DATA(BBIF1_FLOW_MARK,		PORT99_FN2),
+	PINMUX_DATA(LCD1_WR_MARK,		PORT99_FN6),
+	PINMUX_DATA(LCD1_DCK_MARK,		PORT99_FN7),
+	PINMUX_DATA(IRQ14_PORT99_MARK,		PORT99_FN0,	MSEL1CR_14_0),
+
+	/* Port100 */
+	PINMUX_DATA(MEMC_AD7_MARK,		PORT100_FN1),
+	PINMUX_DATA(BBIF1_RX_FLOW_N_MARK,	PORT100_FN2),
+	PINMUX_DATA(LCD1_DON_MARK,		PORT100_FN7),
+	PINMUX_DATA(IRQ15_PORT100_MARK,		PORT100_FN0,	MSEL1CR_15_0),
+
+	/* Port101 */
+	PINMUX_DATA(FCE0_MARK,			PORT101_FN1),
+
+	/* Port102 */
+	PINMUX_DATA(FRB_MARK,			PORT102_FN1),
+	PINMUX_DATA(LCD0_LCLK_PORT102_MARK,	PORT102_FN4,	MSEL5CR_6_0),
+
+	/* Port103 */
+	PINMUX_DATA(CS5B_MARK,			PORT103_FN1),
+	PINMUX_DATA(FCE1_MARK,			PORT103_FN2),
+	PINMUX_DATA(MMC1_CLK_PORT103_MARK,	PORT103_FN3,	MSEL4CR_15_1),
+
+	/* Port104 */
+	PINMUX_DATA(CS6A_MARK,			PORT104_FN1),
+	PINMUX_DATA(MMC1_CMD_PORT104_MARK,	PORT104_FN3,	MSEL4CR_15_1),
+	PINMUX_DATA(IRQ11_MARK,			PORT104_FN0),
+
+	/* Port105 */
+	PINMUX_DATA(CS5A_PORT105_MARK,		PORT105_FN1,	MSEL5CR_2_0),
+	PINMUX_DATA(SCIFA3_RTS_PORT105_MARK,	PORT105_FN4,	MSEL5CR_8_0),
+
+	/* Port106 */
+	PINMUX_DATA(IOIS16_MARK,		PORT106_FN1),
+	PINMUX_DATA(IDE_EXBUF_ENB_MARK,		PORT106_FN6),
+
+	/* Port107 - Port115 Function */
+	PINMUX_DATA(WE3_ICIOWR_MARK,		PORT107_FN1),
+	PINMUX_DATA(WE2_ICIORD_MARK,		PORT108_FN1),
+	PINMUX_DATA(CS0_MARK,			PORT109_FN1),
+	PINMUX_DATA(CS2_MARK,			PORT110_FN1),
+	PINMUX_DATA(CS4_MARK,			PORT111_FN1),
+	PINMUX_DATA(WE1_MARK,			PORT112_FN1),
+	PINMUX_DATA(WE0_FWE_MARK,		PORT113_FN1),
+	PINMUX_DATA(RDWR_MARK,			PORT114_FN1),
+	PINMUX_DATA(RD_FSC_MARK,		PORT115_FN1),
+
+	/* Port116 */
+	PINMUX_DATA(A25_MARK,			PORT116_FN1),
+	PINMUX_DATA(MSIOF0_SS2_MARK,		PORT116_FN2),
+	PINMUX_DATA(MSIOF1_SS2_PORT116_MARK,	PORT116_FN3,	MSEL4CR_10_0),
+	PINMUX_DATA(SCIFA3_SCK_PORT116_MARK,	PORT116_FN4,	MSEL5CR_8_0),
+	PINMUX_DATA(GPO1_MARK,			PORT116_FN5),
+
+	/* Port117 */
+	PINMUX_DATA(A24_MARK,			PORT117_FN1),
+	PINMUX_DATA(MSIOF0_SS1_MARK,		PORT117_FN2),
+	PINMUX_DATA(MSIOF1_SS1_PORT117_MARK,	PORT117_FN3,	MSEL4CR_10_0),
+	PINMUX_DATA(SCIFA3_CTS_PORT117_MARK,	PORT117_FN4,	MSEL5CR_8_0),
+	PINMUX_DATA(GPO0_MARK,			PORT117_FN5),
+
+	/* Port118 */
+	PINMUX_DATA(A23_MARK,			PORT118_FN1),
+	PINMUX_DATA(MSIOF0_MCK1_MARK,		PORT118_FN2),
+	PINMUX_DATA(MSIOF1_RXD_PORT118_MARK,	PORT118_FN3,	MSEL4CR_10_0),
+	PINMUX_DATA(GPI1_MARK,			PORT118_FN5),
+	PINMUX_DATA(IRQ9_PORT118_MARK,		PORT118_FN0,	MSEL1CR_9_0),
+
+	/* Port119 */
+	PINMUX_DATA(A22_MARK,			PORT119_FN1),
+	PINMUX_DATA(MSIOF0_MCK0_MARK,		PORT119_FN2),
+	PINMUX_DATA(MSIOF1_TXD_PORT119_MARK,	PORT119_FN3,	MSEL4CR_10_0),
+	PINMUX_DATA(GPI0_MARK,			PORT119_FN5),
+	PINMUX_DATA(IRQ8_MARK,			PORT119_FN0),
+
+	/* Port120 */
+	PINMUX_DATA(A21_MARK,			PORT120_FN1),
+	PINMUX_DATA(MSIOF0_RSYNC_MARK,		PORT120_FN2),
+	PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK,	PORT120_FN3,	MSEL4CR_10_0),
+	PINMUX_DATA(IRQ7_PORT120_MARK,		PORT120_FN0,	MSEL1CR_7_0),
+
+	/* Port121 */
+	PINMUX_DATA(A20_MARK,			PORT121_FN1),
+	PINMUX_DATA(MSIOF0_RSCK_MARK,		PORT121_FN2),
+	PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK,	PORT121_FN3,	MSEL4CR_10_0),
+	PINMUX_DATA(IRQ6_PORT121_MARK,		PORT121_FN0,	MSEL1CR_6_0),
+
+	/* Port122 */
+	PINMUX_DATA(A19_MARK,			PORT122_FN1),
+	PINMUX_DATA(MSIOF0_RXD_MARK,		PORT122_FN2),
+
+	/* Port123 */
+	PINMUX_DATA(A18_MARK,			PORT123_FN1),
+	PINMUX_DATA(MSIOF0_TSCK_MARK,		PORT123_FN2),
+
+	/* Port124 */
+	PINMUX_DATA(A17_MARK,			PORT124_FN1),
+	PINMUX_DATA(MSIOF0_TSYNC_MARK,		PORT124_FN2),
+
+	/* Port125 - Port141 Function */
+	PINMUX_DATA(A16_MARK,			PORT125_FN1),
+	PINMUX_DATA(A15_MARK,			PORT126_FN1),
+	PINMUX_DATA(A14_MARK,			PORT127_FN1),
+	PINMUX_DATA(A13_MARK,			PORT128_FN1),
+	PINMUX_DATA(A12_MARK,			PORT129_FN1),
+	PINMUX_DATA(A11_MARK,			PORT130_FN1),
+	PINMUX_DATA(A10_MARK,			PORT131_FN1),
+	PINMUX_DATA(A9_MARK,			PORT132_FN1),
+	PINMUX_DATA(A8_MARK,			PORT133_FN1),
+	PINMUX_DATA(A7_MARK,			PORT134_FN1),
+	PINMUX_DATA(A6_MARK,			PORT135_FN1),
+	PINMUX_DATA(A5_FCDE_MARK,		PORT136_FN1),
+	PINMUX_DATA(A4_FOE_MARK,		PORT137_FN1),
+	PINMUX_DATA(A3_MARK,			PORT138_FN1),
+	PINMUX_DATA(A2_MARK,			PORT139_FN1),
+	PINMUX_DATA(A1_MARK,			PORT140_FN1),
+	PINMUX_DATA(CKO_MARK,			PORT141_FN1),
+
+	/* Port142 - Port157 Function1 */
+	PINMUX_DATA(D15_NAF15_MARK,		PORT142_FN1),
+	PINMUX_DATA(D14_NAF14_MARK,		PORT143_FN1),
+	PINMUX_DATA(D13_NAF13_MARK,		PORT144_FN1),
+	PINMUX_DATA(D12_NAF12_MARK,		PORT145_FN1),
+	PINMUX_DATA(D11_NAF11_MARK,		PORT146_FN1),
+	PINMUX_DATA(D10_NAF10_MARK,		PORT147_FN1),
+	PINMUX_DATA(D9_NAF9_MARK,		PORT148_FN1),
+	PINMUX_DATA(D8_NAF8_MARK,		PORT149_FN1),
+	PINMUX_DATA(D7_NAF7_MARK,		PORT150_FN1),
+	PINMUX_DATA(D6_NAF6_MARK,		PORT151_FN1),
+	PINMUX_DATA(D5_NAF5_MARK,		PORT152_FN1),
+	PINMUX_DATA(D4_NAF4_MARK,		PORT153_FN1),
+	PINMUX_DATA(D3_NAF3_MARK,		PORT154_FN1),
+	PINMUX_DATA(D2_NAF2_MARK,		PORT155_FN1),
+	PINMUX_DATA(D1_NAF1_MARK,		PORT156_FN1),
+	PINMUX_DATA(D0_NAF0_MARK,		PORT157_FN1),
+
+	/* Port142 - Port149 Function3 */
+	PINMUX_DATA(MMC1_D7_PORT142_MARK,	PORT142_FN3,	MSEL4CR_15_1),
+	PINMUX_DATA(MMC1_D6_PORT143_MARK,	PORT143_FN3,	MSEL4CR_15_1),
+	PINMUX_DATA(MMC1_D5_PORT144_MARK,	PORT144_FN3,	MSEL4CR_15_1),
+	PINMUX_DATA(MMC1_D4_PORT145_MARK,	PORT145_FN3,	MSEL4CR_15_1),
+	PINMUX_DATA(MMC1_D3_PORT146_MARK,	PORT146_FN3,	MSEL4CR_15_1),
+	PINMUX_DATA(MMC1_D2_PORT147_MARK,	PORT147_FN3,	MSEL4CR_15_1),
+	PINMUX_DATA(MMC1_D1_PORT148_MARK,	PORT148_FN3,	MSEL4CR_15_1),
+	PINMUX_DATA(MMC1_D0_PORT149_MARK,	PORT149_FN3,	MSEL4CR_15_1),
+
+	/* Port158 */
+	PINMUX_DATA(D31_MARK,			PORT158_FN1),
+	PINMUX_DATA(SCIFA3_SCK_PORT158_MARK,	PORT158_FN2,	MSEL5CR_8_1),
+	PINMUX_DATA(RMII_REF125CK_MARK,		PORT158_FN3),
+	PINMUX_DATA(LCD0_D21_PORT158_MARK,	PORT158_FN4,	MSEL5CR_6_1),
+	PINMUX_DATA(IRDA_FIRSEL_MARK,		PORT158_FN5),
+	PINMUX_DATA(IDE_D15_MARK,		PORT158_FN6),
+
+	/* Port159 */
+	PINMUX_DATA(D30_MARK,			PORT159_FN1),
+	PINMUX_DATA(SCIFA3_RXD_PORT159_MARK,	PORT159_FN2,	MSEL5CR_8_1),
+	PINMUX_DATA(RMII_REF50CK_MARK,		PORT159_FN3),
+	PINMUX_DATA(LCD0_D23_PORT159_MARK,	PORT159_FN4,	MSEL5CR_6_1),
+	PINMUX_DATA(IDE_D14_MARK,		PORT159_FN6),
+
+	/* Port160 */
+	PINMUX_DATA(D29_MARK,			PORT160_FN1),
+	PINMUX_DATA(SCIFA3_TXD_PORT160_MARK,	PORT160_FN2,	MSEL5CR_8_1),
+	PINMUX_DATA(LCD0_D22_PORT160_MARK,	PORT160_FN4,	MSEL5CR_6_1),
+	PINMUX_DATA(VIO1_HD_MARK,		PORT160_FN5),
+	PINMUX_DATA(IDE_D13_MARK,		PORT160_FN6),
+
+	/* Port161 */
+	PINMUX_DATA(D28_MARK,			PORT161_FN1),
+	PINMUX_DATA(SCIFA3_RTS_PORT161_MARK,	PORT161_FN2,	MSEL5CR_8_1),
+	PINMUX_DATA(ET_RX_DV_MARK,		PORT161_FN3),
+	PINMUX_DATA(LCD0_D20_PORT161_MARK,	PORT161_FN4,	MSEL5CR_6_1),
+	PINMUX_DATA(IRDA_IN_MARK,		PORT161_FN5),
+	PINMUX_DATA(IDE_D12_MARK,		PORT161_FN6),
+
+	/* Port162 */
+	PINMUX_DATA(D27_MARK,			PORT162_FN1),
+	PINMUX_DATA(SCIFA3_CTS_PORT162_MARK,	PORT162_FN2,	MSEL5CR_8_1),
+	PINMUX_DATA(LCD0_D19_PORT162_MARK,	PORT162_FN4,	MSEL5CR_6_1),
+	PINMUX_DATA(IRDA_OUT_MARK,		PORT162_FN5),
+	PINMUX_DATA(IDE_D11_MARK,		PORT162_FN6),
+
+	/* Port163 */
+	PINMUX_DATA(D26_MARK,			PORT163_FN1),
+	PINMUX_DATA(MSIOF2_SS2_MARK,		PORT163_FN2),
+	PINMUX_DATA(ET_COL_MARK,		PORT163_FN3),
+	PINMUX_DATA(LCD0_D18_PORT163_MARK,	PORT163_FN4,	MSEL5CR_6_1),
+	PINMUX_DATA(IROUT_MARK,			PORT163_FN5),
+	PINMUX_DATA(IDE_D10_MARK,		PORT163_FN6),
+
+	/* Port164 */
+	PINMUX_DATA(D25_MARK,			PORT164_FN1),
+	PINMUX_DATA(MSIOF2_TSYNC_MARK,		PORT164_FN2),
+	PINMUX_DATA(ET_PHY_INT_MARK,		PORT164_FN3),
+	PINMUX_DATA(LCD0_RD_MARK,		PORT164_FN4),
+	PINMUX_DATA(IDE_D9_MARK,		PORT164_FN6),
+
+	/* Port165 */
+	PINMUX_DATA(D24_MARK,			PORT165_FN1),
+	PINMUX_DATA(MSIOF2_RXD_MARK,		PORT165_FN2),
+	PINMUX_DATA(LCD0_LCLK_PORT165_MARK,	PORT165_FN4,	MSEL5CR_6_1),
+	PINMUX_DATA(IDE_D8_MARK,		PORT165_FN6),
+
+	/* Port166 - Port171 Function1 */
+	PINMUX_DATA(D21_MARK,			PORT166_FN1),
+	PINMUX_DATA(D20_MARK,			PORT167_FN1),
+	PINMUX_DATA(D19_MARK,			PORT168_FN1),
+	PINMUX_DATA(D18_MARK,			PORT169_FN1),
+	PINMUX_DATA(D17_MARK,			PORT170_FN1),
+	PINMUX_DATA(D16_MARK,			PORT171_FN1),
+
+	/* Port166 - Port171 Function3 */
+	PINMUX_DATA(ET_ETXD5_MARK,		PORT166_FN3),
+	PINMUX_DATA(ET_ETXD4_MARK,		PORT167_FN3),
+	PINMUX_DATA(ET_ETXD3_MARK,		PORT168_FN3),
+	PINMUX_DATA(ET_ETXD2_MARK,		PORT169_FN3),
+	PINMUX_DATA(ET_ETXD1_MARK,		PORT170_FN3),
+	PINMUX_DATA(ET_ETXD0_MARK,		PORT171_FN3),
+
+	/* Port166 - Port171 Function6 */
+	PINMUX_DATA(IDE_D5_MARK,		PORT166_FN6),
+	PINMUX_DATA(IDE_D4_MARK,		PORT167_FN6),
+	PINMUX_DATA(IDE_D3_MARK,		PORT168_FN6),
+	PINMUX_DATA(IDE_D2_MARK,		PORT169_FN6),
+	PINMUX_DATA(IDE_D1_MARK,		PORT170_FN6),
+	PINMUX_DATA(IDE_D0_MARK,		PORT171_FN6),
+
+	/* Port167 - Port171 IRQ */
+	PINMUX_DATA(IRQ31_PORT167_MARK,		PORT167_FN0,	MSEL1CR_31_0),
+	PINMUX_DATA(IRQ27_PORT168_MARK,		PORT168_FN0,	MSEL1CR_27_0),
+	PINMUX_DATA(IRQ28_PORT169_MARK,		PORT169_FN0,	MSEL1CR_28_0),
+	PINMUX_DATA(IRQ29_PORT170_MARK,		PORT170_FN0,	MSEL1CR_29_0),
+	PINMUX_DATA(IRQ30_PORT171_MARK,		PORT171_FN0,	MSEL1CR_30_0),
+
+	/* Port172 */
+	PINMUX_DATA(D23_MARK,			PORT172_FN1),
+	PINMUX_DATA(SCIFB_RTS_PORT172_MARK,	PORT172_FN2,	MSEL5CR_17_1),
+	PINMUX_DATA(ET_ETXD7_MARK,		PORT172_FN3),
+	PINMUX_DATA(IDE_D7_MARK,		PORT172_FN6),
+	PINMUX_DATA(IRQ4_PORT172_MARK,		PORT172_FN0,	MSEL1CR_4_1),
+
+	/* Port173 */
+	PINMUX_DATA(D22_MARK,			PORT173_FN1),
+	PINMUX_DATA(SCIFB_CTS_PORT173_MARK,	PORT173_FN2,	MSEL5CR_17_1),
+	PINMUX_DATA(ET_ETXD6_MARK,		PORT173_FN3),
+	PINMUX_DATA(IDE_D6_MARK,		PORT173_FN6),
+	PINMUX_DATA(IRQ6_PORT173_MARK,		PORT173_FN0,	MSEL1CR_6_1),
+
+	/* Port174 */
+	PINMUX_DATA(A26_MARK,			PORT174_FN1),
+	PINMUX_DATA(MSIOF0_TXD_MARK,		PORT174_FN2),
+	PINMUX_DATA(ET_RX_CLK_MARK,		PORT174_FN3),
+	PINMUX_DATA(SCIFA3_RXD_PORT174_MARK,	PORT174_FN4,	MSEL5CR_8_0),
+
+	/* Port175 */
+	PINMUX_DATA(A0_MARK,			PORT175_FN1),
+	PINMUX_DATA(BS_MARK,			PORT175_FN2),
+	PINMUX_DATA(ET_WOL_MARK,		PORT175_FN3),
+	PINMUX_DATA(SCIFA3_TXD_PORT175_MARK,	PORT175_FN4,	MSEL5CR_8_0),
+
+	/* Port176 */
+	PINMUX_DATA(ET_GTX_CLK_MARK,		PORT176_FN3),
+
+	/* Port177 */
+	PINMUX_DATA(WAIT_PORT177_MARK,		PORT177_FN1,	MSEL5CR_2_0),
+	PINMUX_DATA(ET_LINK_MARK,		PORT177_FN3),
+	PINMUX_DATA(IDE_IOWR_MARK,		PORT177_FN6),
+	PINMUX_DATA(SDHI2_WP_PORT177_MARK,	PORT177_FN7,	MSEL5CR_19_1),
+
+	/* Port178 */
+	PINMUX_DATA(VIO0_D12_MARK,		PORT178_FN1),
+	PINMUX_DATA(VIO1_D4_MARK,		PORT178_FN5),
+	PINMUX_DATA(IDE_IORD_MARK,		PORT178_FN6),
+
+	/* Port179 */
+	PINMUX_DATA(VIO0_D11_MARK,		PORT179_FN1),
+	PINMUX_DATA(VIO1_D3_MARK,		PORT179_FN5),
+	PINMUX_DATA(IDE_IORDY_MARK,		PORT179_FN6),
+
+	/* Port180 */
+	PINMUX_DATA(VIO0_D10_MARK,		PORT180_FN1),
+	PINMUX_DATA(TPU0TO3_MARK,		PORT180_FN4),
+	PINMUX_DATA(VIO1_D2_MARK,		PORT180_FN5),
+	PINMUX_DATA(IDE_INT_MARK,		PORT180_FN6),
+	PINMUX_DATA(IRQ24_MARK,			PORT180_FN0),
+
+	/* Port181 */
+	PINMUX_DATA(VIO0_D9_MARK,		PORT181_FN1),
+	PINMUX_DATA(VIO1_D1_MARK,		PORT181_FN5),
+	PINMUX_DATA(IDE_RST_MARK,		PORT181_FN6),
+
+	/* Port182 */
+	PINMUX_DATA(VIO0_D8_MARK,		PORT182_FN1),
+	PINMUX_DATA(VIO1_D0_MARK,		PORT182_FN5),
+	PINMUX_DATA(IDE_DIRECTION_MARK,		PORT182_FN6),
+
+	/* Port183 */
+	PINMUX_DATA(DREQ1_MARK,			PORT183_FN1),
+	PINMUX_DATA(BBIF2_TXD2_PORT183_MARK,	PORT183_FN2,	MSEL5CR_0_1),
+	PINMUX_DATA(ET_TX_EN_MARK,		PORT183_FN3),
+
+	/* Port184 */
+	PINMUX_DATA(DACK1_MARK,			PORT184_FN1),
+	PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK,	PORT184_FN2,	MSEL5CR_0_1),
+	PINMUX_DATA(ET_TX_CLK_MARK,		PORT184_FN3),
+
+	/* Port185 - Port192 Function1 */
+	PINMUX_DATA(SCIFA1_SCK_MARK,		PORT185_FN1),
+	PINMUX_DATA(SCIFB_RTS_PORT186_MARK,	PORT186_FN1,	MSEL5CR_17_0),
+	PINMUX_DATA(SCIFB_CTS_PORT187_MARK,	PORT187_FN1,	MSEL5CR_17_0),
+	PINMUX_DATA(SCIFA0_SCK_MARK,		PORT188_FN1),
+	PINMUX_DATA(SCIFB_SCK_PORT190_MARK,	PORT190_FN1,	MSEL5CR_17_0),
+	PINMUX_DATA(SCIFB_RXD_PORT191_MARK,	PORT191_FN1,	MSEL5CR_17_0),
+	PINMUX_DATA(SCIFB_TXD_PORT192_MARK,	PORT192_FN1,	MSEL5CR_17_0),
+
+	/* Port185 - Port192 Function3 */
+	PINMUX_DATA(ET_ERXD0_MARK,		PORT185_FN3),
+	PINMUX_DATA(ET_ERXD1_MARK,		PORT186_FN3),
+	PINMUX_DATA(ET_ERXD2_MARK,		PORT187_FN3),
+	PINMUX_DATA(ET_ERXD3_MARK,		PORT188_FN3),
+	PINMUX_DATA(ET_ERXD4_MARK,		PORT189_FN3),
+	PINMUX_DATA(ET_ERXD5_MARK,		PORT190_FN3),
+	PINMUX_DATA(ET_ERXD6_MARK,		PORT191_FN3),
+	PINMUX_DATA(ET_ERXD7_MARK,		PORT192_FN3),
+
+	/* Port185 - Port192 Function6 */
+	PINMUX_DATA(STP1_IPCLK_MARK,		PORT185_FN6),
+	PINMUX_DATA(STP1_IPD0_PORT186_MARK,	PORT186_FN6,	MSEL5CR_23_0),
+	PINMUX_DATA(STP1_IPEN_PORT187_MARK,	PORT187_FN6,	MSEL5CR_23_0),
+	PINMUX_DATA(STP1_IPSYNC_MARK,		PORT188_FN6),
+	PINMUX_DATA(STP0_IPCLK_MARK,		PORT189_FN6),
+	PINMUX_DATA(STP0_IPD0_MARK,		PORT190_FN6),
+	PINMUX_DATA(STP0_IPEN_MARK,		PORT191_FN6),
+	PINMUX_DATA(STP0_IPSYNC_MARK,		PORT192_FN6),
+
+	/* Port193 */
+	PINMUX_DATA(SCIFA0_CTS_MARK,		PORT193_FN1),
+	PINMUX_DATA(RMII_CRS_DV_MARK,		PORT193_FN3),
+	PINMUX_DATA(STP1_IPEN_PORT193_MARK,	PORT193_FN6,	MSEL5CR_23_1),
+	PINMUX_DATA(LCD1_D17_MARK,		PORT193_FN7),
+
+	/* Port194 */
+	PINMUX_DATA(SCIFA0_RTS_MARK,		PORT194_FN1),
+	PINMUX_DATA(RMII_RX_ER_MARK,		PORT194_FN3),
+	PINMUX_DATA(STP1_IPD0_PORT194_MARK,	PORT194_FN6,	MSEL5CR_23_1),
+	PINMUX_DATA(LCD1_D16_MARK,		PORT194_FN7),
+
+	/* Port195 */
+	PINMUX_DATA(SCIFA1_RXD_MARK,		PORT195_FN1),
+	PINMUX_DATA(RMII_RXD0_MARK,		PORT195_FN3),
+	PINMUX_DATA(STP1_IPD3_MARK,		PORT195_FN6),
+	PINMUX_DATA(LCD1_D15_MARK,		PORT195_FN7),
+
+	/* Port196 */
+	PINMUX_DATA(SCIFA1_TXD_MARK,		PORT196_FN1),
+	PINMUX_DATA(RMII_RXD1_MARK,		PORT196_FN3),
+	PINMUX_DATA(STP1_IPD2_MARK,		PORT196_FN6),
+	PINMUX_DATA(LCD1_D14_MARK,		PORT196_FN7),
+
+	/* Port197 */
+	PINMUX_DATA(SCIFA0_RXD_MARK,		PORT197_FN1),
+	PINMUX_DATA(VIO1_CLK_MARK,		PORT197_FN5),
+	PINMUX_DATA(STP1_IPD5_MARK,		PORT197_FN6),
+	PINMUX_DATA(LCD1_D19_MARK,		PORT197_FN7),
+
+	/* Port198 */
+	PINMUX_DATA(SCIFA0_TXD_MARK,		PORT198_FN1),
+	PINMUX_DATA(VIO1_VD_MARK,		PORT198_FN5),
+	PINMUX_DATA(STP1_IPD4_MARK,		PORT198_FN6),
+	PINMUX_DATA(LCD1_D18_MARK,		PORT198_FN7),
+
+	/* Port199 */
+	PINMUX_DATA(MEMC_NWE_MARK,		PORT199_FN1),
+	PINMUX_DATA(SCIFA2_SCK_PORT199_MARK,	PORT199_FN2,	MSEL5CR_7_1),
+	PINMUX_DATA(RMII_TX_EN_MARK,		PORT199_FN3),
+	PINMUX_DATA(SIM_D_PORT199_MARK,		PORT199_FN4,	MSEL5CR_21_1),
+	PINMUX_DATA(STP1_IPD1_MARK,		PORT199_FN6),
+	PINMUX_DATA(LCD1_D13_MARK,		PORT199_FN7),
+
+	/* Port200 */
+	PINMUX_DATA(MEMC_NOE_MARK,		PORT200_FN1),
+	PINMUX_DATA(SCIFA2_RXD_MARK,		PORT200_FN2),
+	PINMUX_DATA(RMII_TXD0_MARK,		PORT200_FN3),
+	PINMUX_DATA(STP0_IPD7_MARK,		PORT200_FN6),
+	PINMUX_DATA(LCD1_D12_MARK,		PORT200_FN7),
+
+	/* Port201 */
+	PINMUX_DATA(MEMC_WAIT_MARK,		PORT201_FN1,	MSEL4CR_6_0),
+	PINMUX_DATA(MEMC_DREQ1_MARK,		PORT201_FN1,	MSEL4CR_6_1),
+
+	PINMUX_DATA(SCIFA2_TXD_MARK,		PORT201_FN2),
+	PINMUX_DATA(RMII_TXD1_MARK,		PORT201_FN3),
+	PINMUX_DATA(STP0_IPD6_MARK,		PORT201_FN6),
+	PINMUX_DATA(LCD1_D11_MARK,		PORT201_FN7),
+
+	/* Port202 */
+	PINMUX_DATA(MEMC_BUSCLK_MARK,		PORT202_FN1,	MSEL4CR_6_0),
+	PINMUX_DATA(MEMC_A0_MARK,		PORT202_FN1,	MSEL4CR_6_1),
+
+	PINMUX_DATA(MSIOF1_SS2_PORT202_MARK,	PORT202_FN2,	MSEL4CR_10_1),
+	PINMUX_DATA(RMII_MDC_MARK,		PORT202_FN3),
+	PINMUX_DATA(TPU0TO2_PORT202_MARK,	PORT202_FN4,	MSEL5CR_25_1),
+	PINMUX_DATA(IDE_CS0_MARK,		PORT202_FN6),
+	PINMUX_DATA(SDHI2_CD_PORT202_MARK,	PORT202_FN7,	MSEL5CR_19_1),
+	PINMUX_DATA(IRQ21_MARK,			PORT202_FN0),
+
+	/* Port203 - Port208 Function1 */
+	PINMUX_DATA(SDHI2_CLK_MARK,		PORT203_FN1),
+	PINMUX_DATA(SDHI2_CMD_MARK,		PORT204_FN1),
+	PINMUX_DATA(SDHI2_D0_MARK,		PORT205_FN1),
+	PINMUX_DATA(SDHI2_D1_MARK,		PORT206_FN1),
+	PINMUX_DATA(SDHI2_D2_MARK,		PORT207_FN1),
+	PINMUX_DATA(SDHI2_D3_MARK,		PORT208_FN1),
+
+	/* Port203 - Port208 Function3 */
+	PINMUX_DATA(ET_TX_ER_MARK,		PORT203_FN3),
+	PINMUX_DATA(ET_RX_ER_MARK,		PORT204_FN3),
+	PINMUX_DATA(ET_CRS_MARK,		PORT205_FN3),
+	PINMUX_DATA(ET_MDC_MARK,		PORT206_FN3),
+	PINMUX_DATA(ET_MDIO_MARK,		PORT207_FN3),
+	PINMUX_DATA(RMII_MDIO_MARK,		PORT208_FN3),
+
+	/* Port203 - Port208 Function6 */
+	PINMUX_DATA(IDE_A2_MARK,		PORT203_FN6),
+	PINMUX_DATA(IDE_A1_MARK,		PORT204_FN6),
+	PINMUX_DATA(IDE_A0_MARK,		PORT205_FN6),
+	PINMUX_DATA(IDE_IODACK_MARK,		PORT206_FN6),
+	PINMUX_DATA(IDE_IODREQ_MARK,		PORT207_FN6),
+	PINMUX_DATA(IDE_CS1_MARK,		PORT208_FN6),
+
+	/* Port203 - Port208 Function7 */
+	PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0,
+			MSEL5CR_11_1),
+	PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0,
+			MSEL5CR_11_1),
+	PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
+	PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
+	PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0,
+			MSEL5CR_14_1),
+	PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0,
+			MSEL5CR_14_1),
+
+	/* Port209 */
+	PINMUX_DATA(VBUS_MARK, PORT209_FN1),
+	PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1),
+
+	/* Port210 */
+	PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
+
+	/* Port211 */
+	PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
+
+	/* LCDC select */
+	PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
+	PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
+
+	/* SDENC */
+	PINMUX_DATA(SDENC_CPG_MARK,	MSEL4CR_19_0),
+	PINMUX_DATA(SDENC_DV_CLKI_MARK,	MSEL4CR_19_1),
+
+	/* SYSC */
+	PINMUX_DATA(RESETP_PULLUP_MARK,	MSEL4CR_4_0),
+	PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
+
+	/* DEBUG */
+	PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
+	PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
+
+	PINMUX_DATA(TRACEAUD_FROM_VIO_MARK,	MSEL5CR_30_0, MSEL5CR_29_0),
+	PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
+	PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+
+	/* PORT */
+	GPIO_PORT_ALL(),
+
+	/* IRQ */
+	GPIO_FN(IRQ0_PORT2),	GPIO_FN(IRQ0_PORT13),
+	GPIO_FN(IRQ1),
+	GPIO_FN(IRQ2_PORT11),	GPIO_FN(IRQ2_PORT12),
+	GPIO_FN(IRQ3_PORT10),	GPIO_FN(IRQ3_PORT14),
+	GPIO_FN(IRQ4_PORT15),	GPIO_FN(IRQ4_PORT172),
+	GPIO_FN(IRQ5_PORT0),	GPIO_FN(IRQ5_PORT1),
+	GPIO_FN(IRQ6_PORT121),	GPIO_FN(IRQ6_PORT173),
+	GPIO_FN(IRQ7_PORT120),	GPIO_FN(IRQ7_PORT209),
+	GPIO_FN(IRQ8),
+	GPIO_FN(IRQ9_PORT118),	GPIO_FN(IRQ9_PORT210),
+	GPIO_FN(IRQ10),
+	GPIO_FN(IRQ11),
+	GPIO_FN(IRQ12_PORT42),	GPIO_FN(IRQ12_PORT97),
+	GPIO_FN(IRQ13_PORT64),	GPIO_FN(IRQ13_PORT98),
+	GPIO_FN(IRQ14_PORT63),	GPIO_FN(IRQ14_PORT99),
+	GPIO_FN(IRQ15_PORT62),	GPIO_FN(IRQ15_PORT100),
+	GPIO_FN(IRQ16_PORT68),	GPIO_FN(IRQ16_PORT211),
+	GPIO_FN(IRQ17),
+	GPIO_FN(IRQ18),
+	GPIO_FN(IRQ19),
+	GPIO_FN(IRQ20),
+	GPIO_FN(IRQ21),
+	GPIO_FN(IRQ22),
+	GPIO_FN(IRQ23),
+	GPIO_FN(IRQ24),
+	GPIO_FN(IRQ25),
+	GPIO_FN(IRQ26_PORT58),	GPIO_FN(IRQ26_PORT81),
+	GPIO_FN(IRQ27_PORT57),	GPIO_FN(IRQ27_PORT168),
+	GPIO_FN(IRQ28_PORT56),	GPIO_FN(IRQ28_PORT169),
+	GPIO_FN(IRQ29_PORT50),	GPIO_FN(IRQ29_PORT170),
+	GPIO_FN(IRQ30_PORT49),	GPIO_FN(IRQ30_PORT171),
+	GPIO_FN(IRQ31_PORT41),	GPIO_FN(IRQ31_PORT167),
+
+	/* Function */
+
+	/* DBGT */
+	GPIO_FN(DBGMDT2),	GPIO_FN(DBGMDT1),	GPIO_FN(DBGMDT0),
+	GPIO_FN(DBGMD10),	GPIO_FN(DBGMD11),	GPIO_FN(DBGMD20),
+	GPIO_FN(DBGMD21),
+
+	/* FSI */
+	GPIO_FN(FSIAISLD_PORT0),	/* FSIAISLD Port 0/5 */
+	GPIO_FN(FSIAISLD_PORT5),
+	GPIO_FN(FSIASPDIF_PORT9),	/* FSIASPDIF Port 9/18 */
+	GPIO_FN(FSIASPDIF_PORT18),
+	GPIO_FN(FSIAOSLD1),	GPIO_FN(FSIAOSLD2),	GPIO_FN(FSIAOLR),
+	GPIO_FN(FSIAOBT),	GPIO_FN(FSIAOSLD),	GPIO_FN(FSIAOMC),
+	GPIO_FN(FSIACK),	GPIO_FN(FSIAILR),	GPIO_FN(FSIAIBT),
+
+	/* FMSI */
+	GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
+	GPIO_FN(FMSISLD_PORT6),
+	GPIO_FN(FMSIILR),	GPIO_FN(FMSIIBT),	GPIO_FN(FMSIOLR),
+	GPIO_FN(FMSIOBT),	GPIO_FN(FMSICK),	GPIO_FN(FMSOILR),
+	GPIO_FN(FMSOIBT),	GPIO_FN(FMSOOLR),	GPIO_FN(FMSOOBT),
+	GPIO_FN(FMSOSLD),	GPIO_FN(FMSOCK),
+
+	/* SCIFA0 */
+	GPIO_FN(SCIFA0_SCK),	GPIO_FN(SCIFA0_CTS),	GPIO_FN(SCIFA0_RTS),
+	GPIO_FN(SCIFA0_RXD),	GPIO_FN(SCIFA0_TXD),
+
+	/* SCIFA1 */
+	GPIO_FN(SCIFA1_CTS),	GPIO_FN(SCIFA1_SCK),
+	GPIO_FN(SCIFA1_RXD),	GPIO_FN(SCIFA1_TXD),	GPIO_FN(SCIFA1_RTS),
+
+	/* SCIFA2 */
+	GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
+	GPIO_FN(SCIFA2_SCK_PORT199),
+	GPIO_FN(SCIFA2_RXD),	GPIO_FN(SCIFA2_TXD),
+	GPIO_FN(SCIFA2_CTS),	GPIO_FN(SCIFA2_RTS),
+
+	/* SCIFA3 */
+	GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
+	GPIO_FN(SCIFA3_SCK_PORT116),
+	GPIO_FN(SCIFA3_CTS_PORT117),
+	GPIO_FN(SCIFA3_RXD_PORT174),
+	GPIO_FN(SCIFA3_TXD_PORT175),
+
+	GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
+	GPIO_FN(SCIFA3_SCK_PORT158),
+	GPIO_FN(SCIFA3_CTS_PORT162),
+	GPIO_FN(SCIFA3_RXD_PORT159),
+	GPIO_FN(SCIFA3_TXD_PORT160),
+
+	/* SCIFA4 */
+	GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
+	GPIO_FN(SCIFA4_TXD_PORT13),
+
+	GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
+	GPIO_FN(SCIFA4_TXD_PORT203),
+
+	GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
+	GPIO_FN(SCIFA4_TXD_PORT93),
+
+	GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
+	GPIO_FN(SCIFA4_SCK_PORT205),
+
+	/* SCIFA5 */
+	GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
+	GPIO_FN(SCIFA5_RXD_PORT10),
+
+	GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
+	GPIO_FN(SCIFA5_TXD_PORT208),
+
+	GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
+	GPIO_FN(SCIFA5_RXD_PORT92),
+
+	GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
+	GPIO_FN(SCIFA5_SCK_PORT206),
+
+	/* SCIFA6 */
+	GPIO_FN(SCIFA6_SCK),	GPIO_FN(SCIFA6_RXD),	GPIO_FN(SCIFA6_TXD),
+
+	/* SCIFA7 */
+	GPIO_FN(SCIFA7_TXD),	GPIO_FN(SCIFA7_RXD),
+
+	/* SCIFAB */
+	GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
+	GPIO_FN(SCIFB_RXD_PORT191),
+	GPIO_FN(SCIFB_TXD_PORT192),
+	GPIO_FN(SCIFB_RTS_PORT186),
+	GPIO_FN(SCIFB_CTS_PORT187),
+
+	GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
+	GPIO_FN(SCIFB_RXD_PORT3),
+	GPIO_FN(SCIFB_TXD_PORT4),
+	GPIO_FN(SCIFB_RTS_PORT172),
+	GPIO_FN(SCIFB_CTS_PORT173),
+
+	/* LCD0 */
+	GPIO_FN(LCD0_D0),	GPIO_FN(LCD0_D1),	GPIO_FN(LCD0_D2),
+	GPIO_FN(LCD0_D3),	GPIO_FN(LCD0_D4),	GPIO_FN(LCD0_D5),
+	GPIO_FN(LCD0_D6),	GPIO_FN(LCD0_D7),	GPIO_FN(LCD0_D8),
+	GPIO_FN(LCD0_D9),	GPIO_FN(LCD0_D10),	GPIO_FN(LCD0_D11),
+	GPIO_FN(LCD0_D12),	GPIO_FN(LCD0_D13),	GPIO_FN(LCD0_D14),
+	GPIO_FN(LCD0_D15),	GPIO_FN(LCD0_D16),	GPIO_FN(LCD0_D17),
+	GPIO_FN(LCD0_DON),	GPIO_FN(LCD0_VCPWC),	GPIO_FN(LCD0_VEPWC),
+	GPIO_FN(LCD0_DCK),	GPIO_FN(LCD0_VSYN),
+	GPIO_FN(LCD0_HSYN),	GPIO_FN(LCD0_DISP),
+	GPIO_FN(LCD0_WR),	GPIO_FN(LCD0_RD),
+	GPIO_FN(LCD0_CS),	GPIO_FN(LCD0_RS),
+
+	GPIO_FN(LCD0_D18_PORT163),	GPIO_FN(LCD0_D19_PORT162),
+	GPIO_FN(LCD0_D20_PORT161),	GPIO_FN(LCD0_D21_PORT158),
+	GPIO_FN(LCD0_D22_PORT160),	GPIO_FN(LCD0_D23_PORT159),
+	GPIO_FN(LCD0_LCLK_PORT165),	/* MSEL5CR_6_1 */
+
+	GPIO_FN(LCD0_D18_PORT40),	GPIO_FN(LCD0_D19_PORT4),
+	GPIO_FN(LCD0_D20_PORT3),	GPIO_FN(LCD0_D21_PORT2),
+	GPIO_FN(LCD0_D22_PORT0),	GPIO_FN(LCD0_D23_PORT1),
+	GPIO_FN(LCD0_LCLK_PORT102),	/* MSEL5CR_6_0 */
+
+	/* LCD1 */
+	GPIO_FN(LCD1_D0),	GPIO_FN(LCD1_D1),	GPIO_FN(LCD1_D2),
+	GPIO_FN(LCD1_D3),	GPIO_FN(LCD1_D4),	GPIO_FN(LCD1_D5),
+	GPIO_FN(LCD1_D6),	GPIO_FN(LCD1_D7),	GPIO_FN(LCD1_D8),
+	GPIO_FN(LCD1_D9),	GPIO_FN(LCD1_D10),	GPIO_FN(LCD1_D11),
+	GPIO_FN(LCD1_D12),	GPIO_FN(LCD1_D13),	GPIO_FN(LCD1_D14),
+	GPIO_FN(LCD1_D15),	GPIO_FN(LCD1_D16),	GPIO_FN(LCD1_D17),
+	GPIO_FN(LCD1_D18),	GPIO_FN(LCD1_D19),	GPIO_FN(LCD1_D20),
+	GPIO_FN(LCD1_D21),	GPIO_FN(LCD1_D22),	GPIO_FN(LCD1_D23),
+	GPIO_FN(LCD1_RS),	GPIO_FN(LCD1_RD),	GPIO_FN(LCD1_CS),
+	GPIO_FN(LCD1_WR),	GPIO_FN(LCD1_DCK),	GPIO_FN(LCD1_DON),
+	GPIO_FN(LCD1_VCPWC),	GPIO_FN(LCD1_LCLK),	GPIO_FN(LCD1_HSYN),
+	GPIO_FN(LCD1_VSYN),	GPIO_FN(LCD1_VEPWC),	GPIO_FN(LCD1_DISP),
+
+	/* RSPI */
+	GPIO_FN(RSPI_SSL0_A),	GPIO_FN(RSPI_SSL1_A),	GPIO_FN(RSPI_SSL2_A),
+	GPIO_FN(RSPI_SSL3_A),	GPIO_FN(RSPI_CK_A),	GPIO_FN(RSPI_MOSI_A),
+	GPIO_FN(RSPI_MISO_A),
+
+	/* VIO CKO */
+	GPIO_FN(VIO_CKO1),
+	GPIO_FN(VIO_CKO2),
+	GPIO_FN(VIO_CKO_1),
+	GPIO_FN(VIO_CKO),
+
+	/* VIO0 */
+	GPIO_FN(VIO0_D0),	GPIO_FN(VIO0_D1),	GPIO_FN(VIO0_D2),
+	GPIO_FN(VIO0_D3),	GPIO_FN(VIO0_D4),	GPIO_FN(VIO0_D5),
+	GPIO_FN(VIO0_D6),	GPIO_FN(VIO0_D7),	GPIO_FN(VIO0_D8),
+	GPIO_FN(VIO0_D9),	GPIO_FN(VIO0_D10),	GPIO_FN(VIO0_D11),
+	GPIO_FN(VIO0_D12),	GPIO_FN(VIO0_VD),	GPIO_FN(VIO0_HD),
+	GPIO_FN(VIO0_CLK),	GPIO_FN(VIO0_FIELD),
+
+	GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
+	GPIO_FN(VIO0_D14_PORT25),
+	GPIO_FN(VIO0_D15_PORT24),
+
+	GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
+	GPIO_FN(VIO0_D14_PORT95),
+	GPIO_FN(VIO0_D15_PORT96),
+
+	/* VIO1 */
+	GPIO_FN(VIO1_D0),	GPIO_FN(VIO1_D1),	GPIO_FN(VIO1_D2),
+	GPIO_FN(VIO1_D3),	GPIO_FN(VIO1_D4),	GPIO_FN(VIO1_D5),
+	GPIO_FN(VIO1_D6),	GPIO_FN(VIO1_D7),	GPIO_FN(VIO1_VD),
+	GPIO_FN(VIO1_HD),	GPIO_FN(VIO1_CLK),	GPIO_FN(VIO1_FIELD),
+
+	/* TPU0 */
+	GPIO_FN(TPU0TO0),	GPIO_FN(TPU0TO1),	GPIO_FN(TPU0TO3),
+	GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
+	GPIO_FN(TPU0TO2_PORT202),
+
+	/* SSP1 0 */
+	GPIO_FN(STP0_IPD0),	GPIO_FN(STP0_IPD1),	GPIO_FN(STP0_IPD2),
+	GPIO_FN(STP0_IPD3),	GPIO_FN(STP0_IPD4),	GPIO_FN(STP0_IPD5),
+	GPIO_FN(STP0_IPD6),	GPIO_FN(STP0_IPD7),	GPIO_FN(STP0_IPEN),
+	GPIO_FN(STP0_IPCLK),	GPIO_FN(STP0_IPSYNC),
+
+	/* SSP1 1 */
+	GPIO_FN(STP1_IPD1),	GPIO_FN(STP1_IPD2),	GPIO_FN(STP1_IPD3),
+	GPIO_FN(STP1_IPD4),	GPIO_FN(STP1_IPD5),	GPIO_FN(STP1_IPD6),
+	GPIO_FN(STP1_IPD7),	GPIO_FN(STP1_IPCLK),	GPIO_FN(STP1_IPSYNC),
+
+	GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
+	GPIO_FN(STP1_IPEN_PORT187),
+
+	GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
+	GPIO_FN(STP1_IPEN_PORT193),
+
+	/* SIM */
+	GPIO_FN(SIM_RST),	GPIO_FN(SIM_CLK),
+	GPIO_FN(SIM_D_PORT22), /* SIM_D  Port 22/199 */
+	GPIO_FN(SIM_D_PORT199),
+
+	/* SDHI0 */
+	GPIO_FN(SDHI0_D0),	GPIO_FN(SDHI0_D1),	GPIO_FN(SDHI0_D2),
+	GPIO_FN(SDHI0_D3),	GPIO_FN(SDHI0_CD),	GPIO_FN(SDHI0_WP),
+	GPIO_FN(SDHI0_CMD),	GPIO_FN(SDHI0_CLK),
+
+	/* SDHI1 */
+	GPIO_FN(SDHI1_D0),	GPIO_FN(SDHI1_D1),	GPIO_FN(SDHI1_D2),
+	GPIO_FN(SDHI1_D3),	GPIO_FN(SDHI1_CD),	GPIO_FN(SDHI1_WP),
+	GPIO_FN(SDHI1_CMD),	GPIO_FN(SDHI1_CLK),
+
+	/* SDHI2 */
+	GPIO_FN(SDHI2_D0),	GPIO_FN(SDHI2_D1),	GPIO_FN(SDHI2_D2),
+	GPIO_FN(SDHI2_D3),	GPIO_FN(SDHI2_CLK),	GPIO_FN(SDHI2_CMD),
+
+	GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
+	GPIO_FN(SDHI2_WP_PORT25),
+
+	GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
+	GPIO_FN(SDHI2_CD_PORT202),
+
+	/* MSIOF2 */
+	GPIO_FN(MSIOF2_TXD),	GPIO_FN(MSIOF2_RXD),	GPIO_FN(MSIOF2_TSCK),
+	GPIO_FN(MSIOF2_SS2),	GPIO_FN(MSIOF2_TSYNC),	GPIO_FN(MSIOF2_SS1),
+	GPIO_FN(MSIOF2_MCK1),	GPIO_FN(MSIOF2_MCK0),	GPIO_FN(MSIOF2_RSYNC),
+	GPIO_FN(MSIOF2_RSCK),
+
+	/* KEYSC */
+	GPIO_FN(KEYIN4),	GPIO_FN(KEYIN5),
+	GPIO_FN(KEYIN6),	GPIO_FN(KEYIN7),
+	GPIO_FN(KEYOUT0),	GPIO_FN(KEYOUT1),	GPIO_FN(KEYOUT2),
+	GPIO_FN(KEYOUT3),	GPIO_FN(KEYOUT4),	GPIO_FN(KEYOUT5),
+	GPIO_FN(KEYOUT6),	GPIO_FN(KEYOUT7),
+
+	GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
+	GPIO_FN(KEYIN1_PORT44),
+	GPIO_FN(KEYIN2_PORT45),
+	GPIO_FN(KEYIN3_PORT46),
+
+	GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
+	GPIO_FN(KEYIN1_PORT57),
+	GPIO_FN(KEYIN2_PORT56),
+	GPIO_FN(KEYIN3_PORT55),
+
+	/* VOU */
+	GPIO_FN(DV_D0),		GPIO_FN(DV_D1),		GPIO_FN(DV_D2),
+	GPIO_FN(DV_D3),		GPIO_FN(DV_D4),		GPIO_FN(DV_D5),
+	GPIO_FN(DV_D6),		GPIO_FN(DV_D7),		GPIO_FN(DV_D8),
+	GPIO_FN(DV_D9),		GPIO_FN(DV_D10),	GPIO_FN(DV_D11),
+	GPIO_FN(DV_D12),	GPIO_FN(DV_D13),	GPIO_FN(DV_D14),
+	GPIO_FN(DV_D15),	GPIO_FN(DV_CLK),
+	GPIO_FN(DV_VSYNC),	GPIO_FN(DV_HSYNC),
+
+	/* MEMC */
+	GPIO_FN(MEMC_AD0),	GPIO_FN(MEMC_AD1),	GPIO_FN(MEMC_AD2),
+	GPIO_FN(MEMC_AD3),	GPIO_FN(MEMC_AD4),	GPIO_FN(MEMC_AD5),
+	GPIO_FN(MEMC_AD6),	GPIO_FN(MEMC_AD7),	GPIO_FN(MEMC_AD8),
+	GPIO_FN(MEMC_AD9),	GPIO_FN(MEMC_AD10),	GPIO_FN(MEMC_AD11),
+	GPIO_FN(MEMC_AD12),	GPIO_FN(MEMC_AD13),	GPIO_FN(MEMC_AD14),
+	GPIO_FN(MEMC_AD15),	GPIO_FN(MEMC_CS0),	GPIO_FN(MEMC_INT),
+	GPIO_FN(MEMC_NWE),	GPIO_FN(MEMC_NOE),	GPIO_FN(MEMC_CS1),
+	GPIO_FN(MEMC_A1),	GPIO_FN(MEMC_ADV),	GPIO_FN(MEMC_DREQ0),
+	GPIO_FN(MEMC_WAIT),	GPIO_FN(MEMC_DREQ1),	GPIO_FN(MEMC_BUSCLK),
+	GPIO_FN(MEMC_A0),
+
+	/* MMC */
+	GPIO_FN(MMC0_D0_PORT68),	GPIO_FN(MMC0_D1_PORT69),
+	GPIO_FN(MMC0_D2_PORT70),	GPIO_FN(MMC0_D3_PORT71),
+	GPIO_FN(MMC0_D4_PORT72),	GPIO_FN(MMC0_D5_PORT73),
+	GPIO_FN(MMC0_D6_PORT74),	GPIO_FN(MMC0_D7_PORT75),
+	GPIO_FN(MMC0_CLK_PORT66),
+	GPIO_FN(MMC0_CMD_PORT67),	/* MSEL4CR_15_0 */
+
+	GPIO_FN(MMC1_D0_PORT149),	GPIO_FN(MMC1_D1_PORT148),
+	GPIO_FN(MMC1_D2_PORT147),	GPIO_FN(MMC1_D3_PORT146),
+	GPIO_FN(MMC1_D4_PORT145),	GPIO_FN(MMC1_D5_PORT144),
+	GPIO_FN(MMC1_D6_PORT143),	GPIO_FN(MMC1_D7_PORT142),
+	GPIO_FN(MMC1_CLK_PORT103),
+	GPIO_FN(MMC1_CMD_PORT104),	/* MSEL4CR_15_1 */
+
+	/* MSIOF0 */
+	GPIO_FN(MSIOF0_SS1),	GPIO_FN(MSIOF0_SS2),	GPIO_FN(MSIOF0_RXD),
+	GPIO_FN(MSIOF0_TXD),	GPIO_FN(MSIOF0_MCK0),	GPIO_FN(MSIOF0_MCK1),
+	GPIO_FN(MSIOF0_RSYNC),	GPIO_FN(MSIOF0_RSCK),	GPIO_FN(MSIOF0_TSCK),
+	GPIO_FN(MSIOF0_TSYNC),
+
+	/* MSIOF1 */
+	GPIO_FN(MSIOF1_RSCK),	GPIO_FN(MSIOF1_RSYNC),
+	GPIO_FN(MSIOF1_MCK0),	GPIO_FN(MSIOF1_MCK1),
+
+	GPIO_FN(MSIOF1_SS2_PORT116),	GPIO_FN(MSIOF1_SS1_PORT117),
+	GPIO_FN(MSIOF1_RXD_PORT118),	GPIO_FN(MSIOF1_TXD_PORT119),
+	GPIO_FN(MSIOF1_TSYNC_PORT120),
+	GPIO_FN(MSIOF1_TSCK_PORT121),	/* MSEL4CR_10_0 */
+
+	GPIO_FN(MSIOF1_SS1_PORT67),	GPIO_FN(MSIOF1_TSCK_PORT72),
+	GPIO_FN(MSIOF1_TSYNC_PORT73),	GPIO_FN(MSIOF1_TXD_PORT74),
+	GPIO_FN(MSIOF1_RXD_PORT75),
+	GPIO_FN(MSIOF1_SS2_PORT202),	/* MSEL4CR_10_1 */
+
+	/* GPIO */
+	GPIO_FN(GPO0),	GPIO_FN(GPI0),
+	GPIO_FN(GPO1),	GPIO_FN(GPI1),
+
+	/* USB0 */
+	GPIO_FN(USB0_OCI),	GPIO_FN(USB0_PPON),	GPIO_FN(VBUS),
+
+	/* USB1 */
+	GPIO_FN(USB1_OCI),	GPIO_FN(USB1_PPON),
+
+	/* BBIF1 */
+	GPIO_FN(BBIF1_RXD),	GPIO_FN(BBIF1_TXD),	GPIO_FN(BBIF1_TSYNC),
+	GPIO_FN(BBIF1_TSCK),	GPIO_FN(BBIF1_RSCK),	GPIO_FN(BBIF1_RSYNC),
+	GPIO_FN(BBIF1_FLOW),	GPIO_FN(BBIF1_RX_FLOW_N),
+
+	/* BBIF2 */
+	GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
+	GPIO_FN(BBIF2_RXD2_PORT60),
+	GPIO_FN(BBIF2_TSYNC2_PORT6),
+	GPIO_FN(BBIF2_TSCK2_PORT59),
+
+	GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
+	GPIO_FN(BBIF2_TXD2_PORT183),
+	GPIO_FN(BBIF2_TSCK2_PORT89),
+	GPIO_FN(BBIF2_TSYNC2_PORT184),
+
+	/* BSC / FLCTL / PCMCIA */
+	GPIO_FN(CS0),	GPIO_FN(CS2),	GPIO_FN(CS4),
+	GPIO_FN(CS5B),	GPIO_FN(CS6A),
+	GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
+	GPIO_FN(CS5A_PORT19),
+	GPIO_FN(IOIS16), /* ? */
+
+	GPIO_FN(A0),	GPIO_FN(A1),	GPIO_FN(A2),	GPIO_FN(A3),
+	GPIO_FN(A4_FOE),	GPIO_FN(A5_FCDE),	/* share with FLCTL */
+	GPIO_FN(A6),	GPIO_FN(A7),	GPIO_FN(A8),	GPIO_FN(A9),
+	GPIO_FN(A10),	GPIO_FN(A11),	GPIO_FN(A12),	GPIO_FN(A13),
+	GPIO_FN(A14),	GPIO_FN(A15),	GPIO_FN(A16),	GPIO_FN(A17),
+	GPIO_FN(A18),	GPIO_FN(A19),	GPIO_FN(A20),	GPIO_FN(A21),
+	GPIO_FN(A22),	GPIO_FN(A23),	GPIO_FN(A24),	GPIO_FN(A25),
+	GPIO_FN(A26),
+
+	GPIO_FN(D0_NAF0),	GPIO_FN(D1_NAF1),	/* share with FLCTL */
+	GPIO_FN(D2_NAF2),	GPIO_FN(D3_NAF3),	/* share with FLCTL */
+	GPIO_FN(D4_NAF4),	GPIO_FN(D5_NAF5),	/* share with FLCTL */
+	GPIO_FN(D6_NAF6),	GPIO_FN(D7_NAF7),	/* share with FLCTL */
+	GPIO_FN(D8_NAF8),	GPIO_FN(D9_NAF9),	/* share with FLCTL */
+	GPIO_FN(D10_NAF10),	GPIO_FN(D11_NAF11),	/* share with FLCTL */
+	GPIO_FN(D12_NAF12),	GPIO_FN(D13_NAF13),	/* share with FLCTL */
+	GPIO_FN(D14_NAF14),	GPIO_FN(D15_NAF15),	/* share with FLCTL */
+	GPIO_FN(D16),	GPIO_FN(D17),	GPIO_FN(D18),	GPIO_FN(D19),
+	GPIO_FN(D20),	GPIO_FN(D21),	GPIO_FN(D22),	GPIO_FN(D23),
+	GPIO_FN(D24),	GPIO_FN(D25),	GPIO_FN(D26),	GPIO_FN(D27),
+	GPIO_FN(D28),	GPIO_FN(D29),	GPIO_FN(D30),	GPIO_FN(D31),
+
+	GPIO_FN(WE0_FWE),	/* share with FLCTL */
+	GPIO_FN(WE1),
+	GPIO_FN(WE2_ICIORD),	/* share with PCMCIA */
+	GPIO_FN(WE3_ICIOWR),	/* share with PCMCIA */
+	GPIO_FN(CKO),	GPIO_FN(BS),	GPIO_FN(RDWR),
+	GPIO_FN(RD_FSC),	/* share with FLCTL */
+	GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
+	GPIO_FN(WAIT_PORT90),
+
+	GPIO_FN(FCE0),	GPIO_FN(FCE1),	GPIO_FN(FRB), /* FLCTL */
+
+	/* IRDA */
+	GPIO_FN(IRDA_FIRSEL),	GPIO_FN(IRDA_IN),	GPIO_FN(IRDA_OUT),
+
+	/* ATAPI */
+	GPIO_FN(IDE_D0),	GPIO_FN(IDE_D1),	GPIO_FN(IDE_D2),
+	GPIO_FN(IDE_D3),	GPIO_FN(IDE_D4),	GPIO_FN(IDE_D5),
+	GPIO_FN(IDE_D6),	GPIO_FN(IDE_D7),	GPIO_FN(IDE_D8),
+	GPIO_FN(IDE_D9),	GPIO_FN(IDE_D10),	GPIO_FN(IDE_D11),
+	GPIO_FN(IDE_D12),	GPIO_FN(IDE_D13),	GPIO_FN(IDE_D14),
+	GPIO_FN(IDE_D15),	GPIO_FN(IDE_A0),	GPIO_FN(IDE_A1),
+	GPIO_FN(IDE_A2),	GPIO_FN(IDE_CS0),	GPIO_FN(IDE_CS1),
+	GPIO_FN(IDE_IOWR),	GPIO_FN(IDE_IORD),	GPIO_FN(IDE_IORDY),
+	GPIO_FN(IDE_INT),	GPIO_FN(IDE_RST),	GPIO_FN(IDE_DIRECTION),
+	GPIO_FN(IDE_EXBUF_ENB),	GPIO_FN(IDE_IODACK),	GPIO_FN(IDE_IODREQ),
+
+	/* RMII */
+	GPIO_FN(RMII_CRS_DV),	GPIO_FN(RMII_RX_ER),	GPIO_FN(RMII_RXD0),
+	GPIO_FN(RMII_RXD1),	GPIO_FN(RMII_TX_EN),	GPIO_FN(RMII_TXD0),
+	GPIO_FN(RMII_MDC),	GPIO_FN(RMII_TXD1),	GPIO_FN(RMII_MDIO),
+	GPIO_FN(RMII_REF50CK),	GPIO_FN(RMII_REF125CK),	/* for GMII */
+
+	/* GEther */
+	GPIO_FN(ET_TX_CLK),	GPIO_FN(ET_TX_EN),	GPIO_FN(ET_ETXD0),
+	GPIO_FN(ET_ETXD1),	GPIO_FN(ET_ETXD2),	GPIO_FN(ET_ETXD3),
+	GPIO_FN(ET_ETXD4),	GPIO_FN(ET_ETXD5), /* for GEther */
+	GPIO_FN(ET_ETXD6),	GPIO_FN(ET_ETXD7), /* for GEther */
+	GPIO_FN(ET_COL),	GPIO_FN(ET_TX_ER),	GPIO_FN(ET_RX_CLK),
+	GPIO_FN(ET_RX_DV),	GPIO_FN(ET_ERXD0),	GPIO_FN(ET_ERXD1),
+	GPIO_FN(ET_ERXD2),	GPIO_FN(ET_ERXD3),
+	GPIO_FN(ET_ERXD4),	GPIO_FN(ET_ERXD5), /* for GEther */
+	GPIO_FN(ET_ERXD6),	GPIO_FN(ET_ERXD7), /* for GEther */
+	GPIO_FN(ET_RX_ER),	GPIO_FN(ET_CRS),	GPIO_FN(ET_MDC),
+	GPIO_FN(ET_MDIO),	GPIO_FN(ET_LINK),	GPIO_FN(ET_PHY_INT),
+	GPIO_FN(ET_WOL),	GPIO_FN(ET_GTX_CLK),
+
+	/* DMA0 */
+	GPIO_FN(DREQ0),	GPIO_FN(DACK0),
+
+	/* DMA1 */
+	GPIO_FN(DREQ1),	GPIO_FN(DACK1),
+
+	/* SYSC */
+	GPIO_FN(RESETOUTS),
+
+	/* IRREM */
+	GPIO_FN(IROUT),
+
+	/* LCDC */
+	GPIO_FN(LCDC0_SELECT),
+	GPIO_FN(LCDC1_SELECT),
+
+	/* SDENC */
+	GPIO_FN(SDENC_CPG),
+	GPIO_FN(SDENC_DV_CLKI),
+
+	/* SYSC */
+	GPIO_FN(RESETP_PULLUP),
+	GPIO_FN(RESETP_PLAIN),
+
+	/* DEBUG */
+	GPIO_FN(EDEBGREQ_PULLDOWN),
+	GPIO_FN(EDEBGREQ_PULLUP),
+
+	GPIO_FN(TRACEAUD_FROM_VIO),
+	GPIO_FN(TRACEAUD_FROM_LCDC0),
+	GPIO_FN(TRACEAUD_FROM_MEMC),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	PORTCR(0,	0xe6050000), /* PORT0CR */
+	PORTCR(1,	0xe6050001), /* PORT1CR */
+	PORTCR(2,	0xe6050002), /* PORT2CR */
+	PORTCR(3,	0xe6050003), /* PORT3CR */
+	PORTCR(4,	0xe6050004), /* PORT4CR */
+	PORTCR(5,	0xe6050005), /* PORT5CR */
+	PORTCR(6,	0xe6050006), /* PORT6CR */
+	PORTCR(7,	0xe6050007), /* PORT7CR */
+	PORTCR(8,	0xe6050008), /* PORT8CR */
+	PORTCR(9,	0xe6050009), /* PORT9CR */
+	PORTCR(10,	0xe605000a), /* PORT10CR */
+	PORTCR(11,	0xe605000b), /* PORT11CR */
+	PORTCR(12,	0xe605000c), /* PORT12CR */
+	PORTCR(13,	0xe605000d), /* PORT13CR */
+	PORTCR(14,	0xe605000e), /* PORT14CR */
+	PORTCR(15,	0xe605000f), /* PORT15CR */
+	PORTCR(16,	0xe6050010), /* PORT16CR */
+	PORTCR(17,	0xe6050011), /* PORT17CR */
+	PORTCR(18,	0xe6050012), /* PORT18CR */
+	PORTCR(19,	0xe6050013), /* PORT19CR */
+	PORTCR(20,	0xe6050014), /* PORT20CR */
+	PORTCR(21,	0xe6050015), /* PORT21CR */
+	PORTCR(22,	0xe6050016), /* PORT22CR */
+	PORTCR(23,	0xe6050017), /* PORT23CR */
+	PORTCR(24,	0xe6050018), /* PORT24CR */
+	PORTCR(25,	0xe6050019), /* PORT25CR */
+	PORTCR(26,	0xe605001a), /* PORT26CR */
+	PORTCR(27,	0xe605001b), /* PORT27CR */
+	PORTCR(28,	0xe605001c), /* PORT28CR */
+	PORTCR(29,	0xe605001d), /* PORT29CR */
+	PORTCR(30,	0xe605001e), /* PORT30CR */
+	PORTCR(31,	0xe605001f), /* PORT31CR */
+	PORTCR(32,	0xe6050020), /* PORT32CR */
+	PORTCR(33,	0xe6050021), /* PORT33CR */
+	PORTCR(34,	0xe6050022), /* PORT34CR */
+	PORTCR(35,	0xe6050023), /* PORT35CR */
+	PORTCR(36,	0xe6050024), /* PORT36CR */
+	PORTCR(37,	0xe6050025), /* PORT37CR */
+	PORTCR(38,	0xe6050026), /* PORT38CR */
+	PORTCR(39,	0xe6050027), /* PORT39CR */
+	PORTCR(40,	0xe6050028), /* PORT40CR */
+	PORTCR(41,	0xe6050029), /* PORT41CR */
+	PORTCR(42,	0xe605002a), /* PORT42CR */
+	PORTCR(43,	0xe605002b), /* PORT43CR */
+	PORTCR(44,	0xe605002c), /* PORT44CR */
+	PORTCR(45,	0xe605002d), /* PORT45CR */
+	PORTCR(46,	0xe605002e), /* PORT46CR */
+	PORTCR(47,	0xe605002f), /* PORT47CR */
+	PORTCR(48,	0xe6050030), /* PORT48CR */
+	PORTCR(49,	0xe6050031), /* PORT49CR */
+	PORTCR(50,	0xe6050032), /* PORT50CR */
+	PORTCR(51,	0xe6050033), /* PORT51CR */
+	PORTCR(52,	0xe6050034), /* PORT52CR */
+	PORTCR(53,	0xe6050035), /* PORT53CR */
+	PORTCR(54,	0xe6050036), /* PORT54CR */
+	PORTCR(55,	0xe6050037), /* PORT55CR */
+	PORTCR(56,	0xe6050038), /* PORT56CR */
+	PORTCR(57,	0xe6050039), /* PORT57CR */
+	PORTCR(58,	0xe605003a), /* PORT58CR */
+	PORTCR(59,	0xe605003b), /* PORT59CR */
+	PORTCR(60,	0xe605003c), /* PORT60CR */
+	PORTCR(61,	0xe605003d), /* PORT61CR */
+	PORTCR(62,	0xe605003e), /* PORT62CR */
+	PORTCR(63,	0xe605003f), /* PORT63CR */
+	PORTCR(64,	0xe6050040), /* PORT64CR */
+	PORTCR(65,	0xe6050041), /* PORT65CR */
+	PORTCR(66,	0xe6050042), /* PORT66CR */
+	PORTCR(67,	0xe6050043), /* PORT67CR */
+	PORTCR(68,	0xe6050044), /* PORT68CR */
+	PORTCR(69,	0xe6050045), /* PORT69CR */
+	PORTCR(70,	0xe6050046), /* PORT70CR */
+	PORTCR(71,	0xe6050047), /* PORT71CR */
+	PORTCR(72,	0xe6050048), /* PORT72CR */
+	PORTCR(73,	0xe6050049), /* PORT73CR */
+	PORTCR(74,	0xe605004a), /* PORT74CR */
+	PORTCR(75,	0xe605004b), /* PORT75CR */
+	PORTCR(76,	0xe605004c), /* PORT76CR */
+	PORTCR(77,	0xe605004d), /* PORT77CR */
+	PORTCR(78,	0xe605004e), /* PORT78CR */
+	PORTCR(79,	0xe605004f), /* PORT79CR */
+	PORTCR(80,	0xe6050050), /* PORT80CR */
+	PORTCR(81,	0xe6050051), /* PORT81CR */
+	PORTCR(82,	0xe6050052), /* PORT82CR */
+	PORTCR(83,	0xe6050053), /* PORT83CR */
+
+	PORTCR(84,	0xe6051054), /* PORT84CR */
+	PORTCR(85,	0xe6051055), /* PORT85CR */
+	PORTCR(86,	0xe6051056), /* PORT86CR */
+	PORTCR(87,	0xe6051057), /* PORT87CR */
+	PORTCR(88,	0xe6051058), /* PORT88CR */
+	PORTCR(89,	0xe6051059), /* PORT89CR */
+	PORTCR(90,	0xe605105a), /* PORT90CR */
+	PORTCR(91,	0xe605105b), /* PORT91CR */
+	PORTCR(92,	0xe605105c), /* PORT92CR */
+	PORTCR(93,	0xe605105d), /* PORT93CR */
+	PORTCR(94,	0xe605105e), /* PORT94CR */
+	PORTCR(95,	0xe605105f), /* PORT95CR */
+	PORTCR(96,	0xe6051060), /* PORT96CR */
+	PORTCR(97,	0xe6051061), /* PORT97CR */
+	PORTCR(98,	0xe6051062), /* PORT98CR */
+	PORTCR(99,	0xe6051063), /* PORT99CR */
+	PORTCR(100,	0xe6051064), /* PORT100CR */
+	PORTCR(101,	0xe6051065), /* PORT101CR */
+	PORTCR(102,	0xe6051066), /* PORT102CR */
+	PORTCR(103,	0xe6051067), /* PORT103CR */
+	PORTCR(104,	0xe6051068), /* PORT104CR */
+	PORTCR(105,	0xe6051069), /* PORT105CR */
+	PORTCR(106,	0xe605106a), /* PORT106CR */
+	PORTCR(107,	0xe605106b), /* PORT107CR */
+	PORTCR(108,	0xe605106c), /* PORT108CR */
+	PORTCR(109,	0xe605106d), /* PORT109CR */
+	PORTCR(110,	0xe605106e), /* PORT110CR */
+	PORTCR(111,	0xe605106f), /* PORT111CR */
+	PORTCR(112,	0xe6051070), /* PORT112CR */
+	PORTCR(113,	0xe6051071), /* PORT113CR */
+	PORTCR(114,	0xe6051072), /* PORT114CR */
+
+	PORTCR(115,	0xe6052073), /* PORT115CR */
+	PORTCR(116,	0xe6052074), /* PORT116CR */
+	PORTCR(117,	0xe6052075), /* PORT117CR */
+	PORTCR(118,	0xe6052076), /* PORT118CR */
+	PORTCR(119,	0xe6052077), /* PORT119CR */
+	PORTCR(120,	0xe6052078), /* PORT120CR */
+	PORTCR(121,	0xe6052079), /* PORT121CR */
+	PORTCR(122,	0xe605207a), /* PORT122CR */
+	PORTCR(123,	0xe605207b), /* PORT123CR */
+	PORTCR(124,	0xe605207c), /* PORT124CR */
+	PORTCR(125,	0xe605207d), /* PORT125CR */
+	PORTCR(126,	0xe605207e), /* PORT126CR */
+	PORTCR(127,	0xe605207f), /* PORT127CR */
+	PORTCR(128,	0xe6052080), /* PORT128CR */
+	PORTCR(129,	0xe6052081), /* PORT129CR */
+	PORTCR(130,	0xe6052082), /* PORT130CR */
+	PORTCR(131,	0xe6052083), /* PORT131CR */
+	PORTCR(132,	0xe6052084), /* PORT132CR */
+	PORTCR(133,	0xe6052085), /* PORT133CR */
+	PORTCR(134,	0xe6052086), /* PORT134CR */
+	PORTCR(135,	0xe6052087), /* PORT135CR */
+	PORTCR(136,	0xe6052088), /* PORT136CR */
+	PORTCR(137,	0xe6052089), /* PORT137CR */
+	PORTCR(138,	0xe605208a), /* PORT138CR */
+	PORTCR(139,	0xe605208b), /* PORT139CR */
+	PORTCR(140,	0xe605208c), /* PORT140CR */
+	PORTCR(141,	0xe605208d), /* PORT141CR */
+	PORTCR(142,	0xe605208e), /* PORT142CR */
+	PORTCR(143,	0xe605208f), /* PORT143CR */
+	PORTCR(144,	0xe6052090), /* PORT144CR */
+	PORTCR(145,	0xe6052091), /* PORT145CR */
+	PORTCR(146,	0xe6052092), /* PORT146CR */
+	PORTCR(147,	0xe6052093), /* PORT147CR */
+	PORTCR(148,	0xe6052094), /* PORT148CR */
+	PORTCR(149,	0xe6052095), /* PORT149CR */
+	PORTCR(150,	0xe6052096), /* PORT150CR */
+	PORTCR(151,	0xe6052097), /* PORT151CR */
+	PORTCR(152,	0xe6052098), /* PORT152CR */
+	PORTCR(153,	0xe6052099), /* PORT153CR */
+	PORTCR(154,	0xe605209a), /* PORT154CR */
+	PORTCR(155,	0xe605209b), /* PORT155CR */
+	PORTCR(156,	0xe605209c), /* PORT156CR */
+	PORTCR(157,	0xe605209d), /* PORT157CR */
+	PORTCR(158,	0xe605209e), /* PORT158CR */
+	PORTCR(159,	0xe605209f), /* PORT159CR */
+	PORTCR(160,	0xe60520a0), /* PORT160CR */
+	PORTCR(161,	0xe60520a1), /* PORT161CR */
+	PORTCR(162,	0xe60520a2), /* PORT162CR */
+	PORTCR(163,	0xe60520a3), /* PORT163CR */
+	PORTCR(164,	0xe60520a4), /* PORT164CR */
+	PORTCR(165,	0xe60520a5), /* PORT165CR */
+	PORTCR(166,	0xe60520a6), /* PORT166CR */
+	PORTCR(167,	0xe60520a7), /* PORT167CR */
+	PORTCR(168,	0xe60520a8), /* PORT168CR */
+	PORTCR(169,	0xe60520a9), /* PORT169CR */
+	PORTCR(170,	0xe60520aa), /* PORT170CR */
+	PORTCR(171,	0xe60520ab), /* PORT171CR */
+	PORTCR(172,	0xe60520ac), /* PORT172CR */
+	PORTCR(173,	0xe60520ad), /* PORT173CR */
+	PORTCR(174,	0xe60520ae), /* PORT174CR */
+	PORTCR(175,	0xe60520af), /* PORT175CR */
+	PORTCR(176,	0xe60520b0), /* PORT176CR */
+	PORTCR(177,	0xe60520b1), /* PORT177CR */
+	PORTCR(178,	0xe60520b2), /* PORT178CR */
+	PORTCR(179,	0xe60520b3), /* PORT179CR */
+	PORTCR(180,	0xe60520b4), /* PORT180CR */
+	PORTCR(181,	0xe60520b5), /* PORT181CR */
+	PORTCR(182,	0xe60520b6), /* PORT182CR */
+	PORTCR(183,	0xe60520b7), /* PORT183CR */
+	PORTCR(184,	0xe60520b8), /* PORT184CR */
+	PORTCR(185,	0xe60520b9), /* PORT185CR */
+	PORTCR(186,	0xe60520ba), /* PORT186CR */
+	PORTCR(187,	0xe60520bb), /* PORT187CR */
+	PORTCR(188,	0xe60520bc), /* PORT188CR */
+	PORTCR(189,	0xe60520bd), /* PORT189CR */
+	PORTCR(190,	0xe60520be), /* PORT190CR */
+	PORTCR(191,	0xe60520bf), /* PORT191CR */
+	PORTCR(192,	0xe60520c0), /* PORT192CR */
+	PORTCR(193,	0xe60520c1), /* PORT193CR */
+	PORTCR(194,	0xe60520c2), /* PORT194CR */
+	PORTCR(195,	0xe60520c3), /* PORT195CR */
+	PORTCR(196,	0xe60520c4), /* PORT196CR */
+	PORTCR(197,	0xe60520c5), /* PORT197CR */
+	PORTCR(198,	0xe60520c6), /* PORT198CR */
+	PORTCR(199,	0xe60520c7), /* PORT199CR */
+	PORTCR(200,	0xe60520c8), /* PORT200CR */
+	PORTCR(201,	0xe60520c9), /* PORT201CR */
+	PORTCR(202,	0xe60520ca), /* PORT202CR */
+	PORTCR(203,	0xe60520cb), /* PORT203CR */
+	PORTCR(204,	0xe60520cc), /* PORT204CR */
+	PORTCR(205,	0xe60520cd), /* PORT205CR */
+	PORTCR(206,	0xe60520ce), /* PORT206CR */
+	PORTCR(207,	0xe60520cf), /* PORT207CR */
+	PORTCR(208,	0xe60520d0), /* PORT208CR */
+	PORTCR(209,	0xe60520d1), /* PORT209CR */
+
+	PORTCR(210,	0xe60530d2), /* PORT210CR */
+	PORTCR(211,	0xe60530d3), /* PORT211CR */
+
+	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
+			MSEL1CR_31_0,	MSEL1CR_31_1,
+			MSEL1CR_30_0,	MSEL1CR_30_1,
+			MSEL1CR_29_0,	MSEL1CR_29_1,
+			MSEL1CR_28_0,	MSEL1CR_28_1,
+			MSEL1CR_27_0,	MSEL1CR_27_1,
+			MSEL1CR_26_0,	MSEL1CR_26_1,
+			0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			0, 0, 0, 0, 0, 0, 0, 0,
+			MSEL1CR_16_0,	MSEL1CR_16_1,
+			MSEL1CR_15_0,	MSEL1CR_15_1,
+			MSEL1CR_14_0,	MSEL1CR_14_1,
+			MSEL1CR_13_0,	MSEL1CR_13_1,
+			MSEL1CR_12_0,	MSEL1CR_12_1,
+			0, 0, 0, 0,
+			MSEL1CR_9_0,	MSEL1CR_9_1,
+			0, 0,
+			MSEL1CR_7_0,	MSEL1CR_7_1,
+			MSEL1CR_6_0,	MSEL1CR_6_1,
+			MSEL1CR_5_0,	MSEL1CR_5_1,
+			MSEL1CR_4_0,	MSEL1CR_4_1,
+			MSEL1CR_3_0,	MSEL1CR_3_1,
+			MSEL1CR_2_0,	MSEL1CR_2_1,
+			0, 0,
+			MSEL1CR_0_0,	MSEL1CR_0_1,
+		}
+	},
+	{ PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
+			0, 0, 0, 0, 0, 0, 0, 0,
+			0, 0, 0, 0, 0, 0, 0, 0,
+			0, 0, 0, 0, 0, 0, 0, 0,
+			0, 0, 0, 0, 0, 0, 0, 0,
+			MSEL3CR_15_0,	MSEL3CR_15_1,
+			0, 0, 0, 0, 0, 0, 0, 0,
+			0, 0, 0, 0, 0, 0, 0, 0,
+			MSEL3CR_6_0,	MSEL3CR_6_1,
+			0, 0, 0, 0, 0, 0, 0, 0,
+			0, 0, 0, 0,
+			}
+	},
+	{ PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
+			0, 0, 0, 0, 0, 0, 0, 0,
+			0, 0, 0, 0, 0, 0, 0, 0,
+			0, 0, 0, 0, 0, 0, 0, 0,
+			MSEL4CR_19_0,	MSEL4CR_19_1,
+			MSEL4CR_18_0,	MSEL4CR_18_1,
+			0, 0, 0, 0,
+			MSEL4CR_15_0,	MSEL4CR_15_1,
+			0, 0, 0, 0, 0, 0, 0, 0,
+			MSEL4CR_10_0,	MSEL4CR_10_1,
+			0, 0, 0, 0, 0, 0,
+			MSEL4CR_6_0,	MSEL4CR_6_1,
+			0, 0,
+			MSEL4CR_4_0,	MSEL4CR_4_1,
+			0, 0, 0, 0,
+			MSEL4CR_1_0,	MSEL4CR_1_1,
+			0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
+			MSEL5CR_31_0,	MSEL5CR_31_1,
+			MSEL5CR_30_0,	MSEL5CR_30_1,
+			MSEL5CR_29_0,	MSEL5CR_29_1,
+			0, 0,
+			MSEL5CR_27_0,	MSEL5CR_27_1,
+			0, 0,
+			MSEL5CR_25_0,	MSEL5CR_25_1,
+			0, 0,
+			MSEL5CR_23_0,	MSEL5CR_23_1,
+			0, 0,
+			MSEL5CR_21_0,	MSEL5CR_21_1,
+			0, 0,
+			MSEL5CR_19_0,	MSEL5CR_19_1,
+			0, 0,
+			MSEL5CR_17_0,	MSEL5CR_17_1,
+			0, 0,
+			MSEL5CR_15_0,	MSEL5CR_15_1,
+			MSEL5CR_14_0,	MSEL5CR_14_1,
+			MSEL5CR_13_0,	MSEL5CR_13_1,
+			MSEL5CR_12_0,	MSEL5CR_12_1,
+			MSEL5CR_11_0,	MSEL5CR_11_1,
+			MSEL5CR_10_0,	MSEL5CR_10_1,
+			0, 0,
+			MSEL5CR_8_0,	MSEL5CR_8_1,
+			MSEL5CR_7_0,	MSEL5CR_7_1,
+			MSEL5CR_6_0,	MSEL5CR_6_1,
+			MSEL5CR_5_0,	MSEL5CR_5_1,
+			MSEL5CR_4_0,	MSEL5CR_4_1,
+			MSEL5CR_3_0,	MSEL5CR_3_1,
+			MSEL5CR_2_0,	MSEL5CR_2_1,
+			0, 0,
+			MSEL5CR_0_0,	MSEL5CR_0_1,
+		}
+	},
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
+		PORT31_DATA,	PORT30_DATA,	PORT29_DATA,	PORT28_DATA,
+		PORT27_DATA,	PORT26_DATA,	PORT25_DATA,	PORT24_DATA,
+		PORT23_DATA,	PORT22_DATA,	PORT21_DATA,	PORT20_DATA,
+		PORT19_DATA,	PORT18_DATA,	PORT17_DATA,	PORT16_DATA,
+		PORT15_DATA,	PORT14_DATA,	PORT13_DATA,	PORT12_DATA,
+		PORT11_DATA,	PORT10_DATA,	PORT9_DATA,	PORT8_DATA,
+		PORT7_DATA,	PORT6_DATA,	PORT5_DATA,	PORT4_DATA,
+		PORT3_DATA,	PORT2_DATA,	PORT1_DATA,	PORT0_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
+		PORT63_DATA,	PORT62_DATA,	PORT61_DATA,	PORT60_DATA,
+		PORT59_DATA,	PORT58_DATA,	PORT57_DATA,	PORT56_DATA,
+		PORT55_DATA,	PORT54_DATA,	PORT53_DATA,	PORT52_DATA,
+		PORT51_DATA,	PORT50_DATA,	PORT49_DATA,	PORT48_DATA,
+		PORT47_DATA,	PORT46_DATA,	PORT45_DATA,	PORT44_DATA,
+		PORT43_DATA,	PORT42_DATA,	PORT41_DATA,	PORT40_DATA,
+		PORT39_DATA,	PORT38_DATA,	PORT37_DATA,	PORT36_DATA,
+		PORT35_DATA,	PORT34_DATA,	PORT33_DATA,	PORT32_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		PORT83_DATA,	PORT82_DATA,	PORT81_DATA,	PORT80_DATA,
+		PORT79_DATA,	PORT78_DATA,	PORT77_DATA,	PORT76_DATA,
+		PORT75_DATA,	PORT74_DATA,	PORT73_DATA,	PORT72_DATA,
+		PORT71_DATA,	PORT70_DATA,	PORT69_DATA,	PORT68_DATA,
+		PORT67_DATA,	PORT66_DATA,	PORT65_DATA,	PORT64_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
+		PORT95_DATA,	PORT94_DATA,	PORT93_DATA,	PORT92_DATA,
+		PORT91_DATA,	PORT90_DATA,	PORT89_DATA,	PORT88_DATA,
+		PORT87_DATA,	PORT86_DATA,	PORT85_DATA,	PORT84_DATA,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0 }
+	},
+	{ PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0,		PORT114_DATA,	PORT113_DATA,	PORT112_DATA,
+		PORT111_DATA,	PORT110_DATA,	PORT109_DATA,	PORT108_DATA,
+		PORT107_DATA,	PORT106_DATA,	PORT105_DATA,	PORT104_DATA,
+		PORT103_DATA,	PORT102_DATA,	PORT101_DATA,	PORT100_DATA,
+		PORT99_DATA,	PORT98_DATA,	PORT97_DATA,	PORT96_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
+		PORT127_DATA,	PORT126_DATA,	PORT125_DATA,	PORT124_DATA,
+		PORT123_DATA,	PORT122_DATA,	PORT121_DATA,	PORT120_DATA,
+		PORT119_DATA,	PORT118_DATA,	PORT117_DATA,	PORT116_DATA,
+		PORT115_DATA,	0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0 }
+	},
+	{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
+		PORT159_DATA,	PORT158_DATA,	PORT157_DATA,	PORT156_DATA,
+		PORT155_DATA,	PORT154_DATA,	PORT153_DATA,	PORT152_DATA,
+		PORT151_DATA,	PORT150_DATA,	PORT149_DATA,	PORT148_DATA,
+		PORT147_DATA,	PORT146_DATA,	PORT145_DATA,	PORT144_DATA,
+		PORT143_DATA,	PORT142_DATA,	PORT141_DATA,	PORT140_DATA,
+		PORT139_DATA,	PORT138_DATA,	PORT137_DATA,	PORT136_DATA,
+		PORT135_DATA,	PORT134_DATA,	PORT133_DATA,	PORT132_DATA,
+		PORT131_DATA,	PORT130_DATA,	PORT129_DATA,	PORT128_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
+		PORT191_DATA,	PORT190_DATA,	PORT189_DATA,	PORT188_DATA,
+		PORT187_DATA,	PORT186_DATA,	PORT185_DATA,	PORT184_DATA,
+		PORT183_DATA,	PORT182_DATA,	PORT181_DATA,	PORT180_DATA,
+		PORT179_DATA,	PORT178_DATA,	PORT177_DATA,	PORT176_DATA,
+		PORT175_DATA,	PORT174_DATA,	PORT173_DATA,	PORT172_DATA,
+		PORT171_DATA,	PORT170_DATA,	PORT169_DATA,	PORT168_DATA,
+		PORT167_DATA,	PORT166_DATA,	PORT165_DATA,	PORT164_DATA,
+		PORT163_DATA,	PORT162_DATA,	PORT161_DATA,	PORT160_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0,				PORT209_DATA,	PORT208_DATA,
+		PORT207_DATA,	PORT206_DATA,	PORT205_DATA,	PORT204_DATA,
+		PORT203_DATA,	PORT202_DATA,	PORT201_DATA,	PORT200_DATA,
+		PORT199_DATA,	PORT198_DATA,	PORT197_DATA,	PORT196_DATA,
+		PORT195_DATA,	PORT194_DATA,	PORT193_DATA,	PORT192_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		PORT211_DATA,	PORT210_DATA, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0 }
+	},
+	{ },
+};
+
+static struct pinmux_irq pinmux_irqs[] = {
+	PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0,	 PORT13_FN0),	/* IRQ0A */
+	PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0),		/* IRQ1A */
+	PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0,	 PORT12_FN0),	/* IRQ2A */
+	PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0,	 PORT14_FN0),	/* IRQ3A */
+	PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0,	 PORT172_FN0),	/* IRQ4A */
+	PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0,	 PORT1_FN0),	/* IRQ5A */
+	PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0),	/* IRQ6A */
+	PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0),	/* IRQ7A */
+	PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0),		/* IRQ8A */
+	PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0),	/* IRQ9A */
+	PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0),		/* IRQ10A */
+	PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0),		/* IRQ11A */
+	PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0,	 PORT97_FN0),	/* IRQ12A */
+	PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0,	 PORT98_FN0),	/* IRQ13A */
+	PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0,	 PORT99_FN0),	/* IRQ14A */
+	PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0,	 PORT100_FN0),	/* IRQ15A */
+	PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0,	 PORT211_FN0),	/* IRQ16A */
+	PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0),		/* IRQ17A */
+	PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0),		/* IRQ18A */
+	PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0),		/* IRQ19A */
+	PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0),		/* IRQ20A */
+	PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0),		/* IRQ21A */
+	PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0),		/* IRQ22A */
+	PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0),		/* IRQ23A */
+	PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0),		/* IRQ24A */
+	PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0),		/* IRQ25A */
+	PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0,	 PORT81_FN0),	/* IRQ26A */
+	PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0,	 PORT168_FN0),	/* IRQ27A */
+	PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0,	 PORT169_FN0),	/* IRQ28A */
+	PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0,	 PORT170_FN0),	/* IRQ29A */
+	PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0,	 PORT171_FN0),	/* IRQ30A */
+	PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0,	 PORT167_FN0),	/* IRQ31A */
+};
+
+static struct pinmux_info r8a7740_pinmux_info = {
+	.name		= "r8a7740_pfc",
+	.reserved_id	= PINMUX_RESERVED,
+	.data		= { PINMUX_DATA_BEGIN,
+			    PINMUX_DATA_END },
+	.input		= { PINMUX_INPUT_BEGIN,
+			    PINMUX_INPUT_END },
+	.input_pu	= { PINMUX_INPUT_PULLUP_BEGIN,
+			    PINMUX_INPUT_PULLUP_END },
+	.input_pd	= { PINMUX_INPUT_PULLDOWN_BEGIN,
+			    PINMUX_INPUT_PULLDOWN_END },
+	.output		= { PINMUX_OUTPUT_BEGIN,
+			    PINMUX_OUTPUT_END },
+	.mark		= { PINMUX_MARK_BEGIN,
+			    PINMUX_MARK_END },
+	.function	= { PINMUX_FUNCTION_BEGIN,
+			    PINMUX_FUNCTION_END },
+
+	.first_gpio	= GPIO_PORT0,
+	.last_gpio	= GPIO_FN_TRACEAUD_FROM_MEMC,
+
+	.gpios		= pinmux_gpios,
+	.cfg_regs	= pinmux_config_regs,
+	.data_regs	= pinmux_data_regs,
+
+	.gpio_data	= pinmux_data,
+	.gpio_data_size	= ARRAY_SIZE(pinmux_data),
+
+	.gpio_irq	= pinmux_irqs,
+	.gpio_irq_size	= ARRAY_SIZE(pinmux_irqs),
+};
+
+void r8a7740_pinmux_init(void)
+{
+	register_pinmux(&r8a7740_pinmux_info);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
new file mode 100644
index 000000000..1259062a6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
@@ -0,0 +1,829 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
+ *     This file is r8a7790 processor support - PFC hardware block.
+ *
+ * Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Magnus Damm
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include "pfc-r8a7790.h"
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
+	FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
+	FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
+	FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
+	FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
+	FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
+	FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
+	FN_IP3_14_12, FN_IP3_17_15,
+
+	/* GPSR1 */
+	FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
+	FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
+	FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
+	FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
+	FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
+	FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
+	FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
+
+	/* GPSR2 */
+	FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
+	FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
+	FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
+	FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
+	FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
+	FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
+	FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
+
+	/* GPSR3 */
+	FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
+	FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
+	FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
+	FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
+	FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
+	FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
+	FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
+
+	/* GPSR4 */
+	FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
+	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
+	FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
+	FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
+	FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
+	FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
+	FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
+	FN_IP14_15_12, FN_IP14_18_16,
+
+	/* GPSR5 */
+	FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
+	FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
+	FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
+	FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
+	FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
+	FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
+	FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
+
+	/* IPSR0 - IPSR5 */
+	/* IPSR6 */
+	FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+	FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
+	FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+	FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
+	FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
+	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
+	FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+	FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
+	FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
+	FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
+	FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
+	FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
+	FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+	FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
+	FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+	FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
+	FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+	FN_STP_IVCXO27_1_B, FN_HRX0_F,
+
+	/* IPSR7 */
+	FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+	FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
+	FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+	FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
+	FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
+	FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
+	FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
+	FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+	FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
+	FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+	FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
+	FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
+	FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
+	FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
+	FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
+	FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+	FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+	FN_MII_RXD2,
+
+	/* IPSR8 - IPSR16 */
+
+	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+	FN_SEL_SCIF1_4,
+	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
+	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
+	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+	FN_SEL_SCIFB1_4,
+	FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
+	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
+	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+	FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+	FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
+	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+	FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
+	FN_SEL_VI3_0, FN_SEL_VI3_1,
+	FN_SEL_VI2_0, FN_SEL_VI2_1,
+	FN_SEL_VI1_0, FN_SEL_VI1_1,
+	FN_SEL_VI0_0, FN_SEL_VI0_1,
+	FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
+	FN_SEL_LBS_0, FN_SEL_LBS_1,
+	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+	FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+	FN_SEL_SOF0_0, FN_SEL_SOF0_1,
+
+	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
+	FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+	FN_SEL_ADI_0, FN_SEL_ADI_1,
+	FN_SEL_SSP_0, FN_SEL_SSP_1,
+	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+	FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
+	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
+	FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
+	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
+	FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+	FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
+	FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
+	FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
+
+	FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+	FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+	FN_SEL_IIC2_4,
+	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
+	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+	FN_SEL_I2C2_4,
+	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
+
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+	DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+	VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
+	DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
+	SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
+	INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
+	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
+	ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
+	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
+	SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
+	STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
+	SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
+	STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
+	SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
+	RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
+	TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
+	RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
+	STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
+	ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
+	STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
+
+	ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
+	SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
+	RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
+	ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
+	HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
+	SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
+	STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
+	ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
+	TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
+	SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
+	GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
+	STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
+	PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
+	PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
+	AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
+	ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
+	VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
+	MII_RXD2_MARK,
+
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	PINMUX_IPSR_DATA(IP6_2_0, DACK0),
+	PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
+	PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
+	PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
+	PINMUX_IPSR_DATA(IP6_8_6, DACK1),
+	PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
+	PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
+	PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
+	PINMUX_IPSR_DATA(IP6_13_11, DACK2),
+	PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
+	PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
+	PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
+	PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
+	PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
+	PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
+	PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
+	PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
+	PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
+	PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
+	PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
+	PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
+	PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
+	PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
+
+	PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
+	PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
+	PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
+	PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
+	PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
+	PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
+	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
+	PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
+	PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
+	PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
+	PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
+	PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
+	PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
+	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_18_16, PWM0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_21_19, PWM1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
+	PINMUX_IPSR_DATA(IP7_24_22, PWM2),
+	PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
+	PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
+	PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
+	PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
+	PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
+	PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
+	PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
+	PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
+	PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
+	PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
+	PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
+	PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
+
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+
+	/*IPSR0 - IPSR5*/
+	/*IPSR6*/
+	GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N),
+	GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B),
+	GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB),
+	GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B),
+	GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B),
+	GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B),
+	GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2),
+	GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B),
+	GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV),
+	GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D),
+	GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E),
+	GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B),
+	GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E),
+	GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0),
+	GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C),
+	GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1),
+	GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B),
+	GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G),
+	GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E),
+	GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E),
+	GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E),
+	GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F),
+
+	/*IPSR7*/
+	GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E),
+	GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1),
+	GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G),
+	GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN),
+	GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC),
+	GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0),
+	GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C),
+	GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC),
+	GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C),
+	GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B),
+	GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1),
+	GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C),
+	GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0),
+	GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C),
+	GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C),
+	GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1),
+	GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N),
+	GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2),
+	/*IPSR8 - IPSR16*/
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+		GP_0_31_FN, FN_IP3_17_15,
+		GP_0_30_FN, FN_IP3_14_12,
+		GP_0_29_FN, FN_IP3_11_8,
+		GP_0_28_FN, FN_IP3_7_4,
+		GP_0_27_FN, FN_IP3_3_0,
+		GP_0_26_FN, FN_IP2_28_26,
+		GP_0_25_FN, FN_IP2_25_22,
+		GP_0_24_FN, FN_IP2_21_18,
+		GP_0_23_FN, FN_IP2_17_15,
+		GP_0_22_FN, FN_IP2_14_12,
+		GP_0_21_FN, FN_IP2_11_9,
+		GP_0_20_FN, FN_IP2_8_6,
+		GP_0_19_FN, FN_IP2_5_3,
+		GP_0_18_FN, FN_IP2_2_0,
+		GP_0_17_FN, FN_IP1_29_28,
+		GP_0_16_FN, FN_IP1_27_26,
+		GP_0_15_FN, FN_IP1_25_22,
+		GP_0_14_FN, FN_IP1_21_18,
+		GP_0_13_FN, FN_IP1_17_15,
+		GP_0_12_FN, FN_IP1_14_12,
+		GP_0_11_FN, FN_IP1_11_8,
+		GP_0_10_FN, FN_IP1_7_4,
+		GP_0_9_FN, FN_IP1_3_0,
+		GP_0_8_FN, FN_IP0_30_27,
+		GP_0_7_FN, FN_IP0_26_23,
+		GP_0_6_FN, FN_IP0_22_20,
+		GP_0_5_FN, FN_IP0_19_16,
+		GP_0_4_FN, FN_IP0_15_12,
+		GP_0_3_FN, FN_IP0_11_9,
+		GP_0_2_FN, FN_IP0_8_6,
+		GP_0_1_FN, FN_IP0_5_3,
+		GP_0_0_FN, FN_IP0_2_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_1_29_FN, FN_IP6_13_11,
+		GP_1_28_FN, FN_IP6_10_9,
+		GP_1_27_FN, FN_IP6_8_6,
+		GP_1_26_FN, FN_IP6_5_3,
+		GP_1_25_FN, FN_IP6_2_0,
+		GP_1_24_FN, FN_IP5_29_27,
+		GP_1_23_FN, FN_IP5_26_24,
+		GP_1_22_FN, FN_IP5_23_21,
+		GP_1_21_FN, FN_IP5_20_18,
+		GP_1_20_FN, FN_IP5_17_15,
+		GP_1_19_FN, FN_IP5_14_13,
+		GP_1_18_FN, FN_IP5_12_10,
+		GP_1_17_FN, FN_IP5_9_6,
+		GP_1_16_FN, FN_IP5_5_3,
+		GP_1_15_FN, FN_IP5_2_0,
+		GP_1_14_FN, FN_IP4_29_27,
+		GP_1_13_FN, FN_IP4_26_24,
+		GP_1_12_FN, FN_IP4_23_21,
+		GP_1_11_FN, FN_IP4_20_18,
+		GP_1_10_FN, FN_IP4_17_15,
+		GP_1_9_FN, FN_IP4_14_12,
+		GP_1_8_FN, FN_IP4_11_9,
+		GP_1_7_FN, FN_IP4_8_6,
+		GP_1_6_FN, FN_IP4_5_3,
+		GP_1_5_FN, FN_IP4_2_0,
+		GP_1_4_FN, FN_IP3_31_29,
+		GP_1_3_FN, FN_IP3_28_26,
+		GP_1_2_FN, FN_IP3_25_23,
+		GP_1_1_FN, FN_IP3_22_20,
+		GP_1_0_FN, FN_IP3_19_18, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_2_29_FN, FN_IP7_15_13,
+		GP_2_28_FN, FN_IP7_12_10,
+		GP_2_27_FN, FN_IP7_9_8,
+		GP_2_26_FN, FN_IP7_7_6,
+		GP_2_25_FN, FN_IP7_5_3,
+		GP_2_24_FN, FN_IP7_2_0,
+		GP_2_23_FN, FN_IP6_31_29,
+		GP_2_22_FN, FN_IP6_28_26,
+		GP_2_21_FN, FN_IP6_25_23,
+		GP_2_20_FN, FN_IP6_22_20,
+		GP_2_19_FN, FN_IP6_19_17,
+		GP_2_18_FN, FN_IP6_16_14,
+		GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
+		GP_2_16_FN, FN_IP8_27,
+		GP_2_15_FN, FN_IP8_26,
+		GP_2_14_FN, FN_IP8_25_24,
+		GP_2_13_FN, FN_IP8_23_22,
+		GP_2_12_FN, FN_IP8_21_20,
+		GP_2_11_FN, FN_IP8_19_18,
+		GP_2_10_FN, FN_IP8_17_16,
+		GP_2_9_FN, FN_IP8_15_14,
+		GP_2_8_FN, FN_IP8_13_12,
+		GP_2_7_FN, FN_IP8_11_10,
+		GP_2_6_FN, FN_IP8_9_8,
+		GP_2_5_FN, FN_IP8_7_6,
+		GP_2_4_FN, FN_IP8_5_4,
+		GP_2_3_FN, FN_IP8_3_2,
+		GP_2_2_FN, FN_IP8_1_0,
+		GP_2_1_FN, FN_IP7_30_29,
+		GP_2_0_FN, FN_IP7_28_27 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+		GP_3_31_FN, FN_IP11_21_18,
+		GP_3_30_FN, FN_IP11_17_15,
+		GP_3_29_FN, FN_IP11_14_13,
+		GP_3_28_FN, FN_IP11_12_11,
+		GP_3_27_FN, FN_IP11_10_9,
+		GP_3_26_FN, FN_IP11_8_7,
+		GP_3_25_FN, FN_IP11_6_5,
+		GP_3_24_FN, FN_IP11_4,
+		GP_3_23_FN, FN_IP11_3_0,
+		GP_3_22_FN, FN_IP10_29_26,
+		GP_3_21_FN, FN_IP10_25_23,
+		GP_3_20_FN, FN_IP10_22_19,
+		GP_3_19_FN, FN_IP10_18_15,
+		GP_3_18_FN, FN_IP10_14_11,
+		GP_3_17_FN, FN_IP10_10_7,
+		GP_3_16_FN, FN_IP10_6_4,
+		GP_3_15_FN, FN_IP10_3_0,
+		GP_3_14_FN, FN_IP9_31_28,
+		GP_3_13_FN, FN_IP9_27_26,
+		GP_3_12_FN, FN_IP9_25_24,
+		GP_3_11_FN, FN_IP9_23_22,
+		GP_3_10_FN, FN_IP9_21_20,
+		GP_3_9_FN, FN_IP9_19_18,
+		GP_3_8_FN, FN_IP9_17_16,
+		GP_3_7_FN, FN_IP9_15_12,
+		GP_3_6_FN, FN_IP9_11_8,
+		GP_3_5_FN, FN_IP9_7_6,
+		GP_3_4_FN, FN_IP9_5_4,
+		GP_3_3_FN, FN_IP9_3_2,
+		GP_3_2_FN, FN_IP9_1_0,
+		GP_3_1_FN, FN_IP8_30_29,
+		GP_3_0_FN, FN_IP8_28 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+		GP_4_31_FN, FN_IP14_18_16,
+		GP_4_30_FN, FN_IP14_15_12,
+		GP_4_29_FN, FN_IP14_11_9,
+		GP_4_28_FN, FN_IP14_8_6,
+		GP_4_27_FN, FN_IP14_5_3,
+		GP_4_26_FN, FN_IP14_2_0,
+		GP_4_25_FN, FN_IP13_30_29,
+		GP_4_24_FN, FN_IP13_28_26,
+		GP_4_23_FN, FN_IP13_25_23,
+		GP_4_22_FN, FN_IP13_22_19,
+		GP_4_21_FN, FN_IP13_18_16,
+		GP_4_20_FN, FN_IP13_15_13,
+		GP_4_19_FN, FN_IP13_12_10,
+		GP_4_18_FN, FN_IP13_9_7,
+		GP_4_17_FN, FN_IP13_6_3,
+		GP_4_16_FN, FN_IP13_2_0,
+		GP_4_15_FN, FN_IP12_30_28,
+		GP_4_14_FN, FN_IP12_27_25,
+		GP_4_13_FN, FN_IP12_24_23,
+		GP_4_12_FN, FN_IP12_22_20,
+		GP_4_11_FN, FN_IP12_19_17,
+		GP_4_10_FN, FN_IP12_16_14,
+		GP_4_9_FN, FN_IP12_13_11,
+		GP_4_8_FN, FN_IP12_10_8,
+		GP_4_7_FN, FN_IP12_7_6,
+		GP_4_6_FN, FN_IP12_5_4,
+		GP_4_5_FN, FN_IP12_3_2,
+		GP_4_4_FN, FN_IP12_1_0,
+		GP_4_3_FN, FN_IP11_31_30,
+		GP_4_2_FN, FN_IP11_29_27,
+		GP_4_1_FN, FN_IP11_26_24,
+		GP_4_0_FN, FN_IP11_23_22 }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+		GP_5_31_FN, FN_IP7_24_22,
+		GP_5_30_FN, FN_IP7_21_19,
+		GP_5_29_FN, FN_IP7_18_16,
+		GP_5_28_FN, FN_DU_DOTCLKIN2,
+		GP_5_27_FN, FN_IP7_26_25,
+		GP_5_26_FN, FN_DU_DOTCLKIN0,
+		GP_5_25_FN, FN_AVS2,
+		GP_5_24_FN, FN_AVS1,
+		GP_5_23_FN, FN_USB2_OVC,
+		GP_5_22_FN, FN_USB2_PWEN,
+		GP_5_21_FN, FN_IP16_7,
+		GP_5_20_FN, FN_IP16_6,
+		GP_5_19_FN, FN_USB0_OVC_VBUS,
+		GP_5_18_FN, FN_USB0_PWEN,
+		GP_5_17_FN, FN_IP16_5_3,
+		GP_5_16_FN, FN_IP16_2_0,
+		GP_5_15_FN, FN_IP15_29_28,
+		GP_5_14_FN, FN_IP15_27_26,
+		GP_5_13_FN, FN_IP15_25_23,
+		GP_5_12_FN, FN_IP15_22_20,
+		GP_5_11_FN, FN_IP15_19_18,
+		GP_5_10_FN, FN_IP15_17_16,
+		GP_5_9_FN, FN_IP15_15_14,
+		GP_5_8_FN, FN_IP15_13_12,
+		GP_5_7_FN, FN_IP15_11_9,
+		GP_5_6_FN, FN_IP15_8_6,
+		GP_5_5_FN, FN_IP15_5_3,
+		GP_5_4_FN, FN_IP15_2_0,
+		GP_5_3_FN, FN_IP14_30_28,
+		GP_5_2_FN, FN_IP14_27_25,
+		GP_5_1_FN, FN_IP14_24_22,
+		GP_5_0_FN, FN_IP14_21_19 }
+	},
+
+	/*IPSR0 - IPSR5*/
+	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+			     3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
+		/* IP6_31_29 [3] */
+		FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+		FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
+		/* IP6_28_26 [3] */
+		FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+		FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
+		/* IP6_25_23 [3] */
+		FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+		FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
+		/* IP6_22_20 [3] */
+		FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
+		FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
+		/* IP6_19_17 [3] */
+		FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
+		FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
+		/* IP6_16_14 [3] */
+		FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+		FN_SCL2_CIS_E, 0,
+		/* IP6_13_11 [3] */
+		FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+		FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
+		/* IP6_10_9 [2] */
+		FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
+		/* IP6_8_6 [3] */
+		FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
+		FN_SSI_SDATA8_C, 0, 0, 0,
+		/* IP6_5_3 [3] */
+		FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+		FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
+		/* IP6_2_0 [3] */
+		FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+		FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+			     1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
+		/* IP7_31 [1] */
+		0, 0,
+		/* IP7_30_29 [2] */
+		FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+		FN_MII_RXD2,
+		/* IP7_28_27 [2] */
+		FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+		/* IP7_26_25 [2] */
+		FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
+		/* IP7_24_22 [3] */
+		FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
+		0, 0, 0,
+		/* IP7_21_19 [3] */
+		FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
+		FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
+		/* IP7_18_16 [3] */
+		FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+		FN_GLO_SS_C, 0, 0, 0,
+		/* IP7_15_13 [3] */
+		FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+		FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
+		/* IP7_12_10 [3] */
+		FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
+		FN_GLO_SCLK_C, 0, 0, 0,
+		/* IP7_9_8 [2] */
+		FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
+		/* IP7_7_6 [2] */
+		FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
+		/* IP7_5_3 [3] */
+		FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+		0, 0, 0,
+		/* IP7_2_0 [3] */
+		FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+		FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
+	},
+	/*IPSR8 - IPSR16*/
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_1_29_IN, GP_1_29_OUT,
+		GP_1_28_IN, GP_1_28_OUT,
+		GP_1_27_IN, GP_1_27_OUT,
+		GP_1_26_IN, GP_1_26_OUT,
+		GP_1_25_IN, GP_1_25_OUT,
+		GP_1_24_IN, GP_1_24_OUT,
+		GP_1_23_IN, GP_1_23_OUT,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_2_29_IN, GP_2_29_OUT,
+		GP_2_28_IN, GP_2_28_OUT,
+		GP_2_27_IN, GP_2_27_OUT,
+		GP_2_26_IN, GP_2_26_OUT,
+		GP_2_25_IN, GP_2_25_OUT,
+		GP_2_24_IN, GP_2_24_OUT,
+		GP_2_23_IN, GP_2_23_OUT,
+		GP_2_22_IN, GP_2_22_OUT,
+		GP_2_21_IN, GP_2_21_OUT,
+		GP_2_20_IN, GP_2_20_OUT,
+		GP_2_19_IN, GP_2_19_OUT,
+		GP_2_18_IN, GP_2_18_OUT,
+		GP_2_17_IN, GP_2_17_OUT,
+		GP_2_16_IN, GP_2_16_OUT,
+		GP_2_15_IN, GP_2_15_OUT,
+		GP_2_14_IN, GP_2_14_OUT,
+		GP_2_13_IN, GP_2_13_OUT,
+		GP_2_12_IN, GP_2_12_OUT,
+		GP_2_11_IN, GP_2_11_OUT,
+		GP_2_10_IN, GP_2_10_OUT,
+		GP_2_9_IN, GP_2_9_OUT,
+		GP_2_8_IN, GP_2_8_OUT,
+		GP_2_7_IN, GP_2_7_OUT,
+		GP_2_6_IN, GP_2_6_OUT,
+		GP_2_5_IN, GP_2_5_OUT,
+		GP_2_4_IN, GP_2_4_OUT,
+		GP_2_3_IN, GP_2_3_OUT,
+		GP_2_2_IN, GP_2_2_OUT,
+		GP_2_1_IN, GP_2_1_OUT,
+		GP_2_0_IN, GP_2_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, GP_1_29_DATA, GP_1_28_DATA,
+		GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
+		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
+		0, 0, GP_2_29_DATA, GP_2_28_DATA,
+		GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
+		GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
+		GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
+		GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
+		GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
+		GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
+		GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
+	{ },
+};
+
+static struct pinmux_info r8a7790_pinmux_info = {
+	.name = "r8a7790_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7790_pinmux_init(void)
+{
+	register_pinmux(&r8a7790_pinmux_info);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
new file mode 100644
index 000000000..a13317be0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __PFC_R8A7790_H__
+#define __PFC_R8A7790_H__
+
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+
+#define CPU_32_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
+	PORT_1(fn, pfx##31, sfx)
+
+#define CPU_32_PORT2(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx)
+
+#if defined(CONFIG_R8A7790)
+#define CPU_32_PORT1(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx)				\
+/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
+#define CPU_ALL_PORT(fn, pfx, sfx)				\
+	CPU_32_PORT(fn, pfx##_0_, sfx),				\
+	CPU_32_PORT1(fn, pfx##_1_, sfx),			\
+	CPU_32_PORT2(fn, pfx##_2_, sfx),			\
+	CPU_32_PORT(fn, pfx##_3_, sfx),				\
+	CPU_32_PORT(fn, pfx##_4_, sfx),				\
+	CPU_32_PORT(fn, pfx##_5_, sfx)
+
+#elif defined(CONFIG_R8A7791)
+#define CPU_32_PORT1(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
+
+/*
+ * GP_0_0_DATA -> GP_7_25_DATA
+ * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
+ *  GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
+ */
+#define CPU_ALL_PORT(fn, pfx, sfx)				\
+	CPU_32_PORT(fn, pfx##_0_, sfx),				\
+	CPU_32_PORT1(fn, pfx##_1_, sfx),			\
+	CPU_32_PORT(fn, pfx##_2_, sfx),				\
+	CPU_32_PORT(fn, pfx##_3_, sfx),				\
+	CPU_32_PORT(fn, pfx##_4_, sfx),				\
+	CPU_32_PORT(fn, pfx##_5_, sfx),				\
+	CPU_32_PORT(fn, pfx##_6_, sfx),				\
+	CPU_32_PORT1(fn, pfx##_7_, sfx)
+#else
+#error "NO support"
+#endif
+
+#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
+#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
+				       GP##pfx##_IN, GP##pfx##_OUT)
+
+#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
+#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
+
+#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
+#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
+
+#define PORT_10_REV(fn, pfx, sfx)				\
+	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
+	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
+	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
+	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
+	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+
+#define CPU_32_PORT_REV(fn, pfx, sfx)					\
+	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
+	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
+	PORT_10_REV(fn, pfx, sfx)
+
+#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+							  FN_##ipsr, FN_##fn)
+
+#endif /* __PFC_R8A7790_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
new file mode 100644
index 000000000..f49f990a0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
@@ -0,0 +1,1117 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include "pfc-r8a7790.h"
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
+	FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
+	FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
+	FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
+	FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
+	FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
+
+	/* GPSR1 */
+	FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
+	FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
+	FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
+	FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
+	FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
+	FN_IP3_21_20,
+
+	/* GPSR2 */
+	FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
+	FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
+	FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
+	FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
+	FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
+	FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
+	FN_IP6_5_3, FN_IP6_7_6,
+
+	/* GPSR3 */
+	FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
+	FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
+	FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
+	FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
+	FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
+	FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
+	FN_IP9_18_17,
+
+	/* GPSR4 */
+	FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
+	FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2,
+	FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5,
+	FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
+	FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
+	FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
+	FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
+	FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
+
+	/* GPSR5 */
+	FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
+	FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
+	FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
+	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
+	FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
+	FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
+	FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
+
+	/* GPSR6 */
+	FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
+	FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
+	FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
+	FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
+	FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
+	FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
+
+	/* GPSR7 */
+	FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
+	FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
+	FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
+	FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
+	FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
+	FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
+
+	/* IPSR0 -  IPSR10 */
+
+	/* IPSR11 */
+	FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
+	FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
+	FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+	FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
+	FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
+	FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
+	FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
+	FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
+	FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
+	FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
+	FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
+	FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
+	FN_VI1_DATA7, FN_AVB_MDC,
+	FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
+	FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
+
+	/* IPSR12 */
+	FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
+	FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
+	FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
+	FN_SCL2_D, FN_MSIOF1_RXD_E,
+	FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
+	FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
+	FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
+	FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
+	FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
+	FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
+	FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
+	FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
+	FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
+	FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+	FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
+	FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+	FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+
+	/* IPSR13 */
+	/* MOD_SEL */
+	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
+	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
+	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+	FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+	FN_SEL_QSP_0, FN_SEL_QSP_1,
+	FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
+	FN_SEL_HSCIF1_4,
+	FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
+	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+	FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
+	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+	FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
+
+	/* MOD_SEL2 */
+	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+	FN_SEL_SCIF0_4,
+	FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+	FN_SEL_CAN0_4, FN_SEL_CAN0_5,
+	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
+	FN_SEL_ADG_0, FN_SEL_ADG_1,
+	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
+	FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
+	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+	FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
+	FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
+	FN_SEL_SIM_0, FN_SEL_SIM_1,
+	FN_SEL_SSI8_0, FN_SEL_SSI8_1,
+
+	/* MOD_SEL3 */
+	FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
+	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+	FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
+	FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
+	FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
+	FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
+	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
+	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+	FN_SEL_MMC_0, FN_SEL_MMC_1,
+	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
+	FN_SEL_IIC1_4,
+	FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
+
+	/* MOD_SEL4 */
+	FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
+	FN_SEL_SOF1_4,
+	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+	FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
+	FN_SEL_RAD_0, FN_SEL_RAD_1,
+	FN_SEL_RCN_0, FN_SEL_RCN_1,
+	FN_SEL_RSP_0, FN_SEL_RSP_1,
+	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
+	FN_SEL_SCIF2_4,
+	FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
+	FN_SEL_SOF2_4,
+	FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+	FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+	EX_CS0_N_MARK, RD_N_MARK,
+
+	AUDIO_CLKA_MARK,
+
+	VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK,
+	VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK,
+	VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK,
+
+	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK,
+
+	/* IPSR0  IPSR10 */
+	/* IPSR11 */
+	VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
+	VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
+	VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
+	SDA4_B_MARK, _MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
+	VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
+	TX4_B_MARK, SCIFA4_TXD_B_MARK,
+	VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
+	RX4_B_MARK, SCIFA4_RXD_B_MARK,
+	VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
+	VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
+	VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
+	VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
+	VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
+	VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
+	VI1_DATA7_MARK, AVB_MDC_MARK,
+	ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
+	ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
+
+	/* IPSR12 */
+	ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
+	ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
+	ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
+	SCL2_D_MARK, MSIOF1_RXD_E_MARK,
+	ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
+	SDA2_D_MARK, MSIOF1_SCK_E_MARK,
+	ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
+	CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
+	ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
+	CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
+	ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
+	ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
+	ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
+	ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
+	STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
+	ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
+	STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
+	ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
+
+	/* IPSR13 */
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	/* OTHER IPSR0  - IPSR10 */
+	/* IPSR11 */
+	PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
+	PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
+	PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
+	PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
+	PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
+	PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
+	PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
+	PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
+	PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
+	PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
+	PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
+	PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
+	PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
+	PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
+
+	/* IPSR12 */
+	PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
+	PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
+	PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
+	PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
+	PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
+	PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
+	PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
+	PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
+	PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
+	PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
+	PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
+	PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
+	PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
+	PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
+	PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
+	PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
+	PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
+	PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
+	PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
+	PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
+	PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
+
+	/* IPSR13 - IPSR16 */
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+
+	/* OTHER, IPSR0 - IPSR10 */
+	/* IPSR11 */
+	GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B),
+	GPIO_FN(RX0_C), GPIO_FN(SDA1_D),
+	GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7),
+	GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B),
+	GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B),
+	GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E),
+	GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D),
+	GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B),
+	GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B),
+	GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B),
+	GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B),
+	GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B),
+	GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B),
+	GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4),
+	GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5),
+	GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6),
+	GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7),
+	GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER),
+	GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO),
+	GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV),
+	GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC),
+	GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC),
+	GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C),
+	GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C),
+
+	/* IPSR12 */
+	GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7),
+	GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7),
+	GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C),
+	GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E),
+	GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C),
+	GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E),
+	GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B),
+	GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E),
+	GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B),
+	GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E),
+	GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3),
+	GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B),
+	GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C),
+	GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C),
+	GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C),
+	GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D),
+	GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C),
+	GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D),
+	GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C),
+
+	/* IPSR13 - IPSR16 */
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+		GP_0_31_FN, FN_IP1_22_20,
+		GP_0_30_FN, FN_IP1_19_17,
+		GP_0_29_FN, FN_IP1_16_14,
+		GP_0_28_FN, FN_IP1_13_11,
+		GP_0_27_FN, FN_IP1_10_8,
+		GP_0_26_FN, FN_IP1_7_6,
+		GP_0_25_FN, FN_IP1_5_4,
+		GP_0_24_FN, FN_IP1_3_2,
+		GP_0_23_FN, FN_IP1_1_0,
+		GP_0_22_FN, FN_IP0_30_29,
+		GP_0_21_FN, FN_IP0_28_27,
+		GP_0_20_FN, FN_IP0_26_25,
+		GP_0_19_FN, FN_IP0_24_23,
+		GP_0_18_FN, FN_IP0_22_21,
+		GP_0_17_FN, FN_IP0_20_19,
+		GP_0_16_FN, FN_IP0_18_16,
+		GP_0_15_FN, FN_IP0_15,
+		GP_0_14_FN, FN_IP0_14,
+		GP_0_13_FN, FN_IP0_13,
+		GP_0_12_FN, FN_IP0_12,
+		GP_0_11_FN, FN_IP0_11,
+		GP_0_10_FN, FN_IP0_10,
+		GP_0_9_FN, FN_IP0_9,
+		GP_0_8_FN, FN_IP0_8,
+		GP_0_7_FN, FN_IP0_7,
+		GP_0_6_FN, FN_IP0_6,
+		GP_0_5_FN, FN_IP0_5,
+		GP_0_4_FN, FN_IP0_4,
+		GP_0_3_FN, FN_IP0_3,
+		GP_0_2_FN, FN_IP0_2,
+		GP_0_1_FN, FN_IP0_1,
+		GP_0_0_FN, FN_IP0_0, }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_25_FN, FN_IP3_21_20,
+		GP_1_24_FN, FN_IP3_19_18,
+		GP_1_23_FN, FN_IP3_17_16,
+		GP_1_22_FN, FN_IP3_15_14,
+		GP_1_21_FN, FN_IP3_13_12,
+		GP_1_20_FN, FN_IP3_11_9,
+		GP_1_19_FN, FN_RD_N,
+		GP_1_18_FN, FN_IP3_8_6,
+		GP_1_17_FN, FN_IP3_5_3,
+		GP_1_16_FN, FN_IP3_2_0,
+		GP_1_15_FN, FN_IP2_29_27,
+		GP_1_14_FN, FN_IP2_26_25,
+		GP_1_13_FN, FN_IP2_24_23,
+		GP_1_12_FN, FN_EX_CS0_N,
+		GP_1_11_FN, FN_IP2_22_21,
+		GP_1_10_FN, FN_IP2_20_19,
+		GP_1_9_FN, FN_IP2_18_16,
+		GP_1_8_FN, FN_IP2_15_13,
+		GP_1_7_FN, FN_IP2_12_10,
+		GP_1_6_FN, FN_IP2_9_7,
+		GP_1_5_FN, FN_IP2_6_5,
+		GP_1_4_FN, FN_IP2_4_3,
+		GP_1_3_FN, FN_IP2_2_0,
+		GP_1_2_FN, FN_IP1_31_29,
+		GP_1_1_FN, FN_IP1_28_26,
+		GP_1_0_FN, FN_IP1_25_23, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+		GP_2_31_FN, FN_IP6_7_6,
+		GP_2_30_FN, FN_IP6_5_3,
+		GP_2_29_FN, FN_IP6_2_0,
+		GP_2_28_FN, FN_AUDIO_CLKA,
+		GP_2_27_FN, FN_IP5_31_29,
+		GP_2_26_FN, FN_IP5_28_26,
+		GP_2_25_FN, FN_IP5_25_24,
+		GP_2_24_FN, FN_IP5_23_22,
+		GP_2_23_FN, FN_IP5_21_20,
+		GP_2_22_FN, FN_IP5_19_17,
+		GP_2_21_FN, FN_IP5_16_15,
+		GP_2_20_FN, FN_IP5_14_12,
+		GP_2_19_FN, FN_IP5_11_9,
+		GP_2_18_FN, FN_IP5_8_6,
+		GP_2_17_FN, FN_IP5_5_3,
+		GP_2_16_FN, FN_IP5_2_0,
+		GP_2_15_FN, FN_IP4_30_28,
+		GP_2_14_FN, FN_IP4_27_26,
+		GP_2_13_FN, FN_IP4_25_24,
+		GP_2_12_FN, FN_IP4_23_22,
+		GP_2_11_FN, FN_IP4_21,
+		GP_2_10_FN, FN_IP4_20,
+		GP_2_9_FN, FN_IP4_19,
+		GP_2_8_FN, FN_IP4_18_16,
+		GP_2_7_FN, FN_IP4_15_13,
+		GP_2_6_FN, FN_IP4_12_10,
+		GP_2_5_FN, FN_IP4_9_8,
+		GP_2_4_FN, FN_IP4_7_5,
+		GP_2_3_FN, FN_IP4_4_2,
+		GP_2_2_FN, FN_IP4_1_0,
+		GP_2_1_FN, FN_IP3_30_28,
+		GP_2_0_FN, FN_IP3_27_25 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+		GP_3_31_FN, FN_IP9_18_17,
+		GP_3_30_FN, FN_IP9_16,
+		GP_3_29_FN, FN_IP9_15_13,
+		GP_3_28_FN, FN_IP9_12,
+		GP_3_27_FN, FN_IP9_11,
+		GP_3_26_FN, FN_IP9_10_8,
+		GP_3_25_FN, FN_IP9_7,
+		GP_3_24_FN, FN_IP9_6,
+		GP_3_23_FN, FN_IP9_5_3,
+		GP_3_22_FN, FN_IP9_2_0,
+		GP_3_21_FN, FN_IP8_30_28,
+		GP_3_20_FN, FN_IP8_27_26,
+		GP_3_19_FN, FN_IP8_25_24,
+		GP_3_18_FN, FN_IP8_23_21,
+		GP_3_17_FN, FN_IP8_20_18,
+		GP_3_16_FN, FN_IP8_17_15,
+		GP_3_15_FN, FN_IP8_14_12,
+		GP_3_14_FN, FN_IP8_11_9,
+		GP_3_13_FN, FN_IP8_8_6,
+		GP_3_12_FN, FN_IP8_5_3,
+		GP_3_11_FN, FN_IP8_2_0,
+		GP_3_10_FN, FN_IP7_29_27,
+		GP_3_9_FN, FN_IP7_26_24,
+		GP_3_8_FN, FN_IP7_23_21,
+		GP_3_7_FN, FN_IP7_20_19,
+		GP_3_6_FN, FN_IP7_18_17,
+		GP_3_5_FN, FN_IP7_16_15,
+		GP_3_4_FN, FN_IP7_14_13,
+		GP_3_3_FN, FN_IP7_12_11,
+		GP_3_2_FN, FN_IP7_10_9,
+		GP_3_1_FN, FN_IP7_8_6,
+		GP_3_0_FN, FN_IP7_5_3 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+		GP_4_31_FN, FN_IP15_5_4,
+		GP_4_30_FN, FN_IP15_3_2,
+		GP_4_29_FN, FN_IP15_1_0,
+		GP_4_28_FN, FN_IP11_8_6,
+		GP_4_27_FN, FN_IP11_5_3,
+		GP_4_26_FN, FN_IP11_2_0,
+		GP_4_25_FN, FN_IP10_31_29,
+		GP_4_24_FN, FN_IP10_28_27,
+		GP_4_23_FN, FN_IP10_26_25,
+		GP_4_22_FN, FN_IP10_24_22,
+		GP_4_21_FN, FN_IP10_21_19,
+		GP_4_20_FN, FN_IP10_18_17,
+		GP_4_19_FN, FN_IP10_16_15,
+		GP_4_18_FN, FN_IP10_14_12,
+		GP_4_17_FN, FN_IP10_11_9,
+		GP_4_16_FN, FN_IP10_8_6,
+		GP_4_15_FN, FN_IP10_5_3,
+		GP_4_14_FN, FN_IP10_2_0,
+		GP_4_13_FN, FN_IP9_31_29,
+		GP_4_12_FN, FN_VI0_DATA0_VI0_B7,
+		GP_4_11_FN, FN_VI0_DATA0_VI0_B6,
+		GP_4_10_FN, FN_VI0_DATA0_VI0_B5,
+		GP_4_9_FN, FN_VI0_DATA0_VI0_B4,
+		GP_4_8_FN, FN_IP9_28_27,
+		GP_4_7_FN, FN_VI0_DATA0_VI0_B2,
+		GP_4_6_FN, FN_VI0_DATA0_VI0_B1,
+		GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
+		GP_4_4_FN, FN_IP9_26_25,
+		GP_4_3_FN, FN_IP9_24_23,
+		GP_4_2_FN, FN_IP9_22_21,
+		GP_4_1_FN, FN_IP9_20_19,
+		GP_4_0_FN, FN_VI0_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+		GP_5_31_FN, FN_IP3_24_22,
+		GP_5_30_FN, FN_IP13_9_7,
+		GP_5_29_FN, FN_IP13_6_5,
+		GP_5_28_FN, FN_IP13_4_3,
+		GP_5_27_FN, FN_IP13_2_0,
+		GP_5_26_FN, FN_IP12_29_27,
+		GP_5_25_FN, FN_IP12_26_24,
+		GP_5_24_FN, FN_IP12_23_22,
+		GP_5_23_FN, FN_IP12_21_20,
+		GP_5_22_FN, FN_IP12_19_18,
+		GP_5_21_FN, FN_IP12_17_16,
+		GP_5_20_FN, FN_IP12_15_13,
+		GP_5_19_FN, FN_IP12_12_10,
+		GP_5_18_FN, FN_IP12_9_7,
+		GP_5_17_FN, FN_IP12_6_4,
+		GP_5_16_FN, FN_IP12_3_2,
+		GP_5_15_FN, FN_IP12_1_0,
+		GP_5_14_FN, FN_IP11_31_30,
+		GP_5_13_FN, FN_IP11_29_28,
+		GP_5_12_FN, FN_IP11_27,
+		GP_5_11_FN, FN_IP11_26,
+		GP_5_10_FN, FN_IP11_25,
+		GP_5_9_FN, FN_IP11_24,
+		GP_5_8_FN, FN_IP11_23,
+		GP_5_7_FN, FN_IP11_22,
+		GP_5_6_FN, FN_IP11_21,
+		GP_5_5_FN, FN_IP11_20,
+		GP_5_4_FN, FN_IP11_19,
+		GP_5_3_FN, FN_IP11_18_17,
+		GP_5_2_FN, FN_IP11_16_15,
+		GP_5_1_FN, FN_IP11_14_12,
+		GP_5_0_FN, FN_IP11_11_9 }
+	},
+	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_6_29_FN, FN_IP14_31_29,
+		GP_6_28_FN, FN_IP14_28_26,
+		GP_6_27_FN, FN_IP14_25_23,
+		GP_6_26_FN, FN_IP14_22_20,
+		GP_6_25_FN, FN_IP14_19_17,
+		GP_6_24_FN, FN_IP14_16_14,
+		GP_6_23_FN, FN_IP14_13_11,
+		GP_6_22_FN, FN_IP14_10_8,
+		GP_6_21_FN, FN_IP14_7,
+		GP_6_20_FN, FN_IP14_6,
+		GP_6_19_FN, FN_IP14_5,
+		GP_6_18_FN, FN_IP14_4,
+		GP_6_17_FN, FN_IP14_3,
+		GP_6_16_FN, FN_IP14_2,
+		GP_6_15_FN, FN_IP14_1_0,
+		GP_6_14_FN, FN_IP13_30_28,
+		GP_6_13_FN, FN_IP13_27,
+		GP_6_12_FN, FN_IP13_26,
+		GP_6_11_FN, FN_IP13_25,
+		GP_6_10_FN, FN_IP13_24_23,
+		GP_6_9_FN, FN_IP13_22,
+		0, 0,
+		GP_6_7_FN, FN_IP13_21_19,
+		GP_6_6_FN, FN_IP13_18_16,
+		GP_6_5_FN, FN_IP13_15,
+		GP_6_4_FN, FN_IP13_14,
+		GP_6_3_FN, FN_IP13_13,
+		GP_6_2_FN, FN_IP13_12,
+		GP_6_1_FN, FN_IP13_11,
+		GP_6_0_FN, FN_IP13_10 }
+	},
+	{ PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_25_FN, FN_USB1_PWEN,
+		GP_7_24_FN, FN_USB0_OVC,
+		GP_7_23_FN, FN_USB0_PWEN,
+		GP_7_22_FN, FN_IP15_14_12,
+		GP_7_21_FN, FN_IP15_11_9,
+		GP_7_20_FN, FN_IP15_8_6,
+		GP_7_19_FN, FN_IP7_2_0,
+		GP_7_18_FN, FN_IP6_29_27,
+		GP_7_17_FN, FN_IP6_26_24,
+		GP_7_16_FN, FN_IP6_23_21,
+		GP_7_15_FN, FN_IP6_20_19,
+		GP_7_14_FN, FN_IP6_18_16,
+		GP_7_13_FN, FN_IP6_15_14,
+		GP_7_12_FN, FN_IP6_13_12,
+		GP_7_11_FN, FN_IP6_11_10,
+		GP_7_10_FN, FN_IP6_9_8,
+		GP_7_9_FN, FN_IP16_11_10,
+		GP_7_8_FN, FN_IP16_9_8,
+		GP_7_7_FN, FN_IP16_7_6,
+		GP_7_6_FN, FN_IP16_5_3,
+		GP_7_5_FN, FN_IP16_2_0,
+		GP_7_4_FN, FN_IP15_29_27,
+		GP_7_3_FN, FN_IP15_26_24,
+		GP_7_2_FN, FN_IP15_23_21,
+		GP_7_1_FN, FN_IP15_20_18,
+		GP_7_0_FN, FN_IP15_17_15 }
+	},
+	/* IPSR0 - IPSR10 */
+	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+			     2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
+			     3, 3, 3, 3, 3) {
+		/* IP11_31_30 [2] */
+		FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
+		/* IP11_29_28 [2] */
+		FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
+		/* IP11_27 [1] */
+		FN_VI1_DATA7, FN_AVB_MDC,
+		/* IP11_26 [1] */
+		FN_VI1_DATA6, FN_AVB_MAGIC,
+		/* IP11_25 [1] */
+		FN_VI1_DATA5, FN_AVB_RX_DV,
+		/* IP11_24 [1] */
+		FN_VI1_DATA4, FN_AVB_MDIO,
+		/* IP11_23 [1] */
+		FN_VI1_DATA3, FN_AVB_RX_ER,
+		/* IP11_22 [1] */
+		FN_VI1_DATA2, FN_AVB_RXD7,
+		/* IP11_21 [1] */
+		FN_VI1_DATA1, FN_AVB_RXD6,
+		/* IP11_20 [1] */
+		FN_VI1_DATA0, FN_AVB_RXD5,
+		/* IP11_19 [1] */
+		FN_VI1_CLK, FN_AVB_RXD4,
+		/* IP11_18_17 [2] */
+		FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
+		/* IP11_16_15 [2] */
+		FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
+		/* IP11_14_12 [3] */
+		FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
+		FN_RX4_B, FN_SCIFA4_RXD_B,
+		0, 0, 0,
+		/* IP11_11_9 [3] */
+		FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
+		FN_TX4_B, FN_SCIFA4_TXD_B,
+		0, 0, 0,
+		/* IP11_8_6 [3] */
+		FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+		FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
+		/* IP11_5_3 [3] */
+		FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
+		0, 0, 0,
+		/* IP11_2_0 [3] */
+		FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
+		0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+			     2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
+		/* IP12_31_30 [2] */
+		0, 0, 0, 0,
+		/* IP12_29_27 [3] */
+		FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+		FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+		0, 0, 0,
+		/* IP12_26_24 [3] */
+		FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+		FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
+		0, 0, 0,
+		/* IP12_23_22 [2] */
+		FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
+		/* IP12_21_20 [2] */
+		FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
+		/* IP12_19_18 [2] */
+		FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
+		/* IP12_17_16 [2] */
+		FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
+		/* IP12_15_13 [3] */
+		FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
+		FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
+		0, 0, 0,
+		/* IP12_12_10 [3] */
+		FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
+		FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
+		0, 0, 0,
+		/* IP12_9_7 [3] */
+		FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
+		FN_SDA2_D, FN_MSIOF1_SCK_E,
+		0, 0, 0,
+		/* IP12_6_4 [3] */
+		FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
+		FN_SCL2_D, FN_MSIOF1_RXD_E,
+		0, 0, 0,
+		/* IP12_3_2 [2] */
+		FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
+		/* IP12_1_0 [2] */
+		FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
+	},
+
+	/* IPSR13 - IPSR16 */
+
+	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+			     1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
+			     3, 2, 2, 2, 1, 2, 2, 2) {
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SCIF1 [2] */
+		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+		/* SEL_SCIFB [2] */
+		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
+		/* SEL_SCIFB2 [2] */
+		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
+		FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
+		/* SEL_SCIFB1 [3] */
+		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
+		FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+		0, 0, 0, 0,
+		/* SEL_SCIFA1 [2] */
+		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
+		/* SEL_SSI9 [1] */
+		FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+		/* SEL_SCFA [1] */
+		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+		/* SEL_QSP [1] */
+		FN_SEL_QSP_0, FN_SEL_QSP_1,
+		/* SEL_SSI7 [1] */
+		FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+		/* SEL_HSCIF1 [3] */
+		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
+		FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
+		0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_VI1 [2] */
+		FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_TMU [1] */
+		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+		/* SEL_LBS [2] */
+		FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
+		/* SEL_TSIF0 [2] */
+		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+		/* SEL_SOF0 [2] */
+		FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+			     3, 1, 1, 3, 2, 1, 1, 2, 2,
+			     1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
+		/* SEL_SCIF0 [3] */
+		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
+		FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
+		0, 0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SCIF [1] */
+		FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+		/* SEL_CAN0 [3] */
+		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+		FN_SEL_CAN0_4, FN_SEL_CAN0_5,
+		0, 0,
+		/* SEL_CAN1 [2] */
+		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SCIFA2 [1] */
+		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+		/* SEL_SCIF4 [2] */
+		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_ADG [1] */
+		FN_SEL_ADG_0, FN_SEL_ADG_1,
+		/* SEL_FM [3] */
+		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
+		FN_SEL_FM_3, FN_SEL_FM_4,
+		0, 0, 0,
+		/* SEL_SCIFA5 [2] */
+		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_GPS [2] */
+		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+		/* SEL_SCIFA4 [2] */
+		FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
+		/* SEL_SCIFA3 [2] */
+		FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
+		/* SEL_SIM [1] */
+		FN_SEL_SIM_0, FN_SEL_SIM_1,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SSI8 [1] */
+		FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+			     2, 2, 2, 2, 2, 2, 2, 2,
+			     1, 1, 2, 2, 3, 2, 2, 2, 1) {
+		/* SEL_HSCIF2 [2] */
+		FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+		FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
+		/* SEL_CANCLK [2] */
+		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+		FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+		/* SEL_IIC8 [2] */
+		FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
+		/* SEL_IIC7 [2] */
+		FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
+		/* SEL_IIC4 [2] */
+		FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
+		/* SEL_IIC3 [2] */
+		FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
+		/* SEL_SCIF3 [2] */
+		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
+		/* SEL_IEB [2] */
+		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+		/* SEL_MMC [1] */
+		FN_SEL_MMC_0, FN_SEL_MMC_1,
+		/* SEL_SCIF5 [1] */
+		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_IIC2 [2] */
+		FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+		/* SEL_IIC1 [3] */
+		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
+		FN_SEL_IIC1_4,
+		0, 0, 0,
+		/* SEL_IIC0 [2] */
+		FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [1] */
+		0, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
+			     3, 2, 2, 1, 1, 1, 1, 3, 2,
+			     2, 3, 1, 1, 1, 2, 2, 2, 2) {
+		/* SEL_SOF1 [3] */
+		FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
+		FN_SEL_SOF1_4,
+		0, 0, 0,
+		/* SEL_HSCIF0 [2] */
+		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
+		/* SEL_DIS [2] */
+		FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_RAD [1] */
+		FN_SEL_RAD_0, FN_SEL_RAD_1,
+		/* SEL_RCN [1] */
+		FN_SEL_RCN_0, FN_SEL_RCN_1,
+		/* SEL_RSP [1] */
+		FN_SEL_RSP_0, FN_SEL_RSP_1,
+		/* SEL_SCIF2 [3] */
+		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
+		FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
+		0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_SOF2 [3] */
+		FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
+		FN_SEL_SOF2_3, FN_SEL_SOF2_4,
+		0, 0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SSI1 [1] */
+		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+		/* SEL_SSI0 [1] */
+		FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+		/* SEL_SSP [2] */
+		FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_25_IN, GP_1_25_OUT,
+		GP_1_24_IN, GP_1_24_OUT,
+		GP_1_23_IN, GP_1_23_OUT,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
+	{ PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
+	{ PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_25_IN, GP_7_25_OUT,
+		GP_7_24_IN, GP_7_24_OUT,
+		GP_7_23_IN, GP_7_23_OUT,
+		GP_7_22_IN, GP_7_22_OUT,
+		GP_7_21_IN, GP_7_21_OUT,
+		GP_7_20_IN, GP_7_20_OUT,
+		GP_7_19_IN, GP_7_19_OUT,
+		GP_7_18_IN, GP_7_18_OUT,
+		GP_7_17_IN, GP_7_17_OUT,
+		GP_7_16_IN, GP_7_16_OUT,
+		GP_7_15_IN, GP_7_15_OUT,
+		GP_7_14_IN, GP_7_14_OUT,
+		GP_7_13_IN, GP_7_13_OUT,
+		GP_7_12_IN, GP_7_12_OUT,
+		GP_7_11_IN, GP_7_11_OUT,
+		GP_7_10_IN, GP_7_10_OUT,
+		GP_7_9_IN, GP_7_9_OUT,
+		GP_7_8_IN, GP_7_8_OUT,
+		GP_7_7_IN, GP_7_7_OUT,
+		GP_7_6_IN, GP_7_6_OUT,
+		GP_7_5_IN, GP_7_5_OUT,
+		GP_7_4_IN, GP_7_4_OUT,
+		GP_7_3_IN, GP_7_3_OUT,
+		GP_7_2_IN, GP_7_2_OUT,
+		GP_7_1_IN, GP_7_1_OUT,
+		GP_7_0_IN, GP_7_0_OUT, }
+	},
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_1_25_DATA, GP_1_24_DATA,
+		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
+	{ PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
+	{ PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_7_25_DATA, GP_7_24_DATA,
+		GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA,
+		GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA,
+		GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
+		GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
+		GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
+		GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
+	},
+	{ },
+};
+
+static struct pinmux_info r8a7791_pinmux_info = {
+	.name = "r8a7791_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_MSIOF0_SCK_C /* GPIO_FN_CAN1_RX_B */,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7791_pinmux_init(void)
+{
+	register_pinmux(&r8a7791_pinmux_info);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c
new file mode 100644
index 000000000..55dab7c13
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c
@@ -0,0 +1,2807 @@
+/*
+ * sh73a0 processor support - PFC hardware block
+ *
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ * Copyright (C) 2010 NISHIMOTO Hiroki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/arch/sh73a0-gpio.h>
+
+#define CPU_ALL_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx,    sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx),	\
+	PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx),	\
+	PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx),	\
+	PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx),	\
+	PORT_10(fn, pfx##10, sfx),				\
+	PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx),	\
+	PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx),	\
+	PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx),	\
+	PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx),	\
+	PORT_1(fn, pfx##118, sfx),				\
+	PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx),	\
+	PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx),	\
+	PORT_10(fn, pfx##15, sfx),				\
+	PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx),	\
+	PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx),	\
+	PORT_1(fn, pfx##164, sfx),				\
+	PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx),	\
+	PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx),	\
+	PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx),	\
+	PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx),	\
+	PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx),	\
+	PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx),	\
+	PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx),	\
+	PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx),	\
+	PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx),	\
+	PORT_1(fn, pfx##282, sfx),				\
+	PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx),	\
+	PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	PORT_ALL(DATA),			/* PORT0_DATA -> PORT309_DATA */
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	PORT_ALL(IN),			/* PORT0_IN -> PORT309_IN */
+	PINMUX_INPUT_END,
+
+	PINMUX_INPUT_PULLUP_BEGIN,
+	PORT_ALL(IN_PU),		/* PORT0_IN_PU -> PORT309_IN_PU */
+	PINMUX_INPUT_PULLUP_END,
+
+	PINMUX_INPUT_PULLDOWN_BEGIN,
+	PORT_ALL(IN_PD),		/* PORT0_IN_PD -> PORT309_IN_PD */
+	PINMUX_INPUT_PULLDOWN_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	PORT_ALL(OUT),			/* PORT0_OUT -> PORT309_OUT */
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	PORT_ALL(FN_IN),		/* PORT0_FN_IN -> PORT309_FN_IN */
+	PORT_ALL(FN_OUT),		/* PORT0_FN_OUT -> PORT309_FN_OUT */
+	PORT_ALL(FN0),			/* PORT0_FN0 -> PORT309_FN0 */
+	PORT_ALL(FN1),			/* PORT0_FN1 -> PORT309_FN1 */
+	PORT_ALL(FN2),			/* PORT0_FN2 -> PORT309_FN2 */
+	PORT_ALL(FN3),			/* PORT0_FN3 -> PORT309_FN3 */
+	PORT_ALL(FN4),			/* PORT0_FN4 -> PORT309_FN4 */
+	PORT_ALL(FN5),			/* PORT0_FN5 -> PORT309_FN5 */
+	PORT_ALL(FN6),			/* PORT0_FN6 -> PORT309_FN6 */
+	PORT_ALL(FN7),			/* PORT0_FN7 -> PORT309_FN7 */
+
+	MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+	MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+	MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+	MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+	MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+	MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+	MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+	MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+	MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+	MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+	MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+	MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+	MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+	MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+	MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+	MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+	MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+	MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+	MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+	MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+	MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+	MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+	MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+	MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+	MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+	MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+	MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+	MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+	MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+	MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+	MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+	MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+	MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+	MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+	MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+	MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+	MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+	MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+	MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+	MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+	MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+	MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+	/* Hardware manual Table 25-1 (Function 0-7) */
+	VBUS_0_MARK,
+	GPI0_MARK,
+	GPI1_MARK,
+	GPI2_MARK,
+	GPI3_MARK,
+	GPI4_MARK,
+	GPI5_MARK,
+	GPI6_MARK,
+	GPI7_MARK,
+	SCIFA7_RXD_MARK,
+	SCIFA7_CTS__MARK,
+	GPO7_MARK, MFG0_OUT2_MARK,
+	GPO6_MARK, MFG1_OUT2_MARK,
+	GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
+	SCIFA0_TXD_MARK,
+	SCIFA7_TXD_MARK,
+	SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
+	GPO0_MARK,
+	GPO1_MARK,
+	GPO2_MARK, STATUS0_MARK,
+	GPO3_MARK, STATUS1_MARK,
+	GPO4_MARK, STATUS2_MARK,
+	VINT_MARK,
+	TCKON_MARK,
+	XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
+	MFG0_OUT1_MARK, PORT27_IROUT_MARK,
+	XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
+	PORT28_TPU1TO1_MARK,
+	SIM_RST_MARK, PORT29_TPU1TO1_MARK,
+	SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
+	SIM_D_MARK, PORT31_IROUT_MARK,
+	SCIFA4_TXD_MARK,
+	SCIFA4_RXD_MARK, XWUP_MARK,
+	SCIFA4_RTS__MARK,
+	SCIFA4_CTS__MARK,
+	FSIBOBT_MARK, FSIBIBT_MARK,
+	FSIBOLR_MARK, FSIBILR_MARK,
+	FSIBOSLD_MARK,
+	FSIBISLD_MARK,
+	VACK_MARK,
+	XTAL1L_MARK,
+	SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
+	SCIFA0_RXD_MARK,
+	SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
+	FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
+	FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
+	FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
+	FSICISLD_MARK, FSIDISLD_MARK,
+	FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
+	FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
+
+	FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
+	FSIAOSLD_MARK, BBIF2_TXD2_MARK,
+	FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
+	PORT53_FSICSPDIF_MARK,
+	FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
+	FSICCK_MARK, FSICOMC_MARK,
+	FSIAISLD_MARK, TPU0TO0_MARK,
+	A0_MARK, BS__MARK,
+	A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
+	A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
+	A14_MARK, KEYOUT5_MARK,
+	A15_MARK, KEYOUT4_MARK,
+	A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
+	A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
+	A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
+	A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
+	A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
+	A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
+	A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
+	A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
+	A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
+	A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
+	A26_MARK, KEYIN6_MARK,
+	KEYIN7_MARK,
+	D0_NAF0_MARK,
+	D1_NAF1_MARK,
+	D2_NAF2_MARK,
+	D3_NAF3_MARK,
+	D4_NAF4_MARK,
+	D5_NAF5_MARK,
+	D6_NAF6_MARK,
+	D7_NAF7_MARK,
+	D8_NAF8_MARK,
+	D9_NAF9_MARK,
+	D10_NAF10_MARK,
+	D11_NAF11_MARK,
+	D12_NAF12_MARK,
+	D13_NAF13_MARK,
+	D14_NAF14_MARK,
+	D15_NAF15_MARK,
+	CS4__MARK,
+	CS5A__MARK, PORT91_RDWR_MARK,
+	CS5B__MARK, FCE1__MARK,
+	CS6B__MARK, DACK0_MARK,
+	FCE0__MARK, CS6A__MARK,
+	WAIT__MARK, DREQ0_MARK,
+	RD__FSC_MARK,
+	WE0__FWE_MARK, RDWR_FWE_MARK,
+	WE1__MARK,
+	FRB_MARK,
+	CKO_MARK,
+	NBRSTOUT__MARK,
+	NBRST__MARK,
+	BBIF2_TXD_MARK,
+	BBIF2_RXD_MARK,
+	BBIF2_SYNC_MARK,
+	BBIF2_SCK_MARK,
+	SCIFA3_CTS__MARK, MFG3_IN2_MARK,
+	SCIFA3_RXD_MARK, MFG3_IN1_MARK,
+	BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
+	SCIFA3_TXD_MARK,
+	HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
+	HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
+	HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
+	HSI_TX_READY_MARK, BBIF1_TXD_MARK,
+	HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
+	PORT115_I2C_SCL3_MARK,
+	HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
+	PORT116_I2C_SDA3_MARK,
+	HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
+	HSI_TX_FLAG_MARK,
+	VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
+
+	VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
+	VIO2_HD_MARK, LCD2D1_MARK,
+	VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
+	VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
+	PORT131_KEYOUT11_MARK, LCD2D11_MARK,
+	VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
+	PORT132_KEYOUT10_MARK, LCD2D12_MARK,
+	VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
+	VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
+	VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
+	VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
+	VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
+	VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
+	VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
+	VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
+	VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
+	VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
+	VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
+	VIO2_D5_MARK, LCD2D3_MARK,
+	VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
+	VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
+	PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
+	VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
+	LCD2D18_MARK,
+	VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
+	VIO_CKO_MARK,
+	A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
+	MFG0_IN2_MARK,
+	TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
+	TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
+	TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
+	SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
+	SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
+	SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
+	SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
+	DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
+	PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
+	PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
+	PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
+	PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
+	PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
+	LCDD0_MARK,
+	LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
+	LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
+	LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
+	LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
+	LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
+	LCDD6_MARK,
+	LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
+	LCDD8_MARK, D16_MARK,
+	LCDD9_MARK, D17_MARK,
+	LCDD10_MARK, D18_MARK,
+	LCDD11_MARK, D19_MARK,
+	LCDD12_MARK, D20_MARK,
+	LCDD13_MARK, D21_MARK,
+	LCDD14_MARK, D22_MARK,
+	LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
+	LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
+	LCDD17_MARK, D25_MARK,
+	LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
+	LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
+	LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
+	LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
+	LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
+	LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
+	LCDDCK_MARK, LCDWR__MARK,
+	LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
+	VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
+	LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
+	PORT218_VIO_CKOR_MARK,
+	LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
+	MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
+	LCDVSYN_MARK, LCDVSYN2_MARK,
+	LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
+	MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
+	LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
+	VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
+
+	SCIFA1_TXD_MARK, OVCN2_MARK,
+	EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
+	SCIFA1_RTS__MARK, IDIN_MARK,
+	SCIFA1_RXD_MARK,
+	SCIFA1_CTS__MARK, MFG1_IN1_MARK,
+	MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
+	MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
+	MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
+	MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
+	MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
+	MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
+	MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
+	MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
+	MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
+	MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
+	SCIFA6_TXD_MARK,
+	PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
+	PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
+	PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
+	PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
+	MSIOF2R_RXD_MARK,
+	PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
+	MSIOF2R_TXD_MARK,
+	PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
+	TPU1TO0_MARK,
+	PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
+	TPU3TO1_MARK,
+	PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
+	TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
+	PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
+	MSIOF2R_TSYNC_MARK,
+	SDHICLK0_MARK,
+	SDHICD0_MARK,
+	SDHID0_0_MARK,
+	SDHID0_1_MARK,
+	SDHID0_2_MARK,
+	SDHID0_3_MARK,
+	SDHICMD0_MARK,
+	SDHIWP0_MARK,
+	SDHICLK1_MARK,
+	SDHID1_0_MARK, TS_SPSYNC2_MARK,
+	SDHID1_1_MARK, TS_SDAT2_MARK,
+	SDHID1_2_MARK, TS_SDEN2_MARK,
+	SDHID1_3_MARK, TS_SCK2_MARK,
+	SDHICMD1_MARK,
+	SDHICLK2_MARK,
+	SDHID2_0_MARK, TS_SPSYNC4_MARK,
+	SDHID2_1_MARK, TS_SDAT4_MARK,
+	SDHID2_2_MARK, TS_SDEN4_MARK,
+	SDHID2_3_MARK, TS_SCK4_MARK,
+	SDHICMD2_MARK,
+	MMCCLK0_MARK,
+	MMCD0_0_MARK,
+	MMCD0_1_MARK,
+	MMCD0_2_MARK,
+	MMCD0_3_MARK,
+	MMCD0_4_MARK, TS_SPSYNC5_MARK,
+	MMCD0_5_MARK, TS_SDAT5_MARK,
+	MMCD0_6_MARK, TS_SDEN5_MARK,
+	MMCD0_7_MARK, TS_SCK5_MARK,
+	MMCCMD0_MARK,
+	RESETOUTS__MARK, EXTAL2OUT_MARK,
+	MCP_WAIT__MCP_FRB_MARK,
+	MCP_CKO_MARK, MMCCLK1_MARK,
+	MCP_D15_MCP_NAF15_MARK,
+	MCP_D14_MCP_NAF14_MARK,
+	MCP_D13_MCP_NAF13_MARK,
+	MCP_D12_MCP_NAF12_MARK,
+	MCP_D11_MCP_NAF11_MARK,
+	MCP_D10_MCP_NAF10_MARK,
+	MCP_D9_MCP_NAF9_MARK,
+	MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
+	MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
+
+	MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
+	MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
+	MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
+	MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
+	MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
+	MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
+	MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
+	MCP_NBRSTOUT__MARK,
+	MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
+
+	/* MSEL2 special cases */
+	TSIF2_TS_XX1_MARK,
+	TSIF2_TS_XX2_MARK,
+	TSIF2_TS_XX3_MARK,
+	TSIF2_TS_XX4_MARK,
+	TSIF2_TS_XX5_MARK,
+	TSIF1_TS_XX1_MARK,
+	TSIF1_TS_XX2_MARK,
+	TSIF1_TS_XX3_MARK,
+	TSIF1_TS_XX4_MARK,
+	TSIF1_TS_XX5_MARK,
+	TSIF0_TS_XX1_MARK,
+	TSIF0_TS_XX2_MARK,
+	TSIF0_TS_XX3_MARK,
+	TSIF0_TS_XX4_MARK,
+	TSIF0_TS_XX5_MARK,
+	MST1_TS_XX1_MARK,
+	MST1_TS_XX2_MARK,
+	MST1_TS_XX3_MARK,
+	MST1_TS_XX4_MARK,
+	MST1_TS_XX5_MARK,
+	MST0_TS_XX1_MARK,
+	MST0_TS_XX2_MARK,
+	MST0_TS_XX3_MARK,
+	MST0_TS_XX4_MARK,
+	MST0_TS_XX5_MARK,
+
+	/* MSEL3 special cases */
+	SDHI0_VCCQ_MC0_ON_MARK,
+	SDHI0_VCCQ_MC0_OFF_MARK,
+	DEBUG_MON_VIO_MARK,
+	DEBUG_MON_LCDD_MARK,
+	LCDC_LCDC0_MARK,
+	LCDC_LCDC1_MARK,
+
+	/* MSEL4 special cases */
+	IRQ9_MEM_INT_MARK,
+	IRQ9_MCP_INT_MARK,
+	A11_MARK,
+	KEYOUT8_MARK,
+	TPU4TO3_MARK,
+	RESETA_N_PU_ON_MARK,
+	RESETA_N_PU_OFF_MARK,
+	EDBGREQ_PD_MARK,
+	EDBGREQ_PU_MARK,
+
+	/* Functions with pull-ups */
+	KEYIN0_PU_MARK,
+	KEYIN1_PU_MARK,
+	KEYIN2_PU_MARK,
+	KEYIN3_PU_MARK,
+	KEYIN4_PU_MARK,
+	KEYIN5_PU_MARK,
+	KEYIN6_PU_MARK,
+	KEYIN7_PU_MARK,
+	SDHICD0_PU_MARK,
+	SDHID0_0_PU_MARK,
+	SDHID0_1_PU_MARK,
+	SDHID0_2_PU_MARK,
+	SDHID0_3_PU_MARK,
+	SDHICMD0_PU_MARK,
+	SDHIWP0_PU_MARK,
+	SDHID1_0_PU_MARK,
+	SDHID1_1_PU_MARK,
+	SDHID1_2_PU_MARK,
+	SDHID1_3_PU_MARK,
+	SDHICMD1_PU_MARK,
+	SDHID2_0_PU_MARK,
+	SDHID2_1_PU_MARK,
+	SDHID2_2_PU_MARK,
+	SDHID2_3_PU_MARK,
+	SDHICMD2_PU_MARK,
+	MMCCMD0_PU_MARK,
+	MMCCMD1_PU_MARK,
+	MMCD0_0_PU_MARK,
+	MMCD0_1_PU_MARK,
+	MMCD0_2_PU_MARK,
+	MMCD0_3_PU_MARK,
+	MMCD0_4_PU_MARK,
+	MMCD0_5_PU_MARK,
+	MMCD0_6_PU_MARK,
+	MMCD0_7_PU_MARK,
+	FSIBISLD_PU_MARK,
+	FSIACK_PU_MARK,
+	FSIAILR_PU_MARK,
+	FSIAIBT_PU_MARK,
+	FSIAISLD_PU_MARK,
+
+	PINMUX_MARK_END,
+};
+
+static unsigned short pinmux_data[] = {
+	/* specify valid pin states for each pin in GPIO mode */
+
+	/* Table 25-1 (I/O and Pull U/D) */
+	PORT_DATA_I_PD(0),
+	PORT_DATA_I_PU(1),
+	PORT_DATA_I_PU(2),
+	PORT_DATA_I_PU(3),
+	PORT_DATA_I_PU(4),
+	PORT_DATA_I_PU(5),
+	PORT_DATA_I_PU(6),
+	PORT_DATA_I_PU(7),
+	PORT_DATA_I_PU(8),
+	PORT_DATA_I_PD(9),
+	PORT_DATA_I_PD(10),
+	PORT_DATA_I_PU_PD(11),
+	PORT_DATA_IO_PU_PD(12),
+	PORT_DATA_IO_PU_PD(13),
+	PORT_DATA_IO_PU_PD(14),
+	PORT_DATA_IO_PU_PD(15),
+	PORT_DATA_IO_PD(16),
+	PORT_DATA_IO_PD(17),
+	PORT_DATA_IO_PU(18),
+	PORT_DATA_IO_PU(19),
+	PORT_DATA_O(20),
+	PORT_DATA_O(21),
+	PORT_DATA_O(22),
+	PORT_DATA_O(23),
+	PORT_DATA_O(24),
+	PORT_DATA_I_PD(25),
+	PORT_DATA_I_PD(26),
+	PORT_DATA_IO_PU(27),
+	PORT_DATA_IO_PU(28),
+	PORT_DATA_IO_PD(29),
+	PORT_DATA_IO_PD(30),
+	PORT_DATA_IO_PU(31),
+	PORT_DATA_IO_PD(32),
+	PORT_DATA_I_PU_PD(33),
+	PORT_DATA_IO_PD(34),
+	PORT_DATA_I_PU_PD(35),
+	PORT_DATA_IO_PD(36),
+	PORT_DATA_IO(37),
+	PORT_DATA_O(38),
+	PORT_DATA_I_PU(39),
+	PORT_DATA_I_PU_PD(40),
+	PORT_DATA_O(41),
+	PORT_DATA_IO_PD(42),
+	PORT_DATA_IO_PU_PD(43),
+	PORT_DATA_IO_PU_PD(44),
+	PORT_DATA_IO_PD(45),
+	PORT_DATA_IO_PD(46),
+	PORT_DATA_IO_PD(47),
+	PORT_DATA_I_PD(48),
+	PORT_DATA_IO_PU_PD(49),
+	PORT_DATA_IO_PD(50),
+
+	PORT_DATA_IO_PD(51),
+	PORT_DATA_O(52),
+	PORT_DATA_IO_PU_PD(53),
+	PORT_DATA_IO_PU_PD(54),
+	PORT_DATA_IO_PD(55),
+	PORT_DATA_I_PU_PD(56),
+	PORT_DATA_IO(57),
+	PORT_DATA_IO(58),
+	PORT_DATA_IO(59),
+	PORT_DATA_IO(60),
+	PORT_DATA_IO(61),
+	PORT_DATA_IO_PD(62),
+	PORT_DATA_IO_PD(63),
+	PORT_DATA_IO_PU_PD(64),
+	PORT_DATA_IO_PD(65),
+	PORT_DATA_IO_PU_PD(66),
+	PORT_DATA_IO_PU_PD(67),
+	PORT_DATA_IO_PU_PD(68),
+	PORT_DATA_IO_PU_PD(69),
+	PORT_DATA_IO_PU_PD(70),
+	PORT_DATA_IO_PU_PD(71),
+	PORT_DATA_IO_PU_PD(72),
+	PORT_DATA_I_PU_PD(73),
+	PORT_DATA_IO_PU(74),
+	PORT_DATA_IO_PU(75),
+	PORT_DATA_IO_PU(76),
+	PORT_DATA_IO_PU(77),
+	PORT_DATA_IO_PU(78),
+	PORT_DATA_IO_PU(79),
+	PORT_DATA_IO_PU(80),
+	PORT_DATA_IO_PU(81),
+	PORT_DATA_IO_PU(82),
+	PORT_DATA_IO_PU(83),
+	PORT_DATA_IO_PU(84),
+	PORT_DATA_IO_PU(85),
+	PORT_DATA_IO_PU(86),
+	PORT_DATA_IO_PU(87),
+	PORT_DATA_IO_PU(88),
+	PORT_DATA_IO_PU(89),
+	PORT_DATA_O(90),
+	PORT_DATA_IO_PU(91),
+	PORT_DATA_O(92),
+	PORT_DATA_IO_PU(93),
+	PORT_DATA_O(94),
+	PORT_DATA_I_PU_PD(95),
+	PORT_DATA_IO(96),
+	PORT_DATA_IO(97),
+	PORT_DATA_IO(98),
+	PORT_DATA_I_PU(99),
+	PORT_DATA_O(100),
+	PORT_DATA_O(101),
+	PORT_DATA_I_PU(102),
+	PORT_DATA_IO_PD(103),
+	PORT_DATA_I_PU_PD(104),
+	PORT_DATA_I_PD(105),
+	PORT_DATA_I_PD(106),
+	PORT_DATA_I_PU_PD(107),
+	PORT_DATA_I_PU_PD(108),
+	PORT_DATA_IO_PD(109),
+	PORT_DATA_IO_PD(110),
+	PORT_DATA_IO_PU_PD(111),
+	PORT_DATA_IO_PU_PD(112),
+	PORT_DATA_IO_PU_PD(113),
+	PORT_DATA_IO_PD(114),
+	PORT_DATA_IO_PU(115),
+	PORT_DATA_IO_PU(116),
+	PORT_DATA_IO_PU_PD(117),
+	PORT_DATA_IO_PU_PD(118),
+	PORT_DATA_IO_PD(128),
+
+	PORT_DATA_IO_PD(129),
+	PORT_DATA_IO_PU_PD(130),
+	PORT_DATA_IO_PD(131),
+	PORT_DATA_IO_PD(132),
+	PORT_DATA_IO_PD(133),
+	PORT_DATA_IO_PU_PD(134),
+	PORT_DATA_IO_PU_PD(135),
+	PORT_DATA_IO_PU_PD(136),
+	PORT_DATA_IO_PU_PD(137),
+	PORT_DATA_IO_PD(138),
+	PORT_DATA_IO_PD(139),
+	PORT_DATA_IO_PD(140),
+	PORT_DATA_IO_PD(141),
+	PORT_DATA_IO_PD(142),
+	PORT_DATA_IO_PD(143),
+	PORT_DATA_IO_PU_PD(144),
+	PORT_DATA_IO_PD(145),
+	PORT_DATA_IO_PU_PD(146),
+	PORT_DATA_IO_PU_PD(147),
+	PORT_DATA_IO_PU_PD(148),
+	PORT_DATA_IO_PU_PD(149),
+	PORT_DATA_I_PU_PD(150),
+	PORT_DATA_IO_PU_PD(151),
+	PORT_DATA_IO_PU_PD(152),
+	PORT_DATA_IO_PD(153),
+	PORT_DATA_IO_PD(154),
+	PORT_DATA_I_PU_PD(155),
+	PORT_DATA_IO_PU_PD(156),
+	PORT_DATA_I_PD(157),
+	PORT_DATA_IO_PD(158),
+	PORT_DATA_IO_PU_PD(159),
+	PORT_DATA_IO_PU_PD(160),
+	PORT_DATA_I_PU_PD(161),
+	PORT_DATA_I_PU_PD(162),
+	PORT_DATA_IO_PU_PD(163),
+	PORT_DATA_I_PU_PD(164),
+	PORT_DATA_IO_PD(192),
+	PORT_DATA_IO_PU_PD(193),
+	PORT_DATA_IO_PD(194),
+	PORT_DATA_IO_PU_PD(195),
+	PORT_DATA_IO_PD(196),
+	PORT_DATA_IO_PD(197),
+	PORT_DATA_IO_PD(198),
+	PORT_DATA_IO_PD(199),
+	PORT_DATA_IO_PU_PD(200),
+	PORT_DATA_IO_PU_PD(201),
+	PORT_DATA_IO_PU_PD(202),
+	PORT_DATA_IO_PU_PD(203),
+	PORT_DATA_IO_PU_PD(204),
+	PORT_DATA_IO_PU_PD(205),
+	PORT_DATA_IO_PU_PD(206),
+	PORT_DATA_IO_PD(207),
+	PORT_DATA_IO_PD(208),
+	PORT_DATA_IO_PD(209),
+	PORT_DATA_IO_PD(210),
+	PORT_DATA_IO_PD(211),
+	PORT_DATA_IO_PD(212),
+	PORT_DATA_IO_PD(213),
+	PORT_DATA_IO_PU_PD(214),
+	PORT_DATA_IO_PU_PD(215),
+	PORT_DATA_IO_PD(216),
+	PORT_DATA_IO_PD(217),
+	PORT_DATA_O(218),
+	PORT_DATA_IO_PD(219),
+	PORT_DATA_IO_PD(220),
+	PORT_DATA_IO_PU_PD(221),
+	PORT_DATA_IO_PU_PD(222),
+	PORT_DATA_I_PU_PD(223),
+	PORT_DATA_I_PU_PD(224),
+
+	PORT_DATA_IO_PU_PD(225),
+	PORT_DATA_O(226),
+	PORT_DATA_IO_PU_PD(227),
+	PORT_DATA_I_PU_PD(228),
+	PORT_DATA_I_PD(229),
+	PORT_DATA_IO(230),
+	PORT_DATA_IO_PU_PD(231),
+	PORT_DATA_IO_PU_PD(232),
+	PORT_DATA_I_PU_PD(233),
+	PORT_DATA_IO_PU_PD(234),
+	PORT_DATA_IO_PU_PD(235),
+	PORT_DATA_IO_PU_PD(236),
+	PORT_DATA_IO_PD(237),
+	PORT_DATA_IO_PU_PD(238),
+	PORT_DATA_IO_PU_PD(239),
+	PORT_DATA_IO_PU_PD(240),
+	PORT_DATA_O(241),
+	PORT_DATA_I_PD(242),
+	PORT_DATA_IO_PU_PD(243),
+	PORT_DATA_IO_PU_PD(244),
+	PORT_DATA_IO_PU_PD(245),
+	PORT_DATA_IO_PU_PD(246),
+	PORT_DATA_IO_PU_PD(247),
+	PORT_DATA_IO_PU_PD(248),
+	PORT_DATA_IO_PU_PD(249),
+	PORT_DATA_IO_PU_PD(250),
+	PORT_DATA_IO_PU_PD(251),
+	PORT_DATA_IO_PU_PD(252),
+	PORT_DATA_IO_PU_PD(253),
+	PORT_DATA_IO_PU_PD(254),
+	PORT_DATA_IO_PU_PD(255),
+	PORT_DATA_IO_PU_PD(256),
+	PORT_DATA_IO_PU_PD(257),
+	PORT_DATA_IO_PU_PD(258),
+	PORT_DATA_IO_PU_PD(259),
+	PORT_DATA_IO_PU_PD(260),
+	PORT_DATA_IO_PU_PD(261),
+	PORT_DATA_IO_PU_PD(262),
+	PORT_DATA_IO_PU_PD(263),
+	PORT_DATA_IO_PU_PD(264),
+	PORT_DATA_IO_PU_PD(265),
+	PORT_DATA_IO_PU_PD(266),
+	PORT_DATA_IO_PU_PD(267),
+	PORT_DATA_IO_PU_PD(268),
+	PORT_DATA_IO_PU_PD(269),
+	PORT_DATA_IO_PU_PD(270),
+	PORT_DATA_IO_PU_PD(271),
+	PORT_DATA_IO_PU_PD(272),
+	PORT_DATA_IO_PU_PD(273),
+	PORT_DATA_IO_PU_PD(274),
+	PORT_DATA_IO_PU_PD(275),
+	PORT_DATA_IO_PU_PD(276),
+	PORT_DATA_IO_PU_PD(277),
+	PORT_DATA_IO_PU_PD(278),
+	PORT_DATA_IO_PU_PD(279),
+	PORT_DATA_IO_PU_PD(280),
+	PORT_DATA_O(281),
+	PORT_DATA_O(282),
+	PORT_DATA_I_PU(288),
+	PORT_DATA_IO_PU_PD(289),
+	PORT_DATA_IO_PU_PD(290),
+	PORT_DATA_IO_PU_PD(291),
+	PORT_DATA_IO_PU_PD(292),
+	PORT_DATA_IO_PU_PD(293),
+	PORT_DATA_IO_PU_PD(294),
+	PORT_DATA_IO_PU_PD(295),
+	PORT_DATA_IO_PU_PD(296),
+	PORT_DATA_IO_PU_PD(297),
+	PORT_DATA_IO_PU_PD(298),
+
+	PORT_DATA_IO_PU_PD(299),
+	PORT_DATA_IO_PU_PD(300),
+	PORT_DATA_IO_PU_PD(301),
+	PORT_DATA_IO_PU_PD(302),
+	PORT_DATA_IO_PU_PD(303),
+	PORT_DATA_IO_PU_PD(304),
+	PORT_DATA_IO_PU_PD(305),
+	PORT_DATA_O(306),
+	PORT_DATA_O(307),
+	PORT_DATA_I_PU(308),
+	PORT_DATA_O(309),
+
+	/* Table 25-1 (Function 0-7) */
+	PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
+	PINMUX_DATA(GPI0_MARK, PORT1_FN1),
+	PINMUX_DATA(GPI1_MARK, PORT2_FN1),
+	PINMUX_DATA(GPI2_MARK, PORT3_FN1),
+	PINMUX_DATA(GPI3_MARK, PORT4_FN1),
+	PINMUX_DATA(GPI4_MARK, PORT5_FN1),
+	PINMUX_DATA(GPI5_MARK, PORT6_FN1),
+	PINMUX_DATA(GPI6_MARK, PORT7_FN1),
+	PINMUX_DATA(GPI7_MARK, PORT8_FN1),
+	PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
+	PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
+	PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
+	PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
+	PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
+	PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
+	PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
+	PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
+	PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
+	PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
+	PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
+	PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
+	PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
+	PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
+	PINMUX_DATA(GPO0_MARK, PORT20_FN1),
+	PINMUX_DATA(GPO1_MARK, PORT21_FN1),
+	PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
+	PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
+	PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
+	PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
+	PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
+	PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
+	PINMUX_DATA(VINT_MARK, PORT25_FN1),
+	PINMUX_DATA(TCKON_MARK, PORT26_FN1),
+	PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
+	PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
+		MSEL2CR_MSEL16_1), \
+	PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
+		MSEL2CR_MSEL18_1), \
+	PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
+	PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
+	PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
+	PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
+		MSEL2CR_MSEL16_1), \
+	PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
+		MSEL2CR_MSEL18_1), \
+	PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
+	PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
+	PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
+	PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
+	PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
+	PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
+	PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
+	PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
+	PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
+	PINMUX_DATA(XWUP_MARK, PORT33_FN3),
+	PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
+	PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
+	PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
+	PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
+	PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
+	PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
+	PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
+	PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
+	PINMUX_DATA(VACK_MARK, PORT40_FN1),
+	PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
+	PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
+	PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
+	PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
+	PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
+	PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
+	PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
+	PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
+	PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
+	PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
+	PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
+	PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
+	PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
+	PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
+	PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
+	PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
+	PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
+	PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
+	PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
+	PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
+	PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
+	PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
+	PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
+	PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
+	PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
+	PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
+
+	PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
+	PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
+	PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
+	PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
+	PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
+	PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
+	PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
+	PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
+	PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
+	PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
+	PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
+	PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
+	PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
+	PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
+	PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
+	PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
+	PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
+	PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
+	PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
+	PINMUX_DATA(A0_MARK, PORT57_FN1), \
+	PINMUX_DATA(BS__MARK, PORT57_FN2),
+	PINMUX_DATA(A12_MARK, PORT58_FN1), \
+	PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
+	PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
+	PINMUX_DATA(A13_MARK, PORT59_FN1), \
+	PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
+	PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
+	PINMUX_DATA(A14_MARK, PORT60_FN1), \
+	PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
+	PINMUX_DATA(A15_MARK, PORT61_FN1), \
+	PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
+	PINMUX_DATA(A16_MARK, PORT62_FN1), \
+	PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
+	PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
+	PINMUX_DATA(A17_MARK, PORT63_FN1), \
+	PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
+	PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
+	PINMUX_DATA(A18_MARK, PORT64_FN1), \
+	PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
+	PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
+	PINMUX_DATA(A19_MARK, PORT65_FN1), \
+	PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
+	PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
+	PINMUX_DATA(A20_MARK, PORT66_FN1), \
+	PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
+	PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
+	PINMUX_DATA(A21_MARK, PORT67_FN1), \
+	PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
+	PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
+	PINMUX_DATA(A22_MARK, PORT68_FN1), \
+	PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
+	PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
+	PINMUX_DATA(A23_MARK, PORT69_FN1), \
+	PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
+	PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
+	PINMUX_DATA(A24_MARK, PORT70_FN1), \
+	PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
+	PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
+	PINMUX_DATA(A25_MARK, PORT71_FN1), \
+	PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
+	PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
+	PINMUX_DATA(A26_MARK, PORT72_FN1), \
+	PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
+	PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
+	PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
+	PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
+	PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
+	PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
+	PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
+	PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
+	PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
+	PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
+	PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
+	PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
+	PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
+	PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
+	PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
+	PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
+	PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
+	PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
+	PINMUX_DATA(CS4__MARK, PORT90_FN1),
+	PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
+	PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
+	PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
+	PINMUX_DATA(FCE1__MARK, PORT92_FN2),
+	PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
+	PINMUX_DATA(DACK0_MARK, PORT93_FN4),
+	PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
+	PINMUX_DATA(CS6A__MARK, PORT94_FN2),
+	PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
+	PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
+	PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
+	PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
+	PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
+	PINMUX_DATA(WE1__MARK, PORT98_FN1),
+	PINMUX_DATA(FRB_MARK, PORT99_FN1),
+	PINMUX_DATA(CKO_MARK, PORT100_FN1),
+	PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
+	PINMUX_DATA(NBRST__MARK, PORT102_FN1),
+	PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
+	PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
+	PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
+	PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
+	PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
+	PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
+	PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
+	PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
+	PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
+	PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
+	PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
+	PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
+	PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
+	PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
+	PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
+	PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
+	PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
+	PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
+	PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
+	PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
+	PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
+	PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
+	PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
+	PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
+	PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
+	PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
+	PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
+	PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
+	PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
+	PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
+	PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
+	PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
+	PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
+	PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
+	PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
+	PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
+
+	PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
+	PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
+	PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
+	PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
+	PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
+	PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
+	PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
+		MSEL4CR_MSEL10_1), \
+	PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
+	PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
+	PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
+	PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
+	PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
+	PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
+	PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
+	PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
+	PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
+	PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
+	PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
+	PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
+	PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
+	PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
+	PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
+	PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
+	PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
+	PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
+	PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
+	PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
+	PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
+	PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
+	PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
+	PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
+	PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
+	PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
+	PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
+	PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
+	PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
+	PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
+	PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
+	PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
+	PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
+	PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
+	PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
+	PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
+	PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
+	PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
+	PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
+	PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
+	PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
+	PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
+	PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
+	PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
+	PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
+	PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
+	PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
+	PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
+	PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
+	PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
+	PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
+	PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
+	PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
+	PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
+	PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
+	PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
+	PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
+	PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
+	PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
+	PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
+	PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
+	PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
+	PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
+	PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
+	PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
+	PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
+	PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
+	PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
+	PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
+	PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
+	PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
+	PINMUX_DATA(A27_MARK, PORT149_FN1), \
+	PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
+	PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
+	PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
+	PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
+	PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
+	PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
+	PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
+	PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
+	PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
+	PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
+	PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
+	PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
+	PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
+	PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
+	PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
+	PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
+	PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
+	PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
+	PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
+		MSEL4CR_MSEL10_0),
+	PINMUX_DATA(DINT__MARK, PORT158_FN1), \
+	PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
+	PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
+	PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
+	PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
+	PINMUX_DATA(NMI_MARK, PORT159_FN3),
+	PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
+	PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
+	PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
+	PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
+	PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
+	PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
+	PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
+	PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
+	PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
+	PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
+	PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
+	PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
+		MSEL4CR_MSEL20_1), \
+	PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
+	PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
+	PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
+		MSEL4CR_MSEL20_1), \
+	PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
+	PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
+	PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
+		MSEL4CR_MSEL20_1), \
+	PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
+	PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
+	PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
+		MSEL4CR_MSEL20_1),
+	PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
+	PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
+		MSEL4CR_MSEL20_1), \
+	PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
+	PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
+	PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
+	PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
+	PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
+	PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
+	PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
+	PINMUX_DATA(D16_MARK, PORT200_FN6),
+	PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
+	PINMUX_DATA(D17_MARK, PORT201_FN6),
+	PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
+	PINMUX_DATA(D18_MARK, PORT202_FN6),
+	PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
+	PINMUX_DATA(D19_MARK, PORT203_FN6),
+	PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
+	PINMUX_DATA(D20_MARK, PORT204_FN6),
+	PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
+	PINMUX_DATA(D21_MARK, PORT205_FN6),
+	PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
+	PINMUX_DATA(D22_MARK, PORT206_FN6),
+	PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
+	PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(D23_MARK, PORT207_FN6),
+	PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
+	PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(D24_MARK, PORT208_FN6),
+	PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
+	PINMUX_DATA(D25_MARK, PORT209_FN6),
+	PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
+	PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
+	PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(D26_MARK, PORT210_FN6),
+	PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
+	PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(D27_MARK, PORT211_FN6),
+	PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
+	PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
+	PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(D28_MARK, PORT212_FN6),
+	PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
+	PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
+	PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(D29_MARK, PORT213_FN6),
+	PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
+	PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
+	PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(D30_MARK, PORT214_FN6),
+	PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
+	PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
+	PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(D31_MARK, PORT215_FN6),
+	PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
+	PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
+	PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
+	PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
+	PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
+	PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
+		MSEL4CR_MSEL26_1), \
+	PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
+	PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
+	PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
+	PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
+	PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
+	PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
+	PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
+	PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
+	PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
+	PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
+	PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
+		MSEL4CR_MSEL26_1), \
+	PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
+	PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
+	PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
+	PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
+	PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
+	PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
+	PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
+	PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
+		MSEL4CR_MSEL26_1), \
+	PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
+	PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
+	PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
+	PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
+	PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
+	PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
+	PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
+		MSEL4CR_MSEL26_1), \
+	PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
+
+	PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
+	PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
+	PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
+	PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
+	PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
+	PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
+	PINMUX_DATA(IDIN_MARK, PORT227_FN4),
+	PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
+	PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
+	PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
+	PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
+	PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
+	PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
+	PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
+	PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
+	PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
+	PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
+	PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
+	PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
+	PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
+	PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
+		MSEL4CR_MSEL26_0), \
+	PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
+	PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
+	PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
+	PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
+		MSEL4CR_MSEL26_0), \
+	PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
+	PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
+	PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
+		MSEL2CR_MSEL16_0),
+	PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
+	PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
+		MSEL2CR_MSEL16_0),
+	PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
+	PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
+		MSEL4CR_MSEL26_0), \
+	PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
+	PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
+	PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
+		MSEL4CR_MSEL26_0), \
+	PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
+	PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
+	PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
+	PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
+	PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
+	PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
+	PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
+	PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
+	PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
+	PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
+	PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
+		MSEL4CR_MSEL20_0), \
+	PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
+	PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
+	PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
+	PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
+		MSEL4CR_MSEL20_0), \
+	PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
+	PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
+	PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
+	PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
+		MSEL4CR_MSEL20_0), \
+	PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
+	PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
+	PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
+	PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
+		MSEL4CR_MSEL20_0), \
+	PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
+	PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
+	PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
+	PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
+		MSEL4CR_MSEL20_0), \
+	PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
+	PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
+	PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
+	PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
+		MSEL2CR_MSEL18_0), \
+	PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
+	PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
+	PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
+	PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
+		MSEL2CR_MSEL18_0), \
+	PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
+	PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
+	PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
+	PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
+	PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
+	PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
+	PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
+	PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
+	PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
+	PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
+	PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
+	PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
+	PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
+	PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
+	PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
+	PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
+	PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
+	PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
+	PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
+	PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
+	PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
+	PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
+	PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
+	PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
+	PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
+	PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
+	PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
+	PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
+	PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
+	PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
+		MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
+		MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
+		MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
+		MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
+		MSEL4CR_MSEL15_0), \
+	PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
+	PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
+		MSEL4CR_MSEL15_0), \
+	PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
+	PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
+		MSEL4CR_MSEL15_0), \
+	PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
+	PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
+		MSEL4CR_MSEL15_0), \
+	PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
+	PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
+		MSEL4CR_MSEL15_0),
+	PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
+	PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
+	PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
+	PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
+	PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
+	PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
+	PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
+	PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
+	PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
+	PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
+	PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
+	PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
+	PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
+	PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
+	PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
+	PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
+
+	PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
+	PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
+	PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
+	PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
+	PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
+	PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
+	PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
+	PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
+	PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
+	PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
+	PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
+	PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
+	PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
+	PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
+	PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
+	PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
+	PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
+
+	/* MSEL2 special cases */
+	PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+		MSEL2CR_MSEL12_0),
+	PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+		MSEL2CR_MSEL12_1),
+	PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+		MSEL2CR_MSEL12_0),
+	PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+		MSEL2CR_MSEL12_1),
+	PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
+		MSEL2CR_MSEL12_0),
+	PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+		MSEL2CR_MSEL9_0),
+	PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+		MSEL2CR_MSEL9_1),
+	PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+		MSEL2CR_MSEL9_0),
+	PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+		MSEL2CR_MSEL9_1),
+	PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
+		MSEL2CR_MSEL9_0),
+	PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+		MSEL2CR_MSEL6_0),
+	PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+		MSEL2CR_MSEL6_1),
+	PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+		MSEL2CR_MSEL6_0),
+	PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+		MSEL2CR_MSEL6_1),
+	PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
+		MSEL2CR_MSEL6_0),
+	PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+		MSEL2CR_MSEL3_0),
+	PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+		MSEL2CR_MSEL3_1),
+	PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+		MSEL2CR_MSEL3_0),
+	PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+		MSEL2CR_MSEL3_1),
+	PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
+		MSEL2CR_MSEL3_0),
+	PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+		MSEL2CR_MSEL0_0),
+	PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+		MSEL2CR_MSEL0_1),
+	PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+		MSEL2CR_MSEL0_0),
+	PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+		MSEL2CR_MSEL0_1),
+	PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
+		MSEL2CR_MSEL0_0),
+
+	/* MSEL3 special cases */
+	PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
+	PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
+	PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
+	PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
+	PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
+	PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
+
+	/* MSEL4 special cases */
+	PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
+	PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
+	PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
+	PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
+	PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
+	PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
+	PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
+	PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
+	PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
+
+	/* Functions with pull-ups */
+	PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
+	PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
+	PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
+	PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
+	PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
+	PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
+	PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
+	PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
+
+	PINMUX_DATA(SDHICD0_PU_MARK,  PORT251_FN1, PORT251_IN_PU),
+	PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU),
+	PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU),
+	PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
+	PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
+	PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
+	PINMUX_DATA(SDHIWP0_PU_MARK,  PORT257_FN1, PORT256_IN_PU),
+	PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
+	PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
+	PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
+	PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU),
+	PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU),
+	PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU),
+	PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU),
+	PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU),
+	PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU),
+	PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU),
+
+	PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
+		MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
+		MSEL4CR_MSEL15_1),
+
+	PINMUX_DATA(MMCD0_0_PU_MARK,
+		    PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_1_PU_MARK,
+		    PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_2_PU_MARK,
+		    PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_3_PU_MARK,
+		    PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_4_PU_MARK,
+		    PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_5_PU_MARK,
+		    PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_6_PU_MARK,
+		    PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
+	PINMUX_DATA(MMCD0_7_PU_MARK,
+		    PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
+
+	PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
+	PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
+	PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
+	PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
+	PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	GPIO_PORT_ALL(),
+
+	/* Table 25-1 (Functions 0-7) */
+	GPIO_FN(VBUS_0),
+	GPIO_FN(GPI0),
+	GPIO_FN(GPI1),
+	GPIO_FN(GPI2),
+	GPIO_FN(GPI3),
+	GPIO_FN(GPI4),
+	GPIO_FN(GPI5),
+	GPIO_FN(GPI6),
+	GPIO_FN(GPI7),
+	GPIO_FN(SCIFA7_RXD),
+	GPIO_FN(SCIFA7_CTS_),
+	GPIO_FN(GPO7), \
+	GPIO_FN(MFG0_OUT2),
+	GPIO_FN(GPO6), \
+	GPIO_FN(MFG1_OUT2),
+	GPIO_FN(GPO5), \
+	GPIO_FN(SCIFA0_SCK), \
+	GPIO_FN(FSICOSLDT3), \
+	GPIO_FN(PORT16_VIO_CKOR),
+	GPIO_FN(SCIFA0_TXD),
+	GPIO_FN(SCIFA7_TXD),
+	GPIO_FN(SCIFA7_RTS_), \
+	GPIO_FN(PORT19_VIO_CKO2),
+	GPIO_FN(GPO0),
+	GPIO_FN(GPO1),
+	GPIO_FN(GPO2), \
+	GPIO_FN(STATUS0),
+	GPIO_FN(GPO3), \
+	GPIO_FN(STATUS1),
+	GPIO_FN(GPO4), \
+	GPIO_FN(STATUS2),
+	GPIO_FN(VINT),
+	GPIO_FN(TCKON),
+	GPIO_FN(XDVFS1), \
+	GPIO_FN(PORT27_I2C_SCL2), \
+	GPIO_FN(PORT27_I2C_SCL3), \
+	GPIO_FN(MFG0_OUT1), \
+	GPIO_FN(PORT27_IROUT),
+	GPIO_FN(XDVFS2), \
+	GPIO_FN(PORT28_I2C_SDA2), \
+	GPIO_FN(PORT28_I2C_SDA3), \
+	GPIO_FN(PORT28_TPU1TO1),
+	GPIO_FN(SIM_RST), \
+	GPIO_FN(PORT29_TPU1TO1),
+	GPIO_FN(SIM_CLK), \
+	GPIO_FN(PORT30_VIO_CKOR),
+	GPIO_FN(SIM_D), \
+	GPIO_FN(PORT31_IROUT),
+	GPIO_FN(SCIFA4_TXD),
+	GPIO_FN(SCIFA4_RXD), \
+	GPIO_FN(XWUP),
+	GPIO_FN(SCIFA4_RTS_),
+	GPIO_FN(SCIFA4_CTS_),
+	GPIO_FN(FSIBOBT), \
+	GPIO_FN(FSIBIBT),
+	GPIO_FN(FSIBOLR), \
+	GPIO_FN(FSIBILR),
+	GPIO_FN(FSIBOSLD),
+	GPIO_FN(FSIBISLD),
+	GPIO_FN(VACK),
+	GPIO_FN(XTAL1L),
+	GPIO_FN(SCIFA0_RTS_), \
+	GPIO_FN(FSICOSLDT2),
+	GPIO_FN(SCIFA0_RXD),
+	GPIO_FN(SCIFA0_CTS_), \
+	GPIO_FN(FSICOSLDT1),
+	GPIO_FN(FSICOBT), \
+	GPIO_FN(FSICIBT), \
+	GPIO_FN(FSIDOBT), \
+	GPIO_FN(FSIDIBT),
+	GPIO_FN(FSICOLR), \
+	GPIO_FN(FSICILR), \
+	GPIO_FN(FSIDOLR), \
+	GPIO_FN(FSIDILR),
+	GPIO_FN(FSICOSLD), \
+	GPIO_FN(PORT47_FSICSPDIF),
+	GPIO_FN(FSICISLD), \
+	GPIO_FN(FSIDISLD),
+	GPIO_FN(FSIACK), \
+	GPIO_FN(PORT49_IRDA_OUT), \
+	GPIO_FN(PORT49_IROUT), \
+	GPIO_FN(FSIAOMC),
+	GPIO_FN(FSIAOLR), \
+	GPIO_FN(BBIF2_TSYNC2), \
+	GPIO_FN(TPU2TO2), \
+	GPIO_FN(FSIAILR),
+
+	GPIO_FN(FSIAOBT), \
+	GPIO_FN(BBIF2_TSCK2), \
+	GPIO_FN(TPU2TO3), \
+	GPIO_FN(FSIAIBT),
+	GPIO_FN(FSIAOSLD), \
+	GPIO_FN(BBIF2_TXD2),
+	GPIO_FN(FSIASPDIF), \
+	GPIO_FN(PORT53_IRDA_IN), \
+	GPIO_FN(TPU3TO3), \
+	GPIO_FN(FSIBSPDIF), \
+	GPIO_FN(PORT53_FSICSPDIF),
+	GPIO_FN(FSIBCK), \
+	GPIO_FN(PORT54_IRDA_FIRSEL), \
+	GPIO_FN(TPU3TO2), \
+	GPIO_FN(FSIBOMC), \
+	GPIO_FN(FSICCK), \
+	GPIO_FN(FSICOMC),
+	GPIO_FN(FSIAISLD), \
+	GPIO_FN(TPU0TO0),
+	GPIO_FN(A0), \
+	GPIO_FN(BS_),
+	GPIO_FN(A12), \
+	GPIO_FN(PORT58_KEYOUT7), \
+	GPIO_FN(TPU4TO2),
+	GPIO_FN(A13), \
+	GPIO_FN(PORT59_KEYOUT6), \
+	GPIO_FN(TPU0TO1),
+	GPIO_FN(A14), \
+	GPIO_FN(KEYOUT5),
+	GPIO_FN(A15), \
+	GPIO_FN(KEYOUT4),
+	GPIO_FN(A16), \
+	GPIO_FN(KEYOUT3), \
+	GPIO_FN(MSIOF0_SS1),
+	GPIO_FN(A17), \
+	GPIO_FN(KEYOUT2), \
+	GPIO_FN(MSIOF0_TSYNC),
+	GPIO_FN(A18), \
+	GPIO_FN(KEYOUT1), \
+	GPIO_FN(MSIOF0_TSCK),
+	GPIO_FN(A19), \
+	GPIO_FN(KEYOUT0), \
+	GPIO_FN(MSIOF0_TXD),
+	GPIO_FN(A20), \
+	GPIO_FN(KEYIN0), \
+	GPIO_FN(MSIOF0_RSCK),
+	GPIO_FN(A21), \
+	GPIO_FN(KEYIN1), \
+	GPIO_FN(MSIOF0_RSYNC),
+	GPIO_FN(A22), \
+	GPIO_FN(KEYIN2), \
+	GPIO_FN(MSIOF0_MCK0),
+	GPIO_FN(A23), \
+	GPIO_FN(KEYIN3), \
+	GPIO_FN(MSIOF0_MCK1),
+	GPIO_FN(A24), \
+	GPIO_FN(KEYIN4), \
+	GPIO_FN(MSIOF0_RXD),
+	GPIO_FN(A25), \
+	GPIO_FN(KEYIN5), \
+	GPIO_FN(MSIOF0_SS2),
+	GPIO_FN(A26), \
+	GPIO_FN(KEYIN6),
+	GPIO_FN(KEYIN7),
+	GPIO_FN(D0_NAF0),
+	GPIO_FN(D1_NAF1),
+	GPIO_FN(D2_NAF2),
+	GPIO_FN(D3_NAF3),
+	GPIO_FN(D4_NAF4),
+	GPIO_FN(D5_NAF5),
+	GPIO_FN(D6_NAF6),
+	GPIO_FN(D7_NAF7),
+	GPIO_FN(D8_NAF8),
+	GPIO_FN(D9_NAF9),
+	GPIO_FN(D10_NAF10),
+	GPIO_FN(D11_NAF11),
+	GPIO_FN(D12_NAF12),
+	GPIO_FN(D13_NAF13),
+	GPIO_FN(D14_NAF14),
+	GPIO_FN(D15_NAF15),
+	GPIO_FN(CS4_),
+	GPIO_FN(CS5A_), \
+	GPIO_FN(PORT91_RDWR),
+	GPIO_FN(CS5B_), \
+	GPIO_FN(FCE1_),
+	GPIO_FN(CS6B_), \
+	GPIO_FN(DACK0),
+	GPIO_FN(FCE0_), \
+	GPIO_FN(CS6A_),
+	GPIO_FN(WAIT_), \
+	GPIO_FN(DREQ0),
+	GPIO_FN(RD__FSC),
+	GPIO_FN(WE0__FWE), \
+	GPIO_FN(RDWR_FWE),
+	GPIO_FN(WE1_),
+	GPIO_FN(FRB),
+	GPIO_FN(CKO),
+	GPIO_FN(NBRSTOUT_),
+	GPIO_FN(NBRST_),
+	GPIO_FN(BBIF2_TXD),
+	GPIO_FN(BBIF2_RXD),
+	GPIO_FN(BBIF2_SYNC),
+	GPIO_FN(BBIF2_SCK),
+	GPIO_FN(SCIFA3_CTS_), \
+	GPIO_FN(MFG3_IN2),
+	GPIO_FN(SCIFA3_RXD), \
+	GPIO_FN(MFG3_IN1),
+	GPIO_FN(BBIF1_SS2), \
+	GPIO_FN(SCIFA3_RTS_), \
+	GPIO_FN(MFG3_OUT1),
+	GPIO_FN(SCIFA3_TXD),
+	GPIO_FN(HSI_RX_DATA), \
+	GPIO_FN(BBIF1_RXD),
+	GPIO_FN(HSI_TX_WAKE), \
+	GPIO_FN(BBIF1_TSCK),
+	GPIO_FN(HSI_TX_DATA), \
+	GPIO_FN(BBIF1_TSYNC),
+	GPIO_FN(HSI_TX_READY), \
+	GPIO_FN(BBIF1_TXD),
+	GPIO_FN(HSI_RX_READY), \
+	GPIO_FN(BBIF1_RSCK), \
+	GPIO_FN(PORT115_I2C_SCL2), \
+	GPIO_FN(PORT115_I2C_SCL3),
+	GPIO_FN(HSI_RX_WAKE), \
+	GPIO_FN(BBIF1_RSYNC), \
+	GPIO_FN(PORT116_I2C_SDA2), \
+	GPIO_FN(PORT116_I2C_SDA3),
+	GPIO_FN(HSI_RX_FLAG), \
+	GPIO_FN(BBIF1_SS1), \
+	GPIO_FN(BBIF1_FLOW),
+	GPIO_FN(HSI_TX_FLAG),
+	GPIO_FN(VIO_VD), \
+	GPIO_FN(PORT128_LCD2VSYN), \
+	GPIO_FN(VIO2_VD), \
+	GPIO_FN(LCD2D0),
+
+	GPIO_FN(VIO_HD), \
+	GPIO_FN(PORT129_LCD2HSYN), \
+	GPIO_FN(PORT129_LCD2CS_), \
+	GPIO_FN(VIO2_HD), \
+	GPIO_FN(LCD2D1),
+	GPIO_FN(VIO_D0), \
+	GPIO_FN(PORT130_MSIOF2_RXD), \
+	GPIO_FN(LCD2D10),
+	GPIO_FN(VIO_D1), \
+	GPIO_FN(PORT131_KEYOUT6), \
+	GPIO_FN(PORT131_MSIOF2_SS1), \
+	GPIO_FN(PORT131_KEYOUT11), \
+	GPIO_FN(LCD2D11),
+	GPIO_FN(VIO_D2), \
+	GPIO_FN(PORT132_KEYOUT7), \
+	GPIO_FN(PORT132_MSIOF2_SS2), \
+	GPIO_FN(PORT132_KEYOUT10), \
+	GPIO_FN(LCD2D12),
+	GPIO_FN(VIO_D3), \
+	GPIO_FN(MSIOF2_TSYNC), \
+	GPIO_FN(LCD2D13),
+	GPIO_FN(VIO_D4), \
+	GPIO_FN(MSIOF2_TXD), \
+	GPIO_FN(LCD2D14),
+	GPIO_FN(VIO_D5), \
+	GPIO_FN(MSIOF2_TSCK), \
+	GPIO_FN(LCD2D15),
+	GPIO_FN(VIO_D6), \
+	GPIO_FN(PORT136_KEYOUT8), \
+	GPIO_FN(LCD2D16),
+	GPIO_FN(VIO_D7), \
+	GPIO_FN(PORT137_KEYOUT9), \
+	GPIO_FN(LCD2D17),
+	GPIO_FN(VIO_D8), \
+	GPIO_FN(PORT138_KEYOUT8), \
+	GPIO_FN(VIO2_D0), \
+	GPIO_FN(LCD2D6),
+	GPIO_FN(VIO_D9), \
+	GPIO_FN(PORT139_KEYOUT9), \
+	GPIO_FN(VIO2_D1), \
+	GPIO_FN(LCD2D7),
+	GPIO_FN(VIO_D10), \
+	GPIO_FN(TPU0TO2), \
+	GPIO_FN(VIO2_D2), \
+	GPIO_FN(LCD2D8),
+	GPIO_FN(VIO_D11), \
+	GPIO_FN(TPU0TO3), \
+	GPIO_FN(VIO2_D3), \
+	GPIO_FN(LCD2D9),
+	GPIO_FN(VIO_D12), \
+	GPIO_FN(PORT142_KEYOUT10), \
+	GPIO_FN(VIO2_D4), \
+	GPIO_FN(LCD2D2),
+	GPIO_FN(VIO_D13), \
+	GPIO_FN(PORT143_KEYOUT11), \
+	GPIO_FN(PORT143_KEYOUT6), \
+	GPIO_FN(VIO2_D5), \
+	GPIO_FN(LCD2D3),
+	GPIO_FN(VIO_D14), \
+	GPIO_FN(PORT144_KEYOUT7), \
+	GPIO_FN(VIO2_D6), \
+	GPIO_FN(LCD2D4),
+	GPIO_FN(VIO_D15), \
+	GPIO_FN(TPU1TO3), \
+	GPIO_FN(PORT145_LCD2DISP), \
+	GPIO_FN(PORT145_LCD2RS), \
+	GPIO_FN(VIO2_D7), \
+	GPIO_FN(LCD2D5),
+	GPIO_FN(VIO_CLK), \
+	GPIO_FN(LCD2DCK), \
+	GPIO_FN(PORT146_LCD2WR_), \
+	GPIO_FN(VIO2_CLK), \
+	GPIO_FN(LCD2D18),
+	GPIO_FN(VIO_FIELD), \
+	GPIO_FN(LCD2RD_), \
+	GPIO_FN(VIO2_FIELD), \
+	GPIO_FN(LCD2D19),
+	GPIO_FN(VIO_CKO),
+	GPIO_FN(A27), \
+	GPIO_FN(PORT149_RDWR), \
+	GPIO_FN(MFG0_IN1), \
+	GPIO_FN(PORT149_KEYOUT9),
+	GPIO_FN(MFG0_IN2),
+	GPIO_FN(TS_SPSYNC3), \
+	GPIO_FN(MSIOF2_RSCK),
+	GPIO_FN(TS_SDAT3), \
+	GPIO_FN(MSIOF2_RSYNC),
+	GPIO_FN(TPU1TO2), \
+	GPIO_FN(TS_SDEN3), \
+	GPIO_FN(PORT153_MSIOF2_SS1),
+	GPIO_FN(SCIFA2_TXD1), \
+	GPIO_FN(MSIOF2_MCK0),
+	GPIO_FN(SCIFA2_RXD1), \
+	GPIO_FN(MSIOF2_MCK1),
+	GPIO_FN(SCIFA2_RTS1_), \
+	GPIO_FN(PORT156_MSIOF2_SS2),
+	GPIO_FN(SCIFA2_CTS1_), \
+	GPIO_FN(PORT157_MSIOF2_RXD),
+	GPIO_FN(DINT_), \
+	GPIO_FN(SCIFA2_SCK1), \
+	GPIO_FN(TS_SCK3),
+	GPIO_FN(PORT159_SCIFB_SCK), \
+	GPIO_FN(PORT159_SCIFA5_SCK), \
+	GPIO_FN(NMI),
+	GPIO_FN(PORT160_SCIFB_TXD), \
+	GPIO_FN(PORT160_SCIFA5_TXD),
+	GPIO_FN(PORT161_SCIFB_CTS_), \
+	GPIO_FN(PORT161_SCIFA5_CTS_),
+	GPIO_FN(PORT162_SCIFB_RXD), \
+	GPIO_FN(PORT162_SCIFA5_RXD),
+	GPIO_FN(PORT163_SCIFB_RTS_), \
+	GPIO_FN(PORT163_SCIFA5_RTS_), \
+	GPIO_FN(TPU3TO0),
+	GPIO_FN(LCDD0),
+	GPIO_FN(LCDD1), \
+	GPIO_FN(PORT193_SCIFA5_CTS_), \
+	GPIO_FN(BBIF2_TSYNC1),
+	GPIO_FN(LCDD2), \
+	GPIO_FN(PORT194_SCIFA5_RTS_), \
+	GPIO_FN(BBIF2_TSCK1),
+	GPIO_FN(LCDD3), \
+	GPIO_FN(PORT195_SCIFA5_RXD), \
+	GPIO_FN(BBIF2_TXD1),
+	GPIO_FN(LCDD4), \
+	GPIO_FN(PORT196_SCIFA5_TXD),
+	GPIO_FN(LCDD5), \
+	GPIO_FN(PORT197_SCIFA5_SCK), \
+	GPIO_FN(MFG2_OUT2), \
+	GPIO_FN(TPU2TO1),
+	GPIO_FN(LCDD6),
+	GPIO_FN(LCDD7), \
+	GPIO_FN(TPU4TO1), \
+	GPIO_FN(MFG4_OUT2),
+	GPIO_FN(LCDD8), \
+	GPIO_FN(D16),
+	GPIO_FN(LCDD9), \
+	GPIO_FN(D17),
+	GPIO_FN(LCDD10), \
+	GPIO_FN(D18),
+	GPIO_FN(LCDD11), \
+	GPIO_FN(D19),
+	GPIO_FN(LCDD12), \
+	GPIO_FN(D20),
+	GPIO_FN(LCDD13), \
+	GPIO_FN(D21),
+	GPIO_FN(LCDD14), \
+	GPIO_FN(D22),
+	GPIO_FN(LCDD15), \
+	GPIO_FN(PORT207_MSIOF0L_SS1), \
+	GPIO_FN(D23),
+	GPIO_FN(LCDD16), \
+	GPIO_FN(PORT208_MSIOF0L_SS2), \
+	GPIO_FN(D24),
+	GPIO_FN(LCDD17), \
+	GPIO_FN(D25),
+	GPIO_FN(LCDD18), \
+	GPIO_FN(DREQ2), \
+	GPIO_FN(PORT210_MSIOF0L_SS1), \
+	GPIO_FN(D26),
+	GPIO_FN(LCDD19), \
+	GPIO_FN(PORT211_MSIOF0L_SS2), \
+	GPIO_FN(D27),
+	GPIO_FN(LCDD20), \
+	GPIO_FN(TS_SPSYNC1), \
+	GPIO_FN(MSIOF0L_MCK0), \
+	GPIO_FN(D28),
+	GPIO_FN(LCDD21), \
+	GPIO_FN(TS_SDAT1), \
+	GPIO_FN(MSIOF0L_MCK1), \
+	GPIO_FN(D29),
+	GPIO_FN(LCDD22), \
+	GPIO_FN(TS_SDEN1), \
+	GPIO_FN(MSIOF0L_RSCK), \
+	GPIO_FN(D30),
+	GPIO_FN(LCDD23), \
+	GPIO_FN(TS_SCK1), \
+	GPIO_FN(MSIOF0L_RSYNC), \
+	GPIO_FN(D31),
+	GPIO_FN(LCDDCK), \
+	GPIO_FN(LCDWR_),
+	GPIO_FN(LCDRD_), \
+	GPIO_FN(DACK2), \
+	GPIO_FN(PORT217_LCD2RS), \
+	GPIO_FN(MSIOF0L_TSYNC), \
+	GPIO_FN(VIO2_FIELD3), \
+	GPIO_FN(PORT217_LCD2DISP),
+	GPIO_FN(LCDHSYN), \
+	GPIO_FN(LCDCS_), \
+	GPIO_FN(LCDCS2_), \
+	GPIO_FN(DACK3), \
+	GPIO_FN(PORT218_VIO_CKOR),
+	GPIO_FN(LCDDISP), \
+	GPIO_FN(LCDRS), \
+	GPIO_FN(PORT219_LCD2WR_), \
+	GPIO_FN(DREQ3), \
+	GPIO_FN(MSIOF0L_TSCK), \
+	GPIO_FN(VIO2_CLK3), \
+	GPIO_FN(LCD2DCK_2),
+	GPIO_FN(LCDVSYN), \
+	GPIO_FN(LCDVSYN2),
+	GPIO_FN(LCDLCLK), \
+	GPIO_FN(DREQ1), \
+	GPIO_FN(PORT221_LCD2CS_), \
+	GPIO_FN(PWEN), \
+	GPIO_FN(MSIOF0L_RXD), \
+	GPIO_FN(VIO2_HD3), \
+	GPIO_FN(PORT221_LCD2HSYN),
+	GPIO_FN(LCDDON), \
+	GPIO_FN(LCDDON2), \
+	GPIO_FN(DACK1), \
+	GPIO_FN(OVCN), \
+	GPIO_FN(MSIOF0L_TXD), \
+	GPIO_FN(VIO2_VD3), \
+	GPIO_FN(PORT222_LCD2VSYN),
+
+	GPIO_FN(SCIFA1_TXD), \
+	GPIO_FN(OVCN2),
+	GPIO_FN(EXTLP), \
+	GPIO_FN(SCIFA1_SCK), \
+	GPIO_FN(PORT226_VIO_CKO2),
+	GPIO_FN(SCIFA1_RTS_), \
+	GPIO_FN(IDIN),
+	GPIO_FN(SCIFA1_RXD),
+	GPIO_FN(SCIFA1_CTS_), \
+	GPIO_FN(MFG1_IN1),
+	GPIO_FN(MSIOF1_TXD), \
+	GPIO_FN(SCIFA2_TXD2),
+	GPIO_FN(MSIOF1_TSYNC), \
+	GPIO_FN(SCIFA2_CTS2_),
+	GPIO_FN(MSIOF1_TSCK), \
+	GPIO_FN(SCIFA2_SCK2),
+	GPIO_FN(MSIOF1_RXD), \
+	GPIO_FN(SCIFA2_RXD2),
+	GPIO_FN(MSIOF1_RSCK), \
+	GPIO_FN(SCIFA2_RTS2_), \
+	GPIO_FN(VIO2_CLK2), \
+	GPIO_FN(LCD2D20),
+	GPIO_FN(MSIOF1_RSYNC), \
+	GPIO_FN(MFG1_IN2), \
+	GPIO_FN(VIO2_VD2), \
+	GPIO_FN(LCD2D21),
+	GPIO_FN(MSIOF1_MCK0), \
+	GPIO_FN(PORT236_I2C_SDA2),
+	GPIO_FN(MSIOF1_MCK1), \
+	GPIO_FN(PORT237_I2C_SCL2),
+	GPIO_FN(MSIOF1_SS1), \
+	GPIO_FN(VIO2_FIELD2), \
+	GPIO_FN(LCD2D22),
+	GPIO_FN(MSIOF1_SS2), \
+	GPIO_FN(VIO2_HD2), \
+	GPIO_FN(LCD2D23),
+	GPIO_FN(SCIFA6_TXD),
+	GPIO_FN(PORT241_IRDA_OUT), \
+	GPIO_FN(PORT241_IROUT), \
+	GPIO_FN(MFG4_OUT1), \
+	GPIO_FN(TPU4TO0),
+	GPIO_FN(PORT242_IRDA_IN), \
+	GPIO_FN(MFG4_IN2),
+	GPIO_FN(PORT243_IRDA_FIRSEL), \
+	GPIO_FN(PORT243_VIO_CKO2),
+	GPIO_FN(PORT244_SCIFA5_CTS_), \
+	GPIO_FN(MFG2_IN1), \
+	GPIO_FN(PORT244_SCIFB_CTS_), \
+	GPIO_FN(MSIOF2R_RXD),
+	GPIO_FN(PORT245_SCIFA5_RTS_), \
+	GPIO_FN(MFG2_IN2), \
+	GPIO_FN(PORT245_SCIFB_RTS_), \
+	GPIO_FN(MSIOF2R_TXD),
+	GPIO_FN(PORT246_SCIFA5_RXD), \
+	GPIO_FN(MFG1_OUT1), \
+	GPIO_FN(PORT246_SCIFB_RXD), \
+	GPIO_FN(TPU1TO0),
+	GPIO_FN(PORT247_SCIFA5_TXD), \
+	GPIO_FN(MFG3_OUT2), \
+	GPIO_FN(PORT247_SCIFB_TXD), \
+	GPIO_FN(TPU3TO1),
+	GPIO_FN(PORT248_SCIFA5_SCK), \
+	GPIO_FN(MFG2_OUT1), \
+	GPIO_FN(PORT248_SCIFB_SCK), \
+	GPIO_FN(TPU2TO0), \
+	GPIO_FN(PORT248_I2C_SCL3), \
+	GPIO_FN(MSIOF2R_TSCK),
+	GPIO_FN(PORT249_IROUT), \
+	GPIO_FN(MFG4_IN1), \
+	GPIO_FN(PORT249_I2C_SDA3), \
+	GPIO_FN(MSIOF2R_TSYNC),
+	GPIO_FN(SDHICLK0),
+	GPIO_FN(SDHICD0),
+	GPIO_FN(SDHID0_0),
+	GPIO_FN(SDHID0_1),
+	GPIO_FN(SDHID0_2),
+	GPIO_FN(SDHID0_3),
+	GPIO_FN(SDHICMD0),
+	GPIO_FN(SDHIWP0),
+	GPIO_FN(SDHICLK1),
+	GPIO_FN(SDHID1_0), \
+	GPIO_FN(TS_SPSYNC2),
+	GPIO_FN(SDHID1_1), \
+	GPIO_FN(TS_SDAT2),
+	GPIO_FN(SDHID1_2), \
+	GPIO_FN(TS_SDEN2),
+	GPIO_FN(SDHID1_3), \
+	GPIO_FN(TS_SCK2),
+	GPIO_FN(SDHICMD1),
+	GPIO_FN(SDHICLK2),
+	GPIO_FN(SDHID2_0), \
+	GPIO_FN(TS_SPSYNC4),
+	GPIO_FN(SDHID2_1), \
+	GPIO_FN(TS_SDAT4),
+	GPIO_FN(SDHID2_2), \
+	GPIO_FN(TS_SDEN4),
+	GPIO_FN(SDHID2_3), \
+	GPIO_FN(TS_SCK4),
+	GPIO_FN(SDHICMD2),
+	GPIO_FN(MMCCLK0),
+	GPIO_FN(MMCD0_0),
+	GPIO_FN(MMCD0_1),
+	GPIO_FN(MMCD0_2),
+	GPIO_FN(MMCD0_3),
+	GPIO_FN(MMCD0_4), \
+	GPIO_FN(TS_SPSYNC5),
+	GPIO_FN(MMCD0_5), \
+	GPIO_FN(TS_SDAT5),
+	GPIO_FN(MMCD0_6), \
+	GPIO_FN(TS_SDEN5),
+	GPIO_FN(MMCD0_7), \
+	GPIO_FN(TS_SCK5),
+	GPIO_FN(MMCCMD0),
+	GPIO_FN(RESETOUTS_), \
+	GPIO_FN(EXTAL2OUT),
+	GPIO_FN(MCP_WAIT__MCP_FRB),
+	GPIO_FN(MCP_CKO), \
+	GPIO_FN(MMCCLK1),
+	GPIO_FN(MCP_D15_MCP_NAF15),
+	GPIO_FN(MCP_D14_MCP_NAF14),
+	GPIO_FN(MCP_D13_MCP_NAF13),
+	GPIO_FN(MCP_D12_MCP_NAF12),
+	GPIO_FN(MCP_D11_MCP_NAF11),
+	GPIO_FN(MCP_D10_MCP_NAF10),
+	GPIO_FN(MCP_D9_MCP_NAF9),
+	GPIO_FN(MCP_D8_MCP_NAF8), \
+	GPIO_FN(MMCCMD1),
+	GPIO_FN(MCP_D7_MCP_NAF7), \
+	GPIO_FN(MMCD1_7),
+
+	GPIO_FN(MCP_D6_MCP_NAF6), \
+	GPIO_FN(MMCD1_6),
+	GPIO_FN(MCP_D5_MCP_NAF5), \
+	GPIO_FN(MMCD1_5),
+	GPIO_FN(MCP_D4_MCP_NAF4), \
+	GPIO_FN(MMCD1_4),
+	GPIO_FN(MCP_D3_MCP_NAF3), \
+	GPIO_FN(MMCD1_3),
+	GPIO_FN(MCP_D2_MCP_NAF2), \
+	GPIO_FN(MMCD1_2),
+	GPIO_FN(MCP_D1_MCP_NAF1), \
+	GPIO_FN(MMCD1_1),
+	GPIO_FN(MCP_D0_MCP_NAF0), \
+	GPIO_FN(MMCD1_0),
+	GPIO_FN(MCP_NBRSTOUT_),
+	GPIO_FN(MCP_WE0__MCP_FWE), \
+	GPIO_FN(MCP_RDWR_MCP_FWE),
+
+	/* MSEL2 special cases */
+	GPIO_FN(TSIF2_TS_XX1),
+	GPIO_FN(TSIF2_TS_XX2),
+	GPIO_FN(TSIF2_TS_XX3),
+	GPIO_FN(TSIF2_TS_XX4),
+	GPIO_FN(TSIF2_TS_XX5),
+	GPIO_FN(TSIF1_TS_XX1),
+	GPIO_FN(TSIF1_TS_XX2),
+	GPIO_FN(TSIF1_TS_XX3),
+	GPIO_FN(TSIF1_TS_XX4),
+	GPIO_FN(TSIF1_TS_XX5),
+	GPIO_FN(TSIF0_TS_XX1),
+	GPIO_FN(TSIF0_TS_XX2),
+	GPIO_FN(TSIF0_TS_XX3),
+	GPIO_FN(TSIF0_TS_XX4),
+	GPIO_FN(TSIF0_TS_XX5),
+	GPIO_FN(MST1_TS_XX1),
+	GPIO_FN(MST1_TS_XX2),
+	GPIO_FN(MST1_TS_XX3),
+	GPIO_FN(MST1_TS_XX4),
+	GPIO_FN(MST1_TS_XX5),
+	GPIO_FN(MST0_TS_XX1),
+	GPIO_FN(MST0_TS_XX2),
+	GPIO_FN(MST0_TS_XX3),
+	GPIO_FN(MST0_TS_XX4),
+	GPIO_FN(MST0_TS_XX5),
+
+	/* MSEL3 special cases */
+	GPIO_FN(SDHI0_VCCQ_MC0_ON),
+	GPIO_FN(SDHI0_VCCQ_MC0_OFF),
+	GPIO_FN(DEBUG_MON_VIO),
+	GPIO_FN(DEBUG_MON_LCDD),
+	GPIO_FN(LCDC_LCDC0),
+	GPIO_FN(LCDC_LCDC1),
+
+	/* MSEL4 special cases */
+	GPIO_FN(IRQ9_MEM_INT),
+	GPIO_FN(IRQ9_MCP_INT),
+	GPIO_FN(A11),
+	GPIO_FN(KEYOUT8),
+	GPIO_FN(TPU4TO3),
+	GPIO_FN(RESETA_N_PU_ON),
+	GPIO_FN(RESETA_N_PU_OFF),
+	GPIO_FN(EDBGREQ_PD),
+	GPIO_FN(EDBGREQ_PU),
+
+	/* Functions with pull-ups */
+	GPIO_FN(KEYIN0_PU),
+	GPIO_FN(KEYIN1_PU),
+	GPIO_FN(KEYIN2_PU),
+	GPIO_FN(KEYIN3_PU),
+	GPIO_FN(KEYIN4_PU),
+	GPIO_FN(KEYIN5_PU),
+	GPIO_FN(KEYIN6_PU),
+	GPIO_FN(KEYIN7_PU),
+	GPIO_FN(SDHICD0_PU),
+	GPIO_FN(SDHID0_0_PU),
+	GPIO_FN(SDHID0_1_PU),
+	GPIO_FN(SDHID0_2_PU),
+	GPIO_FN(SDHID0_3_PU),
+	GPIO_FN(SDHICMD0_PU),
+	GPIO_FN(SDHIWP0_PU),
+	GPIO_FN(SDHID1_0_PU),
+	GPIO_FN(SDHID1_1_PU),
+	GPIO_FN(SDHID1_2_PU),
+	GPIO_FN(SDHID1_3_PU),
+	GPIO_FN(SDHICMD1_PU),
+	GPIO_FN(SDHID2_0_PU),
+	GPIO_FN(SDHID2_1_PU),
+	GPIO_FN(SDHID2_2_PU),
+	GPIO_FN(SDHID2_3_PU),
+	GPIO_FN(SDHICMD2_PU),
+	GPIO_FN(MMCCMD0_PU),
+	GPIO_FN(MMCCMD1_PU),
+	GPIO_FN(MMCD0_0_PU),
+	GPIO_FN(MMCD0_1_PU),
+	GPIO_FN(MMCD0_2_PU),
+	GPIO_FN(MMCD0_3_PU),
+	GPIO_FN(MMCD0_4_PU),
+	GPIO_FN(MMCD0_5_PU),
+	GPIO_FN(MMCD0_6_PU),
+	GPIO_FN(MMCD0_7_PU),
+	GPIO_FN(FSIACK_PU),
+	GPIO_FN(FSIAILR_PU),
+	GPIO_FN(FSIAIBT_PU),
+	GPIO_FN(FSIAISLD_PU),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	PORTCR(0, 0xe6050000), /* PORT0CR */
+	PORTCR(1, 0xe6050001), /* PORT1CR */
+	PORTCR(2, 0xe6050002), /* PORT2CR */
+	PORTCR(3, 0xe6050003), /* PORT3CR */
+	PORTCR(4, 0xe6050004), /* PORT4CR */
+	PORTCR(5, 0xe6050005), /* PORT5CR */
+	PORTCR(6, 0xe6050006), /* PORT6CR */
+	PORTCR(7, 0xe6050007), /* PORT7CR */
+	PORTCR(8, 0xe6050008), /* PORT8CR */
+	PORTCR(9, 0xe6050009), /* PORT9CR */
+
+	PORTCR(10, 0xe605000a), /* PORT10CR */
+	PORTCR(11, 0xe605000b), /* PORT11CR */
+	PORTCR(12, 0xe605000c), /* PORT12CR */
+	PORTCR(13, 0xe605000d), /* PORT13CR */
+	PORTCR(14, 0xe605000e), /* PORT14CR */
+	PORTCR(15, 0xe605000f), /* PORT15CR */
+	PORTCR(16, 0xe6050010), /* PORT16CR */
+	PORTCR(17, 0xe6050011), /* PORT17CR */
+	PORTCR(18, 0xe6050012), /* PORT18CR */
+	PORTCR(19, 0xe6050013), /* PORT19CR */
+
+	PORTCR(20, 0xe6050014), /* PORT20CR */
+	PORTCR(21, 0xe6050015), /* PORT21CR */
+	PORTCR(22, 0xe6050016), /* PORT22CR */
+	PORTCR(23, 0xe6050017), /* PORT23CR */
+	PORTCR(24, 0xe6050018), /* PORT24CR */
+	PORTCR(25, 0xe6050019), /* PORT25CR */
+	PORTCR(26, 0xe605001a), /* PORT26CR */
+	PORTCR(27, 0xe605001b), /* PORT27CR */
+	PORTCR(28, 0xe605001c), /* PORT28CR */
+	PORTCR(29, 0xe605001d), /* PORT29CR */
+
+	PORTCR(30, 0xe605001e), /* PORT30CR */
+	PORTCR(31, 0xe605001f), /* PORT31CR */
+	PORTCR(32, 0xe6051020), /* PORT32CR */
+	PORTCR(33, 0xe6051021), /* PORT33CR */
+	PORTCR(34, 0xe6051022), /* PORT34CR */
+	PORTCR(35, 0xe6051023), /* PORT35CR */
+	PORTCR(36, 0xe6051024), /* PORT36CR */
+	PORTCR(37, 0xe6051025), /* PORT37CR */
+	PORTCR(38, 0xe6051026), /* PORT38CR */
+	PORTCR(39, 0xe6051027), /* PORT39CR */
+
+	PORTCR(40, 0xe6051028), /* PORT40CR */
+	PORTCR(41, 0xe6051029), /* PORT41CR */
+	PORTCR(42, 0xe605102a), /* PORT42CR */
+	PORTCR(43, 0xe605102b), /* PORT43CR */
+	PORTCR(44, 0xe605102c), /* PORT44CR */
+	PORTCR(45, 0xe605102d), /* PORT45CR */
+	PORTCR(46, 0xe605102e), /* PORT46CR */
+	PORTCR(47, 0xe605102f), /* PORT47CR */
+	PORTCR(48, 0xe6051030), /* PORT48CR */
+	PORTCR(49, 0xe6051031), /* PORT49CR */
+
+	PORTCR(50, 0xe6051032), /* PORT50CR */
+	PORTCR(51, 0xe6051033), /* PORT51CR */
+	PORTCR(52, 0xe6051034), /* PORT52CR */
+	PORTCR(53, 0xe6051035), /* PORT53CR */
+	PORTCR(54, 0xe6051036), /* PORT54CR */
+	PORTCR(55, 0xe6051037), /* PORT55CR */
+	PORTCR(56, 0xe6051038), /* PORT56CR */
+	PORTCR(57, 0xe6051039), /* PORT57CR */
+	PORTCR(58, 0xe605103a), /* PORT58CR */
+	PORTCR(59, 0xe605103b), /* PORT59CR */
+
+	PORTCR(60, 0xe605103c), /* PORT60CR */
+	PORTCR(61, 0xe605103d), /* PORT61CR */
+	PORTCR(62, 0xe605103e), /* PORT62CR */
+	PORTCR(63, 0xe605103f), /* PORT63CR */
+	PORTCR(64, 0xe6051040), /* PORT64CR */
+	PORTCR(65, 0xe6051041), /* PORT65CR */
+	PORTCR(66, 0xe6051042), /* PORT66CR */
+	PORTCR(67, 0xe6051043), /* PORT67CR */
+	PORTCR(68, 0xe6051044), /* PORT68CR */
+	PORTCR(69, 0xe6051045), /* PORT69CR */
+
+	PORTCR(70, 0xe6051046), /* PORT70CR */
+	PORTCR(71, 0xe6051047), /* PORT71CR */
+	PORTCR(72, 0xe6051048), /* PORT72CR */
+	PORTCR(73, 0xe6051049), /* PORT73CR */
+	PORTCR(74, 0xe605104a), /* PORT74CR */
+	PORTCR(75, 0xe605104b), /* PORT75CR */
+	PORTCR(76, 0xe605104c), /* PORT76CR */
+	PORTCR(77, 0xe605104d), /* PORT77CR */
+	PORTCR(78, 0xe605104e), /* PORT78CR */
+	PORTCR(79, 0xe605104f), /* PORT79CR */
+
+	PORTCR(80, 0xe6051050), /* PORT80CR */
+	PORTCR(81, 0xe6051051), /* PORT81CR */
+	PORTCR(82, 0xe6051052), /* PORT82CR */
+	PORTCR(83, 0xe6051053), /* PORT83CR */
+	PORTCR(84, 0xe6051054), /* PORT84CR */
+	PORTCR(85, 0xe6051055), /* PORT85CR */
+	PORTCR(86, 0xe6051056), /* PORT86CR */
+	PORTCR(87, 0xe6051057), /* PORT87CR */
+	PORTCR(88, 0xe6051058), /* PORT88CR */
+	PORTCR(89, 0xe6051059), /* PORT89CR */
+
+	PORTCR(90, 0xe605105a), /* PORT90CR */
+	PORTCR(91, 0xe605105b), /* PORT91CR */
+	PORTCR(92, 0xe605105c), /* PORT92CR */
+	PORTCR(93, 0xe605105d), /* PORT93CR */
+	PORTCR(94, 0xe605105e), /* PORT94CR */
+	PORTCR(95, 0xe605105f), /* PORT95CR */
+	PORTCR(96, 0xe6052060), /* PORT96CR */
+	PORTCR(97, 0xe6052061), /* PORT97CR */
+	PORTCR(98, 0xe6052062), /* PORT98CR */
+	PORTCR(99, 0xe6052063), /* PORT99CR */
+
+	PORTCR(100, 0xe6052064), /* PORT100CR */
+	PORTCR(101, 0xe6052065), /* PORT101CR */
+	PORTCR(102, 0xe6052066), /* PORT102CR */
+	PORTCR(103, 0xe6052067), /* PORT103CR */
+	PORTCR(104, 0xe6052068), /* PORT104CR */
+	PORTCR(105, 0xe6052069), /* PORT105CR */
+	PORTCR(106, 0xe605206a), /* PORT106CR */
+	PORTCR(107, 0xe605206b), /* PORT107CR */
+	PORTCR(108, 0xe605206c), /* PORT108CR */
+	PORTCR(109, 0xe605206d), /* PORT109CR */
+
+	PORTCR(110, 0xe605206e), /* PORT110CR */
+	PORTCR(111, 0xe605206f), /* PORT111CR */
+	PORTCR(112, 0xe6052070), /* PORT112CR */
+	PORTCR(113, 0xe6052071), /* PORT113CR */
+	PORTCR(114, 0xe6052072), /* PORT114CR */
+	PORTCR(115, 0xe6052073), /* PORT115CR */
+	PORTCR(116, 0xe6052074), /* PORT116CR */
+	PORTCR(117, 0xe6052075), /* PORT117CR */
+	PORTCR(118, 0xe6052076), /* PORT118CR */
+
+	PORTCR(128, 0xe6052080), /* PORT128CR */
+	PORTCR(129, 0xe6052081), /* PORT129CR */
+
+	PORTCR(130, 0xe6052082), /* PORT130CR */
+	PORTCR(131, 0xe6052083), /* PORT131CR */
+	PORTCR(132, 0xe6052084), /* PORT132CR */
+	PORTCR(133, 0xe6052085), /* PORT133CR */
+	PORTCR(134, 0xe6052086), /* PORT134CR */
+	PORTCR(135, 0xe6052087), /* PORT135CR */
+	PORTCR(136, 0xe6052088), /* PORT136CR */
+	PORTCR(137, 0xe6052089), /* PORT137CR */
+	PORTCR(138, 0xe605208a), /* PORT138CR */
+	PORTCR(139, 0xe605208b), /* PORT139CR */
+
+	PORTCR(140, 0xe605208c), /* PORT140CR */
+	PORTCR(141, 0xe605208d), /* PORT141CR */
+	PORTCR(142, 0xe605208e), /* PORT142CR */
+	PORTCR(143, 0xe605208f), /* PORT143CR */
+	PORTCR(144, 0xe6052090), /* PORT144CR */
+	PORTCR(145, 0xe6052091), /* PORT145CR */
+	PORTCR(146, 0xe6052092), /* PORT146CR */
+	PORTCR(147, 0xe6052093), /* PORT147CR */
+	PORTCR(148, 0xe6052094), /* PORT148CR */
+	PORTCR(149, 0xe6052095), /* PORT149CR */
+
+	PORTCR(150, 0xe6052096), /* PORT150CR */
+	PORTCR(151, 0xe6052097), /* PORT151CR */
+	PORTCR(152, 0xe6052098), /* PORT152CR */
+	PORTCR(153, 0xe6052099), /* PORT153CR */
+	PORTCR(154, 0xe605209a), /* PORT154CR */
+	PORTCR(155, 0xe605209b), /* PORT155CR */
+	PORTCR(156, 0xe605209c), /* PORT156CR */
+	PORTCR(157, 0xe605209d), /* PORT157CR */
+	PORTCR(158, 0xe605209e), /* PORT158CR */
+	PORTCR(159, 0xe605209f), /* PORT159CR */
+
+	PORTCR(160, 0xe60520a0), /* PORT160CR */
+	PORTCR(161, 0xe60520a1), /* PORT161CR */
+	PORTCR(162, 0xe60520a2), /* PORT162CR */
+	PORTCR(163, 0xe60520a3), /* PORT163CR */
+	PORTCR(164, 0xe60520a4), /* PORT164CR */
+
+	PORTCR(192, 0xe60520c0), /* PORT192CR */
+	PORTCR(193, 0xe60520c1), /* PORT193CR */
+	PORTCR(194, 0xe60520c2), /* PORT194CR */
+	PORTCR(195, 0xe60520c3), /* PORT195CR */
+	PORTCR(196, 0xe60520c4), /* PORT196CR */
+	PORTCR(197, 0xe60520c5), /* PORT197CR */
+	PORTCR(198, 0xe60520c6), /* PORT198CR */
+	PORTCR(199, 0xe60520c7), /* PORT199CR */
+
+	PORTCR(200, 0xe60520c8), /* PORT200CR */
+	PORTCR(201, 0xe60520c9), /* PORT201CR */
+	PORTCR(202, 0xe60520ca), /* PORT202CR */
+	PORTCR(203, 0xe60520cb), /* PORT203CR */
+	PORTCR(204, 0xe60520cc), /* PORT204CR */
+	PORTCR(205, 0xe60520cd), /* PORT205CR */
+	PORTCR(206, 0xe60520ce), /* PORT206CR */
+	PORTCR(207, 0xe60520cf), /* PORT207CR */
+	PORTCR(208, 0xe60520d0), /* PORT208CR */
+	PORTCR(209, 0xe60520d1), /* PORT209CR */
+
+	PORTCR(210, 0xe60520d2), /* PORT210CR */
+	PORTCR(211, 0xe60520d3), /* PORT211CR */
+	PORTCR(212, 0xe60520d4), /* PORT212CR */
+	PORTCR(213, 0xe60520d5), /* PORT213CR */
+	PORTCR(214, 0xe60520d6), /* PORT214CR */
+	PORTCR(215, 0xe60520d7), /* PORT215CR */
+	PORTCR(216, 0xe60520d8), /* PORT216CR */
+	PORTCR(217, 0xe60520d9), /* PORT217CR */
+	PORTCR(218, 0xe60520da), /* PORT218CR */
+	PORTCR(219, 0xe60520db), /* PORT219CR */
+
+	PORTCR(220, 0xe60520dc), /* PORT220CR */
+	PORTCR(221, 0xe60520dd), /* PORT221CR */
+	PORTCR(222, 0xe60520de), /* PORT222CR */
+	PORTCR(223, 0xe60520df), /* PORT223CR */
+	PORTCR(224, 0xe60530e0), /* PORT224CR */
+	PORTCR(225, 0xe60530e1), /* PORT225CR */
+	PORTCR(226, 0xe60530e2), /* PORT226CR */
+	PORTCR(227, 0xe60530e3), /* PORT227CR */
+	PORTCR(228, 0xe60530e4), /* PORT228CR */
+	PORTCR(229, 0xe60530e5), /* PORT229CR */
+
+	PORTCR(230, 0xe60530e6), /* PORT230CR */
+	PORTCR(231, 0xe60530e7), /* PORT231CR */
+	PORTCR(232, 0xe60530e8), /* PORT232CR */
+	PORTCR(233, 0xe60530e9), /* PORT233CR */
+	PORTCR(234, 0xe60530ea), /* PORT234CR */
+	PORTCR(235, 0xe60530eb), /* PORT235CR */
+	PORTCR(236, 0xe60530ec), /* PORT236CR */
+	PORTCR(237, 0xe60530ed), /* PORT237CR */
+	PORTCR(238, 0xe60530ee), /* PORT238CR */
+	PORTCR(239, 0xe60530ef), /* PORT239CR */
+
+	PORTCR(240, 0xe60530f0), /* PORT240CR */
+	PORTCR(241, 0xe60530f1), /* PORT241CR */
+	PORTCR(242, 0xe60530f2), /* PORT242CR */
+	PORTCR(243, 0xe60530f3), /* PORT243CR */
+	PORTCR(244, 0xe60530f4), /* PORT244CR */
+	PORTCR(245, 0xe60530f5), /* PORT245CR */
+	PORTCR(246, 0xe60530f6), /* PORT246CR */
+	PORTCR(247, 0xe60530f7), /* PORT247CR */
+	PORTCR(248, 0xe60530f8), /* PORT248CR */
+	PORTCR(249, 0xe60530f9), /* PORT249CR */
+
+	PORTCR(250, 0xe60530fa), /* PORT250CR */
+	PORTCR(251, 0xe60530fb), /* PORT251CR */
+	PORTCR(252, 0xe60530fc), /* PORT252CR */
+	PORTCR(253, 0xe60530fd), /* PORT253CR */
+	PORTCR(254, 0xe60530fe), /* PORT254CR */
+	PORTCR(255, 0xe60530ff), /* PORT255CR */
+	PORTCR(256, 0xe6053100), /* PORT256CR */
+	PORTCR(257, 0xe6053101), /* PORT257CR */
+	PORTCR(258, 0xe6053102), /* PORT258CR */
+	PORTCR(259, 0xe6053103), /* PORT259CR */
+
+	PORTCR(260, 0xe6053104), /* PORT260CR */
+	PORTCR(261, 0xe6053105), /* PORT261CR */
+	PORTCR(262, 0xe6053106), /* PORT262CR */
+	PORTCR(263, 0xe6053107), /* PORT263CR */
+	PORTCR(264, 0xe6053108), /* PORT264CR */
+	PORTCR(265, 0xe6053109), /* PORT265CR */
+	PORTCR(266, 0xe605310a), /* PORT266CR */
+	PORTCR(267, 0xe605310b), /* PORT267CR */
+	PORTCR(268, 0xe605310c), /* PORT268CR */
+	PORTCR(269, 0xe605310d), /* PORT269CR */
+
+	PORTCR(270, 0xe605310e), /* PORT270CR */
+	PORTCR(271, 0xe605310f), /* PORT271CR */
+	PORTCR(272, 0xe6053110), /* PORT272CR */
+	PORTCR(273, 0xe6053111), /* PORT273CR */
+	PORTCR(274, 0xe6053112), /* PORT274CR */
+	PORTCR(275, 0xe6053113), /* PORT275CR */
+	PORTCR(276, 0xe6053114), /* PORT276CR */
+	PORTCR(277, 0xe6053115), /* PORT277CR */
+	PORTCR(278, 0xe6053116), /* PORT278CR */
+	PORTCR(279, 0xe6053117), /* PORT279CR */
+
+	PORTCR(280, 0xe6053118), /* PORT280CR */
+	PORTCR(281, 0xe6053119), /* PORT281CR */
+	PORTCR(282, 0xe605311a), /* PORT282CR */
+
+	PORTCR(288, 0xe6052120), /* PORT288CR */
+	PORTCR(289, 0xe6052121), /* PORT289CR */
+
+	PORTCR(290, 0xe6052122), /* PORT290CR */
+	PORTCR(291, 0xe6052123), /* PORT291CR */
+	PORTCR(292, 0xe6052124), /* PORT292CR */
+	PORTCR(293, 0xe6052125), /* PORT293CR */
+	PORTCR(294, 0xe6052126), /* PORT294CR */
+	PORTCR(295, 0xe6052127), /* PORT295CR */
+	PORTCR(296, 0xe6052128), /* PORT296CR */
+	PORTCR(297, 0xe6052129), /* PORT297CR */
+	PORTCR(298, 0xe605212a), /* PORT298CR */
+	PORTCR(299, 0xe605212b), /* PORT299CR */
+
+	PORTCR(300, 0xe605212c), /* PORT300CR */
+	PORTCR(301, 0xe605212d), /* PORT301CR */
+	PORTCR(302, 0xe605212e), /* PORT302CR */
+	PORTCR(303, 0xe605212f), /* PORT303CR */
+	PORTCR(304, 0xe6052130), /* PORT304CR */
+	PORTCR(305, 0xe6052131), /* PORT305CR */
+	PORTCR(306, 0xe6052132), /* PORT306CR */
+	PORTCR(307, 0xe6052133), /* PORT307CR */
+	PORTCR(308, 0xe6052134), /* PORT308CR */
+	PORTCR(309, 0xe6052135), /* PORT309CR */
+
+	{ PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+			MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+			MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+			MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+			0, 0,
+			MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+			MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+			MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+			MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+			MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+			MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+			MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+			MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+			MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+			MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+			MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+			MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+			MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+			MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+			MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+		}
+	},
+	{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
+			0, 0,
+			0, 0,
+			0, 0,
+			MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			0, 0,
+			MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+			0, 0,
+			0, 0,
+			0, 0,
+			MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+			0, 0,
+			MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+			0, 0,
+			0, 0,
+			MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+			0, 0,
+			0, 0,
+			0, 0,
+			MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+			0, 0,
+			0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
+			0, 0,
+			0, 0,
+			MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+			0, 0,
+			MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+			MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+			0, 0,
+			0, 0,
+			0, 0,
+			MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+			MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+			MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+			MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+			0, 0,
+			0, 0,
+			0, 0,
+			MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+			0, 0,
+			MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+			MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+			MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+			MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+			MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+			MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+			MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+			0, 0,
+			0, 0,
+			MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+			0, 0,
+			0, 0,
+			MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+			0, 0,
+		}
+	},
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
+			PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+			PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+			PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+			PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+			PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+			PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+			PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+			PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
+			PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+			PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+			PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+			PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+			PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+			PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+			PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+			PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
+			PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+			PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+			PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+			PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+			PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+			PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+			PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+			PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+			PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+			PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+			PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+			PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+			PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
+			PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+			PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+			PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+			PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+			PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+			PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+			PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+			PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, 0, PORT164_DATA,
+			PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
+			PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
+			PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
+			PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
+			PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
+			PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+			PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+			PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+			PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
+			PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
+			PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
+			PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
+			PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
+			PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
+			PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
+			PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
+			PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
+			0, 0, 0, 0,
+			0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
+			PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
+			PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
+			PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
+			PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
+			PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
+			PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
+	},
+	{ PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
+			0, 0, 0, 0,
+			0, 0, 0, 0,
+			0, 0, PORT309_DATA, PORT308_DATA,
+			PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
+			PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
+			PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
+			PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
+			PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
+	},
+	{ },
+};
+
+#if 0
+/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
+#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
+#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
+#else
+#define EXT_IRQ16L(n) (n)
+#define EXT_IRQ16H(n) (n)
+#endif
+
+static struct pinmux_irq pinmux_irqs[] = {
+	PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
+	PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
+	PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
+};
+
+static struct pinmux_info sh73a0_pinmux_info = {
+	.name = "sh73a0_pfc",
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+	.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_PORT0,
+	.last_gpio = GPIO_FN_FSIAISLD_PU,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+
+	.gpio_irq = pinmux_irqs,
+	.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
+};
+
+void sh73a0_pinmux_init(void)
+{
+	register_pinmux(&sh73a0_pinmux_info);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/timer.c
new file mode 100644
index 000000000..04700e7d3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/rmobile/timer.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch-armv7/globaltimer.h>
+#include <asm/arch/rmobile.h>
+
+static struct globaltimer *global_timer = \
+		(struct globaltimer *)GLOBAL_TIMER_BASE_ADDR;
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+static u64 get_cpu_global_timer(void)
+{
+	u32 low, high;
+	u64 timer;
+
+	u32 old = readl(&global_timer->cnt_h);
+	while (1) {
+		low = readl(&global_timer->cnt_l);
+		high = readl(&global_timer->cnt_h);
+		if (old == high)
+			break;
+		else
+			old = high;
+	}
+
+	timer = high;
+	return (u64)((timer << 32) | low);
+}
+
+static u64 get_time_us(void)
+{
+	u64 timer = get_cpu_global_timer();
+
+	timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
+	do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
+	return timer;
+}
+
+static ulong get_time_ms(void)
+{
+	u64 us = get_time_us();
+
+	do_div(us, 1000);
+	return us;
+}
+
+int timer_init(void)
+{
+	writel(0x01, &global_timer->ctl);
+	return 0;
+}
+
+void __udelay(unsigned long usec)
+{
+	u64 start, current;
+	u64 wait;
+
+	start = get_cpu_global_timer();
+	wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
+	do {
+		current = get_cpu_global_timer();
+	} while ((current - start) < wait);
+}
+
+ulong get_timer(ulong base)
+{
+	return get_time_ms() - base;
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_cpu_global_timer();
+}
+
+ulong get_tbclk(void)
+{
+	return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/Makefile
new file mode 100644
index 000000000..f571d8a0e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2009 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y		+= cpu_info.o
+ifndef CONFIG_SPL_BUILD
+obj-y		+= timer.o
+obj-y		+= sromc.o
+obj-$(CONFIG_PWM)	+= pwm.o
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/cpu_info.c
new file mode 100644
index 000000000..a8d91e769
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/cpu_info.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+
+/* Default is s5pc100 */
+unsigned int s5p_cpu_id = 0xC100;
+/* Default is EVT1 */
+unsigned int s5p_cpu_rev = 1;
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	s5p_set_cpu_id();
+
+	return 0;
+}
+#endif
+
+u32 get_device_type(void)
+{
+	return s5p_cpu_id;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+	char buf[32];
+
+	printf("CPU:\t%s%X@%sMHz\n",
+			s5p_get_cpu_name(), s5p_cpu_id,
+			strmhz(buf, get_arm_clk()));
+
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/pwm.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/pwm.c
new file mode 100644
index 000000000..b8805c8d4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/pwm.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/clk.h>
+
+int pwm_enable(int pwm_id)
+{
+	const struct s5p_timer *pwm =
+			(struct s5p_timer *)samsung_get_base_timer();
+	unsigned long tcon;
+
+	tcon = readl(&pwm->tcon);
+	tcon |= TCON_START(pwm_id);
+
+	writel(tcon, &pwm->tcon);
+
+	return 0;
+}
+
+void pwm_disable(int pwm_id)
+{
+	const struct s5p_timer *pwm =
+			(struct s5p_timer *)samsung_get_base_timer();
+	unsigned long tcon;
+
+	tcon = readl(&pwm->tcon);
+	tcon &= ~TCON_START(pwm_id);
+
+	writel(tcon, &pwm->tcon);
+}
+
+static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
+{
+	unsigned long tin_parent_rate;
+	unsigned int div;
+
+	tin_parent_rate = get_pwm_clk();
+
+	for (div = 2; div <= 16; div *= 2) {
+		if ((tin_parent_rate / (div << 16)) < freq)
+			return tin_parent_rate / div;
+	}
+
+	return tin_parent_rate / 16;
+}
+
+#define NS_IN_SEC 1000000000UL
+
+int pwm_config(int pwm_id, int duty_ns, int period_ns)
+{
+	const struct s5p_timer *pwm =
+			(struct s5p_timer *)samsung_get_base_timer();
+	unsigned int offset;
+	unsigned long tin_rate;
+	unsigned long tin_ns;
+	unsigned long frequency;
+	unsigned long tcon;
+	unsigned long tcnt;
+	unsigned long tcmp;
+
+	/*
+	 * We currently avoid using 64bit arithmetic by using the
+	 * fact that anything faster than 1GHz is easily representable
+	 * by 32bits.
+	 */
+	if (period_ns > NS_IN_SEC || duty_ns > NS_IN_SEC || period_ns == 0)
+		return -ERANGE;
+
+	if (duty_ns > period_ns)
+		return -EINVAL;
+
+	frequency = NS_IN_SEC / period_ns;
+
+	/* Check to see if we are changing the clock rate of the PWM */
+	tin_rate = pwm_calc_tin(pwm_id, frequency);
+
+	tin_ns = NS_IN_SEC / tin_rate;
+	tcnt = period_ns / tin_ns;
+
+	/* Note, counters count down */
+	tcmp = duty_ns / tin_ns;
+	tcmp = tcnt - tcmp;
+
+	/* Update the PWM register block. */
+	offset = pwm_id * 3;
+	if (pwm_id < 4) {
+		writel(tcnt, &pwm->tcntb0 + offset);
+		writel(tcmp, &pwm->tcmpb0 + offset);
+	}
+
+	tcon = readl(&pwm->tcon);
+	tcon |= TCON_UPDATE(pwm_id);
+	if (pwm_id < 4)
+		tcon |= TCON_AUTO_RELOAD(pwm_id);
+	else
+		tcon |= TCON4_AUTO_RELOAD;
+	writel(tcon, &pwm->tcon);
+
+	tcon &= ~TCON_UPDATE(pwm_id);
+	writel(tcon, &pwm->tcon);
+
+	return 0;
+}
+
+int pwm_init(int pwm_id, int div, int invert)
+{
+	u32 val;
+	const struct s5p_timer *pwm =
+			(struct s5p_timer *)samsung_get_base_timer();
+	unsigned long ticks_per_period;
+	unsigned int offset, prescaler;
+
+	/*
+	 * Timer Freq(HZ) =
+	 *	PWM_CLK / { (prescaler_value + 1) * (divider_value) }
+	 */
+
+	val = readl(&pwm->tcfg0);
+	if (pwm_id < 2) {
+		prescaler = PRESCALER_0;
+		val &= ~0xff;
+		val |= (prescaler & 0xff);
+	} else {
+		prescaler = PRESCALER_1;
+		val &= ~(0xff << 8);
+		val |= (prescaler & 0xff) << 8;
+	}
+	writel(val, &pwm->tcfg0);
+	val = readl(&pwm->tcfg1);
+	val &= ~(0xf << MUX_DIV_SHIFT(pwm_id));
+	val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id);
+	writel(val, &pwm->tcfg1);
+
+	if (pwm_id == 4) {
+		/*
+		 * TODO(sjg): Use this as a countdown timer for now. We count
+		 * down from the maximum value to 0, then reset.
+		 */
+		ticks_per_period = -1UL;
+	} else {
+		const unsigned long pwm_hz = 1000;
+		unsigned long timer_rate_hz = get_pwm_clk() /
+			((prescaler + 1) * (1 << div));
+
+		ticks_per_period = timer_rate_hz / pwm_hz;
+	}
+
+	/* set count value */
+	offset = pwm_id * 3;
+
+	writel(ticks_per_period, &pwm->tcntb0 + offset);
+
+	val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id));
+	if (invert && (pwm_id < 4))
+		val |= TCON_INVERTER(pwm_id);
+	writel(val, &pwm->tcon);
+
+	pwm_enable(pwm_id);
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/sromc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/sromc.c
new file mode 100644
index 000000000..806456fe8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/sromc.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sromc.h>
+
+/*
+ * s5p_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank	- SROM
+ * srom_bw_conf  - SMC Band witdh reg configuration value
+ * srom_bc_conf  - SMC Bank Control reg configuration value
+ */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
+{
+	u32 tmp;
+	struct s5p_sromc *srom =
+		(struct s5p_sromc *)samsung_get_base_sromc();
+
+	/* Configure SMC_BW register to handle proper SROMC bank */
+	tmp = srom->bw;
+	tmp &= ~(0xF << (srom_bank * 4));
+	tmp |= srom_bw_conf;
+	srom->bw = tmp;
+
+	/* Configure SMC_BC register */
+	srom->bc[srom_bank] = srom_bc_conf;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/timer.c
new file mode 100644
index 000000000..949abb1c8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5p-common/timer.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Inki Dae <inki.dae@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/clk.h>
+#include <pwm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long get_current_tick(void);
+
+/* macro to read the 16 bit timer */
+static inline struct s5p_timer *s5p_get_base_timer(void)
+{
+	return (struct s5p_timer *)samsung_get_base_timer();
+}
+
+/**
+ * Read the countdown timer.
+ *
+ * This operates at 1MHz and counts downwards. It will wrap about every
+ * hour (2^32 microseconds).
+ *
+ * @return current value of timer
+ */
+static unsigned long timer_get_us_down(void)
+{
+	struct s5p_timer *const timer = s5p_get_base_timer();
+
+	return readl(&timer->tcnto4);
+}
+
+int timer_init(void)
+{
+	/* PWM Timer 4 */
+	pwm_init(4, MUX_DIV_4, 0);
+	pwm_config(4, 100000, 100000);
+	pwm_enable(4);
+
+	/* Use this as the current monotonic time in us */
+	gd->arch.timer_reset_value = 0;
+
+	/* Use this as the last timer value we saw */
+	gd->arch.lastinc = timer_get_us_down();
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long get_timer(unsigned long base)
+{
+	unsigned long long time_ms;
+
+	ulong now = timer_get_us_down();
+
+	/*
+	 * Increment the time by the amount elapsed since the last read.
+	 * The timer may have wrapped around, but it makes no difference to
+	 * our arithmetic here.
+	 */
+	gd->arch.timer_reset_value += gd->arch.lastinc - now;
+	gd->arch.lastinc = now;
+
+	/* Divide by 1000 to convert from us to ms */
+	time_ms = gd->arch.timer_reset_value;
+	do_div(time_ms, 1000);
+	return time_ms - base;
+}
+
+unsigned long __attribute__((no_instrument_function)) timer_get_us(void)
+{
+	static unsigned long base_time_us;
+
+	struct s5p_timer *const timer =
+		(struct s5p_timer *)samsung_get_base_timer();
+	unsigned long now_downward_us = readl(&timer->tcnto4);
+
+	if (!base_time_us)
+		base_time_us = now_downward_us;
+
+	/* Note that this timer counts downward. */
+	return base_time_us - now_downward_us;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+	unsigned long count_value;
+
+	count_value = timer_get_us_down();
+	while ((int)(count_value - timer_get_us_down()) < (int)usec)
+		;
+}
+
+void reset_timer_masked(void)
+{
+	struct s5p_timer *const timer = s5p_get_base_timer();
+
+	/* reset time */
+	gd->arch.lastinc = readl(&timer->tcnto4);
+	gd->arch.tbl = 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/Makefile
new file mode 100644
index 000000000..9f43ded1d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= cache.o
+obj-y	+= reset.o
+
+obj-y	+= clock.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/cache.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/cache.S
new file mode 100644
index 000000000..3089592eb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/cache.S
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * based on arch/arm/cpu/armv7/omap3/cache.S
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.align 5
+
+#include <linux/linkage.h>
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+ENTRY(v7_outer_cache_enable)
+	push	{r0, r1, r2, lr}
+	mrc	15, 0, r3, cr1, cr0, 1
+	orr	r3, r3, #2
+	mcr	15, 0, r3, cr1, cr0, 1
+	pop	{r1, r2, r3, pc}
+ENDPROC(v7_outer_cache_enable)
+
+ENTRY(v7_outer_cache_disable)
+	push	{r0, r1, r2, lr}
+	mrc	15, 0, r3, cr1, cr0, 1
+	bic	r3, r3, #2
+	mcr	15, 0, r3, cr1, cr0, 1
+	pop	{r1, r2, r3, pc}
+ENDPROC(v7_outer_cache_disable)
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/clock.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/clock.c
new file mode 100644
index 000000000..3da00717f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/clock.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+
+#define CLK_M	0
+#define CLK_D	1
+#define CLK_P	2
+
+#ifndef CONFIG_SYS_CLK_FREQ_C100
+#define CONFIG_SYS_CLK_FREQ_C100	12000000
+#endif
+#ifndef CONFIG_SYS_CLK_FREQ_C110
+#define CONFIG_SYS_CLK_FREQ_C110	24000000
+#endif
+
+/* s5pc110: return pll clock frequency */
+static unsigned long s5pc100_get_pll_clk(int pllreg)
+{
+	struct s5pc100_clock *clk =
+		(struct s5pc100_clock *)samsung_get_base_clock();
+	unsigned long r, m, p, s, mask, fout;
+	unsigned int freq;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con);
+		break;
+	case HPLL:
+		r = readl(&clk->hpll_con);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	/*
+	 * APLL_CON: MIDV [25:16]
+	 * MPLL_CON: MIDV [23:16]
+	 * EPLL_CON: MIDV [23:16]
+	 * HPLL_CON: MIDV [23:16]
+	 */
+	if (pllreg == APLL)
+		mask = 0x3ff;
+	else
+		mask = 0x0ff;
+
+	m = (r >> 16) & mask;
+
+	/* PDIV [13:8] */
+	p = (r >> 8) & 0x3f;
+	/* SDIV [2:0] */
+	s = r & 0x7;
+
+	/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+	freq = CONFIG_SYS_CLK_FREQ_C100;
+	fout = m * (freq / (p * (1 << s)));
+
+	return fout;
+}
+
+/* s5pc100: return pll clock frequency */
+static unsigned long s5pc110_get_pll_clk(int pllreg)
+{
+	struct s5pc110_clock *clk =
+		(struct s5pc110_clock *)samsung_get_base_clock();
+	unsigned long r, m, p, s, mask, fout;
+	unsigned int freq;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	/*
+	 * APLL_CON: MIDV [25:16]
+	 * MPLL_CON: MIDV [25:16]
+	 * EPLL_CON: MIDV [24:16]
+	 * VPLL_CON: MIDV [24:16]
+	 */
+	if (pllreg == APLL || pllreg == MPLL)
+		mask = 0x3ff;
+	else
+		mask = 0x1ff;
+
+	m = (r >> 16) & mask;
+
+	/* PDIV [13:8] */
+	p = (r >> 8) & 0x3f;
+	/* SDIV [2:0] */
+	s = r & 0x7;
+
+	freq = CONFIG_SYS_CLK_FREQ_C110;
+	if (pllreg == APLL) {
+		if (s < 1)
+			s = 1;
+		/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+		fout = m * (freq / (p * (1 << (s - 1))));
+	} else
+		/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+		fout = m * (freq / (p * (1 << s)));
+
+	return fout;
+}
+
+/* s5pc110: return ARM clock frequency */
+static unsigned long s5pc110_get_arm_clk(void)
+{
+	struct s5pc110_clock *clk =
+		(struct s5pc110_clock *)samsung_get_base_clock();
+	unsigned long div;
+	unsigned long dout_apll, armclk;
+	unsigned int apll_ratio;
+
+	div = readl(&clk->div0);
+
+	/* APLL_RATIO: [2:0] */
+	apll_ratio = div & 0x7;
+
+	dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+	armclk = dout_apll;
+
+	return armclk;
+}
+
+/* s5pc100: return ARM clock frequency */
+static unsigned long s5pc100_get_arm_clk(void)
+{
+	struct s5pc100_clock *clk =
+		(struct s5pc100_clock *)samsung_get_base_clock();
+	unsigned long div;
+	unsigned long dout_apll, armclk;
+	unsigned int apll_ratio, arm_ratio;
+
+	div = readl(&clk->div0);
+
+	/* ARM_RATIO: [6:4] */
+	arm_ratio = (div >> 4) & 0x7;
+	/* APLL_RATIO: [0] */
+	apll_ratio = div & 0x1;
+
+	dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+	armclk = dout_apll / (arm_ratio + 1);
+
+	return armclk;
+}
+
+/* s5pc100: return HCLKD0 frequency */
+static unsigned long get_hclk(void)
+{
+	struct s5pc100_clock *clk =
+		(struct s5pc100_clock *)samsung_get_base_clock();
+	unsigned long hclkd0;
+	uint div, d0_bus_ratio;
+
+	div = readl(&clk->div0);
+	/* D0_BUS_RATIO: [10:8] */
+	d0_bus_ratio = (div >> 8) & 0x7;
+
+	hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
+
+	return hclkd0;
+}
+
+/* s5pc100: return PCLKD1 frequency */
+static unsigned long get_pclkd1(void)
+{
+	struct s5pc100_clock *clk =
+		(struct s5pc100_clock *)samsung_get_base_clock();
+	unsigned long d1_bus, pclkd1;
+	uint div, d1_bus_ratio, pclkd1_ratio;
+
+	div = readl(&clk->div0);
+	/* D1_BUS_RATIO: [14:12] */
+	d1_bus_ratio = (div >> 12) & 0x7;
+	/* PCLKD1_RATIO: [18:16] */
+	pclkd1_ratio = (div >> 16) & 0x7;
+
+	/* ASYNC Mode */
+	d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
+	pclkd1 = d1_bus / (pclkd1_ratio + 1);
+
+	return pclkd1;
+}
+
+/* s5pc110: return HCLKs frequency */
+static unsigned long get_hclk_sys(int dom)
+{
+	struct s5pc110_clock *clk =
+		(struct s5pc110_clock *)samsung_get_base_clock();
+	unsigned long hclk;
+	unsigned int div;
+	unsigned int offset;
+	unsigned int hclk_sys_ratio;
+
+	if (dom == CLK_M)
+		return get_hclk();
+
+	div = readl(&clk->div0);
+
+	/*
+	 * HCLK_MSYS_RATIO: [10:8]
+	 * HCLK_DSYS_RATIO: [19:16]
+	 * HCLK_PSYS_RATIO: [27:24]
+	 */
+	offset = 8 + (dom << 0x3);
+
+	hclk_sys_ratio = (div >> offset) & 0xf;
+
+	hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
+
+	return hclk;
+}
+
+/* s5pc110: return PCLKs frequency */
+static unsigned long get_pclk_sys(int dom)
+{
+	struct s5pc110_clock *clk =
+		(struct s5pc110_clock *)samsung_get_base_clock();
+	unsigned long pclk;
+	unsigned int div;
+	unsigned int offset;
+	unsigned int pclk_sys_ratio;
+
+	div = readl(&clk->div0);
+
+	/*
+	 * PCLK_MSYS_RATIO: [14:12]
+	 * PCLK_DSYS_RATIO: [22:20]
+	 * PCLK_PSYS_RATIO: [30:28]
+	 */
+	offset = 12 + (dom << 0x3);
+
+	pclk_sys_ratio = (div >> offset) & 0x7;
+
+	pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
+
+	return pclk;
+}
+
+/* s5pc110: return peripheral clock frequency */
+static unsigned long s5pc110_get_pclk(void)
+{
+	return get_pclk_sys(CLK_P);
+}
+
+/* s5pc100: return peripheral clock frequency */
+static unsigned long s5pc100_get_pclk(void)
+{
+	return get_pclkd1();
+}
+
+/* s5pc1xx: return uart clock frequency */
+static unsigned long s5pc1xx_get_uart_clk(int dev_index)
+{
+	if (cpu_is_s5pc110())
+		return s5pc110_get_pclk();
+	else
+		return s5pc100_get_pclk();
+}
+
+/* s5pc1xx: return pwm clock frequency */
+static unsigned long s5pc1xx_get_pwm_clk(void)
+{
+	if (cpu_is_s5pc110())
+		return s5pc110_get_pclk();
+	else
+		return s5pc100_get_pclk();
+}
+
+unsigned long get_pll_clk(int pllreg)
+{
+	if (cpu_is_s5pc110())
+		return s5pc110_get_pll_clk(pllreg);
+	else
+		return s5pc100_get_pll_clk(pllreg);
+}
+
+unsigned long get_arm_clk(void)
+{
+	if (cpu_is_s5pc110())
+		return s5pc110_get_arm_clk();
+	else
+		return s5pc100_get_arm_clk();
+}
+
+unsigned long get_pwm_clk(void)
+{
+	return s5pc1xx_get_pwm_clk();
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+	return s5pc1xx_get_uart_clk(dev_index);
+}
+
+void set_mmc_clk(int dev_index, unsigned int div)
+{
+	/* Do NOTHING */
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/reset.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/reset.S
new file mode 100644
index 000000000..bd74f2b45
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/s5pc1xx/reset.S
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/cpu.h>
+#include <linux/linkage.h>
+
+#define S5PC100_SWRESET			0xE0200000
+#define S5PC110_SWRESET			0xE0102000
+
+ENTRY(reset_cpu)
+	ldr	r1, =S5PC100_PRO_ID
+	ldr	r2, [r1]
+	ldr	r4, =0x00010000
+	and	r4, r2, r4
+	cmp	r4, #0
+	bne	110f
+	/* S5PC100 */
+	ldr	r1, =S5PC100_SWRESET
+	ldr	r2, =0xC100
+	b	200f
+110:	/* S5PC110 */
+	ldr	r1, =S5PC110_SWRESET
+	mov	r2, #1
+200:
+	str	r2, [r1]
+_loop_forever:
+	b	_loop_forever
+ENDPROC(reset_cpu)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/Makefile
new file mode 100644
index 000000000..cbe1d406d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2012 Altera Corporation <www.altera.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= lowlevel_init.o
+obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/clock_manager.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/clock_manager.c
new file mode 100644
index 000000000..23d697dee
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -0,0 +1,361 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+
+static const struct socfpga_clock_manager *clock_manager_base =
+		(void *)SOCFPGA_CLKMGR_ADDRESS;
+
+#define CLKMGR_BYPASS_ENABLE	1
+#define CLKMGR_BYPASS_DISABLE	0
+#define CLKMGR_STAT_IDLE	0
+#define CLKMGR_STAT_BUSY	1
+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1		0
+#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX	1
+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1		0
+#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX	1
+
+#define CLEAR_BGP_EN_PWRDN \
+	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+#define VCO_EN_BASE \
+	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
+	CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
+	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
+
+static inline void cm_wait_for_lock(uint32_t mask)
+{
+	register uint32_t inter_val;
+	do {
+		inter_val = readl(&clock_manager_base->inter) & mask;
+	} while (inter_val != mask);
+}
+
+/* function to poll in the fsm busy bit */
+static inline void cm_wait_for_fsm(void)
+{
+	while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
+		;
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static inline void cm_write_bypass(uint32_t val)
+{
+	writel(val, &clock_manager_base->bypass);
+	cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static inline void cm_write_ctrl(uint32_t val)
+{
+	writel(val, &clock_manager_base->ctrl);
+	cm_wait_for_fsm();
+}
+
+/* function to write a clock register that has phase information */
+static inline void cm_write_with_phase(uint32_t value,
+	uint32_t reg_address, uint32_t mask)
+{
+	/* poll until phase is zero */
+	while (readl(reg_address) & mask)
+		;
+
+	writel(value, reg_address);
+
+	while (readl(reg_address) & mask)
+		;
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ * Put all plls in bypass
+ * Put all plls VCO registers back to reset value (bandgap power down).
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ * Delay 5 us.
+ * Deassert bandgap power down and set numerator and denominator
+ * Start 7 us timer.
+ * set internal dividers
+ * Wait for 7 us timer.
+ * Enable plls
+ * Set external dividers while plls are locking
+ * Wait for pll lock
+ * Assert/deassert outreset all.
+ * Take all pll's out of bypass
+ * Clear safe mode
+ * set source main and peripheral clocks
+ * Ungate clocks
+ */
+
+void cm_basic_init(const cm_config_t *cfg)
+{
+	uint32_t start, timeout;
+
+	/* Start by being paranoid and gate all sw managed clocks */
+
+	/*
+	 * We need to disable nandclk
+	 * and then do another apb access before disabling
+	 * gatting off the rest of the periperal clocks.
+	 */
+	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
+		readl(&clock_manager_base->per_pll_en),
+		&clock_manager_base->per_pll_en);
+
+	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
+	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
+		&clock_manager_base->main_pll_en);
+
+	writel(0, &clock_manager_base->sdr_pll_en);
+
+	/* now we can gate off the rest of the peripheral clocks */
+	writel(0, &clock_manager_base->per_pll_en);
+
+	/* Put all plls in bypass */
+	cm_write_bypass(
+		CLKMGR_BYPASS_PERPLLSRC_SET(
+		CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_SDRPLLSRC_SET(
+		CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
+		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
+		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
+
+	/*
+	 * Put all plls VCO registers back to reset value.
+	 * Some code might have messed with them.
+	 */
+	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->main_pll_vco);
+	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->per_pll_vco);
+	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
+	       &clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * The clocks to the flash devices and the L4_MAIN clocks can
+	 * glitch when coming out of safe mode if their source values
+	 * are different from their reset value.  So the trick it to
+	 * put them back to their reset state, and change input
+	 * after exiting safe mode but before ungating the clocks.
+	 */
+	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
+	       &clock_manager_base->per_pll_src);
+	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
+	       &clock_manager_base->main_pll_l4src);
+
+	/* read back for the required 5 us delay. */
+	readl(&clock_manager_base->main_pll_vco);
+	readl(&clock_manager_base->per_pll_vco);
+	readl(&clock_manager_base->sdr_pll_vco);
+
+
+	/*
+	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
+	 * with numerator and denominator.
+	 */
+	writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->main_pll_vco);
+
+	writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->per_pll_vco);
+
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
+		CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
+		&clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * Time starts here
+	 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
+	 */
+	reset_timer();
+	start = get_timer(0);
+	/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
+	timeout = 7;
+
+	/* main mpu */
+	writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
+
+	/* main main clock */
+	writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
+
+	/* main for dbg */
+	writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
+
+	/* main for cfgs2fuser0clk */
+	writel(cfg->cfg2fuser0clk,
+	       &clock_manager_base->main_pll_cfgs2fuser0clk);
+
+	/* Peri emac0 50 MHz default to RMII */
+	writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
+
+	/* Peri emac1 50 MHz default to RMII */
+	writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
+
+	/* Peri QSPI */
+	writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
+
+	writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
+
+	/* Peri pernandsdmmcclk */
+	writel(cfg->pernandsdmmcclk,
+	       &clock_manager_base->per_pll_pernandsdmmcclk);
+
+	/* Peri perbaseclk */
+	writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
+
+	/* Peri s2fuser1clk */
+	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
+
+	/* 7 us must have elapsed before we can enable the VCO */
+	while (get_timer(start) < timeout)
+		;
+
+	/* Enable vco */
+	/* main pll vco */
+	writel(cfg->main_vco_base | VCO_EN_BASE,
+	       &clock_manager_base->main_pll_vco);
+
+	/* periferal pll */
+	writel(cfg->peri_vco_base | VCO_EN_BASE,
+	       &clock_manager_base->per_pll_vco);
+
+	/* sdram pll vco */
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | VCO_EN_BASE,
+		&clock_manager_base->sdr_pll_vco);
+
+	/* L3 MP and L3 SP */
+	writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
+
+	writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
+
+	writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
+
+	/* L4 MP, L4 SP, can0, and can1 */
+	writel(cfg->perdiv, &clock_manager_base->per_pll_div);
+
+	writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
+
+#define LOCKED_MASK \
+	(CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
+	CLKMGR_INTER_PERPLLLOCKED_MASK  | \
+	CLKMGR_INTER_MAINPLLLOCKED_MASK)
+
+	cm_wait_for_lock(LOCKED_MASK);
+
+	/* write the sdram clock counters before toggling outreset all */
+	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddrdqsclk);
+
+	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddr2xdqsclk);
+
+	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_ddrdqclk);
+
+	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll_s2fuser2clk);
+
+	/*
+	 * after locking, but before taking out of bypass
+	 * assert/deassert outresetall
+	 */
+	uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
+
+	/* assert main outresetall */
+	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->main_pll_vco);
+
+	uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
+
+	/* assert pheriph outresetall */
+	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->per_pll_vco);
+
+	/* assert sdram outresetall */
+	writel(cfg->sdram_vco_base | VCO_EN_BASE|
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
+		&clock_manager_base->sdr_pll_vco);
+
+	/* deassert main outresetall */
+	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->main_pll_vco);
+
+	/* deassert pheriph outresetall */
+	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->per_pll_vco);
+
+	/* deassert sdram outresetall */
+	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
+		cfg->sdram_vco_base | VCO_EN_BASE,
+		&clock_manager_base->sdr_pll_vco);
+
+	/*
+	 * now that we've toggled outreset all, all the clocks
+	 * are aligned nicely; so we can change any phase.
+	 */
+	cm_write_with_phase(cfg->ddrdqsclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
+			    CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
+
+	/* SDRAM DDR2XDQSCLK */
+	cm_write_with_phase(cfg->ddr2xdqsclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
+			    CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
+
+	cm_write_with_phase(cfg->ddrdqclk,
+			    (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
+			    CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
+
+	cm_write_with_phase(cfg->s2fuser2clk,
+			    (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
+			    CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
+
+	/* Take all three PLLs out of bypass when safe mode is cleared. */
+	cm_write_bypass(
+		CLKMGR_BYPASS_PERPLLSRC_SET(
+			CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_SDRPLLSRC_SET(
+			CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
+		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
+		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
+		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
+
+	/* clear safe mode */
+	cm_write_ctrl(readl(&clock_manager_base->ctrl) |
+			CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
+
+	/*
+	 * now that safe mode is clear with clocks gated
+	 * it safe to change the source mux for the flashes the the L4_MAIN
+	 */
+	writel(cfg->persrc, &clock_manager_base->per_pll_src);
+	writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
+
+	/* Now ungate non-hw-managed clocks */
+	writel(~0, &clock_manager_base->main_pll_en);
+	writel(~0, &clock_manager_base->per_pll_en);
+	writel(~0, &clock_manager_base->sdr_pll_en);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/config.mk b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/config.mk
new file mode 100644
index 000000000..3d1849157
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/config.mk
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+ifndef CONFIG_SPL_BUILD
+ALL-y	+= u-boot.img
+endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c
new file mode 100644
index 000000000..b8c9bce1e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c
@@ -0,0 +1,215 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/timer.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_freeze_controller *freeze_controller_base =
+		(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Default state from cold reset is FREEZE_ALL; the global
+ * flag is set to TRUE to indicate the IO banks are frozen
+ */
+static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
+	= { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
+	FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
+
+/* Freeze HPS IOs */
+void sys_mgr_frzctrl_freeze_req(void)
+{
+	u32 ioctrl_reg_offset;
+	u32 reg_value;
+	u32 reg_cfg_mask;
+	u32 channel_id;
+
+	/* select software FSM */
+	writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);
+
+	/* Freeze channel 0 to 2 */
+	for (channel_id = 0; channel_id <= 2; channel_id++) {
+		ioctrl_reg_offset = (u32)(
+			&freeze_controller_base->vioctrl +
+			(channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+
+		/*
+		 * Assert active low enrnsl, plniotri
+		 * and niotri signals
+		 */
+		reg_cfg_mask =
+			SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+		clrbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * Assert active low bhniotri signal and de-assert
+		 * active high csrdone
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+		clrbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/* Set global flag to indicate channel is frozen */
+		frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+	}
+
+	/* Freeze channel 3 */
+	/*
+	 * Assert active low enrnsl, plniotri and
+	 * niotri signals
+	 */
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+	clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+	/*
+	 * assert active low bhniotri & nfrzdrv signals,
+	 * de-assert active high csrdone and assert
+	 * active high frzreg and nfrzdrv signals
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
+	reg_value
+		= (reg_value & ~reg_cfg_mask)
+		| SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/*
+	 * assert active high reinit signal and de-assert
+	 * active high pllbiasen signals
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_value
+		= (reg_value &
+		~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
+		| SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/* Set global flag to indicate channel is frozen */
+	frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+}
+
+/* Unfreeze/Thaw HPS IOs */
+void sys_mgr_frzctrl_thaw_req(void)
+{
+	u32 ioctrl_reg_offset;
+	u32 reg_cfg_mask;
+	u32 reg_value;
+	u32 channel_id;
+
+	/* select software FSM */
+	writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);
+
+	/* Thaw channel 0 to 2 */
+	for (channel_id = 0; channel_id <= 2; channel_id++) {
+		ioctrl_reg_offset
+			= (u32)(&freeze_controller_base->vioctrl
+				+ (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+
+		/*
+		 * Assert active low bhniotri signal and
+		 * de-assert active high csrdone
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+		setbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * de-assert active low plniotri and niotri signals
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+		setbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * de-assert active low enrnsl signal
+		 */
+		setbits_le32(ioctrl_reg_offset,
+			SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
+
+		/* Set global flag to indicate channel is thawed */
+		frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
+	}
+
+	/* Thaw channel 3 */
+	/* de-assert active high reinit signal */
+	clrbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * assert active high pllbiasen signals
+	 */
+	setbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
+
+	/*
+	 * Delay 1000 intosc. intosc is based on eosc1
+	 * Use worst case which is fatest eosc1=50MHz, delay required
+	 * is 1/50MHz * 1000 = 20us
+	 */
+	udelay(20);
+
+	/*
+	 * de-assert active low bhniotri signals,
+	 * assert active high csrdone and nfrzdrv signal
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_value = (reg_value
+		| SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
+		& ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/*
+	 * Delay 33 intosc
+	 * Use worst case which is fatest eosc1=50MHz, delay required
+	 * is 1/50MHz * 33 = 660ns ~= 1us
+	 */
+	udelay(1);
+
+	/* de-assert active low plniotri and niotri signals */
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+
+	setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * de-assert active high frzreg signal
+	 */
+	clrbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * de-assert active low enrnsl signal
+	 */
+	setbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
+
+	/* Set global flag to indicate channel is thawed */
+	frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
new file mode 100644
index 000000000..1caaa2759
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
@@ -0,0 +1,66 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Save the parameter pass in by previous boot loader */
+.global save_boot_params
+save_boot_params:
+	/* save the parameter here */
+
+	/*
+	 * Setup stack for exception, which is located
+	 * at the end of on-chip RAM. We don't expect exception prior to
+	 * relocation and if that happens, we won't worry -- it will overide
+	 * global data region as the code will goto reset. After relocation,
+	 * this region won't be used by other part of program.
+	 * Hence it is safe.
+	 */
+	ldr	r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+	ldr	r1, =IRQ_STACK_START_IN
+	str	r0, [r1]
+
+	bx	lr
+
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Remap */
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * SPL : configure the remap (L3 NIC-301 GPV)
+	 * so the on-chip RAM at lower memory instead ROM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x19
+	str	r1, [r0]
+#else
+	/*
+	 * U-Boot : configure the remap (L3 NIC-301 GPV)
+	 * so the SDRAM at lower memory instead on-chip RAM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x2
+	str	r1, [r0]
+
+	/* Private components security */
+
+	/*
+	 * U-Boot : configure private timer, global timer and cpu
+	 * component access as non secure for kernel stage (as required
+	 * by kernel)
+	 */
+	mrc	p15,4,r0,c15,c0,0
+	add	r1, r0, #0x54
+	ldr	r2, [r1]
+	orr	r2, r2, #0xff
+	orr	r2, r2, #0xf00
+	str	r2, [r1]
+#endif	/* #ifdef CONFIG_SPL_BUILD */
+	mov	pc, lr
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/misc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/misc.c
new file mode 100644
index 000000000..2f1c7160f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/misc.c
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c
new file mode 100644
index 000000000..e320c011a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -0,0 +1,39 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+	/* request a warm reset */
+	writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
+		&reset_manager_base->ctrl);
+	/*
+	 * infinite loop here as watchdog will trigger and reset
+	 * the processor
+	 */
+	while (1)
+		;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	writel(0, &reset_manager_base->per_mod_reset);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/spl.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/spl.c
new file mode 100644
index 000000000..2ae88bbd0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/spl.c
@@ -0,0 +1,137 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <version.h>
+#include <image.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/freeze_controller.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_RAM;
+}
+
+/*
+ * Board initialization after bss clearance
+ */
+void spl_board_init(void)
+{
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+	cm_config_t cm_default_cfg = {
+		/* main group */
+		MAIN_VCO_BASE,
+		CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
+		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
+		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
+			CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
+		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
+		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
+			CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
+		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
+			CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
+		CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
+			CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
+		CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
+			CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
+
+		/* peripheral group */
+		PERI_VCO_BASE,
+		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
+		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
+		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
+		CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
+		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
+			CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
+		CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
+		CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
+		CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
+		CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
+			CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
+		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
+			CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
+		CLKMGR_PERPLLGRP_SRC_QSPI_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
+		CLKMGR_PERPLLGRP_SRC_NAND_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_NAND) |
+		CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
+			CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
+
+		/* sdram pll group */
+		SDR_VCO_BASE,
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
+		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
+		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
+			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
+			CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
+	};
+
+	debug("Freezing all I/O banks\n");
+	/* freeze all IO banks */
+	sys_mgr_frzctrl_freeze_req();
+
+	debug("Reconfigure Clock Manager\n");
+	/* reconfigure the PLLs */
+	cm_basic_init(&cm_default_cfg);
+
+	/* configure the pin muxing through system manager */
+	sysmgr_pinmux_init();
+#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
+
+	/* de-assert reset for peripherals and bridges based on handoff */
+	reset_deassert_peripherals_handoff();
+
+	debug("Unfreezing/Thaw all I/O banks\n");
+	/* unfreeze / thaw all IO banks */
+	sys_mgr_frzctrl_thaw_req();
+
+	/* enable console uart printing */
+	preloader_console_init();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/system_manager.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/system_manager.c
new file mode 100644
index 000000000..d96521ba0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+	unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
+
+	const unsigned long *pval = sys_mgr_init_table;
+	unsigned long i;
+
+	for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
+		i++, offset += sizeof(unsigned long)) {
+		writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/timer.c
new file mode 100644
index 000000000..58fc789e6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/timer.c
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Timer initialization
+ */
+int timer_init(void)
+{
+	writel(TIMER_LOAD_VAL, &timer_base->load_val);
+	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
+	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
new file mode 100644
index 000000000..4282beb39
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
@@ -0,0 +1,53 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/armv7/start.o	(.text*)
+		*(.text*)
+	} >.sdram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+
+	. = ALIGN(8);
+	__malloc_start = .;
+	. = . + CONFIG_SPL_MALLOC_SIZE;
+	__malloc_end = .;
+
+	. = . + CONFIG_SPL_STACK_SIZE;
+	. = ALIGN(8);
+	__stack_start = .;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/start.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/start.S
new file mode 100644
index 000000000..27be451a8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/start.S
@@ -0,0 +1,444 @@
+/*
+ * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
+ *
+ * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
+ *
+ * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+.globl _start
+_start: b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+#ifdef CONFIG_SPL_BUILD
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt:	.word _software_interrupt
+_prefetch_abort:	.word _prefetch_abort
+_data_abort:		.word _data_abort
+_not_used:		.word _not_used
+_irq:			.word _irq
+_fiq:			.word _fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#else
+.globl _undefined_instruction
+_undefined_instruction: .word undefined_instruction
+.globl _software_interrupt
+_software_interrupt:	.word software_interrupt
+.globl _prefetch_abort
+_prefetch_abort:	.word prefetch_abort
+.globl _data_abort
+_data_abort:		.word data_abort
+.globl _not_used
+_not_used:		.word not_used
+.globl _irq
+_irq:			.word irq
+.globl _fiq
+_fiq:			.word fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_SPL_BUILD */
+
+.global _end_vect
+_end_vect:
+
+	.balignl 16,0xdeadbeef
+/*************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************/
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	bl	save_boot_params
+	/*
+	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
+	 * except if in HYP mode already
+	 */
+	mrs	r0, cpsr
+	and	r1, r0, #0x1f		@ mask mode bits
+	teq	r1, #0x1a		@ test for HYP mode
+	bicne	r0, r0, #0x1f		@ clear all mode bits
+	orrne	r0, r0, #0x13		@ set SVC mode
+	orr	r0, r0, #0xc0		@ disable FIQ and IRQ
+	msr	cpsr,r0
+
+/*
+ * Setup vector:
+ * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
+ * Continue to use ROM code vector only in OMAP4 spl)
+ */
+#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
+	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
+	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTRL Register
+	bic	r0, #CR_V		@ V = 0
+	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTRL Register
+
+	/* Set vector address in CP15 VBAR register */
+	ldr	r0, =_start
+	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
+#endif
+
+	/* the mask ROM code should have PLL and others stable */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_cp15
+	bl	cpu_init_crit
+#endif
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+ENTRY(c_runtime_cpu_setup)
+/*
+ * If I-cache is enabled invalidate it
+ */
+#ifndef CONFIG_SYS_ICACHE_OFF
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
+	mcr     p15, 0, r0, c7, c10, 4	@ DSB
+	mcr     p15, 0, r0, c7, c5, 4	@ ISB
+#endif
+/*
+ * Move vector table
+ */
+	/* Set vector address in CP15 VBAR register */
+	ldr     r0, =_start
+	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
+
+	bx	lr
+
+ENDPROC(c_runtime_cpu_setup)
+
+/*************************************************************************
+ *
+ * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+ *	__attribute__((weak));
+ *
+ * Stack pointer is not yet initialized at this moment
+ * Don't save anything to stack even if compiled with -O0
+ *
+ *************************************************************************/
+ENTRY(save_boot_params)
+	bx	lr			@ back to my caller
+ENDPROC(save_boot_params)
+	.weak	save_boot_params
+
+/*************************************************************************
+ *
+ * cpu_init_cp15
+ *
+ * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
+ * CONFIG_SYS_ICACHE_OFF is defined.
+ *
+ *************************************************************************/
+ENTRY(cpu_init_cp15)
+	/*
+	 * Invalidate L1 I/D
+	 */
+	mov	r0, #0			@ set up for MCR
+	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
+	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
+	mcr     p15, 0, r0, c7, c10, 4	@ DSB
+	mcr     p15, 0, r0, c7, c5, 4	@ ISB
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
+	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
+	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
+	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
+#ifdef CONFIG_SYS_ICACHE_OFF
+	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
+#else
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
+#endif
+	mcr	p15, 0, r0, c1, c0, 0
+
+#ifdef CONFIG_ARM_ERRATA_716044
+	mrc	p15, 0, r0, c1, c0, 0	@ read system control register
+	orr	r0, r0, #1 << 11	@ set bit #11
+	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
+#endif
+
+#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 4		@ set bit #4
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_743622
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 6		@ set bit #6
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_751472
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 11	@ set bit #11
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
+#ifdef CONFIG_ARM_ERRATA_761320
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 21	@ set bit #21
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
+
+	mov	pc, lr			@ back to my caller
+ENDPROC(cpu_init_cp15)
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************/
+ENTRY(cpu_init_crit)
+	/*
+	 * Jump to board specific initialization...
+	 * The Mask ROM will have already initialized
+	 * basic memory. Go here to bump up clock rate and handle
+	 * wake up conditions.
+	 */
+	b	lowlevel_init		@ go setup pll,mux,memory
+ENDPROC(cpu_init_crit)
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
+						@ user stack
+	stmia	sp, {r0 - r12}			@ Save user registers (now in
+						@ svc mode) r0-r12
+	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort
+						@ stack
+	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
+						@ and cpsr (into parm regs)
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp				@ save current stack into r0
+						@ (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
+						@ a reserved stack spot would
+						@ be good.
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into
+						@ cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter
+						@ in banked mode)
+
+	str	lr, [r13]			@ save caller lr in position 0
+						@ of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r13, #4]			@ save spsr in position 1 of
+						@ saved stack
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13			@ switch modes, make sure
+						@ moves will execute
+	mov	lr, pc				@ capture return pc
+	movs	pc, lr				@ jump to next instruction &
+						@ switch modes.
+	.endm
+
+	.macro get_bad_stack_swi
+	sub	r13, r13, #4			@ space on current stack for
+						@ scratch reg.
+	str	r0, [r13]			@ save R0's value.
+	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
+						@ spots for abort stack
+	str	lr, [r0]			@ save caller lr in position 0
+						@ of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r0, #4]			@ save spsr in position 1 of
+						@ saved stack
+	ldr	lr, [r0]			@ restore lr
+	ldr	r0, [r13]			@ restore r0
+	add	r13, r13, #4			@ pop stack entry
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack_swi
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effective fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif /* CONFIG_USE_IRQ */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/syslib.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/syslib.c
new file mode 100644
index 000000000..4ae259606
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/syslib.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+/************************************************************
+ * sdelay() - simple spin loop.  Will be constant time as
+ *  its generally used in bypass conditions only.  This
+ *  is necessary until timers are accessible.
+ *
+ *  not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ *   volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+		  u32 bound)
+{
+	u32 i = 0, val;
+	do {
+		++i;
+		val = readl((u32)read_addr) & read_bit_mask;
+		if (val == match_value)
+			return 1;
+		if (i == bound)
+			return 0;
+	} while (1);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra-common/Makefile
new file mode 100644
index 000000000..463c260f1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra-common/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c
new file mode 100644
index 000000000..a94ec93e7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Derived from code (arch/arm/lib/reset.c) that is:
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/pmc.h>
+
+static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	puts("Entering RCM...\n");
+	udelay(50000);
+
+	pmc->pmc_scratch0 = 2;
+	disable_interrupts();
+	reset_cpu(0);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	enterrcm, 1, 0, do_enterrcm,
+	"reset Tegra and enter USB Recovery Mode",
+	""
+);
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra114/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra114/Makefile
new file mode 100644
index 000000000..77e231959
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra114/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+# necessary to create built-in.o
+obj- := __dummy__.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra124/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra124/Makefile
new file mode 100644
index 000000000..9478d447d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra124/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+# necessary to create built-in.o
+obj- := __dummy__.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra20/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra20/Makefile
new file mode 100644
index 000000000..9b4295c72
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra20/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_PWM_TEGRA) += pwm.o
+obj-$(CONFIG_VIDEO_TEGRA) += display.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra20/display.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra20/display.c
new file mode 100644
index 000000000..488f0c639
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra20/display.c
@@ -0,0 +1,393 @@
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/display.h>
+#include <asm/arch/dc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+
+static struct fdt_disp_config config;
+
+static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
+{
+	unsigned h_dda, v_dda;
+	unsigned long val;
+
+	val = readl(&dc->cmd.disp_win_header);
+	val |= WINDOW_A_SELECT;
+	writel(val, &dc->cmd.disp_win_header);
+
+	writel(win->fmt, &dc->win.color_depth);
+
+	clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
+			BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
+
+	val = win->out_x << H_POSITION_SHIFT;
+	val |= win->out_y << V_POSITION_SHIFT;
+	writel(val, &dc->win.pos);
+
+	val = win->out_w << H_SIZE_SHIFT;
+	val |= win->out_h << V_SIZE_SHIFT;
+	writel(val, &dc->win.size);
+
+	val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
+	val |= win->h << V_PRESCALED_SIZE_SHIFT;
+	writel(val, &dc->win.prescaled_size);
+
+	writel(0, &dc->win.h_initial_dda);
+	writel(0, &dc->win.v_initial_dda);
+
+	h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1);
+	v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1);
+
+	val = h_dda << H_DDA_INC_SHIFT;
+	val |= v_dda << V_DDA_INC_SHIFT;
+	writel(val, &dc->win.dda_increment);
+
+	writel(win->stride, &dc->win.line_stride);
+	writel(0, &dc->win.buf_stride);
+
+	val = WIN_ENABLE;
+	if (win->bpp < 24)
+		val |= COLOR_EXPAND;
+	writel(val, &dc->win.win_opt);
+
+	writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
+	writel(win->x, &dc->winbuf.addr_h_offset);
+	writel(win->y, &dc->winbuf.addr_v_offset);
+
+	writel(0xff00, &dc->win.blend_nokey);
+	writel(0xff00, &dc->win.blend_1win);
+
+	val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
+	val |= GENERAL_UPDATE | WIN_A_UPDATE;
+	writel(val, &dc->cmd.state_ctrl);
+}
+
+static void write_pair(struct fdt_disp_config *config, int item, u32 *reg)
+{
+	writel(config->horiz_timing[item] |
+			(config->vert_timing[item] << 16), reg);
+}
+
+static int update_display_mode(struct dc_disp_reg *disp,
+		struct fdt_disp_config *config)
+{
+	unsigned long val;
+	unsigned long rate;
+	unsigned long div;
+
+	writel(0x0, &disp->disp_timing_opt);
+	write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
+	write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
+	write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
+	write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
+
+	writel(config->width | (config->height << 16), &disp->disp_active);
+
+	val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
+	val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
+	writel(val, &disp->data_enable_opt);
+
+	val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
+	val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
+	val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
+	writel(val, &disp->disp_interface_ctrl);
+
+	/*
+	 * The pixel clock divider is in 7.1 format (where the bottom bit
+	 * represents 0.5). Here we calculate the divider needed to get from
+	 * the display clock (typically 600MHz) to the pixel clock. We round
+	 * up or down as requried.
+	 */
+	rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
+	div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
+	debug("Display clock %lu, divider %lu\n", rate, div);
+
+	writel(0x00010001, &disp->shift_clk_opt);
+
+	val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
+	val |= div << SHIFT_CLK_DIVIDER_SHIFT;
+	writel(val, &disp->disp_clk_ctrl);
+
+	return 0;
+}
+
+/* Start up the display and turn on power to PWMs */
+static void basic_init(struct dc_cmd_reg *cmd)
+{
+	u32 val;
+
+	writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
+	writel(0x0000011a, &cmd->cont_syncpt_vsync);
+	writel(0x00000000, &cmd->int_type);
+	writel(0x00000000, &cmd->int_polarity);
+	writel(0x00000000, &cmd->int_mask);
+	writel(0x00000000, &cmd->int_enb);
+
+	val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
+	val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
+	val |= PM1_ENABLE;
+	writel(val, &cmd->disp_pow_ctrl);
+
+	val = readl(&cmd->disp_cmd);
+	val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
+	writel(val, &cmd->disp_cmd);
+}
+
+static void basic_init_timer(struct dc_disp_reg *disp)
+{
+	writel(0x00000020, &disp->mem_high_pri);
+	writel(0x00000001, &disp->mem_high_pri_timer);
+}
+
+static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
+	0x00000000,
+	0x01000000,
+	0x00000000,
+	0x00000000,
+};
+
+static const u32 rgb_data_tab[PIN_REG_COUNT] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00210222,
+	0x00002200,
+	0x00020000,
+};
+
+static void rgb_enable(struct dc_com_reg *com)
+{
+	int i;
+
+	for (i = 0; i < PIN_REG_COUNT; i++) {
+		writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
+		writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
+		writel(rgb_data_tab[i], &com->pin_output_data[i]);
+	}
+
+	for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
+		writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
+}
+
+int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config)
+{
+	win->x = 0;
+	win->y = 0;
+	win->w = config->width;
+	win->h = config->height;
+	win->out_x = 0;
+	win->out_y = 0;
+	win->out_w = config->width;
+	win->out_h = config->height;
+	win->phys_addr = config->frame_buffer;
+	win->stride = config->width * (1 << config->log2_bpp) / 8;
+	debug("%s: depth = %d\n", __func__, config->log2_bpp);
+	switch (config->log2_bpp) {
+	case 5:
+	case 24:
+		win->fmt = COLOR_DEPTH_R8G8B8A8;
+		win->bpp = 32;
+		break;
+	case 4:
+		win->fmt = COLOR_DEPTH_B5G6R5;
+		win->bpp = 16;
+		break;
+
+	default:
+		debug("Unsupported LCD bit depth");
+		return -1;
+	}
+
+	return 0;
+}
+
+struct fdt_disp_config *tegra_display_get_config(void)
+{
+	return config.valid ? &config : NULL;
+}
+
+static void debug_timing(const char *name, unsigned int timing[])
+{
+#ifdef DEBUG
+	int i;
+
+	debug("%s timing: ", name);
+	for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
+		debug("%d ", timing[i]);
+	debug("\n");
+#endif
+}
+
+/**
+ * Decode panel information from the fdt, according to a standard binding
+ *
+ * @param blob		fdt blob
+ * @param node		offset of fdt node to read from
+ * @param config	structure to store fdt config into
+ * @return 0 if ok, -ve on error
+ */
+static int tegra_decode_panel(const void *blob, int node,
+			      struct fdt_disp_config *config)
+{
+	int front, back, ref;
+
+	config->width = fdtdec_get_int(blob, node, "xres", -1);
+	config->height = fdtdec_get_int(blob, node, "yres", -1);
+	config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0);
+	if (!config->pixel_clock || config->width == -1 ||
+			config->height == -1) {
+		debug("%s: Pixel parameters missing\n", __func__);
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	back = fdtdec_get_int(blob, node, "left-margin", -1);
+	front = fdtdec_get_int(blob, node, "right-margin", -1);
+	ref = fdtdec_get_int(blob, node, "hsync-len", -1);
+	if ((back | front | ref) == -1) {
+		debug("%s: Horizontal parameters missing\n", __func__);
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	/* Use a ref-to-sync of 1 always, and take this from the front porch */
+	config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
+	config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
+	config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
+	config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
+		config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
+	debug_timing("horiz", config->horiz_timing);
+
+	back = fdtdec_get_int(blob, node, "upper-margin", -1);
+	front = fdtdec_get_int(blob, node, "lower-margin", -1);
+	ref = fdtdec_get_int(blob, node, "vsync-len", -1);
+	if ((back | front | ref) == -1) {
+		debug("%s: Vertical parameters missing\n", __func__);
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
+	config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
+	config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
+	config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
+		config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
+	debug_timing("vert", config->vert_timing);
+
+	return 0;
+}
+
+/**
+ * Decode the display controller information from the fdt.
+ *
+ * @param blob		fdt blob
+ * @param config	structure to store fdt config into
+ * @return 0 if ok, -ve on error
+ */
+static int tegra_display_decode_config(const void *blob,
+				       struct fdt_disp_config *config)
+{
+	int node, rgb;
+	int bpp, bit;
+
+	/* TODO: Support multiple controllers */
+	node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC);
+	if (node < 0) {
+		debug("%s: Cannot find display controller node in fdt\n",
+		      __func__);
+		return node;
+	}
+	config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	if (!config->disp) {
+		debug("%s: No display controller address\n", __func__);
+		return -1;
+	}
+
+	rgb = fdt_subnode_offset(blob, node, "rgb");
+
+	config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
+	if (!config->panel_node < 0) {
+		debug("%s: Cannot find panel information\n", __func__);
+		return -1;
+	}
+
+	if (tegra_decode_panel(blob, config->panel_node, config)) {
+		debug("%s: Failed to decode panel information\n", __func__);
+		return -1;
+	}
+
+	bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel",
+			     -1);
+	bit = ffs(bpp) - 1;
+	if (bpp == (1 << bit))
+		config->log2_bpp = bit;
+	else
+		config->log2_bpp = bpp;
+	if (bpp == -1) {
+		debug("%s: Pixel bpp parameters missing\n", __func__);
+		return -FDT_ERR_NOTFOUND;
+	}
+	config->bpp = bpp;
+
+	config->valid = 1;	/* we have a valid configuration */
+
+	return 0;
+}
+
+int tegra_display_probe(const void *blob, void *default_lcd_base)
+{
+	struct disp_ctl_win window;
+	struct dc_ctlr *dc;
+
+	if (tegra_display_decode_config(blob, &config))
+		return -1;
+
+	config.frame_buffer = (u32)default_lcd_base;
+
+	dc = (struct dc_ctlr *)config.disp;
+
+	/*
+	 * A header file for clock constants was NAKed upstream.
+	 * TODO: Put this into the FDT and fdt_lcd struct when we have clock
+	 * support there
+	 */
+	clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
+			       144 * 1000000);
+	clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
+			       600 * 1000000);
+	basic_init(&dc->cmd);
+	basic_init_timer(&dc->disp);
+	rgb_enable(&dc->com);
+
+	if (config.pixel_clock)
+		update_display_mode(&dc->disp, &config);
+
+	if (setup_window(&window, &config))
+		return -1;
+
+	update_window(dc, &window);
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra20/pwm.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra20/pwm.c
new file mode 100644
index 000000000..5b886363f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra20/pwm.c
@@ -0,0 +1,86 @@
+/*
+ * Tegra2 pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pwm.h>
+
+struct pwm_info {
+	struct pwm_ctlr *pwm;		/* Registers for our pwm controller */
+	int pwm_node;			/* PWM device tree node */
+} local;
+
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
+{
+	u32 reg;
+
+	assert(channel < PWM_NUM_CHANNELS);
+
+	/* TODO: Can we use clock_adjust_periph_pll_div() here? */
+	clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
+
+	reg = PWM_ENABLE_MASK;
+	reg |= pulse_width << PWM_WIDTH_SHIFT;
+	reg |= freq_divider << PWM_DIVIDER_SHIFT;
+	writel(reg, &local.pwm[channel].control);
+	debug("%s: channel=%d, rate=%d\n", __func__, channel, rate);
+}
+
+int pwm_request(const void *blob, int node, const char *prop_name)
+{
+	int pwm_node;
+	u32 data[3];
+
+	if (fdtdec_get_int_array(blob, node, prop_name, data,
+			ARRAY_SIZE(data))) {
+		debug("%s: Cannot decode PWM property '%s'\n", __func__,
+		      prop_name);
+		return -1;
+	}
+
+	pwm_node = fdt_node_offset_by_phandle(blob, data[0]);
+	if (pwm_node != local.pwm_node) {
+		debug("%s: PWM property '%s' phandle %d not recognised"
+		      "- expecting %d\n", __func__, prop_name, data[0],
+		      local.pwm_node);
+		return -1;
+	}
+	if (data[1] >= PWM_NUM_CHANNELS) {
+		debug("%s: PWM property '%s': invalid channel %u\n", __func__,
+		      prop_name, data[1]);
+		return -1;
+	}
+
+	/*
+	 * TODO: We could maintain a list of requests, but it might not be
+	 * worth it for U-Boot.
+	 */
+	return data[1];
+}
+
+int pwm_init(const void *blob)
+{
+	local.pwm_node = fdtdec_next_compatible(blob, 0,
+						COMPAT_NVIDIA_TEGRA20_PWM);
+	if (local.pwm_node < 0) {
+		debug("%s: Cannot find device tree node\n", __func__);
+		return -1;
+	}
+
+	local.pwm = (struct pwm_ctlr *)fdtdec_get_addr(blob, local.pwm_node,
+						       "reg");
+	if (local.pwm == (struct pwm_ctlr *)FDT_ADDR_T_NONE) {
+		debug("%s: Cannot find pwm reg address\n", __func__);
+		return -1;
+	}
+	debug("Tegra PWM at %p, node %d\n", local.pwm, local.pwm_node);
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra30/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra30/Makefile
new file mode 100644
index 000000000..413eba102
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/tegra30/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+# necessary to create built-in.o
+obj- := __dummy__.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/Makefile
new file mode 100644
index 000000000..fad9d4ae3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= timer.o clock.o prcmu.o cpu.o
+obj-y	+= lowlevel.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/clock.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/clock.c
new file mode 100644
index 000000000..1e3b3d520
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/clock.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2009 ST-Ericsson
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clkrst {
+	unsigned int pcken;
+	unsigned int pckdis;
+	unsigned int kcken;
+	unsigned int kckdis;
+};
+
+static unsigned int clkrst_base[] = {
+	U8500_CLKRST1_BASE,
+	U8500_CLKRST2_BASE,
+	U8500_CLKRST3_BASE,
+	0,
+	U8500_CLKRST5_BASE,
+	U8500_CLKRST6_BASE,
+	U8500_CLKRST7_BASE,	/* ED only */
+};
+
+/* Turn on peripheral clock at PRCC level */
+void u8500_clock_enable(int periph, int cluster, int kern)
+{
+	struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1];
+
+	if (kern != -1)
+		writel(1 << kern, &clkrst->kcken);
+
+	if (cluster != -1)
+		writel(1 << cluster, &clkrst->pcken);
+}
+
+void db8500_clocks_init(void)
+{
+	/*
+	 * Enable all clocks. This is u-boot, we can enable it all. There is no
+	 * powersave in u-boot.
+	 */
+
+	u8500_clock_enable(1, 9, -1); /* GPIO0 */
+	u8500_clock_enable(2, 11, -1);/* GPIO1 */
+	u8500_clock_enable(3, 8, -1); /* GPIO2 */
+	u8500_clock_enable(5, 1, -1); /* GPIO3 */
+	u8500_clock_enable(3, 6, 6);  /* UART2 */
+	u8500_clock_enable(3, 3, 3);  /* I2C0 */
+	u8500_clock_enable(1, 5, 5);  /* SDI0 */
+	u8500_clock_enable(2, 4, 2);  /* SDI4 */
+	u8500_clock_enable(6, 6, -1); /* MTU0 */
+	u8500_clock_enable(3, 4, 4);  /* SDI2 */
+
+	/*
+	 * Enabling clocks for all devices which are AMBA devices in the
+	 * kernel.  Otherwise they will not get probe()'d because the
+	 * peripheral ID register will not be powered.
+	 */
+
+	/* XXX: some of these differ between ED/V1 */
+
+	u8500_clock_enable(1, 1, 1);  /* UART1 */
+	u8500_clock_enable(1, 0, 0);  /* UART0 */
+	u8500_clock_enable(3, 2, 2);  /* SSP1 */
+	u8500_clock_enable(3, 1, 1);  /* SSP0 */
+	u8500_clock_enable(2, 8, -1); /* SPI0 */
+	u8500_clock_enable(2, 5, 3);  /* MSP2 */
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/cpu.c
new file mode 100644
index 000000000..d8634bebb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/cpu.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2012 Linaro Limited
+ * Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * Based on original code from Joakim Axelsson at ST-Ericsson
+ * (C) Copyright 2010 ST-Ericsson
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/prcmu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+
+#include <asm/arch/hardware.h>
+
+#define CPUID_DB8500V1		0x411fc091
+#define CPUID_DB8500V2		0x412fc091
+#define ASICID_DB8500V11	0x008500A1
+
+#define CACHE_CONTR_BASE	0xA0412000
+/* Cache controller register offsets
+ * as found in ARM's technical reference manual
+ */
+#define CACHE_INVAL_BY_WAY	(CACHE_CONTR_BASE + 0x77C)
+#define CACHE_LOCKDOWN_BY_D	(CACHE_CONTR_BASE + 0X900)
+#define CACHE_LOCKDOWN_BY_I	(CACHE_CONTR_BASE + 0X904)
+
+static unsigned int read_asicid(void);
+
+static inline unsigned int read_cpuid(void)
+{
+	unsigned int val;
+
+	/* Main ID register (MIDR) */
+	asm("mrc        p15, 0, %0, c0, c0, 0"
+	   : "=r" (val)
+	   :
+	   : "cc");
+
+	return val;
+}
+
+static int cpu_is_u8500v11(void)
+{
+	return read_asicid() == ASICID_DB8500V11;
+}
+
+static int cpu_is_u8500v2(void)
+{
+	return read_cpuid() == CPUID_DB8500V2;
+}
+
+static unsigned int read_asicid(void)
+{
+	unsigned int *address;
+
+	if (cpu_is_u8500v2())
+		address = (void *) U8500_ASIC_ID_LOC_V2;
+	else
+		address = (void *) U8500_ASIC_ID_LOC_ED_V1;
+
+	return readl(address);
+}
+
+void cpu_cache_initialization(void)
+{
+	unsigned int value;
+	/* invalidate all cache entries */
+	writel(0xFFFF, CACHE_INVAL_BY_WAY);
+
+	/* ways are set to '0' when they are totally
+	 * cleaned and invalidated
+	 */
+	do {
+		value = readl(CACHE_INVAL_BY_WAY);
+	} while (value & 0xFF);
+
+	/* Invalidate register 9 D and I lockdown */
+	writel(0xFF, CACHE_LOCKDOWN_BY_D);
+	writel(0xFF, CACHE_LOCKDOWN_BY_I);
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+/*
+ * SOC specific cpu init
+ */
+int arch_cpu_init(void)
+{
+	db8500_prcmu_init();
+	db8500_clocks_init();
+
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+#ifdef CONFIG_MMC
+
+int u8500_mmc_power_init(void)
+{
+	int ret;
+	int enable, voltage;
+	int ab8500_revision;
+
+	if (!cpu_is_u8500v11() && !cpu_is_u8500v2())
+		return 0;
+
+	/* Get AB8500 revision */
+	ret = ab8500_read(AB8500_MISC, AB8500_REV_REG);
+	if (ret < 0)
+		goto out;
+
+	ab8500_revision = ret;
+
+	/*
+	 * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
+	 * card to work.  This is done by enabling the regulators in the AB8500
+	 * via PRCMU I2C transactions.
+	 *
+	 * This code is derived from the handling of AB8500_LDO_VAUX3 in
+	 * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
+	 *
+	 * Turn off and delay is required to have it work across soft reboots.
+	 */
+
+	/* Turn off (read-modify-write) */
+	ret = ab8500_read(AB8500_REGU_CTRL2,
+				AB8500_REGU_VRF1VAUX3_REGU_REG);
+	if (ret < 0)
+		goto out;
+
+	enable = ret;
+
+	/* Turn off */
+	ret = ab8500_write(AB8500_REGU_CTRL2,
+			AB8500_REGU_VRF1VAUX3_REGU_REG,
+			enable & ~LDO_VAUX3_ENABLE_MASK);
+	if (ret < 0)
+		goto out;
+
+	udelay(10 * 1000);
+
+	/* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */
+	ret = ab8500_read(AB8500_REGU_CTRL2,
+			AB8500_REGU_VRF1VAUX3_SEL_REG);
+	if (ret < 0)
+		goto out;
+
+	voltage = ret;
+
+	if (ab8500_revision < 0x20) {
+		voltage &= ~LDO_VAUX3_SEL_MASK;
+		voltage |= LDO_VAUX3_SEL_2V9;
+	} else {
+		voltage &= ~LDO_VAUX3_V2_SEL_MASK;
+		voltage |= LDO_VAUX3_V2_SEL_2V91;
+	}
+
+	ret = ab8500_write(AB8500_REGU_CTRL2,
+			AB8500_REGU_VRF1VAUX3_SEL_REG, voltage);
+	if (ret < 0)
+		goto out;
+
+	/* Turn on the supply */
+	enable &= ~LDO_VAUX3_ENABLE_MASK;
+	enable |= LDO_VAUX3_ENABLE_VAL;
+
+	ret = ab8500_write(AB8500_REGU_CTRL2,
+			AB8500_REGU_VRF1VAUX3_REGU_REG, enable);
+
+out:
+	return ret;
+}
+#endif /* CONFIG_MMC */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/lowlevel.S b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/lowlevel.S
new file mode 100644
index 000000000..d3e392060
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/lowlevel.S
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2011 ST-Ericsson
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	mov	pc, lr
+ENDPROC(lowlevel_init)
+
+	.align	5
+ENTRY(reset_cpu)
+	ldr r0, =CFG_PRCMU_BASE
+	ldr r1, =0x1
+	str r1, [r0, #0x228]
+_loop_forever:
+	b	_loop_forever
+ENDPROC(reset_cpu)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/prcmu.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/prcmu.c
new file mode 100644
index 000000000..26ffdc2e0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/prcmu.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson SA
+ *
+ * Adapted from the Linux version:
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * NOTE: This currently does not support the I2C workaround access method.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/prcmu.h>
+
+/* CPU mailbox registers */
+#define PRCMU_I2C_WRITE(slave)  \
+	(((slave) << 1) | I2CWRITE | (1 << 6))
+#define PRCMU_I2C_READ(slave) \
+	(((slave) << 1) | I2CREAD | (1 << 6))
+
+#define I2C_MBOX_BIT    (1 << 5)
+
+static int prcmu_is_ready(void)
+{
+	int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
+	if (!ready)
+		printf("PRCMU firmware not ready\n");
+	return ready;
+}
+
+static int wait_for_i2c_mbx_rdy(void)
+{
+	int timeout = 10000;
+
+	if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) {
+		printf("prcmu: warning i2c mailbox was not acked\n");
+		/* clear mailbox 5 ack irq */
+		writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
+	}
+
+	/* check any already on-going transaction */
+	while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout)
+		timeout--;
+
+	if (timeout == 0)
+		return -1;
+
+	return 0;
+}
+
+static int wait_for_i2c_req_done(void)
+{
+	int timeout = 10000;
+
+	/* Set an interrupt to XP70 */
+	writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET);
+
+	/* wait for mailbox 5 (i2c) ack */
+	while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout)
+		timeout--;
+
+	if (timeout == 0)
+		return -1;
+
+	return 0;
+}
+
+/**
+ * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C
+ * @reg: - db8500 register bank to be accessed
+ * @slave:  - db8500 register to be accessed
+ * Returns: ACK_MB5  value containing the status
+ */
+int prcmu_i2c_read(u8 reg, u16 slave)
+{
+	uint8_t i2c_status;
+	uint8_t i2c_val;
+	int ret;
+
+	if (!prcmu_is_ready())
+		return -1;
+
+	debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n",
+			reg, slave);
+
+	ret = wait_for_i2c_mbx_rdy();
+	if (ret) {
+		printf("prcmu_i2c_read: mailbox became not ready\n");
+		return ret;
+	}
+
+	/* prepare the data for mailbox 5 */
+	writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
+	writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
+	writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
+	writeb(0, PRCM_REQ_MB5_I2CVAL);
+
+	ret = wait_for_i2c_req_done();
+	if (ret) {
+		printf("prcmu_i2c_read: mailbox request timed out\n");
+		return ret;
+	}
+
+	/* retrieve values */
+	debug("ack-mb5:transfer status = %x\n",
+			readb(PRCM_ACK_MB5_STATUS));
+	debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
+	debug("ack-mb5:slave_add = %x\n",
+			readb(PRCM_ACK_MB5_SLAVE));
+	debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
+
+	i2c_status = readb(PRCM_ACK_MB5_STATUS);
+	i2c_val = readb(PRCM_ACK_MB5_VAL);
+	/* clear mailbox 5 ack irq */
+	writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
+
+	if (i2c_status == I2C_RD_OK)
+		return i2c_val;
+
+	printf("prcmu_i2c_read:read return status= %d\n", i2c_status);
+	return -1;
+}
+
+/**
+ * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C
+ * @reg: - db8500 register bank to be accessed
+ * @slave:  - db800 register to be written to
+ * @reg_data: - the data to write
+ * Returns: ACK_MB5 value containing the status
+ */
+int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
+{
+	uint8_t i2c_status;
+	int ret;
+
+	if (!prcmu_is_ready())
+		return -1;
+
+	debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n",
+			reg, slave);
+
+	ret = wait_for_i2c_mbx_rdy();
+	if (ret) {
+		printf("prcmu_i2c_write: mailbox became not ready\n");
+		return ret;
+	}
+
+	/* prepare the data for mailbox 5 */
+	writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
+	writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
+	writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
+	writeb(reg_data, PRCM_REQ_MB5_I2CVAL);
+
+	ret = wait_for_i2c_req_done();
+	if (ret) {
+		printf("prcmu_i2c_write: mailbox request timed out\n");
+		return ret;
+	}
+
+	/* retrieve values */
+	debug("ack-mb5:transfer status = %x\n",
+			readb(PRCM_ACK_MB5_STATUS));
+	debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
+	debug("ack-mb5:slave_add = %x\n",
+			readb(PRCM_ACK_MB5_SLAVE));
+	debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
+
+	i2c_status = readb(PRCM_ACK_MB5_STATUS);
+	debug("\ni2c_status = %x\n", i2c_status);
+	/* clear mailbox 5 ack irq */
+	writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
+
+	if (i2c_status == I2C_WR_OK)
+		return 0;
+
+	printf("%s: i2c_status : 0x%x\n", __func__, i2c_status);
+	return -1;
+}
+
+void u8500_prcmu_enable(u32 *reg)
+{
+	writel(readl(reg) | (1 << 8), reg);
+}
+
+void db8500_prcmu_init(void)
+{
+	/* Enable timers */
+	writel(1 << 17, PRCM_TCR);
+
+	u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG);
+	u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG);
+	u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG);
+	/* PER4CLK does not exist */
+	u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG);
+	u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG);
+	/* Only exists in ED but is always ok to write to */
+	u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG);
+
+	u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG);
+	u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG);
+
+	u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG);
+
+	/* Clean up the mailbox interrupts after pre-u-boot code. */
+	writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/timer.c
new file mode 100644
index 000000000..6b74e13d9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/u8500/timer.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2010 Linaro Limited
+ * John Rigby <john.rigby@linaro.org>
+ *
+ * Based on original from Linux kernel source and
+ * internal ST-Ericsson U-Boot source.
+ * (C) Copyright 2009 Alessandro Rubini
+ * (C) Copyright 2010 ST-Ericsson
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The MTU device has some interrupt control registers
+ * followed by 4 timers.
+ */
+
+/* The timers */
+struct u8500_mtu_timer {
+	u32 lr;			/* Load value */
+	u32 cv;			/* Current value */
+	u32 cr;			/* Control reg */
+	u32 bglr;		/* ??? */
+};
+
+/* The MTU that contains the timers */
+struct u8500_mtu {
+	u32 imsc;		/* Interrupt mask set/clear */
+	u32 ris;		/* Raw interrupt status */
+	u32 mis;		/* Masked interrupt status */
+	u32 icr;		/* Interrupt clear register */
+	struct u8500_mtu_timer pt[4];
+};
+
+/* bits for the control register */
+#define MTU_CR_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR */
+#define MTU_CR_32BITS		0x02
+
+#define MTU_CR_PRESCALE_1	0x00
+#define MTU_CR_PRESCALE_16	0x04
+#define MTU_CR_PRESCALE_256	0x08
+#define MTU_CR_PRESCALE_MASK	0x0c
+
+#define MTU_CR_PERIODIC		0x40	/* if 0 = free-running */
+#define MTU_CR_ENA		0x80
+
+/*
+ * The MTU is clocked at 133 MHz by default. (V1 and later)
+ */
+#define TIMER_CLOCK		(133 * 1000 * 1000 / 16)
+#define COUNT_TO_USEC(x)	((x) * 16 / 133)
+#define USEC_TO_COUNT(x)	((x) * 133 / 16)
+#define TICKS_PER_HZ		(TIMER_CLOCK / CONFIG_SYS_HZ)
+#define TICKS_TO_HZ(x)		((x) / TICKS_PER_HZ)
+#define TIMER_LOAD_VAL		0xffffffff
+
+/*
+ * MTU timer to use (from 0 to 3).
+ */
+#define MTU_TIMER 2
+
+static struct u8500_mtu_timer *timer_base =
+	&((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER];
+
+/* macro to read the 32 bit timer: since it decrements, we invert read value */
+#define READ_TIMER() (~readl(&timer_base->cv))
+
+/* Configure a free-running, auto-wrap counter with /16 prescaler */
+int timer_init(void)
+{
+	writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS,
+	       &timer_base->cr);
+	return 0;
+}
+
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = TICKS_TO_HZ(READ_TIMER());
+
+	if (now >= gd->arch.lastinc) {	/* normal (non rollover) */
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	} else {			/* rollover */
+		gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) -
+					gd->arch.lastinc) + now;
+	}
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
+}
+
+/* Delay x useconds */
+void __udelay(ulong usec)
+{
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	ulong now, last = READ_TIMER();
+
+	while (tmo > 0) {
+		now = READ_TIMER();
+		if (now > last)	/* normal (non rollover) */
+			tmo -= now - last;
+		else		/* rollover */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		last = now;
+	}
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * Emulation of Power architecture long long timebase.
+ *
+ * TODO: Support gd->arch.tbu for real long long timebase.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * Emulation of Power architecture timebase.
+ * NB: Low resolution compared to Power tbclk.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/vf610/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/vf610/Makefile
new file mode 100644
index 000000000..68cb756d6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/vf610/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= generic.o
+obj-y	+= timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/vf610/generic.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/vf610/generic.c
new file mode 100644
index 000000000..a26d63ebe
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/vf610/generic.c
@@ -0,0 +1,318 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <netdev.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	u32 reg;
+
+	reg = readl(&ccm->ccgr6);
+	if (enable)
+		reg |= CCM_CCGR6_OCOTP_CTRL_MASK;
+	else
+		reg &= ~CCM_CCGR6_OCOTP_CTRL_MASK;
+	writel(reg, &ccm->ccgr6);
+}
+#endif
+
+static u32 get_mcu_main_clk(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	u32 ccm_ccsr, ccm_cacrr, armclk_div;
+	u32 sysclk_sel, pll_pfd_sel = 0;
+	u32 freq = 0;
+
+	ccm_ccsr = readl(&ccm->ccsr);
+	sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
+	sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
+
+	ccm_cacrr = readl(&ccm->cacrr);
+	armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
+	armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
+	armclk_div += 1;
+
+	switch (sysclk_sel) {
+	case 0:
+		freq = FASE_CLK_FREQ;
+		break;
+	case 1:
+		freq = SLOW_CLK_FREQ;
+		break;
+	case 2:
+		pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
+		pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
+		if (pll_pfd_sel == 0)
+			freq = PLL2_MAIN_FREQ;
+		else if (pll_pfd_sel == 1)
+			freq = PLL2_PFD1_FREQ;
+		else if (pll_pfd_sel == 2)
+			freq = PLL2_PFD2_FREQ;
+		else if (pll_pfd_sel == 3)
+			freq = PLL2_PFD3_FREQ;
+		else if (pll_pfd_sel == 4)
+			freq = PLL2_PFD4_FREQ;
+		break;
+	case 3:
+		freq = PLL2_MAIN_FREQ;
+		break;
+	case 4:
+		pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
+		pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
+		if (pll_pfd_sel == 0)
+			freq = PLL1_MAIN_FREQ;
+		else if (pll_pfd_sel == 1)
+			freq = PLL1_PFD1_FREQ;
+		else if (pll_pfd_sel == 2)
+			freq = PLL1_PFD2_FREQ;
+		else if (pll_pfd_sel == 3)
+			freq = PLL1_PFD3_FREQ;
+		else if (pll_pfd_sel == 4)
+			freq = PLL1_PFD4_FREQ;
+		break;
+	case 5:
+		freq = PLL3_MAIN_FREQ;
+		break;
+	default:
+		printf("unsupported system clock select\n");
+	}
+
+	return freq / armclk_div;
+}
+
+static u32 get_bus_clk(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	u32 ccm_cacrr, busclk_div;
+
+	ccm_cacrr = readl(&ccm->cacrr);
+
+	busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
+	busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
+	busclk_div += 1;
+
+	return get_mcu_main_clk() / busclk_div;
+}
+
+static u32 get_ipg_clk(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	u32 ccm_cacrr, ipgclk_div;
+
+	ccm_cacrr = readl(&ccm->cacrr);
+
+	ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
+	ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
+	ipgclk_div += 1;
+
+	return get_bus_clk() / ipgclk_div;
+}
+
+static u32 get_uart_clk(void)
+{
+	return get_ipg_clk();
+}
+
+static u32 get_sdhc_clk(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
+	u32 freq = 0;
+
+	ccm_cscmr1 = readl(&ccm->cscmr1);
+	sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
+	sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
+
+	ccm_cscdr2 = readl(&ccm->cscdr2);
+	sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
+	sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
+	sdhc_clk_div += 1;
+
+	switch (sdhc_clk_sel) {
+	case 0:
+		freq = PLL3_MAIN_FREQ;
+		break;
+	case 1:
+		freq = PLL3_PFD3_FREQ;
+		break;
+	case 2:
+		freq = PLL1_PFD3_FREQ;
+		break;
+	case 3:
+		freq = get_bus_clk();
+		break;
+	}
+
+	return freq / sdhc_clk_div;
+}
+
+u32 get_fec_clk(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	u32 ccm_cscmr2, rmii_clk_sel;
+	u32 freq = 0;
+
+	ccm_cscmr2 = readl(&ccm->cscmr2);
+	rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
+	rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
+
+	switch (rmii_clk_sel) {
+	case 0:
+		freq = ENET_EXTERNAL_CLK;
+		break;
+	case 1:
+		freq = AUDIO_EXTERNAL_CLK;
+		break;
+	case 2:
+		freq = PLL5_MAIN_FREQ;
+		break;
+	case 3:
+		freq = PLL5_MAIN_FREQ / 2;
+		break;
+	}
+
+	return freq;
+}
+
+static u32 get_i2c_clk(void)
+{
+	return get_ipg_clk();
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return get_mcu_main_clk();
+	case MXC_BUS_CLK:
+		return get_bus_clk();
+	case MXC_IPG_CLK:
+		return get_ipg_clk();
+	case MXC_UART_CLK:
+		return get_uart_clk();
+	case MXC_ESDHC_CLK:
+		return get_sdhc_clk();
+	case MXC_FEC_CLK:
+		return get_fec_clk();
+	case MXC_I2C_CLK:
+		return get_i2c_clk();
+	default:
+		break;
+	}
+	return -1;
+}
+
+/* Dump some core clocks */
+int do_vf610_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+			 char * const argv[])
+{
+	printf("\n");
+	printf("cpu clock : %8d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("bus clock : %8d MHz\n", mxc_get_clock(MXC_BUS_CLK) / 1000000);
+	printf("ipg clock : %8d MHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000000);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks, CONFIG_SYS_MAXARGS, 1, do_vf610_showclocks,
+	"display clocks",
+	""
+);
+
+#ifdef CONFIG_FEC_MXC
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[4];
+	struct fuse_bank4_regs *fuse =
+		(struct fuse_bank4_regs *)bank->fuse_regs;
+
+	u32 value = readl(&fuse->mac_addr0);
+	mac[0] = (value >> 8);
+	mac[1] = value;
+
+	value = readl(&fuse->mac_addr1);
+	mac[2] = value >> 24;
+	mac[3] = value >> 16;
+	mac[4] = value >> 8;
+	mac[5] = value;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+	u32 cause;
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+	cause = readl(&src_regs->srsr);
+	writel(cause, &src_regs->srsr);
+	cause &= 0xff;
+
+	switch (cause) {
+	case 0x08:
+		return "WDOG";
+	case 0x20:
+		return "JTAG HIGH-Z";
+	case 0x80:
+		return "EXTERNAL RESET";
+	case 0xfd:
+		return "POR";
+	default:
+		return "unknown reset";
+	}
+}
+
+int print_cpuinfo(void)
+{
+	printf("CPU:   Freescale Vybrid VF610 at %d MHz\n",
+		mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("Reset cause: %s\n", get_reset_cause());
+
+	return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+	rc = fecmxc_initialize(bis);
+#endif
+
+	return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/vf610/timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/vf610/timer.c
new file mode 100644
index 000000000..e51c6c6a2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/vf610/timer.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+static struct pit_reg *cur_pit = (struct pit_reg *)PIT_BASE_ADDR;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, mxc_get_clock(MXC_IPG_CLK));
+
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+	usec = usec * mxc_get_clock(MXC_IPG_CLK)  + 999999;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+int timer_init(void)
+{
+	__raw_writel(0, &cur_pit->mcr);
+
+	__raw_writel(TIMER_LOAD_VAL, &cur_pit->ldval1);
+	__raw_writel(0, &cur_pit->tctrl1);
+	__raw_writel(1, &cur_pit->tctrl1);
+
+	gd->arch.tbl = 0;
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	ulong now = TIMER_LOAD_VAL - __raw_readl(&cur_pit->cval1);
+
+	/* increment tbu if tbl has rolled over */
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
+
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+	unsigned long long start;
+	ulong tmo;
+
+	start = get_ticks();			/* get current timestamp */
+	tmo = us_to_tick(usec);			/* convert usecs to ticks */
+	while ((get_ticks() - start) < tmo)
+		;				/* loop till time has passed */
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return mxc_get_clock(MXC_IPG_CLK);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/virt-v7.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/virt-v7.c
new file mode 100644
index 000000000..2cd604f97
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/virt-v7.c
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2013
+ * Andre Przywara, Linaro <andre.przywara@linaro.org>
+ *
+ * Routines to transition ARMv7 processors from secure into non-secure state
+ * and from non-secure SVC into HYP mode
+ * needed to enable ARMv7 virtualization for current hypervisors
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/gic.h>
+#include <asm/io.h>
+
+unsigned long gic_dist_addr;
+
+static unsigned int read_cpsr(void)
+{
+	unsigned int reg;
+
+	asm volatile ("mrs %0, cpsr\n" : "=r" (reg));
+	return reg;
+}
+
+static unsigned int read_id_pfr1(void)
+{
+	unsigned int reg;
+
+	asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
+	return reg;
+}
+
+static unsigned long get_gicd_base_address(void)
+{
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+	return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
+#else
+	unsigned midr;
+	unsigned periphbase;
+
+	/* check whether we are an Cortex-A15 or A7.
+	 * The actual HYP switch should work with all CPUs supporting
+	 * the virtualization extension, but we need the GIC address,
+	 * which we know only for sure for those two CPUs.
+	 */
+	asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
+	switch (midr & MIDR_PRIMARY_PART_MASK) {
+	case MIDR_CORTEX_A9_R0P1:
+	case MIDR_CORTEX_A15_R0P0:
+	case MIDR_CORTEX_A7_R0P0:
+		break;
+	default:
+		printf("nonsec: could not determine GIC address.\n");
+		return -1;
+	}
+
+	/* get the GIC base address from the CBAR register */
+	asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
+
+	/* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
+	 * encode this). Bail out here since we cannot access this without
+	 * enabling paging.
+	 */
+	if ((periphbase & 0xff) != 0) {
+		printf("nonsec: PERIPHBASE is above 4 GB, no access.\n");
+		return -1;
+	}
+
+	return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
+#endif
+}
+
+static void kick_secondary_cpus_gic(unsigned long gicdaddr)
+{
+	/* kick all CPUs (except this one) by writing to GICD_SGIR */
+	writel(1U << 24, gicdaddr + GICD_SGIR);
+}
+
+void __weak smp_kick_all_cpus(void)
+{
+	kick_secondary_cpus_gic(gic_dist_addr);
+}
+
+int armv7_switch_hyp(void)
+{
+	unsigned int reg;
+
+	/* check whether we are in HYP mode already */
+	if ((read_cpsr() & 0x1f) == 0x1a) {
+		debug("CPU already in HYP mode\n");
+		return 0;
+	}
+
+	/* check whether the CPU supports the virtualization extensions */
+	reg = read_id_pfr1();
+	if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) {
+		printf("HYP mode: Virtualization extensions not implemented.\n");
+		return -1;
+	}
+
+	/* call the HYP switching code on this CPU also */
+	_switch_to_hyp();
+
+	if ((read_cpsr() & 0x1F) != 0x1a) {
+		printf("HYP mode: switch not successful.\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int armv7_switch_nonsec(void)
+{
+	unsigned int reg;
+	unsigned itlinesnr, i;
+
+	/* check whether the CPU supports the security extensions */
+	reg = read_id_pfr1();
+	if ((reg & 0xF0) == 0) {
+		printf("nonsec: Security extensions not implemented.\n");
+		return -1;
+	}
+
+	/* the SCR register will be set directly in the monitor mode handler,
+	 * according to the spec one should not tinker with it in secure state
+	 * in SVC mode. Do not try to read it once in non-secure state,
+	 * any access to it will trap.
+	 */
+
+	gic_dist_addr = get_gicd_base_address();
+	if (gic_dist_addr == -1)
+		return -1;
+
+	/* enable the GIC distributor */
+	writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
+	       gic_dist_addr + GICD_CTLR);
+
+	/* TYPER[4:0] contains an encoded number of available interrupts */
+	itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
+
+	/* set all bits in the GIC group registers to one to allow access
+	 * from non-secure state. The first 32 interrupts are private per
+	 * CPU and will be set later when enabling the GIC for each core
+	 */
+	for (i = 1; i <= itlinesnr; i++)
+		writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
+
+	smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
+	smp_kick_all_cpus();
+
+	/* call the non-sec switching code on this CPU also */
+	_nonsec_init();
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/Makefile
new file mode 100644
index 000000000..3363a3c71
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/Makefile
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= timer.o
+obj-y	+= cpu.o
+obj-y	+= ddrc.o
+obj-y	+= slcr.o
+obj-y	+= clk.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/clk.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/clk.c
new file mode 100644
index 000000000..d2885dc2b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/clk.c
@@ -0,0 +1,664 @@
+/*
+ * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
+ * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+
+/* Board oscillator frequency */
+#ifndef CONFIG_ZYNQ_PS_CLK_FREQ
+# define CONFIG_ZYNQ_PS_CLK_FREQ	33333333UL
+#endif
+
+/* Register bitfield defines */
+#define PLLCTRL_FBDIV_MASK	0x7f000
+#define PLLCTRL_FBDIV_SHIFT	12
+#define PLLCTRL_BPFORCE_MASK	(1 << 4)
+#define PLLCTRL_PWRDWN_MASK	2
+#define PLLCTRL_PWRDWN_SHIFT	1
+#define PLLCTRL_RESET_MASK	1
+#define PLLCTRL_RESET_SHIFT	0
+
+#define ZYNQ_CLK_MAXDIV		0x3f
+#define CLK_CTRL_DIV1_SHIFT	20
+#define CLK_CTRL_DIV1_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
+#define CLK_CTRL_DIV0_SHIFT	8
+#define CLK_CTRL_DIV0_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
+#define CLK_CTRL_SRCSEL_SHIFT	4
+#define CLK_CTRL_SRCSEL_MASK	(0x3 << CLK_CTRL_SRCSEL_SHIFT)
+
+#define CLK_CTRL_DIV2X_SHIFT	26
+#define CLK_CTRL_DIV2X_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
+#define CLK_CTRL_DIV3X_SHIFT	20
+#define CLK_CTRL_DIV3X_MASK	(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
+
+#define ZYNQ_CLKMUX_SEL_0	0
+#define ZYNQ_CLKMUX_SEL_1	1
+#define ZYNQ_CLKMUX_SEL_2	2
+#define ZYNQ_CLKMUX_SEL_3	3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clk;
+
+/**
+ * struct clk_ops:
+ * @set_rate:	Function pointer to set_rate() implementation
+ * @get_rate:	Function pointer to get_rate() implementation
+ */
+struct clk_ops {
+	int (*set_rate)(struct clk *clk, unsigned long rate);
+	unsigned long (*get_rate)(struct clk *clk);
+};
+
+/**
+ * struct clk:
+ * @name:	Clock name
+ * @frequency:	Currenct frequency
+ * @parent:	Parent clock
+ * @flags:	Clock flags
+ * @reg:	Clock control register
+ * @ops:	Clock operations
+ */
+struct clk {
+	char		*name;
+	unsigned long	frequency;
+	enum zynq_clk	parent;
+	unsigned int	flags;
+	u32		*reg;
+	struct clk_ops	ops;
+};
+#define ZYNQ_CLK_FLAGS_HAS_2_DIVS	1
+
+static struct clk clks[clk_max];
+
+/**
+ * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
+ * @srcsel:	Mux select value
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
+{
+	unsigned int ret;
+
+	switch (srcsel) {
+	case ZYNQ_CLKMUX_SEL_0:
+	case ZYNQ_CLKMUX_SEL_1:
+		ret = armpll_clk;
+		break;
+	case ZYNQ_CLKMUX_SEL_2:
+		ret = ddrpll_clk;
+		break;
+	case ZYNQ_CLKMUX_SEL_3:
+		ret = iopll_clk;
+		break;
+	default:
+		ret = armpll_clk;
+		break;
+	}
+
+	return ret;
+}
+
+/**
+ * ddr2x_get_rate() - Get clock rate of DDR2x clock
+ * @clk:	Clock handle
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long ddr2x_get_rate(struct clk *clk)
+{
+	u32 clk_ctrl = readl(clk->reg);
+	u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
+
+	return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
+}
+
+/**
+ * ddr3x_get_rate() - Get clock rate of DDR3x clock
+ * @clk:	Clock handle
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long ddr3x_get_rate(struct clk *clk)
+{
+	u32 clk_ctrl = readl(clk->reg);
+	u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
+
+	return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
+}
+
+static void init_ddr_clocks(void)
+{
+	u32 div0, div1;
+	unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
+	u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
+
+	/* DDR2x */
+	clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
+	clks[ddr2x_clk].parent = ddrpll_clk;
+	clks[ddr2x_clk].name = "ddr_2x";
+	clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
+	clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
+
+	/* DDR3x */
+	clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
+	clks[ddr3x_clk].parent = ddrpll_clk;
+	clks[ddr3x_clk].name = "ddr_3x";
+	clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
+	clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
+
+	/* DCI */
+	clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
+	div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
+	clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
+	clks[dci_clk].parent = ddrpll_clk;
+	clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
+			DIV_ROUND_CLOSEST(prate, div0), div1);
+	clks[dci_clk].name = "dci";
+
+	gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
+}
+
+static void init_cpu_clocks(void)
+{
+	int clk_621;
+	u32 reg, div, srcsel;
+	enum zynq_clk parent;
+
+	reg = readl(&slcr_base->arm_clk_ctrl);
+	clk_621 = readl(&slcr_base->clk_621_true) & 1;
+	div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+	parent = __zynq_clk_cpu_get_parent(srcsel);
+
+	/* cpu clocks */
+	clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
+	clks[cpu_6or4x_clk].parent = parent;
+	clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
+			zynq_clk_get_rate(parent), div);
+	clks[cpu_6or4x_clk].name = "cpu_6or4x";
+
+	clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
+	clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
+	clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
+	clks[cpu_3or2x_clk].name = "cpu_3or2x";
+
+	clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
+	clks[cpu_2x_clk].parent = cpu_6or4x_clk;
+	clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
+			(2 + clk_621);
+	clks[cpu_2x_clk].name = "cpu_2x";
+
+	clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
+	clks[cpu_1x_clk].parent = cpu_6or4x_clk;
+	clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
+			(4 + 2 * clk_621);
+	clks[cpu_1x_clk].name = "cpu_1x";
+}
+
+/**
+ * periph_calc_two_divs() - Calculate clock dividers
+ * @cur_rate:	Current clock rate
+ * @tgt_rate:	Target clock rate
+ * @prate:	Parent clock rate
+ * @div0:	First divider (output)
+ * @div1:	Second divider (output)
+ * Returns the actual clock rate possible.
+ *
+ * Calculates clock dividers for clocks with two 6-bit dividers.
+ */
+static unsigned long periph_calc_two_divs(unsigned long cur_rate,
+		unsigned long tgt_rate, unsigned long prate, u32 *div0,
+		u32 *div1)
+{
+	long err, best_err = (long)(~0UL >> 1);
+	unsigned long rate, best_rate = 0;
+	u32 d0, d1;
+
+	for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
+		for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
+			rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
+					d1);
+			err = abs(rate - tgt_rate);
+
+			if (err < best_err) {
+				*div0 = d0;
+				*div1 = d1;
+				best_err = err;
+				best_rate = rate;
+			}
+		}
+	}
+
+	return best_rate;
+}
+
+/**
+ * zynq_clk_periph_set_rate() - Set clock rate
+ * @clk:	Handle of the peripheral clock
+ * @rate:	New clock rate
+ * Sets the clock frequency of @clk to @rate. Returns zero on success.
+ */
+static int zynq_clk_periph_set_rate(struct clk *clk,
+		unsigned long rate)
+{
+	u32 ctrl, div0 = 0, div1 = 0;
+	unsigned long prate, new_rate, cur_rate = clk->frequency;
+
+	ctrl = readl(clk->reg);
+	prate = zynq_clk_get_rate(clk->parent);
+	ctrl &= ~CLK_CTRL_DIV0_MASK;
+
+	if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
+		ctrl &= ~CLK_CTRL_DIV1_MASK;
+		new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
+				&div1);
+		ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
+	} else {
+		div0 = DIV_ROUND_CLOSEST(prate, rate);
+		div0 &= ZYNQ_CLK_MAXDIV;
+		new_rate = DIV_ROUND_CLOSEST(rate, div0);
+	}
+
+	/* write new divs to hardware */
+	ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
+	writel(ctrl, clk->reg);
+
+	/* update frequency in clk framework */
+	clk->frequency = new_rate;
+
+	return 0;
+}
+
+/**
+ * zynq_clk_periph_get_rate() - Get clock rate
+ * @clk:	Handle of the peripheral clock
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
+{
+	u32 clk_ctrl = readl(clk->reg);
+	u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	u32 div1 = 1;
+
+	if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
+		div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
+
+	/* a register value of zero == division by 1 */
+	if (!div0)
+		div0 = 1;
+	if (!div1)
+		div1 = 1;
+
+	return
+		DIV_ROUND_CLOSEST(
+			DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
+			div1);
+}
+
+/**
+ * __zynq_clk_periph_get_parent() - Decode clock multiplexer
+ * @srcsel:	Mux select value
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
+{
+	switch (srcsel) {
+	case ZYNQ_CLKMUX_SEL_0:
+	case ZYNQ_CLKMUX_SEL_1:
+		return iopll_clk;
+	case ZYNQ_CLKMUX_SEL_2:
+		return armpll_clk;
+	case ZYNQ_CLKMUX_SEL_3:
+		return ddrpll_clk;
+	default:
+		return 0;
+	}
+}
+
+/**
+ * zynq_clk_periph_get_parent() - Decode clock multiplexer
+ * @clk:	Clock handle
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
+{
+	u32 clk_ctrl = readl(clk->reg);
+	u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+
+	return __zynq_clk_periph_get_parent(srcsel);
+}
+
+/**
+ * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
+ * @clk:	Pointer to struct clk for the clock
+ * @ctrl:	Clock control register
+ * @name:	PLL name
+ * @two_divs:	Indicates whether the clock features one or two dividers
+ */
+static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name,
+		bool two_divs)
+{
+	clk->name = name;
+	clk->reg = ctrl;
+	if (two_divs)
+		clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
+	clk->parent = zynq_clk_periph_get_parent(clk);
+	clk->frequency = zynq_clk_periph_get_rate(clk);
+	clk->ops.get_rate = zynq_clk_periph_get_rate;
+	clk->ops.set_rate = zynq_clk_periph_set_rate;
+
+	return 0;
+}
+
+static void init_periph_clocks(void)
+{
+	zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl,
+				     "gem0", 1);
+	zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl,
+				     "gem1", 1);
+
+	zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl,
+				     "smc", 0);
+
+	zynq_clk_register_periph_clk(&clks[lqspi_clk],
+				     &slcr_base->lqspi_clk_ctrl, "lqspi", 0);
+
+	zynq_clk_register_periph_clk(&clks[sdio0_clk],
+				     &slcr_base->sdio_clk_ctrl, "sdio0", 0);
+	zynq_clk_register_periph_clk(&clks[sdio1_clk],
+				     &slcr_base->sdio_clk_ctrl, "sdio1", 0);
+
+	zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl,
+				     "spi0", 0);
+	zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl,
+				     "spi1", 0);
+
+	zynq_clk_register_periph_clk(&clks[uart0_clk],
+				     &slcr_base->uart_clk_ctrl, "uart0", 0);
+	zynq_clk_register_periph_clk(&clks[uart1_clk],
+				     &slcr_base->uart_clk_ctrl, "uart1", 0);
+
+	zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
+				     &slcr_base->dbg_clk_ctrl, "dbg_trc", 0);
+	zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
+				     &slcr_base->dbg_clk_ctrl, "dbg_apb", 0);
+
+	zynq_clk_register_periph_clk(&clks[pcap_clk],
+				     &slcr_base->pcap_clk_ctrl, "pcap", 0);
+
+	zynq_clk_register_periph_clk(&clks[fclk0_clk],
+				     &slcr_base->fpga0_clk_ctrl, "fclk0", 1);
+	zynq_clk_register_periph_clk(&clks[fclk1_clk],
+				     &slcr_base->fpga1_clk_ctrl, "fclk1", 1);
+	zynq_clk_register_periph_clk(&clks[fclk2_clk],
+				     &slcr_base->fpga2_clk_ctrl, "fclk2", 1);
+	zynq_clk_register_periph_clk(&clks[fclk3_clk],
+				     &slcr_base->fpga3_clk_ctrl, "fclk3", 1);
+}
+
+/**
+ * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
+ * @clk:	Pointer to struct clk for the clock
+ * @ctrl:	Clock control register
+ * @name:	PLL name
+ */
+static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name)
+{
+	clk->name = name;
+	clk->reg = ctrl;
+	clk->parent = cpu_1x_clk;
+	clk->frequency = zynq_clk_get_rate(clk->parent);
+}
+
+static void init_aper_clocks(void)
+{
+	zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "usb0_aper");
+	zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "usb1_aper");
+
+	zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "gem0_aper");
+	zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "gem1_aper");
+
+	zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "sdio0_aper");
+	zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "sdio1_aper");
+
+	zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "spi0_aper");
+	zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "spi1_aper");
+
+	zynq_clk_register_aper_clk(&clks[can0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "can0_aper");
+	zynq_clk_register_aper_clk(&clks[can1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "can1_aper");
+
+	zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "i2c0_aper");
+	zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "i2c1_aper");
+
+	zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "uart0_aper");
+	zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "uart1_aper");
+
+	zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "gpio_aper");
+
+	zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "lqspi_aper");
+
+	zynq_clk_register_aper_clk(&clks[smc_aper_clk],
+				   &slcr_base->aper_clk_ctrl, "smc_aper");
+}
+
+/**
+ * __zynq_clk_pll_get_rate() - Get PLL rate
+ * @addr:	Address of the PLL's control register
+ * Returns the current PLL output rate.
+ */
+static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
+{
+	u32 reg, mul, bypass;
+
+	reg = readl(addr);
+	bypass = reg & PLLCTRL_BPFORCE_MASK;
+	if (bypass)
+		mul = 1;
+	else
+		mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
+
+	return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
+}
+
+/**
+ * zynq_clk_pll_get_rate() - Get PLL rate
+ * @pll:	Handle of the PLL
+ * Returns the current clock rate of @pll.
+ */
+static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
+{
+	return __zynq_clk_pll_get_rate(pll->reg);
+}
+
+/**
+ * zynq_clk_register_pll() - Set up a PLL with the framework
+ * @clk:	Pointer to struct clk for the PLL
+ * @ctrl:	PLL control register
+ * @name:	PLL name
+ * @prate:	PLL input clock rate
+ */
+static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name,
+		unsigned long prate)
+{
+	clk->name = name;
+	clk->reg = ctrl;
+	clk->frequency = zynq_clk_pll_get_rate(clk);
+	clk->ops.get_rate = zynq_clk_pll_get_rate;
+}
+
+/**
+ * clkid_2_register() - Get clock control register
+ * @id:	Clock identifier of one of the PLLs
+ * Returns the address of the requested PLL's control register.
+ */
+static u32 *clkid_2_register(enum zynq_clk id)
+{
+	switch (id) {
+	case armpll_clk:
+		return &slcr_base->arm_pll_ctrl;
+	case ddrpll_clk:
+		return &slcr_base->ddr_pll_ctrl;
+	case iopll_clk:
+		return &slcr_base->io_pll_ctrl;
+	default:
+		return &slcr_base->io_pll_ctrl;
+	}
+}
+
+/* API */
+/**
+ * zynq_clk_early_init() - Early init for the clock framework
+ *
+ * This function is called from before relocation and sets up the CPU clock
+ * frequency in the global data struct.
+ */
+void zynq_clk_early_init(void)
+{
+	u32 reg = readl(&slcr_base->arm_clk_ctrl);
+	u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+	enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
+	u32 *pllreg = clkid_2_register(parent);
+	unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
+
+	if (!div)
+		div = 1;
+
+	gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
+}
+
+/**
+ * get_uart_clk() - Get UART input frequency
+ * @dev_index:	UART ID
+ * Returns UART input clock frequency in Hz.
+ *
+ * Compared to zynq_clk_get_rate() this function is designed to work before
+ * relocation and can be called when the serial UART is set up.
+ */
+unsigned long get_uart_clk(int dev_index)
+{
+	u32 reg = readl(&slcr_base->uart_clk_ctrl);
+	u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+	u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+	enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
+	u32 *pllreg = clkid_2_register(parent);
+	unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
+
+	if (!div)
+		div = 1;
+
+	return DIV_ROUND_CLOSEST(prate, div);
+}
+
+/**
+ * set_cpu_clk_info() - Initialize clock framework
+ * Always returns zero.
+ *
+ * This function is called from common code after relocation and sets up the
+ * clock framework. The framework must not be used before this function had been
+ * called.
+ */
+int set_cpu_clk_info(void)
+{
+	zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
+			      "armpll", CONFIG_ZYNQ_PS_CLK_FREQ);
+	zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
+			      "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ);
+	zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
+			      "iopll", CONFIG_ZYNQ_PS_CLK_FREQ);
+
+	init_ddr_clocks();
+	init_cpu_clocks();
+	init_periph_clocks();
+	init_aper_clocks();
+
+	gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+	gd->bd->bi_dsp_freq = 0;
+
+	return 0;
+}
+
+/**
+ * zynq_clk_get_rate() - Get clock rate
+ * @clk:	Clock identifier
+ * Returns the current clock rate of @clk on success or zero for an invalid
+ * clock id.
+ */
+unsigned long zynq_clk_get_rate(enum zynq_clk clk)
+{
+	if (clk < 0 || clk >= clk_max)
+		return 0;
+
+	return clks[clk].frequency;
+}
+
+/**
+ * zynq_clk_set_rate() - Set clock rate
+ * @clk:	Clock identifier
+ * @rate:	Requested clock rate
+ * Passes on the return value from the clock's set_rate() function or negative
+ * errno.
+ */
+int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
+{
+	if (clk < 0 || clk >= clk_max)
+		return -ENODEV;
+
+	if (clks[clk].ops.set_rate)
+		return clks[clk].ops.set_rate(&clks[clk], rate);
+
+	return -ENXIO;
+}
+
+/**
+ * zynq_clk_get_name() - Get clock name
+ * @clk:	Clock identifier
+ * Returns the name of @clk.
+ */
+const char *zynq_clk_get_name(enum zynq_clk clk)
+{
+	return clks[clk].name;
+}
+
+/**
+ * soc_clk_dump() - Print clock frequencies
+ * Returns zero on success
+ *
+ * Implementation for the clk dump command.
+ */
+int soc_clk_dump(void)
+{
+	int i;
+
+	printf("clk\t\tfrequency\n");
+	for (i = 0; i < clk_max; i++) {
+		const char *name = zynq_clk_get_name(i);
+		if (name)
+			printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
+	}
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/cpu.c
new file mode 100644
index 000000000..7626b5c1a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/cpu.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+
+void lowlevel_init(void)
+{
+}
+
+int arch_cpu_init(void)
+{
+	zynq_slcr_unlock();
+#ifndef CONFIG_SPL_BUILD
+	/* Device config APB, unlock the PCAP */
+	writel(0x757BDF0D, &devcfg_base->unlock);
+	writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
+
+#if (CONFIG_SYS_SDRAM_BASE == 0)
+	/* remap DDR to zero, FILTERSTART */
+	writel(0, &scu_base->filter_start);
+
+	/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
+	writel(0x1F, &slcr_base->ocm_cfg);
+	/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
+	writel(0x0, &slcr_base->fpga_rst_ctrl);
+	/* Set urgent bits with register */
+	writel(0x0, &slcr_base->ddr_urgent_sel);
+	/* Urgent write, ports S2/S3 */
+	writel(0xC, &slcr_base->ddr_urgent);
+#endif
+#endif
+	zynq_clk_early_init();
+	zynq_slcr_lock();
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	zynq_slcr_cpu_reset();
+	while (1)
+		;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/ddrc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/ddrc.c
new file mode 100644
index 000000000..ba6a6aee5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/ddrc.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Control regsiter bitfield definitions */
+#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK		0xC
+#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT	2
+#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT	1
+
+/* ECC scrub regsiter definitions */
+#define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK	0x7
+#define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED	0x4
+
+void zynq_ddrc_init(void)
+{
+	u32 width, ecctype;
+
+	width = readl(&ddrc_base->ddrc_ctrl);
+	width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >>
+					ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT;
+	ecctype = (readl(&ddrc_base->ecc_scrub) &
+		ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK);
+
+	/* ECC is enabled when memory is in 16bit mode and it is enabled */
+	if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
+	    (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
+		puts("Memory: ECC enabled\n");
+		/*
+		 * Clear the first 1MB because it is not initialized from
+		 * first stage bootloader. To get ECC to work all memory has
+		 * been initialized by writing any value.
+		 */
+		memset(0, 0, 1 * 1024 * 1024);
+	} else {
+		puts("Memory: ECC disabled\n");
+	}
+
+	if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
+		gd->ram_size /= 2;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/slcr.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/slcr.c
new file mode 100644
index 000000000..d7c188233
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/slcr.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+
+#define SLCR_LOCK_MAGIC		0x767B
+#define SLCR_UNLOCK_MAGIC	0xDF0D
+
+#define SLCR_IDCODE_MASK	0x1F000
+#define SLCR_IDCODE_SHIFT	12
+
+static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
+
+void zynq_slcr_lock(void)
+{
+	if (!slcr_lock)
+		writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
+}
+
+void zynq_slcr_unlock(void)
+{
+	if (slcr_lock)
+		writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
+}
+
+/* Reset the entire system */
+void zynq_slcr_cpu_reset(void)
+{
+	/*
+	 * Unlock the SLCR then reset the system.
+	 * Note that this seems to require raw i/o
+	 * functions or there's a lockup?
+	 */
+	zynq_slcr_unlock();
+
+	/*
+	 * Clear 0x0F000000 bits of reboot status register to workaround
+	 * the FSBL not loading the bitstream after soft-reboot
+	 * This is a temporary solution until we know more.
+	 */
+	clrbits_le32(&slcr_base->reboot_status, 0xF000000);
+
+	writel(1, &slcr_base->pss_rst_ctrl);
+}
+
+/* Setup clk for network */
+void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
+{
+	int ret;
+
+	zynq_slcr_unlock();
+
+	if (gem_id > 1) {
+		printf("Non existing GEM id %d\n", gem_id);
+		goto out;
+	}
+
+	ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
+	if (ret)
+		goto out;
+
+	if (gem_id) {
+		/* Configure GEM_RCLK_CTRL */
+		writel(1, &slcr_base->gem1_rclk_ctrl);
+	} else {
+		/* Configure GEM_RCLK_CTRL */
+		writel(1, &slcr_base->gem0_rclk_ctrl);
+	}
+	udelay(100000);
+out:
+	zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_disable(void)
+{
+	zynq_slcr_unlock();
+
+	/* Disable AXI interface */
+	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
+
+	/* Set Level Shifters DT618760 */
+	writel(0xA, &slcr_base->lvl_shftr_en);
+
+	zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_enable(void)
+{
+	zynq_slcr_unlock();
+
+	/* Set Level Shifters DT618760 */
+	writel(0xF, &slcr_base->lvl_shftr_en);
+
+	/* Disable AXI interface */
+	writel(0x0, &slcr_base->fpga_rst_ctrl);
+
+	zynq_slcr_lock();
+}
+
+u32 zynq_slcr_get_boot_mode(void)
+{
+	/* Get the bootmode register value */
+	return readl(&slcr_base->boot_mode);
+}
+
+u32 zynq_slcr_get_idcode(void)
+{
+	return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
+							SLCR_IDCODE_SHIFT;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/spl.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/spl.c
new file mode 100644
index 000000000..fcad762c0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/spl.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+	ps7_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Set global data pointer. */
+	gd = &gdata;
+
+	preloader_console_init();
+	arch_cpu_init();
+	board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+	u32 mode;
+
+	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+#ifdef CONFIG_SPL_SPI_SUPPORT
+	case ZYNQ_BM_QSPI:
+		puts("qspi boot\n");
+		mode = BOOT_DEVICE_SPI;
+		break;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	case ZYNQ_BM_SD:
+		puts("mmc boot\n");
+		mode = BOOT_DEVICE_MMC1;
+		break;
+#endif
+	default:
+		puts("Unsupported boot mode selected\n");
+		hang();
+	}
+
+	return mode;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(void)
+{
+	return MMCSD_MODE_FAT;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* boot linux */
+	return 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/timer.c
new file mode 100644
index 000000000..303dbcfce
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/timer.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct scu_timer {
+	u32 load; /* Timer Load Register */
+	u32 counter; /* Timer Counter Register */
+	u32 control; /* Timer Control Register */
+};
+
+static struct scu_timer *timer_base =
+			      (struct scu_timer *)ZYNQ_SCUTIMER_BASEADDR;
+
+#define SCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00 /* Prescaler */
+#define SCUTIMER_CONTROL_PRESCALER_SHIFT	8
+#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK	0x00000002 /* Auto-reload */
+#define SCUTIMER_CONTROL_ENABLE_MASK		0x00000001 /* Timer enable */
+
+#define TIMER_LOAD_VAL 0xFFFFFFFF
+#define TIMER_PRESCALE 255
+
+int timer_init(void)
+{
+	const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK |
+			(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
+			SCUTIMER_CONTROL_ENABLE_MASK;
+
+	gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
+
+	/* Load the timer counter register */
+	writel(0xFFFFFFFF, &timer_base->load);
+
+	/*
+	 * Start the A9Timer device
+	 * Enable Auto reload mode, Clear prescaler control bits
+	 * Set prescaler value, Enable the decrementer
+	 */
+	clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK,
+								emask);
+
+	/* Reset time */
+	gd->arch.lastinc = readl(&timer_base->counter) /
+				(gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
+	gd->arch.tbl = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+ulong get_timer_masked(void)
+{
+	ulong now;
+
+	now = readl(&timer_base->counter) /
+			(gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
+
+	if (gd->arch.lastinc >= now) {
+		/* Normal mode */
+		gd->arch.tbl += gd->arch.lastinc - now;
+	} else {
+		/* We have an overflow ... */
+		gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now + 1;
+	}
+	gd->arch.lastinc = now;
+
+	return gd->arch.tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+	u32 countticks;
+	u32 timeend;
+	u32 timediff;
+	u32 timenow;
+
+	if (usec == 0)
+		return;
+
+	countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec),
+			   1000000);
+
+	/* decrementing timer */
+	timeend = readl(&timer_base->counter) - countticks;
+
+#if TIMER_LOAD_VAL != 0xFFFFFFFF
+	/* do not manage multiple overflow */
+	if (countticks >= TIMER_LOAD_VAL)
+		countticks = TIMER_LOAD_VAL - 1;
+#endif
+
+	do {
+		timenow = readl(&timer_base->counter);
+
+		if (timenow >= timeend) {
+			/* normal case */
+			timediff = timenow - timeend;
+		} else {
+			if ((TIMER_LOAD_VAL - timeend + timenow) <=
+								countticks) {
+				/* overflow */
+				timediff = TIMER_LOAD_VAL - timeend + timenow;
+			} else {
+				/* missed the exact match */
+				break;
+			}
+		}
+	} while (timediff > 0);
+}
+
+/* Timer without interrupts */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/u-boot-spl.lds
new file mode 100644
index 000000000..0c4501e5c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/u-boot-spl.lds
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2014 Xilinx, Inc. Michal Simek
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text :
+	{
+		__image_copy_start = .;
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	} > .sram
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} > .sram
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	} > .sram
+
+	. = ALIGN(4);
+
+	. = .;
+
+	__image_copy_end = .;
+
+	_end = .;
+
+	/* Move BSS section to RAM because of FAT */
+	.bss (NOLOAD) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		__bss_end = .;
+	} > .sdram
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/u-boot.lds b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/u-boot.lds
new file mode 100644
index 000000000..f2a596598
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	/*
+	 * Zynq needs to discard more sections because the user
+	 * is expected to pass this image on to tools for boot.bin
+	 * generation that require them to be dropped.
+	 */
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynbss*) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+	/DISCARD/ : { *(.ARM.exidx*) }
+	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/Makefile b/qemu/roms/u-boot/arch/arm/cpu/armv8/Makefile
new file mode 100644
index 000000000..7d93f5942
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/Makefile
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	:= start.o
+
+obj-y	+= cpu.o
+obj-y	+= generic_timer.o
+obj-y	+= cache_v8.o
+obj-y	+= exceptions.o
+obj-y	+= cache.o
+obj-y	+= tlb.o
+obj-y	+= transition.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/cache.S b/qemu/roms/u-boot/arch/arm/cpu/armv8/cache.S
new file mode 100644
index 000000000..4b3ee6ed6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/cache.S
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * This file is based on sample code from ARMv8 ARM.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+/*
+ * void __asm_flush_dcache_level(level)
+ *
+ * clean and invalidate one level cache.
+ *
+ * x0: cache level
+ * x1: 0 flush & invalidate, 1 invalidate only
+ * x2~x9: clobbered
+ */
+ENTRY(__asm_flush_dcache_level)
+	lsl	x12, x0, #1
+	msr	csselr_el1, x12		/* select cache level */
+	isb				/* sync change of cssidr_el1 */
+	mrs	x6, ccsidr_el1		/* read the new cssidr_el1 */
+	and	x2, x6, #7		/* x2 <- log2(cache line size)-4 */
+	add	x2, x2, #4		/* x2 <- log2(cache line size) */
+	mov	x3, #0x3ff
+	and	x3, x3, x6, lsr #3	/* x3 <- max number of #ways */
+	clz	w5, w3			/* bit position of #ways */
+	mov	x4, #0x7fff
+	and	x4, x4, x6, lsr #13	/* x4 <- max number of #sets */
+	/* x12 <- cache level << 1 */
+	/* x2 <- line length offset */
+	/* x3 <- number of cache ways - 1 */
+	/* x4 <- number of cache sets - 1 */
+	/* x5 <- bit position of #ways */
+
+loop_set:
+	mov	x6, x3			/* x6 <- working copy of #ways */
+loop_way:
+	lsl	x7, x6, x5
+	orr	x9, x12, x7		/* map way and level to cisw value */
+	lsl	x7, x4, x2
+	orr	x9, x9, x7		/* map set number to cisw value */
+	tbz	w1, #0, 1f
+	dc	isw, x9
+	b	2f
+1:	dc	cisw, x9		/* clean & invalidate by set/way */
+2:	subs	x6, x6, #1		/* decrement the way */
+	b.ge	loop_way
+	subs	x4, x4, #1		/* decrement the set */
+	b.ge	loop_set
+
+	ret
+ENDPROC(__asm_flush_dcache_level)
+
+/*
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 flush & invalidate, 1 invalidate only
+ *
+ * clean and invalidate all data cache by SET/WAY.
+ */
+ENTRY(__asm_dcache_all)
+	mov	x1, x0
+	dsb	sy
+	mrs	x10, clidr_el1		/* read clidr_el1 */
+	lsr	x11, x10, #24
+	and	x11, x11, #0x7		/* x11 <- loc */
+	cbz	x11, finished		/* if loc is 0, exit */
+	mov	x15, lr
+	mov	x0, #0			/* start flush at cache level 0 */
+	/* x0  <- cache level */
+	/* x10 <- clidr_el1 */
+	/* x11 <- loc */
+	/* x15 <- return address */
+
+loop_level:
+	lsl	x12, x0, #1
+	add	x12, x12, x0		/* x0 <- tripled cache level */
+	lsr	x12, x10, x12
+	and	x12, x12, #7		/* x12 <- cache type */
+	cmp	x12, #2
+	b.lt	skip			/* skip if no cache or icache */
+	bl	__asm_flush_dcache_level	/* x1 = 0 flush, 1 invalidate */
+skip:
+	add	x0, x0, #1		/* increment cache level */
+	cmp	x11, x0
+	b.gt	loop_level
+
+	mov	x0, #0
+	msr	csselr_el1, x0		/* resotre csselr_el1 */
+	dsb	sy
+	isb
+	mov	lr, x15
+
+finished:
+	ret
+ENDPROC(__asm_dcache_all)
+
+ENTRY(__asm_flush_dcache_all)
+	mov	x16, lr
+	mov	x0, #0
+	bl	__asm_dcache_all
+	mov	lr, x16
+	ret
+ENDPROC(__asm_flush_dcache_all)
+
+ENTRY(__asm_invalidate_dcache_all)
+	mov	x16, lr
+	mov	x0, #0xffff
+	bl	__asm_dcache_all
+	mov	lr, x16
+	ret
+ENDPROC(__asm_invalidate_dcache_all)
+
+/*
+ * void __asm_flush_dcache_range(start, end)
+ *
+ * clean & invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+ENTRY(__asm_flush_dcache_range)
+	mrs	x3, ctr_el0
+	lsr	x3, x3, #16
+	and	x3, x3, #0xf
+	mov	x2, #4
+	lsl	x2, x2, x3		/* cache line size */
+
+	/* x2 <- minimal cache line size in cache system */
+	sub	x3, x2, #1
+	bic	x0, x0, x3
+1:	dc	civac, x0	/* clean & invalidate data or unified cache */
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	ret
+ENDPROC(__asm_flush_dcache_range)
+
+/*
+ * void __asm_invalidate_icache_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+ENTRY(__asm_invalidate_icache_all)
+	ic	ialluis
+	isb	sy
+	ret
+ENDPROC(__asm_invalidate_icache_all)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/cache_v8.c b/qemu/roms/u-boot/arch/arm/cpu/armv8/cache_v8.c
new file mode 100644
index 000000000..a96ecda7e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/cache_v8.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+static void set_pgtable_section(u64 section, u64 memory_type)
+{
+	u64 *page_table = (u64 *)gd->arch.tlb_addr;
+	u64 value;
+
+	value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;
+	value |= PMD_ATTRINDX(memory_type);
+	page_table[section] = value;
+}
+
+/* to activate the MMU we need to set up virtual memory */
+static void mmu_setup(void)
+{
+	int i, j, el;
+	bd_t *bd = gd->bd;
+
+	/* Setup an identity-mapping for all spaces */
+	for (i = 0; i < (PGTABLE_SIZE >> 3); i++)
+		set_pgtable_section(i, MT_DEVICE_NGNRNE);
+
+	/* Setup an identity-mapping for all RAM space */
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		ulong start = bd->bi_dram[i].start;
+		ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
+		for (j = start >> SECTION_SHIFT;
+		     j < end >> SECTION_SHIFT; j++) {
+			set_pgtable_section(j, MT_NORMAL);
+		}
+	}
+
+	/* load TTBR0 */
+	el = current_el();
+	if (el == 1) {
+		asm volatile("msr ttbr0_el1, %0"
+			     : : "r" (gd->arch.tlb_addr) : "memory");
+		asm volatile("msr tcr_el1, %0"
+			     : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
+			     : "memory");
+		asm volatile("msr mair_el1, %0"
+			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+	} else if (el == 2) {
+		asm volatile("msr ttbr0_el2, %0"
+			     : : "r" (gd->arch.tlb_addr) : "memory");
+		asm volatile("msr tcr_el2, %0"
+			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
+			     : "memory");
+		asm volatile("msr mair_el2, %0"
+			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+	} else {
+		asm volatile("msr ttbr0_el3, %0"
+			     : : "r" (gd->arch.tlb_addr) : "memory");
+		asm volatile("msr tcr_el3, %0"
+			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
+			     : "memory");
+		asm volatile("msr mair_el3, %0"
+			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+	}
+
+	/* enable the mmu */
+	set_sctlr(get_sctlr() | CR_M);
+}
+
+/*
+ * Performs a invalidation of the entire data cache at all levels
+ */
+void invalidate_dcache_all(void)
+{
+	__asm_invalidate_dcache_all();
+}
+
+/*
+ * Performs a clean & invalidation of the entire data cache at all levels
+ */
+void flush_dcache_all(void)
+{
+	__asm_flush_dcache_all();
+}
+
+/*
+ * Invalidates range in all levels of D-cache/unified cache
+ */
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	__asm_flush_dcache_range(start, stop);
+}
+
+/*
+ * Flush range(clean & invalidate) from all levels of D-cache/unified cache
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	__asm_flush_dcache_range(start, stop);
+}
+
+void dcache_enable(void)
+{
+	/* The data cache is not active unless the mmu is enabled */
+	if (!(get_sctlr() & CR_M)) {
+		invalidate_dcache_all();
+		__asm_invalidate_tlb_all();
+		mmu_setup();
+	}
+
+	set_sctlr(get_sctlr() | CR_C);
+}
+
+void dcache_disable(void)
+{
+	uint32_t sctlr;
+
+	sctlr = get_sctlr();
+
+	/* if cache isn't enabled no need to disable */
+	if (!(sctlr & CR_C))
+		return;
+
+	set_sctlr(sctlr & ~(CR_C|CR_M));
+
+	flush_dcache_all();
+	__asm_invalidate_tlb_all();
+}
+
+int dcache_status(void)
+{
+	return (get_sctlr() & CR_C) != 0;
+}
+
+#else	/* CONFIG_SYS_DCACHE_OFF */
+
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+	return 0;
+}
+
+#endif	/* CONFIG_SYS_DCACHE_OFF */
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+
+void icache_enable(void)
+{
+	__asm_invalidate_icache_all();
+	set_sctlr(get_sctlr() | CR_I);
+}
+
+void icache_disable(void)
+{
+	set_sctlr(get_sctlr() & ~CR_I);
+}
+
+int icache_status(void)
+{
+	return (get_sctlr() & CR_I) != 0;
+}
+
+void invalidate_icache_all(void)
+{
+	__asm_invalidate_icache_all();
+}
+
+#else	/* CONFIG_SYS_ICACHE_OFF */
+
+void icache_enable(void)
+{
+}
+
+void icache_disable(void)
+{
+}
+
+int icache_status(void)
+{
+	return 0;
+}
+
+void invalidate_icache_all(void)
+{
+}
+
+#endif	/* CONFIG_SYS_ICACHE_OFF */
+
+/*
+ * Enable dCache & iCache, whether cache is actually enabled
+ * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
+ */
+void enable_caches(void)
+{
+	icache_enable();
+	dcache_enable();
+}
+
+/*
+ * Flush range from all levels of d-cache/unified-cache
+ */
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/config.mk b/qemu/roms/u-boot/arch/arm/cpu/armv8/config.mk
new file mode 100644
index 000000000..f5b95591a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/config.mk
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+PLATFORM_RELFLAGS += -fno-common -ffixed-x18
+
+PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a)
+PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8)
+PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/armv8/cpu.c
new file mode 100644
index 000000000..e06c3cc04
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/cpu.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+#include <linux/compiler.h>
+
+int cleanup_before_linux(void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * disable interrupt and turn off caches etc ...
+	 */
+	disable_interrupts();
+
+	/*
+	 * Turn off I-cache and invalidate it
+	 */
+	icache_disable();
+	invalidate_icache_all();
+
+	/*
+	 * turn off D-cache
+	 * dcache_disable() in turn flushes the d-cache and disables MMU
+	 */
+	dcache_disable();
+	invalidate_dcache_all();
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/exceptions.S b/qemu/roms/u-boot/arch/arm/cpu/armv8/exceptions.S
new file mode 100644
index 000000000..b91a1b662
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/exceptions.S
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/ptrace.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+/*
+ * Enter Exception.
+ * This will save the processor state that is ELR/X0~X30
+ * to the stack frame.
+ */
+.macro	exception_entry
+	stp	x29, x30, [sp, #-16]!
+	stp	x27, x28, [sp, #-16]!
+	stp	x25, x26, [sp, #-16]!
+	stp	x23, x24, [sp, #-16]!
+	stp	x21, x22, [sp, #-16]!
+	stp	x19, x20, [sp, #-16]!
+	stp	x17, x18, [sp, #-16]!
+	stp	x15, x16, [sp, #-16]!
+	stp	x13, x14, [sp, #-16]!
+	stp	x11, x12, [sp, #-16]!
+	stp	x9, x10, [sp, #-16]!
+	stp	x7, x8, [sp, #-16]!
+	stp	x5, x6, [sp, #-16]!
+	stp	x3, x4, [sp, #-16]!
+	stp	x1, x2, [sp, #-16]!
+
+	/* Could be running at EL3/EL2/EL1 */
+	switch_el x11, 3f, 2f, 1f
+3:	mrs	x1, esr_el3
+	mrs	x2, elr_el3
+	b	0f
+2:	mrs	x1, esr_el2
+	mrs	x2, elr_el2
+	b	0f
+1:	mrs	x1, esr_el1
+	mrs	x2, elr_el1
+0:
+	stp	x2, x0, [sp, #-16]!
+	mov	x0, sp
+.endm
+
+/*
+ * Exception vectors.
+ */
+	.align	11
+	.globl	vectors
+vectors:
+	.align	7
+	b	_do_bad_sync	/* Current EL Synchronous Thread */
+
+	.align	7
+	b	_do_bad_irq	/* Current EL IRQ Thread */
+
+	.align	7
+	b	_do_bad_fiq	/* Current EL FIQ Thread */
+
+	.align	7
+	b	_do_bad_error	/* Current EL Error Thread */
+
+	.align	7
+	b	_do_sync	/* Current EL Synchronous Handler */
+
+	.align	7
+	b	_do_irq		/* Current EL IRQ Handler */
+
+	.align	7
+	b	_do_fiq		/* Current EL FIQ Handler */
+
+	.align	7
+	b	_do_error	/* Current EL Error Handler */
+
+
+_do_bad_sync:
+	exception_entry
+	bl	do_bad_sync
+
+_do_bad_irq:
+	exception_entry
+	bl	do_bad_irq
+
+_do_bad_fiq:
+	exception_entry
+	bl	do_bad_fiq
+
+_do_bad_error:
+	exception_entry
+	bl	do_bad_error
+
+_do_sync:
+	exception_entry
+	bl	do_sync
+
+_do_irq:
+	exception_entry
+	bl	do_irq
+
+_do_fiq:
+	exception_entry
+	bl	do_fiq
+
+_do_error:
+	exception_entry
+	bl	do_error
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/generic_timer.c b/qemu/roms/u-boot/arch/arm/cpu/armv8/generic_timer.c
new file mode 100644
index 000000000..223b95e21
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/generic_timer.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+/*
+ * Generic timer implementation of get_tbclk()
+ */
+unsigned long get_tbclk(void)
+{
+	unsigned long cntfrq;
+	asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
+	return cntfrq;
+}
+
+/*
+ * Generic timer implementation of timer_read_counter()
+ */
+unsigned long timer_read_counter(void)
+{
+	unsigned long cntpct;
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+	return cntpct;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/start.S b/qemu/roms/u-boot/arch/arm/cpu/armv8/start.S
new file mode 100644
index 000000000..33d3f3688
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/start.S
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/armv8/mmu.h>
+
+/*************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ *************************************************************************/
+
+.globl	_start
+_start:
+	b	reset
+
+	.align 3
+
+.globl	_TEXT_BASE
+_TEXT_BASE:
+	.quad	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the linker script.
+ */
+.globl	_end_ofs
+_end_ofs:
+	.quad	_end - _start
+
+.globl	_bss_start_ofs
+_bss_start_ofs:
+	.quad	__bss_start - _start
+
+.globl	_bss_end_ofs
+_bss_end_ofs:
+	.quad	__bss_end - _start
+
+reset:
+	/*
+	 * Could be EL3/EL2/EL1, Initial State:
+	 * Little Endian, MMU Disabled, i/dCache Disabled
+	 */
+	adr	x0, vectors
+	switch_el x1, 3f, 2f, 1f
+3:	mrs	x0, scr_el3
+	orr	x0, x0, #0xf			/* SCR_EL3.NS|IRQ|FIQ|EA */
+	msr	scr_el3, x0
+	msr	vbar_el3, x0
+	msr	cptr_el3, xzr			/* Enable FP/SIMD */
+	ldr	x0, =COUNTER_FREQUENCY
+	msr	cntfrq_el0, x0			/* Initialize CNTFRQ */
+	b	0f
+2:	msr	vbar_el2, x0
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0			/* Enable FP/SIMD */
+	b	0f
+1:	msr	vbar_el1, x0
+	mov	x0, #3 << 20
+	msr	cpacr_el1, x0			/* Enable FP/SIMD */
+0:
+
+	/*
+	 * Cache/BPB/TLB Invalidate
+	 * i-cache is invalidated before enabled in icache_enable()
+	 * tlb is invalidated before mmu is enabled in dcache_enable()
+	 * d-cache is invalidated before enabled in dcache_enable()
+	 */
+
+	/* Processor specific initialization */
+	bl	lowlevel_init
+
+	branch_if_master x0, x1, master_cpu
+
+	/*
+	 * Slave CPUs
+	 */
+slave_cpu:
+	wfe
+	ldr	x1, =CPU_RELEASE_ADDR
+	ldr	x0, [x1]
+	cbz	x0, slave_cpu
+	br	x0			/* branch to the given address */
+
+	/*
+	 * Master CPU
+	 */
+master_cpu:
+	bl	_main
+
+/*-----------------------------------------------------------------------*/
+
+WEAK(lowlevel_init)
+	mov	x29, lr			/* Save LR */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+	branch_if_slave x0, 1f
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+1:
+#if defined(CONFIG_GICV3)
+	ldr	x0, =GICR_BASE
+	bl	gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+	ldr	x0, =GICD_BASE
+	ldr	x1, =GICC_BASE
+	bl	gic_init_secure_percpu
+#endif
+#endif
+
+	branch_if_master x0, x1, 2f
+
+	/*
+	 * Slave should wait for master clearing spin table.
+	 * This sync prevent salves observing incorrect
+	 * value of spin table and jumping to wrong place.
+	 */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+	ldr	x0, =GICC_BASE
+#endif
+	bl	gic_wait_for_interrupt
+#endif
+
+	/*
+	 * All slaves will enter EL2 and optionally EL1.
+	 */
+	bl	armv8_switch_to_el2
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	bl	armv8_switch_to_el1
+#endif
+
+2:
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(lowlevel_init)
+
+WEAK(smp_kick_all_cpus)
+	/* Kick secondary cpus up by SGI 0 interrupt */
+	mov	x29, lr			/* Save LR */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+	ldr	x0, =GICD_BASE
+	bl	gic_kick_secondary_cpus
+#endif
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(smp_kick_all_cpus)
+
+/*-----------------------------------------------------------------------*/
+
+ENTRY(c_runtime_cpu_setup)
+	/* Relocate vBAR */
+	adr	x0, vectors
+	switch_el x1, 3f, 2f, 1f
+3:	msr	vbar_el3, x0
+	b	0f
+2:	msr	vbar_el2, x0
+	b	0f
+1:	msr	vbar_el1, x0
+0:
+
+	ret
+ENDPROC(c_runtime_cpu_setup)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/tlb.S b/qemu/roms/u-boot/arch/arm/cpu/armv8/tlb.S
new file mode 100644
index 000000000..f840b04df
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/tlb.S
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+/*
+ * void __asm_invalidate_tlb_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+ENTRY(__asm_invalidate_tlb_all)
+	switch_el x9, 3f, 2f, 1f
+3:	tlbi	alle3
+	dsb	sy
+	isb
+	b	0f
+2:	tlbi	alle2
+	dsb	sy
+	isb
+	b	0f
+1:	tlbi	vmalle1
+	dsb	sy
+	isb
+0:
+	ret
+ENDPROC(__asm_invalidate_tlb_all)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/transition.S b/qemu/roms/u-boot/arch/arm/cpu/armv8/transition.S
new file mode 100644
index 000000000..e0a594600
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/transition.S
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+ENTRY(armv8_switch_to_el2)
+	switch_el x0, 1f, 0f, 0f
+0:	ret
+1:
+	mov	x0, #0x5b1	/* Non-secure EL0/EL1 | HVC | 64bit EL2 */
+	msr	scr_el3, x0
+	msr	cptr_el3, xzr	/* Disable coprocessor traps to EL3 */
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0	/* Disable coprocessor traps to EL2 */
+
+	/* Initialize SCTLR_EL2 */
+	msr	sctlr_el2, xzr
+
+	/* Return to the EL2_SP2 mode from EL3 */
+	mov	x0, sp
+	msr	sp_el2, x0	/* Migrate SP */
+	mrs	x0, vbar_el3
+	msr	vbar_el2, x0	/* Migrate VBAR */
+	mov	x0, #0x3c9
+	msr	spsr_el3, x0	/* EL2_SP2 | D | A | I | F */
+	msr	elr_el3, lr
+	eret
+ENDPROC(armv8_switch_to_el2)
+
+ENTRY(armv8_switch_to_el1)
+	switch_el x0, 0f, 1f, 0f
+0:	ret
+1:
+	/* Initialize Generic Timers */
+	mrs	x0, cnthctl_el2
+	orr	x0, x0, #0x3		/* Enable EL1 access to timers */
+	msr	cnthctl_el2, x0
+	msr	cntvoff_el2, x0
+	mrs	x0, cntkctl_el1
+	orr	x0, x0, #0x3		/* Enable EL0 access to timers */
+	msr	cntkctl_el1, x0
+
+	/* Initilize MPID/MPIDR registers */
+	mrs	x0, midr_el1
+	mrs	x1, mpidr_el1
+	msr	vpidr_el2, x0
+	msr	vmpidr_el2, x1
+
+	/* Disable coprocessor traps */
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0		/* Disable coprocessor traps to EL2 */
+	msr	hstr_el2, xzr		/* Disable coprocessor traps to EL2 */
+	mov	x0, #3 << 20
+	msr	cpacr_el1, x0		/* Enable FP/SIMD at EL1 */
+
+	/* Initialize HCR_EL2 */
+	mov	x0, #(1 << 31)		/* 64bit EL1 */
+	orr	x0, x0, #(1 << 29)	/* Disable HVC */
+	msr	hcr_el2, x0
+
+	/* SCTLR_EL1 initialization */
+	mov	x0, #0x0800
+	movk	x0, #0x30d0, lsl #16
+	msr	sctlr_el1, x0
+
+	/* Return to the EL1_SP1 mode from EL2 */
+	mov	x0, sp
+	msr	sp_el1, x0		/* Migrate SP */
+	mrs	x0, vbar_el2
+	msr	vbar_el1, x0		/* Migrate VBAR */
+	mov	x0, #0x3c5
+	msr	spsr_el2, x0		/* EL1_SP1 | D | A | I | F */
+	msr	elr_el2, lr
+	eret
+ENDPROC(armv8_switch_to_el1)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv8/u-boot.lds b/qemu/roms/u-boot/arch/arm/cpu/armv8/u-boot.lds
new file mode 100644
index 000000000..4c1222237
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/armv8/u-boot.lds
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(8);
+	.text :
+	{
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(8);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(8);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(8);
+
+	. = .;
+
+	. = ALIGN(8);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(8);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	. = ALIGN(8);
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rela.dyn : {
+		*(.rela*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	_end = .;
+
+	. = ALIGN(8);
+
+	.bss_start : {
+		KEEP(*(.__bss_start));
+	}
+
+	.bss : {
+		*(.bss*)
+		 . = ALIGN(8);
+	}
+
+	.bss_end : {
+		KEEP(*(.__bss_end));
+	}
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/at91-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/at91-common/Makefile
new file mode 100644
index 000000000..5b978384e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/at91-common/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2013 Atmel Corporation
+#		     Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
+obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/at91-common/mpddrc.c b/qemu/roms/u-boot/arch/arm/cpu/at91-common/mpddrc.c
new file mode 100644
index 000000000..813639640
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/at91-common/mpddrc.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/atmel_mpddrc.h>
+
+static inline void atmel_mpddr_op(int mode, u32 ram_address)
+{
+	struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+
+	writel(mode, &mpddr->mr);
+	writel(0, ram_address);
+}
+
+int ddr2_init(const unsigned int ram_address,
+	      const struct atmel_mpddr *mpddr_value)
+{
+	struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	u32 ba_off, cr;
+
+	/* Compute bank offset according to NC in configuration register */
+	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
+	if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
+		ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
+
+	ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
+
+	/* Program the memory device type into the memory device register */
+	writel(mpddr_value->md, &mpddr->md);
+
+	/* Program the configuration register */
+	writel(mpddr_value->cr, &mpddr->cr);
+
+	/* Program the timing register */
+	writel(mpddr_value->tpr0, &mpddr->tpr0);
+	writel(mpddr_value->tpr1, &mpddr->tpr1);
+	writel(mpddr_value->tpr2, &mpddr->tpr2);
+
+	/* Issue a NOP command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+
+	/* A 200 us is provided to precede any signal toggle */
+	udelay(200);
+
+	/* Issue a NOP command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+
+	/* Issue an all banks precharge command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
+
+	/* Issue an extended mode register set(EMRS2) to choose operation */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x2 << ba_off));
+
+	/* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x3 << ba_off));
+
+	/*
+	 * Issue an extended mode register set(EMRS1) to enable DLL and
+	 * program D.I.C (output driver impedance control)
+	 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x1 << ba_off));
+
+	/* Enable DLL reset */
+	cr = readl(&mpddr->cr);
+	writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
+
+	/* A mode register set(MRS) cycle is issued to reset DLL */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
+
+	/* Issue an all banks precharge command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
+
+	/* Two auto-refresh (CBR) cycles are provided */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
+
+	/* Disable DLL reset */
+	cr = readl(&mpddr->cr);
+	writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
+
+	/* A mode register set (MRS) cycle is issued to disable DLL reset */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
+
+	/* Set OCD calibration in default state */
+	cr = readl(&mpddr->cr);
+	writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
+
+	/*
+	 * An extended mode register set (EMRS1) cycle is issued
+	 * to OCD default value
+	 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x1 << ba_off));
+
+	 /* OCD calibration mode exit */
+	cr = readl(&mpddr->cr);
+	writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
+
+	/*
+	 * An extended mode register set (EMRS1) cycle is issued
+	 * to enable OCD exit
+	 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x1 << ba_off));
+
+	/* A nornal mode command is provided */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
+
+	/* Perform a write access to any DDR2-SDRAM address */
+	writel(0, ram_address);
+
+	/* Write the refresh rate */
+	writel(mpddr_value->rtr, &mpddr->rtr);
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/at91-common/phy.c b/qemu/roms/u-boot/arch/arm/cpu/at91-common/phy.c
new file mode 100644
index 000000000..2cba7169e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/at91-common/phy.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * Copyright (C) 2013 DENX Software Engineering, hs@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <watchdog.h>
+
+void at91_phy_reset(void)
+{
+	unsigned long erstl;
+	unsigned long start = get_timer(0);
+	unsigned long const timeout = 1000; /* 1000ms */
+	at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+
+	/*
+	 * Need to reset PHY -> 500ms reset
+	 * Reset PHY by pulling the NRST line for 500ms to low. To do so
+	 * disable user reset for low level on NRST pin and poll the NRST
+	 * level in reset status register.
+	 */
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+		AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+
+	/* Wait for end of hardware reset */
+	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
+		/* avoid shutdown by watchdog */
+		WATCHDOG_RESET();
+		mdelay(10);
+
+		/* timeout for not getting stuck in an endless loop */
+		if (get_timer(start) >= timeout) {
+			puts("*** ERROR: Timeout waiting for PHY reset!\n");
+			break;
+		}
+	};
+
+	/* Restore NRST value */
+	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/at91-common/spl.c b/qemu/roms/u-boot/arch/arm/cpu/at91-common/spl.c
new file mode 100644
index 000000000..7f4debb91
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/at91-common/spl.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_wdt.h>
+#include <asm/arch/clk.h>
+#include <spl.h>
+
+static void at91_disable_wdt(void)
+{
+	struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
+
+	writel(AT91_WDT_MR_WDDIS, &wdt->mr);
+}
+
+void at91_plla_init(u32 pllar)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(pllar, &pmc->pllar);
+	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
+		;
+}
+
+void at91_mck_init(u32 mckr)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = readl(&pmc->mckr);
+	tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
+		 AT91_PMC_MCKR_MDIV_MASK |
+		 AT91_PMC_MCKR_PLLADIV_2);
+	tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
+		       AT91_PMC_MCKR_MDIV_MASK |
+		       AT91_PMC_MCKR_PLLADIV_2);
+	writel(tmp, &pmc->mckr);
+
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
+}
+
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	return BOOT_DEVICE_MMC1;
+#elif CONFIG_SYS_USE_NANDFLASH
+	return BOOT_DEVICE_NAND;
+#elif CONFIG_SYS_USE_SERIALFLASH
+	return BOOT_DEVICE_SPI;
+#endif
+	return BOOT_DEVICE_NONE;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+#ifdef CONFIG_SYS_USE_MMC
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_FAT;
+		break;
+#endif
+	case BOOT_DEVICE_NONE:
+	default:
+		hang();
+	}
+}
+
+void s_init(void)
+{
+	/* disable watchdog */
+	at91_disable_wdt();
+
+	/* PMC configuration */
+	at91_pmc_init();
+
+	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+
+	timer_init();
+
+	board_early_init_f();
+
+	preloader_console_init();
+
+	mem_init();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/at91-common/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/at91-common/u-boot-spl.lds
new file mode 100644
index 000000000..57ac1eb24
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/at91-common/u-boot-spl.lds
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * (C) 2013 Atmel Corporation
+ *	    Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text*)
+		*(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/pxa/Makefile b/qemu/roms/u-boot/arch/arm/cpu/pxa/Makefile
new file mode 100644
index 000000000..8cd475e3a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/pxa/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+
+obj-$(CONFIG_CPU_PXA25X)	+= pxa2xx.o
+obj-$(CONFIG_CPU_PXA27X)	+= pxa2xx.o
+
+obj-y	+= cpuinfo.o
+obj-y	+= timer.o
+obj-y	+= usb.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/pxa/config.mk b/qemu/roms/u-boot/arch/arm/cpu/pxa/config.mk
new file mode 100644
index 000000000..525f5d33b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/pxa/config.mk
@@ -0,0 +1,22 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mcpu=xscale
+
+#
+# !WARNING!
+# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from
+# really small OneNAND memories where the mmap'd window is only 1KiB big. The
+# .text.0 contains only the bare minimum needed to load the real SPL into SRAM.
+# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd,
+# they are not discarded.
+#
+
+#ifdef CONFIG_SPL_BUILD
+OBJCOPYFLAGS += -j .text.0 -j .text.1
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/pxa/cpuinfo.c b/qemu/roms/u-boot/arch/arm/cpu/pxa/cpuinfo.c
new file mode 100644
index 000000000..9d1607995
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/pxa/cpuinfo.c
@@ -0,0 +1,126 @@
+/*
+ * PXA CPU information display
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <linux/compiler.h>
+
+#define	CPU_MASK_PXA_PRODID	0x000003f0
+#define	CPU_MASK_PXA_REVID	0x0000000f
+
+#define	CPU_MASK_PRODREV	(CPU_MASK_PXA_PRODID | CPU_MASK_PXA_REVID)
+
+#define	CPU_VALUE_PXA25X	0x100
+#define	CPU_VALUE_PXA27X	0x110
+
+static uint32_t pxa_get_cpuid(void)
+{
+	uint32_t cpuid;
+	asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid));
+	return cpuid;
+}
+
+int cpu_is_pxa25x(void)
+{
+	uint32_t id = pxa_get_cpuid();
+	id &= CPU_MASK_PXA_PRODID;
+	return id == CPU_VALUE_PXA25X;
+}
+
+int cpu_is_pxa27x(void)
+{
+	uint32_t id = pxa_get_cpuid();
+	id &= CPU_MASK_PXA_PRODID;
+	return id == CPU_VALUE_PXA27X;
+}
+
+uint32_t pxa_get_cpu_revision(void)
+{
+	return pxa_get_cpuid() & CPU_MASK_PRODREV;
+}
+
+#ifdef	CONFIG_DISPLAY_CPUINFO
+static const char *pxa25x_get_revision(void)
+{
+	static __maybe_unused const char * const revs_25x[] = { "A0" };
+	static __maybe_unused const char * const revs_26x[] = {
+								"A0", "B0", "B1"
+								};
+	static const char *unknown = "Unknown";
+	uint32_t id;
+
+	if (!cpu_is_pxa25x())
+		return unknown;
+
+	id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
+
+/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */
+#ifdef	CONFIG_CPU_PXA26X
+	switch (id) {
+	case 3: return revs_26x[0];
+	case 5: return revs_26x[1];
+	case 6: return revs_26x[2];
+	}
+#else
+	if (id == 6)
+		return revs_25x[0];
+#endif
+	return unknown;
+}
+
+static const char *pxa27x_get_revision(void)
+{
+	static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" };
+	static const char *unknown = "Unknown";
+	uint32_t id;
+
+	if (!cpu_is_pxa27x())
+		return unknown;
+
+	id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
+
+	if ((id == 5) || (id == 6) || (id > 7))
+		return unknown;
+
+	/* Cap the special PXA270 C5 case. */
+	if (id == 7)
+		id = 5;
+
+	return rev[id];
+}
+
+static int print_cpuinfo_pxa2xx(void)
+{
+	if (cpu_is_pxa25x()) {
+		puts("Marvell PXA25x rev. ");
+		puts(pxa25x_get_revision());
+	} else if (cpu_is_pxa27x()) {
+		puts("Marvell PXA27x rev. ");
+		puts(pxa27x_get_revision());
+	} else
+		return -EINVAL;
+
+	puts("\n");
+
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	int ret;
+
+	puts("CPU: ");
+
+	ret = print_cpuinfo_pxa2xx();
+	if (!ret)
+		return ret;
+
+	return ret;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/pxa/pxa2xx.c b/qemu/roms/u-boot/arch/arm/cpu/pxa/pxa2xx.c
new file mode 100644
index 000000000..7e861e26d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/pxa/pxa2xx.c
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/system.h>
+#include <command.h>
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+/* Flush I/D-cache */
+static void cache_flush(void)
+{
+	unsigned long i = 0;
+
+	asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
+}
+
+int cleanup_before_linux(void)
+{
+	/*
+	 * This function is called just before we call Linux. It prepares
+	 * the processor for Linux by just disabling everything that can
+	 * disturb booting Linux.
+	 */
+
+	disable_interrupts();
+	icache_disable();
+	dcache_disable();
+	cache_flush();
+
+	return 0;
+}
+
+void pxa_wait_ticks(int ticks)
+{
+	writel(0, OSCR);
+	while (readl(OSCR) < ticks)
+		asm volatile("" : : : "memory");
+}
+
+inline void writelrb(uint32_t val, uint32_t addr)
+{
+	writel(val, addr);
+	asm volatile("" : : : "memory");
+	readl(addr);
+	asm volatile("" : : : "memory");
+}
+
+void pxa2xx_dram_init(void)
+{
+	uint32_t tmp;
+	int i;
+	/*
+	 * 1) Initialize Asynchronous static memory controller
+	 */
+
+	writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
+	writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
+	writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
+	/*
+	 * 2) Initialize Card Interface
+	 */
+
+	/* MECR: Memory Expansion Card Register */
+	writelrb(CONFIG_SYS_MECR_VAL, MECR);
+	/* MCMEM0: Card Interface slot 0 timing */
+	writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
+	/* MCMEM1: Card Interface slot 1 timing */
+	writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+	writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+	writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
+	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
+	writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
+	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
+	writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
+
+	/*
+	 * 3) Configure Fly-By DMA register
+	 */
+
+	writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
+
+	/*
+	 * 4) Initialize Timing for Sync Memory (SDCLK0)
+	 */
+
+	/*
+	 * Before accessing MDREFR we need a valid DRI field, so we set
+	 * this to power on defaults + DRI field.
+	 */
+
+	/* Read current MDREFR config and zero out DRI */
+	tmp = readl(MDREFR) & ~0xfff;
+	/* Add user-specified DRI */
+	tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
+	/* Configure important bits */
+	tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
+	tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
+
+	/* Write MDREFR back */
+	writelrb(tmp, MDREFR);
+
+	/*
+	 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
+	 */
+
+	/* Initialize SXCNFG register. Assert the enable bits.
+	 *
+	 * Write SXMRS to cause an MRS command to all enabled banks of
+	 * synchronous static memory. Note that SXLCR need not be written
+	 * at this time.
+	 */
+	writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
+
+	/*
+	 * 6) Initialize SDRAM
+	 */
+
+	writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
+	writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
+
+	/*
+	 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
+	 *    but not enable each SDRAM partition pair.
+	 */
+
+	writelrb(CONFIG_SYS_MDCNFG_VAL &
+		~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
+	/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
+	pxa_wait_ticks(0x300);
+
+	/*
+	 * 8) Trigger a number (usually 8) refresh cycles by attempting
+	 *    non-burst read or write accesses to disabled SDRAM, as commonly
+	 *    specified in the power up sequence documented in SDRAM data
+	 *    sheets. The address(es) used for this purpose must not be
+	 *    cacheable.
+	 */
+	for (i = 9; i >= 0; i--) {
+		writel(i, 0xa0000000);
+		asm volatile("" : : : "memory");
+	}
+	/*
+	 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
+	 */
+
+	tmp = CONFIG_SYS_MDCNFG_VAL &
+		(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
+	tmp |= readl(MDCNFG);
+	writelrb(tmp, MDCNFG);
+
+	/*
+	 * 10) Write MDMRS.
+	 */
+
+	writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
+
+	/*
+	 * 11) Enable APD
+	 */
+
+	if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
+		tmp = readl(MDREFR);
+		tmp |= MDREFR_APD;
+		writelrb(tmp, MDREFR);
+	}
+}
+
+void pxa_gpio_setup(void)
+{
+	writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
+	writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
+	writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
+#if defined(CONFIG_CPU_PXA27X)
+	writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
+#endif
+
+	writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
+	writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
+	writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
+#if defined(CONFIG_CPU_PXA27X)
+	writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
+#endif
+
+	writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
+	writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
+	writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
+#if defined(CONFIG_CPU_PXA27X)
+	writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
+#endif
+
+	writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
+	writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
+	writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
+	writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
+	writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
+	writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
+#if defined(CONFIG_CPU_PXA27X)
+	writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
+	writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
+#endif
+
+	writel(CONFIG_SYS_PSSR_VAL, PSSR);
+}
+
+void pxa_interrupt_setup(void)
+{
+	writel(0, ICLR);
+	writel(0, ICMR);
+#if defined(CONFIG_CPU_PXA27X)
+	writel(0, ICLR2);
+	writel(0, ICMR2);
+#endif
+}
+
+void pxa_clock_setup(void)
+{
+	writel(CONFIG_SYS_CKEN, CKEN);
+	writel(CONFIG_SYS_CCCR, CCCR);
+	asm volatile("mcr	p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
+
+	/* enable the 32Khz oscillator for RTC and PowerManager */
+	writel(OSCC_OON, OSCC);
+	while (!(readl(OSCC) & OSCC_OOK))
+		asm volatile("" : : : "memory");
+}
+
+void pxa_wakeup(void)
+{
+	uint32_t rcsr;
+
+	rcsr = readl(RCSR);
+	writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
+
+	/* Wakeup */
+	if (rcsr & RCSR_SMR) {
+		writel(PSSR_PH, PSSR);
+		pxa2xx_dram_init();
+		icache_disable();
+		dcache_disable();
+		asm volatile("mov	pc, %0" : : "r"(readl(PSPR)));
+	}
+}
+
+int arch_cpu_init(void)
+{
+	pxa_gpio_setup();
+	pxa_wakeup();
+	pxa_interrupt_setup();
+	pxa_clock_setup();
+	return 0;
+}
+
+void i2c_clk_enable(void)
+{
+	/* Set the global I2C clock on */
+	writel(readl(CKEN) | CKEN14_I2C, CKEN);
+}
+
+void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
+
+void reset_cpu(ulong ignored)
+{
+	uint32_t tmp;
+
+	setbits_le32(OWER, OWER_WME);
+
+	tmp = readl(OSCR);
+	tmp += 0x1000;
+	writel(tmp, OSMR3);
+	writel(MDREFR_SLFRSH, MDREFR);
+
+	for (;;)
+		;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/pxa/start.S b/qemu/roms/u-boot/arch/arm/cpu/pxa/start.S
new file mode 100644
index 000000000..ae0d13ce8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/pxa/start.S
@@ -0,0 +1,450 @@
+/*
+ *  armboot - Startup Code for XScale CPU-core
+ *
+ *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
+ *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
+ *  Copyright (C) 2001	Alex Zuepke <azu@sysgo.de>
+ *  Copyright (C) 2001	Marius Groger <mag@sysgo.de>
+ *  Copyright (C) 2002	Alex Zupke <azu@sysgo.de>
+ *  Copyright (C) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (C) 2002	Kyle Harris <kharris@nexus-tech.net>
+ *  Copyright (C) 2003	Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ *  Copyright (C) 2003	Kshitij <kshitij@ti.com>
+ *  Copyright (C) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (C) 2003	Robert Schwebel <r.schwebel@pengutronix.de>
+ *  Copyright (C) 2004	Texas Instruments <r-woodruff2@ti.com>
+ *  Copyright (C) 2010	Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+
+#ifdef CONFIG_CPU_PXA25X
+#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
+#error "Init SP address must be set to 0xfffff800 for PXA250"
+#endif
+#endif
+
+.globl _start
+_start: b	reset
+#ifdef CONFIG_SPL_BUILD
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+
+_hang:
+	.word	do_hang
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678	/* now 16*4=64 */
+#else
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_SPL_BUILD */
+.global _end_vect
+_end_vect:
+
+	.balignl 16,0xdeadbeef
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl  cpu_init_crit
+#endif
+
+#ifdef	CONFIG_CPU_PXA25X
+	bl	lock_cache_for_stack
+#endif
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+#ifdef CONFIG_CPU_PXA25X
+	/*
+	 * Unlock (actually, disable) the cache now that board_init_f
+	 * is done. We could do this earlier but we would need to add
+	 * a new C runtime hook, whereas c_runtime_cpu_setup already
+	 * exists.
+	 * As this routine is just a call to cpu_init_crit, let us
+	 * tail-optimize and do a simple branch here.
+	 */
+	b	cpu_init_crit
+#else
+	bx	lr
+#endif
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00003300	@ clear bits 13:12, 9:8 (--VI --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	mcr	p15, 0, r0, c1, c0, 0
+
+	mov	pc, lr		/* back to my caller */
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
+	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
+
+	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
+	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp				@ save current stack into r0 (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
+
+	str	lr, [r13]			@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13			@ switch modes, make sure moves will execute
+	mov	lr, pc				@ capture return pc
+	movs	pc, lr				@ jump to next instruction & switch modes.
+	.endm
+
+	.macro get_bad_stack_swi
+	sub	r13, r13, #4			@ space on current stack for scratch reg.
+	str	r0, [r13]			@ save R0's value.
+	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
+	str	lr, [r0]			@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
+	ldr	lr, [r0]			@ restore lr
+	ldr	r0, [r13]			@ restore r0
+	add	r13, r13, #4			@ pop stack entry
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+#endif	/* CONFIG_SPL_BUILD */
+
+/*
+ * exception handlers
+ */
+#ifdef CONFIG_SPL_BUILD
+	.align	5
+do_hang:
+	bl	hang				/* hang and never return */
+#else	/* !CONFIG_SPL_BUILD */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack_swi
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+	.align 5
+#endif	/* CONFIG_SPL_BUILD */
+
+
+/*
+ * Enable MMU to use DCache as DRAM.
+ *
+ * This is useful on PXA25x and PXA26x in early bootstages, where there is no
+ * other possible memory available to hold stack.
+ */
+#ifdef CONFIG_CPU_PXA25X
+.macro CPWAIT reg
+	mrc	p15, 0, \reg, c2, c0, 0
+	mov	\reg, \reg
+	sub	pc, pc, #4
+.endm
+lock_cache_for_stack:
+	/* Domain access -- enable for all CPs */
+	ldr	r0, =0x0000ffff
+	mcr	p15, 0, r0, c3, c0, 0
+
+	/* Point TTBR to MMU table */
+	ldr	r0, =mmutable
+	mcr	p15, 0, r0, c2, c0, 0
+
+	/* Kick in MMU, ICache, DCache, BTB */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, #0x1b00
+	bic	r0, #0x0087
+	orr	r0, #0x1800
+	orr	r0, #0x0005
+	mcr	p15, 0, r0, c1, c0, 0
+	CPWAIT	r0
+
+	/* Unlock Icache, Dcache */
+	mcr	p15, 0, r0, c9, c1, 1
+	mcr	p15, 0, r0, c9, c2, 1
+
+	/* Flush Icache, Dcache, BTB */
+	mcr	p15, 0, r0, c7, c7, 0
+
+	/* Unlock I-TLB, D-TLB */
+	mcr	p15, 0, r0, c10, c4, 1
+	mcr	p15, 0, r0, c10, c8, 1
+
+	/* Flush TLB */
+	mcr	p15, 0, r0, c8, c7, 0
+
+	/* Allocate 4096 bytes of Dcache as RAM */
+
+	/* Drain pending loads and stores */
+	mcr	p15, 0, r0, c7, c10, 4
+
+	mov	r4, #0x00
+	mov	r5, #0x00
+	mov	r2, #0x01
+	mcr	p15, 0, r0, c9, c2, 0
+	CPWAIT	r0
+
+	/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
+	mov	r0, #128
+	ldr	r1, =0xfffff000
+
+alloc:
+	mcr	p15, 0, r1, c7, c2, 5
+	/* Drain pending loads and stores */
+	mcr	p15, 0, r0, c7, c10, 4
+	strd	r4, [r1], #8
+	strd	r4, [r1], #8
+	strd	r4, [r1], #8
+	strd	r4, [r1], #8
+	subs	r0, #0x01
+	bne	alloc
+	/* Drain pending loads and stores */
+	mcr	p15, 0, r0, c7, c10, 4
+	mov	r2, #0x00
+	mcr	p15, 0, r2, c9, c2, 0
+	CPWAIT	r0
+
+	mov	pc, lr
+
+.section .mmutable, "a"
+mmutable:
+	.align	14
+	/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
+	.set	__base, 0
+	.rept	0xfff
+	.word	(__base << 20) | 0xc12
+	.set	__base, __base + 1
+	.endr
+
+	/* 0xfff00000 : 1:1, cached mapping */
+	.word	(0xfff << 20) | 0x1c1e
+#endif	/* CONFIG_CPU_PXA25X */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/pxa/timer.c b/qemu/roms/u-boot/arch/arm/cpu/pxa/timer.c
new file mode 100644
index 000000000..c4717de6a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/pxa/timer.c
@@ -0,0 +1,85 @@
+/*
+ * Marvell PXA2xx/3xx timer driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+#include <common.h>
+#include <div64.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define	TIMER_LOAD_VAL	0xffffffff
+
+#define	timestamp	(gd->arch.tbl)
+#define	lastinc		(gd->arch.lastinc)
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define	TIMER_FREQ_HZ	3250000
+#elif defined(CONFIG_CPU_PXA25X)
+#define	TIMER_FREQ_HZ	3686400
+#else
+#error "Timer frequency unknown - please config PXA CPU type"
+#endif
+
+static unsigned long long tick_to_time(unsigned long long tick)
+{
+	return lldiv(tick * CONFIG_SYS_HZ, TIMER_FREQ_HZ);
+}
+
+static unsigned long long us_to_tick(unsigned long long us)
+{
+	return lldiv(us * TIMER_FREQ_HZ, 1000000);
+}
+
+int timer_init(void)
+{
+	writel(0, OSCR);
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	/* Current tick value */
+	uint32_t now = readl(OSCR);
+
+	if (now >= lastinc) {
+		/*
+		 * Normal mode (non roll)
+		 * Move stamp forward with absolute diff ticks
+		 */
+		timestamp += (now - lastinc);
+	} else {
+		/* We have rollover of incrementer */
+		timestamp += (TIMER_LOAD_VAL - lastinc) + now;
+	}
+
+	lastinc = now;
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return tick_to_time(get_ticks()) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+ulong get_tbclk(void)
+{
+	return TIMER_FREQ_HZ;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/pxa/usb.c b/qemu/roms/u-boot/arch/arm/cpu/pxa/usb.c
new file mode 100644
index 000000000..c31c2d733
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/pxa/usb.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+#include <usb.h>
+
+int usb_cpu_init(void)
+{
+#if defined(CONFIG_CPU_MONAHANS)
+	/* Enable USB host clock. */
+	writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
+	udelay(100);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+	/* Enable USB host clock. */
+	writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
+#endif
+
+#if defined(CONFIG_CPU_MONAHANS)
+	/* Configure Port 2 for Host (USB Client Registers) */
+	writel(0x3000c, UP2OCR);
+#endif
+
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	mdelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		udelay(1);
+
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+	writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+	writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
+#endif
+	writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
+
+	return 0;
+}
+
+int usb_cpu_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
+	udelay(10);
+
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+	writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+	writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
+#endif
+	writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
+
+#if defined(CONFIG_CPU_MONAHANS)
+	/* Disable USB host clock. */
+	writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
+	udelay(100);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+	/* Disable USB host clock. */
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+#endif
+
+	return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+	return usb_cpu_stop();
+}
+
+# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/sa1100/Makefile b/qemu/roms/u-boot/arch/arm/cpu/sa1100/Makefile
new file mode 100644
index 000000000..85a0d28f4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/sa1100/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+
+obj-y	+= cpu.o
+obj-y	+= timer.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/sa1100/config.mk b/qemu/roms/u-boot/arch/arm/cpu/sa1100/config.mk
new file mode 100644
index 000000000..3afa685b3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/sa1100/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
diff --git a/qemu/roms/u-boot/arch/arm/cpu/sa1100/cpu.c b/qemu/roms/u-boot/arch/arm/cpu/sa1100/cpu.c
new file mode 100644
index 000000000..6651898de
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/sa1100/cpu.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * just disable everything that can disturb booting linux
+	 */
+
+	disable_interrupts ();
+
+	/* turn off I-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I-cache */
+	cache_flush();
+
+	return (0);
+}
+
+/* flush I/D-cache */
+static void cache_flush (void)
+{
+	unsigned long i = 0;
+
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/sa1100/start.S b/qemu/roms/u-boot/arch/arm/cpu/sa1100/start.S
new file mode 100644
index 000000000..bf80937a7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/sa1100/start.S
@@ -0,0 +1,349 @@
+/*
+ *  armboot - Startup Code for SA1100 CPU
+ *
+ *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
+ *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
+ *  Copyright (c) 2001	Alex Züpke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:	b       reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:	.word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+
+	.balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+	bl	_main
+
+/*------------------------------------------------------------------------------*/
+
+	.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+	mov	pc, lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+/* Interrupt-Controller base address */
+IC_BASE:	.word	0x90050000
+#define ICMR	0x04
+
+
+/* Reset-Controller */
+RST_BASE:		.word   0x90030000
+#define RSRR	0x00
+#define RCSR	0x04
+
+
+/* PWR */
+PWR_BASE:		.word   0x90020000
+#define PSPR    0x08
+#define PPCR    0x14
+cpuspeed:		.word   CONFIG_SYS_CPUSPEED
+
+
+cpu_init_crit:
+	/*
+	 * mask all IRQs
+	 */
+	ldr	r0, IC_BASE
+	mov	r1, #0x00
+	str	r1, [r0, #ICMR]
+
+	/* set clock speed */
+	ldr	r0, PWR_BASE
+	ldr	r1, cpuspeed
+	str	r1, [r0, #PPCR]
+
+	/*
+	 * before relocating, we have to setup RAM timing
+	 * because memory timing is board-dependend, you will
+	 * find a lowlevel_init.S in your board directory.
+	 */
+	mov	ip,	lr
+	bl	lowlevel_init
+	mov	lr,	ip
+
+	/*
+	 * disable MMU stuff and enable I-cache
+	 */
+	mrc	p15,0,r0,c1,c0
+	bic	r0, r0, #0x00002000	@ clear bit 13 (X)
+	bic	r0, r0, #0x0000000f	@ clear bits 3-0 (WCAM)
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) Icache
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	mcr	p15,0,r0,c1,c0
+
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	mov	pc, lr
+
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add     r8, sp, #S_PC
+
+	ldr	r2, IRQ_STACK_START_IN
+	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
+	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
+	mov	r0, sp
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add     r8, sp, #S_PC
+	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
+	str     lr, [r8, #0]                    @ Save calling PC
+	mrs     r6, spsr
+	str     r6, [r8, #4]                    @ Save CPSR
+	str     r0, [r8, #8]                    @ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+
+	str	lr, [r13]			@ save caller lr / spsr
+	mrs	lr, spsr
+	str     lr, [r13, #4]
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	msr	spsr_c, r13
+	mov	lr, pc
+	movs	pc, lr
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align  5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr	r0, RST_BASE
+	mov	r1, #0x0			@ set bit 3-0 ...
+	str	r1, [r0, #RCSR]			@ ... to clear in RCSR
+	mov	r1, #0x1
+	str	r1, [r0, #RSRR]			@ and perform reset
+	b	reset_cpu			@ silly, but repeat endlessly
diff --git a/qemu/roms/u-boot/arch/arm/cpu/sa1100/timer.c b/qemu/roms/u-boot/arch/arm/cpu/sa1100/timer.c
new file mode 100644
index 000000000..0a0006b42
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/sa1100/timer.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked ();
+}
+
+void __udelay (unsigned long usec)
+{
+	udelay_masked (usec);
+}
+
+ulong get_timer_masked (void)
+{
+	return OSCR;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 1000;
+	} else {
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/Makefile
new file mode 100644
index 000000000..892556e64
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/Makefile
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ap.o
+obj-y += board.o
+obj-y += cache.o
+obj-y += clock.o
+obj-y += lowlevel_init.o
+obj-y += pinmux-common.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra-common/ap.c b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/ap.c
new file mode 100644
index 000000000..91d70da65
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/ap.c
@@ -0,0 +1,166 @@
+/*
+* (C) Copyright 2010-2014
+* NVIDIA Corporation <www.nvidia.com>
+*
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+/* Tegra AP (Application Processor) code */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clock.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include <asm/arch-tegra/tegra.h>
+#include <asm/arch-tegra/warmboot.h>
+
+int tegra_get_chip(void)
+{
+	int rev;
+	struct apb_misc_gp_ctlr *gp =
+		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+
+	/*
+	 * This is undocumented, Chip ID is bits 15:8 of the register
+	 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
+	 * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
+	 */
+	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
+	debug("%s: CHIPID is 0x%02X\n", __func__, rev);
+
+	return rev;
+}
+
+int tegra_get_sku_info(void)
+{
+	int sku_id;
+	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
+
+	sku_id = readl(&fuse->sku_info) & 0xff;
+	debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
+
+	return sku_id;
+}
+
+int tegra_get_chip_sku(void)
+{
+	uint sku_id, chip_id;
+
+	chip_id = tegra_get_chip();
+	sku_id = tegra_get_sku_info();
+
+	switch (chip_id) {
+	case CHIPID_TEGRA20:
+		switch (sku_id) {
+		case SKU_ID_T20_7:
+		case SKU_ID_T20:
+			return TEGRA_SOC_T20;
+		case SKU_ID_T25SE:
+		case SKU_ID_AP25:
+		case SKU_ID_T25:
+		case SKU_ID_AP25E:
+		case SKU_ID_T25E:
+			return TEGRA_SOC_T25;
+		}
+		break;
+	case CHIPID_TEGRA30:
+		switch (sku_id) {
+		case SKU_ID_T33:
+		case SKU_ID_T30:
+		case SKU_ID_TM30MQS_P_A3:
+		default:
+			return TEGRA_SOC_T30;
+		}
+		break;
+	case CHIPID_TEGRA114:
+		switch (sku_id) {
+		case SKU_ID_T114_ENG:
+		case SKU_ID_T114_1:
+		default:
+			return TEGRA_SOC_T114;
+		}
+		break;
+	case CHIPID_TEGRA124:
+		switch (sku_id) {
+		case SKU_ID_T124_ENG:
+		default:
+			return TEGRA_SOC_T124;
+		}
+		break;
+	}
+
+	/* unknown chip/sku id */
+	printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
+		__func__, chip_id, sku_id);
+	return TEGRA_SOC_UNKNOWN;
+}
+
+static void enable_scu(void)
+{
+	struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
+	u32 reg;
+
+	/* Only enable the SCU on T20/T25 */
+	if (tegra_get_chip() != CHIPID_TEGRA20)
+		return;
+
+	/* If SCU already setup/enabled, return */
+	if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
+		return;
+
+	/* Invalidate all ways for all processors */
+	writel(0xFFFF, &scu->scu_inv_all);
+
+	/* Enable SCU - bit 0 */
+	reg = readl(&scu->scu_ctrl);
+	reg |= SCU_CTRL_ENABLE;
+	writel(reg, &scu->scu_ctrl);
+}
+
+static u32 get_odmdata(void)
+{
+	/*
+	 * ODMDATA is stored in the BCT in IRAM by the BootROM.
+	 * The BCT start and size are stored in the BIT in IRAM.
+	 * Read the data @ bct_start + (bct_size - 12). This works
+	 * on BCTs for currently supported SoCs, which are locked down.
+	 * If this changes in new chips, we can revisit this algorithm.
+	 */
+
+	u32 bct_start, odmdata;
+
+	bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
+	odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
+
+	return odmdata;
+}
+
+static void init_pmc_scratch(void)
+{
+	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 odmdata;
+	int i;
+
+	/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
+	for (i = 0; i < 23; i++)
+		writel(0, &pmc->pmc_scratch1+i);
+
+	/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
+	odmdata = get_odmdata();
+	writel(odmdata, &pmc->pmc_scratch20);
+}
+
+void s_init(void)
+{
+	/* Init PMC scratch memory */
+	init_pmc_scratch();
+
+	enable_scu();
+
+	/* init the cache */
+	config_cache();
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra-common/board.c b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/board.c
new file mode 100644
index 000000000..6a6faf4b2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/board.c
@@ -0,0 +1,181 @@
+/*
+ *  (C) Copyright 2010-2014
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/warmboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	/* UARTs which we can enable */
+	UARTA	= 1 << 0,
+	UARTB	= 1 << 1,
+	UARTC	= 1 << 2,
+	UARTD	= 1 << 3,
+	UARTE	= 1 << 4,
+	UART_COUNT = 5,
+};
+
+/*
+ * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
+ * so we are using this value to identify memory size.
+ */
+
+unsigned int query_sdram_size(void)
+{
+	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	reg = readl(&pmc->pmc_scratch20);
+	debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
+
+#if defined(CONFIG_TEGRA20)
+	/* bits 30:28 in OdmData are used for RAM size on T20  */
+	reg &= 0x70000000;
+
+	switch ((reg) >> 28) {
+	case 1:
+		return 0x10000000;	/* 256 MB */
+	case 0:
+	case 2:
+	default:
+		return 0x20000000;	/* 512 MB */
+	case 3:
+		return 0x40000000;	/* 1GB */
+	}
+#else	/* Tegra30/Tegra114 */
+	/* bits 31:28 in OdmData are used for RAM size on T30  */
+	switch ((reg) >> 28) {
+	case 0:
+	case 1:
+	default:
+		return 0x10000000;	/* 256 MB */
+	case 2:
+		return 0x20000000;	/* 512 MB */
+	case 3:
+		return 0x30000000;	/* 768 MB */
+	case 4:
+		return 0x40000000;	/* 1GB */
+	case 8:
+		return 0x7ff00000;	/* 2GB - 1MB */
+	}
+#endif
+}
+
+int dram_init(void)
+{
+	/* We do not initialise DRAM here. We just query the size */
+	gd->ram_size = query_sdram_size();
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("Board: %s\n", sysinfo.board_string);
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_BOARDINFO */
+
+static int uart_configs[] = {
+#if defined(CONFIG_TEGRA20)
+ #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
+	FUNCMUX_UART1_UAA_UAB,
+ #elif defined(CONFIG_TEGRA_UARTA_GPU)
+	FUNCMUX_UART1_GPU,
+ #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
+	FUNCMUX_UART1_SDIO1,
+ #else
+	FUNCMUX_UART1_IRRX_IRTX,
+#endif
+	FUNCMUX_UART2_UAD,
+	-1,
+	FUNCMUX_UART4_GMC,
+	-1,
+#elif defined(CONFIG_TEGRA30)
+	FUNCMUX_UART1_ULPI,	/* UARTA */
+	-1,
+	-1,
+	-1,
+	-1,
+#elif defined(CONFIG_TEGRA114)
+	-1,
+	-1,
+	-1,
+	FUNCMUX_UART4_GMI,	/* UARTD */
+	-1,
+#else	/* Tegra124 */
+	FUNCMUX_UART1_KBC,	/* UARTA */
+	-1,
+	-1,
+	FUNCMUX_UART4_GPIO,	/* UARTD */
+	-1,
+#endif
+};
+
+/**
+ * Set up the specified uarts
+ *
+ * @param uarts_ids	Mask containing UARTs to init (UARTx)
+ */
+static void setup_uarts(int uart_ids)
+{
+	static enum periph_id id_for_uart[] = {
+		PERIPH_ID_UART1,
+		PERIPH_ID_UART2,
+		PERIPH_ID_UART3,
+		PERIPH_ID_UART4,
+		PERIPH_ID_UART5,
+	};
+	size_t i;
+
+	for (i = 0; i < UART_COUNT; i++) {
+		if (uart_ids & (1 << i)) {
+			enum periph_id id = id_for_uart[i];
+
+			funcmux_select(id, uart_configs[i]);
+			clock_ll_start_uart(id);
+		}
+	}
+}
+
+void board_init_uart_f(void)
+{
+	int uart_ids = 0;	/* bit mask of which UART ids to enable */
+
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
+	uart_ids |= UARTA;
+#endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTB
+	uart_ids |= UARTB;
+#endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTC
+	uart_ids |= UARTC;
+#endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTD
+	uart_ids |= UARTD;
+#endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTE
+	uart_ids |= UARTE;
+#endif
+	setup_uarts(uart_ids);
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra-common/cache.c b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/cache.c
new file mode 100644
index 000000000..94f5bce90
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/cache.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra cache routines */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch/gp_padctrl.h>
+
+void config_cache(void)
+{
+	u32 reg = 0;
+
+	/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
+	asm volatile(
+		"mrc p15, 0, r0, c1, c0, 1\n"
+		"orr r0, r0, #0x41\n"
+		"mcr p15, 0, r0, c1, c0, 1\n");
+
+	/* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
+	if (tegra_get_chip() < CHIPID_TEGRA114)
+		return;
+
+	/*
+	 * Systems with an architectural L2 cache must not use the PL310.
+	 * Config L2CTLR here for a data RAM latency of 3 cycles.
+	 */
+	asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
+	reg &= ~7;
+	reg |= 2;
+	asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra-common/clock.c b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/clock.c
new file mode 100644
index 000000000..11c743550
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/clock.c
@@ -0,0 +1,669 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra SoC common clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * This is our record of the current clock rate of each clock. We don't
+ * fill all of these in since we are only really interested in clocks which
+ * we use as parents.
+ */
+static unsigned pll_rate[CLOCK_ID_COUNT];
+
+/*
+ * The oscillator frequency is fixed to one of four set values. Based on this
+ * the other clocks are set up appropriately.
+ */
+static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
+	13000000,
+	19200000,
+	12000000,
+	26000000,
+};
+
+/* return 1 if a peripheral ID is in range */
+#define clock_type_id_isvalid(id) ((id) >= 0 && \
+		(id) < CLOCK_TYPE_COUNT)
+
+char pllp_valid = 1;	/* PLLP is set up correctly */
+
+/* return 1 if a periphc_internal_id is in range */
+#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
+		(id) < PERIPHC_COUNT)
+
+/* number of clock outputs of a PLL */
+static const u8 pll_num_clkouts[] = {
+	1,	/* PLLC */
+	1,	/* PLLM */
+	4,	/* PLLP */
+	1,	/* PLLA */
+	0,	/* PLLU */
+	0,	/* PLLD */
+};
+
+int clock_get_osc_bypass(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
+}
+
+/* Returns a pointer to the registers of the given pll */
+static struct clk_pll *get_pll(enum clock_id clkid)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+	assert(clock_id_is_pll(clkid));
+	return &clkrst->crc_pll[clkid];
+}
+
+int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
+		u32 *divp, u32 *cpcon, u32 *lfcon)
+{
+	struct clk_pll *pll = get_pll(clkid);
+	u32 data;
+
+	assert(clkid != CLOCK_ID_USB);
+
+	/* Safety check, adds to code size but is small */
+	if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
+		return -1;
+	data = readl(&pll->pll_base);
+	*divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
+	*divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
+	*divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
+	data = readl(&pll->pll_misc);
+	*cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
+	*lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
+
+	return 0;
+}
+
+unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
+		u32 divp, u32 cpcon, u32 lfcon)
+{
+	struct clk_pll *pll = get_pll(clkid);
+	u32 data;
+
+	/*
+	 * We cheat by treating all PLL (except PLLU) in the same fashion.
+	 * This works only because:
+	 * - same fields are always mapped at same offsets, except DCCON
+	 * - DCCON is always 0, doesn't conflict
+	 * - M,N, P of PLLP values are ignored for PLLP
+	 */
+	data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
+	writel(data, &pll->pll_misc);
+
+	data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
+			(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
+
+	if (clkid == CLOCK_ID_USB)
+		data |= divp << PLLU_VCO_FREQ_SHIFT;
+	else
+		data |= divp << PLL_DIVP_SHIFT;
+	writel(data, &pll->pll_base);
+
+	/* calculate the stable time */
+	return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
+}
+
+void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
+			unsigned divisor)
+{
+	u32 *reg = get_periph_source_reg(periph_id);
+	u32 value;
+
+	value = readl(reg);
+
+	value &= ~OUT_CLK_SOURCE_31_30_MASK;
+	value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
+
+	value &= ~OUT_CLK_DIVISOR_MASK;
+	value |= divisor << OUT_CLK_DIVISOR_SHIFT;
+
+	writel(value, reg);
+}
+
+void clock_ll_set_source(enum periph_id periph_id, unsigned source)
+{
+	u32 *reg = get_periph_source_reg(periph_id);
+
+	clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+			source << OUT_CLK_SOURCE_31_30_SHIFT);
+}
+
+/**
+ * Given the parent's rate and the required rate for the children, this works
+ * out the peripheral clock divider to use, in 7.1 binary format.
+ *
+ * @param divider_bits	number of divider bits (8 or 16)
+ * @param parent_rate	clock rate of parent clock in Hz
+ * @param rate		required clock rate for this clock
+ * @return divider which should be used
+ */
+static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
+			   unsigned long rate)
+{
+	u64 divider = parent_rate * 2;
+	unsigned max_divider = 1 << divider_bits;
+
+	divider += rate - 1;
+	do_div(divider, rate);
+
+	if ((s64)divider - 2 < 0)
+		return 0;
+
+	if ((s64)divider - 2 >= max_divider)
+		return -1;
+
+	return divider - 2;
+}
+
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
+{
+	struct clk_pll *pll = get_pll(clkid);
+	int data = 0, div = 0, offset = 0;
+
+	if (!clock_id_is_pll(clkid))
+		return -1;
+
+	if (pllout + 1 > pll_num_clkouts[clkid])
+		return -1;
+
+	div = clk_get_divider(8, pll_rate[clkid], rate);
+
+	if (div < 0)
+		return -1;
+
+	/* out2 and out4 are in the high part of the register */
+	if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
+		offset = 16;
+
+	data = (div << PLL_OUT_RATIO_SHIFT) |
+			PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
+	clrsetbits_le32(&pll->pll_out[pllout >> 1],
+			PLL_OUT_RATIO_MASK << offset, data << offset);
+
+	return 0;
+}
+
+/**
+ * Given the parent's rate and the divider in 7.1 format, this works out the
+ * resulting peripheral clock rate.
+ *
+ * @param parent_rate	clock rate of parent clock in Hz
+ * @param divider which should be used in 7.1 format
+ * @return effective clock rate of peripheral
+ */
+static unsigned long get_rate_from_divider(unsigned long parent_rate,
+					   int divider)
+{
+	u64 rate;
+
+	rate = (u64)parent_rate * 2;
+	do_div(rate, divider + 2);
+	return rate;
+}
+
+unsigned long clock_get_periph_rate(enum periph_id periph_id,
+		enum clock_id parent)
+{
+	u32 *reg = get_periph_source_reg(periph_id);
+
+	return get_rate_from_divider(pll_rate[parent],
+		(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
+}
+
+/**
+ * Find the best available 7.1 format divisor given a parent clock rate and
+ * required child clock rate. This function assumes that a second-stage
+ * divisor is available which can divide by powers of 2 from 1 to 256.
+ *
+ * @param divider_bits	number of divider bits (8 or 16)
+ * @param parent_rate	clock rate of parent clock in Hz
+ * @param rate		required clock rate for this clock
+ * @param extra_div	value for the second-stage divisor (not set if this
+ *			function returns -1.
+ * @return divider which should be used, or -1 if nothing is valid
+ *
+ */
+static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
+				unsigned long rate, int *extra_div)
+{
+	int shift;
+	int best_divider = -1;
+	int best_error = rate;
+
+	/* try dividers from 1 to 256 and find closest match */
+	for (shift = 0; shift <= 8 && best_error > 0; shift++) {
+		unsigned divided_parent = parent_rate >> shift;
+		int divider = clk_get_divider(divider_bits, divided_parent,
+						rate);
+		unsigned effective_rate = get_rate_from_divider(divided_parent,
+						divider);
+		int error = rate - effective_rate;
+
+		/* Given a valid divider, look for the lowest error */
+		if (divider != -1 && error < best_error) {
+			best_error = error;
+			*extra_div = 1 << shift;
+			best_divider = divider;
+		}
+	}
+
+	/* return what we found - *extra_div will already be set */
+	return best_divider;
+}
+
+/**
+ * Adjust peripheral PLL to use the given divider and source.
+ *
+ * @param periph_id	peripheral to adjust
+ * @param source	Source number (0-3 or 0-7)
+ * @param mux_bits	Number of mux bits (2 or 4)
+ * @param divider	Required divider in 7.1 or 15.1 format
+ * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
+ *		for this peripheral)
+ */
+static int adjust_periph_pll(enum periph_id periph_id, int source,
+				int mux_bits, unsigned divider)
+{
+	u32 *reg = get_periph_source_reg(periph_id);
+
+	clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
+			divider << OUT_CLK_DIVISOR_SHIFT);
+	udelay(1);
+
+	/* work out the source clock and set it */
+	if (source < 0)
+		return -1;
+
+	switch (mux_bits) {
+	case MASK_BITS_31_30:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+				source << OUT_CLK_SOURCE_31_30_SHIFT);
+		break;
+
+	case MASK_BITS_31_29:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
+				source << OUT_CLK_SOURCE_31_29_SHIFT);
+		break;
+
+	case MASK_BITS_31_28:
+		clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+				source << OUT_CLK_SOURCE_31_28_SHIFT);
+		break;
+
+	default:
+		return -1;
+	}
+
+	udelay(2);
+	return 0;
+}
+
+unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
+		enum clock_id parent, unsigned rate, int *extra_div)
+{
+	unsigned effective_rate;
+	int mux_bits, divider_bits, source;
+	int divider;
+	int xdiv = 0;
+
+	/* work out the source clock and set it */
+	source = get_periph_clock_source(periph_id, parent, &mux_bits,
+					 &divider_bits);
+
+	divider = find_best_divider(divider_bits, pll_rate[parent],
+				    rate, &xdiv);
+	if (extra_div)
+		*extra_div = xdiv;
+
+	assert(divider >= 0);
+	if (adjust_periph_pll(periph_id, source, mux_bits, divider))
+		return -1U;
+	debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
+		get_periph_source_reg(periph_id),
+		readl(get_periph_source_reg(periph_id)));
+
+	/* Check what we ended up with. This shouldn't matter though */
+	effective_rate = clock_get_periph_rate(periph_id, parent);
+	if (extra_div)
+		effective_rate /= *extra_div;
+	if (rate != effective_rate)
+		debug("Requested clock rate %u not honored (got %u)\n",
+			rate, effective_rate);
+	return effective_rate;
+}
+
+unsigned clock_start_periph_pll(enum periph_id periph_id,
+		enum clock_id parent, unsigned rate)
+{
+	unsigned effective_rate;
+
+	reset_set_enable(periph_id, 1);
+	clock_enable(periph_id);
+
+	effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
+						 NULL);
+
+	reset_set_enable(periph_id, 0);
+	return effective_rate;
+}
+
+void clock_enable(enum periph_id clkid)
+{
+	clock_set_enable(clkid, 1);
+}
+
+void clock_disable(enum periph_id clkid)
+{
+	clock_set_enable(clkid, 0);
+}
+
+void reset_periph(enum periph_id periph_id, int us_delay)
+{
+	/* Put peripheral into reset */
+	reset_set_enable(periph_id, 1);
+	udelay(us_delay);
+
+	/* Remove reset */
+	reset_set_enable(periph_id, 0);
+
+	udelay(us_delay);
+}
+
+void reset_cmplx_set_enable(int cpu, int which, int reset)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 mask;
+
+	/* Form the mask, which depends on the cpu chosen (2 or 4) */
+	assert(cpu >= 0 && cpu < MAX_NUM_CPU);
+	mask = which << cpu;
+
+	/* either enable or disable those reset for that CPU */
+	if (reset)
+		writel(mask, &clkrst->crc_cpu_cmplx_set);
+	else
+		writel(mask, &clkrst->crc_cpu_cmplx_clr);
+}
+
+unsigned clock_get_rate(enum clock_id clkid)
+{
+	struct clk_pll *pll;
+	u32 base;
+	u32 divm;
+	u64 parent_rate;
+	u64 rate;
+
+	parent_rate = osc_freq[clock_get_osc_freq()];
+	if (clkid == CLOCK_ID_OSC)
+		return parent_rate;
+
+	pll = get_pll(clkid);
+	base = readl(&pll->pll_base);
+
+	/* Oh for bf_unpack()... */
+	rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
+	divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
+	if (clkid == CLOCK_ID_USB)
+		divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
+	else
+		divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
+	do_div(rate, divm);
+	return rate;
+}
+
+/**
+ * Set the output frequency you want for each PLL clock.
+ * PLL output frequencies are programmed by setting their N, M and P values.
+ * The governing equations are:
+ *     VCO = (Fi / m) * n, Fo = VCO / (2^p)
+ *     where Fo is the output frequency from the PLL.
+ * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
+ *     216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
+ * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
+ *
+ * @param n PLL feedback divider(DIVN)
+ * @param m PLL input divider(DIVN)
+ * @param p post divider(DIVP)
+ * @param cpcon base PLL charge pump(CPCON)
+ * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
+ *		be overriden), 1 if PLL is already correct
+ */
+int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
+{
+	u32 base_reg;
+	u32 misc_reg;
+	struct clk_pll *pll;
+
+	pll = get_pll(clkid);
+
+	base_reg = readl(&pll->pll_base);
+
+	/* Set BYPASS, m, n and p to PLL_BASE */
+	base_reg &= ~PLL_DIVM_MASK;
+	base_reg |= m << PLL_DIVM_SHIFT;
+
+	base_reg &= ~PLL_DIVN_MASK;
+	base_reg |= n << PLL_DIVN_SHIFT;
+
+	base_reg &= ~PLL_DIVP_MASK;
+	base_reg |= p << PLL_DIVP_SHIFT;
+
+	if (clkid == CLOCK_ID_PERIPH) {
+		/*
+		 * If the PLL is already set up, check that it is correct
+		 * and record this info for clock_verify() to check.
+		 */
+		if (base_reg & PLL_BASE_OVRRIDE_MASK) {
+			base_reg |= PLL_ENABLE_MASK;
+			if (base_reg != readl(&pll->pll_base))
+				pllp_valid = 0;
+			return pllp_valid ? 1 : -1;
+		}
+		base_reg |= PLL_BASE_OVRRIDE_MASK;
+	}
+
+	base_reg |= PLL_BYPASS_MASK;
+	writel(base_reg, &pll->pll_base);
+
+	/* Set cpcon to PLL_MISC */
+	misc_reg = readl(&pll->pll_misc);
+	misc_reg &= ~PLL_CPCON_MASK;
+	misc_reg |= cpcon << PLL_CPCON_SHIFT;
+	writel(misc_reg, &pll->pll_misc);
+
+	/* Enable PLL */
+	base_reg |= PLL_ENABLE_MASK;
+	writel(base_reg, &pll->pll_base);
+
+	/* Disable BYPASS */
+	base_reg &= ~PLL_BYPASS_MASK;
+	writel(base_reg, &pll->pll_base);
+
+	return 0;
+}
+
+void clock_ll_start_uart(enum periph_id periph_id)
+{
+	/* Assert UART reset and enable clock */
+	reset_set_enable(periph_id, 1);
+	clock_enable(periph_id);
+	clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
+
+	/* wait for 2us */
+	udelay(2);
+
+	/* De-assert reset to UART */
+	reset_set_enable(periph_id, 0);
+}
+
+#ifdef CONFIG_OF_CONTROL
+int clock_decode_periph_id(const void *blob, int node)
+{
+	enum periph_id id;
+	u32 cell[2];
+	int err;
+
+	err = fdtdec_get_int_array(blob, node, "clocks", cell,
+				   ARRAY_SIZE(cell));
+	if (err)
+		return -1;
+	id = clk_id_to_periph_id(cell[1]);
+	assert(clock_periph_id_isvalid(id));
+	return id;
+}
+#endif /* CONFIG_OF_CONTROL */
+
+int clock_verify(void)
+{
+	struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
+	u32 reg = readl(&pll->pll_base);
+
+	if (!pllp_valid) {
+		printf("Warning: PLLP %x is not correct\n", reg);
+		return -1;
+	}
+	debug("PLLP %x is correct\n", reg);
+	return 0;
+}
+
+void clock_init(void)
+{
+	pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
+	pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
+	pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
+	pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
+	pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
+	pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
+	debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
+	debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
+	debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
+	debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
+	debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
+
+	/* Do any special system timer/TSC setup */
+	arch_timer_init();
+}
+
+static void set_avp_clock_source(u32 src)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 val;
+
+	val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+		(src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+		(src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+		(src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+		(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+	writel(val, &clkrst->crc_sclk_brst_pol);
+	udelay(3);
+}
+
+/*
+ * This function is useful on Tegra30, and any later SoCs that have compatible
+ * PLLP configuration registers.
+ */
+void tegra30_set_up_pllp(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	/*
+	 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
+	 * run up to 275MHz. On power on, the default sytem clock source is set
+	 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
+	 * 408MHz which is beyond system clock's upper limit.
+	 *
+	 * The fix is to set the system clock to CLK_M before initializing PLLP,
+	 * and then switch back to PLLP_OUT4, which has an appropriate divider
+	 * configured, after PLLP has been configured
+	 */
+	set_avp_clock_source(SCLK_SOURCE_CLKM);
+
+	/*
+	 * PLLP output frequency set to 408Mhz
+	 * PLLC output frequency set to 228Mhz
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+
+	/* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+
+	/* OUT1, 2 */
+	/* Assert RSTN before enable */
+	reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+	/* Set divisor and reenable */
+	reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
+		| PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
+		| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
+		| PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+
+	/* OUT3, 4 */
+	/* Assert RSTN before enable */
+	reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+	/* Set divisor and reenable */
+	reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
+		| PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
+		| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
+		| PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+
+	set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra-common/lowlevel_init.S b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/lowlevel_init.S
new file mode 100644
index 000000000..a211bb3b1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/lowlevel_init.S
@@ -0,0 +1,26 @@
+/*
+ * SoC-specific setup info
+ *
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+
+	.align	5
+ENTRY(reset_cpu)
+	ldr	r1, rstctl			@ get addr for global reset
+						@ reg
+	ldr	r3, [r1]
+	orr	r3, r3, #0x10
+	str	r3, [r1]			@ force reset
+	mov	r0, r0
+_loop_forever:
+	b	_loop_forever
+rstctl:
+	.word	PRM_RSTCTRL
+ENDPROC(reset_cpu)
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra-common/pinmux-common.c b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/pinmux-common.c
new file mode 100644
index 000000000..d62618cd0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -0,0 +1,508 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) \
+	(((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
+
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) \
+	(((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
+
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) \
+	(((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) \
+	(((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
+
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) \
+	(((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) \
+	(((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
+
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+	(((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
+	 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+	(((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
+	 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+#define _R(offset)	(u32 *)(NV_PA_APB_MISC_BASE + (offset))
+
+#if defined(CONFIG_TEGRA20)
+
+#define MUX_REG(grp)	_R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
+#define MUX_SHIFT(grp)	((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
+
+#define PULL_REG(grp)	_R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
+#define PULL_SHIFT(grp)	((tegra_soc_pingroups[grp].pull_id % 16) * 2)
+
+#define TRI_REG(grp)	_R(0x14 + (((grp) / 32) * 4))
+#define TRI_SHIFT(grp)	((grp) % 32)
+
+#else
+
+#define REG(pin)	_R(0x3000 + ((pin) * 4))
+
+#define MUX_REG(pin)	REG(pin)
+#define MUX_SHIFT(pin)	0
+
+#define PULL_REG(pin)	REG(pin)
+#define PULL_SHIFT(pin)	2
+
+#define TRI_REG(pin)	REG(pin)
+#define TRI_SHIFT(pin)	4
+
+#endif /* CONFIG_TEGRA20 */
+
+#define DRV_REG(group)	_R(0x868 + ((group) * 4))
+
+#define IO_SHIFT	5
+#define OD_SHIFT	6
+#define LOCK_SHIFT	7
+#define IO_RESET_SHIFT	8
+#define RCV_SEL_SHIFT	9
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+	u32 *reg = MUX_REG(pin);
+	int i, mux = -1;
+	u32 val;
+
+	/* Error check on pin and func */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_func_isvalid(func));
+
+	if (func >= PMUX_FUNC_RSVD1) {
+		mux = (func - PMUX_FUNC_RSVD1) & 3;
+	} else {
+		/* Search for the appropriate function */
+		for (i = 0; i < 4; i++) {
+			if (tegra_soc_pingroups[pin].funcs[i] == func) {
+				mux = i;
+				break;
+			}
+		}
+	}
+	assert(mux != -1);
+
+	val = readl(reg);
+	val &= ~(3 << MUX_SHIFT(pin));
+	val |= (mux << MUX_SHIFT(pin));
+	writel(val, reg);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+	u32 *reg = PULL_REG(pin);
+	u32 val;
+
+	/* Error check on pin and pupd */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_pupd_isvalid(pupd));
+
+	val = readl(reg);
+	val &= ~(3 << PULL_SHIFT(pin));
+	val |= (pupd << PULL_SHIFT(pin));
+	writel(val, reg);
+}
+
+static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
+{
+	u32 *reg = TRI_REG(pin);
+	u32 val;
+
+	/* Error check on pin */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_tristate_isvalid(tri));
+
+	val = readl(reg);
+	if (tri == PMUX_TRI_TRISTATE)
+		val |= (1 << TRI_SHIFT(pin));
+	else
+		val &= ~(1 << TRI_SHIFT(pin));
+	writel(val, reg);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
+}
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+	u32 *reg = REG(pin);
+	u32 val;
+
+	if (io == PMUX_PIN_NONE)
+		return;
+
+	/* Error check on pin and io */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_io_isvalid(io));
+
+	val = readl(reg);
+	if (io == PMUX_PIN_INPUT)
+		val |= (io & 1) << IO_SHIFT;
+	else
+		val &= ~(1 << IO_SHIFT);
+	writel(val, reg);
+}
+
+static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+	u32 *reg = REG(pin);
+	u32 val;
+
+	if (lock == PMUX_PIN_LOCK_DEFAULT)
+		return;
+
+	/* Error check on pin and lock */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_lock_isvalid(lock));
+
+	val = readl(reg);
+	if (lock == PMUX_PIN_LOCK_ENABLE) {
+		val |= (1 << LOCK_SHIFT);
+	} else {
+		if (val & (1 << LOCK_SHIFT))
+			printf("%s: Cannot clear LOCK bit!\n", __func__);
+		val &= ~(1 << LOCK_SHIFT);
+	}
+	writel(val, reg);
+
+	return;
+}
+
+static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+	u32 *reg = REG(pin);
+	u32 val;
+
+	if (od == PMUX_PIN_OD_DEFAULT)
+		return;
+
+	/* Error check on pin and od */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_od_isvalid(od));
+
+	val = readl(reg);
+	if (od == PMUX_PIN_OD_ENABLE)
+		val |= (1 << OD_SHIFT);
+	else
+		val &= ~(1 << OD_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+
+static void pinmux_set_ioreset(enum pmux_pingrp pin,
+				enum pmux_pin_ioreset ioreset)
+{
+	u32 *reg = REG(pin);
+	u32 val;
+
+	if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+		return;
+
+	/* Error check on pin and ioreset */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_ioreset_isvalid(ioreset));
+
+	val = readl(reg);
+	if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+		val |= (1 << IO_RESET_SHIFT);
+	else
+		val &= ~(1 << IO_RESET_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
+				enum pmux_pin_rcv_sel rcv_sel)
+{
+	u32 *reg = REG(pin);
+	u32 val;
+
+	if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+		return;
+
+	/* Error check on pin and rcv_sel */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+	val = readl(reg);
+	if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+		val |= (1 << RCV_SEL_SHIFT);
+	else
+		val &= ~(1 << RCV_SEL_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
+{
+	enum pmux_pingrp pin = config->pingrp;
+
+	pinmux_set_func(pin, config->func);
+	pinmux_set_pullupdown(pin, config->pull);
+	pinmux_set_tristate(pin, config->tristate);
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+	pinmux_set_io(pin, config->io);
+	pinmux_set_lock(pin, config->lock);
+	pinmux_set_od(pin, config->od);
+	pinmux_set_ioreset(pin, config->ioreset);
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+	pinmux_set_rcv_sel(pin, config->rcv_sel);
+#endif
+#endif
+}
+
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+				int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		pinmux_config_pingrp(&config[i]);
+}
+
+#ifdef TEGRA_PMX_HAS_DRVGRPS
+
+#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
+
+#define pmux_slw_isvalid(slw) \
+	(((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
+
+#define pmux_drv_isvalid(drv) \
+	(((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
+
+#define pmux_lpmd_isvalid(lpm) \
+	(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
+
+#define pmux_schmt_isvalid(schmt) \
+	(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
+
+#define pmux_hsm_isvalid(hsm) \
+	(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
+
+#define HSM_SHIFT	2
+#define SCHMT_SHIFT	3
+#define LPMD_SHIFT	4
+#define LPMD_MASK	(3 << LPMD_SHIFT)
+#define DRVDN_SHIFT	12
+#define DRVDN_MASK	(0x7F << DRVDN_SHIFT)
+#define DRVUP_SHIFT	20
+#define DRVUP_MASK	(0x7F << DRVUP_SHIFT)
+#define SLWR_SHIFT	28
+#define SLWR_MASK	(3 << SLWR_SHIFT)
+#define SLWF_SHIFT	30
+#define SLWF_MASK	(3 << SLWF_SHIFT)
+
+static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
+{
+	u32 *reg = DRV_REG(grp);
+	u32 val;
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (slwf == PMUX_SLWF_NONE)
+		return;
+
+	/* Error check on pad and slwf */
+	assert(pmux_drvgrp_isvalid(grp));
+	assert(pmux_slw_isvalid(slwf));
+
+	val = readl(reg);
+	val &= ~SLWF_MASK;
+	val |= (slwf << SLWF_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+
+static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
+{
+	u32 *reg = DRV_REG(grp);
+	u32 val;
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (slwr == PMUX_SLWR_NONE)
+		return;
+
+	/* Error check on pad and slwr */
+	assert(pmux_drvgrp_isvalid(grp));
+	assert(pmux_slw_isvalid(slwr));
+
+	val = readl(reg);
+	val &= ~SLWR_MASK;
+	val |= (slwr << SLWR_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+
+static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
+{
+	u32 *reg = DRV_REG(grp);
+	u32 val;
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (drvup == PMUX_DRVUP_NONE)
+		return;
+
+	/* Error check on pad and drvup */
+	assert(pmux_drvgrp_isvalid(grp));
+	assert(pmux_drv_isvalid(drvup));
+
+	val = readl(reg);
+	val &= ~DRVUP_MASK;
+	val |= (drvup << DRVUP_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+
+static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
+{
+	u32 *reg = DRV_REG(grp);
+	u32 val;
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (drvdn == PMUX_DRVDN_NONE)
+		return;
+
+	/* Error check on pad and drvdn */
+	assert(pmux_drvgrp_isvalid(grp));
+	assert(pmux_drv_isvalid(drvdn));
+
+	val = readl(reg);
+	val &= ~DRVDN_MASK;
+	val |= (drvdn << DRVDN_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+
+static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
+{
+	u32 *reg = DRV_REG(grp);
+	u32 val;
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (lpmd == PMUX_LPMD_NONE)
+		return;
+
+	/* Error check pad and lpmd value */
+	assert(pmux_drvgrp_isvalid(grp));
+	assert(pmux_lpmd_isvalid(lpmd));
+
+	val = readl(reg);
+	val &= ~LPMD_MASK;
+	val |= (lpmd << LPMD_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+
+static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
+{
+	u32 *reg = DRV_REG(grp);
+	u32 val;
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (schmt == PMUX_SCHMT_NONE)
+		return;
+
+	/* Error check pad */
+	assert(pmux_drvgrp_isvalid(grp));
+	assert(pmux_schmt_isvalid(schmt));
+
+	val = readl(reg);
+	if (schmt == PMUX_SCHMT_ENABLE)
+		val |= (1 << SCHMT_SHIFT);
+	else
+		val &= ~(1 << SCHMT_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+
+static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
+{
+	u32 *reg = DRV_REG(grp);
+	u32 val;
+
+	/* NONE means unspecified/do not change/use POR value */
+	if (hsm == PMUX_HSM_NONE)
+		return;
+
+	/* Error check pad */
+	assert(pmux_drvgrp_isvalid(grp));
+	assert(pmux_hsm_isvalid(hsm));
+
+	val = readl(reg);
+	if (hsm == PMUX_HSM_ENABLE)
+		val |= (1 << HSM_SHIFT);
+	else
+		val &= ~(1 << HSM_SHIFT);
+	writel(val, reg);
+
+	return;
+}
+
+static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
+{
+	enum pmux_drvgrp grp = config->drvgrp;
+
+	pinmux_set_drvup_slwf(grp, config->slwf);
+	pinmux_set_drvdn_slwr(grp, config->slwr);
+	pinmux_set_drvup(grp, config->drvup);
+	pinmux_set_drvdn(grp, config->drvdn);
+	pinmux_set_lpmd(grp, config->lpmd);
+	pinmux_set_schmt(grp, config->schmt);
+	pinmux_set_hsm(grp, config->hsm);
+}
+
+void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
+				int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		pinmux_config_drvgrp(&config[i]);
+}
+#endif /* TEGRA_PMX_HAS_DRVGRPS */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra-common/sys_info.c b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/sys_info.c
new file mode 100644
index 000000000..de20325ec
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra-common/sys_info.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/ctype.h>
+
+void upstring(char *s)
+{
+	while (*s) {
+		*s = toupper(*s);
+		s++;
+	}
+}
+
+/* Print CPU information */
+int print_cpuinfo(void)
+{
+	char soc_name[10];
+
+	strncpy(soc_name, CONFIG_SYS_SOC, 10);
+	upstring(soc_name);
+	puts(soc_name);
+	puts("\n");
+
+	/* TBD: Add printf of major/minor rev info, stepping, etc. */
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/Makefile
new file mode 100644
index 000000000..d959b575c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/Makefile
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+obj-y	+= clock.o funcmux.o pinmux.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/clock.c b/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/clock.c
new file mode 100644
index 000000000..d5194e11b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/clock.c
@@ -0,0 +1,669 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra114 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
+	CLOCK_TYPE_MCPA,	/* and so on */
+	CLOCK_TYPE_MCPT,
+	CLOCK_TYPE_PCM,
+	CLOCK_TYPE_PCMT,
+	CLOCK_TYPE_PCMT16,
+	CLOCK_TYPE_PDCT,
+	CLOCK_TYPE_ACPT,
+	CLOCK_TYPE_ASPTE,
+	CLOCK_TYPE_PMDACD2T,
+	CLOCK_TYPE_PCST,
+
+	CLOCK_TYPE_COUNT,
+	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
+};
+
+enum {
+	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ *  The extra column in each clock source array is used to store the mask
+ *  bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(SFROM32KHZ),	CLK(PERIPH),	CLK(OSC),
+		CLK(EPCI),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(MEMORY),	CLK(DISPLAY),	CLK(AUDIO),
+		CLK(CGENERAL),	CLK(DISPLAY2),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(SFROM32KHZ),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_28}
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+	/* 0x00 */
+	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_IN,	CLOCK_TYPE_PCM),
+	TYPE(PERIPHC_PWM,	CLOCK_TYPE_PCST),  /* only PWM uses b29:28 */
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC3,	CLOCK_TYPE_PCMT),
+
+	/* 0x08 */
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_I2C5,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_DISP1,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_DISP2,	CLOCK_TYPE_PMDACD2T),
+
+	/* 0x10 */
+	TYPE(PERIPHC_CVE,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_G3D,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_G2D,	CLOCK_TYPE_MCPA),
+
+	/* 0x18 */
+	TYPE(PERIPHC_NDFLASH,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VFIR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_EPP,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MPE,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MIPI,	CLOCK_TYPE_PCMT),	/* MIPI base-band HSI */
+	TYPE(PERIPHC_UART1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART2,	CLOCK_TYPE_PCMT),
+
+	/* 0x20 */
+	TYPE(PERIPHC_HOST1X,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVO,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVDAC,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),
+
+	/* 0x28 */
+	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PCMT),
+
+	/* 0x30 */
+	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2S0,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+
+	/* 0x38h */  /* Jumps to reg offset 0x3B0h */
+	TYPE(PERIPHC_G3D2,      CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MSELECT,   CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_TSENSOR,   CLOCK_TYPE_PCST),	/* s/b PCTS */
+	TYPE(PERIPHC_I2S3,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S4,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2C4,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SBC5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC6,	CLOCK_TYPE_PCMT),
+
+	/* 0x40 */
+	TYPE(PERIPHC_AUDIO,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DAM0,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM1,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM2,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_ACTMON,	CLOCK_TYPE_PCST),	/* MASK 31:30 */
+	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+	/* 0x48 */
+	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_NANDSPEED,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2CSLOW,	CLOCK_TYPE_PCST),	/* MASK 31:30 */
+	TYPE(PERIPHC_SYS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SPEEDO,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+
+	/* 0x50 */
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SATAOOB,	CLOCK_TYPE_PCMT),	/* offset 0x420h */
+	TYPE(PERIPHC_SATA,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_HDA,	CLOCK_TYPE_PCMT),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
+ *	SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+	/* Low word: 31:0 */
+	NONE(CPU),
+	NONE(COP),
+	NONE(TRIGSYS),
+	NONE(RESERVED3),
+	NONE(RTC),
+	NONE(TMR),
+	PERIPHC_UART1,
+	PERIPHC_UART2,	/* and vfir 0x68 */
+
+	/* 8 */
+	NONE(GPIO),
+	PERIPHC_SDMMC2,
+	NONE(SPDIF),		/* 0x08 and 0x0c, unclear which to use */
+	PERIPHC_I2S1,
+	PERIPHC_I2C1,
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC4,
+
+	/* 16 */
+	NONE(RESERVED16),
+	PERIPHC_PWM,
+	PERIPHC_I2S2,
+	PERIPHC_EPP,
+	PERIPHC_VI,
+	PERIPHC_G2D,
+	NONE(USBD),
+	NONE(ISP),
+
+	/* 24 */
+	PERIPHC_G3D,
+	NONE(RESERVED25),
+	PERIPHC_DISP2,
+	PERIPHC_DISP1,
+	PERIPHC_HOST1X,
+	NONE(VCP),
+	PERIPHC_I2S0,
+	NONE(CACHE2),
+
+	/* Middle word: 63:32 */
+	NONE(MEM),
+	NONE(AHBDMA),
+	NONE(APBDMA),
+	NONE(RESERVED35),
+	NONE(RESERVED36),
+	NONE(STAT_MON),
+	NONE(RESERVED38),
+	NONE(RESERVED39),
+
+	/* 40 */
+	NONE(KFUSE),
+	NONE(SBC1),	/* SBC1, 0x34, is this SPI1? */
+	PERIPHC_NOR,
+	NONE(RESERVED43),
+	PERIPHC_SBC2,
+	NONE(RESERVED45),
+	PERIPHC_SBC3,
+	PERIPHC_I2C5,
+
+	/* 48 */
+	NONE(DSI),
+	PERIPHC_TVO,	/* also CVE 0x40 */
+	PERIPHC_MIPI,
+	PERIPHC_HDMI,
+	NONE(CSI),
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_UART3,
+
+	/* 56 */
+	NONE(RESERVED56),
+	PERIPHC_EMC,
+	NONE(USB2),
+	NONE(USB3),
+	PERIPHC_MPE,
+	PERIPHC_VDE,
+	NONE(BSEA),
+	NONE(BSEV),
+
+	/* Upper word 95:64 */
+	PERIPHC_SPEEDO,
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_I2C3,
+	PERIPHC_SBC4,
+	PERIPHC_SDMMC3,
+	NONE(PCIE),
+	PERIPHC_OWR,
+
+	/* 72 */
+	NONE(AFI),
+	PERIPHC_CSITE,
+	NONE(PCIEXCLK),
+	NONE(AVPUCQ),
+	NONE(RESERVED76),
+	NONE(RESERVED77),
+	NONE(RESERVED78),
+	NONE(DTV),
+
+	/* 80 */
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	NONE(DSIB),
+	NONE(RESERVED83),
+	NONE(IRAMA),
+	NONE(IRAMB),
+	NONE(IRAMC),
+	NONE(IRAMD),
+
+	/* 88 */
+	NONE(CRAM2),
+	NONE(RESERVED89),
+	NONE(MDOUBLER),
+	NONE(RESERVED91),
+	NONE(SUSOUT),
+	NONE(RESERVED93),
+	NONE(RESERVED94),
+	NONE(RESERVED95),
+
+	/* V word: 31:0 */
+	NONE(CPUG),
+	NONE(CPULP),
+	PERIPHC_G3D2,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+
+	/* 08 */
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+	PERIPHC_AUDIO,
+	NONE(APBIF),
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+
+	/* 16 */
+	NONE(ATOMICS),
+	NONE(RESERVED17),
+	NONE(RESERVED18),
+	NONE(RESERVED19),
+	NONE(RESERVED20),
+	NONE(RESERVED21),
+	NONE(RESERVED22),
+	PERIPHC_ACTMON,
+
+	/* 24 */
+	NONE(RESERVED24),
+	NONE(RESERVED25),
+	NONE(RESERVED26),
+	NONE(RESERVED27),
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+	NONE(RESERVED30),
+	NONE(RESERVED31),
+
+	/* W word: 31:0 */
+	NONE(HDA2HDMICODEC),
+	NONE(RESERVED1_SATACOLD),
+	NONE(RESERVED2_PCIERX0),
+	NONE(RESERVED3_PCIERX1),
+	NONE(RESERVED4_PCIERX2),
+	NONE(RESERVED5_PCIERX3),
+	NONE(RESERVED6_PCIERX4),
+	NONE(RESERVED7_PCIERX5),
+
+	/* 40 */
+	NONE(CEC),
+	NONE(PCIE2_IOBIST),
+	NONE(EMC_IOBIST),
+	NONE(HDMI_IOBIST),
+	NONE(SATA_IOBIST),
+	NONE(MIPI_IOBIST),
+	NONE(EMC1_IOBIST),
+	NONE(XUSB),
+
+	/* 48 */
+	NONE(CILAB),
+	NONE(CILCD),
+	NONE(CILE),
+	NONE(DSIA_LP),
+	NONE(DSIB_LP),
+	NONE(RESERVED21_ENTROPY),
+	NONE(RESERVED22_W),
+	NONE(RESERVED23_W),
+
+	/* 56 */
+	NONE(RESERVED24_W),
+	NONE(AMX0),
+	NONE(ADX0),
+	NONE(DVFS),
+	NONE(XUSB_SS),
+	NONE(EMC_DLL),
+	NONE(MC1),
+	NONE(EMC1),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that T30/T114 support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+	if (reg & 1)				/* one of the newer freqs */
+		printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+	return reg >> 2;	/* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	enum periphc_internal_id internal_id;
+
+	/* Coresight is a special case */
+	if (periph_id == PERIPH_ID_CSI)
+		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(internal_id != -1);
+	if (internal_id >= PERIPHC_VW_FIRST) {
+		internal_id -= PERIPHC_VW_FIRST;
+		return &clkrst->crc_clk_src_vw[internal_id];
+	} else
+		return &clkrst->crc_clk_src[internal_id];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id	peripheral to start
+ * @param source	PLL id of required parent clock
+ * @param mux_bits	Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+	enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+	enum clock_type_id type;
+	enum periphc_internal_id internal_id;
+	int mux;
+
+	assert(clock_periph_id_isvalid(periph_id));
+
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(periphc_internal_id_isvalid(internal_id));
+
+	type = clock_periph_type[internal_id];
+	assert(clock_type_id_isvalid(type));
+
+	*mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+	if (type == CLOCK_TYPE_PCMT16)
+		*divider_bits = 16;
+	else
+		*divider_bits = 8;
+
+	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+		if (clock_source[type][mux] == parent)
+			return mux;
+
+	/* if we get here, either us or the caller has made a mistake */
+	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+		parent);
+	return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *clk;
+	u32 reg;
+
+	/* Enable/disable the clock to this peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+	else
+		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+	reg = readl(clk);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *reset;
+	u32 reg;
+
+	/* Enable/disable reset to the peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if (periph_id < PERIPH_ID_VW_FIRST)
+		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+	else
+		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+	reg = readl(reset);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id    Clock ID according to tegra114 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+	if (clk_id > PERIPH_ID_COUNT)
+		return PERIPH_ID_NONE;
+
+	switch (clk_id) {
+	case PERIPH_ID_RESERVED3:
+	case PERIPH_ID_RESERVED16:
+	case PERIPH_ID_RESERVED24:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED43:
+	case PERIPH_ID_RESERVED45:
+	case PERIPH_ID_RESERVED56:
+	case PERIPH_ID_RESERVED76:
+	case PERIPH_ID_RESERVED77:
+	case PERIPH_ID_RESERVED78:
+	case PERIPH_ID_RESERVED83:
+	case PERIPH_ID_RESERVED89:
+	case PERIPH_ID_RESERVED91:
+	case PERIPH_ID_RESERVED93:
+	case PERIPH_ID_RESERVED94:
+	case PERIPH_ID_RESERVED95:
+		return PERIPH_ID_NONE;
+	default:
+		return clk_id;
+	}
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+	tegra30_set_up_pllp();
+
+	/*
+	 * PLLC output frequency set to 600Mhz
+	 * PLLD output frequency set to 925Mhz
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+
+	/* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
+	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
+
+	/* PLLC_MISC: Set LOCK_ENABLE */
+	writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
+	udelay(2);
+
+	/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
+	writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+	udelay(2);
+}
+
+void arch_timer_init(void)
+{
+	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+	u32 freq, val;
+
+	freq = clock_get_rate(CLOCK_ID_OSC);
+	debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+	/* ARM CNTFRQ */
+	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+	/* Only T114 has the System Counter regs */
+	debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+	writel(freq, &sysctr->cntfid0);
+
+	val = readl(&sysctr->cntcr);
+	val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+	writel(val, &sysctr->cntcr);
+	debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/funcmux.c b/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/funcmux.c
new file mode 100644
index 000000000..52441c71e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/funcmux.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+	int bad_config = config != FUNCMUX_DEFAULT;
+
+	switch (id) {
+	case PERIPH_ID_UART4:
+		switch (config) {
+		case FUNCMUX_UART4_GMI:
+			pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
+					PMUX_FUNC_UARTD);
+			pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
+					PMUX_FUNC_UARTD);
+			pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
+					PMUX_FUNC_UARTD);
+			pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
+					PMUX_FUNC_UARTD);
+
+			pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
+			pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
+			pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
+			pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
+
+			pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
+			pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
+			pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
+			pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
+			break;
+		}
+		break;
+
+	/* Add other periph IDs here as needed */
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	if (bad_config) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/pinmux.c b/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/pinmux.c
new file mode 100644
index 000000000..3e5acb93c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra114-common/pinmux.c
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+#define PIN(pin, f0, f1, f2, f3)	\
+	{				\
+		.funcs = {		\
+			PMUX_FUNC_##f0,	\
+			PMUX_FUNC_##f1,	\
+			PMUX_FUNC_##f2,	\
+			PMUX_FUNC_##f3,	\
+		},			\
+	}
+
+#define PIN_RESERVED {}
+
+static const struct pmux_pingrp_desc tegra114_pingroups[] = {
+	/*  pin,                    f0,         f1,       f2,           f3 */
+	/* Offset 0x3000 */
+	PIN(ULPI_DATA0_PO1,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA1_PO2,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA2_PO3,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA3_PO4,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA4_PO5,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA5_PO6,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA6_PO7,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA7_PO0,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_CLK_PY0,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(ULPI_DIR_PY1,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(ULPI_NXT_PY2,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(ULPI_STP_PY3,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(DAP3_FS_PP0,            I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+	PIN(DAP3_DIN_PP1,           I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+	PIN(DAP3_DOUT_PP2,          I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+	PIN(DAP3_SCLK_PP3,          I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+	PIN(PV0,                    USB,        RSVD2,    RSVD3,        RSVD4),
+	PIN(PV1,                    RSVD1,      RSVD2,    RSVD3,        RSVD4),
+	PIN(SDMMC1_CLK_PZ0,         SDMMC1,     CLK12,    RSVD3,        RSVD4),
+	PIN(SDMMC1_CMD_PZ1,         SDMMC1,     SPDIF,    SPI4,         UARTA),
+	PIN(SDMMC1_DAT3_PY4,        SDMMC1,     SPDIF,    SPI4,         UARTA),
+	PIN(SDMMC1_DAT2_PY5,        SDMMC1,     PWM0,     SPI4,         UARTA),
+	PIN(SDMMC1_DAT1_PY6,        SDMMC1,     PWM1,     SPI4,         UARTA),
+	PIN(SDMMC1_DAT0_PY7,        SDMMC1,     RSVD2,    SPI4,         UARTA),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3068 */
+	PIN(CLK2_OUT_PW5,           EXTPERIPH2, RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK2_REQ_PCC5,          DAP,        RSVD2,    RSVD3,        RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3110 */
+	PIN(HDMI_INT_PN7,           RSVD1,      RSVD2,    RSVD3,        RSVD4),
+	PIN(DDC_SCL_PV4,            I2C4,       RSVD2,    RSVD3,        RSVD4),
+	PIN(DDC_SDA_PV5,            I2C4,       RSVD2,    RSVD3,        RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3164 */
+	PIN(UART2_RXD_PC3,          IRDA,       SPDIF,    UARTA,        SPI4),
+	PIN(UART2_TXD_PC2,          IRDA,       SPDIF,    UARTA,        SPI4),
+	PIN(UART2_RTS_N_PJ6,        UARTA,      UARTB,    RSVD3,        SPI4),
+	PIN(UART2_CTS_N_PJ5,        UARTA,      UARTB,    RSVD3,        SPI4),
+	PIN(UART3_TXD_PW6,          UARTC,      RSVD2,    RSVD3,        SPI4),
+	PIN(UART3_RXD_PW7,          UARTC,      RSVD2,    RSVD3,        SPI4),
+	PIN(UART3_CTS_N_PA1,        UARTC,      SDMMC1,   DTV,          SPI4),
+	PIN(UART3_RTS_N_PC0,        UARTC,      PWM0,     DTV,          DISPLAYA),
+	PIN(PU0,                    OWR,        UARTA,    RSVD3,        RSVD4),
+	PIN(PU1,                    RSVD1,      UARTA,    RSVD3,        RSVD4),
+	PIN(PU2,                    RSVD1,      UARTA,    RSVD3,        RSVD4),
+	PIN(PU3,                    PWM0,       UARTA,    DISPLAYA,     DISPLAYB),
+	PIN(PU4,                    PWM1,       UARTA,    DISPLAYA,     DISPLAYB),
+	PIN(PU5,                    PWM2,       UARTA,    DISPLAYA,     DISPLAYB),
+	PIN(PU6,                    PWM3,       UARTA,    USB,          DISPLAYB),
+	PIN(GEN1_I2C_SDA_PC5,       I2C1,       RSVD2,    RSVD3,        RSVD4),
+	PIN(GEN1_I2C_SCL_PC4,       I2C1,       RSVD2,    RSVD3,        RSVD4),
+	PIN(DAP4_FS_PP4,            I2S3,       RSVD2,    DTV,          RSVD4),
+	PIN(DAP4_DIN_PP5,           I2S3,       RSVD2,    RSVD3,        RSVD4),
+	PIN(DAP4_DOUT_PP6,          I2S3,       RSVD2,    DTV,          RSVD4),
+	PIN(DAP4_SCLK_PP7,          I2S3,       RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK3_OUT_PEE0,          EXTPERIPH3, RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK3_REQ_PEE1,          DEV3,       RSVD2,    RSVD3,        RSVD4),
+	PIN(GMI_WP_N_PC7,           RSVD1,      NAND,     GMI,          GMI_ALT),
+	PIN(GMI_IORDY_PI5,          SDMMC2,     RSVD2,    GMI,          TRACE),
+	PIN(GMI_WAIT_PI7,           SPI4,       NAND,     GMI,          DTV),
+	PIN(GMI_ADV_N_PK0,          RSVD1,      NAND,     GMI,          TRACE),
+	PIN(GMI_CLK_PK1,            SDMMC2,     NAND,     GMI,          TRACE),
+	PIN(GMI_CS0_N_PJ0,          RSVD1,      NAND,     GMI,          USB),
+	PIN(GMI_CS1_N_PJ2,          RSVD1,      NAND,     GMI,          SOC),
+	PIN(GMI_CS2_N_PK3,          SDMMC2,     NAND,     GMI,          TRACE),
+	PIN(GMI_CS3_N_PK4,          SDMMC2,     NAND,     GMI,          GMI_ALT),
+	PIN(GMI_CS4_N_PK2,          USB,        NAND,     GMI,          TRACE),
+	PIN(GMI_CS6_N_PI3,          NAND,       NAND_ALT, GMI,          SPI4),
+	PIN(GMI_CS7_N_PI6,          NAND,       NAND_ALT, GMI,          SDMMC2),
+	PIN(GMI_AD0_PG0,            RSVD1,      NAND,     GMI,          RSVD4),
+	PIN(GMI_AD1_PG1,            RSVD1,      NAND,     GMI,          RSVD4),
+	PIN(GMI_AD2_PG2,            RSVD1,      NAND,     GMI,          RSVD4),
+	PIN(GMI_AD3_PG3,            RSVD1,      NAND,     GMI,          RSVD4),
+	PIN(GMI_AD4_PG4,            RSVD1,      NAND,     GMI,          RSVD4),
+	PIN(GMI_AD5_PG5,            RSVD1,      NAND,     GMI,          SPI4),
+	PIN(GMI_AD6_PG6,            RSVD1,      NAND,     GMI,          SPI4),
+	PIN(GMI_AD7_PG7,            RSVD1,      NAND,     GMI,          SPI4),
+	PIN(GMI_AD8_PH0,            PWM0,       NAND,     GMI,          DTV),
+	PIN(GMI_AD9_PH1,            PWM1,       NAND,     GMI,          CLDVFS),
+	PIN(GMI_AD10_PH2,           PWM2,       NAND,     GMI,          CLDVFS),
+	PIN(GMI_AD11_PH3,           PWM3,       NAND,     GMI,          USB),
+	PIN(GMI_AD12_PH4,           SDMMC2,     NAND,     GMI,          RSVD4),
+	PIN(GMI_AD13_PH5,           SDMMC2,     NAND,     GMI,          RSVD4),
+	PIN(GMI_AD14_PH6,           SDMMC2,     NAND,     GMI,          DTV),
+	PIN(GMI_AD15_PH7,           SDMMC2,     NAND,     GMI,          DTV),
+	PIN(GMI_A16_PJ7,            UARTD,      TRACE,    GMI,          GMI_ALT),
+	PIN(GMI_A17_PB0,            UARTD,      RSVD2,    GMI,          TRACE),
+	PIN(GMI_A18_PB1,            UARTD,      RSVD2,    GMI,          TRACE),
+	PIN(GMI_A19_PK7,            UARTD,      SPI4,     GMI,          TRACE),
+	PIN(GMI_WR_N_PI0,           RSVD1,      NAND,     GMI,          SPI4),
+	PIN(GMI_OE_N_PI1,           RSVD1,      NAND,     GMI,          SOC),
+	PIN(GMI_DQS_P_PJ3,          SDMMC2,     NAND,     GMI,          TRACE),
+	PIN(GMI_RST_N_PI4,          NAND,       NAND_ALT, GMI,          RSVD4),
+	PIN(GEN2_I2C_SCL_PT5,       I2C2,       RSVD2,    GMI,          RSVD4),
+	PIN(GEN2_I2C_SDA_PT6,       I2C2,       RSVD2,    GMI,          RSVD4),
+	PIN(SDMMC4_CLK_PCC4,        SDMMC4,     RSVD2,    GMI,          RSVD4),
+	PIN(SDMMC4_CMD_PT7,         SDMMC4,     RSVD2,    GMI,          RSVD4),
+	PIN(SDMMC4_DAT0_PAA0,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT1_PAA1,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT2_PAA2,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT3_PAA3,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT4_PAA4,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT5_PAA5,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT6_PAA6,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT7_PAA7,       SDMMC4,     RSVD2,    GMI,          RSVD4),
+	PIN_RESERVED,
+	/* Offset 0x3284 */
+	PIN(CAM_MCLK_PCC0,          VI,         VI_ALT1,  VI_ALT3,      RSVD4),
+	PIN(PCC1,                   I2S4,       RSVD2,    RSVD3,        RSVD4),
+	PIN(PBB0,                   I2S4,       VI,       VI_ALT1,      VI_ALT3),
+	PIN(CAM_I2C_SCL_PBB1,       VGP1,       I2C3,     RSVD3,        RSVD4),
+	PIN(CAM_I2C_SDA_PBB2,       VGP2,       I2C3,     RSVD3,        RSVD4),
+	PIN(PBB3,                   VGP3,       DISPLAYA, DISPLAYB,     RSVD4),
+	PIN(PBB4,                   VGP4,       DISPLAYA, DISPLAYB,     RSVD4),
+	PIN(PBB5,                   VGP5,       DISPLAYA, DISPLAYB,     RSVD4),
+	PIN(PBB6,                   VGP6,       DISPLAYA, DISPLAYB,     RSVD4),
+	PIN(PBB7,                   I2S4,       RSVD2,    RSVD3,        RSVD4),
+	PIN(PCC2,                   I2S4,       RSVD2,    RSVD3,        RSVD4),
+	PIN(JTAG_RTCK,              RTCK,       RSVD2,    RSVD3,        RSVD4),
+	PIN(PWR_I2C_SCL_PZ6,        I2CPWR,     RSVD2,    RSVD3,        RSVD4),
+	PIN(PWR_I2C_SDA_PZ7,        I2CPWR,     RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW0_PR0,            KBC,        RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW1_PR1,            KBC,        RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW2_PR2,            KBC,        RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW3_PR3,            KBC,        DISPLAYA, RSVD3,        DISPLAYB),
+	PIN(KB_ROW4_PR4,            KBC,        DISPLAYA, SPI2,         DISPLAYB),
+	PIN(KB_ROW5_PR5,            KBC,        DISPLAYA, SPI2,         DISPLAYB),
+	PIN(KB_ROW6_PR6,            KBC,        DISPLAYA, DISPLAYA_ALT, DISPLAYB),
+	PIN(KB_ROW7_PR7,            KBC,        RSVD2,    CLDVFS,       UARTA),
+	PIN(KB_ROW8_PS0,            KBC,        RSVD2,    CLDVFS,       UARTA),
+	PIN(KB_ROW9_PS1,            KBC,        RSVD2,    RSVD3,        UARTA),
+	PIN(KB_ROW10_PS2,           KBC,        RSVD2,    RSVD3,        UARTA),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x32fc */
+	PIN(KB_COL0_PQ0,            KBC,        USB,      SPI2,         EMC_DLL),
+	PIN(KB_COL1_PQ1,            KBC,        RSVD2,    SPI2,         EMC_DLL),
+	PIN(KB_COL2_PQ2,            KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(KB_COL3_PQ3,            KBC,        DISPLAYA, PWM2,         UARTA),
+	PIN(KB_COL4_PQ4,            KBC,        OWR,      SDMMC3,       UARTA),
+	PIN(KB_COL5_PQ5,            KBC,        RSVD2,    SDMMC1,       RSVD4),
+	PIN(KB_COL6_PQ6,            KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(KB_COL7_PQ7,            KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(CLK_32K_OUT_PA0,        BLINK,      SOC,      RSVD3,        RSVD4),
+	PIN(SYS_CLK_REQ_PZ5,        SYSCLK,     RSVD2,    RSVD3,        RSVD4),
+	PIN(CORE_PWR_REQ,           PWRON,      RSVD2,    RSVD3,        RSVD4),
+	PIN(CPU_PWR_REQ,            CPU,        RSVD2,    RSVD3,        RSVD4),
+	PIN(PWR_INT_N,              PMI,        RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK_32K_IN,             CLK,        RSVD2,    RSVD3,        RSVD4),
+	PIN(OWR,                    OWR,        RSVD2,    RSVD3,        RSVD4),
+	PIN(DAP1_FS_PN0,            I2S0,       HDA,      GMI,          RSVD4),
+	PIN(DAP1_DIN_PN1,           I2S0,       HDA,      GMI,          RSVD4),
+	PIN(DAP1_DOUT_PN2,          I2S0,       HDA,      GMI,          RSVD4),
+	PIN(DAP1_SCLK_PN3,          I2S0,       HDA,      GMI,          RSVD4),
+	PIN(CLK1_REQ_PEE2,          DAP,        DAP1,     RSVD3,        RSVD4),
+	PIN(CLK1_OUT_PW4,           EXTPERIPH1, DAP2,     RSVD3,        RSVD4),
+	PIN(SPDIF_IN_PK6,           SPDIF,      USB,      RSVD3,        RSVD4),
+	PIN(SPDIF_OUT_PK5,          SPDIF,      RSVD2,    RSVD3,        RSVD4),
+	PIN(DAP2_FS_PA2,            I2S1,       HDA,      RSVD3,        RSVD4),
+	PIN(DAP2_DIN_PA4,           I2S1,       HDA,      RSVD3,        RSVD4),
+	PIN(DAP2_DOUT_PA5,          I2S1,       HDA,      RSVD3,        RSVD4),
+	PIN(DAP2_SCLK_PA3,          I2S1,       HDA,      RSVD3,        RSVD4),
+	PIN(DVFS_PWM_PX0,           SPI6,       CLDVFS,   RSVD3,        RSVD4),
+	PIN(GPIO_X1_AUD_PX1,        SPI6,       RSVD2,    RSVD3,        RSVD4),
+	PIN(GPIO_X3_AUD_PX3,        SPI6,       SPI1,     RSVD3,        RSVD4),
+	PIN(DVFS_CLK_PX2,           SPI6,       CLDVFS,   RSVD3,        RSVD4),
+	PIN(GPIO_X4_AUD_PX4,        RSVD1,      SPI1,     SPI2,         DAP2),
+	PIN(GPIO_X5_AUD_PX5,        RSVD1,      SPI1,     SPI2,         RSVD4),
+	PIN(GPIO_X6_AUD_PX6,        SPI6,       SPI1,     SPI2,         RSVD4),
+	PIN(GPIO_X7_AUD_PX7,        RSVD1,      SPI1,     SPI2,         RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3390 */
+	PIN(SDMMC3_CLK_PA6,         SDMMC3,     RSVD2,    RSVD3,        SPI3),
+	PIN(SDMMC3_CMD_PA7,         SDMMC3,     PWM3,     UARTA,        SPI3),
+	PIN(SDMMC3_DAT0_PB7,        SDMMC3,     RSVD2,    RSVD3,        SPI3),
+	PIN(SDMMC3_DAT1_PB6,        SDMMC3,     PWM2,     UARTA,        SPI3),
+	PIN(SDMMC3_DAT2_PB5,        SDMMC3,     PWM1,     DISPLAYA,     SPI3),
+	PIN(SDMMC3_DAT3_PB4,        SDMMC3,     PWM0,     DISPLAYB,     SPI3),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x33e0 */
+	PIN(HDMI_CEC_PEE3,          CEC,        SDMMC3,   RSVD3,        SOC),
+	PIN(SDMMC1_WP_N_PV3,        SDMMC1,     CLK12,    SPI4,         UARTA),
+	PIN(SDMMC3_CD_N_PV2,        SDMMC3,     OWR,      RSVD3,        RSVD4),
+	PIN(GPIO_W2_AUD_PW2,        SPI6,       RSVD2,    SPI2,         I2C1),
+	PIN(GPIO_W3_AUD_PW3,        SPI6,       SPI1,     SPI2,         I2C1),
+	PIN(USB_VBUS_EN0_PN4,       USB,        RSVD2,    RSVD3,        RSVD4),
+	PIN(USB_VBUS_EN1_PN5,       USB,        RSVD2,    RSVD3,        RSVD4),
+	PIN(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,     RSVD2,    RSVD3,        RSVD4),
+	PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,     RSVD2,    RSVD3,        RSVD4),
+	PIN(GMI_CLK_LB,             SDMMC2,     NAND,     GMI,          RSVD4),
+	PIN(RESET_OUT_N,            RSVD1,      RSVD2,    RSVD3,        RESET_OUT_N),
+};
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups;
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/Makefile
new file mode 100644
index 000000000..ff77992b3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= clock.o
+obj-y	+= funcmux.o
+obj-y	+= pinmux.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/clock.c b/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/clock.c
new file mode 100644
index 000000000..739436326
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/clock.c
@@ -0,0 +1,826 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra124 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
+	CLOCK_TYPE_MCPA,	/* and so on */
+	CLOCK_TYPE_MCPT,
+	CLOCK_TYPE_PCM,
+	CLOCK_TYPE_PCMT,
+	CLOCK_TYPE_PDCT,
+	CLOCK_TYPE_ACPT,
+	CLOCK_TYPE_ASPTE,
+	CLOCK_TYPE_PMDACD2T,
+	CLOCK_TYPE_PCST,
+
+	CLOCK_TYPE_PC2CC3M,
+	CLOCK_TYPE_PC2CC3S_T,
+	CLOCK_TYPE_PC2CC3M_T,
+	CLOCK_TYPE_PC2CC3M_T16,	/* PC2CC3M_T, but w/16-bit divisor (I2C) */
+	CLOCK_TYPE_MC2CC3P_A,
+	CLOCK_TYPE_M,
+	CLOCK_TYPE_MCPTM2C2C3,
+	CLOCK_TYPE_PC2CC3T_S,
+	CLOCK_TYPE_AC2CC3P_TS2,
+
+	CLOCK_TYPE_COUNT,
+	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
+};
+
+enum {
+	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ *  The extra column in each clock source array is used to store the mask
+ *  bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(SFROM32KHZ),	CLK(PERIPH),	CLK(OSC),
+		CLK(EPCI),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(MEMORY),	CLK(DISPLAY),	CLK(AUDIO),
+		CLK(CGENERAL),	CLK(DISPLAY2),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(SFROM32KHZ),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_28},
+
+	/* Additional clock types on Tegra114+ */
+	/* CLOCK_TYPE_PC2CC3M */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(MEMORY),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3S_T */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(SFROM32KHZ), CLK(NONE),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3M_T */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(MEMORY),	CLK(NONE),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(MEMORY),	CLK(NONE),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_MC2CC3P_A */
+	{ CLK(MEMORY),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(PERIPH),	CLK(NONE),	CLK(AUDIO),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_M */
+	{ CLK(MEMORY),		CLK(NONE),	CLK(NONE),	CLK(NONE),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	/* CLOCK_TYPE_MCPTM2C2C3 */
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(MEMORY2),	CLK(CGENERAL2),	CLK(CGENERAL3),	CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_PC2CC3T_S */
+	{ CLK(PERIPH),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(OSC),	CLK(NONE),	CLK(SFROM32KHZ), CLK(NONE),
+		MASK_BITS_31_29},
+	/* CLOCK_TYPE_AC2CC3P_TS2 */
+	{ CLK(AUDIO),	CLK(CGENERAL2),	CLK(CGENERAL),	CLK(CGENERAL3),
+		CLK(PERIPH),	CLK(NONE),	CLK(OSC),	CLK(SRC2),
+		MASK_BITS_31_29},
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+	/* 0x00 */
+	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_IN,	CLOCK_TYPE_PC2CC3M),
+	TYPE(PERIPHC_PWM,	CLOCK_TYPE_PC2CC3S_T),
+	TYPE(PERIPHC_05h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC2,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_SBC3,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x08 */
+	TYPE(PERIPHC_08h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_I2C5,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_0bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_0ch,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC1,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_DISP1,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_DISP2,	CLOCK_TYPE_PMDACD2T),
+
+	/* 0x10 */
+	TYPE(PERIPHC_10h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_11h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_13h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC1,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_16h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_17h,	CLOCK_TYPE_NONE),
+
+	/* 0x18 */
+	TYPE(PERIPHC_18h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_VFIR,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_1Bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_1Ch,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_HSI,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_UART1,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_UART2,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x20 */
+	TYPE(PERIPHC_HOST1X,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_21h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_22h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_24h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_25h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPTM2C2C3),
+
+	/* 0x28 */
+	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_29h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI_SENSOR,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_2bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_2ch,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC4,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x30 */
+	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_I2S0,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_DTV,	CLOCK_TYPE_NONE),
+
+	/* 0x38 */
+	TYPE(PERIPHC_38h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_39h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_3ah,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_3bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_MSENC,	CLOCK_TYPE_MC2CC3P_A),
+	TYPE(PERIPHC_TSEC,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_3eh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_OSC,	CLOCK_TYPE_NONE),
+
+	/* 0x40 */
+	TYPE(PERIPHC_40h,	CLOCK_TYPE_NONE),	/* start with 0x3b0 */
+	TYPE(PERIPHC_MSELECT,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_TSENSOR,	CLOCK_TYPE_PC2CC3T_S),
+	TYPE(PERIPHC_I2S3,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S4,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2C4,	CLOCK_TYPE_PC2CC3M_T16),
+	TYPE(PERIPHC_SBC5,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_SBC6,	CLOCK_TYPE_PC2CC3M_T),
+
+	/* 0x48 */
+	TYPE(PERIPHC_AUDIO,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_49h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DAM0,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_DAM1,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_DAM2,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_ACTMON,	CLOCK_TYPE_PC2CC3S_T),
+	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+	/* 0x50 */
+	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_52h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2CSLOW,	CLOCK_TYPE_PC2CC3S_T),
+	TYPE(PERIPHC_SYS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_55h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_56h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_57h,	CLOCK_TYPE_NONE),
+
+	/* 0x58 */
+	TYPE(PERIPHC_58h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_59h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_5ah,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_5bh,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SATAOOB,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SATA,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_HDA,	CLOCK_TYPE_PC2CC3M_T),
+	TYPE(PERIPHC_5fh,	CLOCK_TYPE_NONE),
+
+	/* 0x60 */
+	TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_FS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_XUSB_SS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CILAB,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CILCD,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CILE,	CLOCK_TYPE_NONE),
+
+	/* 0x68 */
+	TYPE(PERIPHC_DSIA_LP,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DSIB_LP,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_ENTROPY,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DVFS_REF,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DVFS_SOC,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_ADX0,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_AMX0,	CLOCK_TYPE_NONE),
+
+	/* 0x70 */
+	TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SOC_THERM,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_72h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_73h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_74h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_75h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C6,	CLOCK_TYPE_PC2CC3M_T16),
+
+	/* 0x78 */
+	TYPE(PERIPHC_78h,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_EMC_DLL,	CLOCK_TYPE_MCPTM2C2C3),
+	TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_CLK72MHZ,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_ADX1,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_AMX1,	CLOCK_TYPE_AC2CC3P_TS2),
+	TYPE(PERIPHC_VIC,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_7Fh,	CLOCK_TYPE_NONE),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
+ *	SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+	/* Low word: 31:0 */
+	NONE(CPU),
+	NONE(COP),
+	NONE(TRIGSYS),
+	NONE(ISPB),
+	NONE(RESERVED4),
+	NONE(TMR),
+	PERIPHC_UART1,
+	PERIPHC_UART2,	/* and vfir 0x68 */
+
+	/* 8 */
+	NONE(GPIO),
+	PERIPHC_SDMMC2,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_I2S1,
+	PERIPHC_I2C1,
+	NONE(RESERVED13),
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC4,
+
+	/* 16 */
+	NONE(TCW),
+	PERIPHC_PWM,
+	PERIPHC_I2S2,
+	NONE(RESERVED19),
+	PERIPHC_VI,
+	NONE(RESERVED21),
+	NONE(USBD),
+	NONE(ISP),
+
+	/* 24 */
+	NONE(RESERVED24),
+	NONE(RESERVED25),
+	PERIPHC_DISP2,
+	PERIPHC_DISP1,
+	PERIPHC_HOST1X,
+	NONE(VCP),
+	PERIPHC_I2S0,
+	NONE(CACHE2),
+
+	/* Middle word: 63:32 */
+	NONE(MEM),
+	NONE(AHBDMA),
+	NONE(APBDMA),
+	NONE(RESERVED35),
+	NONE(RESERVED36),
+	NONE(STAT_MON),
+	NONE(RESERVED38),
+	NONE(FUSE),
+
+	/* 40 */
+	NONE(KFUSE),
+	PERIPHC_SBC1,		/* SBCx = SPIx */
+	PERIPHC_NOR,
+	NONE(RESERVED43),
+	PERIPHC_SBC2,
+	NONE(XIO),
+	PERIPHC_SBC3,
+	PERIPHC_I2C5,
+
+	/* 48 */
+	NONE(DSI),
+	NONE(RESERVED49),
+	PERIPHC_HSI,
+	PERIPHC_HDMI,
+	NONE(CSI),
+	NONE(RESERVED53),
+	PERIPHC_I2C2,
+	PERIPHC_UART3,
+
+	/* 56 */
+	NONE(MIPI_CAL),
+	PERIPHC_EMC,
+	NONE(USB2),
+	NONE(USB3),
+	NONE(RESERVED60),
+	PERIPHC_VDE,
+	NONE(BSEA),
+	NONE(BSEV),
+
+	/* Upper word 95:64 */
+	NONE(RESERVED64),
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_I2C3,
+	PERIPHC_SBC4,
+	PERIPHC_SDMMC3,
+	NONE(PCIE),
+	PERIPHC_OWR,
+
+	/* 72 */
+	NONE(AFI),
+	PERIPHC_CSITE,
+	NONE(PCIEXCLK),
+	NONE(AVPUCQ),
+	NONE(LA),
+	NONE(TRACECLKIN),
+	NONE(SOC_THERM),
+	NONE(DTV),
+
+	/* 80 */
+	NONE(RESERVED80),
+	PERIPHC_I2CSLOW,
+	NONE(DSIB),
+	PERIPHC_TSEC,
+	NONE(RESERVED84),
+	NONE(RESERVED85),
+	NONE(RESERVED86),
+	NONE(EMUCIF),
+
+	/* 88 */
+	NONE(RESERVED88),
+	NONE(XUSB_HOST),
+	NONE(RESERVED90),
+	PERIPHC_MSENC,
+	NONE(RESERVED92),
+	NONE(RESERVED93),
+	NONE(RESERVED94),
+	NONE(XUSB_DEV),
+
+	/* V word: 31:0 */
+	NONE(CPUG),
+	NONE(CPULP),
+	NONE(V_RESERVED2),
+	PERIPHC_MSELECT,
+	NONE(V_RESERVED4),
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+
+	/* 104 */
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+	PERIPHC_AUDIO,
+	NONE(APBIF),
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+
+	/* 112 */
+	NONE(ATOMICS),
+	NONE(V_RESERVED17),
+	NONE(V_RESERVED18),
+	NONE(V_RESERVED19),
+	NONE(V_RESERVED20),
+	NONE(V_RESERVED21),
+	NONE(V_RESERVED22),
+	PERIPHC_ACTMON,
+
+	/* 120 */
+	NONE(EXTPERIPH1),
+	NONE(EXTPERIPH2),
+	NONE(EXTPERIPH3),
+	NONE(OOB),
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+	NONE(TZRAM),
+	NONE(SE),
+
+	/* W word: 31:0 */
+	NONE(HDA2HDMICODEC),
+	NONE(SATACOLD),
+	NONE(W_RESERVED2),
+	NONE(W_RESERVED3),
+	NONE(W_RESERVED4),
+	NONE(W_RESERVED5),
+	NONE(W_RESERVED6),
+	NONE(W_RESERVED7),
+
+	/* 136 */
+	NONE(CEC),
+	NONE(W_RESERVED9),
+	NONE(W_RESERVED10),
+	NONE(W_RESERVED11),
+	NONE(W_RESERVED12),
+	NONE(W_RESERVED13),
+	NONE(XUSB_PADCTL),
+	NONE(W_RESERVED15),
+
+	/* 144 */
+	NONE(W_RESERVED16),
+	NONE(W_RESERVED17),
+	NONE(W_RESERVED18),
+	NONE(W_RESERVED19),
+	NONE(W_RESERVED20),
+	NONE(ENTROPY),
+	NONE(DDS),
+	NONE(W_RESERVED23),
+
+	/* 152 */
+	NONE(DP2),
+	NONE(AMX0),
+	NONE(ADX0),
+	NONE(DVFS),
+	NONE(XUSB_SS),
+	NONE(W_RESERVED29),
+	NONE(W_RESERVED30),
+	NONE(W_RESERVED31),
+
+	/* X word: 31:0 */
+	NONE(SPARE),
+	NONE(X_RESERVED1),
+	NONE(X_RESERVED2),
+	NONE(X_RESERVED3),
+	NONE(CAM_MCLK),
+	NONE(CAM_MCLK2),
+	PERIPHC_I2C6,
+	NONE(X_RESERVED7),
+
+	/* 168 */
+	NONE(X_RESERVED8),
+	NONE(X_RESERVED9),
+	NONE(X_RESERVED10),
+	NONE(VIM2_CLK),
+	NONE(X_RESERVED12),
+	NONE(X_RESERVED13),
+	NONE(EMC_DLL),
+	NONE(X_RESERVED15),
+
+	/* 176 */
+	NONE(HDMI_AUDIO),
+	NONE(CLK72MHZ),
+	NONE(VIC),
+	NONE(X_RESERVED19),
+	NONE(ADX1),
+	NONE(DPAUX),
+	NONE(SOR0),
+	NONE(X_RESERVED23),
+
+	/* 184 */
+	NONE(GPU),
+	NONE(AMX1),
+	NONE(X_RESERVED26),
+	NONE(X_RESERVED27),
+	NONE(X_RESERVED28),
+	NONE(X_RESERVED29),
+	NONE(X_RESERVED30),
+	NONE(X_RESERVED31),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that Tegra30+ support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+	if (reg & 1)				/* one of the newer freqs */
+		printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+	return reg >> 2;	/* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	enum periphc_internal_id internal_id;
+
+	/* Coresight is a special case */
+	if (periph_id == PERIPH_ID_CSI)
+		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(internal_id != -1);
+	if (internal_id >= PERIPHC_VW_FIRST) {
+		internal_id -= PERIPHC_VW_FIRST;
+		return &clkrst->crc_clk_src_vw[internal_id];
+	} else {
+		return &clkrst->crc_clk_src[internal_id];
+	}
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id	peripheral to start
+ * @param source	PLL id of required parent clock
+ * @param mux_bits	Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+	enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+	enum clock_type_id type;
+	enum periphc_internal_id internal_id;
+	int mux;
+
+	assert(clock_periph_id_isvalid(periph_id));
+
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(periphc_internal_id_isvalid(internal_id));
+
+	type = clock_periph_type[internal_id];
+	assert(clock_type_id_isvalid(type));
+
+	*mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+	if (type == CLOCK_TYPE_PC2CC3M_T16)
+		*divider_bits = 16;
+	else
+		*divider_bits = 8;
+
+	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+		if (clock_source[type][mux] == parent)
+			return mux;
+
+	/* if we get here, either us or the caller has made a mistake */
+	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+	       parent);
+	return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *clk;
+	u32 reg;
+
+	/* Enable/disable the clock to this peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+	else
+		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+	reg = readl(clk);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *reset;
+	u32 reg;
+
+	/* Enable/disable reset to the peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if (periph_id < PERIPH_ID_VW_FIRST)
+		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+	else
+		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+	reg = readl(reset);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id    Clock ID according to tegra124 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+	if (clk_id > PERIPH_ID_COUNT)
+		return PERIPH_ID_NONE;
+
+	switch (clk_id) {
+	case PERIPH_ID_RESERVED4:
+	case PERIPH_ID_RESERVED25:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED36:
+	case PERIPH_ID_RESERVED38:
+	case PERIPH_ID_RESERVED43:
+	case PERIPH_ID_RESERVED49:
+	case PERIPH_ID_RESERVED53:
+	case PERIPH_ID_RESERVED64:
+	case PERIPH_ID_RESERVED84:
+	case PERIPH_ID_RESERVED85:
+	case PERIPH_ID_RESERVED86:
+	case PERIPH_ID_RESERVED88:
+	case PERIPH_ID_RESERVED90:
+	case PERIPH_ID_RESERVED92:
+	case PERIPH_ID_RESERVED93:
+	case PERIPH_ID_RESERVED94:
+	case PERIPH_ID_V_RESERVED2:
+	case PERIPH_ID_V_RESERVED4:
+	case PERIPH_ID_V_RESERVED17:
+	case PERIPH_ID_V_RESERVED18:
+	case PERIPH_ID_V_RESERVED19:
+	case PERIPH_ID_V_RESERVED20:
+	case PERIPH_ID_V_RESERVED21:
+	case PERIPH_ID_V_RESERVED22:
+	case PERIPH_ID_W_RESERVED2:
+	case PERIPH_ID_W_RESERVED3:
+	case PERIPH_ID_W_RESERVED4:
+	case PERIPH_ID_W_RESERVED5:
+	case PERIPH_ID_W_RESERVED6:
+	case PERIPH_ID_W_RESERVED7:
+	case PERIPH_ID_W_RESERVED9:
+	case PERIPH_ID_W_RESERVED10:
+	case PERIPH_ID_W_RESERVED11:
+	case PERIPH_ID_W_RESERVED12:
+	case PERIPH_ID_W_RESERVED13:
+	case PERIPH_ID_W_RESERVED15:
+	case PERIPH_ID_W_RESERVED16:
+	case PERIPH_ID_W_RESERVED17:
+	case PERIPH_ID_W_RESERVED18:
+	case PERIPH_ID_W_RESERVED19:
+	case PERIPH_ID_W_RESERVED20:
+	case PERIPH_ID_W_RESERVED23:
+	case PERIPH_ID_W_RESERVED29:
+	case PERIPH_ID_W_RESERVED30:
+	case PERIPH_ID_W_RESERVED31:
+		return PERIPH_ID_NONE;
+	default:
+		return clk_id;
+	}
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+	tegra30_set_up_pllp();
+
+	/*
+	 * PLLC output frequency set to 600Mhz
+	 * PLLD output frequency set to 925Mhz
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+
+	/* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
+	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
+
+	/* PLLC_MISC: Set LOCK_ENABLE */
+	writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
+	udelay(2);
+
+	/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
+	writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+	udelay(2);
+}
+
+void arch_timer_init(void)
+{
+	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+	u32 freq, val;
+
+	freq = clock_get_rate(CLOCK_ID_OSC);
+	debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+	/* ARM CNTFRQ */
+	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+	/* Only Tegra114+ has the System Counter regs */
+	debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+	writel(freq, &sysctr->cntfid0);
+
+	val = readl(&sysctr->cntcr);
+	val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+	writel(val, &sysctr->cntcr);
+	debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/funcmux.c b/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/funcmux.c
new file mode 100644
index 000000000..cced787e6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/funcmux.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+	int bad_config = config != FUNCMUX_DEFAULT;
+
+	switch (id) {
+	case PERIPH_ID_UART4:
+		switch (config) {
+		case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
+			pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
+			pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
+			pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
+			pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
+
+			pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
+			pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
+			pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
+			pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
+
+			pinmux_tristate_disable(PMUX_PINGRP_PJ7);
+			pinmux_tristate_disable(PMUX_PINGRP_PB0);
+			pinmux_tristate_disable(PMUX_PINGRP_PB1);
+			pinmux_tristate_disable(PMUX_PINGRP_PK7);
+			break;
+		}
+		break;
+
+	case PERIPH_ID_UART1:
+		switch (config) {
+		case FUNCMUX_UART1_KBC:
+			pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
+					PMUX_FUNC_UARTA);
+			pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
+					PMUX_FUNC_UARTA);
+
+			pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
+			pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
+
+			pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
+			pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
+			break;
+		}
+		break;
+
+	/* Add other periph IDs here as needed */
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	if (bad_config) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/pinmux.c b/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/pinmux.c
new file mode 100644
index 000000000..c6685eaae
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra124-common/pinmux.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+#define PIN(pin, f0, f1, f2, f3)	\
+	{				\
+		.funcs = {		\
+			PMUX_FUNC_##f0,	\
+			PMUX_FUNC_##f1,	\
+			PMUX_FUNC_##f2,	\
+			PMUX_FUNC_##f3,	\
+		},			\
+	}
+
+#define PIN_RESERVED {}
+
+static const struct pmux_pingrp_desc tegra124_pingroups[] = {
+	/*  pin,                    f0,         f1,       f2,           f3 */
+	/* Offset 0x3000 */
+	PIN(ULPI_DATA0_PO1,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA1_PO2,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA2_PO3,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA3_PO4,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA4_PO5,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA5_PO6,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA6_PO7,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA7_PO0,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_CLK_PY0,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(ULPI_DIR_PY1,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(ULPI_NXT_PY2,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(ULPI_STP_PY3,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(DAP3_FS_PP0,            I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+	PIN(DAP3_DIN_PP1,           I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+	PIN(DAP3_DOUT_PP2,          I2S2,       SPI5,     DISPLAYA,     RSVD4),
+	PIN(DAP3_SCLK_PP3,          I2S2,       SPI5,     RSVD3,        DISPLAYB),
+	PIN(PV0,                    RSVD1,      RSVD2,    RSVD3,        RSVD4),
+	PIN(PV1,                    RSVD1,      RSVD2,    RSVD3,        RSVD4),
+	PIN(SDMMC1_CLK_PZ0,         SDMMC1,     CLK12,    RSVD3,        RSVD4),
+	PIN(SDMMC1_CMD_PZ1,         SDMMC1,     SPDIF,    SPI4,         UARTA),
+	PIN(SDMMC1_DAT3_PY4,        SDMMC1,     SPDIF,    SPI4,         UARTA),
+	PIN(SDMMC1_DAT2_PY5,        SDMMC1,     PWM0,     SPI4,         UARTA),
+	PIN(SDMMC1_DAT1_PY6,        SDMMC1,     PWM1,     SPI4,         UARTA),
+	PIN(SDMMC1_DAT0_PY7,        SDMMC1,     RSVD2,    SPI4,         UARTA),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3068 */
+	PIN(CLK2_OUT_PW5,           EXTPERIPH2, RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK2_REQ_PCC5,          DAP,        RSVD2,    RSVD3,        RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3110 */
+	PIN(HDMI_INT_PN7,           RSVD1,      RSVD2,    RSVD3,        RSVD4),
+	PIN(DDC_SCL_PV4,            I2C4,       RSVD2,    RSVD3,        RSVD4),
+	PIN(DDC_SDA_PV5,            I2C4,       RSVD2,    RSVD3,        RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3164 */
+	PIN(UART2_RXD_PC3,          IRDA,       SPDIF,    UARTA,        SPI4),
+	PIN(UART2_TXD_PC2,          IRDA,       SPDIF,    UARTA,        SPI4),
+	PIN(UART2_RTS_N_PJ6,        UARTA,      UARTB,    GMI,          SPI4),
+	PIN(UART2_CTS_N_PJ5,        UARTA,      UARTB,    GMI,          SPI4),
+	PIN(UART3_TXD_PW6,          UARTC,      RSVD2,    GMI,          SPI4),
+	PIN(UART3_RXD_PW7,          UARTC,      RSVD2,    GMI,          SPI4),
+	PIN(UART3_CTS_N_PA1,        UARTC,      SDMMC1,   DTV,          GMI),
+	PIN(UART3_RTS_N_PC0,        UARTC,      PWM0,     DTV,          GMI),
+	PIN(PU0,                    OWR,        UARTA,    GMI,          RSVD4),
+	PIN(PU1,                    RSVD1,      UARTA,    GMI,          RSVD4),
+	PIN(PU2,                    RSVD1,      UARTA,    GMI,          RSVD4),
+	PIN(PU3,                    PWM0,       UARTA,    GMI,          DISPLAYB),
+	PIN(PU4,                    PWM1,       UARTA,    GMI,          DISPLAYB),
+	PIN(PU5,                    PWM2,       UARTA,    GMI,          DISPLAYB),
+	PIN(PU6,                    PWM3,       UARTA,    RSVD3,        GMI),
+	PIN(GEN1_I2C_SDA_PC5,       I2C1,       RSVD2,    RSVD3,        RSVD4),
+	PIN(GEN1_I2C_SCL_PC4,       I2C1,       RSVD2,    RSVD3,        RSVD4),
+	PIN(DAP4_FS_PP4,            I2S3,       GMI,      DTV,          RSVD4),
+	PIN(DAP4_DIN_PP5,           I2S3,       GMI,      RSVD3,        RSVD4),
+	PIN(DAP4_DOUT_PP6,          I2S3,       GMI,      DTV,          RSVD4),
+	PIN(DAP4_SCLK_PP7,          I2S3,       GMI,      RSVD3,        RSVD4),
+	PIN(CLK3_OUT_PEE0,          EXTPERIPH3, RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK3_REQ_PEE1,          DEV3,       RSVD2,    RSVD3,        RSVD4),
+	PIN(PC7,                    RSVD1,      RSVD2,    GMI,          GMI_ALT),
+	PIN(PI5,                    SDMMC2,     RSVD2,    GMI,          RSVD4),
+	PIN(PI7,                    RSVD1,      TRACE,    GMI,          DTV),
+	PIN(PK0,                    RSVD1,      SDMMC3,   GMI,          SOC),
+	PIN(PK1,                    SDMMC2,     TRACE,    GMI,          RSVD4),
+	PIN(PJ0,                    RSVD1,      RSVD2,    GMI,          USB),
+	PIN(PJ2,                    RSVD1,      RSVD2,    GMI,          SOC),
+	PIN(PK3,                    SDMMC2,     TRACE,    GMI,          CCLA),
+	PIN(PK4,                    SDMMC2,     RSVD2,    GMI,          GMI_ALT),
+	PIN(PK2,                    RSVD1,      RSVD2,    GMI,          RSVD4),
+	PIN(PI3,                    RSVD1,      RSVD2,    GMI,          SPI4),
+	PIN(PI6,                    RSVD1,      RSVD2,    GMI,          SDMMC2),
+	PIN(PG0,                    RSVD1,      RSVD2,    GMI,          RSVD4),
+	PIN(PG1,                    RSVD1,      RSVD2,    GMI,          RSVD4),
+	PIN(PG2,                    RSVD1,      TRACE,    GMI,          RSVD4),
+	PIN(PG3,                    RSVD1,      TRACE,    GMI,          RSVD4),
+	PIN(PG4,                    RSVD1,      TMDS,     GMI,          SPI4),
+	PIN(PG5,                    RSVD1,      RSVD2,    GMI,          SPI4),
+	PIN(PG6,                    RSVD1,      RSVD2,    GMI,          SPI4),
+	PIN(PG7,                    RSVD1,      RSVD2,    GMI,          SPI4),
+	PIN(PH0,                    PWM0,       TRACE,    GMI,          DTV),
+	PIN(PH1,                    PWM1,       TMDS,     GMI,          DISPLAYA),
+	PIN(PH2,                    PWM2,       TMDS,     GMI,          CLDVFS),
+	PIN(PH3,                    PWM3,       SPI4,     GMI,          CLDVFS),
+	PIN(PH4,                    SDMMC2,     RSVD2,    GMI,          RSVD4),
+	PIN(PH5,                    SDMMC2,     RSVD2,    GMI,          RSVD4),
+	PIN(PH6,                    SDMMC2,     TRACE,    GMI,          DTV),
+	PIN(PH7,                    SDMMC2,     TRACE,    GMI,          DTV),
+	PIN(PJ7,                    UARTD,      RSVD2,    GMI,          GMI_ALT),
+	PIN(PB0,                    UARTD,      RSVD2,    GMI,          RSVD4),
+	PIN(PB1,                    UARTD,      RSVD2,    GMI,          RSVD4),
+	PIN(PK7,                    UARTD,      RSVD2,    GMI,          RSVD4),
+	PIN(PI0,                    RSVD1,      RSVD2,    GMI,          RSVD4),
+	PIN(PI1,                    RSVD1,      RSVD2,    GMI,          RSVD4),
+	PIN(PI2,                    SDMMC2,     TRACE,    GMI,          RSVD4),
+	PIN(PI4,                    SPI4,       TRACE,    GMI,          DISPLAYA),
+	PIN(GEN2_I2C_SCL_PT5,       I2C2,       RSVD2,    GMI,          RSVD4),
+	PIN(GEN2_I2C_SDA_PT6,       I2C2,       RSVD2,    GMI,          RSVD4),
+	PIN(SDMMC4_CLK_PCC4,        SDMMC4,     RSVD2,    GMI,          RSVD4),
+	PIN(SDMMC4_CMD_PT7,         SDMMC4,     RSVD2,    GMI,          RSVD4),
+	PIN(SDMMC4_DAT0_PAA0,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT1_PAA1,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT2_PAA2,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT3_PAA3,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT4_PAA4,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT5_PAA5,       SDMMC4,     SPI3,     RSVD3,        RSVD4),
+	PIN(SDMMC4_DAT6_PAA6,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT7_PAA7,       SDMMC4,     RSVD2,    GMI,          RSVD4),
+	PIN_RESERVED,
+	/* Offset 0x3284 */
+	PIN(CAM_MCLK_PCC0,          VI,         VI_ALT1,  VI_ALT3,      SDMMC2),
+	PIN(PCC1,                   I2S4,       RSVD2,    RSVD3,        SDMMC2),
+	PIN(PBB0,                   VGP6,       VIMCLK2,  SDMMC2,       VIMCLK2_ALT),
+	PIN(CAM_I2C_SCL_PBB1,       VGP1,       I2C3,     RSVD3,        SDMMC2),
+	PIN(CAM_I2C_SDA_PBB2,       VGP2,       I2C3,     RSVD3,        SDMMC2),
+	PIN(PBB3,                   VGP3,       DISPLAYA, DISPLAYB,     SDMMC2),
+	PIN(PBB4,                   VGP4,       DISPLAYA, DISPLAYB,     SDMMC2),
+	PIN(PBB5,                   VGP5,       DISPLAYA, RSVD3,        SDMMC2),
+	PIN(PBB6,                   I2S4,       RSVD2,    DISPLAYB,     SDMMC2),
+	PIN(PBB7,                   I2S4,       RSVD2,    RSVD3,        SDMMC2),
+	PIN(PCC2,                   I2S4,       RSVD2,    SDMMC3,       SDMMC2),
+	PIN(JTAG_RTCK,              RTCK,       RSVD2,    RSVD3,        RSVD4),
+	PIN(PWR_I2C_SCL_PZ6,        I2CPWR,     RSVD2,    RSVD3,        RSVD4),
+	PIN(PWR_I2C_SDA_PZ7,        I2CPWR,     RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW0_PR0,            KBC,        RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW1_PR1,            KBC,        RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW2_PR2,            KBC,        RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW3_PR3,            KBC,        DISPLAYA, SYS,          DISPLAYB),
+	PIN(KB_ROW4_PR4,            KBC,        DISPLAYA, RSVD3,        DISPLAYB),
+	PIN(KB_ROW5_PR5,            KBC,        DISPLAYA, RSVD3,        DISPLAYB),
+	PIN(KB_ROW6_PR6,            KBC,        DISPLAYA, DISPLAYA_ALT, DISPLAYB),
+	PIN(KB_ROW7_PR7,            KBC,        RSVD2,    CLDVFS,       UARTA),
+	PIN(KB_ROW8_PS0,            KBC,        RSVD2,    CLDVFS,       UARTA),
+	PIN(KB_ROW9_PS1,            KBC,        RSVD2,    RSVD3,        UARTA),
+	PIN(KB_ROW10_PS2,           KBC,        RSVD2,    RSVD3,        UARTA),
+	PIN(KB_ROW11_PS3,           KBC,        RSVD2,    RSVD3,        IRDA),
+	PIN(KB_ROW12_PS4,           KBC,        RSVD2,    RSVD3,        IRDA),
+	PIN(KB_ROW13_PS5,           KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(KB_ROW14_PS6,           KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(KB_ROW15_PS7,           KBC,        SOC,      RSVD3,        RSVD4),
+	PIN(KB_COL0_PQ0,            KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(KB_COL1_PQ1,            KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(KB_COL2_PQ2,            KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(KB_COL3_PQ3,            KBC,        DISPLAYA, PWM2,         UARTA),
+	PIN(KB_COL4_PQ4,            KBC,        OWR,      SDMMC3,       UARTA),
+	PIN(KB_COL5_PQ5,            KBC,        RSVD2,    SDMMC3,       RSVD4),
+	PIN(KB_COL6_PQ6,            KBC,        RSVD2,    SPI2,         UARTD),
+	PIN(KB_COL7_PQ7,            KBC,        RSVD2,    SPI2,         UARTD),
+	PIN(CLK_32K_OUT_PA0,        BLINK,      SOC,      RSVD3,        RSVD4),
+	PIN_RESERVED,
+	/* Offset 0x3324 */
+	PIN(CORE_PWR_REQ,           PWRON,      RSVD2,    RSVD3,        RSVD4),
+	PIN(CPU_PWR_REQ,            CPU,        RSVD2,    RSVD3,        RSVD4),
+	PIN(PWR_INT_N,              PMI,        RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK_32K_IN,             CLK,        RSVD2,    RSVD3,        RSVD4),
+	PIN(OWR,                    OWR,        RSVD2,    RSVD3,        RSVD4),
+	PIN(DAP1_FS_PN0,            I2S0,       HDA,      GMI,          RSVD4),
+	PIN(DAP1_DIN_PN1,           I2S0,       HDA,      GMI,          RSVD4),
+	PIN(DAP1_DOUT_PN2,          I2S0,       HDA,      GMI,          SATA),
+	PIN(DAP1_SCLK_PN3,          I2S0,       HDA,      GMI,          RSVD4),
+	PIN(DAP_MCLK1_REQ_PEE2,     DAP,        DAP1,     SATA,         RSVD4),
+	PIN(DAP_MCLK1_PW4,          EXTPERIPH1, DAP2,     RSVD3,        RSVD4),
+	PIN(SPDIF_IN_PK6,           SPDIF,      RSVD2,    RSVD3,        I2C3),
+	PIN(SPDIF_OUT_PK5,          SPDIF,      RSVD2,    RSVD3,        I2C3),
+	PIN(DAP2_FS_PA2,            I2S1,       HDA,      GMI,          RSVD4),
+	PIN(DAP2_DIN_PA4,           I2S1,       HDA,      GMI,          RSVD4),
+	PIN(DAP2_DOUT_PA5,          I2S1,       HDA,      GMI,          RSVD4),
+	PIN(DAP2_SCLK_PA3,          I2S1,       HDA,      GMI,          RSVD4),
+	PIN(DVFS_PWM_PX0,           SPI6,       CLDVFS,   GMI,          RSVD4),
+	PIN(GPIO_X1_AUD_PX1,        SPI6,       RSVD2,    GMI,          RSVD4),
+	PIN(GPIO_X3_AUD_PX3,        SPI6,       SPI1,     GMI,          RSVD4),
+	PIN(DVFS_CLK_PX2,           SPI6,       CLDVFS,   GMI,          RSVD4),
+	PIN(GPIO_X4_AUD_PX4,        GMI,        SPI1,     SPI2,         DAP2),
+	PIN(GPIO_X5_AUD_PX5,        GMI,        SPI1,     SPI2,         RSVD4),
+	PIN(GPIO_X6_AUD_PX6,        SPI6,       SPI1,     SPI2,         GMI),
+	PIN(GPIO_X7_AUD_PX7,        RSVD1,      SPI1,     SPI2,         RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3390 */
+	PIN(SDMMC3_CLK_PA6,         SDMMC3,     RSVD2,    RSVD3,        SPI3),
+	PIN(SDMMC3_CMD_PA7,         SDMMC3,     PWM3,     UARTA,        SPI3),
+	PIN(SDMMC3_DAT0_PB7,        SDMMC3,     RSVD2,    RSVD3,        SPI3),
+	PIN(SDMMC3_DAT1_PB6,        SDMMC3,     PWM2,     UARTA,        SPI3),
+	PIN(SDMMC3_DAT2_PB5,        SDMMC3,     PWM1,     DISPLAYA,     SPI3),
+	PIN(SDMMC3_DAT3_PB4,        SDMMC3,     PWM0,     DISPLAYB,     SPI3),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x33bc */
+	PIN(PEX_L0_RST_N_PDD1,      PE0,        RSVD2,    RSVD3,        RSVD4),
+	PIN(PEX_L0_CLKREQ_N_PDD2,   PE0,        RSVD2,    RSVD3,        RSVD4),
+	PIN(PEX_WAKE_N_PDD3,        PE,         RSVD2,    RSVD3,        RSVD4),
+	PIN_RESERVED,
+	/* Offset 0x33cc */
+	PIN(PEX_L1_RST_N_PDD5,      PE1,        RSVD2,    RSVD3,        RSVD4),
+	PIN(PEX_L1_CLKREQ_N_PDD6,   PE1,        RSVD2,    RSVD3,        RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x33e0 */
+	PIN(HDMI_CEC_PEE3,          CEC,        RSVD2,    RSVD3,        RSVD4),
+	PIN(SDMMC1_WP_N_PV3,        SDMMC1,     CLK12,    SPI4,         UARTA),
+	PIN(SDMMC3_CD_N_PV2,        SDMMC3,     OWR,      RSVD3,        RSVD4),
+	PIN(GPIO_W2_AUD_PW2,        SPI6,       RSVD2,    SPI2,         I2C1),
+	PIN(GPIO_W3_AUD_PW3,        SPI6,       SPI1,     SPI2,         I2C1),
+	PIN(USB_VBUS_EN0_PN4,       USB,        RSVD2,    RSVD3,        RSVD4),
+	PIN(USB_VBUS_EN1_PN5,       USB,        RSVD2,    RSVD3,        RSVD4),
+	PIN(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,     RSVD2,    RSVD3,        RSVD4),
+	PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,     RSVD2,    RSVD3,        RSVD4),
+	PIN(GMI_CLK_LB,             SDMMC2,     RSVD2,    GMI,          RSVD4),
+	PIN(RESET_OUT_N,            RSVD1,      RSVD2,    RSVD3,        RESET_OUT_N),
+	PIN(KB_ROW16_PT0,           KBC,        RSVD2,    RSVD3,        UARTC),
+	PIN(KB_ROW17_PT1,           KBC,        RSVD2,    RSVD3,        UARTC),
+	PIN(USB_VBUS_EN2_PFF1,      USB,        RSVD2,    RSVD3,        RSVD4),
+	PIN(PFF2,                   SATA,       RSVD2,    RSVD3,        RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3430 */
+	PIN(DP_HPD_PFF0,            DP,         RSVD2,    RSVD3,        RSVD4),
+};
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/Makefile
new file mode 100644
index 000000000..0e4b3fc1d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/Makefile
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+# The AVP is ARMv4T architecture so we must use special compiler
+# flags for any startup files it might use.
+CFLAGS_warmboot_avp.o += -march=armv4t
+
+obj-y	+= clock.o funcmux.o pinmux.o
+obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
+obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
+obj-$(CONFIG_TEGRA_PMU) += pmu.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/clock.c b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/clock.c
new file mode 100644
index 000000000..0c4f5fb28
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/clock.c
@@ -0,0 +1,550 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Tegra20 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra20 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
+	CLOCK_TYPE_MCPA,	/* and so on */
+	CLOCK_TYPE_MCPT,
+	CLOCK_TYPE_PCM,
+	CLOCK_TYPE_PCMT,
+	CLOCK_TYPE_PCMT16,	/* CLOCK_TYPE_PCMT with 16-bit divider */
+	CLOCK_TYPE_PCXTS,
+	CLOCK_TYPE_PDCT,
+
+	CLOCK_TYPE_COUNT,
+	CLOCK_TYPE_NONE = -1,	/* invalid clock type */
+};
+
+enum {
+	CLOCK_MAX_MUX	= 4	/* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
+ * is special as it has 5 sources. Since it also has a different number of
+ * bits in its register for the source, we just handle it with a special
+ * case in the code.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
+	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC)	},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO)	},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC)	},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE)	},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(XCPU),	CLK(OSC)	},
+	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC)	},
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
+ * not in the header file since it is for purely internal use - we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ *
+ * Note to SOC vendors: perhaps define a unified numbering for peripherals and
+ * use it for reset, clock enable, clock source/divider and even pinmuxing
+ * if you can.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_SPI1,
+	PERIPHC_SPI2,
+	PERIPHC_SPI3,
+
+	/* 0x08 */
+	PERIPHC_XIO,
+	PERIPHC_I2C1,
+	PERIPHC_DVC_I2C,
+	PERIPHC_TWC,
+	PERIPHC_0c,
+	PERIPHC_10,	/* PERIPHC_SPI1, what is this really? */
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_CVE,
+	PERIPHC_IDE0,
+	PERIPHC_VI,
+	PERIPHC_1c,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_EPP,
+	PERIPHC_MPE,
+	PERIPHC_MIPI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21,
+	PERIPHC_TVO,
+	PERIPHC_HDMI,
+	PERIPHC_24,
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2b,
+	PERIPHC_2c,
+	PERIPHC_SPI4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+	/* 0x00 */
+	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_IN,	CLOCK_TYPE_PCM),
+	TYPE(PERIPHC_PWM,	CLOCK_TYPE_PCXTS),
+	TYPE(PERIPHC_SPI1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SPI22,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SPI3,	CLOCK_TYPE_PCMT),
+
+	/* 0x08 */
+	TYPE(PERIPHC_XIO,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_DVC_I2C,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_TWC,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SPI1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_DISP1,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_DISP2,	CLOCK_TYPE_PDCT),
+
+	/* 0x10 */
+	TYPE(PERIPHC_CVE,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_IDE0,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_G3D,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_G2D,	CLOCK_TYPE_MCPA),
+
+	/* 0x18 */
+	TYPE(PERIPHC_NDFLASH,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VFIR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_EPP,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MPE,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MIPI,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART2,	CLOCK_TYPE_PCMT),
+
+	/* 0x20 */
+	TYPE(PERIPHC_HOST1X,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVO,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVDAC,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),
+
+	/* 0x28 */
+	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SPI4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PCMT),
+
+	/* 0x30 */
+	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PCMT),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
+ *	SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+	/* Low word: 31:0 */
+	NONE(CPU),
+	NONE(RESERVED1),
+	NONE(RESERVED2),
+	NONE(AC97),
+	NONE(RTC),
+	NONE(TMR),
+	PERIPHC_UART1,
+	PERIPHC_UART2,	/* and vfir 0x68 */
+
+	/* 0x08 */
+	NONE(GPIO),
+	PERIPHC_SDMMC2,
+	NONE(SPDIF),		/* 0x08 and 0x0c, unclear which to use */
+	PERIPHC_I2S1,
+	PERIPHC_I2C1,
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC4,
+
+	/* 0x10 */
+	PERIPHC_TWC,
+	PERIPHC_PWM,
+	PERIPHC_I2S2,
+	PERIPHC_EPP,
+	PERIPHC_VI,
+	PERIPHC_G2D,
+	NONE(USBD),
+	NONE(ISP),
+
+	/* 0x18 */
+	PERIPHC_G3D,
+	PERIPHC_IDE0,
+	PERIPHC_DISP2,
+	PERIPHC_DISP1,
+	PERIPHC_HOST1X,
+	NONE(VCP),
+	NONE(RESERVED30),
+	NONE(CACHE2),
+
+	/* Middle word: 63:32 */
+	NONE(MEM),
+	NONE(AHBDMA),
+	NONE(APBDMA),
+	NONE(RESERVED35),
+	NONE(KBC),
+	NONE(STAT_MON),
+	NONE(PMC),
+	NONE(FUSE),
+
+	/* 0x28 */
+	NONE(KFUSE),
+	NONE(SBC1),	/* SBC1, 0x34, is this SPI1? */
+	PERIPHC_NOR,
+	PERIPHC_SPI1,
+	PERIPHC_SPI2,
+	PERIPHC_XIO,
+	PERIPHC_SPI3,
+	PERIPHC_DVC_I2C,
+
+	/* 0x30 */
+	NONE(DSI),
+	PERIPHC_TVO,	/* also CVE 0x40 */
+	PERIPHC_MIPI,
+	PERIPHC_HDMI,
+	PERIPHC_CSITE,
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_UART3,
+
+	/* 0x38 */
+	NONE(RESERVED56),
+	PERIPHC_EMC,
+	NONE(USB2),
+	NONE(USB3),
+	PERIPHC_MPE,
+	PERIPHC_VDE,
+	NONE(BSEA),
+	NONE(BSEV),
+
+	/* Upper word 95:64 */
+	NONE(SPEEDO),
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_I2C3,
+	PERIPHC_SPI4,
+	PERIPHC_SDMMC3,
+	NONE(PCIE),
+	PERIPHC_OWR,
+
+	/* 0x48 */
+	NONE(AFI),
+	NONE(CORESIGHT),
+	NONE(RESERVED74),
+	NONE(AVPUCQ),
+	NONE(RESERVED76),
+	NONE(RESERVED77),
+	NONE(RESERVED78),
+	NONE(RESERVED79),
+
+	/* 0x50 */
+	NONE(RESERVED80),
+	NONE(RESERVED81),
+	NONE(RESERVED82),
+	NONE(RESERVED83),
+	NONE(IRAMA),
+	NONE(IRAMB),
+	NONE(IRAMC),
+	NONE(IRAMD),
+
+	/* 0x58 */
+	NONE(CRAM2),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. T20 has 4 frequencies that it supports.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	enum periphc_internal_id internal_id;
+
+	assert(clock_periph_id_isvalid(periph_id));
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(internal_id != -1);
+	return &clkrst->crc_clk_src[internal_id];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id	peripheral to start
+ * @param source	PLL id of required parent clock
+ * @param mux_bits	Set to number of bits in mux register: 2 or 4
+ * @param divider_bits	Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+		enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+	enum clock_type_id type;
+	enum periphc_internal_id internal_id;
+	int mux;
+
+	assert(clock_periph_id_isvalid(periph_id));
+
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(periphc_internal_id_isvalid(internal_id));
+
+	type = clock_periph_type[internal_id];
+	assert(clock_type_id_isvalid(type));
+
+	/*
+	 * Special cases here for the clock with a 4-bit source mux and I2C
+	 * with its 16-bit divisor
+	 */
+	if (type == CLOCK_TYPE_PCXTS)
+		*mux_bits = MASK_BITS_31_28;
+	else
+		*mux_bits = MASK_BITS_31_30;
+	if (type == CLOCK_TYPE_PCMT16)
+		*divider_bits = 16;
+	else
+		*divider_bits = 8;
+
+	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+		if (clock_source[type][mux] == parent)
+			return mux;
+
+	/*
+	 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
+	 * which is not in our table. If not, then they are asking for a
+	 * source which this peripheral can't access through its mux.
+	 */
+	assert(type == CLOCK_TYPE_PCXTS);
+	assert(parent == CLOCK_ID_SFROM32KHZ);
+	if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
+		return 4;	/* mux value for this clock */
+
+	/* if we get here, either us or the caller has made a mistake */
+	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+		parent);
+	return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+	u32 reg;
+
+	/* Enable/disable the clock to this peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	reg = readl(clk);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+	u32 reg;
+
+	/* Enable/disable reset to the peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	reg = readl(reset);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id	Clock ID according to tegra20 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+	if (clk_id > PERIPH_ID_COUNT)
+		return PERIPH_ID_NONE;
+
+	switch (clk_id) {
+	case PERIPH_ID_RESERVED1:
+	case PERIPH_ID_RESERVED2:
+	case PERIPH_ID_RESERVED30:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED56:
+	case PERIPH_ID_RESERVED74:
+	case PERIPH_ID_RESERVED76:
+	case PERIPH_ID_RESERVED77:
+	case PERIPH_ID_RESERVED78:
+	case PERIPH_ID_RESERVED79:
+	case PERIPH_ID_RESERVED80:
+	case PERIPH_ID_RESERVED81:
+	case PERIPH_ID_RESERVED82:
+	case PERIPH_ID_RESERVED83:
+	case PERIPH_ID_RESERVED91:
+		return PERIPH_ID_NONE;
+	default:
+		return clk_id;
+	}
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+	/*
+	 * PLLP output frequency set to 216MHz
+	 * PLLC output frequency set to 600Mhz
+	 *
+	 * TODO: Can we calculate these values instead of hard-coding?
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+}
+
+void arch_timer_init(void)
+{
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/crypto.c b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/crypto.c
new file mode 100644
index 000000000..ec95d7ceb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/crypto.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include "crypto.h"
+#include "aes.h"
+
+static u8 zero_key[16];
+
+#define AES_CMAC_CONST_RB 0x87  /* from RFC 4493, Figure 2.2 */
+
+enum security_op {
+	SECURITY_SIGN		= 1 << 0,	/* Sign the data */
+	SECURITY_ENCRYPT	= 1 << 1,	/* Encrypt the data */
+};
+
+/**
+ * Shift a vector left by one bit
+ *
+ * \param in	Input vector
+ * \param out	Output vector
+ * \param size	Length of vector in bytes
+ */
+static void left_shift_vector(u8 *in, u8 *out, int size)
+{
+	int carry = 0;
+	int i;
+
+	for (i = size - 1; i >= 0; i--) {
+		out[i] = (in[i] << 1) | carry;
+		carry = in[i] >> 7;	/* get most significant bit */
+	}
+}
+
+/**
+ * Sign a block of data, putting the result into dst.
+ *
+ * \param key			Input AES key, length AES_KEY_LENGTH
+ * \param key_schedule		Expanded key to use
+ * \param src			Source data of length 'num_aes_blocks' blocks
+ * \param dst			Destination buffer, length AES_KEY_LENGTH
+ * \param num_aes_blocks	Number of AES blocks to encrypt
+ */
+static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
+			u32 num_aes_blocks)
+{
+	u8 tmp_data[AES_KEY_LENGTH];
+	u8 left[AES_KEY_LENGTH];
+	u8 k1[AES_KEY_LENGTH];
+	u8 *cbc_chain_data;
+	unsigned i;
+
+	cbc_chain_data = zero_key;	/* Convenient array of 0's for IV */
+
+	/* compute K1 constant needed by AES-CMAC calculation */
+	for (i = 0; i < AES_KEY_LENGTH; i++)
+		tmp_data[i] = 0;
+
+	aes_cbc_encrypt_blocks(key_schedule, tmp_data, left, 1);
+
+	left_shift_vector(left, k1, sizeof(left));
+
+	if ((left[0] >> 7) != 0) /* get MSB of L */
+		k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB;
+
+	/* compute the AES-CMAC value */
+	for (i = 0; i < num_aes_blocks; i++) {
+		/* Apply the chain data */
+		aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
+
+		/* for the final block, XOR K1 into the IV */
+		if (i == num_aes_blocks - 1)
+			aes_apply_cbc_chain_data(tmp_data, k1, tmp_data);
+
+		/* encrypt the AES block */
+		aes_encrypt(tmp_data, key_schedule, dst);
+
+		debug("sign_obj: block %d of %d\n", i, num_aes_blocks);
+
+		/* Update pointers for next loop. */
+		cbc_chain_data = dst;
+		src += AES_KEY_LENGTH;
+	}
+}
+
+/**
+ * Encrypt and sign a block of data (depending on security mode).
+ *
+ * \param key		Input AES key, length AES_KEY_LENGTH
+ * \param oper		Security operations mask to perform (enum security_op)
+ * \param src		Source data
+ * \param length	Size of source data
+ * \param sig_dst	Destination address for signature, AES_KEY_LENGTH bytes
+ */
+static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
+			    u32 length, u8 *sig_dst)
+{
+	u32 num_aes_blocks;
+	u8 key_schedule[AES_EXPAND_KEY_LENGTH];
+
+	debug("encrypt_and_sign: length = %d\n", length);
+
+	/*
+	 * The only need for a key is for signing/checksum purposes, so
+	 * if not encrypting, expand a key of 0s.
+	 */
+	aes_expand_key(oper & SECURITY_ENCRYPT ? key : zero_key, key_schedule);
+
+	num_aes_blocks = (length + AES_KEY_LENGTH - 1) / AES_KEY_LENGTH;
+
+	if (oper & SECURITY_ENCRYPT) {
+		/* Perform this in place, resulting in src being encrypted. */
+		debug("encrypt_and_sign: begin encryption\n");
+		aes_cbc_encrypt_blocks(key_schedule, src, src, num_aes_blocks);
+		debug("encrypt_and_sign: end encryption\n");
+	}
+
+	if (oper & SECURITY_SIGN) {
+		/* encrypt the data, overwriting the result in signature. */
+		debug("encrypt_and_sign: begin signing\n");
+		sign_object(key, key_schedule, src, sig_dst, num_aes_blocks);
+		debug("encrypt_and_sign: end signing\n");
+	}
+
+	return 0;
+}
+
+int sign_data_block(u8 *source, unsigned length, u8 *signature)
+{
+	return encrypt_and_sign(zero_key, SECURITY_SIGN, source,
+				length, signature);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/crypto.h b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/crypto.h
new file mode 100644
index 000000000..f59b92768
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/crypto.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CRYPTO_H_
+#define _CRYPTO_H_
+
+/**
+ * Sign a block of data
+ *
+ * \param source	Source data
+ * \param length	Size of source data
+ * \param signature	Destination address for signature, AES_KEY_LENGTH bytes
+ */
+int sign_data_block(u8 *source, unsigned length, u8 *signature);
+
+#endif /* #ifndef _CRYPTO_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/emc.c b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/emc.c
new file mode 100644
index 000000000..ed2462ab0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/emc.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/apb_misc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/emc.h>
+#include <asm/arch/tegra.h>
+
+/*
+ * The EMC registers have shadow registers.  When the EMC clock is updated
+ * in the clock controller, the shadow registers are copied to the active
+ * registers, allowing glitchless memory bus frequency changes.
+ * This function updates the shadow registers for a new clock frequency,
+ * and relies on the clock lock on the emc clock to avoid races between
+ * multiple frequency changes
+ */
+
+/*
+ * This table defines the ordering of the registers provided to
+ * tegra_set_mmc()
+ * TODO: Convert to fdt version once available
+ */
+static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
+	0x2c,	/* RC */
+	0x30,	/* RFC */
+	0x34,	/* RAS */
+	0x38,	/* RP */
+	0x3c,	/* R2W */
+	0x40,	/* W2R */
+	0x44,	/* R2P */
+	0x48,	/* W2P */
+	0x4c,	/* RD_RCD */
+	0x50,	/* WR_RCD */
+	0x54,	/* RRD */
+	0x58,	/* REXT */
+	0x5c,	/* WDV */
+	0x60,	/* QUSE */
+	0x64,	/* QRST */
+	0x68,	/* QSAFE */
+	0x6c,	/* RDV */
+	0x70,	/* REFRESH */
+	0x74,	/* BURST_REFRESH_NUM */
+	0x78,	/* PDEX2WR */
+	0x7c,	/* PDEX2RD */
+	0x80,	/* PCHG2PDEN */
+	0x84,	/* ACT2PDEN */
+	0x88,	/* AR2PDEN */
+	0x8c,	/* RW2PDEN */
+	0x90,	/* TXSR */
+	0x94,	/* TCKE */
+	0x98,	/* TFAW */
+	0x9c,	/* TRPAB */
+	0xa0,	/* TCLKSTABLE */
+	0xa4,	/* TCLKSTOP */
+	0xa8,	/* TREFBW */
+	0xac,	/* QUSE_EXTRA */
+	0x114,	/* FBIO_CFG6 */
+	0xb0,	/* ODT_WRITE */
+	0xb4,	/* ODT_READ */
+	0x104,	/* FBIO_CFG5 */
+	0x2bc,	/* CFG_DIG_DLL */
+	0x2c0,	/* DLL_XFORM_DQS */
+	0x2c4,	/* DLL_XFORM_QUSE */
+	0x2e0,	/* ZCAL_REF_CNT */
+	0x2e4,	/* ZCAL_WAIT_CNT */
+	0x2a8,	/* AUTO_CAL_INTERVAL */
+	0x2d0,	/* CFG_CLKTRIM_0 */
+	0x2d4,	/* CFG_CLKTRIM_1 */
+	0x2d8,	/* CFG_CLKTRIM_2 */
+};
+
+struct emc_ctlr *emc_get_controller(const void *blob)
+{
+	fdt_addr_t addr;
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
+	if (node > 0) {
+		addr = fdtdec_get_addr(blob, node, "reg");
+		if (addr != FDT_ADDR_T_NONE)
+			return (struct emc_ctlr *)addr;
+	}
+	return NULL;
+}
+
+/* Error codes we use */
+enum {
+	ERR_NO_EMC_NODE = -10,
+	ERR_NO_EMC_REG,
+	ERR_NO_FREQ,
+	ERR_FREQ_NOT_FOUND,
+	ERR_BAD_REGS,
+	ERR_NO_RAM_CODE,
+	ERR_RAM_CODE_NOT_FOUND,
+};
+
+/**
+ * Find EMC tables for the given ram code.
+ *
+ * The tegra EMC binding has two options, one using the ram code and one not.
+ * We detect which is in use by looking for the nvidia,use-ram-code property.
+ * If this is not present, then the EMC tables are directly below 'node',
+ * otherwise we select the correct emc-tables subnode based on the 'ram_code'
+ * value.
+ *
+ * @param blob		Device tree blob
+ * @param node		EMC node (nvidia,tegra20-emc compatible string)
+ * @param ram_code	RAM code to select (0-3, or -1 if unknown)
+ * @return 0 if ok, otherwise a -ve ERR_ code (see enum above)
+ */
+static int find_emc_tables(const void *blob, int node, int ram_code)
+{
+	int need_ram_code;
+	int depth;
+	int offset;
+
+	/* If we are using RAM codes, scan through the tables for our code */
+	need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code");
+	if (!need_ram_code)
+		return node;
+	if (ram_code == -1) {
+		debug("%s: RAM code required but not supplied\n", __func__);
+		return ERR_NO_RAM_CODE;
+	}
+
+	offset = node;
+	depth = 0;
+	do {
+		/*
+		 * Sadly there is no compatible string so we cannot use
+		 * fdtdec_next_compatible_subnode().
+		 */
+		offset = fdt_next_node(blob, offset, &depth);
+		if (depth <= 0)
+			break;
+
+		/* Make sure this is a direct subnode */
+		if (depth != 1)
+			continue;
+		if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL)))
+			continue;
+
+		if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1)
+				== ram_code)
+			return offset;
+	} while (1);
+
+	debug("%s: Could not find tables for RAM code %d\n", __func__,
+	      ram_code);
+	return ERR_RAM_CODE_NOT_FOUND;
+}
+
+/**
+ * Decode the EMC node of the device tree, returning a pointer to the emc
+ * controller and the table to be used for the given rate.
+ *
+ * @param blob	Device tree blob
+ * @param rate	Clock speed of memory controller in Hz (=2x memory bus rate)
+ * @param emcp	Returns address of EMC controller registers
+ * @param tablep Returns pointer to table to program into EMC. There are
+ *		TEGRA_EMC_NUM_REGS entries, destined for offsets as per the
+ *		emc_reg_addr array.
+ * @return 0 if ok, otherwise a -ve error code which will allow someone to
+ * figure out roughly what went wrong by looking at this code.
+ */
+static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
+		      const u32 **tablep)
+{
+	struct apb_misc_pp_ctlr *pp =
+		(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
+	int ram_code;
+	int depth;
+	int node;
+
+	ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK)
+			>> RAM_CODE_SHIFT;
+	/*
+	 * The EMC clock rate is twice the bus rate, and the bus rate is
+	 * measured in kHz
+	 */
+	rate = rate / 2 / 1000;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
+	if (node < 0) {
+		debug("%s: No EMC node found in FDT\n", __func__);
+		return ERR_NO_EMC_NODE;
+	}
+	*emcp = (struct emc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	if (*emcp == (struct emc_ctlr *)FDT_ADDR_T_NONE) {
+		debug("%s: No EMC node reg property\n", __func__);
+		return ERR_NO_EMC_REG;
+	}
+
+	/* Work out the parent node which contains our EMC tables */
+	node = find_emc_tables(blob, node, ram_code & 3);
+	if (node < 0)
+		return node;
+
+	depth = 0;
+	for (;;) {
+		int node_rate;
+
+		node = fdtdec_next_compatible_subnode(blob, node,
+				COMPAT_NVIDIA_TEGRA20_EMC_TABLE, &depth);
+		if (node < 0)
+			break;
+		node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1);
+		if (node_rate == -1) {
+			debug("%s: Missing clock-frequency\n", __func__);
+			return ERR_NO_FREQ; /* we expect this property */
+		}
+
+		if (node_rate == rate)
+			break;
+	}
+	if (node < 0) {
+		debug("%s: No node found for clock frequency %d\n", __func__,
+		      rate);
+		return ERR_FREQ_NOT_FOUND;
+	}
+
+	*tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers",
+				      TEGRA_EMC_NUM_REGS);
+	if (!*tablep) {
+		debug("%s: node '%s' array missing / wrong size\n", __func__,
+		      fdt_get_name(blob, node, NULL));
+		return ERR_BAD_REGS;
+	}
+
+	/* All seems well */
+	return 0;
+}
+
+int tegra_set_emc(const void *blob, unsigned rate)
+{
+	struct emc_ctlr *emc;
+	const u32 *table = NULL;
+	int err, i;
+
+	err = decode_emc(blob, rate, &emc, &table);
+	if (err) {
+		debug("Warning: no valid EMC (%d), memory timings unset\n",
+		       err);
+		return err;
+	}
+
+	debug("%s: Table found, setting EMC values as follows:\n", __func__);
+	for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) {
+		u32 value = fdt32_to_cpu(table[i]);
+		u32 addr = (uintptr_t)emc + emc_reg_addr[i];
+
+		debug("   %#x: %#x\n", addr, value);
+		writel(value, addr);
+	}
+
+	/* trigger emc with new settings */
+	clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY,
+				clock_get_rate(CLOCK_ID_MEMORY), NULL);
+	debug("EMC clock set to %lu\n",
+	      clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY));
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/funcmux.c b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/funcmux.c
new file mode 100644
index 000000000..0df4a0738
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/funcmux.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Tegra20 high-level function multiplexing */
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+/*
+ * The PINMUX macro is used to set up pinmux tables.
+ */
+#define PINMUX(grp, mux, pupd, tri)                   \
+	{PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
+
+static const struct pmux_pingrp_config disp1_default[] = {
+	PINMUX(LDI,   DISPA,      NORMAL,    NORMAL),
+	PINMUX(LHP0,  DISPA,      NORMAL,    NORMAL),
+	PINMUX(LHP1,  DISPA,      NORMAL,    NORMAL),
+	PINMUX(LHP2,  DISPA,      NORMAL,    NORMAL),
+	PINMUX(LHS,   DISPA,      NORMAL,    NORMAL),
+	PINMUX(LM0,   RSVD4,      NORMAL,    NORMAL),
+	PINMUX(LPP,   DISPA,      NORMAL,    NORMAL),
+	PINMUX(LPW0,  DISPA,      NORMAL,    NORMAL),
+	PINMUX(LPW2,  DISPA,      NORMAL,    NORMAL),
+	PINMUX(LSC0,  DISPA,      NORMAL,    NORMAL),
+	PINMUX(LSPI,  DISPA,      NORMAL,    NORMAL),
+	PINMUX(LVP1,  DISPA,      NORMAL,    NORMAL),
+	PINMUX(LVS,   DISPA,      NORMAL,    NORMAL),
+	PINMUX(SLXD,  SPDIF,      NORMAL,    NORMAL),
+};
+
+
+int funcmux_select(enum periph_id id, int config)
+{
+	int bad_config = config != FUNCMUX_DEFAULT;
+
+	switch (id) {
+	case PERIPH_ID_UART1:
+		switch (config) {
+		case FUNCMUX_UART1_IRRX_IRTX:
+			pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA);
+			pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PMUX_PINGRP_IRRX);
+			pinmux_tristate_disable(PMUX_PINGRP_IRTX);
+			break;
+		case FUNCMUX_UART1_UAA_UAB:
+			pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA);
+			pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PMUX_PINGRP_UAA);
+			pinmux_tristate_disable(PMUX_PINGRP_UAB);
+			bad_config = 0;
+			break;
+		case FUNCMUX_UART1_GPU:
+			pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PMUX_PINGRP_GPU);
+			bad_config = 0;
+			break;
+		case FUNCMUX_UART1_SDIO1:
+			pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
+			bad_config = 0;
+			break;
+		}
+		if (!bad_config) {
+			/*
+			 * Tegra appears to boot with function UARTA pre-
+			 * selected on mux group SDB. If two mux groups are
+			 * both set to the same function, it's unclear which
+			 * group's pins drive the RX signals into the HW.
+			 * For UARTA, SDB certainly overrides group IRTX in
+			 * practice. To solve this, configure some alternative
+			 * function on SDB to avoid the conflict. Also, tri-
+			 * state the group to avoid driving any signal onto it
+			 * until we know what's connected.
+			 */
+			pinmux_tristate_enable(PMUX_PINGRP_SDB);
+			pinmux_set_func(PMUX_PINGRP_SDB,  PMUX_FUNC_SDIO3);
+		}
+		break;
+
+	case PERIPH_ID_UART2:
+		if (config == FUNCMUX_UART2_UAD) {
+			pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB);
+			pinmux_tristate_disable(PMUX_PINGRP_UAD);
+		}
+		break;
+
+	case PERIPH_ID_UART4:
+		if (config == FUNCMUX_UART4_GMC) {
+			pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD);
+			pinmux_tristate_disable(PMUX_PINGRP_GMC);
+		}
+		break;
+
+	case PERIPH_ID_DVC_I2C:
+		/* there is only one selection, pinmux_config is ignored */
+		if (config == FUNCMUX_DVC_I2CP) {
+			pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C);
+			pinmux_tristate_disable(PMUX_PINGRP_I2CP);
+		}
+		break;
+
+	case PERIPH_ID_I2C1:
+		/* support pinmux_config of 0 for now, */
+		if (config == FUNCMUX_I2C1_RM) {
+			pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C);
+			pinmux_tristate_disable(PMUX_PINGRP_RM);
+		}
+		break;
+	case PERIPH_ID_I2C2: /* I2C2 */
+		switch (config) {
+		case FUNCMUX_I2C2_DDC:	/* DDC pin group, select I2C2 */
+			pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2);
+			/* PTA to HDMI */
+			pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI);
+			pinmux_tristate_disable(PMUX_PINGRP_DDC);
+			break;
+		case FUNCMUX_I2C2_PTA:	/* PTA pin group, select I2C2 */
+			pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2);
+			/* set DDC_SEL to RSVDx (RSVD2 works for now) */
+			pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2);
+			pinmux_tristate_disable(PMUX_PINGRP_PTA);
+			bad_config = 0;
+			break;
+		}
+		break;
+	case PERIPH_ID_I2C3: /* I2C3 */
+		/* support pinmux_config of 0 for now */
+		if (config == FUNCMUX_I2C3_DTF) {
+			pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3);
+			pinmux_tristate_disable(PMUX_PINGRP_DTF);
+		}
+		break;
+
+	case PERIPH_ID_SDMMC1:
+		if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
+			pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+			pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
+		}
+		break;
+
+	case PERIPH_ID_SDMMC2:
+		if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
+			pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2);
+			pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2);
+
+			pinmux_tristate_disable(PMUX_PINGRP_DTA);
+			pinmux_tristate_disable(PMUX_PINGRP_DTD);
+		}
+		break;
+
+	case PERIPH_ID_SDMMC3:
+		switch (config) {
+		case FUNCMUX_SDMMC3_SDB_SLXA_8BIT:
+			pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3);
+			pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3);
+			pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3);
+			pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3);
+
+			pinmux_tristate_disable(PMUX_PINGRP_SLXA);
+			pinmux_tristate_disable(PMUX_PINGRP_SLXC);
+			pinmux_tristate_disable(PMUX_PINGRP_SLXD);
+			pinmux_tristate_disable(PMUX_PINGRP_SLXK);
+			/* fall through */
+
+		case FUNCMUX_SDMMC3_SDB_4BIT:
+			pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
+			pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3);
+			pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3);
+
+			pinmux_tristate_disable(PMUX_PINGRP_SDB);
+			pinmux_tristate_disable(PMUX_PINGRP_SDC);
+			pinmux_tristate_disable(PMUX_PINGRP_SDD);
+			bad_config = 0;
+			break;
+		}
+		break;
+
+	case PERIPH_ID_SDMMC4:
+		switch (config) {
+		case FUNCMUX_SDMMC4_ATC_ATD_8BIT:
+			pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4);
+			pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4);
+
+			pinmux_tristate_disable(PMUX_PINGRP_ATC);
+			pinmux_tristate_disable(PMUX_PINGRP_ATD);
+			break;
+
+		case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT:
+			pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
+			pinmux_tristate_disable(PMUX_PINGRP_GME);
+			/* fall through */
+
+		case FUNCMUX_SDMMC4_ATB_GMA_4_BIT:
+			pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
+			pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
+
+			pinmux_tristate_disable(PMUX_PINGRP_ATB);
+			pinmux_tristate_disable(PMUX_PINGRP_GMA);
+			bad_config = 0;
+			break;
+		}
+		break;
+
+	case PERIPH_ID_KBC:
+		if (config == FUNCMUX_DEFAULT) {
+			enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA,
+				PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC,
+				PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE,
+				PMUX_PINGRP_KBCF};
+			int i;
+
+			for (i = 0; i < ARRAY_SIZE(grp); i++) {
+				pinmux_tristate_disable(grp[i]);
+				pinmux_set_func(grp[i], PMUX_FUNC_KBC);
+				pinmux_set_pullupdown(grp[i], PMUX_PULL_UP);
+			}
+		}
+		break;
+
+	case PERIPH_ID_USB2:
+		if (config == FUNCMUX_USB2_ULPI) {
+			pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI);
+			pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI);
+			pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI);
+
+			pinmux_tristate_disable(PMUX_PINGRP_UAA);
+			pinmux_tristate_disable(PMUX_PINGRP_UAB);
+			pinmux_tristate_disable(PMUX_PINGRP_UDA);
+		}
+		break;
+
+	case PERIPH_ID_SPI1:
+		if (config == FUNCMUX_SPI1_GMC_GMD) {
+			pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
+			pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
+
+			pinmux_tristate_disable(PMUX_PINGRP_GMC);
+			pinmux_tristate_disable(PMUX_PINGRP_GMD);
+		}
+		break;
+
+	case PERIPH_ID_NDFLASH:
+		switch (config) {
+		case FUNCMUX_NDFLASH_ATC:
+			pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND);
+			pinmux_tristate_disable(PMUX_PINGRP_ATC);
+			break;
+		case FUNCMUX_NDFLASH_KBC_8_BIT:
+			pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
+			pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
+			pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
+			pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
+			pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
+
+			pinmux_tristate_disable(PMUX_PINGRP_KBCA);
+			pinmux_tristate_disable(PMUX_PINGRP_KBCC);
+			pinmux_tristate_disable(PMUX_PINGRP_KBCD);
+			pinmux_tristate_disable(PMUX_PINGRP_KBCE);
+			pinmux_tristate_disable(PMUX_PINGRP_KBCF);
+
+			bad_config = 0;
+			break;
+		}
+		break;
+	case PERIPH_ID_DISP1:
+		if (config == FUNCMUX_DEFAULT) {
+			int i;
+
+			for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) {
+				pinmux_set_func(i, PMUX_FUNC_DISPA);
+				pinmux_tristate_disable(i);
+				pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
+			}
+			pinmux_config_pingrp_table(disp1_default,
+						   ARRAY_SIZE(disp1_default));
+		}
+		break;
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	if (bad_config) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/pinmux.c b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/pinmux.c
new file mode 100644
index 000000000..e484f991b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/pinmux.c
@@ -0,0 +1,425 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Tegra20 pin multiplexing functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+/*
+ * This defines the order of the pin mux control bits in the registers. For
+ * some reason there is no correspendence between the tristate, pin mux and
+ * pullup/pulldown registers.
+ */
+enum pmux_ctlid {
+	/* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
+	MUXCTL_UAA,
+	MUXCTL_UAB,
+	MUXCTL_UAC,
+	MUXCTL_UAD,
+	MUXCTL_UDA,
+	MUXCTL_RESERVED5,
+	MUXCTL_ATE,
+	MUXCTL_RM,
+
+	MUXCTL_ATB,
+	MUXCTL_RESERVED9,
+	MUXCTL_ATD,
+	MUXCTL_ATC,
+	MUXCTL_ATA,
+	MUXCTL_KBCF,
+	MUXCTL_KBCE,
+	MUXCTL_SDMMC1,
+
+	/* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
+	MUXCTL_GMA,
+	MUXCTL_GMC,
+	MUXCTL_HDINT,
+	MUXCTL_SLXA,
+	MUXCTL_OWC,
+	MUXCTL_SLXC,
+	MUXCTL_SLXD,
+	MUXCTL_SLXK,
+
+	MUXCTL_UCA,
+	MUXCTL_UCB,
+	MUXCTL_DTA,
+	MUXCTL_DTB,
+	MUXCTL_RESERVED28,
+	MUXCTL_DTC,
+	MUXCTL_DTD,
+	MUXCTL_DTE,
+
+	/* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
+	MUXCTL_DDC,
+	MUXCTL_CDEV1,
+	MUXCTL_CDEV2,
+	MUXCTL_CSUS,
+	MUXCTL_I2CP,
+	MUXCTL_KBCA,
+	MUXCTL_KBCB,
+	MUXCTL_KBCC,
+
+	MUXCTL_IRTX,
+	MUXCTL_IRRX,
+	MUXCTL_DAP1,
+	MUXCTL_DAP2,
+	MUXCTL_DAP3,
+	MUXCTL_DAP4,
+	MUXCTL_GMB,
+	MUXCTL_GMD,
+
+	/* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
+	MUXCTL_GME,
+	MUXCTL_GPV,
+	MUXCTL_GPU,
+	MUXCTL_SPDO,
+	MUXCTL_SPDI,
+	MUXCTL_SDB,
+	MUXCTL_SDC,
+	MUXCTL_SDD,
+
+	MUXCTL_SPIH,
+	MUXCTL_SPIG,
+	MUXCTL_SPIF,
+	MUXCTL_SPIE,
+	MUXCTL_SPID,
+	MUXCTL_SPIC,
+	MUXCTL_SPIB,
+	MUXCTL_SPIA,
+
+	/* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
+	MUXCTL_LPW0,
+	MUXCTL_LPW1,
+	MUXCTL_LPW2,
+	MUXCTL_LSDI,
+	MUXCTL_LSDA,
+	MUXCTL_LSPI,
+	MUXCTL_LCSN,
+	MUXCTL_LDC,
+
+	MUXCTL_LSCK,
+	MUXCTL_LSC0,
+	MUXCTL_LSC1,
+	MUXCTL_LHS,
+	MUXCTL_LVS,
+	MUXCTL_LM0,
+	MUXCTL_LM1,
+	MUXCTL_LVP0,
+
+	/* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
+	MUXCTL_LD0,
+	MUXCTL_LD1,
+	MUXCTL_LD2,
+	MUXCTL_LD3,
+	MUXCTL_LD4,
+	MUXCTL_LD5,
+	MUXCTL_LD6,
+	MUXCTL_LD7,
+
+	MUXCTL_LD8,
+	MUXCTL_LD9,
+	MUXCTL_LD10,
+	MUXCTL_LD11,
+	MUXCTL_LD12,
+	MUXCTL_LD13,
+	MUXCTL_LD14,
+	MUXCTL_LD15,
+
+	/* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
+	MUXCTL_LD16,
+	MUXCTL_LD17,
+	MUXCTL_LHP1,
+	MUXCTL_LHP2,
+	MUXCTL_LVP1,
+	MUXCTL_LHP0,
+	MUXCTL_RESERVED102,
+	MUXCTL_LPP,
+
+	MUXCTL_LDI,
+	MUXCTL_PMC,
+	MUXCTL_CRTP,
+	MUXCTL_PTA,
+	MUXCTL_RESERVED108,
+	MUXCTL_KBCD,
+	MUXCTL_GPU7,
+	MUXCTL_DTF,
+
+	MUXCTL_NONE = -1,
+};
+
+/*
+ * And this defines the order of the pullup/pulldown controls which are again
+ * in a different order
+ */
+enum pmux_pullid {
+	/* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
+	PUCTL_ATA,
+	PUCTL_ATB,
+	PUCTL_ATC,
+	PUCTL_ATD,
+	PUCTL_ATE,
+	PUCTL_DAP1,
+	PUCTL_DAP2,
+	PUCTL_DAP3,
+
+	PUCTL_DAP4,
+	PUCTL_DTA,
+	PUCTL_DTB,
+	PUCTL_DTC,
+	PUCTL_DTD,
+	PUCTL_DTE,
+	PUCTL_DTF,
+	PUCTL_GPV,
+
+	/* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
+	PUCTL_RM,
+	PUCTL_I2CP,
+	PUCTL_PTA,
+	PUCTL_GPU7,
+	PUCTL_KBCA,
+	PUCTL_KBCB,
+	PUCTL_KBCC,
+	PUCTL_KBCD,
+
+	PUCTL_SPDI,
+	PUCTL_SPDO,
+	PUCTL_GPSLXAU,
+	PUCTL_CRTP,
+	PUCTL_SLXC,
+	PUCTL_SLXD,
+	PUCTL_SLXK,
+
+	/* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
+	PUCTL_CDEV1,
+	PUCTL_CDEV2,
+	PUCTL_SPIA,
+	PUCTL_SPIB,
+	PUCTL_SPIC,
+	PUCTL_SPID,
+	PUCTL_SPIE,
+	PUCTL_SPIF,
+
+	PUCTL_SPIG,
+	PUCTL_SPIH,
+	PUCTL_IRTX,
+	PUCTL_IRRX,
+	PUCTL_GME,
+	PUCTL_RESERVED45,
+	PUCTL_XM2D,
+	PUCTL_XM2C,
+
+	/* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
+	PUCTL_UAA,
+	PUCTL_UAB,
+	PUCTL_UAC,
+	PUCTL_UAD,
+	PUCTL_UCA,
+	PUCTL_UCB,
+	PUCTL_LD17,
+	PUCTL_LD19_18,
+
+	PUCTL_LD21_20,
+	PUCTL_LD23_22,
+	PUCTL_LS,
+	PUCTL_LC,
+	PUCTL_CSUS,
+	PUCTL_DDRC,
+	PUCTL_SDC,
+	PUCTL_SDD,
+
+	/* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
+	PUCTL_KBCF,
+	PUCTL_KBCE,
+	PUCTL_PMCA,
+	PUCTL_PMCB,
+	PUCTL_PMCC,
+	PUCTL_PMCD,
+	PUCTL_PMCE,
+	PUCTL_CK32,
+
+	PUCTL_UDA,
+	PUCTL_SDMMC1,
+	PUCTL_GMA,
+	PUCTL_GMB,
+	PUCTL_GMC,
+	PUCTL_GMD,
+	PUCTL_DDC,
+	PUCTL_OWC,
+
+	PUCTL_NONE = -1
+};
+
+/* Convenient macro for defining pin group properties */
+#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd)	\
+	{						\
+		.funcs = {				\
+			PMUX_FUNC_ ## f0,		\
+			PMUX_FUNC_ ## f1,		\
+			PMUX_FUNC_ ## f2,		\
+			PMUX_FUNC_ ## f3,		\
+		},					\
+		.ctl_id = mux,				\
+		.pull_id = pupd				\
+	}
+
+/* A normal pin group where the mux name and pull-up name match */
+#define PIN(pingrp, f0, f1, f2, f3) \
+	PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
+
+/* A pin group where the pull-up name doesn't have a 1-1 mapping */
+#define PINP(pingrp, f0, f1, f2, f3, pupd) \
+	PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
+
+/* A pin group number which is not used */
+#define PIN_RESERVED \
+	PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
+
+#define DRVGRP(drvgrp) \
+	PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
+
+static const struct pmux_pingrp_desc tegra20_pingroups[] = {
+	PIN(ATA,    IDE,       NAND,      GMI,       RSVD4),
+	PIN(ATB,    IDE,       NAND,      GMI,       SDIO4),
+	PIN(ATC,    IDE,       NAND,      GMI,       SDIO4),
+	PIN(ATD,    IDE,       NAND,      GMI,       SDIO4),
+	PIN(CDEV1,  OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC),
+	PIN(CDEV2,  OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4),
+	PIN(CSUS,   PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
+	PIN(DAP1,   DAP1,      RSVD2,     GMI,       SDIO2),
+
+	PIN(DAP2,   DAP2,      TWC,       RSVD3,     GMI),
+	PIN(DAP3,   DAP3,      RSVD2,     RSVD3,     RSVD4),
+	PIN(DAP4,   DAP4,      RSVD2,     GMI,       RSVD4),
+	PIN(DTA,    RSVD1,     SDIO2,     VI,        RSVD4),
+	PIN(DTB,    RSVD1,     RSVD2,     VI,        SPI1),
+	PIN(DTC,    RSVD1,     RSVD2,     VI,        RSVD4),
+	PIN(DTD,    RSVD1,     SDIO2,     VI,        RSVD4),
+	PIN(DTE,    RSVD1,     RSVD2,     VI,        SPI1),
+
+	PINP(GPU,   PWM,       UARTA,     GMI,       RSVD4,         GPSLXAU),
+	PIN(GPV,    PCIE,      RSVD2,     RSVD3,     RSVD4),
+	PIN(I2CP,   I2C,       RSVD2,     RSVD3,     RSVD4),
+	PIN(IRTX,   UARTA,     UARTB,     GMI,       SPI4),
+	PIN(IRRX,   UARTA,     UARTB,     GMI,       SPI4),
+	PIN(KBCB,   KBC,       NAND,      SDIO2,     MIO),
+	PIN(KBCA,   KBC,       NAND,      SDIO2,     EMC_TEST0_DLL),
+	PINP(PMC,   PWR_ON,    PWR_INTR,  RSVD3,     RSVD4,         NONE),
+
+	PIN(PTA,    I2C2,      HDMI,      GMI,       RSVD4),
+	PIN(RM,     I2C,       RSVD2,     RSVD3,     RSVD4),
+	PIN(KBCE,   KBC,       NAND,      OWR,       RSVD4),
+	PIN(KBCF,   KBC,       NAND,      TRACE,     MIO),
+	PIN(GMA,    UARTE,     SPI3,      GMI,       SDIO4),
+	PIN(GMC,    UARTD,     SPI4,      GMI,       SFLASH),
+	PIN(SDMMC1, SDIO1,     RSVD2,     UARTE,     UARTA),
+	PIN(OWC,    OWR,       RSVD2,     RSVD3,     RSVD4),
+
+	PIN(GME,    RSVD1,     DAP5,      GMI,       SDIO4),
+	PIN(SDC,    PWM,       TWC,       SDIO3,     SPI3),
+	PIN(SDD,    UARTA,     PWM,       SDIO3,     SPI3),
+	PIN_RESERVED,
+	PINP(SLXA,  PCIE,      SPI4,      SDIO3,     SPI2,          CRTP),
+	PIN(SLXC,   SPDIF,     SPI4,      SDIO3,     SPI2),
+	PIN(SLXD,   SPDIF,     SPI4,      SDIO3,     SPI2),
+	PIN(SLXK,   PCIE,      SPI4,      SDIO3,     SPI2),
+
+	PIN(SPDI,   SPDIF,     RSVD2,     I2C,       SDIO2),
+	PIN(SPDO,   SPDIF,     RSVD2,     I2C,       SDIO2),
+	PIN(SPIA,   SPI1,      SPI2,      SPI3,      GMI),
+	PIN(SPIB,   SPI1,      SPI2,      SPI3,      GMI),
+	PIN(SPIC,   SPI1,      SPI2,      SPI3,      GMI),
+	PIN(SPID,   SPI2,      SPI1,      SPI2_ALT,  GMI),
+	PIN(SPIE,   SPI2,      SPI1,      SPI2_ALT,  GMI),
+	PIN(SPIF,   SPI3,      SPI1,      SPI2,      RSVD4),
+
+	PIN(SPIG,   SPI3,      SPI2,      SPI2_ALT,  I2C),
+	PIN(SPIH,   SPI3,      SPI2,      SPI2_ALT,  I2C),
+	PIN(UAA,    SPI3,      MIPI_HS,   UARTA,     ULPI),
+	PIN(UAB,    SPI2,      MIPI_HS,   UARTA,     ULPI),
+	PIN(UAC,    OWR,       RSVD2,     RSVD3,     RSVD4),
+	PIN(UAD,    UARTB,     SPDIF,     UARTA,     SPI4),
+	PIN(UCA,    UARTC,     RSVD2,     GMI,       RSVD4),
+	PIN(UCB,    UARTC,     PWM,       GMI,       RSVD4),
+
+	PIN_RESERVED,
+	PIN(ATE,    IDE,       NAND,      GMI,       RSVD4),
+	PIN(KBCC,   KBC,       NAND,      TRACE,     EMC_TEST1_DLL),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN(GMB,    IDE,       NAND,      GMI,       GMI_INT),
+	PIN(GMD,    RSVD1,     NAND,      GMI,       SFLASH),
+	PIN(DDC,    I2C2,      RSVD2,     RSVD3,     RSVD4),
+
+	/* 64 */
+	PINP(LD0,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD1,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD2,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD3,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD4,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD5,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD6,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD7,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+
+	PINP(LD8,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD9,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD10,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD11,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD12,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD13,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD14,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD15,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+
+	PINP(LD16,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+	PINP(LD17,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD17),
+	PINP(LHP0,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD21_20),
+	PINP(LHP1,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD19_18),
+	PINP(LHP2,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD19_18),
+	PINP(LVP0,  DISPA,     DISPB,     RSVD3,     RSVD4,         LC),
+	PINP(LVP1,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD21_20),
+	PINP(HDINT, HDMI,      RSVD2,     RSVD3,     RSVD4,         LC),
+
+	PINP(LM0,   DISPA,     DISPB,     SPI3,      RSVD4,         LC),
+	PINP(LM1,   DISPA,     DISPB,     RSVD3,     CRT,           LC),
+	PINP(LVS,   DISPA,     DISPB,     XIO,       RSVD4,         LC),
+	PINP(LSC0,  DISPA,     DISPB,     XIO,       RSVD4,         LC),
+	PINP(LSC1,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
+	PINP(LSCK,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
+	PINP(LDC,   DISPA,     DISPB,     RSVD3,     RSVD4,         LS),
+	PINP(LCSN,  DISPA,     DISPB,     SPI3,      RSVD4,         LS),
+
+	/* 96 */
+	PINP(LSPI,  DISPA,     DISPB,     XIO,       HDMI,          LC),
+	PINP(LSDA,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
+	PINP(LSDI,  DISPA,     DISPB,     SPI3,      RSVD4,         LS),
+	PINP(LPW0,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
+	PINP(LPW1,  DISPA,     DISPB,     RSVD3,     RSVD4,         LS),
+	PINP(LPW2,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
+	PINP(LDI,   DISPA,     DISPB,     RSVD3,     RSVD4,         LD23_22),
+	PINP(LHS,   DISPA,     DISPB,     XIO,       RSVD4,         LC),
+
+	PINP(LPP,   DISPA,     DISPB,     RSVD3,     RSVD4,         LD23_22),
+	PIN_RESERVED,
+	PIN(KBCD,   KBC,       NAND,      SDIO2,     MIO),
+	PIN(GPU7,   RTCK,      RSVD2,     RSVD3,     RSVD4),
+	PIN(DTF,    I2C3,      RSVD2,     VI,        RSVD4),
+	PIN(UDA,    SPI1,      RSVD2,     UARTD,     ULPI),
+	PIN(CRTP,   CRT,       RSVD2,     RSVD3,     RSVD4),
+	PINP(SDB,   UARTA,     PWM,       SDIO3,     SPI2,          NONE),
+
+	/* these pin groups only have pullup and pull down control */
+	DRVGRP(CK32),
+	DRVGRP(DDRC),
+	DRVGRP(PMCA),
+	DRVGRP(PMCB),
+	DRVGRP(PMCC),
+	DRVGRP(PMCD),
+	DRVGRP(PMCE),
+	DRVGRP(XM2C),
+	DRVGRP(XM2D),
+};
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/pmu.c b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/pmu.c
new file mode 100644
index 000000000..c595f70e9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/pmu.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <tps6586x.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <asm/arch-tegra/sys_proto.h>
+
+#define VDD_CORE_NOMINAL_T25	0x17	/* 1.3v */
+#define VDD_CPU_NOMINAL_T25	0x10	/* 1.125v */
+
+#define VDD_CORE_NOMINAL_T20	0x16	/* 1.275v */
+#define VDD_CPU_NOMINAL_T20	0x0f	/* 1.1v */
+
+#define VDD_RELATION		0x02	/*  50mv */
+#define VDD_TRANSITION_STEP	0x06	/* 150mv */
+#define VDD_TRANSITION_RATE	0x06	/* 3.52mv/us */
+
+int pmu_set_nominal(void)
+{
+	int core, cpu, bus;
+
+	/* by default, the table has been filled with T25 settings */
+	switch (tegra_get_chip_sku()) {
+	case TEGRA_SOC_T20:
+		core = VDD_CORE_NOMINAL_T20;
+		cpu = VDD_CPU_NOMINAL_T20;
+		break;
+	case TEGRA_SOC_T25:
+		core = VDD_CORE_NOMINAL_T25;
+		cpu = VDD_CPU_NOMINAL_T25;
+		break;
+	default:
+		debug("%s: Unknown SKU id\n", __func__);
+		return -1;
+	}
+
+	bus = tegra_i2c_get_dvc_bus_num();
+	if (bus == -1) {
+		debug("%s: Cannot find DVC I2C bus\n", __func__);
+		return -1;
+	}
+	tps6586x_init(bus);
+	tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
+	return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
+				VDD_TRANSITION_RATE, VDD_RELATION);
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/warmboot.c b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/warmboot.c
new file mode 100644
index 000000000..5fdc4bbb5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/warmboot.c
@@ -0,0 +1,372 @@
+/*
+ * (C) Copyright 2010 - 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/emc.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sdram_param.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/apb_misc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/warmboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_TEGRA_CLOCK_SCALING
+#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
+#endif
+
+/*
+ * This is the place in SRAM where the SDRAM parameters are stored. There
+ * are 4 blocks, one for each RAM code
+ */
+#define SDRAM_PARAMS_BASE	(NV_PA_BASE_SRAM + 0x188)
+
+/* TODO: If we later add support for the Misc GP controller, refactor this */
+union xm2cfga_reg {
+	struct {
+		u32 reserved0:2;
+		u32 hsm_en:1;
+		u32 reserved1:2;
+		u32 preemp_en:1;
+		u32 vref_en:1;
+		u32 reserved2:5;
+		u32 cal_drvdn:5;
+		u32 reserved3:3;
+		u32 cal_drvup:5;
+		u32 reserved4:3;
+		u32 cal_drvdn_slwr:2;
+		u32 cal_drvup_slwf:2;
+	};
+	u32 word;
+};
+
+union xm2cfgd_reg {
+	struct {
+		u32 reserved0:2;
+		u32 hsm_en:1;
+		u32 schmt_en:1;
+		u32 lpmd:2;
+		u32 vref_en:1;
+		u32 reserved1:5;
+		u32 cal_drvdn:5;
+		u32 reserved2:3;
+		u32 cal_drvup:5;
+		u32 reserved3:3;
+		u32 cal_drvdn_slwr:2;
+		u32 cal_drvup_slwf:2;
+	};
+	u32 word;
+};
+
+/*
+ * TODO: This register is not documented in the TRM yet. We could move this
+ * into the EMC and give it a proper interface, but not while it is
+ * undocumented.
+ */
+union fbio_spare_reg {
+	struct {
+		u32 reserved:24;
+		u32 cfg_wb0:8;
+	};
+	u32 word;
+};
+
+/* We pack the resume information into these unions for later */
+union scratch2_reg {
+	struct {
+		u32 pllm_base_divm:5;
+		u32 pllm_base_divn:10;
+		u32 pllm_base_divp:3;
+		u32 pllm_misc_lfcon:4;
+		u32 pllm_misc_cpcon:4;
+		u32 gp_xm2cfga_padctrl_preemp:1;
+		u32 gp_xm2cfgd_padctrl_schmt:1;
+		u32 osc_ctrl_xobp:1;
+		u32 memory_type:3;
+	};
+	u32 word;
+};
+
+union scratch4_reg {
+	struct {
+		u32 emc_clock_divider:8;
+		u32 pllm_stable_time:8;
+		u32 pllx_stable_time:8;
+		u32 emc_fbio_spare_cfg_wb0:8;
+	};
+	u32 word;
+};
+
+union scratch24_reg {
+	struct {
+		u32 emc_auto_cal_wait:8;
+		u32 emc_pin_program_wait:8;
+		u32 warmboot_wait:8;
+		u32 reserved:8;
+	};
+	u32 word;
+};
+
+int warmboot_save_sdram_params(void)
+{
+	u32 ram_code;
+	struct sdram_params sdram;
+	struct apb_misc_pp_ctlr *apb_misc =
+				(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct apb_misc_gp_ctlr *gp =
+			(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+	struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
+	union scratch2_reg scratch2;
+	union scratch4_reg scratch4;
+	union scratch24_reg scratch24;
+	union xm2cfga_reg xm2cfga;
+	union xm2cfgd_reg xm2cfgd;
+	union fbio_spare_reg fbio_spare;
+
+	/* get ram code that is used as index to array sdram_params in BCT */
+	ram_code = (readl(&apb_misc->strapping_opt_a) >>
+			  STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
+	memcpy(&sdram,
+	       (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
+	       sizeof(sdram));
+
+	xm2cfga.word = readl(&gp->xm2cfga);
+	xm2cfgd.word = readl(&gp->xm2cfgd);
+
+	scratch2.word = 0;
+	scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
+
+	/* Get the memory PLL settings */
+	{
+		u32 divm, divn, divp, cpcon, lfcon;
+
+		if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
+					&cpcon, &lfcon))
+			return -1;
+		scratch2.pllm_base_divm = divm;
+		scratch2.pllm_base_divn = divn;
+		scratch2.pllm_base_divp = divp;
+		scratch2.pllm_misc_cpcon = cpcon;
+		scratch2.pllm_misc_lfcon = lfcon;
+	}
+
+	scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
+	scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
+	scratch2.memory_type = sdram.memory_type;
+	writel(scratch2.word, &pmc->pmc_scratch2);
+
+	/* collect data from various sources for pmc_scratch4 */
+	fbio_spare.word = readl(&emc->fbio_spare);
+	scratch4.word = 0;
+	scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
+	scratch4.emc_clock_divider = sdram.emc_clock_divider;
+	scratch4.pllm_stable_time = -1;
+	scratch4.pllx_stable_time = -1;
+	writel(scratch4.word, &pmc->pmc_scratch4);
+
+	/* collect various data from sdram for pmc_scratch24 */
+	scratch24.word = 0;
+	scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
+	scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
+	scratch24.warmboot_wait = sdram.warm_boot_wait;
+	writel(scratch24.word, &pmc->pmc_scratch24);
+
+	return 0;
+}
+
+static u32 get_major_version(void)
+{
+	u32 major_id;
+	struct apb_misc_gp_ctlr *gp =
+		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+
+	major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
+			HIDREV_MAJORPREV_SHIFT;
+	return major_id;
+}
+
+static int is_production_mode_fuse_set(struct fuse_regs *fuse)
+{
+	return readl(&fuse->production_mode);
+}
+
+static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse)
+{
+	return readl(&fuse->security_mode);
+}
+
+static int is_failure_analysis_mode(struct fuse_regs *fuse)
+{
+	return readl(&fuse->fa);
+}
+
+static int ap20_is_odm_production_mode(void)
+{
+	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
+
+	if (!is_failure_analysis_mode(fuse) &&
+	    is_odm_production_mode_fuse_set(fuse))
+		return 1;
+	else
+		return 0;
+}
+
+static int ap20_is_production_mode(void)
+{
+	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
+
+	if (get_major_version() == 0)
+		return 1;
+
+	if (!is_failure_analysis_mode(fuse) &&
+	    is_production_mode_fuse_set(fuse) &&
+	    !is_odm_production_mode_fuse_set(fuse))
+		return 1;
+	else
+		return 0;
+}
+
+static enum fuse_operating_mode fuse_get_operation_mode(void)
+{
+	u32 chip_id;
+	struct apb_misc_gp_ctlr *gp =
+		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+
+	chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
+			HIDREV_CHIPID_SHIFT;
+	if (chip_id == CHIPID_TEGRA20) {
+		if (ap20_is_odm_production_mode()) {
+			printf("!! odm_production_mode is not supported !!\n");
+			return MODE_UNDEFINED;
+		} else
+			if (ap20_is_production_mode())
+				return MODE_PRODUCTION;
+			else
+				return MODE_UNDEFINED;
+	}
+	return MODE_UNDEFINED;
+}
+
+static void determine_crypto_options(int *is_encrypted, int *is_signed,
+				     int *use_zero_key)
+{
+	switch (fuse_get_operation_mode()) {
+	case MODE_PRODUCTION:
+		*is_encrypted = 0;
+		*is_signed = 1;
+		*use_zero_key = 1;
+		break;
+	case MODE_UNDEFINED:
+	default:
+		*is_encrypted = 0;
+		*is_signed = 0;
+		*use_zero_key  = 0;
+		break;
+	}
+}
+
+static int sign_wb_code(u32 start, u32 length, int use_zero_key)
+{
+	int err;
+	u8 *source;		/* Pointer to source */
+	u8 *hash;
+
+	/* Calculate AES block parameters. */
+	source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
+	length -= offsetof(struct wb_header, random_aes_block);
+	hash = (u8 *)(start + offsetof(struct wb_header, hash));
+	err = sign_data_block(source, length, hash);
+
+	return err;
+}
+
+int warmboot_prepare_code(u32 seg_address, u32 seg_length)
+{
+	int err = 0;
+	u32 length;			/* length of the signed/encrypt code */
+	struct wb_header *dst_header;	/* Pointer to dest WB header */
+	int is_encrypted;		/* Segment is encrypted */
+	int is_signed;			/* Segment is signed */
+	int use_zero_key;		/* Use key of all zeros */
+
+	/* Determine crypto options. */
+	determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key);
+
+	/* Get the actual code limits. */
+	length = roundup(((u32)wb_end - (u32)wb_start), 16);
+
+	/*
+	 * The region specified by seg_address must be in SDRAM and must be
+	 * nonzero in length.
+	 */
+	if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
+		seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
+		err = -EFAULT;
+		goto fail;
+	}
+
+	/* Things must be 16-byte aligned. */
+	if ((seg_length & 0xF) || (seg_address & 0xF)) {
+		err = -EINVAL;
+		goto fail;
+	}
+
+	/* Will the code fit? (destination includes wb_header + wb code) */
+	if (seg_length < (length + sizeof(struct wb_header))) {
+		err = -EINVAL;
+		goto fail;
+	}
+
+	dst_header = (struct wb_header *)seg_address;
+	memset((char *)dst_header, 0, sizeof(struct wb_header));
+
+	/* Populate the random_aes_block as requested. */
+	{
+		u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
+		u32 *end = (u32 *)(((u32)aes_block) +
+				   sizeof(dst_header->random_aes_block));
+
+		do {
+			*aes_block++ = 0;
+		} while (aes_block < end);
+	}
+
+	/* Populate the header. */
+	dst_header->length_insecure = length + sizeof(struct wb_header);
+	dst_header->length_secure = length + sizeof(struct wb_header);
+	dst_header->destination = NV_WB_RUN_ADDRESS;
+	dst_header->entry_point = NV_WB_RUN_ADDRESS;
+	dst_header->code_length = length;
+
+	if (is_encrypted) {
+		printf("!!!! Encryption is not supported !!!!\n");
+		dst_header->length_insecure = 0;
+		err = -EACCES;
+		goto fail;
+	} else
+		/* copy the wb code directly following dst_header. */
+		memcpy((char *)(dst_header+1), (char *)wb_start, length);
+
+	if (is_signed)
+		err = sign_wb_code(seg_address, dst_header->length_insecure,
+				   use_zero_key);
+
+fail:
+	if (err)
+		printf("Warning: warmboot code copy failed (error=%d)\n", err);
+
+	return err;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/warmboot_avp.c b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/warmboot_avp.c
new file mode 100644
index 000000000..27ce5f480
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/warmboot_avp.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2010 - 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/apb_misc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/warmboot.h>
+#include "warmboot_avp.h"
+
+#define DEBUG_RESET_CORESIGHT
+
+void wb_start(void)
+{
+	struct apb_misc_pp_ctlr *apb_misc =
+				(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	union osc_ctrl_reg osc_ctrl;
+	union pllx_base_reg pllx_base;
+	union pllx_misc_reg pllx_misc;
+	union scratch3_reg scratch3;
+	u32 reg;
+
+	/* enable JTAG & TBE */
+	writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
+
+	/* Are we running where we're supposed to be? */
+	asm volatile (
+		"adr	%0, wb_start;"	/* reg: wb_start address */
+		: "=r"(reg)		/* output */
+					/* no input, no clobber list */
+	);
+
+	if (reg != NV_WB_RUN_ADDRESS)
+		goto do_reset;
+
+	/* Are we running with AVP? */
+	if (readl(NV_PA_PG_UP_BASE + PG_UP_TAG_0) != PG_UP_TAG_AVP)
+		goto do_reset;
+
+#ifdef DEBUG_RESET_CORESIGHT
+	/* Assert CoreSight reset */
+	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
+	reg |= SWR_CSITE_RST;
+	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
+#endif
+
+	/* TODO: Set the drive strength - maybe make this a board parameter? */
+	osc_ctrl.word = readl(&clkrst->crc_osc_ctrl);
+	osc_ctrl.xofs = 4;
+	osc_ctrl.xoe = 1;
+	writel(osc_ctrl.word, &clkrst->crc_osc_ctrl);
+
+	/* Power up the CPU complex if necessary */
+	if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) {
+		reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START;
+		writel(reg, &pmc->pmc_pwrgate_toggle);
+		while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU))
+			;
+	}
+
+	/* Remove the I/O clamps from the CPU power partition. */
+	reg = readl(&pmc->pmc_remove_clamping);
+	reg |= CPU_CLMP;
+	writel(reg, &pmc->pmc_remove_clamping);
+
+	reg = EVENT_ZERO_VAL_20 | EVENT_MSEC | EVENT_MODE_STOP;
+	writel(reg, &flow->halt_cop_events);
+
+	/* Assert CPU complex reset */
+	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);
+	reg |= CPU_RST;
+	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
+
+	/* Hold both CPUs in reset */
+	reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_CPURESET1 | CPU_CMPLX_DERESET0 |
+	      CPU_CMPLX_DERESET1 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DBGRESET1;
+	writel(reg, &clkrst->crc_cpu_cmplx_set);
+
+	/* Halt CPU1 at the flow controller for uni-processor configurations */
+	writel(EVENT_MODE_STOP, &flow->halt_cpu1_events);
+
+	/*
+	 * Set the CPU reset vector. SCRATCH41 contains the physical
+	 * address of the CPU-side restoration code.
+	 */
+	reg = readl(&pmc->pmc_scratch41);
+	writel(reg, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+	/* Select CPU complex clock source */
+	writel(CCLK_PLLP_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+
+	/* Start the CPU0 clock and stop the CPU1 clock */
+	reg = CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 | CPU_CMPLX_CPU0_CLK_STP_RUN |
+	      CPU_CMPLX_CPU1_CLK_STP_STOP;
+	writel(reg, &clkrst->crc_clk_cpu_cmplx);
+
+	/* Enable the CPU complex clock */
+	reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]);
+	reg |= CLK_ENB_CPU;
+	writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]);
+
+	/* Make sure the resets were held for at least 2 microseconds */
+	reg = readl(TIMER_USEC_CNTR);
+	while (readl(TIMER_USEC_CNTR) <= (reg + 2))
+		;
+
+#ifdef DEBUG_RESET_CORESIGHT
+	/*
+	 * De-assert CoreSight reset.
+	 * NOTE: We're leaving the CoreSight clock on the oscillator for
+	 *	now. It will be restored to its original clock source
+	 *	when the CPU-side restoration code runs.
+	 */
+	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
+	reg &= ~SWR_CSITE_RST;
+	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
+#endif
+
+	/* Unlock the CPU CoreSight interfaces */
+	reg = 0xC5ACCE55;
+	writel(reg, CSITE_CPU_DBG0_LAR);
+	writel(reg, CSITE_CPU_DBG1_LAR);
+
+	/*
+	 * Sample the microsecond timestamp again. This is the time we must
+	 * use when returning from LP0 for PLL stabilization delays.
+	 */
+	reg = readl(TIMER_USEC_CNTR);
+	writel(reg, &pmc->pmc_scratch1);
+
+	pllx_base.word = 0;
+	pllx_misc.word = 0;
+	scratch3.word = readl(&pmc->pmc_scratch3);
+
+	/* Get the OSC. For 19.2 MHz, use 19 to make the calculations easier */
+	reg = (readl(TIMER_USEC_CFG) & USEC_CFG_DIVISOR_MASK) + 1;
+
+	/*
+	 * According to the TRM, for 19.2MHz OSC, the USEC_DIVISOR is 0x5f, and
+	 * USEC_DIVIDEND is 0x04. So, if USEC_DIVISOR > 26, OSC is 19.2 MHz.
+	 *
+	 * reg is used to calculate the pllx freq, which is used to determine if
+	 * to set dccon or not.
+	 */
+	if (reg > 26)
+		reg = 19;
+
+	/* PLLX_BASE.PLLX_DIVM */
+	if (scratch3.pllx_base_divm == reg)
+		reg = 0;
+	else
+		reg = 1;
+
+	/* PLLX_BASE.PLLX_DIVN */
+	pllx_base.divn = scratch3.pllx_base_divn;
+	reg = scratch3.pllx_base_divn << reg;
+
+	/* PLLX_BASE.PLLX_DIVP */
+	pllx_base.divp = scratch3.pllx_base_divp;
+	reg = reg >> scratch3.pllx_base_divp;
+
+	pllx_base.bypass = 1;
+
+	/* PLLX_MISC_DCCON must be set for pllx frequency > 600 MHz. */
+	if (reg > 600)
+		pllx_misc.dccon = 1;
+
+	/* PLLX_MISC_LFCON */
+	pllx_misc.lfcon = scratch3.pllx_misc_lfcon;
+
+	/* PLLX_MISC_CPCON */
+	pllx_misc.cpcon = scratch3.pllx_misc_cpcon;
+
+	writel(pllx_misc.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_misc);
+	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+
+	pllx_base.enable = 1;
+	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+	pllx_base.bypass = 0;
+	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+
+	writel(0, flow->halt_cpu_events);
+
+	reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DERESET0;
+	writel(reg, &clkrst->crc_cpu_cmplx_clr);
+
+	reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
+	      PLLM_OUT1_RATIO_VAL_8;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);
+
+	reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
+	      SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |
+	      SCLK_SYS_STATE_IDLE;
+	writel(reg, &clkrst->crc_sclk_brst_pol);
+
+	/* avp_resume: no return after the write */
+	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);
+	reg &= ~CPU_RST;
+	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
+
+	/* avp_halt: */
+avp_halt:
+	reg = EVENT_MODE_STOP | EVENT_JTAG;
+	writel(reg, flow->halt_cop_events);
+	goto avp_halt;
+
+do_reset:
+	/*
+	 * Execution comes here if something goes wrong. The chip is reset and
+	 * a cold boot is performed.
+	 */
+	writel(SWR_TRIG_SYS_RST, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
+	goto do_reset;
+}
+
+/*
+ * wb_end() is a dummy function, and must be directly following wb_start(),
+ * and is used to calculate the size of wb_start().
+ */
+void wb_end(void)
+{
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/warmboot_avp.h b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/warmboot_avp.h
new file mode 100644
index 000000000..7b86acb15
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra20-common/warmboot_avp.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _WARMBOOT_AVP_H_
+#define _WARMBOOT_AVP_H_
+
+#define TEGRA_DEV_L			0
+#define TEGRA_DEV_H			1
+#define TEGRA_DEV_U			2
+
+#define SIMPLE_PLLX			(CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
+#define SIMPLE_PLLE			(CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE)
+
+#define TIMER_USEC_CNTR			(NV_PA_TMRUS_BASE + 0)
+#define TIMER_USEC_CFG			(NV_PA_TMRUS_BASE + 4)
+
+#define USEC_CFG_DIVISOR_MASK		0xffff
+
+#define CONFIG_CTL_TBE			(1 << 7)
+#define CONFIG_CTL_JTAG			(1 << 6)
+
+#define CPU_RST				(1 << 0)
+#define CLK_ENB_CPU			(1 << 0)
+#define SWR_TRIG_SYS_RST		(1 << 2)
+#define SWR_CSITE_RST			(1 << 9)
+
+#define PWRGATE_STATUS_CPU		(1 << 0)
+#define PWRGATE_TOGGLE_PARTID_CPU	(0 << 0)
+#define PWRGATE_TOGGLE_START		(1 << 8)
+
+#define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4	(3 << 0)
+#define CPU_CMPLX_CPU0_CLK_STP_STOP	(1 << 8)
+#define CPU_CMPLX_CPU0_CLK_STP_RUN	(0 << 8)
+#define CPU_CMPLX_CPU1_CLK_STP_STOP	(1 << 9)
+#define CPU_CMPLX_CPU1_CLK_STP_RUN	(0 << 9)
+
+#define CPU_CMPLX_CPURESET0		(1 << 0)
+#define CPU_CMPLX_CPURESET1		(1 << 1)
+#define CPU_CMPLX_DERESET0		(1 << 4)
+#define CPU_CMPLX_DERESET1		(1 << 5)
+#define CPU_CMPLX_DBGRESET0		(1 << 12)
+#define CPU_CMPLX_DBGRESET1		(1 << 13)
+
+#define PLLM_OUT1_RSTN_RESET_DISABLE	(1 << 0)
+#define PLLM_OUT1_CLKEN_ENABLE		(1 << 1)
+#define PLLM_OUT1_RATIO_VAL_8		(8 << 8)
+
+#define SCLK_SYS_STATE_IDLE		(1 << 28)
+#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1	(7 << 12)
+#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1	(7 << 8)
+#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1	(7 << 4)
+#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1	(7 << 0)
+
+#define EVENT_ZERO_VAL_20		(20 << 0)
+#define EVENT_MSEC			(1 << 24)
+#define EVENT_JTAG			(1 << 28)
+#define EVENT_MODE_STOP			(2 << 29)
+
+#define CCLK_PLLP_BURST_POLICY		0x20004444
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/Makefile b/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/Makefile
new file mode 100644
index 000000000..d2d616e8a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/Makefile
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+obj-y	+= clock.o funcmux.o pinmux.o
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/clock.c b/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/clock.c
new file mode 100644
index 000000000..80ba2d8c1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/clock.c
@@ -0,0 +1,589 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra30 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
+	CLOCK_TYPE_MCPA,	/* and so on */
+	CLOCK_TYPE_MCPT,
+	CLOCK_TYPE_PCM,
+	CLOCK_TYPE_PCMT,
+	CLOCK_TYPE_PCMT16,
+	CLOCK_TYPE_PDCT,
+	CLOCK_TYPE_ACPT,
+	CLOCK_TYPE_ASPTE,
+	CLOCK_TYPE_PMDACD2T,
+	CLOCK_TYPE_PCST,
+
+	CLOCK_TYPE_COUNT,
+	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
+};
+
+enum {
+	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ *  The extra column in each clock source array is used to store the mask
+ *  bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+	{ CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),  CLK(DISPLAY),   CLK(CGENERAL),  CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),   CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),   CLK(SFROM32KHZ),	CLK(PERIPH),   CLK(OSC),
+		CLK(EPCI),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),  CLK(MEMORY),    CLK(DISPLAY),   CLK(AUDIO),
+		CLK(CGENERAL),  CLK(DISPLAY2),  CLK(OSC),       CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ), CLK(OSC),
+		CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+		MASK_BITS_31_28}
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+	/* 0x00 */
+	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S2,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_IN,  CLOCK_TYPE_PCM),
+	TYPE(PERIPHC_PWM,       CLOCK_TYPE_PCST),  /* only PWM uses b29:28 */
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC2,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC3,      CLOCK_TYPE_PCMT),
+
+	/* 0x08 */
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C1,      CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_DVC_I2C,   CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC1,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PMDACD2T),
+
+	/* 0x10 */
+	TYPE(PERIPHC_CVE,       CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC1,    CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_G3D,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_G2D,	CLOCK_TYPE_MCPA),
+
+	/* 0x18 */
+	TYPE(PERIPHC_NDFLASH,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VFIR,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_EPP,       CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MPE,       CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MIPI,      CLOCK_TYPE_PCMT),       /* MIPI base-band HSI */
+	TYPE(PERIPHC_UART1,     CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART2,     CLOCK_TYPE_PCMT),
+
+	/* 0x20 */
+	TYPE(PERIPHC_HOST1X,    CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVO,       CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_HDMI,      CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVDAC,     CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_I2C2,      CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),
+
+	/* 0x28 */
+	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC4,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C3,      CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SDMMC3,    CLOCK_TYPE_PCMT),
+
+	/* 0x30 */
+	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_OWR,       CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NOR,       CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_CSITE,     CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2S0,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+
+	/* 0x38h */	     /* Jumps to reg offset 0x3B0h - new for T30 */
+	TYPE(PERIPHC_G3D2,      CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MSELECT,   CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_TSENSOR,   CLOCK_TYPE_PCST),       /* s/b PCTS */
+	TYPE(PERIPHC_I2S3,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S4,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2C4,      CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SBC5,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC6,      CLOCK_TYPE_PCMT),
+
+	/* 0x40 */
+	TYPE(PERIPHC_AUDIO,     CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DAM0,      CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM1,      CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM2,      CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_ACTMON,    CLOCK_TYPE_PCST),       /* MASK 31:30 */
+	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+	/* 0x48 */
+	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2CSLOW,   CLOCK_TYPE_PCST),       /* MASK 31:30 */
+	TYPE(PERIPHC_SYS,       CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SPEEDO,    CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+
+	/* 0x50 */
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SATAOOB,   CLOCK_TYPE_PCMT),       /* offset 0x420h */
+	TYPE(PERIPHC_SATA,      CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_HDA,       CLOCK_TYPE_PCMT),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
+ *	SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+	/* Low word: 31:0 */
+	NONE(CPU),
+	NONE(COP),
+	NONE(TRIGSYS),
+	NONE(RESERVED3),
+	NONE(RESERVED4),
+	NONE(TMR),
+	PERIPHC_UART1,
+	PERIPHC_UART2,  /* and vfir 0x68 */
+
+	/* 8 */
+	NONE(GPIO),
+	PERIPHC_SDMMC2,
+	NONE(SPDIF),	    /* 0x08 and 0x0c, unclear which to use */
+	PERIPHC_I2S1,
+	PERIPHC_I2C1,
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC4,
+
+	/* 16 */
+	NONE(RESERVED16),
+	PERIPHC_PWM,
+	PERIPHC_I2S2,
+	PERIPHC_EPP,
+	PERIPHC_VI,
+	PERIPHC_G2D,
+	NONE(USBD),
+	NONE(ISP),
+
+	/* 24 */
+	PERIPHC_G3D,
+	NONE(RESERVED25),
+	PERIPHC_DISP2,
+	PERIPHC_DISP1,
+	PERIPHC_HOST1X,
+	NONE(VCP),
+	PERIPHC_I2S0,
+	NONE(CACHE2),
+
+	/* Middle word: 63:32 */
+	NONE(MEM),
+	NONE(AHBDMA),
+	NONE(APBDMA),
+	NONE(RESERVED35),
+	NONE(RESERVED36),
+	NONE(STAT_MON),
+	NONE(RESERVED38),
+	NONE(RESERVED39),
+
+	/* 40 */
+	NONE(KFUSE),
+	PERIPHC_SBC1,
+	PERIPHC_NOR,
+	NONE(RESERVED43),
+	PERIPHC_SBC2,
+	NONE(RESERVED45),
+	PERIPHC_SBC3,
+	PERIPHC_DVC_I2C,
+
+	/* 48 */
+	NONE(DSI),
+	PERIPHC_TVO,    /* also CVE 0x40 */
+	PERIPHC_MIPI,
+	PERIPHC_HDMI,
+	NONE(CSI),
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_UART3,
+
+	/* 56 */
+	NONE(RESERVED56),
+	PERIPHC_EMC,
+	NONE(USB2),
+	NONE(USB3),
+	PERIPHC_MPE,
+	PERIPHC_VDE,
+	NONE(BSEA),
+	NONE(BSEV),
+
+	/* Upper word 95:64 */
+	PERIPHC_SPEEDO,
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_I2C3,
+	PERIPHC_SBC4,
+	PERIPHC_SDMMC3,
+	NONE(PCIE),
+	PERIPHC_OWR,
+
+	/* 72 */
+	NONE(AFI),
+	PERIPHC_CSITE,
+	NONE(PCIEXCLK),
+	NONE(AVPUCQ),
+	NONE(RESERVED76),
+	NONE(RESERVED77),
+	NONE(RESERVED78),
+	NONE(DTV),
+
+	/* 80 */
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	NONE(DSIB),
+	NONE(RESERVED83),
+	NONE(IRAMA),
+	NONE(IRAMB),
+	NONE(IRAMC),
+	NONE(IRAMD),
+
+	/* 88 */
+	NONE(CRAM2),
+	NONE(RESERVED89),
+	NONE(MDOUBLER),
+	NONE(RESERVED91),
+	NONE(SUSOUT),
+	NONE(RESERVED93),
+	NONE(RESERVED94),
+	NONE(RESERVED95),
+
+	/* V word: 31:0 */
+	NONE(CPUG),
+	NONE(CPULP),
+	PERIPHC_G3D2,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+
+	/* 08 */
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+	PERIPHC_AUDIO,
+	NONE(APBIF),
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+
+	/* 16 */
+	NONE(ATOMICS),
+	NONE(RESERVED17),
+	NONE(RESERVED18),
+	NONE(RESERVED19),
+	NONE(RESERVED20),
+	NONE(RESERVED21),
+	NONE(RESERVED22),
+	PERIPHC_ACTMON,
+
+	/* 24 */
+	NONE(RESERVED24),
+	NONE(RESERVED25),
+	NONE(RESERVED26),
+	NONE(RESERVED27),
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+	NONE(RESERVED30),
+	NONE(RESERVED31),
+
+	/* W word: 31:0 */
+	NONE(HDA2HDMICODEC),
+	NONE(SATACOLD),
+	NONE(RESERVED0_PCIERX0),
+	NONE(RESERVED1_PCIERX1),
+	NONE(RESERVED2_PCIERX2),
+	NONE(RESERVED3_PCIERX3),
+	NONE(RESERVED4_PCIERX4),
+	NONE(RESERVED5_PCIERX5),
+
+	/* 40 */
+	NONE(CEC),
+	NONE(RESERVED6_PCIE2),
+	NONE(RESERVED7_EMC),
+	NONE(RESERVED8_HDMI),
+	NONE(RESERVED9_SATA),
+	NONE(RESERVED10_MIPI),
+	NONE(EX_RESERVED46),
+	NONE(EX_RESERVED47),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that T30 supports 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+	if (reg & 1)			/* one of the newer freqs */
+		printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+	return reg >> 2;	/* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	enum periphc_internal_id internal_id;
+
+	/* Coresight is a special case */
+	if (periph_id == PERIPH_ID_CSI)
+		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(internal_id != -1);
+	if (internal_id >= PERIPHC_VW_FIRST) {
+		internal_id -= PERIPHC_VW_FIRST;
+		return &clkrst->crc_clk_src_vw[internal_id];
+	} else
+		return &clkrst->crc_clk_src[internal_id];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id	peripheral to start
+ * @param source	PLL id of required parent clock
+ * @param mux_bits	Set to number of bits in mux register: 2 or 4
+ * @param divider_bits  Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+	enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+	enum clock_type_id type;
+	enum periphc_internal_id internal_id;
+	int mux;
+
+	assert(clock_periph_id_isvalid(periph_id));
+
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(periphc_internal_id_isvalid(internal_id));
+
+	type = clock_periph_type[internal_id];
+	assert(clock_type_id_isvalid(type));
+
+	*mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+	if (type == CLOCK_TYPE_PCMT16)
+		*divider_bits = 16;
+	else
+		*divider_bits = 8;
+
+	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+		if (clock_source[type][mux] == parent)
+			return mux;
+
+	/* if we get here, either us or the caller has made a mistake */
+	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+		parent);
+	return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *clk;
+	u32 reg;
+
+	/* Enable/disable the clock to this peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+	else
+		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+	reg = readl(clk);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *reset;
+	u32 reg;
+
+	/* Enable/disable reset to the peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if (periph_id < PERIPH_ID_VW_FIRST)
+		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+	else
+		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+	reg = readl(reset);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id	Clock ID according to tegra30 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+	if (clk_id > PERIPH_ID_COUNT)
+		return PERIPH_ID_NONE;
+
+	switch (clk_id) {
+	case PERIPH_ID_RESERVED3:
+	case PERIPH_ID_RESERVED4:
+	case PERIPH_ID_RESERVED16:
+	case PERIPH_ID_RESERVED24:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED43:
+	case PERIPH_ID_RESERVED45:
+	case PERIPH_ID_RESERVED56:
+	case PERIPH_ID_RESERVED76:
+	case PERIPH_ID_RESERVED77:
+	case PERIPH_ID_RESERVED78:
+	case PERIPH_ID_RESERVED83:
+	case PERIPH_ID_RESERVED89:
+	case PERIPH_ID_RESERVED91:
+	case PERIPH_ID_RESERVED93:
+	case PERIPH_ID_RESERVED94:
+	case PERIPH_ID_RESERVED95:
+		return PERIPH_ID_NONE;
+	default:
+		return clk_id;
+	}
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+	tegra30_set_up_pllp();
+}
+
+void arch_timer_init(void)
+{
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/funcmux.c b/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/funcmux.c
new file mode 100644
index 000000000..409335ce1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/funcmux.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+	int bad_config = config != FUNCMUX_DEFAULT;
+
+	switch (id) {
+	case PERIPH_ID_UART1:
+		switch (config) {
+		case FUNCMUX_UART1_ULPI:
+			pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1,
+					PMUX_FUNC_UARTA);
+			pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2,
+					PMUX_FUNC_UARTA);
+			pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3,
+					PMUX_FUNC_UARTA);
+			pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4,
+					PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1);
+			pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2);
+			pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3);
+			pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4);
+			break;
+		}
+		break;
+
+	/* Add other periph IDs here as needed */
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	if (bad_config) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/pinmux.c b/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/pinmux.c
new file mode 100644
index 000000000..7eb05743b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/tegra30-common/pinmux.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+#define PIN(pin, f0, f1, f2, f3)	\
+	{				\
+		.funcs = {		\
+			PMUX_FUNC_##f0,	\
+			PMUX_FUNC_##f1,	\
+			PMUX_FUNC_##f2,	\
+			PMUX_FUNC_##f3,	\
+		},			\
+	}
+
+#define PIN_RESERVED {}
+
+static const struct pmux_pingrp_desc tegra30_pingroups[] = {
+	/*  pin,                  f0,           f1,       f2,       f3 */
+	/* Offset 0x3000 */
+	PIN(ULPI_DATA0_PO1,       SPI3,         HSI,      UARTA,    ULPI),
+	PIN(ULPI_DATA1_PO2,       SPI3,         HSI,      UARTA,    ULPI),
+	PIN(ULPI_DATA2_PO3,       SPI3,         HSI,      UARTA,    ULPI),
+	PIN(ULPI_DATA3_PO4,       SPI3,         HSI,      UARTA,    ULPI),
+	PIN(ULPI_DATA4_PO5,       SPI2,         HSI,      UARTA,    ULPI),
+	PIN(ULPI_DATA5_PO6,       SPI2,         HSI,      UARTA,    ULPI),
+	PIN(ULPI_DATA6_PO7,       SPI2,         HSI,      UARTA,    ULPI),
+	PIN(ULPI_DATA7_PO0,       SPI2,         HSI,      UARTA,    ULPI),
+	PIN(ULPI_CLK_PY0,         SPI1,         RSVD2,    UARTD,    ULPI),
+	PIN(ULPI_DIR_PY1,         SPI1,         RSVD2,    UARTD,    ULPI),
+	PIN(ULPI_NXT_PY2,         SPI1,         RSVD2,    UARTD,    ULPI),
+	PIN(ULPI_STP_PY3,         SPI1,         RSVD2,    UARTD,    ULPI),
+	PIN(DAP3_FS_PP0,          I2S2,         RSVD2,    DISPLAYA, DISPLAYB),
+	PIN(DAP3_DIN_PP1,         I2S2,         RSVD2,    DISPLAYA, DISPLAYB),
+	PIN(DAP3_DOUT_PP2,        I2S2,         RSVD2,    DISPLAYA, DISPLAYB),
+	PIN(DAP3_SCLK_PP3,        I2S2,         RSVD2,    DISPLAYA, DISPLAYB),
+	PIN(PV0,                  RSVD1,        RSVD2,    RSVD3,    RSVD4),
+	PIN(PV1,                  RSVD1,        RSVD2,    RSVD3,    RSVD4),
+	PIN(SDMMC1_CLK_PZ0,       SDMMC1,       RSVD2,    RSVD3,    UARTA),
+	PIN(SDMMC1_CMD_PZ1,       SDMMC1,       RSVD2,    RSVD3,    UARTA),
+	PIN(SDMMC1_DAT3_PY4,      SDMMC1,       RSVD2,    UARTE,    UARTA),
+	PIN(SDMMC1_DAT2_PY5,      SDMMC1,       RSVD2,    UARTE,    UARTA),
+	PIN(SDMMC1_DAT1_PY6,      SDMMC1,       RSVD2,    UARTE,    UARTA),
+	PIN(SDMMC1_DAT0_PY7,      SDMMC1,       RSVD2,    UARTE,    UARTA),
+	PIN(PV2,                  OWR,          RSVD2,    RSVD3,    RSVD4),
+	PIN(PV3,                  CLK_12M_OUT,  RSVD2,    RSVD3,    RSVD4),
+	PIN(CLK2_OUT_PW5,         EXTPERIPH2,   RSVD2,    RSVD3,    RSVD4),
+	PIN(CLK2_REQ_PCC5,        DAP,          RSVD2,    RSVD3,    RSVD4),
+	PIN(LCD_PWR1_PC1,         DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_PWR2_PC6,         DISPLAYA,     DISPLAYB, SPI5,     HDCP),
+	PIN(LCD_SDIN_PZ2,         DISPLAYA,     DISPLAYB, SPI5,     RSVD4),
+	PIN(LCD_SDOUT_PN5,        DISPLAYA,     DISPLAYB, SPI5,     HDCP),
+	PIN(LCD_WR_N_PZ3,         DISPLAYA,     DISPLAYB, SPI5,     HDCP),
+	PIN(LCD_CS0_N_PN4,        DISPLAYA,     DISPLAYB, SPI5,     RSVD4),
+	PIN(LCD_DC0_PN6,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_SCK_PZ4,          DISPLAYA,     DISPLAYB, SPI5,     HDCP),
+	PIN(LCD_PWR0_PB2,         DISPLAYA,     DISPLAYB, SPI5,     HDCP),
+	PIN(LCD_PCLK_PB3,         DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_DE_PJ1,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_HSYNC_PJ3,        DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_VSYNC_PJ4,        DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D0_PE0,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D1_PE1,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D2_PE2,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D3_PE3,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D4_PE4,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D5_PE5,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D6_PE6,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D7_PE7,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D8_PF0,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D9_PF1,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D10_PF2,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D11_PF3,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D12_PF4,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D13_PF5,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D14_PF6,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D15_PF7,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D16_PM0,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D17_PM1,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D18_PM2,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D19_PM3,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D20_PM4,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D21_PM5,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D22_PM6,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_D23_PM7,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_CS1_N_PW0,        DISPLAYA,     DISPLAYB, SPI5,     RSVD4),
+	PIN(LCD_M1_PW1,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(LCD_DC1_PD2,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+	PIN(HDMI_INT_PN7,         HDMI,         RSVD2,    RSVD3,    RSVD4),
+	PIN(DDC_SCL_PV4,          I2C4,         RSVD2,    RSVD3,    RSVD4),
+	PIN(DDC_SDA_PV5,          I2C4,         RSVD2,    RSVD3,    RSVD4),
+	PIN(CRT_HSYNC_PV6,        CRT,          RSVD2,    RSVD3,    RSVD4),
+	PIN(CRT_VSYNC_PV7,        CRT,          RSVD2,    RSVD3,    RSVD4),
+	PIN(VI_D0_PT4,            DDR,          RSVD2,    VI,       RSVD4),
+	PIN(VI_D1_PD5,            DDR,          SDMMC2,   VI,       RSVD4),
+	PIN(VI_D2_PL0,            DDR,          SDMMC2,   VI,       RSVD4),
+	PIN(VI_D3_PL1,            DDR,          SDMMC2,   VI,       RSVD4),
+	PIN(VI_D4_PL2,            DDR,          SDMMC2,   VI,       RSVD4),
+	PIN(VI_D5_PL3,            DDR,          SDMMC2,   VI,       RSVD4),
+	PIN(VI_D6_PL4,            DDR,          SDMMC2,   VI,       RSVD4),
+	PIN(VI_D7_PL5,            DDR,          SDMMC2,   VI,       RSVD4),
+	PIN(VI_D8_PL6,            DDR,          SDMMC2,   VI,       RSVD4),
+	PIN(VI_D9_PL7,            DDR,          SDMMC2,   VI,       RSVD4),
+	PIN(VI_D10_PT2,           DDR,          RSVD2,    VI,       RSVD4),
+	PIN(VI_D11_PT3,           DDR,          RSVD2,    VI,       RSVD4),
+	PIN(VI_PCLK_PT0,          RSVD1,        SDMMC2,   VI,       RSVD4),
+	PIN(VI_MCLK_PT1,          VI,           VI_ALT1,  VI_ALT2,  VI_ALT3),
+	PIN(VI_VSYNC_PD6,         DDR,          RSVD2,    VI,       RSVD4),
+	PIN(VI_HSYNC_PD7,         DDR,          RSVD2,    VI,       RSVD4),
+	PIN(UART2_RXD_PC3,        UARTB,        SPDIF,    UARTA,    SPI4),
+	PIN(UART2_TXD_PC2,        UARTB,        SPDIF,    UARTA,    SPI4),
+	PIN(UART2_RTS_N_PJ6,      UARTA,        UARTB,    GMI,      SPI4),
+	PIN(UART2_CTS_N_PJ5,      UARTA,        UARTB,    GMI,      SPI4),
+	PIN(UART3_TXD_PW6,        UARTC,        RSVD2,    GMI,      RSVD4),
+	PIN(UART3_RXD_PW7,        UARTC,        RSVD2,    GMI,      RSVD4),
+	PIN(UART3_CTS_N_PA1,      UARTC,        RSVD2,    GMI,      RSVD4),
+	PIN(UART3_RTS_N_PC0,      UARTC,        PWM0,     GMI,      RSVD4),
+	PIN(PU0,                  OWR,          UARTA,    GMI,      RSVD4),
+	PIN(PU1,                  RSVD1,        UARTA,    GMI,      RSVD4),
+	PIN(PU2,                  RSVD1,        UARTA,    GMI,      RSVD4),
+	PIN(PU3,                  PWM0,         UARTA,    GMI,      RSVD4),
+	PIN(PU4,                  PWM1,         UARTA,    GMI,      RSVD4),
+	PIN(PU5,                  PWM2,         UARTA,    GMI,      RSVD4),
+	PIN(PU6,                  PWM3,         UARTA,    GMI,      RSVD4),
+	PIN(GEN1_I2C_SDA_PC5,     I2C1,         RSVD2,    RSVD3,    RSVD4),
+	PIN(GEN1_I2C_SCL_PC4,     I2C1,         RSVD2,    RSVD3,    RSVD4),
+	PIN(DAP4_FS_PP4,          I2S3,         RSVD2,    GMI,      RSVD4),
+	PIN(DAP4_DIN_PP5,         I2S3,         RSVD2,    GMI,      RSVD4),
+	PIN(DAP4_DOUT_PP6,        I2S3,         RSVD2,    GMI,      RSVD4),
+	PIN(DAP4_SCLK_PP7,        I2S3,         RSVD2,    GMI,      RSVD4),
+	PIN(CLK3_OUT_PEE0,        EXTPERIPH3,   RSVD2,    RSVD3,    RSVD4),
+	PIN(CLK3_REQ_PEE1,        DEV3,         RSVD2,    RSVD3,    RSVD4),
+	PIN(GMI_WP_N_PC7,         RSVD1,        NAND,     GMI,      GMI_ALT),
+	PIN(GMI_IORDY_PI5,        RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_WAIT_PI7,         RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_ADV_N_PK0,        RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_CLK_PK1,          RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_CS0_N_PJ0,        RSVD1,        NAND,     GMI,      DTV),
+	PIN(GMI_CS1_N_PJ2,        RSVD1,        NAND,     GMI,      DTV),
+	PIN(GMI_CS2_N_PK3,        RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_CS3_N_PK4,        RSVD1,        NAND,     GMI,      GMI_ALT),
+	PIN(GMI_CS4_N_PK2,        RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_CS6_N_PI3,        NAND,         NAND_ALT, GMI,      SATA),
+	PIN(GMI_CS7_N_PI6,        NAND,         NAND_ALT, GMI,      GMI_ALT),
+	PIN(GMI_AD0_PG0,          RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD1_PG1,          RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD2_PG2,          RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD3_PG3,          RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD4_PG4,          RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD5_PG5,          RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD6_PG6,          RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD7_PG7,          RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD8_PH0,          PWM0,         NAND,     GMI,      RSVD4),
+	PIN(GMI_AD9_PH1,          PWM1,         NAND,     GMI,      RSVD4),
+	PIN(GMI_AD10_PH2,         PWM2,         NAND,     GMI,      RSVD4),
+	PIN(GMI_AD11_PH3,         PWM3,         NAND,     GMI,      RSVD4),
+	PIN(GMI_AD12_PH4,         RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD13_PH5,         RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD14_PH6,         RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_AD15_PH7,         RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_A16_PJ7,          UARTD,        SPI4,     GMI,      GMI_ALT),
+	PIN(GMI_A17_PB0,          UARTD,        SPI4,     GMI,      DTV),
+	PIN(GMI_A18_PB1,          UARTD,        SPI4,     GMI,      DTV),
+	PIN(GMI_A19_PK7,          UARTD,        SPI4,     GMI,      RSVD4),
+	PIN(GMI_WR_N_PI0,         RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_OE_N_PI1,         RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_DQS_PI2,          RSVD1,        NAND,     GMI,      RSVD4),
+	PIN(GMI_RST_N_PI4,        NAND,         NAND_ALT, GMI,      RSVD4),
+	PIN(GEN2_I2C_SCL_PT5,     I2C2,         HDCP,     GMI,      RSVD4),
+	PIN(GEN2_I2C_SDA_PT6,     I2C2,         HDCP,     GMI,      RSVD4),
+	PIN(SDMMC4_CLK_PCC4,      INVALID,      NAND,     GMI,      SDMMC4),
+	PIN(SDMMC4_CMD_PT7,       I2C3,         NAND,     GMI,      SDMMC4),
+	PIN(SDMMC4_DAT0_PAA0,     UARTE,        SPI3,     GMI,      SDMMC4),
+	PIN(SDMMC4_DAT1_PAA1,     UARTE,        SPI3,     GMI,      SDMMC4),
+	PIN(SDMMC4_DAT2_PAA2,     UARTE,        SPI3,     GMI,      SDMMC4),
+	PIN(SDMMC4_DAT3_PAA3,     UARTE,        SPI3,     GMI,      SDMMC4),
+	PIN(SDMMC4_DAT4_PAA4,     I2C3,         I2S4,     GMI,      SDMMC4),
+	PIN(SDMMC4_DAT5_PAA5,     VGP3,         I2S4,     GMI,      SDMMC4),
+	PIN(SDMMC4_DAT6_PAA6,     VGP4,         I2S4,     GMI,      SDMMC4),
+	PIN(SDMMC4_DAT7_PAA7,     VGP5,         I2S4,     GMI,      SDMMC4),
+	PIN(SDMMC4_RST_N_PCC3,    VGP6,         RSVD2,    RSVD3,    SDMMC4),
+	PIN(CAM_MCLK_PCC0,        VI,           VI_ALT1,  VI_ALT3,  SDMMC4),
+	PIN(PCC1,                 I2S4,         RSVD2,    RSVD3,    SDMMC4),
+	PIN(PBB0,                 I2S4,         RSVD2,    RSVD3,    SDMMC4),
+	PIN(CAM_I2C_SCL_PBB1,     VGP1,         I2C3,     RSVD3,    SDMMC4),
+	PIN(CAM_I2C_SDA_PBB2,     VGP2,         I2C3,     RSVD3,    SDMMC4),
+	PIN(PBB3,                 VGP3,         DISPLAYA, DISPLAYB, SDMMC4),
+	PIN(PBB4,                 VGP4,         DISPLAYA, DISPLAYB, SDMMC4),
+	PIN(PBB5,                 VGP5,         DISPLAYA, DISPLAYB, SDMMC4),
+	PIN(PBB6,                 VGP6,         DISPLAYA, DISPLAYB, SDMMC4),
+	PIN(PBB7,                 I2S4,         RSVD2,    RSVD3,    SDMMC4),
+	PIN(PCC2,                 I2S4,         RSVD2,    RSVD3,    RSVD4),
+	PIN(JTAG_RTCK_PU7,        RTCK,         RSVD2,    RSVD3,    RSVD4),
+	PIN(PWR_I2C_SCL_PZ6,      I2CPWR,       RSVD2,    RSVD3,    RSVD4),
+	PIN(PWR_I2C_SDA_PZ7,      I2CPWR,       RSVD2,    RSVD3,    RSVD4),
+	PIN(KB_ROW0_PR0,          KBC,          NAND,     RSVD3,    RSVD4),
+	PIN(KB_ROW1_PR1,          KBC,          NAND,     RSVD3,    RSVD4),
+	PIN(KB_ROW2_PR2,          KBC,          NAND,     RSVD3,    RSVD4),
+	PIN(KB_ROW3_PR3,          KBC,          NAND,     RSVD3,    INVALID),
+	PIN(KB_ROW4_PR4,          KBC,          NAND,     TRACE,    RSVD4),
+	PIN(KB_ROW5_PR5,          KBC,          NAND,     TRACE,    OWR),
+	PIN(KB_ROW6_PR6,          KBC,          NAND,     SDMMC2,   MIO),
+	PIN(KB_ROW7_PR7,          KBC,          NAND,     SDMMC2,   MIO),
+	PIN(KB_ROW8_PS0,          KBC,          NAND,     SDMMC2,   MIO),
+	PIN(KB_ROW9_PS1,          KBC,          NAND,     SDMMC2,   MIO),
+	PIN(KB_ROW10_PS2,         KBC,          NAND,     SDMMC2,   MIO),
+	PIN(KB_ROW11_PS3,         KBC,          NAND,     SDMMC2,   MIO),
+	PIN(KB_ROW12_PS4,         KBC,          NAND,     SDMMC2,   MIO),
+	PIN(KB_ROW13_PS5,         KBC,          NAND,     SDMMC2,   MIO),
+	PIN(KB_ROW14_PS6,         KBC,          NAND,     SDMMC2,   MIO),
+	PIN(KB_ROW15_PS7,         KBC,          NAND,     SDMMC2,   MIO),
+	PIN(KB_COL0_PQ0,          KBC,          NAND,     TRACE,    TEST),
+	PIN(KB_COL1_PQ1,          KBC,          NAND,     TRACE,    TEST),
+	PIN(KB_COL2_PQ2,          KBC,          NAND,     TRACE,    RSVD4),
+	PIN(KB_COL3_PQ3,          KBC,          NAND,     TRACE,    RSVD4),
+	PIN(KB_COL4_PQ4,          KBC,          NAND,     TRACE,    RSVD4),
+	PIN(KB_COL5_PQ5,          KBC,          NAND,     TRACE,    RSVD4),
+	PIN(KB_COL6_PQ6,          KBC,          NAND,     TRACE,    MIO),
+	PIN(KB_COL7_PQ7,          KBC,          NAND,     TRACE,    MIO),
+	PIN(CLK_32K_OUT_PA0,      BLINK,        RSVD2,    RSVD3,    RSVD4),
+	PIN(SYS_CLK_REQ_PZ5,      SYSCLK,       RSVD2,    RSVD3,    RSVD4),
+	PIN(CORE_PWR_REQ,         CORE_PWR_REQ, RSVD2,    RSVD3,    RSVD4),
+	PIN(CPU_PWR_REQ,          CPU_PWR_REQ,  RSVD2,    RSVD3,    RSVD4),
+	PIN(PWR_INT_N,            PWR_INT_N,    RSVD2,    RSVD3,    RSVD4),
+	PIN(CLK_32K_IN,           CLK_32K_IN,   RSVD2,    RSVD3,    RSVD4),
+	PIN(OWR,                  OWR,          CEC,      RSVD3,    RSVD4),
+	PIN(DAP1_FS_PN0,          I2S0,         HDA,      GMI,      SDMMC2),
+	PIN(DAP1_DIN_PN1,         I2S0,         HDA,      GMI,      SDMMC2),
+	PIN(DAP1_DOUT_PN2,        I2S0,         HDA,      GMI,      SDMMC2),
+	PIN(DAP1_SCLK_PN3,        I2S0,         HDA,      GMI,      SDMMC2),
+	PIN(CLK1_REQ_PEE2,        DAP,          HDA,      RSVD3,    RSVD4),
+	PIN(CLK1_OUT_PW4,         EXTPERIPH1,   RSVD2,    RSVD3,    RSVD4),
+	PIN(SPDIF_IN_PK6,         SPDIF,        HDA,      I2C1,     SDMMC2),
+	PIN(SPDIF_OUT_PK5,        SPDIF,        RSVD2,    I2C1,     SDMMC2),
+	PIN(DAP2_FS_PA2,          I2S1,         HDA,      RSVD3,    GMI),
+	PIN(DAP2_DIN_PA4,         I2S1,         HDA,      RSVD3,    GMI),
+	PIN(DAP2_DOUT_PA5,        I2S1,         HDA,      RSVD3,    GMI),
+	PIN(DAP2_SCLK_PA3,        I2S1,         HDA,      RSVD3,    GMI),
+	PIN(SPI2_MOSI_PX0,        SPI6,         SPI2,     SPI3,     GMI),
+	PIN(SPI2_MISO_PX1,        SPI6,         SPI2,     SPI3,     GMI),
+	PIN(SPI2_CS0_N_PX3,       SPI6,         SPI2,     SPI3,     GMI),
+	PIN(SPI2_SCK_PX2,         SPI6,         SPI2,     SPI3,     GMI),
+	PIN(SPI1_MOSI_PX4,        SPI2,         SPI1,     SPI2_ALT, GMI),
+	PIN(SPI1_SCK_PX5,         SPI2,         SPI1,     SPI2_ALT, GMI),
+	PIN(SPI1_CS0_N_PX6,       SPI2,         SPI1,     SPI2_ALT, GMI),
+	PIN(SPI1_MISO_PX7,        SPI3,         SPI1,     SPI2_ALT, RSVD4),
+	PIN(SPI2_CS1_N_PW2,       SPI3,         SPI2,     SPI2_ALT, I2C1),
+	PIN(SPI2_CS2_N_PW3,       SPI3,         SPI2,     SPI2_ALT, I2C1),
+	PIN(SDMMC3_CLK_PA6,       UARTA,        PWM2,     SDMMC3,   SPI3),
+	PIN(SDMMC3_CMD_PA7,       UARTA,        PWM3,     SDMMC3,   SPI2),
+	PIN(SDMMC3_DAT0_PB7,      RSVD1,        RSVD2,    SDMMC3,   SPI3),
+	PIN(SDMMC3_DAT1_PB6,      RSVD1,        RSVD2,    SDMMC3,   SPI3),
+	PIN(SDMMC3_DAT2_PB5,      RSVD1,        PWM1,     SDMMC3,   SPI3),
+	PIN(SDMMC3_DAT3_PB4,      RSVD1,        PWM0,     SDMMC3,   SPI3),
+	PIN(SDMMC3_DAT4_PD1,      PWM1,         SPI4,     SDMMC3,   SPI2),
+	PIN(SDMMC3_DAT5_PD0,      PWM0,         SPI4,     SDMMC3,   SPI2),
+	PIN(SDMMC3_DAT6_PD3,      SPDIF,        SPI4,     SDMMC3,   SPI2),
+	PIN(SDMMC3_DAT7_PD4,      SPDIF,        SPI4,     SDMMC3,   SPI2),
+	PIN(PEX_L0_PRSNT_N_PDD0,  PCIE,         HDA,      RSVD3,    RSVD4),
+	PIN(PEX_L0_RST_N_PDD1,    PCIE,         HDA,      RSVD3,    RSVD4),
+	PIN(PEX_L0_CLKREQ_N_PDD2, PCIE,         HDA,      RSVD3,    RSVD4),
+	PIN(PEX_WAKE_N_PDD3,      PCIE,         HDA,      RSVD3,    RSVD4),
+	PIN(PEX_L1_PRSNT_N_PDD4,  PCIE,         HDA,      RSVD3,    RSVD4),
+	PIN(PEX_L1_RST_N_PDD5,    PCIE,         HDA,      RSVD3,    RSVD4),
+	PIN(PEX_L1_CLKREQ_N_PDD6, PCIE,         HDA,      RSVD3,    RSVD4),
+	PIN(PEX_L2_PRSNT_N_PDD7,  PCIE,         HDA,      RSVD3,    RSVD4),
+	PIN(PEX_L2_RST_N_PCC6,    PCIE,         HDA,      RSVD3,    RSVD4),
+	PIN(PEX_L2_CLKREQ_N_PCC7, PCIE,         HDA,      RSVD3,    RSVD4),
+	PIN(HDMI_CEC_PEE3,        CEC,          RSVD2,    RSVD3,    RSVD4),
+};
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups;
diff --git a/qemu/roms/u-boot/arch/arm/cpu/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/u-boot-spl.lds
new file mode 100644
index 000000000..3e886680e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/u-boot-spl.lds
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		__image_copy_start = .;
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	__image_copy_end = .;
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		__bss_end = .;
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}
+
+#if defined(CONFIG_SPL_MAX_SIZE)
+ASSERT(__image_copy_end - __image_copy_start < (CONFIG_SPL_MAX_SIZE), \
+	"SPL image too big");
+#endif
+
+#if defined(CONFIG_SPL_BSS_MAX_SIZE)
+ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \
+	"SPL image BSS too big");
+#endif
+
+#if defined(CONFIG_SPL_MAX_FOOTPRINT)
+ASSERT(__bss_end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \
+	"SPL image plus BSS too big");
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/cpu/u-boot.lds b/qemu/roms/u-boot/arch/arm/cpu/u-boot.lds
new file mode 100644
index 000000000..33c1f99fc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/cpu/u-boot.lds
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+	.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
+}
diff --git a/qemu/roms/u-boot/arch/arm/dts/.gitignore b/qemu/roms/u-boot/arch/arm/dts/.gitignore
new file mode 100644
index 000000000..b60ed208c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/.gitignore
@@ -0,0 +1 @@
+*.dtb
diff --git a/qemu/roms/u-boot/arch/arm/dts/Makefile b/qemu/roms/u-boot/arch/arm/dts/Makefile
new file mode 100644
index 000000000..55546152b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/Makefile
@@ -0,0 +1,43 @@
+dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
+	exynos4210-universal_c210.dtb \
+	exynos4210-trats.dtb \
+	exynos4412-trats2.dtb
+
+dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
+	exynos5250-snow.dtb \
+	exynos5250-smdk5250.dtb \
+	exynos5420-smdk5420.dtb
+dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb
+dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
+	tegra20-medcom-wide.dtb \
+	tegra20-paz00.dtb \
+	tegra20-plutux.dtb \
+	tegra20-seaboard.dtb \
+	tegra20-tec.dtb \
+	tegra20-trimslice.dtb \
+	tegra20-ventana.dtb \
+	tegra20-whistler.dtb \
+	tegra20-colibri_t20_iris.dtb \
+	tegra30-beaver.dtb \
+	tegra30-cardhu.dtb \
+	tegra30-tec-ng.dtb \
+	tegra114-dalmore.dtb \
+	tegra124-jetson-tk1.dtb \
+	tegra124-venice2.dtb
+dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
+	zynq-zc706.dtb \
+	zynq-zed.dtb \
+	zynq-microzed.dtb \
+	zynq-zc770-xm010.dtb \
+	zynq-zc770-xm012.dtb \
+	zynq-zc770-xm013.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos4.dtsi b/qemu/roms/u-boot/arch/arm/dts/exynos4.dtsi
new file mode 100644
index 000000000..71dc7ebf4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos4.dtsi
@@ -0,0 +1,138 @@
+/*
+ * Samsung's Exynos4 SoC common device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	serial@13800000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13800000 0x3c>;
+		id = <0>;
+	};
+
+	serial@13810000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13810000 0x3c>;
+		id = <1>;
+	};
+
+	serial@13820000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13820000 0x3c>;
+		id = <2>;
+	};
+
+	serial@13830000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13830000 0x3c>;
+		id = <3>;
+	};
+
+	serial@13840000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13840000 0x3c>;
+		id = <4>;
+	};
+
+	i2c@13860000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <0 0 0>;
+	};
+
+	i2c@13870000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <1 1 0>;
+	};
+
+	i2c@13880000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <2 2 0>;
+	};
+
+	i2c@13890000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <3 3 0>;
+	};
+
+	i2c@138a0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <4 4 0>;
+	};
+
+	i2c@138b0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <5 5 0>;
+	};
+
+	i2c@138c0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <6 6 0>;
+	};
+
+	i2c@138d0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		interrupts = <7 7 0>;
+	};
+
+	sdhci@12510000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-mmc";
+		reg = <0x12510000 0x1000>;
+		interrupts = <0 75 0>;
+	};
+
+	sdhci@12520000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-mmc";
+		reg = <0x12520000 0x1000>;
+		interrupts = <0 76 0>;
+	};
+
+	sdhci@12530000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-mmc";
+		reg = <0x12530000 0x1000>;
+		interrupts = <0 77 0>;
+	};
+
+	sdhci@12540000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-mmc";
+		reg = <0x12540000 0x1000>;
+		interrupts = <0 78 0>;
+	};
+
+	gpio: gpio {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos4210-origen.dts b/qemu/roms/u-boot/arch/arm/dts/exynos4210-origen.dts
new file mode 100644
index 000000000..5c9d2aed6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos4210-origen.dts
@@ -0,0 +1,45 @@
+/*
+ * Samsung's Exynos4210 based Origen board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
+
+/ {
+	model = "Insignal Origen evaluation board based on Exynos4210";
+	compatible = "insignal,origen", "samsung,exynos4210";
+
+	chosen {
+		bootargs ="";
+	};
+
+	aliases {
+		serial0 = "/serial@13800000";
+		console = "/serial@13820000";
+		mmc2 = "sdhci@12530000";
+	};
+
+	sdhci@12510000 {
+		status = "disabled";
+	};
+
+	sdhci@12520000 {
+		status = "disabled";
+	};
+
+	sdhci@12530000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		cd-gpios = <&gpio 0x2008002 0>;
+	};
+
+	sdhci@12540000 {
+		status = "disabled";
+	};
+};
\ No newline at end of file
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos4210-trats.dts b/qemu/roms/u-boot/arch/arm/dts/exynos4210-trats.dts
new file mode 100644
index 000000000..992e0234c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos4210-trats.dts
@@ -0,0 +1,120 @@
+/*
+ * Samsung's Exynos4210 based Trats board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+	model = "Samsung Trats based on Exynos4210";
+	compatible = "samsung,trats", "samsung,exynos4210";
+
+	config {
+		samsung,dsim-device-name = "s6e8ax0";
+	};
+
+	aliases {
+		i2c0 = "/i2c@13860000";
+		i2c1 = "/i2c@13870000";
+		i2c2 = "/i2c@13880000";
+		i2c3 = "/i2c@13890000";
+		i2c4 = "/i2c@138a0000";
+		i2c5 = "/i2c@138b0000";
+		i2c6 = "/i2c@138c0000";
+		i2c7 = "/i2c@138d0000";
+		serial0 = "/serial@13800000";
+		console = "/serial@13820000";
+		mmc0 = "sdhci@12510000";
+		mmc2 = "sdhci@12530000";
+	};
+
+	fimd@11c00000 {
+		compatible = "samsung,exynos-fimd";
+		reg = <0x11c00000 0xa4>;
+
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <720>;
+		samsung,vl-row = <1280>;
+		samsung,vl-width = <720>;
+		samsung,vl-height = <1280>;
+
+		samsung,vl-clkp = <0>;
+		samsung,vl-oep = <0>;
+		samsung,vl-hsp = <1>;
+		samsung,vl-vsp = <1>;
+		samsung,vl-dp = <1>;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <5>;
+		samsung,vl-hbpd = <10>;
+		samsung,vl-hfpd = <10>;
+		samsung,vl-vspw = <2>;
+		samsung,vl-vbpd = <1>;
+		samsung,vl-vfpd = <13>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,winid = <3>;
+		samsung,power-on-delay = <30>;
+		samsung,interface-mode = <1>;
+		samsung,mipi-enabled = <1>;
+		samsung,dp-enabled;
+		samsung,dual-lcd-enabled;
+
+		samsung,logo-on = <1>;
+		samsung,resolution = <0>;
+		samsung,rgb-mode = <0>;
+	};
+
+	mipidsi@11c80000 {
+		compatible = "samsung,exynos-mipi-dsi";
+		reg = <0x11c80000 0x5c>;
+
+		samsung,dsim-config-e-interface = <1>;
+		samsung,dsim-config-e-virtual-ch = <0>;
+		samsung,dsim-config-e-pixel-format = <7>;
+		samsung,dsim-config-e-burst-mode = <1>;
+		samsung,dsim-config-e-no-data-lane = <3>;
+		samsung,dsim-config-e-byte-clk = <0>;
+		samsung,dsim-config-hfp = <1>;
+
+		samsung,dsim-config-p = <3>;
+		samsung,dsim-config-m = <120>;
+		samsung,dsim-config-s = <1>;
+
+		samsung,dsim-config-pll-stable-time = <500>;
+		samsung,dsim-config-esc-clk = <20000000>;
+		samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+		samsung,dsim-config-bta-timeout = <0xff>;
+		samsung,dsim-config-rx-timeout = <0xffff>;
+
+		samsung,dsim-device-id = <0xffffffff>;
+		samsung,dsim-device-bus-id = <0>;
+
+		samsung,dsim-device-reverse-panel = <1>;
+	};
+
+	sdhci@12510000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		pwr-gpios = <&gpio 0x2008002 0>;
+	};
+
+	sdhci@12520000 {
+		status = "disabled";
+	};
+
+	sdhci@12530000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		cd-gpios = <&gpio 0x20c6004 0>;
+	};
+
+	sdhci@12540000 {
+		status = "disabled";
+	};
+};
\ No newline at end of file
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos4210-universal_c210.dts b/qemu/roms/u-boot/arch/arm/dts/exynos4210-universal_c210.dts
new file mode 100644
index 000000000..1cdd981d6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos4210-universal_c210.dts
@@ -0,0 +1,83 @@
+/*
+ * Samsung's Exynos4210 based Universal C210 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+	model = "Samsung Universal C210 based on Exynos4210 rev0";
+	compatible = "samsung,universal_c210", "samsung,exynos4210";
+
+	aliases {
+		serial0 = "/serial@13800000";
+		console = "/serial@13820000";
+		mmc0 = "sdhci@12510000";
+		mmc2 = "sdhci@12530000";
+	};
+
+	sdhci@12510000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		pwr-gpios = <&gpio 0x2008002 0>;
+	};
+
+	sdhci@12520000 {
+		status = "disabled";
+	};
+
+	sdhci@12530000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		cd-gpios = <&gpio 0x20c6004 0>;
+	};
+
+	sdhci@12540000 {
+		status = "disabled";
+	};
+
+	fimd@11c00000 {
+		compatible = "samsung,exynos-fimd";
+		reg = <0x11c00000 0xa4>;
+
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <480>;
+		samsung,vl-row = <800>;
+		samsung,vl-width = <480>;
+		samsung,vl-height = <800>;
+
+		samsung,vl-clkp = <0>;
+		samsung,vl-oep = <0>;
+		samsung,vl-hsp = <1>;
+		samsung,vl-vsp = <1>;
+		samsung,vl-dp = <1>;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <2>;
+		samsung,vl-hbpd = <16>;
+		samsung,vl-hfpd = <16>;
+		samsung,vl-vspw = <2>;
+		samsung,vl-vbpd = <8>;
+		samsung,vl-vfpd = <8>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,pclk_name = <1>;
+		samsung,sclk_div = <1>;
+
+		samsung,winid = <0>;
+		samsung,power-on-delay = <10000>;
+		samsung,interface-mode = <1>;
+		samsung,mipi-enabled = <0>;
+		samsung,dp-enabled;
+		samsung,dual-lcd-enabled;
+
+		samsung,logo-on = <1>;
+		samsung,resolution = <0>;
+		samsung,rgb-mode = <0>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos4412-trats2.dts b/qemu/roms/u-boot/arch/arm/dts/exynos4412-trats2.dts
new file mode 100644
index 000000000..7d32067fd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos4412-trats2.dts
@@ -0,0 +1,434 @@
+/*
+ * Samsung's Exynos4412 based Trats2 board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos4.dtsi"
+
+/ {
+	model = "Samsung Trats2 based on Exynos4412";
+	compatible = "samsung,trats2", "samsung,exynos4412";
+
+	config {
+		samsung,dsim-device-name = "s6e8ax0";
+	};
+
+	aliases {
+		i2c0 = "/i2c@13860000";
+		i2c1 = "/i2c@13870000";
+		i2c2 = "/i2c@13880000";
+		i2c3 = "/i2c@13890000";
+		i2c4 = "/i2c@138a0000";
+		i2c5 = "/i2c@138b0000";
+		i2c6 = "/i2c@138c0000";
+		i2c7 = "/i2c@138d0000";
+		serial0 = "/serial@13800000";
+		console = "/serial@13820000";
+		mmc0 = "sdhci@12510000";
+		mmc2 = "sdhci@12530000";
+	};
+
+	i2c@138d0000 {
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-slave-addr = <0x10>;
+		samsung,i2c-max-bus-freq = <100000>;
+		status = "okay";
+
+		max77686_pmic@09 {
+			compatible = "maxim,max77686_pmic";
+			interrupts = <7 0>;
+			reg = <0x09 0 0>;
+			#clock-cells = <1>;
+
+			voltage-regulators {
+				ldo1_reg: ldo1 {
+					regulator-compatible = "LDO1";
+					regulator-name = "VALIVE_1.0V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo2_reg: ldo2 {
+					regulator-compatible = "LDO2";
+					regulator-name = "VM1M2_1.2V_AP";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo3_reg: ldo3 {
+					regulator-compatible = "LDO3";
+					regulator-name = "VCC_1.8V_AP";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo4_reg: ldo4 {
+					regulator-compatible = "LDO4";
+					regulator-name = "VCC_2.8V_AP";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo5_reg: ldo5 {
+					regulator-compatible = "LDO5";
+					regulator-name = "VCC_1.8V_IO";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo6_reg: ldo6 {
+					regulator-compatible = "LDO6";
+					regulator-name = "VMPLL_1.0V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo7_reg: ldo7 {
+					regulator-compatible = "LDO7";
+					regulator-name = "VPLL_1.0V_AP";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+					regulator-mem-on;
+				};
+
+				ldo8_reg: ldo8 {
+					regulator-compatible = "LDO8";
+					regulator-name = "VMIPI_1.0V";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-mem-off;
+				};
+
+				ldo9_reg: ldo9 {
+					regulator-compatible = "LDO9";
+					regulator-name = "CAM_ISP_MIPI_1.2V";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-mem-idle;
+				};
+
+				ldo10_reg: ldo10 {
+					regulator-compatible = "LDO10";
+					regulator-name = "VMIPI_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-off;
+				};
+
+				ldo11_reg: ldo11 {
+					regulator-compatible = "LDO11";
+					regulator-name = "VABB1_1.95V";
+					regulator-min-microvolt = <1950000>;
+					regulator-max-microvolt = <1950000>;
+					regulator-always-on;
+					regulator-mem-off;
+				};
+
+				ldo12_reg: ldo12 {
+					regulator-compatible = "LDO12";
+					regulator-name = "VUOTG_3.0V";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+					regulator-mem-off;
+				};
+
+				ldo13_reg: ldo13 {
+					regulator-compatible = "LDO13";
+					regulator-name = "NFC_AVDD_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-idle;
+				};
+
+				ldo14_reg: ldo14 {
+					regulator-compatible = "LDO14";
+					regulator-name = "VABB2_1.95V";
+					regulator-min-microvolt = <1950000>;
+					regulator-max-microvolt = <1950000>;
+					regulator-always-on;
+					regulator-mem-off;
+				};
+
+				ldo15_reg: ldo15 {
+					regulator-compatible = "LDO15";
+					regulator-name = "VHSIC_1.0V";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-mem-off;
+				};
+
+				ldo16_reg: ldo16 {
+					regulator-compatible = "LDO16";
+					regulator-name = "VHSIC_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-off;
+				};
+
+				ldo17_reg: ldo17 {
+					regulator-compatible = "LDO17";
+					regulator-name = "CAM_SENSOR_CORE_1.2V";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-mem-idle;
+				};
+
+				ldo18_reg: ldo18 {
+					regulator-compatible = "LDO18";
+					regulator-name = "CAM_ISP_SEN_IO_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-idle;
+				};
+
+				ldo19_reg: ldo19 {
+					regulator-compatible = "LDO19";
+					regulator-name = "VT_CAM_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-idle;
+				};
+
+				ldo20_reg: ldo20 {
+					regulator-compatible = "LDO20";
+					regulator-name = "VDDQ_PRE_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-idle;
+				};
+
+				ldo21_reg: ldo21 {
+					regulator-compatible = "LDO21";
+					regulator-name = "VTF_2.8V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-mem-idle;
+				};
+
+				ldo22_reg: ldo22 {
+					regulator-compatible = "LDO22";
+					regulator-name = "VMEM_VDD_2.8V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+					regulator-mem-off;
+				};
+
+				ldo23_reg: ldo23 {
+					regulator-compatible = "LDO23";
+					regulator-name = "TSP_AVDD_3.3V";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-mem-idle;
+				};
+
+				ldo24_reg: ldo24 {
+					regulator-compatible = "LDO24";
+					regulator-name = "TSP_VDD_1.8V";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-mem-idle;
+				};
+
+				ldo25_reg: ldo25 {
+					regulator-compatible = "LDO25";
+					regulator-name = "LCD_VCC_3.3V";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-mem-idle;
+				};
+
+				ldo26_reg: ldo26 {
+					regulator-compatible = "LDO26";
+					regulator-name = "MOTOR_VCC_3.0V";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+					regulator-mem-idle;
+				};
+
+				buck1_reg: buck1 {
+					regulator-compatible = "BUCK1";
+					regulator-name = "vdd_mif";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-mem-off;
+				};
+
+				buck2_reg: buck2 {
+					regulator-compatible = "BUCK2";
+					regulator-name = "vdd_arm";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-mem-off;
+				};
+
+				buck3_reg: buck3 {
+					regulator-compatible = "BUCK3";
+					regulator-name = "vdd_int";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1150000>;
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-mem-off;
+				};
+
+				buck4_reg: buck4 {
+					regulator-compatible = "BUCK4";
+					regulator-name = "vdd_g3d";
+					regulator-min-microvolt = <850000>;
+					regulator-max-microvolt = <1150000>;
+					regulator-boot-on;
+					regulator-mem-off;
+				};
+
+				buck5_reg: buck5 {
+					regulator-compatible = "BUCK5";
+					regulator-name = "VMEM_1.2V_AP";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				buck6_reg: buck6 {
+					regulator-compatible = "BUCK6";
+					regulator-name = "VCC_SUB_1.35V";
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
+					regulator-always-on;
+				};
+
+				buck7_reg: buck7 {
+					regulator-compatible = "BUCK7";
+					regulator-name = "VCC_SUB_2.0V";
+					regulator-min-microvolt = <2000000>;
+					regulator-max-microvolt = <2000000>;
+					regulator-always-on;
+				};
+
+				buck8_reg: buck8 {
+					regulator-compatible = "BUCK8";
+					regulator-name = "VMEM_VDDF_3.0V";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+					regulator-mem-off;
+				};
+
+				buck9_reg: buck9 {
+					regulator-compatible = "BUCK9";
+					regulator-name = "CAM_ISP_CORE_1.2V";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-mem-off;
+				};
+			};
+		};
+	};
+
+	fimd@11c00000 {
+		compatible = "samsung,exynos-fimd";
+		reg = <0x11c00000 0xa4>;
+
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <720>;
+		samsung,vl-row = <1280>;
+		samsung,vl-width = <720>;
+		samsung,vl-height = <1280>;
+
+		samsung,vl-clkp = <0>;
+		samsung,vl-oep = <0>;
+		samsung,vl-hsp = <1>;
+		samsung,vl-vsp = <1>;
+		samsung,vl-dp = <1>;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <5>;
+		samsung,vl-hbpd = <10>;
+		samsung,vl-hfpd = <10>;
+		samsung,vl-vspw = <2>;
+		samsung,vl-vbpd = <1>;
+		samsung,vl-vfpd = <13>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,winid = <0>;
+		samsung,power-on-delay = <30>;
+		samsung,interface-mode = <1>;
+		samsung,mipi-enabled = <1>;
+		samsung,dp-enabled;
+		samsung,dual-lcd-enabled;
+
+		samsung,logo-on = <1>;
+		samsung,resolution = <0>;
+		samsung,rgb-mode = <0>;
+	};
+
+	mipidsi@11c80000 {
+		compatible = "samsung,exynos-mipi-dsi";
+		reg = <0x11c80000 0x5c>;
+
+		samsung,dsim-config-e-interface = <1>;
+		samsung,dsim-config-e-virtual-ch = <0>;
+		samsung,dsim-config-e-pixel-format = <7>;
+		samsung,dsim-config-e-burst-mode = <1>;
+		samsung,dsim-config-e-no-data-lane = <3>;
+		samsung,dsim-config-e-byte-clk = <0>;
+		samsung,dsim-config-hfp = <1>;
+
+		samsung,dsim-config-p = <3>;
+		samsung,dsim-config-m = <120>;
+		samsung,dsim-config-s = <1>;
+
+		samsung,dsim-config-pll-stable-time = <500>;
+		samsung,dsim-config-esc-clk = <20000000>;
+		samsung,dsim-config-stop-holding-cnt = <0x7ff>;
+		samsung,dsim-config-bta-timeout = <0xff>;
+		samsung,dsim-config-rx-timeout = <0xffff>;
+
+		samsung,dsim-device-id = <0xffffffff>;
+		samsung,dsim-device-bus-id = <0>;
+
+		samsung,dsim-device-reverse-panel = <1>;
+	};
+
+	sdhci@12510000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		pwr-gpios = <&gpio 0x2004002 0>;
+	};
+
+	sdhci@12520000 {
+		status = "disabled";
+	};
+
+	sdhci@12530000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		cd-gpios = <&gpio 0x20C6004 0>;
+	};
+
+	sdhci@12540000 {
+		status = "disabled";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos5.dtsi b/qemu/roms/u-boot/arch/arm/dts/exynos5.dtsi
new file mode 100644
index 000000000..f8c87411b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos5.dtsi
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2013 The Chromium OS Authors
+ * SAMSUNG EXYNOS5 SoC device tree source
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "samsung,exynos5";
+
+	sromc@12250000 {
+		compatible = "samsung,exynos-sromc";
+		reg = <0x12250000 0x20>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	i2c@12c60000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C60000 0x100>;
+		interrupts = <0 56 0>;
+	};
+
+	i2c@12c70000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C70000 0x100>;
+		interrupts = <0 57 0>;
+	};
+
+	i2c@12c80000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C80000 0x100>;
+		interrupts = <0 58 0>;
+	};
+
+	i2c@12c90000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C90000 0x100>;
+		interrupts = <0 59 0>;
+	};
+
+	spi@12d20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x12d20000 0x30>;
+		interrupts = <0 68 0>;
+	};
+
+	spi@12d30000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x12d30000 0x30>;
+		interrupts = <0 69 0>;
+	};
+
+	spi@12d40000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x12d40000 0x30>;
+		clock-frequency = <50000000>;
+		interrupts = <0 70 0>;
+        };
+
+	spi@131a0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x131a0000 0x30>;
+		interrupts = <0 129 0>;
+	};
+
+	spi@131b0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x131b0000 0x30>;
+		interrupts = <0 130 0>;
+	};
+
+	ehci@12110000 {
+		compatible = "samsung,exynos-ehci";
+		reg = <0x12110000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		phy {
+			compatible = "samsung,exynos-usb-phy";
+			reg = <0x12130000 0x100>;
+		};
+	};
+
+	tmu@10060000 {
+		compatible = "samsung,exynos-tmu";
+		reg = <0x10060000 0x10000>;
+	};
+
+	fimd@14400000 {
+		compatible = "samsung,exynos-fimd";
+		reg = <0x14400000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
+	dp@145b0000 {
+		compatible = "samsung,exynos5-dp";
+		reg = <0x145b0000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
+	xhci0: xhci@12000000 {
+		compatible = "samsung,exynos5250-xhci";
+		reg = <0x12000000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		phy {
+			compatible = "samsung,exynos5250-usb3-phy";
+			reg = <0x12100000 0x100>;
+		};
+	};
+
+	mmc@12200000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12200000 0x1000>;
+		interrupts = <0 75 0>;
+	};
+
+	mmc@12210000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12210000 0x1000>;
+		interrupts = <0 76 0>;
+	};
+
+	mmc@12220000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12220000 0x1000>;
+		interrupts = <0 77 0>;
+	};
+
+	mmc@12230000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12230000 0x1000>;
+		interrupts = <0 78 0>;
+	};
+
+	serial@12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 51 0>;
+		id = <0>;
+	};
+
+	serial@12C10000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C10000 0x100>;
+		interrupts = <0 52 0>;
+		id = <1>;
+	};
+
+	serial@12C20000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C20000 0x100>;
+		interrupts = <0 53 0>;
+		id = <2>;
+	};
+
+	serial@12C30000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C30000 0x100>;
+		interrupts = <0 54 0>;
+		id = <3>;
+	};
+
+	gpio: gpio {
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos5250-arndale.dts b/qemu/roms/u-boot/arch/arm/dts/exynos5250-arndale.dts
new file mode 100644
index 000000000..202f2ea6e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos5250-arndale.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Arndale board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+/dts-v1/;
+#include "exynos5250.dtsi"
+
+/ {
+	model = "SAMSUNG Arndale board based on EXYNOS5250";
+	compatible = "samsung,arndale", "samsung,exynos5250";
+
+	aliases {
+		serial0 = "/serial@12C20000";
+		console = "/serial@12C20000";
+	};
+
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos5250-smdk5250.dts b/qemu/roms/u-boot/arch/arm/dts/exynos5250-smdk5250.dts
new file mode 100644
index 000000000..9020382d9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos5250-smdk5250.dts
@@ -0,0 +1,151 @@
+/*
+ * SAMSUNG SMDK5250 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+	compatible = "samsung,smdk5250", "samsung,exynos5250";
+
+	aliases {
+		i2c0 = "/i2c@12c60000";
+		i2c1 = "/i2c@12c70000";
+		i2c2 = "/i2c@12c80000";
+		i2c3 = "/i2c@12c90000";
+		i2c4 = "/i2c@12ca0000";
+		i2c5 = "/i2c@12cb0000";
+		i2c6 = "/i2c@12cc0000";
+		i2c7 = "/i2c@12cd0000";
+		spi0 = "/spi@12d20000";
+		spi1 = "/spi@12d30000";
+		spi2 = "/spi@12d40000";
+		spi3 = "/spi@131a0000";
+		spi4 = "/spi@131b0000";
+		mmc0 = "/mmc@12200000";
+		mmc1 = "/mmc@12210000";
+		mmc2 = "/mmc@12220000";
+		mmc3 = "/mmc@12230000";
+		serial0 = "/serial@12C30000";
+		console = "/serial@12C30000";
+		i2s = "/sound@3830000";
+	};
+
+	sromc@12250000 {
+		bank = <1>;
+		srom-timing = <1 9 12 1 6 1 1>;
+		width = <2>;
+		lan@5000000 {
+			compatible = "smsc,lan9215", "smsc,lan";
+			reg = <0x5000000 0x100>;
+			phy-mode = "mii";
+		};
+	};
+
+	sound@3830000 {
+		samsung,codec-type = "wm8994";
+	};
+
+	sound@12d60000 {
+		status = "disabled";
+	};
+
+	i2c@12c70000 {
+		soundcodec@1a {
+			reg = <0x1a>;
+			compatible = "wolfson,wm8994-codec";
+		};
+	};
+
+	i2c@12c60000 {
+		pmic@9 {
+			reg = <0x9>;
+			compatible = "maxim,max77686_pmic";
+		};
+	};
+
+	tmu@10060000 {
+		samsung,min-temp	= <25>;
+		samsung,max-temp	= <125>;
+		samsung,start-warning	= <95>;
+		samsung,start-tripping	= <105>;
+		samsung,hw-tripping	= <110>;
+		samsung,efuse-min-value	= <40>;
+		samsung,efuse-value	= <55>;
+		samsung,efuse-max-value	= <100>;
+		samsung,slope		= <274761730>;
+		samsung,dc-value	= <25>;
+	};
+
+	fimd@14400000 {
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <2560>;
+		samsung,vl-row = <1600>;
+		samsung,vl-width = <2560>;
+		samsung,vl-height = <1600>;
+
+		samsung,vl-clkp;
+		samsung,vl-dp;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <32>;
+		samsung,vl-hbpd = <80>;
+		samsung,vl-hfpd = <48>;
+		samsung,vl-vspw = <6>;
+		samsung,vl-vbpd = <37>;
+		samsung,vl-vfpd = <3>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,winid = <3>;
+		samsung,interface-mode = <1>;
+		samsung,dp-enabled = <1>;
+		samsung,dual-lcd-enabled = <0>;
+	};
+
+	dp@145b0000 {
+		samsung,lt-status = <0>;
+
+		samsung,master-mode = <0>;
+		samsung,bist-mode = <0>;
+		samsung,bist-pattern = <0>;
+		samsung,h-sync-polarity = <0>;
+		samsung,v-sync-polarity = <0>;
+		samsung,interlaced = <0>;
+		samsung,color-space = <0>;
+		samsung,dynamic-range = <0>;
+		samsung,ycbcr-coeff = <0>;
+		samsung,color-depth = <1>;
+	};
+
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		samsung,removable = <0>;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		samsung,removable = <1>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
+
+	ehci@12110000 {
+		samsung,vbus-gpio = <&gpio 0x316 0>; /* X26 */
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos5250-snow.dts b/qemu/roms/u-boot/arch/arm/dts/exynos5250-snow.dts
new file mode 100644
index 000000000..9b48a0ccd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos5250-snow.dts
@@ -0,0 +1,187 @@
+/*
+ * SAMSUNG Snow board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+	model = "Google Snow";
+	compatible = "google,snow", "samsung,exynos5250";
+
+	aliases {
+		i2c0 = "/i2c@12c60000";
+		i2c1 = "/i2c@12c70000";
+		i2c2 = "/i2c@12c80000";
+		i2c3 = "/i2c@12c90000";
+		i2c4 = "/i2c@12ca0000";
+		i2c5 = "/i2c@12cb0000";
+		i2c6 = "/i2c@12cc0000";
+		i2c7 = "/i2c@12cd0000";
+		spi0 = "/spi@12d20000";
+		spi1 = "/spi@12d30000";
+		spi2 = "/spi@12d40000";
+		spi3 = "/spi@131a0000";
+		spi4 = "/spi@131b0000";
+		mmc0 = "/mmc@12200000";
+		mmc1 = "/mmc@12210000";
+		mmc2 = "/mmc@12220000";
+		mmc3 = "/mmc@12230000";
+		serial0 = "/serial@12C30000";
+		console = "/serial@12C30000";
+		i2s = "/sound@3830000";
+	};
+
+	i2c4: i2c@12ca0000 {
+		cros-ec@1e {
+			reg = <0x1e>;
+			compatible = "google,cros-ec";
+			i2c-max-frequency = <100000>;
+			ec-interrupt = <&gpio 782 1>;
+		};
+
+		power-regulator@48 {
+			compatible = "ti,tps65090";
+			reg = <0x48>;
+		};
+	};
+
+	spi@131b0000 {
+		spi-max-frequency = <1000000>;
+		spi-deactivate-delay = <100>;
+		cros-ec@0 {
+			reg = <0>;
+			compatible = "google,cros-ec";
+			spi-max-frequency = <5000000>;
+			ec-interrupt = <&gpio 782 1>;
+			optimise-flash-write;
+			status = "disabled";
+		};
+	};
+
+	sound@3830000 {
+		samsung,codec-type = "max98095";
+		codec-enable-gpio = <&gpio 0xb7 0>;
+	};
+
+	sound@12d60000 {
+		status = "disabled";
+	};
+
+	i2c@12cd0000 {
+		soundcodec@22 {
+			reg = <0x22>;
+			compatible = "maxim,max98095-codec";
+		};
+	};
+
+	i2c@12c60000 {
+		pmic@9 {
+			reg = <0x9>;
+			compatible = "maxim,max77686_pmic";
+		};
+	};
+
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		samsung,removable = <0>;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		samsung,removable = <1>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
+
+	ehci@12110000 {
+		samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */
+	};
+
+	xhci@12000000 {
+		samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */
+	};
+
+	tmu@10060000 {
+		samsung,min-temp	= <25>;
+		samsung,max-temp	= <125>;
+		samsung,start-warning	= <95>;
+		samsung,start-tripping	= <105>;
+		samsung,hw-tripping	= <110>;
+		samsung,efuse-min-value	= <40>;
+		samsung,efuse-value	= <55>;
+		samsung,efuse-max-value	= <100>;
+		samsung,slope		= <274761730>;
+		samsung,dc-value	= <25>;
+	};
+
+	cros-ec-keyb {
+		compatible = "google,cros-ec-keyb";
+		google,key-rows = <8>;
+		google,key-columns = <13>;
+		google,repeat-delay-ms = <240>;
+		google,repeat-rate-ms = <30>;
+		google,ghost-filter;
+		/*
+		 * Keymap entries take the form of 0xRRCCKKKK where
+		 * RR=Row CC=Column KKKK=Key Code
+		 * The values below are for a US keyboard layout and
+		 * are taken from the Linux driver. Note that the
+		 * 102ND key is not used for US keyboards.
+		 */
+		linux,keymap = <
+			/* CAPSLCK F1         B          F10     */
+			0x0001003a 0x0002003b 0x00030030 0x00040044
+			/* N       =          R_ALT      ESC     */
+			0x00060031 0x0008000d 0x000a0064 0x01010001
+			/* F4      G          F7         H       */
+			0x0102003e 0x01030022 0x01040041 0x01060023
+			/* '       F9         BKSPACE    L_CTRL  */
+			0x01080028 0x01090043 0x010b000e 0x0200001d
+			/* TAB     F3         T          F6      */
+			0x0201000f 0x0202003d 0x02030014 0x02040040
+			/* ]       Y          102ND      [       */
+			0x0205001b 0x02060015 0x02070056 0x0208001a
+			/* F8      GRAVE      F2         5       */
+			0x02090042 0x03010029 0x0302003c 0x03030006
+			/* F5      6          -          \       */
+			0x0304003f 0x03060007 0x0308000c 0x030b002b
+			/* R_CTRL  A          D          F       */
+			0x04000061 0x0401001e 0x04020020 0x04030021
+			/* S       K          J          ;       */
+			0x0404001f 0x04050025 0x04060024 0x04080027
+			/* L       ENTER      Z          C       */
+			0x04090026 0x040b001c 0x0501002c 0x0502002e
+			/* V       X          ,          M       */
+			0x0503002f 0x0504002d 0x05050033 0x05060032
+			/* L_SHIFT /          .          SPACE   */
+			0x0507002a 0x05080035 0x05090034 0x050B0039
+			/* 1       3          4          2       */
+			0x06010002 0x06020004 0x06030005 0x06040003
+			/* 8       7          0          9       */
+			0x06050009 0x06060008 0x0608000b 0x0609000a
+			/* L_ALT   DOWN       RIGHT      Q       */
+			0x060a0038 0x060b006c 0x060c006a 0x07010010
+			/* E       R          W          I       */
+			0x07020012 0x07030013 0x07040011 0x07050017
+			/* U       R_SHIFT    P          O       */
+			0x07060016 0x07070036 0x07080019 0x07090018
+			/* UP      LEFT    */
+			0x070b0067 0x070c0069>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos5250.dtsi b/qemu/roms/u-boot/arch/arm/dts/exynos5250.dtsi
new file mode 100644
index 000000000..0c644e7ca
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos5250.dtsi
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * SAMSUNG EXYNOS5250 SoC device tree source
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "exynos5.dtsi"
+
+/ {
+	i2c@12ca0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CA0000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c@12cb0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CB0000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c@12cc0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CC0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c@12cd0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CD0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	sound@3830000 {
+		compatible = "samsung,exynos-sound";
+		reg = <0x3830000 0x50>;
+		samsung,i2s-epll-clock-frequency = <192000000>;
+		samsung,i2s-sampling-rate = <48000>;
+		samsung,i2s-bits-per-sample = <16>;
+		samsung,i2s-channels = <2>;
+		samsung,i2s-lr-clk-framesize = <256>;
+		samsung,i2s-bit-clk-framesize = <32>;
+		samsung,i2s-id = <0>;
+	};
+
+	sound@12d60000 {
+		compatible = "samsung,exynos-sound";
+		reg = <0x12d60000 0x20>;
+		samsung,i2s-epll-clock-frequency = <192000000>;
+		samsung,i2s-sampling-rate = <48000>;
+		samsung,i2s-bits-per-sample = <16>;
+		samsung,i2s-channels = <2>;
+		samsung,i2s-lr-clk-framesize = <256>;
+		samsung,i2s-bit-clk-framesize = <32>;
+		samsung,i2s-id = <1>;
+	};
+
+
+	xhci@12000000 {
+		compatible = "samsung,exynos5250-xhci";
+		reg = <0x12000000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		phy {
+			compatible = "samsung,exynos5250-usb3-phy";
+			reg = <0x12100000 0x100>;
+		};
+	};
+
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos5420-smdk5420.dts b/qemu/roms/u-boot/arch/arm/dts/exynos5420-smdk5420.dts
new file mode 100644
index 000000000..d73976356
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,169 @@
+/*
+ * SAMSUNG SMDK5420 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos5420.dtsi"
+
+/ {
+	model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
+	compatible = "samsung,smdk5420", "samsung,exynos5";
+
+	config {
+		hwid = "smdk5420 TEST A-A 9382";
+	};
+
+	aliases {
+		i2c0 = "/i2c@12c60000";
+		i2c1 = "/i2c@12c70000";
+		i2c2 = "/i2c@12c80000";
+		i2c3 = "/i2c@12c90000";
+		i2c4 = "/i2c@12ca0000";
+		i2c5 = "/i2c@12cb0000";
+		i2c6 = "/i2c@12cc0000";
+		i2c7 = "/i2c@12cd0000";
+		i2c8 = "/i2c@12e00000";
+		i2c9 = "/i2c@12e10000";
+		i2c10 = "/i2c@12e20000";
+		spi0 = "/spi@12d20000";
+		spi1 = "/spi@12d30000";
+		spi2 = "/spi@12d40000";
+		spi3 = "/spi@131a0000";
+		spi4 = "/spi@131b0000";
+		mmc0 = "/mmc@12200000";
+		mmc1 = "/mmc@12210000";
+		mmc2 = "/mmc@12220000";
+		xhci0 = "/xhci@12000000";
+		xhci1 = "/xhci@12400000";
+		serial0 = "/serial@12C30000";
+		console = "/serial@12C30000";
+	};
+
+	tmu@10060000 {
+		samsung,min-temp	= <25>;
+		samsung,max-temp	= <125>;
+		samsung,start-warning	= <95>;
+		samsung,start-tripping	= <105>;
+		samsung,hw-tripping	= <110>;
+		samsung,efuse-min-value	= <40>;
+		samsung,efuse-value	= <55>;
+		samsung,efuse-max-value	= <100>;
+		samsung,slope		= <274761730>;
+		samsung,dc-value	= <25>;
+	};
+
+	/* s2mps11 is on i2c bus 4 */
+	i2c@12ca0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pmic@66 {
+			reg = <0x66>;
+			compatible = "samsung,s2mps11-pmic";
+		};
+	};
+
+	spi@12d20000 { /* spi0 */
+		spi-max-frequency = <50000000>;
+		firmware_storage_spi: flash@0 {
+			reg = <0>;
+		};
+	};
+
+	fimd@14400000 {
+		samsung,vl-freq = <60>;
+		samsung,vl-col = <2560>;
+		samsung,vl-row = <1600>;
+		samsung,vl-width = <2560>;
+		samsung,vl-height = <1600>;
+
+		samsung,vl-clkp;
+		samsung,vl-dp;
+		samsung,vl-bpix = <4>;
+
+		samsung,vl-hspw = <32>;
+		samsung,vl-hbpd = <80>;
+		samsung,vl-hfpd = <48>;
+		samsung,vl-vspw = <6>;
+		samsung,vl-vbpd = <37>;
+		samsung,vl-vfpd = <3>;
+		samsung,vl-cmd-allow-len = <0xf>;
+
+		samsung,winid = <3>;
+		samsung,interface-mode = <1>;
+		samsung,dp-enabled = <1>;
+		samsung,dual-lcd-enabled = <0>;
+	};
+
+	sound@3830000 {
+		samsung,codec-type = "wm8994";
+	};
+
+	i2c@12c70000 {
+		soundcodec@1a {
+			reg = <0x1a>;
+			compatible = "wolfson,wm8994-codec";
+		};
+	};
+
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		samsung,removable = <0>;
+		samsung,pre-init;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		samsung,removable = <1>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
+
+	fimd@14400000 {
+		/* sysmmu is not used in U-Boot */
+		samsung,disable-sysmmu;
+	};
+
+	dp@145b0000 {
+		samsung,lt-status = <0>;
+
+		samsung,master-mode = <0>;
+		samsung,bist-mode = <0>;
+		samsung,bist-pattern = <0>;
+		samsung,h-sync-polarity = <0>;
+		samsung,v-sync-polarity = <0>;
+		samsung,interlaced = <0>;
+		samsung,color-space = <0>;
+		samsung,dynamic-range = <0>;
+		samsung,ycbcr-coeff = <0>;
+		samsung,color-depth = <1>;
+	};
+
+	dmc {
+		mem-type = "ddr3";
+	};
+
+	xhci1: xhci@12400000 {
+		compatible = "samsung,exynos5250-xhci";
+		reg = <0x12400000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		phy {
+			compatible = "samsung,exynos5250-usb3-phy";
+			reg = <0x12500000 0x100>;
+		};
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/exynos5420.dtsi b/qemu/roms/u-boot/arch/arm/dts/exynos5420.dtsi
new file mode 100644
index 000000000..02ead61a4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/exynos5420.dtsi
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * SAMSUNG EXYNOS5420 SoC device tree source
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "exynos5.dtsi"
+
+/ {
+	config {
+		machine-arch-id = <4151>;
+	};
+
+	i2c@12ca0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CA0000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c@12cb0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CB0000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c@12cc0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CC0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c@12cd0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CD0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	i2c@12e00000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E00000 0x100>;
+		interrupts = <0 87 0>;
+	};
+
+	i2c@12e10000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E10000 0x100>;
+		interrupts = <0 88 0>;
+	};
+
+	i2c@12e20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E20000 0x100>;
+		interrupts = <0 203 0>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/imx6q-sabreauto.dts b/qemu/roms/u-boot/arch/arm/dts/imx6q-sabreauto.dts
new file mode 100644
index 000000000..a3c9c91f3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/imx6q-sabreauto.dts
@@ -0,0 +1,13 @@
+/*
+    + * Copyright 2012 Freescale Semiconductor, Inc.
+    + * Copyright 2011 Linaro Ltd.
+    + *
+    + * SPDX-License-Identifier:     GPL-2.0+
+    + */
+
+/dts-v1/;
+
+/ {
+	model = "Freescale i.MX6 Quad SABRE Automotive Board";
+	compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/skeleton.dtsi b/qemu/roms/u-boot/arch/arm/dts/skeleton.dtsi
new file mode 100644
index 000000000..b41d241de
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/skeleton.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value.  The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	chosen { };
+	aliases { };
+	memory { device_type = "memory"; reg = <0 0>; };
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra114-dalmore.dts b/qemu/roms/u-boot/arch/arm/dts/tegra114-dalmore.dts
new file mode 100644
index 000000000..435c01e9f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra114-dalmore.dts
@@ -0,0 +1,71 @@
+/dts-v1/;
+
+#include "tegra114.dtsi"
+
+/ {
+	model = "NVIDIA Dalmore";
+	compatible = "nvidia,dalmore", "nvidia,tegra114";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+		sdhci0 = "/sdhci@78000600";
+		sdhci1 = "/sdhci@78000400";
+		usb0 = "/usb@7d008000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	sdhci@78000400 {
+		cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+		bus-width = <4>;
+		status = "okay";
+	};
+
+	sdhci@78000600 {
+		bus-width = <8>;
+		status = "okay";
+	};
+
+	usb@7d008000 {
+		/* SPDIF_IN: USB_VBUS_EN1 */
+		nvidia,vbus-gpio = <&gpio 86 0>;
+		status = "okay";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra114.dtsi b/qemu/roms/u-boot/arch/arm/dts/tegra114.dtsi
new file mode 100644
index 000000000..f52fcf14d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra114.dtsi
@@ -0,0 +1,246 @@
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra114";
+
+	tegra_car: clock {
+		compatible = "nvidia,tegra114-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	apbdma: dma {
+		compatible = "nvidia,tegra114-apbdma", "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
+		reg = <0x6000a000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+	};
+
+	gpio: gpio {
+		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
+		reg = <0x6000d000 0x1000>;
+		interrupts = <0 32 0x04
+			      0 33 0x04
+			      0 34 0x04
+			      0 35 0x04
+			      0 55 0x04
+			      0 87 0x04
+			      0 89 0x04
+			      0 125 0x04>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+	};
+
+	i2c@7000c000 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c000 0x100>;
+		interrupts = <0 38 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 12>;
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c400 0x100>;
+		interrupts = <0 84 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 54>;
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c500 0x100>;
+		interrupts = <0 92 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 67>;
+		status = "disabled";
+	};
+
+	i2c@7000c700 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000c700 0x100>;
+		interrupts = <0 120 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 103>;
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		compatible = "nvidia,tegra114-i2c";
+		reg = <0x7000d000 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>;
+		status = "disabled";
+	};
+
+	spi@7000d400 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC1, PLLP_OUT0 */
+		clocks = <&tegra_car 41>;
+	};
+
+	spi@7000d600 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC2, PLLP_OUT0 */
+		clocks = <&tegra_car 44>;
+	};
+
+	spi@7000d800 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000d800 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC3, PLLP_OUT0 */
+		clocks = <&tegra_car 46>;
+	};
+
+	spi@7000da00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC4, PLLP_OUT0 */
+		clocks = <&tegra_car 68>;
+	};
+
+	spi@7000dc00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC5, PLLP_OUT0 */
+		clocks = <&tegra_car 104>;
+	};
+
+	spi@7000de00 {
+		compatible = "nvidia,tegra114-spi";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SBC6, PLLP_OUT0 */
+		clocks = <&tegra_car 105>;
+	};
+
+	sdhci@78000000 {
+		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
+		reg = <0x78000000 0x200>;
+		interrupts = <0 14 0x04>;
+		clocks = <&tegra_car 14>;
+		status = "disable";
+	};
+
+	sdhci@78000200 {
+		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
+		reg = <0x78000200 0x200>;
+		interrupts = <0 15 0x04>;
+		clocks = <&tegra_car 9>;
+		status = "disable";
+	};
+
+	sdhci@78000400 {
+		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
+		reg = <0x78000400 0x200>;
+		interrupts = <0 19 0x04>;
+		clocks = <&tegra_car 69>;
+		status = "disable";
+	};
+
+	sdhci@78000600 {
+		compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
+		reg = <0x78000600 0x200>;
+		interrupts = <0 31 0x04>;
+		clocks = <&tegra_car 15>;
+		status = "disable";
+	};
+
+	usb@7d000000 {
+		compatible = "nvidia,tegra114-ehci";
+		reg = <0x7d000000 0x4000>;
+		interrupts = <52>;
+		phy_type = "utmi";
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
+		status = "disabled";
+	};
+
+	usb@7d004000 {
+		compatible = "nvidia,tegra114-ehci";
+		reg = <0x7d004000 0x4000>;
+		interrupts = <53>;
+		phy_type = "hsic";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
+		status = "disabled";
+	};
+
+	usb@7d008000 {
+		compatible = "nvidia,tegra114-ehci";
+		reg = <0x7d008000 0x4000>;
+		interrupts = <129>;
+		phy_type = "utmi";
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
+		status = "disabled";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra124-jetson-tk1.dts b/qemu/roms/u-boot/arch/arm/dts/tegra124-jetson-tk1.dts
new file mode 100644
index 000000000..52e8c0e59
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -0,0 +1,84 @@
+/dts-v1/;
+
+#include "tegra124.dtsi"
+
+/ {
+	model = "NVIDIA Jetson TK1";
+	compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+		i2c5 = "/i2c@7000d100";
+		sdhci0 = "/sdhci@700b0600";
+		sdhci1 = "/sdhci@700b0400";
+		spi0 = "/spi@7000d400";
+		spi1 = "/spi@7000da00";
+		usb0 = "/usb@7d008000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d100 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	spi@7000d400 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	sdhci@700b0400 {
+		status = "okay";
+		cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+		power-gpios = <&gpio 136 0>; /* gpio PR0 */
+		bus-width = <4>;
+	};
+
+	sdhci@700b0600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	usb@7d008000 {
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra124-venice2.dts b/qemu/roms/u-boot/arch/arm/dts/tegra124-venice2.dts
new file mode 100644
index 000000000..2f8d1dcc3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra124-venice2.dts
@@ -0,0 +1,84 @@
+/dts-v1/;
+
+#include "tegra124.dtsi"
+
+/ {
+	model = "NVIDIA Venice2";
+	compatible = "nvidia,venice2", "nvidia,tegra124";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+		i2c5 = "/i2c@7000d100";
+		sdhci0 = "/sdhci@700b0600";
+		sdhci1 = "/sdhci@700b0400";
+		spi0 = "/spi@7000d400";
+		spi1 = "/spi@7000da00";
+		usb0 = "/usb@7d008000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d100 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	spi@7000d400 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	sdhci@700b0400 {
+		status = "okay";
+		cd-gpios = <&gpio 170 0>; /* gpio PV2 */
+		power-gpios = <&gpio 136 0>; /* gpio PR0 */
+		bus-width = <4>;
+	};
+
+	sdhci@700b0600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	usb@7d008000 {
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra124.dtsi b/qemu/roms/u-boot/arch/arm/dts/tegra124.dtsi
new file mode 100644
index 000000000..18a8b24b7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra124.dtsi
@@ -0,0 +1,250 @@
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra124";
+
+	tegra_car: clock@60006000 {
+		compatible = "nvidia,tegra124-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	apbdma: dma@60020000 {
+		compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
+		reg = <0x60020000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+	};
+
+	gpio: gpio@6000d000 {
+		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
+		reg = <0x6000d000 0x1000>;
+		interrupts = <0 32 0x04
+			      0 33 0x04
+			      0 34 0x04
+			      0 35 0x04
+			      0 55 0x04
+			      0 87 0x04
+			      0 89 0x04
+			      0 125 0x04>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+	};
+
+	i2c@7000c000 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c000 0x100>;
+		interrupts = <0 38 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 12>;
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c400 0x100>;
+		interrupts = <0 84 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 54>;
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c500 0x100>;
+		interrupts = <0 92 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 67>;
+		status = "disabled";
+	};
+
+	i2c@7000c700 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000c700 0x100>;
+		interrupts = <0 120 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 103>;
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000d000 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>;
+		status = "disabled";
+	};
+
+	i2c@7000d100 {
+		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+		reg = <0x7000d100 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>;
+		status = "disabled";
+	};
+
+	spi@7000d400 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 41>;
+	};
+
+	spi@7000d600 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 44>;
+	};
+
+	spi@7000d800 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000d800 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 46>;
+	};
+
+	spi@7000da00 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 68>;
+	};
+
+	spi@7000dc00 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 104>;
+	};
+
+	spi@7000de00 {
+		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		clocks = <&tegra_car 105>;
+	};
+
+	sdhci@700b0000 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0000 0x200>;
+		interrupts = <0 14 0x04>;
+		clocks = <&tegra_car 14>;
+		status = "disabled";
+	};
+
+	sdhci@700b0200 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0200 0x200>;
+		interrupts = <0 15 0x04>;
+		clocks = <&tegra_car 9>;
+		status = "disabled";
+	};
+
+	sdhci@700b0400 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0400 0x200>;
+		interrupts = <0 19 0x04>;
+		clocks = <&tegra_car 69>;
+		status = "disabled";
+	};
+
+	sdhci@700b0600 {
+		compatible = "nvidia,tegra124-sdhci";
+		reg = <0x700b0600 0x200>;
+		interrupts = <0 31 0x04>;
+		clocks = <&tegra_car 15>;
+		status = "disabled";
+	};
+
+	usb@7d000000 {
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+		reg = <0x7d000000 0x4000>;
+		interrupts = < 52 >;
+		phy_type = "utmi";
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
+		status = "disabled";
+	};
+
+	usb@7d004000 {
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+		reg = <0x7d004000 0x4000>;
+		interrupts = < 53 >;
+		phy_type = "hsic";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
+		status = "disabled";
+	};
+
+	usb@7d008000 {
+		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+		reg = <0x7d008000 0x4000>;
+		interrupts = < 129 >;
+		phy_type = "utmi";
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
+		status = "disabled";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-colibri_t20_iris.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-colibri_t20_iris.dts
new file mode 100644
index 000000000..c0e54af88
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-colibri_t20_iris.dts
@@ -0,0 +1,45 @@
+/dts-v1/;
+
+#include "tegra20.dtsi"
+
+/ {
+	model = "Toradex Colibri T20";
+	compatible = "toradex,t20", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5000000";
+		usb2 = "/usb@c5004000";
+		sdhci0 = "/sdhci@c8000600";
+	};
+
+	usb@c5000000 {
+		dr_mode = "otg";
+	};
+
+	usb@c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* PV1 */
+		nvidia,vbus-gpio = <&gpio 217 0>; /* PBB1 */
+	};
+
+	usb@c5008000 {
+		nvidia,vbus-gpio = <&gpio 178 1>; /* PW2 low-active */
+	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 144 0>; /* PS0 */
+		nvidia,width = <8>;
+		nvidia,timing = <15 100 25 80 25 10 15 10 100>;
+
+		nand@0 {
+			reg = <0>;
+			compatible = "nand-flash";
+		};
+	};
+
+	sdhci@c8000600 {
+		status = "okay";
+		cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+		bus-width = <4>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-harmony.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-harmony.dts
new file mode 100644
index 000000000..b115f8782
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-harmony.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+
+#include "tegra20.dtsi"
+
+/ {
+	model = "NVIDIA Tegra20 Harmony evaluation board";
+	compatible = "nvidia,harmony", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5004000";
+		sdhci0 = "/sdhci@c8000600";
+		sdhci1 = "/sdhci@c8000200";
+	};
+
+	memory {
+		reg = <0x00000000 0x40000000>;
+	};
+
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
+		};
+	};
+
+	serial@70006300 {
+		clock-frequency = < 216000000 >;
+	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>;		/* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5000000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+	};
+
+	sdhci@c8000200 {
+		status = "okay";
+		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 155 0>; /* gpio PT3 */
+		bus-width = <4>;
+	};
+
+	sdhci@c8000600 {
+		status = "okay";
+		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
+		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		bus-width = <8>;
+	};
+
+	lcd_panel: panel {
+		clock = <42430000>;
+		xres = <1024>;
+		yres = <600>;
+		left-margin = <138>;
+		right-margin = <34>;
+		hsync-len = <136>;
+		lower-margin = <4>;
+		upper-margin = <21>;
+		vsync-len = <4>;
+		hsync-active-high;
+		vsyncx-active-high;
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 0>;
+		nvidia,backlight-enable-gpios = <&gpio 13 0>;	/* PB5 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>;	/* PB2 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
+		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
+		nvidia,panel-timings = <0 0 200 0 0>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-medcom-wide.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-medcom-wide.dts
new file mode 100644
index 000000000..a9a07f9bc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-medcom-wide.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+#include "tegra20-tamonten.dtsi"
+
+/ {
+	model = "Avionic Design Medcom-Wide";
+	compatible = "ad,medcom-wide", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+		sdhci0 = "/sdhci@c8000600";
+	};
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	host1x {
+		status = "okay";
+
+		dc@54200000 {
+			status = "okay";
+
+			rgb {
+				nvidia,panel = <&lcd_panel>;
+				status = "okay";
+			};
+		};
+	};
+
+	serial@70006300 {
+		clock-frequency = <216000000>;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5000000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+
+	lcd_panel: panel {
+		clock = <61715000>;
+		xres = <1366>;
+		yres = <768>;
+		left-margin = <2>;
+		right-margin = <47>;
+		hsync-len = <136>;
+		lower-margin = <21>;
+		upper-margin = <11>;
+		vsync-len = <4>;
+
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 500000>;
+		nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+		nvidia,panel-timings = <0 0 0 0>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-paz00.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-paz00.dts
new file mode 100644
index 000000000..780203cfb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-paz00.dts
@@ -0,0 +1,91 @@
+/dts-v1/;
+
+#include "tegra20.dtsi"
+
+/ {
+	model = "Toshiba AC100 / Dynabook AZ";
+	compatible = "compal,paz00", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+		sdhci0 = "/sdhci@c8000600";
+		sdhci1 = "/sdhci@c8000000";
+	};
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
+		};
+	};
+
+	serial@70006000 {
+		clock-frequency = < 216000000 >;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5000000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+
+	sdhci@c8000000 {
+		status = "okay";
+		cd-gpios = <&gpio 173 1>; /* gpio PV5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 169 0>; /* gpio PV1 */
+		bus-width = <4>;
+	};
+
+	sdhci@c8000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	lcd_panel: panel {
+		/* PAZ00 has 1024x600 */
+		clock = <54030000>;
+		xres = <1024>;
+		yres = <600>;
+		right-margin = <160>;
+		left-margin = <24>;
+		hsync-len = <136>;
+		upper-margin = <3>;
+		lower-margin = <61>;
+		vsync-len = <6>;
+		hsync-active-high;
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 0>;
+		nvidia,backlight-enable-gpios = <&gpio 164 0>;	/* PU4 */
+		nvidia,lvds-shutdown-gpios = <&gpio 102 0>;	/* PM6 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
+		nvidia,panel-vdd-gpios = <&gpio 4 0>;		/* PA4 */
+		nvidia,panel-timings = <400 4 203 17 15>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-plutux.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-plutux.dts
new file mode 100644
index 000000000..20016f29b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-plutux.dts
@@ -0,0 +1,45 @@
+/dts-v1/;
+
+#include "tegra20-tamonten.dtsi"
+
+/ {
+	model = "Avionic Design Plutux";
+	compatible = "ad,plutux", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+		sdhci0 = "/sdhci@c8000600";
+	};
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	serial@70006300 {
+		clock-frequency = <216000000>;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5000000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-seaboard.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-seaboard.dts
new file mode 100644
index 000000000..c0e2e1e5f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-seaboard.dts
@@ -0,0 +1,191 @@
+/dts-v1/;
+
+#include "tegra20.dtsi"
+
+/ {
+	model = "NVIDIA Seaboard";
+	compatible = "nvidia,seaboard", "nvidia,tegra20";
+
+	chosen {
+		bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
+	};
+
+	aliases {
+		/* This defines the order of our ports */
+		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5000000";
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		sdhci0 = "/sdhci@c8000600";
+		sdhci1 = "/sdhci@c8000400";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = < 0x00000000 0x40000000 >;
+	};
+
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
+		};
+	};
+
+	/* This is not used in U-Boot, but is expected to be in kernel .dts */
+	i2c@7000d000 {
+		clock-frequency = <100000>;
+		pmic@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+
+			clk_32k: clock {
+				compatible = "fixed-clock";
+				/*
+				 * leave out for now due to CPP:
+				 * #clock-cells = <0>;
+				 */
+				clock-frequency = <32768>;
+			};
+		};
+	};
+
+	serial@70006300 {
+		clock-frequency = < 216000000 >;
+	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
+
+	i2c@7000c000 {
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		clock-frequency = <100000>;
+	};
+
+	kbc@7000e200 {
+		linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
+			0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
+			0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
+			0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
+			0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
+			0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
+			0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
+			0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
+			0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
+			0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
+			0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
+			0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
+			0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
+			0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
+			0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
+			0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
+			0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
+			0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
+			0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
+			0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
+			0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
+			0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
+			0x1f04008a>;
+		linux,fn-keymap = <0x05040002>;
+	};
+
+	emc@7000f400 {
+		emc-table@190000 {
+			reg = < 190000 >;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 190000 >;
+			nvidia,emc-registers = < 0x0000000c 0x00000026
+				0x00000009 0x00000003 0x00000004 0x00000004
+				0x00000002 0x0000000c 0x00000003 0x00000003
+				0x00000002 0x00000001 0x00000004 0x00000005
+				0x00000004 0x00000009 0x0000000d 0x0000059f
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000003 0x00000001 0x0000000b 0x000000c8
+				0x00000003 0x00000007 0x00000004 0x0000000f
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0xa06204ae
+				0x007dc010 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@380000 {
+			reg = < 380000 >;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 380000 >;
+			nvidia,emc-registers = < 0x00000017 0x0000004b
+				0x00000012 0x00000006 0x00000004 0x00000005
+				0x00000003 0x0000000c 0x00000006 0x00000006
+				0x00000003 0x00000001 0x00000004 0x00000005
+				0x00000004 0x00000009 0x0000000d 0x00000b5f
+				0x00000000 0x00000003 0x00000003 0x00000006
+				0x00000006 0x00000001 0x00000011 0x000000c8
+				0x00000003 0x0000000e 0x00000007 0x0000000f
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0xe044048b
+				0x007d8010 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+	};
+
+	usb@c5000000 {
+		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+		dr_mode = "otg";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+
+	sdhci@c8000400 {
+		status = "okay";
+		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		bus-width = <4>;
+	};
+
+	sdhci@c8000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	lcd_panel: panel {
+		/* Seaboard has 1366x768 */
+		clock = <70600000>;
+		xres = <1366>;
+		yres = <768>;
+		left-margin = <58>;
+		right-margin = <58>;
+		hsync-len = <58>;
+		lower-margin = <4>;
+		upper-margin = <4>;
+		vsync-len = <4>;
+		hsync-active-high;
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 2 0>;
+		nvidia,backlight-enable-gpios = <&gpio 28 0>;	/* PD4 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>;	/* PB2 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
+		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
+		nvidia,panel-timings = <400 4 203 17 15>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-tamonten.dtsi b/qemu/roms/u-boot/arch/arm/dts/tegra20-tamonten.dtsi
new file mode 100644
index 000000000..f379622c9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-tamonten.dtsi
@@ -0,0 +1,500 @@
+#include "tegra20.dtsi"
+
+/ {
+	model = "Avionic Design Tamonten SOM";
+	compatible = "ad,tamonten", "nvidia,tegra20";
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	host1x {
+		hdmi {
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+		};
+	};
+
+	pinmux {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+					"spia", "spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			dta {
+				nvidia,pins = "dta", "dtd";
+				nvidia,function = "sdio2";
+			};
+			dtb {
+				nvidia,pins = "dtb", "dtc", "dte";
+				nvidia,function = "rsvd1";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uarta";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+					"ld3", "ld4", "ld5", "ld6", "ld7",
+					"ld8", "ld9", "ld10", "ld11", "ld12",
+					"ld13", "ld14", "ld15", "ld16", "ld17",
+					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
+					"lhs", "lm0", "lm1", "lpp", "lpw0",
+					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
+					"lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc", "spdi", "spdo", "uac";
+				nvidia,function = "rsvd2";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+					"cdev1", "cdev2", "dap1", "dtb", "gma",
+					"gmb", "gmc", "gmd", "gme", "gpu7",
+					"gpv", "i2cp", "pta", "rm", "slxa",
+					"slxk", "spia", "spib", "uac";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <0>;
+			};
+			conf_csus {
+				nvidia,pins = "csus", "spid", "spif";
+				nvidia,pull = <1>;
+				nvidia,tristate = <1>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+					"dtc", "dte", "dtf", "gpu", "sdio1",
+					"slxc", "slxd", "spdi", "spdo", "spig",
+					"uda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			conf_ddc {
+				nvidia,pins = "ddc", "dta", "dtd", "kbca",
+					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+					"sdc";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
+					"lvp0", "owc", "sdb";
+				nvidia,tristate = <1>;
+			};
+			conf_irrx {
+				nvidia,pins = "irrx", "irtx", "sdd", "spic",
+					"spie", "spih", "uaa", "uab", "uad",
+					"uca", "ucb";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <2>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+					"lvs", "pmc";
+				nvidia,tristate = <0>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <1>;
+			};
+		};
+
+		state_i2cmux_ddc: pinmux_i2cmux_ddc {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+			};
+		};
+
+		state_i2cmux_pta: pinmux_i2cmux_pta {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "i2c2";
+			};
+		};
+
+		state_i2cmux_idle: pinmux_i2cmux_idle {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+			};
+		};
+	};
+
+	i2s@70002800 {
+		status = "okay";
+	};
+
+	serial@70006300 {
+		status = "okay";
+	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
+
+	i2c@7000c000 {
+		clock-frequency = <400000>;
+		status = "okay";
+	};
+
+	i2c@7000c400 {
+		clock-frequency = <100000>;
+		status = "okay";
+	};
+
+	i2cmux {
+		compatible = "i2c-mux-pinctrl";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c-parent = <&{/i2c@7000c400}>;
+
+		pinctrl-names = "ddc", "pta", "idle";
+		pinctrl-0 = <&state_i2cmux_ddc>;
+		pinctrl-1 = <&state_i2cmux_pta>;
+		pinctrl-2 = <&state_i2cmux_idle>;
+
+		hdmi_ddc: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	i2c@7000d000 {
+		clock-frequency = <400000>;
+		status = "okay";
+
+		pmic: tps6586x@34 {
+			compatible = "ti,tps6586x";
+			reg = <0x34>;
+			interrupts = <0 86 0x4>;
+
+			ti,system-power-controller;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_5v0_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				sys_reg: sys {
+					regulator-name = "vdd_sys";
+					regulator-always-on;
+				};
+
+				sm0 {
+					regulator-name = "vdd_sys_sm0,vdd_core";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-always-on;
+				};
+
+				sm1 {
+					regulator-name = "vdd_sys_sm1,vdd_cpu";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				sm2_reg: sm2 {
+					regulator-name = "vdd_sys_sm2,vin_ldo*";
+					regulator-min-microvolt = <3700000>;
+					regulator-max-microvolt = <3700000>;
+					regulator-always-on;
+				};
+
+				ldo0 {
+					regulator-name = "vdd_ldo0,vddio_pex_clk";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				ldo1 {
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				ldo2 {
+					regulator-name = "vdd_ldo2,vdd_rtc";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+				};
+
+				ldo3 {
+					regulator-name = "vdd_ldo3,avdd_usb*";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo4 {
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo5 {
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+				};
+
+				ldo6 {
+					regulator-name = "vdd_ldo6,avdd_vdac";
+					/*
+					 * According to the Tegra 2 Automotive
+					 * DataSheet, a typical value for this
+					 * would be 2.8V, but the PMIC only
+					 * supports 2.85V.
+					 */
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+				};
+
+				hdmi_vdd_reg: ldo7 {
+					regulator-name = "vdd_ldo7,avdd_hdmi";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				hdmi_pll_reg: ldo8 {
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo9 {
+					regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
+					/*
+					 * According to the Tegra 2 Automotive
+					 * DataSheet, a typical value for this
+					 * would be 2.8V, but the PMIC only
+					 * supports 2.85V.
+					 */
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo_rtc {
+					regulator-name = "vdd_rtc_out";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+
+		temperature-sensor@4c {
+			compatible = "onnn,nct1008";
+			reg = <0x4c>;
+		};
+	};
+
+	pmc {
+		nvidia,invert-interrupt;
+	};
+
+	usb@c5008000 {
+		status = "okay";
+	};
+
+	sdhci@c8000600 {
+		cd-gpios = <&gpio 58 1>; /* gpio PH2 */
+		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+		bus-width = <4>;
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd_5v0_reg: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vdd_5v0";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-tec.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-tec.dts
new file mode 100644
index 000000000..4c1b08d76
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-tec.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+#include "tegra20-tamonten.dtsi"
+
+/ {
+	model = "Avionic Design Tamonten Evaluation Carrier";
+	compatible = "ad,tec", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+		sdhci0 = "/sdhci@c8000600";
+	};
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	host1x {
+		status = "okay";
+
+		dc@54200000 {
+			status = "okay";
+
+			rgb {
+				nvidia,panel = <&lcd_panel>;
+				status = "okay";
+			};
+		};
+	};
+
+	serial@70006300 {
+		clock-frequency = <216000000>;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5000000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+
+	lcd_panel: panel {
+		clock = <33260000>;
+		xres = <800>;
+		yres = <480>;
+		left-margin = <120>;
+		right-margin = <120>;
+		hsync-len = <16>;
+		lower-margin = <15>;
+		upper-margin = <15>;
+		vsync-len = <15>;
+
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 0 500000>;
+		nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+		nvidia,panel-timings = <0 0 0 0>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-trimslice.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-trimslice.dts
new file mode 100644
index 000000000..ee31476c1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-trimslice.dts
@@ -0,0 +1,64 @@
+/dts-v1/;
+
+#include "tegra20.dtsi"
+
+/ {
+	model = "Compulab TrimSlice board";
+	compatible = "compulab,trimslice", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5000000";
+		sdhci0 = "/sdhci@c8000600";
+		sdhci1 = "/sdhci@c8000000";
+	};
+
+	memory {
+		reg = <0x00000000 0x40000000>;
+	};
+
+	serial@70006000 {
+		clock-frequency = <216000000>;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	spi@7000c380 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5000000 {
+		nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+
+	sdhci@c8000000 {
+		status = "okay";
+		bus-width = <4>;
+	};
+
+	sdhci@c8000600 {
+		status = "okay";
+		cd-gpios = <&gpio 121 1>; /* gpio PP1 */
+		wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+		bus-width = <4>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-ventana.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-ventana.dts
new file mode 100644
index 000000000..1a526bab6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-ventana.dts
@@ -0,0 +1,91 @@
+/dts-v1/;
+
+#include "tegra20.dtsi"
+
+/ {
+	model = "NVIDIA Tegra20 Ventana evaluation board";
+	compatible = "nvidia,ventana", "nvidia,tegra20";
+
+	aliases {
+		usb0 = "/usb@c5008000";
+		sdhci0 = "/sdhci@c8000600";
+		sdhci1 = "/sdhci@c8000400";
+	};
+
+	memory {
+		reg = <0x00000000 0x40000000>;
+	};
+
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
+		};
+	};
+
+	serial@70006300 {
+		clock-frequency = < 216000000 >;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		status = "disabled";
+	};
+
+	usb@c5000000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+
+	sdhci@c8000400 {
+		status = "okay";
+		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		bus-width = <4>;
+	};
+
+	sdhci@c8000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	lcd_panel: panel {
+		clock = <72072000>;
+		xres = <1366>;
+		yres = <768>;
+		left-margin = <58>;
+		right-margin = <58>;
+		hsync-len = <58>;
+		lower-margin = <4>;
+		upper-margin = <4>;
+		vsync-len = <4>;
+		hsync-active-high;
+		vsync-active-high;
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 2 0>;
+		nvidia,backlight-enable-gpios = <&gpio 28 0>;	/* PD4 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>;	/* PB2 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
+		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
+		nvidia,panel-timings = <0 0 200 0 0>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20-whistler.dts b/qemu/roms/u-boot/arch/arm/dts/tegra20-whistler.dts
new file mode 100644
index 000000000..eb92264f9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20-whistler.dts
@@ -0,0 +1,73 @@
+/dts-v1/;
+
+#include "tegra20.dtsi"
+
+/ {
+	model = "NVIDIA Tegra20 Whistler evaluation board";
+	compatible = "nvidia,whistler", "nvidia,tegra20";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		usb0 = "/usb@c5008000";
+		sdhci0 = "/sdhci@c8000600";
+		sdhci1 = "/sdhci@c8000400";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = < 0x00000000 0x20000000 >;
+	};
+
+	serial@70006000 {
+		clock-frequency = < 216000000 >;
+	};
+
+	i2c@7000c000 {
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		clock-frequency = <100000>;
+
+		pmic@3c {
+			compatible = "maxim,max8907b";
+			reg = <0x3c>;
+
+			clk_32k: clock {
+				compatible = "fixed-clock";
+				/*
+				 * leave out for now due to CPP:
+				 * #clock-cells = <0>;
+				 */
+				clock-frequency = <32768>;
+			};
+		};
+	};
+
+	usb@c5000000 {
+		status = "disabled";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
+
+	sdhci@c8000400 {
+		status = "okay";
+		wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+		bus-width = <8>;
+	};
+
+	sdhci@c8000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra20.dtsi b/qemu/roms/u-boot/arch/arm/dts/tegra20.dtsi
new file mode 100644
index 000000000..380575058
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra20.dtsi
@@ -0,0 +1,349 @@
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra20";
+	interrupt-parent = <&intc>;
+
+	host1x {
+		compatible = "nvidia,tegra20-host1x", "simple-bus";
+		reg = <0x50000000 0x00024000>;
+		interrupts = <0 65 0x04   /* mpcore syncpt */
+			      0 67 0x04>; /* mpcore general */
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ranges = <0x54000000 0x54000000 0x04000000>;
+
+		/* video-encoding/decoding */
+		mpe {
+			reg = <0x54040000 0x00040000>;
+			interrupts = <0 68 0x04>;
+			status = "disabled";
+		};
+
+		/* video input */
+		vi {
+			reg = <0x54080000 0x00040000>;
+			interrupts = <0 69 0x04>;
+			status = "disabled";
+		};
+
+		/* EPP */
+		epp {
+			reg = <0x540c0000 0x00040000>;
+			interrupts = <0 70 0x04>;
+			status = "disabled";
+		};
+
+		/* ISP */
+		isp {
+			reg = <0x54100000 0x00040000>;
+			interrupts = <0 71 0x04>;
+			status = "disabled";
+		};
+
+		/* 2D engine */
+		gr2d {
+			reg = <0x54140000 0x00040000>;
+			interrupts = <0 72 0x04>;
+			status = "disabled";
+		};
+
+		/* 3D engine */
+		gr3d {
+			reg = <0x54180000 0x00040000>;
+			status = "disabled";
+		};
+
+		/* display controllers */
+		dc@54200000 {
+			compatible = "nvidia,tegra20-dc";
+			reg = <0x54200000 0x00040000>;
+			interrupts = <0 73 0x04>;
+			status = "disabled";
+
+			rgb {
+				status = "disabled";
+			};
+		};
+
+		dc@54240000 {
+			compatible = "nvidia,tegra20-dc";
+			reg = <0x54240000 0x00040000>;
+			interrupts = <0 74 0x04>;
+			status = "disabled";
+
+			rgb {
+				status = "disabled";
+			};
+		};
+
+		/* outputs */
+		hdmi {
+			compatible = "nvidia,tegra20-hdmi";
+			reg = <0x54280000 0x00040000>;
+			interrupts = <0 75 0x04>;
+			status = "disabled";
+		};
+
+		tvo {
+			compatible = "nvidia,tegra20-tvo";
+			reg = <0x542c0000 0x00040000>;
+			interrupts = <0 76 0x04>;
+			status = "disabled";
+		};
+
+		dsi {
+			compatible = "nvidia,tegra20-dsi";
+			reg = <0x54300000 0x00040000>;
+			status = "disabled";
+		};
+	};
+
+	intc: interrupt-controller@50041000 {
+		compatible = "nvidia,tegra20-gic";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = < 0x50041000 0x1000 >,
+		      < 0x50040100 0x0100 >;
+	};
+
+	tegra_car: clock@60006000 {
+		compatible = "nvidia,tegra20-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	apbdma: dma {
+		compatible = "nvidia,tegra20-apbdma";
+		reg = <0x6000a000 0x1200>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04>;
+	};
+
+	gpio: gpio@6000d000 {
+		compatible = "nvidia,tegra20-gpio";
+		reg = < 0x6000d000 0x1000 >;
+		interrupts = < 64 65 66 67 87 119 121 >;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	pinmux: pinmux@70000000 {
+		compatible = "nvidia,tegra20-pinmux";
+		reg = < 0x70000014 0x10    /* Tri-state registers */
+			0x70000080 0x20    /* Mux registers */
+			0x700000a0 0x14    /* Pull-up/down registers */
+			0x70000868 0xa8 >; /* Pad control registers */
+	};
+
+	das@70000c00 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-das";
+		reg = <0x70000c00 0x80>;
+	};
+
+	i2s@70002800 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2s";
+		reg = <0x70002800 0x200>;
+		interrupts = < 45 >;
+		dma-channel = < 2 >;
+	};
+
+	i2s@70002a00 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2s";
+		reg = <0x70002a00 0x200>;
+		interrupts = < 35 >;
+		dma-channel = < 1 >;
+	};
+
+	serial@70006000 {
+		compatible = "nvidia,tegra20-uart";
+		reg = <0x70006000 0x40>;
+		reg-shift = <2>;
+		interrupts = < 68 >;
+	};
+
+	serial@70006040 {
+		compatible = "nvidia,tegra20-uart";
+		reg = <0x70006040 0x40>;
+		reg-shift = <2>;
+		interrupts = < 69 >;
+	};
+
+	serial@70006200 {
+		compatible = "nvidia,tegra20-uart";
+		reg = <0x70006200 0x100>;
+		reg-shift = <2>;
+		interrupts = < 78 >;
+	};
+
+	serial@70006300 {
+		compatible = "nvidia,tegra20-uart";
+		reg = <0x70006300 0x100>;
+		reg-shift = <2>;
+		interrupts = < 122 >;
+	};
+
+	serial@70006400 {
+		compatible = "nvidia,tegra20-uart";
+		reg = <0x70006400 0x100>;
+		reg-shift = <2>;
+		interrupts = < 123 >;
+	};
+
+	nand: nand-controller@70008000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-nand";
+		reg = <0x70008000 0x100>;
+	};
+
+	pwm: pwm@7000a000 {
+		compatible = "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
+	};
+
+	i2c@7000c000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c";
+		reg = <0x7000C000 0x100>;
+		interrupts = < 70 >;
+		/* PERIPH_ID_I2C1, PLL_P_OUT3 */
+		clocks = <&tegra_car 12>, <&tegra_car 124>;
+	};
+
+	spi@7000c380 {
+		compatible = "nvidia,tegra20-sflash";
+		reg = <0x7000c380 0x80>;
+		interrupts = <0 39 0x04>;
+		nvidia,dma-request-selector = <&apbdma 11>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		/* PERIPH_ID_SPI1, PLLP_OUT0 */
+		clocks = <&tegra_car 43>;
+	};
+
+	i2c@7000c400 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c";
+		reg = <0x7000C400 0x100>;
+		interrupts = < 116 >;
+		/* PERIPH_ID_I2C2, PLL_P_OUT3 */
+		clocks = <&tegra_car 54>, <&tegra_car 124>;
+	};
+
+	i2c@7000c500 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c";
+		reg = <0x7000C500 0x100>;
+		interrupts = < 124 >;
+		/* PERIPH_ID_I2C3, PLL_P_OUT3 */
+		clocks = <&tegra_car 67>, <&tegra_car 124>;
+	};
+
+	i2c@7000d000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-i2c-dvc";
+		reg = <0x7000D000 0x200>;
+		interrupts = < 85 >;
+		/* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
+		clocks = <&tegra_car 47>, <&tegra_car 124>;
+	};
+
+	kbc@7000e200 {
+		compatible = "nvidia,tegra20-kbc";
+		reg = <0x7000e200 0x0078>;
+	};
+
+	emc@7000f400 {
+		#address-cells = < 1 >;
+		#size-cells = < 0 >;
+		compatible = "nvidia,tegra20-emc";
+		reg = <0x7000f400 0x200>;
+	};
+
+	usb@c5000000 {
+		compatible = "nvidia,tegra20-ehci", "usb-ehci";
+		reg = <0xc5000000 0x4000>;
+		interrupts = < 52 >;
+		phy_type = "utmi";
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
+		nvidia,has-legacy-mode;
+	};
+
+	usb@c5004000 {
+		compatible = "nvidia,tegra20-ehci", "usb-ehci";
+		reg = <0xc5004000 0x4000>;
+		interrupts = < 53 >;
+		phy_type = "ulpi";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
+	};
+
+	usb@c5008000 {
+		compatible = "nvidia,tegra20-ehci", "usb-ehci";
+		reg = <0xc5008000 0x4000>;
+		interrupts = < 129 >;
+		phy_type = "utmi";
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
+	};
+
+	sdhci@c8000000 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000000 0x200>;
+		interrupts = <0 14 0x04>;
+		clocks = <&tegra_car 14>;
+		status = "disabled";
+	};
+
+	sdhci@c8000200 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000200 0x200>;
+		interrupts = <0 15 0x04>;
+		clocks = <&tegra_car 9>;
+		status = "disabled";
+	};
+
+	sdhci@c8000400 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000400 0x200>;
+		interrupts = <0 19 0x04>;
+		clocks = <&tegra_car 69>;
+		status = "disabled";
+	};
+
+	sdhci@c8000600 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000600 0x200>;
+		interrupts = <0 31 0x04>;
+		clocks = <&tegra_car 15>;
+		status = "disabled";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra30-beaver.dts b/qemu/roms/u-boot/arch/arm/dts/tegra30-beaver.dts
new file mode 100644
index 000000000..a7cc93e93
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra30-beaver.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+#include "tegra30.dtsi"
+
+/ {
+	model = "NVIDIA Beaver";
+	compatible = "nvidia,beaver", "nvidia,tegra30";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+		sdhci0 = "/sdhci@78000600";
+		sdhci1 = "/sdhci@78000000";
+		usb0 = "/usb@7d008000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x7ff00000>;
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+		spi-flash@1 {
+			compatible = "winbond,w25q32";
+			reg = <1>;
+			spi-max-frequency = <20000000>;
+		};
+	};
+
+	sdhci@78000000 {
+		status = "okay";
+		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+		power-gpios = <&gpio 31 0>; /* gpio PD7 */
+		bus-width = <4>;
+	};
+
+	sdhci@78000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	usb@7d008000 {
+		nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
+		status = "okay";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra30-cardhu.dts b/qemu/roms/u-boot/arch/arm/dts/tegra30-cardhu.dts
new file mode 100644
index 000000000..ea2cf76ff
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra30-cardhu.dts
@@ -0,0 +1,72 @@
+/dts-v1/;
+
+#include "tegra30.dtsi"
+
+/ {
+	model = "NVIDIA Cardhu";
+	compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+	aliases {
+		i2c0 = "/i2c@7000d000";
+		i2c1 = "/i2c@7000c000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+		sdhci0 = "/sdhci@78000600";
+		sdhci1 = "/sdhci@78000000";
+		usb0 = "/usb@7d008000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	spi@7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
+	sdhci@78000000 {
+		status = "okay";
+		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+		power-gpios = <&gpio 31 0>; /* gpio PD7 */
+		bus-width = <4>;
+	};
+
+	sdhci@78000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	usb@7d008000 {
+		nvidia,vbus-gpio = <&gpio 236 0>;	/* PDD4 */
+		status = "okay";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra30-tamonten.dtsi b/qemu/roms/u-boot/arch/arm/dts/tegra30-tamonten.dtsi
new file mode 100644
index 000000000..50d576231
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra30-tamonten.dtsi
@@ -0,0 +1,69 @@
+#include "tegra30.dtsi"
+
+/ {
+	model = "Avionic Design Tamonten NG";
+	compatible = "ad,tamonten-ng", "nvidia,tegra30";
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	aliases {
+		i2c0 = "/i2c@7000c000";
+		i2c1 = "/i2c@7000c700";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000d000";
+		sdhci0 = "/sdhci@78000600";
+		sdhci1 = "/sdhci@78000400";
+		sdhci2 = "/sdhci@78000000";
+		usb0 = "/usb@7d008000";
+	};
+
+	/* GEN1 */
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* GEN2 */
+	i2c@7000c400 {
+		clock-frequency = <100000>;
+	};
+
+	/* CAM */
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* DDC */
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* PWR */
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	/* SD slot on the base board */
+	sdhci@78000400 {
+		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+		wp-gpios = <&gpio 67 0>; /* gpio PI3 */
+		bus-width = <4>;
+	};
+
+	/* EMMC on the COM module */
+	sdhci@78000600 {
+		status = "okay";
+		bus-width = <8>;
+	};
+
+	usb@7d008000 {
+		status = "okay";
+	};
+
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra30-tec-ng.dts b/qemu/roms/u-boot/arch/arm/dts/tegra30-tec-ng.dts
new file mode 100644
index 000000000..8a69e818c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra30-tec-ng.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "tegra30-tamonten.dtsi"
+
+/ {
+	model = "Avionic Design Tamonten™ NG Evaluation Carrier";
+	compatible = "ad,tec-ng", "nvidia,tegra30";
+
+	/* GEN2 */
+	i2c@7000c400 {
+		status = "okay";
+	};
+
+	/* SD card slot */
+	sdhci@78000400 {
+		status = "okay";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/tegra30.dtsi b/qemu/roms/u-boot/arch/arm/dts/tegra30.dtsi
new file mode 100644
index 000000000..fee1c36ef
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/tegra30.dtsi
@@ -0,0 +1,246 @@
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra30";
+
+	tegra_car: clock {
+		compatible = "nvidia,tegra30-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	apbdma: dma {
+		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
+		reg = <0x6000a000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+		clocks = <&tegra_car 34>;
+	};
+
+	gpio: gpio {
+		compatible = "nvidia,tegra30-gpio";
+		reg = <0x6000d000 0x1000>;
+		interrupts = <0 32 0x04
+			      0 33 0x04
+			      0 34 0x04
+			      0 35 0x04
+			      0 55 0x04
+			      0 87 0x04
+			      0 89 0x04
+			      0 125 0x04>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+	};
+
+	i2c@7000c000 {
+		compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000c000 0x100>;
+		interrupts = <0 38 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 12>, <&tegra_car 182>;
+		clock-names = "div-clk", "fast-clk";
+		status = "disabled";
+	};
+
+	i2c@7000c400 {
+		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000c400 0x100>;
+		interrupts = <0 84 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 54>, <&tegra_car 182>;
+		clock-names = "div-clk", "fast-clk";
+		status = "disabled";
+	};
+
+	i2c@7000c500 {
+		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000c500 0x100>;
+		interrupts = <0 92 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 67>, <&tegra_car 182>;
+		clock-names = "div-clk", "fast-clk";
+		status = "disabled";
+	};
+
+	i2c@7000c700 {
+		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000c700 0x100>;
+		interrupts = <0 120 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 103>, <&tegra_car 182>;
+		clock-names = "div-clk", "fast-clk";
+		status = "disabled";
+	};
+
+	i2c@7000d000 {
+		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+		reg = <0x7000d000 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>, <&tegra_car 182>;
+		clock-names = "div-clk", "fast-clk";
+		status = "disabled";
+	};
+
+	spi@7000d400 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 41>;
+		status = "disabled";
+	};
+
+	spi@7000d600 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 44>;
+		status = "disabled";
+	};
+
+	spi@7000d800 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d480 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 46>;
+		status = "disabled";
+	};
+
+	spi@7000da00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 68>;
+		status = "disabled";
+	};
+
+	spi@7000dc00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 104>;
+		status = "disabled";
+	};
+
+	spi@7000de00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 105>;
+		status = "disabled";
+	};
+
+	sdhci@78000000 {
+		compatible = "nvidia,tegra30-sdhci";
+		reg = <0x78000000 0x200>;
+		interrupts = <0 14 0x04>;
+		clocks = <&tegra_car 14>;
+		status = "disabled";
+	};
+
+	sdhci@78000200 {
+		compatible = "nvidia,tegra30-sdhci";
+		reg = <0x78000200 0x200>;
+		interrupts = <0 15 0x04>;
+		clocks = <&tegra_car 9>;
+		status = "disabled";
+	};
+
+	sdhci@78000400 {
+		compatible = "nvidia,tegra30-sdhci";
+		reg = <0x78000400 0x200>;
+		interrupts = <0 19 0x04>;
+		clocks = <&tegra_car 69>;
+		status = "disabled";
+	};
+
+	sdhci@78000600 {
+		compatible = "nvidia,tegra30-sdhci";
+		reg = <0x78000600 0x200>;
+		interrupts = <0 31 0x04>;
+		clocks = <&tegra_car 15>;
+		status = "disabled";
+	};
+
+	usb@7d000000 {
+		compatible = "nvidia,tegra30-ehci";
+		reg = <0x7d000000 0x4000>;
+		interrupts = <52>;
+		phy_type = "utmi";
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
+		status = "disabled";
+	};
+
+	usb@7d004000 {
+		compatible = "nvidia,tegra30-ehci";
+		reg = <0x7d004000 0x4000>;
+		interrupts = <53>;
+		phy_type = "hsic";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
+		status = "disabled";
+	};
+
+	usb@7d008000 {
+		compatible = "nvidia,tegra30-ehci";
+		reg = <0x7d008000 0x4000>;
+		interrupts = <129>;
+		phy_type = "utmi";
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
+		status = "disabled";
+	};
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/zynq-7000.dtsi b/qemu/roms/u-boot/arch/arm/dts/zynq-7000.dtsi
new file mode 100644
index 000000000..f20b8bd60
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/zynq-7000.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Xilinx Zynq 7000 DTSI
+ * Describes the hardware common to all Zynq 7000-based boards.
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "xlnx,zynq-7000";
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/zynq-microzed.dts b/qemu/roms/u-boot/arch/arm/dts/zynq-microzed.dts
new file mode 100644
index 000000000..6da71c116
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/zynq-microzed.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx MicroZED board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq MicroZED Board";
+	compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/zynq-zc702.dts b/qemu/roms/u-boot/arch/arm/dts/zynq-zc702.dts
new file mode 100644
index 000000000..667dc2825
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/zynq-zc702.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC702 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC702 Board";
+	compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/zynq-zc706.dts b/qemu/roms/u-boot/arch/arm/dts/zynq-zc706.dts
new file mode 100644
index 000000000..526fc8888
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/zynq-zc706.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC706 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC706 Board";
+	compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/zynq-zc770-xm010.dts b/qemu/roms/u-boot/arch/arm/dts/zynq-zc770-xm010.dts
new file mode 100644
index 000000000..8b542a109
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/zynq-zc770-xm010.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM010 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC770 XM010 Board";
+	compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/zynq-zc770-xm012.dts b/qemu/roms/u-boot/arch/arm/dts/zynq-zc770-xm012.dts
new file mode 100644
index 000000000..0379a0706
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/zynq-zc770-xm012.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM012 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC770 XM012 Board";
+	compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/zynq-zc770-xm013.dts b/qemu/roms/u-boot/arch/arm/dts/zynq-zc770-xm013.dts
new file mode 100644
index 000000000..a4f9e05fc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/zynq-zc770-xm013.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZC770 XM013 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZC770 XM013 Board";
+	compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+};
diff --git a/qemu/roms/u-boot/arch/arm/dts/zynq-zed.dts b/qemu/roms/u-boot/arch/arm/dts/zynq-zed.dts
new file mode 100644
index 000000000..91a5deba4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/dts/zynq-zed.dts
@@ -0,0 +1,14 @@
+/*
+ * Xilinx ZED board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq ZED Board";
+	compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+};
diff --git a/qemu/roms/u-boot/arch/arm/imx-common/Makefile b/qemu/roms/u-boot/arch/arm/imx-common/Makefile
new file mode 100644
index 000000000..b04dfbbcb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/imx-common/Makefile
@@ -0,0 +1,84 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610))
+obj-y	= iomux-v3.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
+obj-y	+= timer.o cpu.o speed.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
+obj-y	+= misc.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx6))
+obj-$(CONFIG_CMD_SATA) += sata.o
+endif
+obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
+obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
+
+quiet_cmd_cpp_cfg = CFGS    $@
+      cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $<
+
+IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%).cfgtmp
+
+$(IMX_CONFIG): %.cfgtmp: % FORCE
+	$(Q)mkdir -p $(dir $@)
+	$(call if_changed_dep,cpp_cfg)
+
+quiet_cmd_mkimage = MKIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
+
+MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
+	-e $(CONFIG_SYS_TEXT_BASE)
+
+u-boot.imx: u-boot.bin $(IMX_CONFIG) FORCE
+	$(call if_changed,mkimage)
+
+ifeq ($(CONFIG_OF_SEPARATE),y)
+MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
+	-e $(CONFIG_SYS_TEXT_BASE)
+
+u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) FORCE
+	$(call if_changed,mkimage)
+endif
+
+MKIMAGEFLAGS_SPL = -n $(filter-out $< $(PHONY),$^) -T imximage \
+	-e $(CONFIG_SPL_TEXT_BASE)
+
+SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE
+	$(call if_changed,mkimage)
+
+MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
+		-e $(CONFIG_SYS_TEXT_BASE) -C none
+
+u-boot.uim: u-boot.bin FORCE
+	$(call if_changed,mkimage)
+
+OBJCOPYFLAGS += -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
+append = cat $(filter-out $< $(PHONY), $^) >> $@
+
+quiet_cmd_pad_cat = CAT     $@
+cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
+
+u-boot-with-spl.imx: SPL u-boot.uim FORCE
+	$(call if_changed,pad_cat)
+
+u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
+	$(call if_changed,pad_cat)
+
+quiet_cmd_u-boot-nand-spl_imx = GEN     $@
+cmd_u-boot-nand-spl_imx = (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
+	dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
+
+spl/u-boot-nand-spl.imx: SPL FORCE
+	$(call if_changed,u-boot-nand-spl_imx)
+
+targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx)
diff --git a/qemu/roms/u-boot/arch/arm/imx-common/cmd_bmode.c b/qemu/roms/u-boot/arch/arm/imx-common/cmd_bmode.c
new file mode 100644
index 000000000..841b1d31c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/imx-common/cmd_bmode.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/imx-common/boot_mode.h>
+#include <malloc.h>
+#include <command.h>
+
+static const struct boot_mode *modes[2];
+
+static const struct boot_mode *search_modes(char *arg)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(modes); i++) {
+		const struct boot_mode *p = modes[i];
+		if (p) {
+			while (p->name) {
+				if (!strcmp(p->name, arg))
+					return p;
+				p++;
+			}
+		}
+	}
+	return NULL;
+}
+
+static int create_usage(char *dest)
+{
+	int i;
+	int size = 0;
+
+	for (i = 0; i < ARRAY_SIZE(modes); i++) {
+		const struct boot_mode *p = modes[i];
+		if (p) {
+			while (p->name) {
+				int len = strlen(p->name);
+				if (dest) {
+					memcpy(dest, p->name, len);
+					dest += len;
+					*dest++ = '|';
+				}
+				size += len + 1;
+				p++;
+			}
+		}
+	}
+	if (dest)
+		memcpy(dest - 1, " [noreset]", 11);	/* include trailing 0 */
+	size += 10;
+	return size;
+}
+
+static int do_boot_mode(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	const struct boot_mode *p;
+	int reset_requested = 1;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	p = search_modes(argv[1]);
+	if (!p)
+		return CMD_RET_USAGE;
+	if (argc == 3) {
+		if (strcmp(argv[2], "noreset"))
+			return CMD_RET_USAGE;
+		reset_requested = 0;
+	}
+
+	boot_mode_apply(p->cfg_val);
+	if (reset_requested && p->cfg_val)
+		do_reset(NULL, 0, 0, NULL);
+	return 0;
+}
+
+U_BOOT_CMD(
+	bmode, 3, 0, do_boot_mode,
+	NULL,
+	"");
+
+void add_board_boot_modes(const struct boot_mode *p)
+{
+	int size;
+	char *dest;
+
+	cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
+
+	if (entry->usage) {
+		free(entry->usage);
+		entry->usage = NULL;
+	}
+
+	modes[0] = p;
+	modes[1] = soc_boot_modes;
+	size = create_usage(NULL);
+	dest = malloc(size);
+	if (dest) {
+		create_usage(dest);
+		entry->usage = dest;
+	}
+}
diff --git a/qemu/roms/u-boot/arch/arm/imx-common/cmd_hdmidet.c b/qemu/roms/u-boot/arch/arm/imx-common/cmd_hdmidet.c
new file mode 100644
index 000000000..e9fd9553c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/imx-common/cmd_hdmidet.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/io.h>
+
+static int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	return (readb(&hdmi->phy_stat0) & HDMI_DVI_STAT) ? 0 : 1;
+}
+
+U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet,
+	"detect HDMI monitor",
+	""
+);
diff --git a/qemu/roms/u-boot/arch/arm/imx-common/cpu.c b/qemu/roms/u-boot/arch/arm/imx-common/cpu.c
new file mode 100644
index 000000000..a77c4decc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/imx-common/cpu.c
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <ipu_pixfmt.h>
+
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+char *get_reset_cause(void)
+{
+	u32 cause;
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+	cause = readl(&src_regs->srsr);
+	writel(cause, &src_regs->srsr);
+
+	switch (cause) {
+	case 0x00001:
+	case 0x00011:
+		return "POR";
+	case 0x00004:
+		return "CSU";
+	case 0x00008:
+		return "IPP USER";
+	case 0x00010:
+		return "WDOG";
+	case 0x00020:
+		return "JTAG HIGH-Z";
+	case 0x00040:
+		return "JTAG SW";
+	case 0x10000:
+		return "WARM BOOT";
+	default:
+		return "unknown reset";
+	}
+}
+
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53)
+#define MEMCTL_BASE	ESDCTL_BASE_ADDR
+#else
+#define MEMCTL_BASE	MMDC_P0_BASE_ADDR
+#endif
+static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
+static const unsigned char bank_lookup[] = {3, 2};
+
+struct esd_mmdc_regs {
+	uint32_t	ctl;
+	uint32_t	pdc;
+	uint32_t	otc;
+	uint32_t	cfg0;
+	uint32_t	cfg1;
+	uint32_t	cfg2;
+	uint32_t	misc;
+	uint32_t	scr;
+	uint32_t	ref;
+	uint32_t	rsvd1;
+	uint32_t	rsvd2;
+	uint32_t	rwd;
+	uint32_t	or;
+	uint32_t	mrr;
+	uint32_t	cfg3lp;
+	uint32_t	mr4;
+};
+
+#define ESD_MMDC_CTL_GET_ROW(mdctl)	((ctl >> 24) & 7)
+#define ESD_MMDC_CTL_GET_COLUMN(mdctl)	((ctl >> 20) & 7)
+#define ESD_MMDC_CTL_GET_WIDTH(mdctl)	((ctl >> 16) & 3)
+#define ESD_MMDC_CTL_GET_CS1(mdctl)	((ctl >> 30) & 1)
+#define ESD_MMDC_MISC_GET_BANK(mdmisc)	((misc >> 5) & 1)
+
+unsigned imx_ddr_size(void)
+{
+	struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
+	unsigned ctl = readl(&mem->ctl);
+	unsigned misc = readl(&mem->misc);
+	int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */
+
+	bits += ESD_MMDC_CTL_GET_ROW(ctl);
+	bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
+	bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
+	bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
+	bits += ESD_MMDC_CTL_GET_CS1(ctl);
+	return 1 << bits;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+
+const char *get_imx_type(u32 imxtype)
+{
+	switch (imxtype) {
+	case MXC_CPU_MX6Q:
+		return "6Q";	/* Quad-core version of the mx6 */
+	case MXC_CPU_MX6D:
+		return "6D";	/* Dual-core version of the mx6 */
+	case MXC_CPU_MX6DL:
+		return "6DL";	/* Dual Lite version of the mx6 */
+	case MXC_CPU_MX6SOLO:
+		return "6SOLO";	/* Solo version of the mx6 */
+	case MXC_CPU_MX6SL:
+		return "6SL";	/* Solo-Lite version of the mx6 */
+	case MXC_CPU_MX51:
+		return "51";
+	case MXC_CPU_MX53:
+		return "53";
+	default:
+		return "??";
+	}
+}
+
+int print_cpuinfo(void)
+{
+	u32 cpurev;
+
+	cpurev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
+		get_imx_type((cpurev & 0xFF000) >> 12),
+		(cpurev & 0x000F0) >> 4,
+		(cpurev & 0x0000F) >> 0,
+		mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("Reset cause: %s\n", get_reset_cause());
+	return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+	rc = fecmxc_initialize(bis);
+#endif
+
+	return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+u32 get_ahb_clk(void)
+{
+	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg, ahb_podf;
+
+	reg = __raw_readl(&imx_ccm->cbcdr);
+	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+	return get_periph_clk() / (ahb_podf + 1);
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+void arch_preboot_os(void)
+{
+	/* disable video before launching O/S */
+	ipuv3_fb_shutdown();
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/imx-common/i2c-mxv7.c b/qemu/roms/u-boot/arch/arm/imx-common/i2c-mxv7.c
new file mode 100644
index 000000000..a58087399
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/imx-common/i2c-mxv7.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <watchdog.h>
+
+static int force_idle_bus(void *priv)
+{
+	int i;
+	int sda, scl;
+	ulong elapsed, start_time;
+	struct i2c_pads_info *p = (struct i2c_pads_info *)priv;
+	int ret = 0;
+
+	gpio_direction_input(p->sda.gp);
+	gpio_direction_input(p->scl.gp);
+
+	imx_iomux_v3_setup_pad(p->sda.gpio_mode);
+	imx_iomux_v3_setup_pad(p->scl.gpio_mode);
+
+	sda = gpio_get_value(p->sda.gp);
+	scl = gpio_get_value(p->scl.gp);
+	if ((sda & scl) == 1)
+		goto exit;		/* Bus is idle already */
+
+	printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__,
+		sda, scl, p->sda.gp, p->scl.gp);
+	/* Send high and low on the SCL line */
+	for (i = 0; i < 9; i++) {
+		gpio_direction_output(p->scl.gp, 0);
+		udelay(50);
+		gpio_direction_input(p->scl.gp);
+		udelay(50);
+	}
+	start_time = get_timer(0);
+	for (;;) {
+		sda = gpio_get_value(p->sda.gp);
+		scl = gpio_get_value(p->scl.gp);
+		if ((sda & scl) == 1)
+			break;
+		WATCHDOG_RESET();
+		elapsed = get_timer(start_time);
+		if (elapsed > (CONFIG_SYS_HZ / 5)) {	/* .2 seconds */
+			ret = -EBUSY;
+			printf("%s: failed to clear bus, sda=%d scl=%d\n",
+					__func__, sda, scl);
+			break;
+		}
+	}
+exit:
+	imx_iomux_v3_setup_pad(p->sda.i2c_mode);
+	imx_iomux_v3_setup_pad(p->scl.i2c_mode);
+	return ret;
+}
+
+static void * const i2c_bases[] = {
+	(void *)I2C1_BASE_ADDR,
+	(void *)I2C2_BASE_ADDR,
+#ifdef I2C3_BASE_ADDR
+	(void *)I2C3_BASE_ADDR,
+#endif
+};
+
+/* i2c_index can be from 0 - 2 */
+void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+		struct i2c_pads_info *p)
+{
+	if (i2c_index >= ARRAY_SIZE(i2c_bases))
+		return;
+	/* Enable i2c clock */
+	enable_i2c_clk(1, i2c_index);
+	/* Make sure bus is idle */
+	force_idle_bus(p);
+	bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr,
+			force_idle_bus, p);
+}
diff --git a/qemu/roms/u-boot/arch/arm/imx-common/iomux-v3.c b/qemu/roms/u-boot/arch/arm/imx-common/iomux-v3.c
new file mode 100644
index 000000000..b59b80283
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/imx-common/iomux-v3.c
@@ -0,0 +1,57 @@
+/*
+ * Based on the iomux-v3.c from Linux kernel:
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                       <armlinux@phytec.de>
+ *
+ * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/iomux-v3.h>
+
+static void *base = (void *)IOMUXC_BASE_ADDR;
+
+/*
+ * configures a single pad in the iomuxer
+ */
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+{
+	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+	u32 sel_input_ofs =
+		(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+	u32 sel_input =
+		(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+	u32 pad_ctrl_ofs =
+		(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
+	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+	if (mux_ctrl_ofs)
+		__raw_writel(mux_mode, base + mux_ctrl_ofs);
+
+	if (sel_input_ofs)
+		__raw_writel(sel_input, base + sel_input_ofs);
+
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+	if (!(pad_ctrl & NO_PAD_CTRL))
+		__raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
+			base + pad_ctrl_ofs);
+#else
+	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+		__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#endif
+}
+
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+				      unsigned count)
+{
+	iomux_v3_cfg_t const *p = pad_list;
+	int i;
+
+	for (i = 0; i < count; i++)
+		imx_iomux_v3_setup_pad(*p++);
+}
diff --git a/qemu/roms/u-boot/arch/arm/imx-common/misc.c b/qemu/roms/u-boot/arch/arm/imx-common/misc.c
new file mode 100644
index 000000000..dbecf4e43
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/imx-common/misc.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2013 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/imx-common/regs-common.h>
+
+/* 1 second delay should be plenty of time for block reset. */
+#define	RESET_MAX_TIMEOUT	1000000
+
+#define	MXS_BLOCK_SFTRST	(1 << 31)
+#define	MXS_BLOCK_CLKGATE	(1 << 30)
+
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
+								int timeout)
+{
+	while (--timeout) {
+		if ((readl(&reg->reg) & mask) == mask)
+			break;
+		udelay(1);
+	}
+
+	return !timeout;
+}
+
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
+								int timeout)
+{
+	while (--timeout) {
+		if ((readl(&reg->reg) & mask) == 0)
+			break;
+		udelay(1);
+	}
+
+	return !timeout;
+}
+
+int mxs_reset_block(struct mxs_register_32 *reg)
+{
+	/* Clear SFTRST */
+	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
+
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+		return 1;
+
+	/* Clear CLKGATE */
+	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
+
+	/* Set SFTRST */
+	writel(MXS_BLOCK_SFTRST, &reg->reg_set);
+
+	/* Wait for CLKGATE being set */
+	if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+		return 1;
+
+	/* Clear SFTRST */
+	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
+
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+		return 1;
+
+	/* Clear CLKGATE */
+	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
+
+	if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+		return 1;
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/imx-common/sata.c b/qemu/roms/u-boot/arch/arm/imx-common/sata.c
new file mode 100644
index 000000000..2e694866e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/imx-common/sata.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/arch/iomux.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+
+	int ret = enable_sata_clock();
+	if (ret)
+		return ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/imx-common/speed.c b/qemu/roms/u-boot/arch/arm/imx-common/speed.c
new file mode 100644
index 000000000..26132bf71
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/imx-common/speed.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_USDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+#else
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#else
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+#else
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#endif
+#endif
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/imx-common/timer.c b/qemu/roms/u-boot/arch/arm/imx-common/timer.c
new file mode 100644
index 000000000..c63f78f68
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/imx-common/timer.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+/* General purpose timers registers */
+struct mxc_gpt {
+	unsigned int control;
+	unsigned int prescaler;
+	unsigned int status;
+	unsigned int nouse[6];
+	unsigned int counter;
+};
+
+static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR		(1 << 15)	/* Software reset */
+#define GPTCR_FRR		(1 << 9)	/* Freerun / restart */
+#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source */
+#define GPTCR_TEN		1		/* Timer enable */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, MXC_CLK32);
+
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+	usec = usec * MXC_CLK32 + 999999;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+int timer_init(void)
+{
+	int i;
+
+	/* setup GP Timer 1 */
+	__raw_writel(GPTCR_SWR, &cur_gpt->control);
+
+	/* We have no udelay by now */
+	for (i = 0; i < 100; i++)
+		__raw_writel(0, &cur_gpt->control);
+
+	__raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
+
+	/* Freerun Mode, PERCLK1 input */
+	i = __raw_readl(&cur_gpt->control);
+	__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
+
+	gd->arch.tbl = __raw_readl(&cur_gpt->counter);
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
+
+	/* increment tbu if tbl has rolled over */
+	if (now < gd->arch.tbl)
+		gd->arch.tbu++;
+	gd->arch.tbl = now;
+	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+ulong get_timer_masked(void)
+{
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return MXC_CLK32;
+}
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-a320/a320.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-a320/a320.h
new file mode 100644
index 000000000..f2db8e106
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-a320/a320.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __A320_H
+#define __A320_H
+
+/*
+ * Hardware register bases
+ */
+#define CONFIG_FTSMC020_BASE	0x90200000	/* Static Memory Controller */
+#define CONFIG_DEBUG_LED	0x902ffffc	/* Debug LED */
+#define CONFIG_FTSDMC020_BASE	0x90300000	/* SDRAM Controller */
+#define CONFIG_FTMAC100_BASE	0x90900000	/* Ethernet */
+#define CONFIG_FTPMU010_BASE	0x98100000	/* Power Management Unit */
+#define CONFIG_FTTMR010_BASE	0x98400000	/* Timer */
+#define CONFIG_FTRTC010_BASE	0x98600000	/* Real Time Clock*/
+
+#endif	/* __A320_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock.h
new file mode 100644
index 000000000..763745754
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock.h
@@ -0,0 +1,113 @@
+/*
+ * clock.h
+ *
+ * clock header
+ *
+ * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CLOCKS_H_
+#define _CLOCKS_H_
+
+#include <asm/arch/clocks_am33xx.h>
+
+#ifdef CONFIG_TI81XX
+#include <asm/arch/clock_ti81xx.h>
+#endif
+
+#define LDELAY 1000000
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+
+struct dpll_params {
+	u32 m;
+	u32 n;
+	s8 m2;
+	s8 m3;
+	s8 m4;
+	s8 m5;
+	s8 m6;
+};
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_dpll;
+	u32 cm_div_m5_dpll;
+	u32 cm_div_m6_dpll;
+};
+
+extern const struct dpll_regs dpll_mpu_regs;
+extern const struct dpll_regs dpll_core_regs;
+extern const struct dpll_regs dpll_per_regs;
+extern const struct dpll_regs dpll_ddr_regs;
+
+extern struct cm_wkuppll *const cmwkup;
+
+const struct dpll_params *get_dpll_mpu_params(void);
+const struct dpll_params *get_dpll_core_params(void);
+const struct dpll_params *get_dpll_per_params(void);
+const struct dpll_params *get_dpll_ddr_params(void);
+void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
+void prcm_init(void);
+void enable_basic_clocks(void);
+void do_enable_clocks(u32 *const *, u32 *const *, u8);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
new file mode 100644
index 000000000..f0699229a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
@@ -0,0 +1,142 @@
+/*
+ * ti81xx.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef _CLOCK_TI81XX_H_
+#define _CLOCK_TI81XX_H_
+
+#define PRCM_MOD_EN     0x2
+
+#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
+#define CM_ALWON_BASE   (PRCM_BASE + 0x1400)
+
+struct cm_def {
+	unsigned int resv0[2];
+	unsigned int l3fastclkstctrl;
+	unsigned int resv1[1];
+	unsigned int pciclkstctrl;
+	unsigned int resv2[1];
+	unsigned int ducaticlkstctrl;
+	unsigned int resv3[1];
+	unsigned int emif0clkctrl;
+	unsigned int emif1clkctrl;
+	unsigned int dmmclkctrl;
+	unsigned int fwclkctrl;
+	unsigned int resv4[10];
+	unsigned int usbclkctrl;
+	unsigned int resv5[1];
+	unsigned int sataclkctrl;
+	unsigned int resv6[4];
+	unsigned int ducaticlkctrl;
+	unsigned int pciclkctrl;
+};
+
+struct cm_alwon {
+	unsigned int l3slowclkstctrl;
+	unsigned int ethclkstctrl;
+	unsigned int l3medclkstctrl;
+	unsigned int mmu_clkstctrl;
+	unsigned int mmucfg_clkstctrl;
+	unsigned int ocmc0clkstctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int vcpclkstctrl;
+#elif defined(CONFIG_TI816X)
+	unsigned int ocmc1clkstctrl;
+#endif
+	unsigned int mpuclkstctrl;
+	unsigned int sysclk4clkstctrl;
+	unsigned int sysclk5clkstctrl;
+	unsigned int sysclk6clkstctrl;
+	unsigned int rtcclkstctrl;
+	unsigned int l3fastclkstctrl;
+	unsigned int resv0[67];
+	unsigned int mcasp0clkctrl;
+	unsigned int mcasp1clkctrl;
+	unsigned int mcasp2clkctrl;
+	unsigned int mcbspclkctrl;
+	unsigned int uart0clkctrl;
+	unsigned int uart1clkctrl;
+	unsigned int uart2clkctrl;
+	unsigned int gpio0clkctrl;
+	unsigned int gpio1clkctrl;
+	unsigned int i2c0clkctrl;
+	unsigned int i2c1clkctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int mcasp345clkctrl;
+	unsigned int atlclkctrl;
+	unsigned int mlbclkctrl;
+	unsigned int pataclkctrl;
+	unsigned int resv1[1];
+	unsigned int uart3clkctrl;
+	unsigned int uart4clkctrl;
+	unsigned int uart5clkctrl;
+#elif defined(CONFIG_TI816X)
+	unsigned int resv1[1];
+	unsigned int timer1clkctrl;
+	unsigned int timer2clkctrl;
+	unsigned int timer3clkctrl;
+	unsigned int timer4clkctrl;
+	unsigned int timer5clkctrl;
+	unsigned int timer6clkctrl;
+	unsigned int timer7clkctrl;
+#endif
+	unsigned int wdtimerclkctrl;
+	unsigned int spiclkctrl;
+	unsigned int mailboxclkctrl;
+	unsigned int spinboxclkctrl;
+	unsigned int mmudataclkctrl;
+	unsigned int resv2[2];
+	unsigned int mmucfgclkctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int resv3[2];
+#elif defined(CONFIG_TI816X)
+	unsigned int resv3[1];
+	unsigned int sdioclkctrl;
+#endif
+	unsigned int ocmc0clkctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int vcpclkctrl;
+#elif defined(CONFIG_TI816X)
+	unsigned int ocmc1clkctrl;
+#endif
+	unsigned int resv4[2];
+	unsigned int controlclkctrl;
+	unsigned int resv5[2];
+	unsigned int gpmcclkctrl;
+	unsigned int ethernet0clkctrl;
+	unsigned int ethernet1clkctrl;
+	unsigned int mpuclkctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int debugssclkctrl;
+#elif defined(CONFIG_TI816X)
+	unsigned int resv6[1];
+#endif
+	unsigned int l3clkctrl;
+	unsigned int l4hsclkctrl;
+	unsigned int l4lsclkctrl;
+	unsigned int rtcclkctrl;
+	unsigned int tpccclkctrl;
+	unsigned int tptc0clkctrl;
+	unsigned int tptc1clkctrl;
+	unsigned int tptc2clkctrl;
+	unsigned int tptc3clkctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int resv6[4];
+	unsigned int dcan01clkctrl;
+	unsigned int mmchs0clkctrl;
+	unsigned int mmchs1clkctrl;
+	unsigned int mmchs2clkctrl;
+	unsigned int custefuseclkctrl;
+#elif defined(CONFIG_TI816X)
+	unsigned int sr0clkctrl;
+	unsigned int sr1clkctrl;
+#endif
+};
+
+#endif /* _CLOCK_TI81XX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
new file mode 100644
index 000000000..4c9352a2e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -0,0 +1,38 @@
+/*
+ * clocks_am33xx.h
+ *
+ * AM33xx clock define
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CLOCKS_AM33XX_H_
+#define _CLOCKS_AM33XX_H_
+
+/* MAIN PLL Fdll supported frequencies */
+#define MPUPLL_M_1000	1000
+#define MPUPLL_M_800	800
+#define MPUPLL_M_720	720
+#define MPUPLL_M_600	600
+#define MPUPLL_M_550	550
+#define MPUPLL_M_300	300
+
+/* MAIN PLL Fdll = 550 MHz, by default */
+#ifndef CONFIG_SYS_MPUCLK
+#define CONFIG_SYS_MPUCLK	MPUPLL_M_550
+#endif
+
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+#define CM_DLL_CTRL_NO_OVERRIDE	0x0
+#define CM_DLL_READYST		0x4
+
+extern void enable_dmm_clocks(void);
+extern const struct dpll_params dpll_core_opp100;
+extern struct dpll_params dpll_mpu_opp100;
+
+#endif	/* endif _CLOCKS_AM33XX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h
new file mode 100644
index 000000000..d9f0306b0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -0,0 +1,536 @@
+/*
+ * cpu.h
+ *
+ * AM33xx specific header file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _AM33XX_CPU_H
+#define _AM33XX_CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <asm/arch/hardware.h>
+
+#define BIT(x)				(1 << x)
+#define CL_BIT(x)			(0 << x)
+
+/* Timer register bits */
+#define TCLR_ST				BIT(0)	/* Start=1 Stop=0 */
+#define TCLR_AR				BIT(1)	/* Auto reload */
+#define TCLR_PRE			BIT(5)	/* Pre-scaler enable */
+#define TCLR_PTV_SHIFT			(2)	/* Pre-scaler shift value */
+#define TCLR_PRE_DISABLE		CL_BIT(5) /* Pre-scalar disable */
+
+/* device type */
+#define DEVICE_MASK			(BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE			0x0
+#define EMU_DEVICE			0x1
+#define HS_DEVICE			0x2
+#define GP_DEVICE			0x3
+
+/* cpu-id for AM33XX and TI81XX family */
+#define AM335X				0xB944
+#define TI81XX				0xB81E
+#define DEVICE_ID			(CTRL_BASE + 0x0600)
+#define DEVICE_ID_MASK			0x1FFF
+
+/* MPU max frequencies */
+#define AM335X_ZCZ_300			0x1FEF
+#define AM335X_ZCZ_600			0x1FAF
+#define AM335X_ZCZ_720			0x1F2F
+#define AM335X_ZCZ_800			0x1E2F
+#define AM335X_ZCZ_1000			0x1C2F
+#define AM335X_ZCE_300			0x1FDF
+#define AM335X_ZCE_600			0x1F9F
+
+/* This gives the status of the boot mode pins on the evm */
+#define SYSBOOT_MASK			(BIT(0) | BIT(1) | BIT(2)\
+					| BIT(3) | BIT(4))
+
+#define PRM_RSTCTRL_RESET		0x01
+#define PRM_RSTST_WARM_RESET_MASK	0x232
+
+/*
+ * Watchdog:
+ * Using the prescaler, the OMAP watchdog could go for many
+ * months before firing.  These limits work without scaling,
+ * with the 60 second default assumed by most tools and docs.
+ */
+#define TIMER_MARGIN_MAX	(24 * 60 * 60)	/* 1 day */
+#define TIMER_MARGIN_DEFAULT	60	/* 60 secs */
+#define TIMER_MARGIN_MIN	1
+
+#define PTV			0	/* prescale */
+#define GET_WLDR_VAL(secs)	(0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
+#define WDT_WWPS_PEND_WCLR	BIT(0)
+#define WDT_WWPS_PEND_WLDR	BIT(2)
+#define WDT_WWPS_PEND_WTGR	BIT(3)
+#define WDT_WWPS_PEND_WSPR	BIT(4)
+
+#define WDT_WCLR_PRE		BIT(5)
+#define WDT_WCLR_PTV_OFF	2
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+
+
+#ifndef CONFIG_AM43XX
+/* Encapsulating core pll registers */
+struct cm_wkuppll {
+	unsigned int wkclkstctrl;	/* offset 0x00 */
+	unsigned int wkctrlclkctrl;	/* offset 0x04 */
+	unsigned int wkgpio0clkctrl;	/* offset 0x08 */
+	unsigned int wkl4wkclkctrl;	/* offset 0x0c */
+	unsigned int resv2[4];
+	unsigned int idlestdpllmpu;	/* offset 0x20 */
+	unsigned int resv3[2];
+	unsigned int clkseldpllmpu;	/* offset 0x2c */
+	unsigned int resv4[1];
+	unsigned int idlestdpllddr;	/* offset 0x34 */
+	unsigned int resv5[2];
+	unsigned int clkseldpllddr;	/* offset 0x40 */
+	unsigned int resv6[4];
+	unsigned int clkseldplldisp;	/* offset 0x54 */
+	unsigned int resv7[1];
+	unsigned int idlestdpllcore;	/* offset 0x5c */
+	unsigned int resv8[2];
+	unsigned int clkseldpllcore;	/* offset 0x68 */
+	unsigned int resv9[1];
+	unsigned int idlestdpllper;	/* offset 0x70 */
+	unsigned int resv10[2];
+	unsigned int clkdcoldodpllper;	/* offset 0x7c */
+	unsigned int divm4dpllcore;	/* offset 0x80 */
+	unsigned int divm5dpllcore;	/* offset 0x84 */
+	unsigned int clkmoddpllmpu;	/* offset 0x88 */
+	unsigned int clkmoddpllper;	/* offset 0x8c */
+	unsigned int clkmoddpllcore;	/* offset 0x90 */
+	unsigned int clkmoddpllddr;	/* offset 0x94 */
+	unsigned int clkmoddplldisp;	/* offset 0x98 */
+	unsigned int clkseldpllper;	/* offset 0x9c */
+	unsigned int divm2dpllddr;	/* offset 0xA0 */
+	unsigned int divm2dplldisp;	/* offset 0xA4 */
+	unsigned int divm2dpllmpu;	/* offset 0xA8 */
+	unsigned int divm2dpllper;	/* offset 0xAC */
+	unsigned int resv11[1];
+	unsigned int wkup_uart0ctrl;	/* offset 0xB4 */
+	unsigned int wkup_i2c0ctrl;	/* offset 0xB8 */
+	unsigned int wkup_adctscctrl;	/* offset 0xBC */
+	unsigned int resv12[6];
+	unsigned int divm6dpllcore;	/* offset 0xD8 */
+};
+
+/**
+ * Encapsulating peripheral functional clocks
+ * pll registers
+ */
+struct cm_perpll {
+	unsigned int l4lsclkstctrl;	/* offset 0x00 */
+	unsigned int l3sclkstctrl;	/* offset 0x04 */
+	unsigned int l4fwclkstctrl;	/* offset 0x08 */
+	unsigned int l3clkstctrl;	/* offset 0x0c */
+	unsigned int resv1;
+	unsigned int cpgmac0clkctrl;	/* offset 0x14 */
+	unsigned int lcdclkctrl;	/* offset 0x18 */
+	unsigned int usb0clkctrl;	/* offset 0x1C */
+	unsigned int resv2;
+	unsigned int tptc0clkctrl;	/* offset 0x24 */
+	unsigned int emifclkctrl;	/* offset 0x28 */
+	unsigned int ocmcramclkctrl;	/* offset 0x2c */
+	unsigned int gpmcclkctrl;	/* offset 0x30 */
+	unsigned int mcasp0clkctrl;	/* offset 0x34 */
+	unsigned int uart5clkctrl;	/* offset 0x38 */
+	unsigned int mmc0clkctrl;	/* offset 0x3C */
+	unsigned int elmclkctrl;	/* offset 0x40 */
+	unsigned int i2c2clkctrl;	/* offset 0x44 */
+	unsigned int i2c1clkctrl;	/* offset 0x48 */
+	unsigned int spi0clkctrl;	/* offset 0x4C */
+	unsigned int spi1clkctrl;	/* offset 0x50 */
+	unsigned int resv3[3];
+	unsigned int l4lsclkctrl;	/* offset 0x60 */
+	unsigned int l4fwclkctrl;	/* offset 0x64 */
+	unsigned int mcasp1clkctrl;	/* offset 0x68 */
+	unsigned int uart1clkctrl;	/* offset 0x6C */
+	unsigned int uart2clkctrl;	/* offset 0x70 */
+	unsigned int uart3clkctrl;	/* offset 0x74 */
+	unsigned int uart4clkctrl;	/* offset 0x78 */
+	unsigned int timer7clkctrl;	/* offset 0x7C */
+	unsigned int timer2clkctrl;	/* offset 0x80 */
+	unsigned int timer3clkctrl;	/* offset 0x84 */
+	unsigned int timer4clkctrl;	/* offset 0x88 */
+	unsigned int resv4[8];
+	unsigned int gpio1clkctrl;	/* offset 0xAC */
+	unsigned int gpio2clkctrl;	/* offset 0xB0 */
+	unsigned int gpio3clkctrl;	/* offset 0xB4 */
+	unsigned int resv5;
+	unsigned int tpccclkctrl;	/* offset 0xBC */
+	unsigned int dcan0clkctrl;	/* offset 0xC0 */
+	unsigned int dcan1clkctrl;	/* offset 0xC4 */
+	unsigned int resv6;
+	unsigned int epwmss1clkctrl;	/* offset 0xCC */
+	unsigned int emiffwclkctrl;	/* offset 0xD0 */
+	unsigned int epwmss0clkctrl;	/* offset 0xD4 */
+	unsigned int epwmss2clkctrl;	/* offset 0xD8 */
+	unsigned int l3instrclkctrl;	/* offset 0xDC */
+	unsigned int l3clkctrl;		/* Offset 0xE0 */
+	unsigned int resv8[4];
+	unsigned int mmc1clkctrl;	/* offset 0xF4 */
+	unsigned int mmc2clkctrl;	/* offset 0xF8 */
+	unsigned int resv9[8];
+	unsigned int l4hsclkstctrl;	/* offset 0x11C */
+	unsigned int l4hsclkctrl;	/* offset 0x120 */
+	unsigned int resv10[8];
+	unsigned int cpswclkstctrl;	/* offset 0x144 */
+	unsigned int lcdcclkstctrl;	/* offset 0x148 */
+};
+
+/* Encapsulating Display pll registers */
+struct cm_dpll {
+	unsigned int resv1[2];
+	unsigned int clktimer2clk;	/* offset 0x08 */
+	unsigned int resv2[10];
+	unsigned int clklcdcpixelclk;	/* offset 0x34 */
+};
+#else
+/* Encapsulating core pll registers */
+struct cm_wkuppll {
+	unsigned int resv0[136];
+	unsigned int wkl4wkclkctrl;	/* offset 0x220 */
+	unsigned int resv1[55];
+	unsigned int wkclkstctrl;	/* offset 0x300 */
+	unsigned int resv2[15];
+	unsigned int wkup_i2c0ctrl;	/* offset 0x340 */
+	unsigned int resv3;
+	unsigned int wkup_uart0ctrl;	/* offset 0x348 */
+	unsigned int resv4[5];
+	unsigned int wkctrlclkctrl;	/* offset 0x360 */
+	unsigned int resv5;
+	unsigned int wkgpio0clkctrl;	/* offset 0x368 */
+
+	unsigned int resv6[109];
+	unsigned int clkmoddpllcore;	/* offset 0x520 */
+	unsigned int idlestdpllcore;	/* offset 0x524 */
+	unsigned int resv61;
+	unsigned int clkseldpllcore;	/* offset 0x52C */
+	unsigned int resv7[2];
+	unsigned int divm4dpllcore;	/* offset 0x538 */
+	unsigned int divm5dpllcore;	/* offset 0x53C */
+	unsigned int divm6dpllcore;	/* offset 0x540 */
+
+	unsigned int resv8[7];
+	unsigned int clkmoddpllmpu;	/* offset 0x560 */
+	unsigned int idlestdpllmpu;	/* offset 0x564 */
+	unsigned int resv9;
+	unsigned int clkseldpllmpu;	/* offset 0x56c */
+	unsigned int divm2dpllmpu;	/* offset 0x570 */
+
+	unsigned int resv10[11];
+	unsigned int clkmoddpllddr;	/* offset 0x5A0 */
+	unsigned int idlestdpllddr;	/* offset 0x5A4 */
+	unsigned int resv11;
+	unsigned int clkseldpllddr;	/* offset 0x5AC */
+	unsigned int divm2dpllddr;	/* offset 0x5B0 */
+
+	unsigned int resv12[11];
+	unsigned int clkmoddpllper;	/* offset 0x5E0 */
+	unsigned int idlestdpllper;	/* offset 0x5E4 */
+	unsigned int resv13;
+	unsigned int clkseldpllper;	/* offset 0x5EC */
+	unsigned int divm2dpllper;	/* offset 0x5F0 */
+	unsigned int resv14[8];
+	unsigned int clkdcoldodpllper;	/* offset 0x614 */
+
+	unsigned int resv15[2];
+	unsigned int clkmoddplldisp;	/* offset 0x620 */
+	unsigned int resv16[2];
+	unsigned int clkseldplldisp;	/* offset 0x62C */
+	unsigned int divm2dplldisp;	/* offset 0x630 */
+};
+
+/*
+ * Encapsulating peripheral functional clocks
+ * pll registers
+ */
+struct cm_perpll {
+	unsigned int l3clkstctrl;	/* offset 0x00 */
+	unsigned int resv0[7];
+	unsigned int l3clkctrl;		/* Offset 0x20 */
+	unsigned int resv1[7];
+	unsigned int l3instrclkctrl;	/* offset 0x40 */
+	unsigned int resv2[3];
+	unsigned int ocmcramclkctrl;	/* offset 0x50 */
+	unsigned int resv3[9];
+	unsigned int tpccclkctrl;	/* offset 0x78 */
+	unsigned int resv4;
+	unsigned int tptc0clkctrl;	/* offset 0x80 */
+
+	unsigned int resv5[7];
+	unsigned int l4hsclkctrl;	/* offset 0x0A0 */
+	unsigned int resv6;
+	unsigned int l4fwclkctrl;	/* offset 0x0A8 */
+	unsigned int resv7[85];
+	unsigned int l3sclkstctrl;	/* offset 0x200 */
+	unsigned int resv8[7];
+	unsigned int gpmcclkctrl;	/* offset 0x220 */
+	unsigned int resv9[5];
+	unsigned int mcasp0clkctrl;	/* offset 0x238 */
+	unsigned int resv10;
+	unsigned int mcasp1clkctrl;	/* offset 0x240 */
+	unsigned int resv11;
+	unsigned int mmc2clkctrl;	/* offset 0x248 */
+	unsigned int resv12[3];
+	unsigned int qspiclkctrl;       /* offset 0x258 */
+	unsigned int resv121;
+	unsigned int usb0clkctrl;	/* offset 0x260 */
+	unsigned int resv13[103];
+	unsigned int l4lsclkstctrl;	/* offset 0x400 */
+	unsigned int resv14[7];
+	unsigned int l4lsclkctrl;	/* offset 0x420 */
+	unsigned int resv15;
+	unsigned int dcan0clkctrl;	/* offset 0x428 */
+	unsigned int resv16;
+	unsigned int dcan1clkctrl;	/* offset 0x430 */
+	unsigned int resv17[13];
+	unsigned int elmclkctrl;	/* offset 0x468 */
+
+	unsigned int resv18[3];
+	unsigned int gpio1clkctrl;	/* offset 0x478 */
+	unsigned int resv19;
+	unsigned int gpio2clkctrl;	/* offset 0x480 */
+	unsigned int resv20;
+	unsigned int gpio3clkctrl;	/* offset 0x488 */
+	unsigned int resv41;
+	unsigned int gpio4clkctrl;	/* offset 0x490 */
+	unsigned int resv42;
+	unsigned int gpio5clkctrl;	/* offset 0x498 */
+	unsigned int resv21[3];
+
+	unsigned int i2c1clkctrl;	/* offset 0x4A8 */
+	unsigned int resv22;
+	unsigned int i2c2clkctrl;	/* offset 0x4B0 */
+	unsigned int resv23[3];
+	unsigned int mmc0clkctrl;	/* offset 0x4C0 */
+	unsigned int resv24;
+	unsigned int mmc1clkctrl;	/* offset 0x4C8 */
+
+	unsigned int resv25[13];
+	unsigned int spi0clkctrl;	/* offset 0x500 */
+	unsigned int resv26;
+	unsigned int spi1clkctrl;	/* offset 0x508 */
+	unsigned int resv27[9];
+	unsigned int timer2clkctrl;	/* offset 0x530 */
+	unsigned int resv28;
+	unsigned int timer3clkctrl;	/* offset 0x538 */
+	unsigned int resv29;
+	unsigned int timer4clkctrl;	/* offset 0x540 */
+	unsigned int resv30[5];
+	unsigned int timer7clkctrl;	/* offset 0x558 */
+
+	unsigned int resv31[9];
+	unsigned int uart1clkctrl;	/* offset 0x580 */
+	unsigned int resv32;
+	unsigned int uart2clkctrl;	/* offset 0x588 */
+	unsigned int resv33;
+	unsigned int uart3clkctrl;	/* offset 0x590 */
+	unsigned int resv34;
+	unsigned int uart4clkctrl;	/* offset 0x598 */
+	unsigned int resv35;
+	unsigned int uart5clkctrl;	/* offset 0x5A0 */
+	unsigned int resv36[87];
+
+	unsigned int emifclkstctrl;	/* offset 0x700 */
+	unsigned int resv361[7];
+	unsigned int emifclkctrl;	/* offset 0x720 */
+	unsigned int resv37[3];
+	unsigned int emiffwclkctrl;	/* offset 0x730 */
+	unsigned int resv371;
+	unsigned int otfaemifclkctrl;	/* offset 0x738 */
+	unsigned int resv38[57];
+	unsigned int lcdclkctrl;	/* offset 0x820 */
+	unsigned int resv39[183];
+	unsigned int cpswclkstctrl;	/* offset 0xB00 */
+	unsigned int resv40[7];
+	unsigned int cpgmac0clkctrl;	/* offset 0xB20 */
+};
+
+struct cm_device_inst {
+	unsigned int cm_clkout1_ctrl;
+	unsigned int cm_dll_ctrl;
+};
+
+struct cm_dpll {
+	unsigned int resv1;
+	unsigned int clktimer2clk;	/* offset 0x04 */
+};
+#endif /* CONFIG_AM43XX */
+
+/* Control Module RTC registers */
+struct cm_rtc {
+	unsigned int rtcclkctrl;	/* offset 0x0 */
+	unsigned int clkstctrl;		/* offset 0x4 */
+};
+
+/* Watchdog timer registers */
+struct wd_timer {
+	unsigned int resv1[4];
+	unsigned int wdtwdsc;	/* offset 0x010 */
+	unsigned int wdtwdst;	/* offset 0x014 */
+	unsigned int wdtwisr;	/* offset 0x018 */
+	unsigned int wdtwier;	/* offset 0x01C */
+	unsigned int wdtwwer;	/* offset 0x020 */
+	unsigned int wdtwclr;	/* offset 0x024 */
+	unsigned int wdtwcrr;	/* offset 0x028 */
+	unsigned int wdtwldr;	/* offset 0x02C */
+	unsigned int wdtwtgr;	/* offset 0x030 */
+	unsigned int wdtwwps;	/* offset 0x034 */
+	unsigned int resv2[3];
+	unsigned int wdtwdly;	/* offset 0x044 */
+	unsigned int wdtwspr;	/* offset 0x048 */
+	unsigned int resv3[1];
+	unsigned int wdtwqeoi;	/* offset 0x050 */
+	unsigned int wdtwqstar;	/* offset 0x054 */
+	unsigned int wdtwqsta;	/* offset 0x058 */
+	unsigned int wdtwqens;	/* offset 0x05C */
+	unsigned int wdtwqenc;	/* offset 0x060 */
+	unsigned int resv4[39];
+	unsigned int wdt_unfr;	/* offset 0x100 */
+};
+
+/* Timer 32 bit registers */
+struct gptimer {
+	unsigned int tidr;		/* offset 0x00 */
+	unsigned char res1[12];
+	unsigned int tiocp_cfg;		/* offset 0x10 */
+	unsigned char res2[12];
+	unsigned int tier;		/* offset 0x20 */
+	unsigned int tistatr;		/* offset 0x24 */
+	unsigned int tistat;		/* offset 0x28 */
+	unsigned int tisr;		/* offset 0x2c */
+	unsigned int tcicr;		/* offset 0x30 */
+	unsigned int twer;		/* offset 0x34 */
+	unsigned int tclr;		/* offset 0x38 */
+	unsigned int tcrr;		/* offset 0x3c */
+	unsigned int tldr;		/* offset 0x40 */
+	unsigned int ttgr;		/* offset 0x44 */
+	unsigned int twpc;		/* offset 0x48 */
+	unsigned int tmar;		/* offset 0x4c */
+	unsigned int tcar1;		/* offset 0x50 */
+	unsigned int tscir;		/* offset 0x54 */
+	unsigned int tcar2;		/* offset 0x58 */
+};
+
+/* UART Registers */
+struct uart_sys {
+	unsigned int resv1[21];
+	unsigned int uartsyscfg;	/* offset 0x54 */
+	unsigned int uartsyssts;	/* offset 0x58 */
+};
+
+/* VTP Registers */
+struct vtp_reg {
+	unsigned int vtp0ctrlreg;
+};
+
+/* Control Status Register */
+struct ctrl_stat {
+	unsigned int resv1[16];
+	unsigned int statusreg;		/* ofset 0x40 */
+	unsigned int resv2[51];
+	unsigned int secure_emif_sdram_config;	/* offset 0x0110 */
+	unsigned int resv3[319];
+	unsigned int dev_attr;
+};
+
+/* AM33XX GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x002c
+#define OMAP_GPIO_IRQSTATUS2		0x0030
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
+/* Control Device Register */
+struct ctrl_dev {
+	unsigned int deviceid;		/* offset 0x00 */
+	unsigned int resv1[7];
+	unsigned int usb_ctrl0;		/* offset 0x20 */
+	unsigned int resv2;
+	unsigned int usb_ctrl1;		/* offset 0x28 */
+	unsigned int resv3;
+	unsigned int macid0l;		/* offset 0x30 */
+	unsigned int macid0h;		/* offset 0x34 */
+	unsigned int macid1l;		/* offset 0x38 */
+	unsigned int macid1h;		/* offset 0x3c */
+	unsigned int resv4[4];
+	unsigned int miisel;		/* offset 0x50 */
+	unsigned int resv5[106];
+	unsigned int efuse_sma;		/* offset 0x1FC */
+};
+
+/* gmii_sel register defines */
+#define GMII1_SEL_MII		0x0
+#define GMII1_SEL_RMII		0x1
+#define GMII1_SEL_RGMII		0x2
+#define GMII2_SEL_MII		0x0
+#define GMII2_SEL_RMII		0x4
+#define GMII2_SEL_RGMII		0x8
+#define RGMII1_IDMODE		BIT(4)
+#define RGMII2_IDMODE		BIT(5)
+#define RMII1_IO_CLK_EN		BIT(6)
+#define RMII2_IO_CLK_EN		BIT(7)
+
+#define MII_MODE_ENABLE		(GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE	(GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+#define RGMII_INT_DELAY		(RGMII1_IDMODE | RGMII2_IDMODE)
+#define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
+
+/* PWMSS */
+struct pwmss_regs {
+	unsigned int idver;
+	unsigned int sysconfig;
+	unsigned int clkconfig;
+	unsigned int clkstatus;
+};
+#define ECAP_CLK_EN		BIT(0)
+#define ECAP_CLK_STOP_REQ	BIT(1)
+
+struct pwmss_ecap_regs {
+	unsigned int tsctr;
+	unsigned int ctrphs;
+	unsigned int cap1;
+	unsigned int cap2;
+	unsigned int cap3;
+	unsigned int cap4;
+	unsigned int resv1[4];
+	unsigned short ecctl1;
+	unsigned short ecctl2;
+};
+
+/* Capture Control register 2 */
+#define ECTRL2_SYNCOSEL_MASK	(0x03 << 6)
+#define ECTRL2_MDSL_ECAP	BIT(9)
+#define ECTRL2_CTRSTP_FREERUN	BIT(4)
+#define ECTRL2_PLSL_LOW		BIT(10)
+#define ECTRL2_SYNC_EN		BIT(5)
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#endif /* _AM33XX_CPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h
new file mode 100644
index 000000000..4d899528f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -0,0 +1,351 @@
+/*
+ * ddr_defs.h
+ *
+ * ddr specific header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DDR_DEFS_H
+#define _DDR_DEFS_H
+
+#include <asm/arch/hardware.h>
+#include <asm/emif.h>
+
+/* AM335X EMIF Register values */
+#define VTP_CTRL_READY		(0x1 << 5)
+#define VTP_CTRL_ENABLE		(0x1 << 6)
+#define VTP_CTRL_START_EN	(0x1)
+#ifdef CONFIG_AM43XX
+#define DDR_CKE_CTRL_NORMAL	0x3
+#else
+#define DDR_CKE_CTRL_NORMAL	0x1
+#endif
+#define PHY_EN_DYN_PWRDN	(0x1 << 20)
+
+/* Micron MT47H128M16RT-25E */
+#define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
+#define MT47H128M16RT25E_EMIF_TIM1		0x0666B3C9
+#define MT47H128M16RT25E_EMIF_TIM2		0x243631CA
+#define MT47H128M16RT25E_EMIF_TIM3		0x0000033F
+#define MT47H128M16RT25E_EMIF_SDCFG		0x41805332
+#define MT47H128M16RT25E_EMIF_SDREF		0x0000081a
+#define MT47H128M16RT25E_RATIO			0x80
+#define MT47H128M16RT25E_INVERT_CLKOUT		0x00
+#define MT47H128M16RT25E_RD_DQS			0x12
+#define MT47H128M16RT25E_WR_DQS			0x00
+#define MT47H128M16RT25E_PHY_WRLVL		0x00
+#define MT47H128M16RT25E_PHY_GATELVL		0x00
+#define MT47H128M16RT25E_PHY_WR_DATA		0x40
+#define MT47H128M16RT25E_PHY_FIFO_WE		0x80
+#define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
+
+/* Micron MT41J128M16JT-125 */
+#define MT41J128MJT125_EMIF_READ_LATENCY	0x100006
+#define MT41J128MJT125_EMIF_TIM1		0x0888A39B
+#define MT41J128MJT125_EMIF_TIM2		0x26337FDA
+#define MT41J128MJT125_EMIF_TIM3		0x501F830F
+#define MT41J128MJT125_EMIF_SDCFG		0x61C04AB2
+#define MT41J128MJT125_EMIF_SDREF		0x0000093B
+#define MT41J128MJT125_ZQ_CFG			0x50074BE4
+#define MT41J128MJT125_RATIO			0x40
+#define MT41J128MJT125_INVERT_CLKOUT		0x1
+#define MT41J128MJT125_RD_DQS			0x3B
+#define MT41J128MJT125_WR_DQS			0x85
+#define MT41J128MJT125_PHY_WR_DATA		0xC1
+#define MT41J128MJT125_PHY_FIFO_WE		0x100
+#define MT41J128MJT125_IOCTRL_VALUE		0x18B
+
+/* Micron MT41K128M16JT-187E */
+#define MT41K128MJT187E_EMIF_READ_LATENCY	0x06
+#define MT41K128MJT187E_EMIF_TIM1		0x0888B3DB
+#define MT41K128MJT187E_EMIF_TIM2		0x36337FDA
+#define MT41K128MJT187E_EMIF_TIM3		0x501F830F
+#define MT41K128MJT187E_EMIF_SDCFG		0x61C04AB2
+#define MT41K128MJT187E_EMIF_SDREF		0x0000093B
+#define MT41K128MJT187E_ZQ_CFG			0x50074BE4
+#define MT41K128MJT187E_RATIO			0x40
+#define MT41K128MJT187E_INVERT_CLKOUT		0x1
+#define MT41K128MJT187E_RD_DQS			0x3B
+#define MT41K128MJT187E_WR_DQS			0x85
+#define MT41K128MJT187E_PHY_WR_DATA		0xC1
+#define MT41K128MJT187E_PHY_FIFO_WE		0x100
+#define MT41K128MJT187E_IOCTRL_VALUE		0x18B
+
+/* Micron MT41J64M16JT-125 */
+#define MT41J64MJT125_EMIF_SDCFG		0x61C04A32
+
+/* Micron MT41J256M16JT-125 */
+#define MT41J256MJT125_EMIF_SDCFG		0x61C04B32
+
+/* Micron MT41J256M8HX-15E */
+#define MT41J256M8HX15E_EMIF_READ_LATENCY	0x100006
+#define MT41J256M8HX15E_EMIF_TIM1		0x0888A39B
+#define MT41J256M8HX15E_EMIF_TIM2		0x26337FDA
+#define MT41J256M8HX15E_EMIF_TIM3		0x501F830F
+#define MT41J256M8HX15E_EMIF_SDCFG		0x61C04B32
+#define MT41J256M8HX15E_EMIF_SDREF		0x0000093B
+#define MT41J256M8HX15E_ZQ_CFG			0x50074BE4
+#define MT41J256M8HX15E_RATIO			0x40
+#define MT41J256M8HX15E_INVERT_CLKOUT		0x1
+#define MT41J256M8HX15E_RD_DQS			0x3B
+#define MT41J256M8HX15E_WR_DQS			0x85
+#define MT41J256M8HX15E_PHY_WR_DATA		0xC1
+#define MT41J256M8HX15E_PHY_FIFO_WE		0x100
+#define MT41J256M8HX15E_IOCTRL_VALUE		0x18B
+
+/* Micron MT41K256M16HA-125E */
+#define MT41K256M16HA125E_EMIF_READ_LATENCY	0x100007
+#define MT41K256M16HA125E_EMIF_TIM1		0x0AAAD4DB
+#define MT41K256M16HA125E_EMIF_TIM2		0x266B7FDA
+#define MT41K256M16HA125E_EMIF_TIM3		0x501F867F
+#define MT41K256M16HA125E_EMIF_SDCFG		0x61C05332
+#define MT41K256M16HA125E_EMIF_SDREF		0xC30
+#define MT41K256M16HA125E_ZQ_CFG		0x50074BE4
+#define MT41K256M16HA125E_RATIO			0x80
+#define MT41K256M16HA125E_INVERT_CLKOUT		0x0
+#define MT41K256M16HA125E_RD_DQS		0x38
+#define MT41K256M16HA125E_WR_DQS		0x44
+#define MT41K256M16HA125E_PHY_WR_DATA		0x7D
+#define MT41K256M16HA125E_PHY_FIFO_WE		0x94
+#define MT41K256M16HA125E_IOCTRL_VALUE		0x18B
+
+/* Micron MT41J512M8RH-125 on EVM v1.5 */
+#define MT41J512M8RH125_EMIF_READ_LATENCY	0x100006
+#define MT41J512M8RH125_EMIF_TIM1		0x0888A39B
+#define MT41J512M8RH125_EMIF_TIM2		0x26517FDA
+#define MT41J512M8RH125_EMIF_TIM3		0x501F84EF
+#define MT41J512M8RH125_EMIF_SDCFG		0x61C04BB2
+#define MT41J512M8RH125_EMIF_SDREF		0x0000093B
+#define MT41J512M8RH125_ZQ_CFG			0x50074BE4
+#define MT41J512M8RH125_RATIO			0x80
+#define MT41J512M8RH125_INVERT_CLKOUT		0x0
+#define MT41J512M8RH125_RD_DQS			0x3B
+#define MT41J512M8RH125_WR_DQS			0x3C
+#define MT41J512M8RH125_PHY_FIFO_WE		0xA5
+#define MT41J512M8RH125_PHY_WR_DATA		0x74
+#define MT41J512M8RH125_IOCTRL_VALUE		0x18B
+
+/* Samsung K4B2G1646E-BIH9 */
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x100007
+#define K4B2G1646EBIH9_EMIF_TIM1		0x0AAAE51B
+#define K4B2G1646EBIH9_EMIF_TIM2		0x2A1D7FDA
+#define K4B2G1646EBIH9_EMIF_TIM3		0x501F83FF
+#define K4B2G1646EBIH9_EMIF_SDCFG		0x61C052B2
+#define K4B2G1646EBIH9_EMIF_SDREF		0x00000C30
+#define K4B2G1646EBIH9_ZQ_CFG			0x50074BE4
+#define K4B2G1646EBIH9_RATIO			0x80
+#define K4B2G1646EBIH9_INVERT_CLKOUT		0x0
+#define K4B2G1646EBIH9_RD_DQS			0x35
+#define K4B2G1646EBIH9_WR_DQS			0x3A
+#define K4B2G1646EBIH9_PHY_FIFO_WE		0x97
+#define K4B2G1646EBIH9_PHY_WR_DATA		0x76
+#define K4B2G1646EBIH9_IOCTRL_VALUE		0x18B
+
+#define  LPDDR2_ADDRCTRL_IOCTRL_VALUE   0x294
+#define  LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  LPDDR2_DATA0_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA1_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
+
+#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
+#define  DDR3_DATA0_IOCTRL_VALUE   0x84
+#define  DDR3_DATA1_IOCTRL_VALUE   0x84
+#define  DDR3_DATA2_IOCTRL_VALUE   0x84
+#define  DDR3_DATA3_IOCTRL_VALUE   0x84
+
+/**
+ * Configure DMM
+ */
+void config_dmm(const struct dmm_lisa_map_regs *regs);
+
+/**
+ * Configure SDRAM
+ */
+void config_sdram(const struct emif_regs *regs, int nr);
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
+
+/**
+ * Set SDRAM timings
+ */
+void set_sdram_timings(const struct emif_regs *regs, int nr);
+
+/**
+ * Configure DDR PHY
+ */
+void config_ddr_phy(const struct emif_regs *regs, int nr);
+
+struct ddr_cmd_regs {
+	unsigned int resv0[7];
+	unsigned int cm0csratio;	/* offset 0x01C */
+	unsigned int resv1[3];
+	unsigned int cm0iclkout;	/* offset 0x02C */
+	unsigned int resv2[8];
+	unsigned int cm1csratio;	/* offset 0x050 */
+	unsigned int resv3[3];
+	unsigned int cm1iclkout;	/* offset 0x060 */
+	unsigned int resv4[8];
+	unsigned int cm2csratio;	/* offset 0x084 */
+	unsigned int resv5[3];
+	unsigned int cm2iclkout;	/* offset 0x094 */
+	unsigned int resv6[3];
+};
+
+struct ddr_data_regs {
+	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
+	unsigned int resv1[4];
+	unsigned int dt0wdsratio0;	/* offset 0x0DC */
+	unsigned int resv2[4];
+	unsigned int dt0wiratio0;	/* offset 0x0F0 */
+	unsigned int resv3;
+	unsigned int dt0wimode0;	/* offset 0x0F8 */
+	unsigned int dt0giratio0;	/* offset 0x0FC */
+	unsigned int resv4;
+	unsigned int dt0gimode0;	/* offset 0x104 */
+	unsigned int dt0fwsratio0;	/* offset 0x108 */
+	unsigned int resv5[4];
+	unsigned int dt0dqoffset;	/* offset 0x11C */
+	unsigned int dt0wrsratio0;	/* offset 0x120 */
+	unsigned int resv6[4];
+	unsigned int dt0rdelays0;	/* offset 0x134 */
+	unsigned int dt0dldiff0;	/* offset 0x138 */
+	unsigned int resv7[12];
+};
+
+/**
+ * This structure represents the DDR registers on AM33XX devices.
+ * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
+ * correspond to DATA1 registers defined here.
+ */
+struct ddr_regs {
+	unsigned int resv0[3];
+	unsigned int cm0config;		/* offset 0x00C */
+	unsigned int cm0configclk;	/* offset 0x010 */
+	unsigned int resv1[2];
+	unsigned int cm0csratio;	/* offset 0x01C */
+	unsigned int resv2[3];
+	unsigned int cm0iclkout;	/* offset 0x02C */
+	unsigned int resv3[4];
+	unsigned int cm1config;		/* offset 0x040 */
+	unsigned int cm1configclk;	/* offset 0x044 */
+	unsigned int resv4[2];
+	unsigned int cm1csratio;	/* offset 0x050 */
+	unsigned int resv5[3];
+	unsigned int cm1iclkout;	/* offset 0x060 */
+	unsigned int resv6[4];
+	unsigned int cm2config;		/* offset 0x074 */
+	unsigned int cm2configclk;	/* offset 0x078 */
+	unsigned int resv7[2];
+	unsigned int cm2csratio;	/* offset 0x084 */
+	unsigned int resv8[3];
+	unsigned int cm2iclkout;	/* offset 0x094 */
+	unsigned int resv9[12];
+	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
+	unsigned int resv10[4];
+	unsigned int dt0wdsratio0;	/* offset 0x0DC */
+	unsigned int resv11[4];
+	unsigned int dt0wiratio0;	/* offset 0x0F0 */
+	unsigned int resv12;
+	unsigned int dt0wimode0;	/* offset 0x0F8 */
+	unsigned int dt0giratio0;	/* offset 0x0FC */
+	unsigned int resv13;
+	unsigned int dt0gimode0;	/* offset 0x104 */
+	unsigned int dt0fwsratio0;	/* offset 0x108 */
+	unsigned int resv14[4];
+	unsigned int dt0dqoffset;	/* offset 0x11C */
+	unsigned int dt0wrsratio0;	/* offset 0x120 */
+	unsigned int resv15[4];
+	unsigned int dt0rdelays0;	/* offset 0x134 */
+	unsigned int dt0dldiff0;	/* offset 0x138 */
+};
+
+/**
+ * Encapsulates DDR CMD control registers.
+ */
+struct cmd_control {
+	unsigned long cmd0csratio;
+	unsigned long cmd0csforce;
+	unsigned long cmd0csdelay;
+	unsigned long cmd0iclkout;
+	unsigned long cmd1csratio;
+	unsigned long cmd1csforce;
+	unsigned long cmd1csdelay;
+	unsigned long cmd1iclkout;
+	unsigned long cmd2csratio;
+	unsigned long cmd2csforce;
+	unsigned long cmd2csdelay;
+	unsigned long cmd2iclkout;
+};
+
+/**
+ * Encapsulates DDR DATA registers.
+ */
+struct ddr_data {
+	unsigned long datardsratio0;
+	unsigned long datawdsratio0;
+	unsigned long datawiratio0;
+	unsigned long datagiratio0;
+	unsigned long datafwsratio0;
+	unsigned long datawrsratio0;
+};
+
+/**
+ * Configure DDR CMD control registers
+ */
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
+
+/**
+ * Configure DDR DATA registers
+ */
+void config_ddr_data(const struct ddr_data *data, int nr);
+
+/**
+ * This structure represents the DDR io control on AM33XX devices.
+ */
+struct ddr_cmdtctrl {
+	unsigned int cm0ioctl;
+	unsigned int cm1ioctl;
+	unsigned int cm2ioctl;
+	unsigned int resv2[12];
+	unsigned int dt0ioctl;
+	unsigned int dt1ioctl;
+	unsigned int dt2ioctrl;
+	unsigned int dt3ioctrl;
+	unsigned int resv3[4];
+	unsigned int emif_sdram_config_ext;
+};
+
+struct ctrl_ioregs {
+	unsigned int cm0ioctl;
+	unsigned int cm1ioctl;
+	unsigned int cm2ioctl;
+	unsigned int dt0ioctl;
+	unsigned int dt1ioctl;
+	unsigned int dt2ioctrl;
+	unsigned int dt3ioctrl;
+	unsigned int emif_sdram_config_ext;
+};
+
+/**
+ * Configure DDR io control registers
+ */
+void config_io_ctrl(const struct ctrl_ioregs *ioregs);
+
+struct ddr_ctrl {
+	unsigned int ddrioctrl;
+	unsigned int resv1[325];
+	unsigned int ddrckectrl;
+};
+
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
+		const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs, int nr);
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
+
+#endif  /* _DDR_DEFS_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/gpio.h
new file mode 100644
index 000000000..220603db5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/gpio.h
@@ -0,0 +1,28 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _GPIO_AM33xx_H
+#define _GPIO_AM33xx_H
+
+#include <asm/omap_gpio.h>
+
+#define OMAP_MAX_GPIO		128
+
+#define AM33XX_GPIO0_BASE       0x44E07000
+#define AM33XX_GPIO1_BASE       0x4804C000
+#define AM33XX_GPIO2_BASE       0x481AC000
+#define AM33XX_GPIO3_BASE       0x481AE000
+#define AM33XX_GPIO4_BASE	0x48320000
+#define AM33XX_GPIO5_BASE	0x48322000
+
+/* GPIO CTRL register */
+#define GPIO_CTRL_DISABLEMODULE_SHIFT	0
+#define GPIO_CTRL_DISABLEMODULE_MASK	(1 << 0)
+#define GPIO_CTRL_ENABLEMODULE		GPIO_CTRL_DISABLEMODULE_MASK
+
+/* GPIO OUTPUT ENABLE register */
+#define GPIO_OE_ENABLE(x)		(1 << x)
+
+/* GPIO SETDATAOUT register */
+#define GPIO_SETDATAOUT(x)		(1 << x)
+#endif /* _GPIO_AM33xx_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware.h
new file mode 100644
index 000000000..dd950e5ac
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -0,0 +1,65 @@
+/*
+ * hardware.h
+ *
+ * hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AM33XX_HARDWARE_H
+#define __AM33XX_HARDWARE_H
+
+#include <config.h>
+#include <asm/arch/omap.h>
+#ifdef CONFIG_AM33XX
+#include <asm/arch/hardware_am33xx.h>
+#elif defined(CONFIG_TI816X)
+#include <asm/arch/hardware_ti816x.h>
+#elif defined(CONFIG_TI814X)
+#include <asm/arch/hardware_ti814x.h>
+#elif defined(CONFIG_AM43XX)
+#include <asm/arch/hardware_am43xx.h>
+#endif
+
+/*
+ * Common hardware definitions
+ */
+
+/* DM Timer base addresses */
+#define DM_TIMER0_BASE			0x4802C000
+#define DM_TIMER1_BASE			0x4802E000
+#define DM_TIMER2_BASE			0x48040000
+#define DM_TIMER3_BASE			0x48042000
+#define DM_TIMER4_BASE			0x48044000
+#define DM_TIMER5_BASE			0x48046000
+#define DM_TIMER6_BASE			0x48048000
+#define DM_TIMER7_BASE			0x4804A000
+
+/* GPIO Base address */
+#define GPIO0_BASE			0x48032000
+#define GPIO1_BASE			0x4804C000
+
+/* BCH Error Location Module */
+#define ELM_BASE			0x48080000
+
+/* EMIF Base address */
+#define EMIF4_0_CFG_BASE		0x4C000000
+#define EMIF4_1_CFG_BASE		0x4D000000
+
+/* DDR Base address */
+#define DDR_CTRL_ADDR			0x44E10E04
+#define DDR_CONTROL_BASE_ADDR		0x44E11404
+
+/* UART */
+#define DEFAULT_UART_BASE		UART0_BASE
+
+/* GPMC Base address */
+#define GPMC_BASE			0x50000000
+
+/* CPSW Config space */
+#define CPSW_BASE			0x4A100000
+
+int clk_get(int clk);
+#endif /* __AM33XX_HARDWARE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
new file mode 100644
index 000000000..c67a0801a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -0,0 +1,70 @@
+/*
+ * hardware_am33xx.h
+ *
+ * AM33xx hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AM33XX_HARDWARE_AM33XX_H
+#define __AM33XX_HARDWARE_AM33XX_H
+
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE			0x44E09000
+
+/* GPIO Base address */
+#define GPIO2_BASE			0x481AC000
+
+/* Watchdog Timer */
+#define WDT_BASE			0x44E35000
+
+/* Control Module Base Address */
+#define CTRL_BASE			0x44E10000
+#define CTRL_DEVICE_BASE		0x44E10600
+
+/* PRCM Base Address */
+#define PRCM_BASE			0x44E00000
+#define CM_PER				0x44E00000
+#define CM_WKUP				0x44E00400
+#define CM_DPLL				0x44E00500
+#define CM_RTC				0x44E00800
+
+#define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
+#define PRM_RSTST			(PRM_RSTCTRL + 8)
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x44E10E0C
+#define VTP1_CTRL_ADDR			0x48140E10
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x44E12000
+#define DDR_PHY_DATA_ADDR		0x44E120C8
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
+#define DDR_DATA_REGS_NR		2
+
+#define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
+
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A101000
+
+/* RTC base address */
+#define RTC_BASE			0x44E3E000
+
+/* OTG */
+#define USB0_OTG_BASE			0x47401000
+#define USB1_OTG_BASE			0x47401800
+
+/* LCD Controller */
+#define LCD_CNTL_BASE			0x4830E000
+
+/* PWMSS */
+#define PWMSS0_BASE			0x48300000
+#define AM33XX_ECAP0_BASE		0x48300100
+
+#endif /* __AM33XX_HARDWARE_AM33XX_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
new file mode 100644
index 000000000..15399dcc7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -0,0 +1,80 @@
+/*
+ * hardware_am43xx.h
+ *
+ * AM43xx hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AM43XX_HARDWARE_AM43XX_H
+#define __AM43XX_HARDWARE_AM43XX_H
+
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE			0x44E09000
+
+/* GPIO Base address */
+#define GPIO2_BASE			0x481AC000
+
+/* Watchdog Timer */
+#define WDT_BASE			0x44E35000
+
+/* Control Module Base Address */
+#define CTRL_BASE			0x44E10000
+#define CTRL_DEVICE_BASE		0x44E10600
+
+/* PRCM Base Address */
+#define PRCM_BASE			0x44DF0000
+#define	CM_WKUP				0x44DF2800
+#define	CM_PER				0x44DF8800
+#define CM_DPLL				0x44DF4200
+#define CM_RTC				0x44DF8500
+
+#define PRM_RSTCTRL			(PRCM_BASE + 0x4000)
+#define PRM_RSTST			(PRM_RSTCTRL + 4)
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x44E10E0C
+#define VTP1_CTRL_ADDR			0x48140E10
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x44E12000
+#define DDR_PHY_DATA_ADDR		0x44E120C8
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
+#define DDR_DATA_REGS_NR		2
+
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A101000
+
+/* RTC base address */
+#define RTC_BASE			0x44E3E000
+
+/* USB Clock Control */
+#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
+#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
+#define USBOTGSSX_CLKCTRL_MODULE_EN	(1 << 1)
+#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
+
+#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
+#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
+#define USBPHYOCPSCP_MODULE_EN	(1 << 1)
+#define CM_DEVICE_INST			0x44df4100
+
+/* Control status register */
+#define CTRL_CRYSTAL_FREQ_SRC_MASK		(1 << 31)
+#define CTRL_CRYSTAL_FREQ_SRC_SHIFT		31
+#define CTRL_CRYSTAL_FREQ_SELECTION_MASK	(0x3 << 29)
+#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT	29
+#define CTRL_SYSBOOT_15_14_MASK			(0x3 << 22)
+#define CTRL_SYSBOOT_15_14_SHIFT		22
+
+#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT		0x0
+#define CTRL_CRYSTAL_FREQ_SRC_EFUSE		0x1
+
+#define NUM_CRYSTAL_FREQ			0x4
+
+#endif /* __AM43XX_HARDWARE_AM43XX_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
new file mode 100644
index 000000000..4509a237d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
@@ -0,0 +1,61 @@
+/*
+ * hardware_ti814x.h
+ *
+ * TI814x hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AM33XX_HARDWARE_TI814X_H
+#define __AM33XX_HARDWARE_TI814X_H
+
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE			0x48020000
+
+/* Watchdog Timer */
+#define WDT_BASE			0x481C7000
+
+/* Control Module Base Address */
+#define CTRL_BASE			0x48140000
+#define CTRL_DEVICE_BASE		0x48140600
+
+/* PRCM Base Address */
+#define PRCM_BASE			0x48180000
+#define CM_PER				0x44E00000
+#define CM_WKUP				0x44E00400
+
+#define PRM_RSTCTRL			(PRCM_BASE + 0x00A0)
+#define PRM_RSTST			(PRM_RSTCTRL + 8)
+
+/* PLL Subsystem Base Address */
+#define PLL_SUBSYS_BASE			0x481C5000
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x48140E0C
+#define VTP1_CTRL_ADDR			0x48140E10
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x47C0C400
+#define DDR_PHY_DATA_ADDR		0x47C0C4C8
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
+#define DDR_DATA_REGS_NR		4
+
+#define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
+
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A100800
+
+/* RTC base address */
+#define RTC_BASE			0x480C0000
+
+/* OTG */
+#define USB0_OTG_BASE			0x47401000
+#define USB1_OTG_BASE			0x47401800
+
+#endif /* __AM33XX_HARDWARE_TI814X_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
new file mode 100644
index 000000000..3c680649a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
@@ -0,0 +1,61 @@
+/*
+ * hardware_ti816x.h
+ *
+ * TI816x hardware specific header
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ * Based on TI-PSP-04.00.02.14
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AM33XX_HARDWARE_TI816X_H
+#define __AM33XX_HARDWARE_TI816X_H
+
+/* UART */
+#define UART0_BASE		0x48020000
+#define UART1_BASE		0x48022000
+#define UART2_BASE		0x48024000
+
+/* Watchdog Timer */
+#define WDT_BASE		0x480C2000
+
+/* Control Module Base Address */
+#define CTRL_BASE		0x48140000
+
+/* PRCM Base Address */
+#define PRCM_BASE		0x48180000
+
+#define PRM_RSTCTRL		(PRCM_BASE + 0x00A0)
+#define PRM_RSTST		(PRM_RSTCTRL + 8)
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR		0x48198358
+#define VTP1_CTRL_ADDR		0x4819A358
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR	0x48198000
+#define DDR_PHY_DATA_ADDR	0x481980C8
+#define DDR_PHY_CMD_ADDR2	0x4819A000
+#define DDR_PHY_DATA_ADDR2	0x4819A0C8
+#define DDR_DATA_REGS_NR	4
+
+
+#define DDRPHY_0_CONFIG_BASE	0x48198000
+#define DDRPHY_1_CONFIG_BASE	0x4819A000
+#define DDRPHY_CONFIG_BASE	((emif == 0) ? \
+	DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
+
+/* RTC base address */
+#define RTC_BASE		0x480C0000
+
+#endif /* __AM33XX_HARDWARE_TI816X_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h
new file mode 100644
index 000000000..8642c8f87
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/i2c.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _I2C_AM33XX_H_
+#define _I2C_AM33XX_H_
+
+#define  I2C_BASE1		0x44E0B000
+#define  I2C_BASE2		0x4802A000
+#define  I2C_BASE3		0x4819C000
+#define	 I2C_BUS_MAX		3
+
+#define I2C_DEFAULT_BASE		I2C_BASE1
+
+struct i2c {
+	unsigned short revnb_lo;        /* 0x00 */
+	unsigned short res1;
+	unsigned short revnb_hi;        /* 0x04 */
+	unsigned short res2[5];
+	unsigned short sysc;		/* 0x10 */
+	unsigned short res3[9];
+	unsigned short irqstatus_raw;   /* 0x24 */
+	unsigned short res4;
+	unsigned short stat;            /* 0x28 */
+	unsigned short res5;
+	unsigned short ie;              /* 0x2C */
+	unsigned short res6;
+	unsigned short irqenable_clr;   /* 0x30 */
+	unsigned short res7;
+	unsigned short iv;              /* 0x34 */
+	unsigned short res8[45];
+	unsigned short syss;            /* 0x90 */
+	unsigned short res9;
+	unsigned short buf;             /* 0x94 */
+	unsigned short res10;
+	unsigned short cnt;             /* 0x98 */
+	unsigned short res11;
+	unsigned short data;            /* 0x9C */
+	unsigned short res13;
+	unsigned short res14;           /* 0xA0 */
+	unsigned short res15;
+	unsigned short con;             /* 0xA4 */
+	unsigned short res16;
+	unsigned short oa;              /* 0xA8 */
+	unsigned short res17;
+	unsigned short sa;              /* 0xAC */
+	unsigned short res18;
+	unsigned short psc;             /* 0xB0 */
+	unsigned short res19;
+	unsigned short scll;            /* 0xB4 */
+	unsigned short res20;
+	unsigned short sclh;            /* 0xB8 */
+	unsigned short res21;
+	unsigned short systest;         /* 0xBC */
+	unsigned short res22;
+	unsigned short bufstat;         /* 0xC0 */
+	unsigned short res23;
+};
+
+#define I2C_IP_CLK			48000000
+#define I2C_INTERNAL_SAMPLING_CLK	12000000
+
+#endif /* _I2C_AM33XX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h
new file mode 100644
index 000000000..e7e8c58b0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mem.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ *		Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *		Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * M_NAND - Micron NAND
+ * STNOR - STMicrolelctronics M29W128GL
+ */
+#define GPMC_SIZE_256M		0x0
+#define GPMC_SIZE_128M		0x8
+#define GPMC_SIZE_64M		0xC
+#define GPMC_SIZE_32M		0xE
+#define GPMC_SIZE_16M		0xF
+
+#define M_NAND_GPMC_CONFIG1	0x00000800
+#define M_NAND_GPMC_CONFIG2	0x001e1e00
+#define M_NAND_GPMC_CONFIG3	0x001e1e00
+#define M_NAND_GPMC_CONFIG4	0x16051807
+#define M_NAND_GPMC_CONFIG5	0x00151e1e
+#define M_NAND_GPMC_CONFIG6	0x16000f80
+#define M_NAND_GPMC_CONFIG7	0x00000008
+
+#define STNOR_GPMC_CONFIG1	0x00001200
+#define STNOR_GPMC_CONFIG2	0x00101000
+#define STNOR_GPMC_CONFIG3	0x00030301
+#define STNOR_GPMC_CONFIG4	0x10041004
+#define STNOR_GPMC_CONFIG5	0x000C1010
+#define STNOR_GPMC_CONFIG6	0x08070280
+#define STNOR_GPMC_CONFIG7	0x00000F48
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS		8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG		7
+
+#define PISMO1_NOR		1
+#define PISMO1_NAND		2
+#define PISMO2_CS0		3
+#define PISMO2_CS1		4
+#define PISMO1_ONENAND		5
+#define DBG_MPDB		6
+#define PISMO2_NAND_CS0		7
+#define PISMO2_NAND_CS1		8
+
+#endif /* endif _MEM_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
new file mode 100644
index 000000000..724e25294
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -0,0 +1,35 @@
+/*
+ * mmc_host_def.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+#include <asm/omap_mmc.h>
+
+/*
+ * OMAP HSMMC register definitions
+ */
+#define OMAP_HSMMC1_BASE		0x48060100
+#define OMAP_HSMMC2_BASE		0x481D8100
+
+#if defined(CONFIG_TI814X)
+#undef MMC_CLOCK_REFERENCE
+#define MMC_CLOCK_REFERENCE	192 /* MHz */
+#elif defined(CONFIG_TI816X)
+#undef MMC_CLOCK_REFERENCE
+#define MMC_CLOCK_REFERENCE	48 /* MHz */
+#endif
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h
new file mode 100644
index 000000000..324943726
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux.h
@@ -0,0 +1,47 @@
+/*
+ * mux.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_H_
+#define _MUX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_AM33XX
+#include <asm/arch/mux_am33xx.h>
+#elif defined(CONFIG_TI814X)
+#include <asm/arch/mux_ti814x.h>
+#elif defined(CONFIG_TI816X)
+#include <asm/arch/mux_ti816x.h>
+#elif defined(CONFIG_AM43XX)
+#include <asm/arch/mux_am43xx.h>
+#endif
+
+struct module_pin_mux {
+	short reg_offset;
+	unsigned int val;
+};
+
+/* Pad control register offset */
+#define PAD_CTRL_BASE	0x800
+#define OFFSET(x)	(unsigned int) (&((struct pad_signals *) \
+				(PAD_CTRL_BASE))->x)
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
+
+#endif /* endif _MUX_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
new file mode 100644
index 000000000..d5cab3e08
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
@@ -0,0 +1,247 @@
+/*
+ * mux_am33xx.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_AM33XX_H_
+#define _MUX_AM33XX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)	\
+	__raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL	(0x1 << 6)
+#define RXACTIVE	(0x1 << 5)
+#define PULLDOWN_EN	(0x0 << 4) /* Pull Down Selection */
+#define PULLUP_EN	(0x1 << 4) /* Pull Up Selection */
+#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
+#define MODE(val)	val	/* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int gpmc_ad0;
+	int gpmc_ad1;
+	int gpmc_ad2;
+	int gpmc_ad3;
+	int gpmc_ad4;
+	int gpmc_ad5;
+	int gpmc_ad6;
+	int gpmc_ad7;
+	int gpmc_ad8;
+	int gpmc_ad9;
+	int gpmc_ad10;
+	int gpmc_ad11;
+	int gpmc_ad12;
+	int gpmc_ad13;
+	int gpmc_ad14;
+	int gpmc_ad15;
+	int gpmc_a0;
+	int gpmc_a1;
+	int gpmc_a2;
+	int gpmc_a3;
+	int gpmc_a4;
+	int gpmc_a5;
+	int gpmc_a6;
+	int gpmc_a7;
+	int gpmc_a8;
+	int gpmc_a9;
+	int gpmc_a10;
+	int gpmc_a11;
+	int gpmc_wait0;
+	int gpmc_wpn;
+	int gpmc_be1n;
+	int gpmc_csn0;
+	int gpmc_csn1;
+	int gpmc_csn2;
+	int gpmc_csn3;
+	int gpmc_clk;
+	int gpmc_advn_ale;
+	int gpmc_oen_ren;
+	int gpmc_wen;
+	int gpmc_be0n_cle;
+	int lcd_data0;
+	int lcd_data1;
+	int lcd_data2;
+	int lcd_data3;
+	int lcd_data4;
+	int lcd_data5;
+	int lcd_data6;
+	int lcd_data7;
+	int lcd_data8;
+	int lcd_data9;
+	int lcd_data10;
+	int lcd_data11;
+	int lcd_data12;
+	int lcd_data13;
+	int lcd_data14;
+	int lcd_data15;
+	int lcd_vsync;
+	int lcd_hsync;
+	int lcd_pclk;
+	int lcd_ac_bias_en;
+	int mmc0_dat3;
+	int mmc0_dat2;
+	int mmc0_dat1;
+	int mmc0_dat0;
+	int mmc0_clk;
+	int mmc0_cmd;
+	int mii1_col;
+	int mii1_crs;
+	int mii1_rxerr;
+	int mii1_txen;
+	int mii1_rxdv;
+	int mii1_txd3;
+	int mii1_txd2;
+	int mii1_txd1;
+	int mii1_txd0;
+	int mii1_txclk;
+	int mii1_rxclk;
+	int mii1_rxd3;
+	int mii1_rxd2;
+	int mii1_rxd1;
+	int mii1_rxd0;
+	int rmii1_refclk;
+	int mdio_data;
+	int mdio_clk;
+	int spi0_sclk;
+	int spi0_d0;
+	int spi0_d1;
+	int spi0_cs0;
+	int spi0_cs1;
+	int ecap0_in_pwm0_out;
+	int uart0_ctsn;
+	int uart0_rtsn;
+	int uart0_rxd;
+	int uart0_txd;
+	int uart1_ctsn;
+	int uart1_rtsn;
+	int uart1_rxd;
+	int uart1_txd;
+	int i2c0_sda;
+	int i2c0_scl;
+	int mcasp0_aclkx;
+	int mcasp0_fsx;
+	int mcasp0_axr0;
+	int mcasp0_ahclkr;
+	int mcasp0_aclkr;
+	int mcasp0_fsr;
+	int mcasp0_axr1;
+	int mcasp0_ahclkx;
+	int xdma_event_intr0;
+	int xdma_event_intr1;
+	int nresetin_out;
+	int porz;
+	int nnmi;
+	int osc0_in;
+	int osc0_out;
+	int rsvd1;
+	int tms;
+	int tdi;
+	int tdo;
+	int tck;
+	int ntrst;
+	int emu0;
+	int emu1;
+	int osc1_in;
+	int osc1_out;
+	int pmic_power_en;
+	int rtc_porz;
+	int rsvd2;
+	int ext_wakeup;
+	int enz_kaldo_1p8v;
+	int usb0_dm;
+	int usb0_dp;
+	int usb0_ce;
+	int usb0_id;
+	int usb0_vbus;
+	int usb0_drvvbus;
+	int usb1_dm;
+	int usb1_dp;
+	int usb1_ce;
+	int usb1_id;
+	int usb1_vbus;
+	int usb1_drvvbus;
+	int ddr_resetn;
+	int ddr_csn0;
+	int ddr_cke;
+	int ddr_ck;
+	int ddr_nck;
+	int ddr_casn;
+	int ddr_rasn;
+	int ddr_wen;
+	int ddr_ba0;
+	int ddr_ba1;
+	int ddr_ba2;
+	int ddr_a0;
+	int ddr_a1;
+	int ddr_a2;
+	int ddr_a3;
+	int ddr_a4;
+	int ddr_a5;
+	int ddr_a6;
+	int ddr_a7;
+	int ddr_a8;
+	int ddr_a9;
+	int ddr_a10;
+	int ddr_a11;
+	int ddr_a12;
+	int ddr_a13;
+	int ddr_a14;
+	int ddr_a15;
+	int ddr_odt;
+	int ddr_d0;
+	int ddr_d1;
+	int ddr_d2;
+	int ddr_d3;
+	int ddr_d4;
+	int ddr_d5;
+	int ddr_d6;
+	int ddr_d7;
+	int ddr_d8;
+	int ddr_d9;
+	int ddr_d10;
+	int ddr_d11;
+	int ddr_d12;
+	int ddr_d13;
+	int ddr_d14;
+	int ddr_d15;
+	int ddr_dqm0;
+	int ddr_dqm1;
+	int ddr_dqs0;
+	int ddr_dqsn0;
+	int ddr_dqs1;
+	int ddr_dqsn1;
+	int ddr_vref;
+	int ddr_vtp;
+	int ddr_strben0;
+	int ddr_strben1;
+	int ain7;
+	int ain6;
+	int ain5;
+	int ain4;
+	int ain3;
+	int ain2;
+	int ain1;
+	int ain0;
+	int vrefp;
+	int vrefn;
+};
+
+#endif /* endif _MUX_AM33XX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
new file mode 100644
index 000000000..98fc2b50d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
@@ -0,0 +1,187 @@
+/*
+ * mux_am43xx.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MUX_AM43XX_H_
+#define _MUX_AM43XX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)	\
+	__raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL	(0x1 << 19)
+#define RXACTIVE	(0x1 << 18)
+#define PULLDOWN_EN	(0x0 << 17) /* Pull Down Selection */
+#define PULLUP_EN	(0x1 << 17) /* Pull Up Selection */
+#define PULLUDEN	(0x0 << 16) /* Pull up/down enable */
+#define PULLUDDIS	(0x1 << 16) /* Pull up/down disable */
+#define MODE(val)	val	/* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int gpmc_ad0;
+	int gpmc_ad1;
+	int gpmc_ad2;
+	int gpmc_ad3;
+	int gpmc_ad4;
+	int gpmc_ad5;
+	int gpmc_ad6;
+	int gpmc_ad7;
+	int gpmc_ad8;
+	int gpmc_ad9;
+	int gpmc_ad10;
+	int gpmc_ad11;
+	int gpmc_ad12;
+	int gpmc_ad13;
+	int gpmc_ad14;
+	int gpmc_ad15;
+	int gpmc_a0;
+	int gpmc_a1;
+	int gpmc_a2;
+	int gpmc_a3;
+	int gpmc_a4;
+	int gpmc_a5;
+	int gpmc_a6;
+	int gpmc_a7;
+	int gpmc_a8;
+	int gpmc_a9;
+	int gpmc_a10;
+	int gpmc_a11;
+	int gpmc_wait0;
+	int gpmc_wpn;
+	int gpmc_be1n;
+	int gpmc_csn0;
+	int gpmc_csn1;
+	int gpmc_csn2;
+	int gpmc_csn3;
+	int gpmc_clk;
+	int gpmc_advn_ale;
+	int gpmc_oen_ren;
+	int gpmc_wen;
+	int gpmc_be0n_cle;
+	int lcd_data0;
+	int lcd_data1;
+	int lcd_data2;
+	int lcd_data3;
+	int lcd_data4;
+	int lcd_data5;
+	int lcd_data6;
+	int lcd_data7;
+	int lcd_data8;
+	int lcd_data9;
+	int lcd_data10;
+	int lcd_data11;
+	int lcd_data12;
+	int lcd_data13;
+	int lcd_data14;
+	int lcd_data15;
+	int lcd_vsync;
+	int lcd_hsync;
+	int lcd_pclk;
+	int lcd_ac_bias_en;
+	int mmc0_dat3;
+	int mmc0_dat2;
+	int mmc0_dat1;
+	int mmc0_dat0;
+	int mmc0_clk;
+	int mmc0_cmd;
+	int mii1_col;
+	int mii1_crs;
+	int mii1_rxerr;
+	int mii1_txen;
+	int mii1_rxdv;
+	int mii1_txd3;
+	int mii1_txd2;
+	int mii1_txd1;
+	int mii1_txd0;
+	int mii1_txclk;
+	int mii1_rxclk;
+	int mii1_rxd3;
+	int mii1_rxd2;
+	int mii1_rxd1;
+	int mii1_rxd0;
+	int rmii1_refclk;
+	int mdio_data;
+	int mdio_clk;
+	int spi0_sclk;
+	int spi0_d0;
+	int spi0_d1;
+	int spi0_cs0;
+	int spi0_cs1;
+	int ecap0_in_pwm0_out;
+	int uart0_ctsn;
+	int uart0_rtsn;
+	int uart0_rxd;
+	int uart0_txd;
+	int uart1_ctsn;
+	int uart1_rtsn;
+	int uart1_rxd;
+	int uart1_txd;
+	int i2c0_sda;
+	int i2c0_scl;
+	int mcasp0_aclkx;
+	int mcasp0_fsx;
+	int mcasp0_axr0;
+	int mcasp0_ahclkr;
+	int mcasp0_aclkr;
+	int mcasp0_fsr;
+	int mcasp0_axr1;
+	int mcasp0_ahclkx;
+	int xdma_event_intr0;
+	int xdma_event_intr1;
+	int nresetin_out;
+	int porz;
+	int nnmi;
+	int osc0_in;
+	int osc0_out;
+	int rsvd1;
+	int tms;
+	int tdi;
+	int tdo;
+	int tck;
+	int ntrst;
+	int emu0;
+	int emu1;
+	int osc1_in;
+	int osc1_out;
+	int pmic_power_en;
+	int rtc_porz;
+	int rsvd2;
+	int ext_wakeup;
+	int enz_kaldo_1p8v;
+	int usb0_dm;
+	int usb0_dp;
+	int usb0_ce;
+	int usb0_id;
+	int usb0_vbus;
+	int usb0_drvvbus;
+	int usb1_dm;
+	int usb1_dp;
+	int usb1_ce;
+	int usb1_id;
+	int usb1_vbus;
+	int usb1_drvvbus;
+	int ddr_resetn;
+	int ddr_csn0;
+	int ddr_cke;
+	int ddr_ck;
+	int ddr_nck;
+	int ddr_casn;
+	int ddr_rasn;
+	int ddr_wen;
+	int ddr_ba0;
+	int ddr_ba1;
+	int ddr_ba2;
+};
+
+#endif /* _MUX_AM43XX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h
new file mode 100644
index 000000000..a26e5038f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti814x.h
@@ -0,0 +1,311 @@
+/*
+ * mux_ti814x.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_TI814X_H_
+#define _MUX_TI814X_H_
+
+/* PAD Control Fields */
+#define PINCNTL_RSV_MSK	(0x3 << 18) /* Reserved bitmask */
+#define PULLUP_EN	(0x1 << 17) /* Pull UP Selection */
+#define PULLUDEN	(0x0 << 16) /* Pull up enabled */
+#define PULLUDDIS	(0x1 << 16) /* Pull up disabled */
+#define MODE(val)	val	/* used for Readability */
+
+#define MUX_CFG(value, offset)				\
+{							\
+	int tmp;					\
+	tmp = __raw_readl(CTRL_BASE + offset);		\
+	tmp &= PINCNTL_RSV_MSK;				\
+	__raw_writel(tmp | value, (CTRL_BASE + offset));\
+}
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int pincntl1;
+	int pincntl2;
+	int pincntl3;
+	int pincntl4;
+	int pincntl5;
+	int pincntl6;
+	int pincntl7;
+	int pincntl8;
+	int pincntl9;
+	int pincntl10;
+	int pincntl11;
+	int pincntl12;
+	int pincntl13;
+	int pincntl14;
+	int pincntl15;
+	int pincntl16;
+	int pincntl17;
+	int pincntl18;
+	int pincntl19;
+	int pincntl20;
+	int pincntl21;
+	int pincntl22;
+	int pincntl23;
+	int pincntl24;
+	int pincntl25;
+	int pincntl26;
+	int pincntl27;
+	int pincntl28;
+	int pincntl29;
+	int pincntl30;
+	int pincntl31;
+	int pincntl32;
+	int pincntl33;
+	int pincntl34;
+	int pincntl35;
+	int pincntl36;
+	int pincntl37;
+	int pincntl38;
+	int pincntl39;
+	int pincntl40;
+	int pincntl41;
+	int pincntl42;
+	int pincntl43;
+	int pincntl44;
+	int pincntl45;
+	int pincntl46;
+	int pincntl47;
+	int pincntl48;
+	int pincntl49;
+	int pincntl50;
+	int pincntl51;
+	int pincntl52;
+	int pincntl53;
+	int pincntl54;
+	int pincntl55;
+	int pincntl56;
+	int pincntl57;
+	int pincntl58;
+	int pincntl59;
+	int pincntl60;
+	int pincntl61;
+	int pincntl62;
+	int pincntl63;
+	int pincntl64;
+	int pincntl65;
+	int pincntl66;
+	int pincntl67;
+	int pincntl68;
+	int pincntl69;
+	int pincntl70;
+	int pincntl71;
+	int pincntl72;
+	int pincntl73;
+	int pincntl74;
+	int pincntl75;
+	int pincntl76;
+	int pincntl77;
+	int pincntl78;
+	int pincntl79;
+	int pincntl80;
+	int pincntl81;
+	int pincntl82;
+	int pincntl83;
+	int pincntl84;
+	int pincntl85;
+	int pincntl86;
+	int pincntl87;
+	int pincntl88;
+	int pincntl89;
+	int pincntl90;
+	int pincntl91;
+	int pincntl92;
+	int pincntl93;
+	int pincntl94;
+	int pincntl95;
+	int pincntl96;
+	int pincntl97;
+	int pincntl98;
+	int pincntl99;
+	int pincntl100;
+	int pincntl101;
+	int pincntl102;
+	int pincntl103;
+	int pincntl104;
+	int pincntl105;
+	int pincntl106;
+	int pincntl107;
+	int pincntl108;
+	int pincntl109;
+	int pincntl110;
+	int pincntl111;
+	int pincntl112;
+	int pincntl113;
+	int pincntl114;
+	int pincntl115;
+	int pincntl116;
+	int pincntl117;
+	int pincntl118;
+	int pincntl119;
+	int pincntl120;
+	int pincntl121;
+	int pincntl122;
+	int pincntl123;
+	int pincntl124;
+	int pincntl125;
+	int pincntl126;
+	int pincntl127;
+	int pincntl128;
+	int pincntl129;
+	int pincntl130;
+	int pincntl131;
+	int pincntl132;
+	int pincntl133;
+	int pincntl134;
+	int pincntl135;
+	int pincntl136;
+	int pincntl137;
+	int pincntl138;
+	int pincntl139;
+	int pincntl140;
+	int pincntl141;
+	int pincntl142;
+	int pincntl143;
+	int pincntl144;
+	int pincntl145;
+	int pincntl146;
+	int pincntl147;
+	int pincntl148;
+	int pincntl149;
+	int pincntl150;
+	int pincntl151;
+	int pincntl152;
+	int pincntl153;
+	int pincntl154;
+	int pincntl155;
+	int pincntl156;
+	int pincntl157;
+	int pincntl158;
+	int pincntl159;
+	int pincntl160;
+	int pincntl161;
+	int pincntl162;
+	int pincntl163;
+	int pincntl164;
+	int pincntl165;
+	int pincntl166;
+	int pincntl167;
+	int pincntl168;
+	int pincntl169;
+	int pincntl170;
+	int pincntl171;
+	int pincntl172;
+	int pincntl173;
+	int pincntl174;
+	int pincntl175;
+	int pincntl176;
+	int pincntl177;
+	int pincntl178;
+	int pincntl179;
+	int pincntl180;
+	int pincntl181;
+	int pincntl182;
+	int pincntl183;
+	int pincntl184;
+	int pincntl185;
+	int pincntl186;
+	int pincntl187;
+	int pincntl188;
+	int pincntl189;
+	int pincntl190;
+	int pincntl191;
+	int pincntl192;
+	int pincntl193;
+	int pincntl194;
+	int pincntl195;
+	int pincntl196;
+	int pincntl197;
+	int pincntl198;
+	int pincntl199;
+	int pincntl200;
+	int pincntl201;
+	int pincntl202;
+	int pincntl203;
+	int pincntl204;
+	int pincntl205;
+	int pincntl206;
+	int pincntl207;
+	int pincntl208;
+	int pincntl209;
+	int pincntl210;
+	int pincntl211;
+	int pincntl212;
+	int pincntl213;
+	int pincntl214;
+	int pincntl215;
+	int pincntl216;
+	int pincntl217;
+	int pincntl218;
+	int pincntl219;
+	int pincntl220;
+	int pincntl221;
+	int pincntl222;
+	int pincntl223;
+	int pincntl224;
+	int pincntl225;
+	int pincntl226;
+	int pincntl227;
+	int pincntl228;
+	int pincntl229;
+	int pincntl230;
+	int pincntl231;
+	int pincntl232;
+	int pincntl233;
+	int pincntl234;
+	int pincntl235;
+	int pincntl236;
+	int pincntl237;
+	int pincntl238;
+	int pincntl239;
+	int pincntl240;
+	int pincntl241;
+	int pincntl242;
+	int pincntl243;
+	int pincntl244;
+	int pincntl245;
+	int pincntl246;
+	int pincntl247;
+	int pincntl248;
+	int pincntl249;
+	int pincntl250;
+	int pincntl251;
+	int pincntl252;
+	int pincntl253;
+	int pincntl254;
+	int pincntl255;
+	int pincntl256;
+	int pincntl257;
+	int pincntl258;
+	int pincntl259;
+	int pincntl260;
+	int pincntl261;
+	int pincntl262;
+	int pincntl263;
+	int pincntl264;
+	int pincntl265;
+	int pincntl266;
+	int pincntl267;
+	int pincntl268;
+	int pincntl269;
+	int pincntl270;
+};
+
+#endif /* endif _MUX_TI814X_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
new file mode 100644
index 000000000..e4e5a48ad
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
@@ -0,0 +1,363 @@
+/*
+ * mux_ti816x.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_TI816X_H_
+#define _MUX_TI816X_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)  \
+	__raw_writel(value, (CTRL_BASE + offset));
+
+#define PULLDOWN_EN	(0x0 << 4)	/* Pull Down Selection */
+#define PULLUP_EN	(0x1 << 4)	/* Pull Up Selection */
+#define PULLUDEN	(0x0 << 3)	/* Pull up enabled */
+#define PULLUDDIS	(0x1 << 3)	/* Pull up disabled */
+#define MODE(val)	(val)		/* used for Readability */
+
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int pincntl1;
+	int pincntl2;
+	int pincntl3;
+	int pincntl4;
+	int pincntl5;
+	int pincntl6;
+	int pincntl7;
+	int pincntl8;
+	int pincntl9;
+	int pincntl10;
+	int pincntl11;
+	int pincntl12;
+	int pincntl13;
+	int pincntl14;
+	int pincntl15;
+	int pincntl16;
+	int pincntl17;
+	int pincntl18;
+	int pincntl19;
+	int pincntl20;
+	int pincntl21;
+	int pincntl22;
+	int pincntl23;
+	int pincntl24;
+	int pincntl25;
+	int pincntl26;
+	int pincntl27;
+	int pincntl28;
+	int pincntl29;
+	int pincntl30;
+	int pincntl31;
+	int pincntl32;
+	int pincntl33;
+	int pincntl34;
+	int pincntl35;
+	int pincntl36;
+	int pincntl37;
+	int pincntl38;
+	int pincntl39;
+	int pincntl40;
+	int pincntl41;
+	int pincntl42;
+	int pincntl43;
+	int pincntl44;
+	int pincntl45;
+	int pincntl46;
+	int pincntl47;
+	int pincntl48;
+	int pincntl49;
+	int pincntl50;
+	int pincntl51;
+	int pincntl52;
+	int pincntl53;
+	int pincntl54;
+	int pincntl55;
+	int pincntl56;
+	int pincntl57;
+	int pincntl58;
+	int pincntl59;
+	int pincntl60;
+	int pincntl61;
+	int pincntl62;
+	int pincntl63;
+	int pincntl64;
+	int pincntl65;
+	int pincntl66;
+	int pincntl67;
+	int pincntl68;
+	int pincntl69;
+	int pincntl70;
+	int pincntl71;
+	int pincntl72;
+	int pincntl73;
+	int pincntl74;
+	int pincntl75;
+	int pincntl76;
+	int pincntl77;
+	int pincntl78;
+	int pincntl79;
+	int pincntl80;
+	int pincntl81;
+	int pincntl82;
+	int pincntl83;
+	int pincntl84;
+	int pincntl85;
+	int pincntl86;
+	int pincntl87;
+	int pincntl88;
+	int pincntl89;
+	int pincntl90;
+	int pincntl91;
+	int pincntl92;
+	int pincntl93;
+	int pincntl94;
+	int pincntl95;
+	int pincntl96;
+	int pincntl97;
+	int pincntl98;
+	int pincntl99;
+	int pincntl100;
+	int pincntl101;
+	int pincntl102;
+	int pincntl103;
+	int pincntl104;
+	int pincntl105;
+	int pincntl106;
+	int pincntl107;
+	int pincntl108;
+	int pincntl109;
+	int pincntl110;
+	int pincntl111;
+	int pincntl112;
+	int pincntl113;
+	int pincntl114;
+	int pincntl115;
+	int pincntl116;
+	int pincntl117;
+	int pincntl118;
+	int pincntl119;
+	int pincntl120;
+	int pincntl121;
+	int pincntl122;
+	int pincntl123;
+	int pincntl124;
+	int pincntl125;
+	int pincntl126;
+	int pincntl127;
+	int pincntl128;
+	int pincntl129;
+	int pincntl130;
+	int pincntl131;
+	int pincntl132;
+	int pincntl133;
+	int pincntl134;
+	int pincntl135;
+	int pincntl136;
+	int pincntl137;
+	int pincntl138;
+	int pincntl139;
+	int pincntl140;
+	int pincntl141;
+	int pincntl142;
+	int pincntl143;
+	int pincntl144;
+	int pincntl145;
+	int pincntl146;
+	int pincntl147;
+	int pincntl148;
+	int pincntl149;
+	int pincntl150;
+	int pincntl151;
+	int pincntl152;
+	int pincntl153;
+	int pincntl154;
+	int pincntl155;
+	int pincntl156;
+	int pincntl157;
+	int pincntl158;
+	int pincntl159;
+	int pincntl160;
+	int pincntl161;
+	int pincntl162;
+	int pincntl163;
+	int pincntl164;
+	int pincntl165;
+	int pincntl166;
+	int pincntl167;
+	int pincntl168;
+	int pincntl169;
+	int pincntl170;
+	int pincntl171;
+	int pincntl172;
+	int pincntl173;
+	int pincntl174;
+	int pincntl175;
+	int pincntl176;
+	int pincntl177;
+	int pincntl178;
+	int pincntl179;
+	int pincntl180;
+	int pincntl181;
+	int pincntl182;
+	int pincntl183;
+	int pincntl184;
+	int pincntl185;
+	int pincntl186;
+	int pincntl187;
+	int pincntl188;
+	int pincntl189;
+	int pincntl190;
+	int pincntl191;
+	int pincntl192;
+	int pincntl193;
+	int pincntl194;
+	int pincntl195;
+	int pincntl196;
+	int pincntl197;
+	int pincntl198;
+	int pincntl199;
+	int pincntl200;
+	int pincntl201;
+	int pincntl202;
+	int pincntl203;
+	int pincntl204;
+	int pincntl205;
+	int pincntl206;
+	int pincntl207;
+	int pincntl208;
+	int pincntl209;
+	int pincntl210;
+	int pincntl211;
+	int pincntl212;
+	int pincntl213;
+	int pincntl214;
+	int pincntl215;
+	int pincntl216;
+	int pincntl217;
+	int pincntl218;
+	int pincntl219;
+	int pincntl220;
+	int pincntl221;
+	int pincntl222;
+	int pincntl223;
+	int pincntl224;
+	int pincntl225;
+	int pincntl226;
+	int pincntl227;
+	int pincntl228;
+	int pincntl229;
+	int pincntl230;
+	int pincntl231;
+	int pincntl232;
+	int pincntl233;
+	int pincntl234;
+	int pincntl235;
+	int pincntl236;
+	int pincntl237;
+	int pincntl238;
+	int pincntl239;
+	int pincntl240;
+	int pincntl241;
+	int pincntl242;
+	int pincntl243;
+	int pincntl244;
+	int pincntl245;
+	int pincntl246;
+	int pincntl247;
+	int pincntl248;
+	int pincntl249;
+	int pincntl250;
+	int pincntl251;
+	int pincntl252;
+	int pincntl253;
+	int pincntl254;
+	int pincntl255;
+	int pincntl256;
+	int pincntl257;
+	int pincntl258;
+	int pincntl259;
+	int pincntl260;
+	int pincntl261;
+	int pincntl262;
+	int pincntl263;
+	int pincntl264;
+	int pincntl265;
+	int pincntl266;
+	int pincntl267;
+	int pincntl268;
+	int pincntl269;
+	int pincntl270;
+	int pincntl271;
+	int pincntl272;
+	int pincntl273;
+	int pincntl274;
+	int pincntl275;
+	int pincntl276;
+	int pincntl277;
+	int pincntl278;
+	int pincntl279;
+	int pincntl280;
+	int pincntl281;
+	int pincntl282;
+	int pincntl283;
+	int pincntl284;
+	int pincntl285;
+	int pincntl286;
+	int pincntl287;
+	int pincntl288;
+	int pincntl289;
+	int pincntl290;
+	int pincntl291;
+	int pincntl292;
+	int pincntl293;
+	int pincntl294;
+	int pincntl295;
+	int pincntl296;
+	int pincntl297;
+	int pincntl298;
+	int pincntl299;
+	int pincntl300;
+	int pincntl301;
+	int pincntl302;
+	int pincntl303;
+	int pincntl304;
+	int pincntl305;
+	int pincntl306;
+	int pincntl307;
+	int pincntl308;
+	int pincntl309;
+	int pincntl310;
+	int pincntl311;
+	int pincntl312;
+	int pincntl313;
+	int pincntl314;
+	int pincntl315;
+	int pincntl316;
+	int pincntl317;
+	int pincntl318;
+	int pincntl319;
+	int pincntl320;
+	int pincntl321;
+	int pincntl322;
+	int pincntl323;
+};
+
+#endif /* endif _MUX_TI816X_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/omap.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/omap.h
new file mode 100644
index 000000000..0855d16ce
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/omap.h
@@ -0,0 +1,34 @@
+/*
+ * omap.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Author:
+ *	Chandan Nath <chandan.nath@ti.com>
+ *
+ * Derived from OMAP4 work by
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _OMAP_H_
+#define _OMAP_H_
+
+#ifdef CONFIG_AM33XX
+#define NON_SECURE_SRAM_START	0x402F0400
+#define NON_SECURE_SRAM_END	0x40310000
+#define SRAM_SCRATCH_SPACE_ADDR	0x4030B800
+#elif defined(CONFIG_TI81XX)
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40320000
+#define SRAM_SCRATCH_SPACE_ADDR	0x4031B800
+#elif defined(CONFIG_AM43XX)
+#define NON_SECURE_SRAM_START	0x402F0400
+#define NON_SECURE_SRAM_END	0x40340000
+#define SRAM_SCRATCH_SPACE_ADDR	0x40337C00
+#define AM4372_BOARD_NAME_START	SRAM_SCRATCH_SPACE_ADDR
+#define AM4372_BOARD_NAME_END	SRAM_SCRATCH_SPACE_ADDR + 0xC
+#define QSPI_BASE              0x47900000
+#endif
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h
new file mode 100644
index 000000000..8543f4399
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/spl.h
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#if defined(CONFIG_TI816X)
+#define BOOT_DEVICE_XIP		2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_MMC1	6
+#define BOOT_DEVICE_MMC2	5
+#define BOOT_DEVICE_UART	0x43
+#elif defined(CONFIG_AM43XX)
+#define BOOT_DEVICE_NOR		1
+#define BOOT_DEVICE_NAND	5
+#define BOOT_DEVICE_MMC1	7
+#define BOOT_DEVICE_MMC2	8
+#define BOOT_DEVICE_SPI		10
+#define BOOT_DEVICE_USB     13
+#define BOOT_DEVICE_UART	65
+#define BOOT_DEVICE_CPGMAC	71
+#else
+#define BOOT_DEVICE_XIP       	2
+#define BOOT_DEVICE_NAND	5
+#if defined(CONFIG_AM33XX)
+#define BOOT_DEVICE_MMC1	8
+#define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
+#elif defined(CONFIG_TI814X)
+#define BOOT_DEVICE_MMC1	9
+#define BOOT_DEVICE_MMC2	8	/* ROM only supports 2nd instance */
+#endif
+#define BOOT_DEVICE_SPI		11
+#define BOOT_DEVICE_UART	65
+#define BOOT_DEVICE_USBETH	68
+#define BOOT_DEVICE_CPGMAC	70
+#endif
+#define BOOT_DEVICE_MMC2_2      0xFF
+
+#if defined(CONFIG_AM33XX)
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END   BOOT_DEVICE_MMC2
+#elif defined(CONFIG_AM43XX)
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
+#ifdef CONFIG_SPL_USB_SUPPORT
+#define MMC_BOOT_DEVICES_END   BOOT_DEVICE_USB
+#else
+#define MMC_BOOT_DEVICES_END   BOOT_DEVICE_MMC2
+#endif
+#elif defined(CONFIG_TI81XX)
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC2
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC1
+#endif
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h
new file mode 100644
index 000000000..91ff2ad0e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -0,0 +1,46 @@
+/*
+ * sys_proto.h
+ *
+ * System information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+#include <linux/mtd/omap_gpmc.h>
+#include <asm/arch/cpu.h>
+
+#define BOARD_REV_ID	0x0
+
+u32 get_cpu_rev(void);
+u32 get_sysboot_value(void);
+
+extern struct ctrl_stat *cstat;
+u32 get_device_type(void);
+void save_omap_boot_params(void);
+void setup_clocks_for_console(void);
+void mpu_pll_config_val(int mpull_m);
+void ddr_pll_config(unsigned int ddrpll_M);
+
+void sdelay(unsigned long);
+
+struct gpmc_cs;
+void gpmc_init(void);
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+			u32 size);
+void omap_nand_switch_ecc(uint32_t, uint32_t);
+
+void set_uart_mux_conf(void);
+void set_mux_conf_regs(void);
+void sdram_init(void);
+u32 wait_on_value(u32, u32, void *, u32);
+#ifdef CONFIG_NOR_BOOT
+void enable_norboot_pin_mux(void);
+#endif
+void am33xx_spl_board_init(void);
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-arm720t/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-arm720t/hardware.h
new file mode 100644
index 000000000..8ca42d9e7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-arm720t/hardware.h
@@ -0,0 +1,17 @@
+#ifndef __ARM7_HW_H
+#define __ARM7_HW_H
+
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+/* include IntegratorCP/CM720T specific hardware file if there was one */
+#else
+#error No hardware file defined for this configuration
+#endif
+
+#endif /* __ARM7_HW_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/armada100.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/armada100.h
new file mode 100644
index 000000000..d9feb1608
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/armada100.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_ARMADA100_H
+#define _ASM_ARCH_ARMADA100_H
+
+#if defined (CONFIG_ARMADA100)
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
+#define APBC_RST        (1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST		0x1
+#define FE_CLK_ENA		0x8
+
+/* SSP2 Clock Control */
+#define SSP2_APBCLK		0x01
+#define SSP2_FNCLK		0x02
+
+/* USB Clock/reset control bits */
+#define USB_SPH_AXICLK_EN	0x10
+#define USB_SPH_AXI_RST		0x02
+
+/* MPMU Clocks */
+#define APB2_26M_EN		(1 << 20)
+#define AP_26M			(1 << 4)
+
+/* Register Base Addresses */
+#define ARMD1_DRAM_BASE		0xB0000000
+#define ARMD1_FEC_BASE		0xC0800000
+#define ARMD1_TIMER_BASE	0xD4014000
+#define ARMD1_APBC1_BASE	0xD4015000
+#define ARMD1_APBC2_BASE	0xD4015800
+#define ARMD1_UART1_BASE	0xD4017000
+#define ARMD1_UART2_BASE	0xD4018000
+#define ARMD1_GPIO_BASE		0xD4019000
+#define ARMD1_SSP1_BASE		0xD401B000
+#define ARMD1_SSP2_BASE		0xD401C000
+#define ARMD1_MFPR_BASE		0xD401E000
+#define ARMD1_SSP3_BASE		0xD401F000
+#define ARMD1_SSP4_BASE		0xD4020000
+#define ARMD1_SSP5_BASE		0xD4021000
+#define ARMD1_UART3_BASE	0xD4026000
+#define ARMD1_MPMU_BASE		0xD4050000
+#define ARMD1_USB_HOST_BASE	0xD4209000
+#define ARMD1_APMU_BASE		0xD4282800
+#define ARMD1_CPU_BASE		0xD4282C00
+
+#endif /* CONFIG_ARMADA100 */
+#endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/config.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/config.h
new file mode 100644
index 000000000..532411e1c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/config.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for Armada100 platform
+ */
+
+#ifndef _ARMD1_CONFIG_H
+#define _ARMD1_CONFIG_H
+
+#include <asm/arch/armada100.h>
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+/* default Dcache Line length for armada100 */
+#define CONFIG_SYS_CACHELINE_SIZE       32
+
+#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
+#define MV_MFPR_BASE		ARMD1_MFPR_BASE
+#define MV_UART_CONSOLE_BASE	ARMD1_UART1_BASE
+#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
+						represents UART Unit Enable */
+/*
+ * I2C definition
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MV		1
+#define CONFIG_MV_I2C_NUM	2
+#define CONFIG_I2C_MULTI_BUS	1
+#define CONFIG_MV_I2C_REG	{0xd4011000, 0xd4025000}
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_SPEED	0
+#define CONFIG_SYS_I2C_SLAVE	0xfe
+#endif
+
+#endif /* _ARMD1_CONFIG_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/cpu.h
new file mode 100644
index 000000000..c1f190dbd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/cpu.h
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ARMADA100CPU_H
+#define _ARMADA100CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Datasheet Appendix A.8
+ */
+struct armd1mpmu_registers {
+	u8 pad0[0x08 - 0x00];
+	u32 fccr;	/*0x0008*/
+	u32 pocr;	/*0x000c*/
+	u32 posr;	/*0x0010*/
+	u32 succr;	/*0x0014*/
+	u8 pad1[0x030 - 0x014 - 4];
+	u32 gpcr;	/*0x0030*/
+	u8 pad2[0x200 - 0x030 - 4];
+	u32 wdtpcr;	/*0x0200*/
+	u8 pad3[0x1000 - 0x200 - 4];
+	u32 apcr;	/*0x1000*/
+	u32 apsr;	/*0x1004*/
+	u8 pad4[0x1020 - 0x1004 - 4];
+	u32 aprr;	/*0x1020*/
+	u32 acgr;	/*0x1024*/
+	u32 arsr;	/*0x1028*/
+};
+
+/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+	u32 pcr;		/* 0x000 */
+	u32 ccr;		/* 0x004 */
+	u32 pad1;
+	u32 ccsr;		/* 0x00C */
+	u32 fc_timer;		/* 0x010 */
+	u32 pad2;
+	u32 ideal_cfg;		/* 0x018 */
+	u8 pad3[0x04C - 0x018 - 4];
+	u32 lcdcrc;		/* 0x04C */
+	u32 cciccrc;		/* 0x050 */
+	u32 sd1crc;		/* 0x054 */
+	u32 sd2crc;		/* 0x058 */
+	u32 usbcrc;		/* 0x05C */
+	u32 nfccrc;		/* 0x060 */
+	u32 dmacrc;		/* 0x064 */
+	u32 pad4;
+	u32 buscrc;		/* 0x06C */
+	u8 pad5[0x07C - 0x06C - 4];
+	u32 wake_clr;		/* 0x07C */
+	u8 pad6[0x090 - 0x07C - 4];
+	u32 core_status;	/* 0x090 */
+	u32 rfsc;		/* 0x094 */
+	u32 imr;		/* 0x098 */
+	u32 irwc;		/* 0x09C */
+	u32 isr;		/* 0x0A0 */
+	u8 pad7[0x0B0 - 0x0A0 - 4];
+	u32 mhst;		/* 0x0B0 */
+	u32 msr;		/* 0x0B4 */
+	u8 pad8[0x0C0 - 0x0B4 - 4];
+	u32 msst;		/* 0x0C0 */
+	u32 pllss;		/* 0x0C4 */
+	u32 smb;		/* 0x0C8 */
+	u32 gccrc;		/* 0x0CC */
+	u8 pad9[0x0D4 - 0x0CC - 4];
+	u32 smccrc;		/* 0x0D4 */
+	u32 pad10;
+	u32 xdcrc;		/* 0x0DC */
+	u32 sd3crc;		/* 0x0E0 */
+	u32 sd4crc;		/* 0x0E4 */
+	u8 pad11[0x0F0 - 0x0E4 - 4];
+	u32 cfcrc;		/* 0x0F0 */
+	u32 mspcrc;		/* 0x0F4 */
+	u32 cmucrc;		/* 0x0F8 */
+	u32 fecrc;		/* 0x0FC */
+	u32 pciecrc;		/* 0x100 */
+	u32 epdcrc;		/* 0x104 */
+};
+
+/*
+ * APB1 Clock Reset/Control Registers
+ * Refer Datasheet Appendix A.10
+ */
+struct armd1apb1_registers {
+	u32 uart1;	/*0x000*/
+	u32 uart2;	/*0x004*/
+	u32 gpio;	/*0x008*/
+	u32 pwm1;	/*0x00c*/
+	u32 pwm2;	/*0x010*/
+	u32 pwm3;	/*0x014*/
+	u32 pwm4;	/*0x018*/
+	u8 pad0[0x028 - 0x018 - 4];
+	u32 rtc;	/*0x028*/
+	u32 twsi0;	/*0x02c*/
+	u32 kpc;	/*0x030*/
+	u32 timers;	/*0x034*/
+	u8 pad1[0x03c - 0x034 - 4];
+	u32 aib;	/*0x03c*/
+	u32 sw_jtag;	/*0x040*/
+	u32 timer1;	/*0x044*/
+	u32 onewire;	/*0x048*/
+	u8 pad2[0x050 - 0x048 - 4];
+	u32 asfar;	/*0x050 AIB Secure First Access Reg*/
+	u32 assar;	/*0x054 AIB Secure Second Access Reg*/
+	u8 pad3[0x06c - 0x054 - 4];
+	u32 twsi1;	/*0x06c*/
+	u32 uart3;	/*0x070*/
+	u8 pad4[0x07c - 0x070 - 4];
+	u32 timer2;	/*0x07C*/
+	u8 pad5[0x084 - 0x07c - 4];
+	u32 ac97;	/*0x084*/
+};
+
+/*
+* APB2 Clock Reset/Control Registers
+* Refer Datasheet Appendix A.11
+*/
+struct armd1apb2_registers {
+	u32 pad1[0x01C - 0x000];
+	u32 ssp1_clkrst;		/* 0x01C */
+	u32 ssp2_clkrst;		/* 0x020 */
+	u32 pad2[0x04C - 0x020 - 4];
+	u32 ssp3_clkrst;		/* 0x04C */
+	u32 pad3[0x058 - 0x04C - 4];
+	u32 ssp4_clkrst;		/* 0x058 */
+	u32 ssp5_clkrst;		/* 0x05C */
+};
+
+/*
+ * CPU Interface Registers
+ * Refer Datasheet Appendix A.2
+ */
+struct armd1cpu_registers {
+	u32 chip_id;		/* Chip Id Reg */
+	u32 pad;
+	u32 cpu_conf;		/* CPU Conf Reg */
+	u32 pad1;
+	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
+	u32 pad2;
+	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
+	u32 mcb_conf;		/* MCB Conf Reg */
+	u32 sys_boot_ctl;	/* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 armd1_sdram_base(int);
+u32 armd1_sdram_size(int);
+
+#endif /* _ARMADA100CPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/gpio.h
new file mode 100644
index 000000000..4927abea9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/gpio.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include <asm/types.h>
+#include <asm/arch/armada100.h>
+
+#define GPIO_HIGH		1
+#define GPIO_LOW		0
+
+#define GPIO_TO_REG(gp)		(gp >> 5)
+#define GPIO_TO_BIT(gp)		(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val)	((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+	const unsigned int offset[4] = {0, 4, 8, 0x100};
+	/* gpio register bank offset - refer Appendix A.36 */
+	return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/mfp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/mfp.h
new file mode 100644
index 000000000..b918239e9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/mfp.h
@@ -0,0 +1,80 @@
+/*
+ * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
+ * (C) Copyright 2007
+ * Marvell Semiconductor <www.marvell.com>
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARMADA100_MFP_H
+#define __ARMADA100_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
+ *
+ * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART1 */
+#define MFP107_UART1_TXD	(MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
+#define MFP107_UART1_RXD	(MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
+#define MFP108_UART1_RXD	(MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
+#define MFP108_UART1_TXD	(MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
+#define MFP109_UART1_CTS	(MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP109_UART1_RTS	(MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP110_UART1_RTS	(MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP110_UART1_CTS	(MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP111_UART1_RI		(MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP111_UART1_DSR	(MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP112_UART1_DTR	(MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP112_UART1_DCD	(MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+/* UART2 */
+#define MFP47_UART2_RXD		(MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM)
+#define MFP48_UART2_TXD		(MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
+#define MFP88_UART2_RXD		(MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP89_UART2_TXD		(MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+/* UART3 */
+#define MFPO8_UART3_TXD		(MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFPO9_UART3_RXD		(MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+/* I2c */
+#define MFP105_CI2C_SDA		(MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP106_CI2C_SCL		(MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK	(MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN		(MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3	(MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2	(MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1	(MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0	(MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS		(MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL		(MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK	(MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER		(MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3	(MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2	(MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1	(MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP099_ETH_RXDQ0	(MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP100_ETH_MDC		(MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP101_ETH_MDIO		(MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP103_ETH_RXDV		(MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+
+/* SPI */
+#define MFP107_SSP2_RXD		(MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
+#define MFP108_SSP2_TXD		(MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM)
+#define MFP110_SSP2_CS		(MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP111_SSP2_CLK		(MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
+
+/* More macros can be defined here... */
+
+#define MFP_PIN_MAX	117
+
+#endif /* __ARMADA100_MFP_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/spi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/spi.h
new file mode 100644
index 000000000..9efa1bf1e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/spi.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARMADA100_SPI_H_
+#define __ARMADA100_SPI_H_
+
+#include <asm/arch/armada100.h>
+
+#define CAT_BASE_ADDR(x)	ARMD1_SSP ## x ## _BASE
+#define SSP_REG_BASE(x)		CAT_BASE_ADDR(x)
+
+/*
+ * SSP Serial Port Registers
+ * refer Appendix A.26
+ */
+struct ssp_reg {
+	u32 sscr0;	/* SSP Control Register 0 - 0x000 */
+	u32 sscr1;	/* SSP Control Register 1 - 0x004 */
+	u32 sssr;	/* SSP Status Register - 0x008 */
+	u32 ssitr;	/* SSP Interrupt Test Register - 0x00C */
+	u32 ssdr;	/* SSP Data Register - 0x010 */
+	u32 pad1[5];
+	u32 ssto;	/* SSP Timeout Register - 0x028 */
+	u32 sspsp;	/* SSP Programmable Serial Protocol Register - 0x02C */
+	u32 sstsa;	/* SSP TX Timeslot Active Register - 0x030 */
+	u32 ssrsa;	/* SSP RX Timeslot Active Register - 0x034 */
+	u32 sstss;	/* SSP Timeslot Status Register - 0x038 */
+};
+
+#define DEFAULT_WORD_LEN	8
+#define SSP_FLUSH_NUM		0x2000
+#define RX_THRESH_DEF		8
+#define TX_THRESH_DEF		8
+#define TIMEOUT_DEF		1000
+
+#define SSCR1_RIE	(1 << 0)	/* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE	(1 << 1)	/* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM	(1 << 2)	/* Loop-Back Mode */
+#define SSCR1_SPO	(1 << 3)	/* Motorola SPI SSPSCLK polarity
+					   setting */
+#define SSCR1_SPH	(1 << 4)	/* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS	(1 << 5)	/* Microwire Transmit Data Size */
+#define SSCR1_TFT	0x03c0		/* Transmit FIFO Threshold (mask) */
+#define SSCR1_RFT	0x3c00		/* Receive FIFO Threshold (mask) */
+
+#define SSCR1_TXTRESH(x)	((x - 1) << 6)	/* level [1..16] */
+#define SSCR1_RXTRESH(x)	((x - 1) << 10)	/* level [1..16] */
+#define SSCR1_TINTE		(1 << 19)	/* Receiver Time-out
+						   Interrupt enable */
+
+#define SSCR0_DSS		0x0f		/* Data Size Select (mask) */
+#define SSCR0_DATASIZE(x)	(x - 1)		/* Data Size Select [4..16] */
+#define SSCR0_FRF		0x30		/* FRame Format (mask) */
+#define SSCR0_MOTO		(0x0 << 4)	/* Motorola's Serial
+						   Peripheral Interface */
+#define SSCR0_TI		(0x1 << 4)	/* TI's Synchronous
+						   Serial Protocol (SSP) */
+#define SSCR0_NATIONAL		(0x2 << 4)	/* National Microwire */
+#define SSCR0_ECS		(1 << 6)	/* External clock select */
+#define SSCR0_SSE		(1 << 7)	/* Synchronous Serial Port
+						   Enable */
+
+#define SSSR_TNF	(1 << 2)	/* Transmit FIFO Not Full */
+#define SSSR_RNE	(1 << 3)	/* Receive FIFO Not Empty */
+#define SSSR_BSY	(1 << 4)	/* SSP Busy */
+#define SSSR_TFS	(1 << 5)	/* Transmit FIFO Service Request */
+#define SSSR_RFS	(1 << 6)	/* Receive FIFO Service Request */
+#define SSSR_ROR	(1 << 7)	/* Receive FIFO Overrun */
+#define SSSR_TINT	(1 << 19)	/* Receiver Time-out Interrupt */
+
+#endif /* __ARMADA100_SPI_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h
new file mode 100644
index 000000000..953dd4413
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armada100/utmi-armada100.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __UTMI_ARMADA100__
+#define __UTMI_ARMADA100__
+
+#define UTMI_PHY_BASE		0xD4206000
+
+/* utmi_ctrl - bits */
+#define INPKT_DELAY_SOF		(1 << 28)
+#define PLL_PWR_UP		2
+#define PHY_PWR_UP		1
+
+/* utmi_pll - bits */
+#define PLL_FBDIV_MASK		0x00000FF0
+#define PLL_FBDIV		4
+#define PLL_REFDIV_MASK		0x0000000F
+#define PLL_REFDIV		0
+#define PLL_READY		0x800000
+#define VCOCAL_START		(1 << 21)
+
+#define N_DIVIDER		0xEE
+#define M_DIVIDER		0x0B
+
+/* utmi_tx - bits */
+#define CK60_PHSEL		17
+#define PHSEL_VAL		0x4
+#define RCAL_START		(1 << 12)
+
+/*
+ * USB PHY registers
+ * Refer Datasheet Appendix A.21
+ */
+struct armd1usb_phy_reg {
+	u32 utmi_rev;	/* USB PHY Revision */
+	u32 utmi_ctrl;	/* USB PHY Control register */
+	u32 utmi_pll;	/* PLL register */
+	u32 utmi_tx;	/* Tx register */
+	u32 utmi_rx;	/* Rx register */
+	u32 utmi_ivref;	/* IVREF register */
+	u32 utmi_tst_g0;	/* Test group 0 register */
+	u32 utmi_tst_g1;	/* Test group 1 register */
+	u32 utmi_tst_g2;	/* Test group 2 register */
+	u32 utmi_tst_g3;	/* Test group 3 register */
+	u32 utmi_tst_g4;	/* Test group 4 register */
+	u32 utmi_tst_g5;	/* Test group 5 register */
+	u32 utmi_reserve;	/* Reserve Register */
+	u32 utmi_usb_int;	/* USB interuppt register */
+	u32 utmi_dbg_ctl;	/* Debug control register */
+	u32 utmi_otg_addon;	/* OTG addon register */
+};
+
+int utmi_init(void);
+
+#endif /* __UTMI_ARMADA100__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h
new file mode 100644
index 000000000..6a19950de
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/globaltimer.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _GLOBALTIMER_H_
+#define _GLOBALTIMER_H_
+
+struct globaltimer {
+	u32 cnt_l; /* 0x00 */
+	u32 cnt_h;
+	u32 ctl;
+	u32 stat;
+	u32 cmp_l; /* 0x10 */
+	u32 cmp_h;
+	u32 inc;
+};
+
+#endif /* _GLOBALTIMER_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h
new file mode 100644
index 000000000..34e88a8f2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/sysctrl.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SYSCTRL_H_
+#define _SYSCTRL_H_
+
+/* System controller (SP810) register definitions */
+#define SP810_TIMER0_ENSEL	(1 << 15)
+#define SP810_TIMER1_ENSEL	(1 << 17)
+#define SP810_TIMER2_ENSEL	(1 << 19)
+#define SP810_TIMER3_ENSEL	(1 << 21)
+
+struct sysctrl {
+	u32 scctrl;		/* 0x000 */
+	u32 scsysstat;
+	u32 scimctrl;
+	u32 scimstat;
+	u32 scxtalctrl;
+	u32 scpllctrl;
+	u32 scpllfctrl;
+	u32 scperctrl0;
+	u32 scperctrl1;
+	u32 scperen;
+	u32 scperdis;
+	u32 scperclken;
+	u32 scperstat;
+	u32 res1[0x006];
+	u32 scflashctrl;	/* 0x04c */
+	u32 res2[0x3a4];
+	u32 scsysid0;		/* 0xee0 */
+	u32 scsysid1;
+	u32 scsysid2;
+	u32 scsysid3;
+	u32 scitcr;
+	u32 scitir0;
+	u32 scitir1;
+	u32 scitor;
+	u32 sccntctrl;
+	u32 sccntdata;
+	u32 sccntstep;
+	u32 res3[0x32];
+	u32 scperiphid0;	/* 0xfe0 */
+	u32 scperiphid1;
+	u32 scperiphid2;
+	u32 scperiphid3;
+	u32 scpcellid0;
+	u32 scpcellid1;
+	u32 scpcellid2;
+	u32 scpcellid3;
+};
+#endif /* _SYSCTRL_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h
new file mode 100644
index 000000000..a0412bd34
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/systimer.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SYSTIMER_H_
+#define _SYSTIMER_H_
+
+/* AMBA timer register base address */
+#define SYSTIMER_BASE		0x10011000
+
+#define SYSHZ_CLOCK		1000000		/* Timers -> 1Mhz */
+#define SYSTIMER_RELOAD		0xFFFFFFFF
+#define SYSTIMER_EN		(1 << 7)
+#define SYSTIMER_32BIT		(1 << 1)
+#define SYSTIMER_PRESC_16	(1 << 2)
+#define SYSTIMER_PRESC_256	(1 << 3)
+
+struct systimer {
+	u32 timer0load;		/* 0x00 */
+	u32 timer0value;
+	u32 timer0control;
+	u32 timer0intclr;
+	u32 timer0ris;
+	u32 timer0mis;
+	u32 timer0bgload;
+	u32 timer1load;		/* 0x20 */
+	u32 timer1value;
+	u32 timer1control;
+	u32 timer1intclr;
+	u32 timer1ris;
+	u32 timer1mis;
+	u32 timer1bgload;
+};
+#endif /* _SYSTIMER_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h
new file mode 100644
index 000000000..4483b1a34
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-armv7/wdt.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2010
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _WDT_H_
+#define _WDT_H_
+
+/* Watchdog timer (SP805) register base address */
+#define WDT_BASE	0x100E5000
+
+#define WDT_EN		0x2
+#define WDT_RESET_LOAD	0x0
+
+struct wdt {
+	u32 wdogload;		/* 0x000 */
+	u32 wdogvalue;
+	u32 wdogcontrol;
+	u32 wdogintclr;
+	u32 wdogris;
+	u32 wdogmis;
+	u32 res1[0x2F9];
+	u32 wdoglock;		/* 0xC00 */
+	u32 res2[0xBE];
+	u32 wdogitcr;		/* 0xF00 */
+	u32 wdogitop;
+	u32 res3[0x35];
+	u32 wdogperiphid0;	/* 0xFE0 */
+	u32 wdogperiphid1;
+	u32 wdogperiphid2;
+	u32 wdogperiphid3;
+	u32 wdogpcellid0;
+	u32 wdogpcellid1;
+	u32 wdogpcellid2;
+	u32 wdogpcellid3;
+};
+
+#endif /* _WDT_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_common.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_common.h
new file mode 100644
index 000000000..59e2f4391
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_common.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_COMMON_H
+#define AT91_COMMON_H
+
+void at91_can_hw_init(void);
+void at91_gmac_hw_init(void);
+void at91_macb_hw_init(void);
+void at91_mci_hw_init(void);
+void at91_serial0_hw_init(void);
+void at91_serial1_hw_init(void);
+void at91_serial2_hw_init(void);
+void at91_seriald_hw_init(void);
+void at91_spi0_hw_init(unsigned long cs_mask);
+void at91_spi1_hw_init(unsigned long cs_mask);
+void at91_udp_hw_init(void);
+void at91_uhp_hw_init(void);
+void at91_lcd_hw_init(void);
+void at91_plla_init(u32 pllar);
+void at91_mck_init(u32 mckr);
+void at91_pmc_init(void);
+void mem_init(void);
+void at91_phy_reset(void);
+
+#endif /* AT91_COMMON_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_dbu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_dbu.h
new file mode 100644
index 000000000..7346fc056
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_dbu.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Debug Unit
+ * Based on AT91SAM9XE datasheet
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_DBU_H
+#define AT91_DBU_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_dbu {
+	u32	cr;	/* Control Register WO */
+	u32	mr;	/* Mode Register  RW */
+	u32	ier;	/* Interrupt Enable Register WO */
+	u32	idr;	/* Interrupt Disable Register WO */
+	u32	imr;	/* Interrupt Mask Register RO */
+	u32	sr;	/* Status Register RO */
+	u32	rhr;	/* Receive Holding Register RO */
+	u32	thr;	/* Transmit Holding Register WO */
+	u32	brgr;	/* Baud Rate Generator Register RW */
+	u32	res1[7];/* 0x0024 - 0x003C Reserved */
+	u32	cidr;	/* Chip ID Register RO */
+	u32	exid;	/* Chip ID Extension Register RO */
+	u32	fnr;	/* Force NTRST Register RW */
+} at91_dbu_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_DBU_CID_ARCH_MASK		0x0ff00000
+#define AT91_DBU_CID_ARCH_9xx		0x01900000
+#define AT91_DBU_CID_ARCH_9XExx	0x02900000
+
+#define AT91_DBU_CIDR_MASK		0x1f
+#define AT91_DBU_CIDR			0x40
+#define AT91_DBU_EXID			0x44
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_eefc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_eefc.h
new file mode 100644
index 000000000..7ffbaee27
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_eefc.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Enhanced Embedded Flash Controller
+ * Based on AT91SAM9XE datasheet
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_EEFC_H
+#define AT91_EEFC_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_eefc {
+	u32	fmr;	/* Flash Mode Register RW */
+	u32	fcr;	/* Flash Command Register WO */
+	u32	fsr;	/* Flash Status Register RO */
+	u32	frr;	/* Flash Result Register RO */
+} at91_eefc_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_EEFC_FMR_FWS_MASK	0x00000f00
+#define AT91_EEFC_FMR_FRDY_BIT	0x00000001
+
+#define AT91_EEFC_FCR_KEY		0x5a000000
+#define AT91_EEFC_FCR_FARG_MASK	0x00ffff00
+#define AT91_EEFC_FCR_FARG_SHIFT	8
+#define AT91_EEFC_FCR_FCMD_GETD	0x0
+#define AT91_EEFC_FCR_FCMD_WP		0x1
+#define AT91_EEFC_FCR_FCMD_WPL		0x2
+#define AT91_EEFC_FCR_FCMD_EWP		0x3
+#define AT91_EEFC_FCR_FCMD_EWPL	0x4
+#define AT91_EEFC_FCR_FCMD_EA		0x5
+#define AT91_EEFC_FCR_FCMD_SLB		0x8
+#define AT91_EEFC_FCR_FCMD_CLB		0x9
+#define AT91_EEFC_FCR_FCMD_GLB		0xA
+#define AT91_EEFC_FCR_FCMD_SGPB	0xB
+#define AT91_EEFC_FCR_FCMD_CGPB	0xC
+#define AT91_EEFC_FCR_FCMD_GGPB	0xD
+
+#define AT91_EEFC_FSR_FRDY	1
+#define AT91_EEFC_FSR_FCMDE	2
+#define AT91_EEFC_FSR_FLOCKE	4
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_emac.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_emac.h
new file mode 100644
index 000000000..a0d74ab66
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_emac.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC))
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_H
+#define AT91_H
+
+typedef struct at91_emac {
+	u32	 ctl;
+	u32	 cfg;
+	u32	 sr;
+	u32	 tar;
+	u32	 tcr;
+	u32	 tsr;
+	u32	 rbqp;
+	u32	 reserved0;
+	u32	 rsr;
+	u32	 isr;
+	u32	 ier;
+	u32	 idr;
+	u32	 imr;
+	u32	 man;
+	u32	 reserved1[2];
+	u32	 fra;
+	u32	 scol;
+	u32	 mocl;
+	u32	 ok;
+	u32	 seqe;
+	u32	 ale;
+	u32	 dte;
+	u32	 lcol;
+	u32	 ecol;
+	u32	 cse;
+	u32	 tue;
+	u32	 cde;
+	u32	 elr;
+	u32	 rjb;
+	u32	 usf;
+	u32	 sqee;
+	u32	 drfc;
+	u32	 reserved2[3];
+	u32	 hsh;
+	u32	 hsl;
+	u32	 sa1l;
+	u32	 sa1h;
+	u32	 sa2l;
+	u32	 sa2h;
+	u32	 sa3l;
+	u32	 sa3h;
+	u32	 sa4l;
+	u32	 sa4h;
+} at91_emac_t;
+
+#define AT91_EMAC_CTL_LB	0x0001
+#define AT91_EMAC_CTL_LBL	0x0002
+#define AT91_EMAC_CTL_RE	0x0004
+#define AT91_EMAC_CTL_TE	0x0008
+#define AT91_EMAC_CTL_MPE	0x0010
+#define AT91_EMAC_CTL_CSR	0x0020
+#define AT91_EMAC_CTL_ISR	0x0040
+#define AT91_EMAC_CTL_WES	0x0080
+#define AT91_EMAC_CTL_BP	0x1000
+
+#define AT91_EMAC_CFG_SPD	0x0001
+#define AT91_EMAC_CFG_FD	0x0002
+#define AT91_EMAC_CFG_BR	0x0004
+#define AT91_EMAC_CFG_CAF	0x0010
+#define AT91_EMAC_CFG_NBC	0x0020
+#define AT91_EMAC_CFG_MTI	0x0040
+#define AT91_EMAC_CFG_UNI	0x0080
+#define AT91_EMAC_CFG_BIG	0x0100
+#define AT91_EMAC_CFG_EAE	0x0200
+#define AT91_EMAC_CFG_CLK_MASK	0xFFFFF3FF
+#define AT91_EMAC_CFG_MCLK_8	0x0000
+#define AT91_EMAC_CFG_MCLK_16	0x0400
+#define AT91_EMAC_CFG_MCLK_32	0x0800
+#define AT91_EMAC_CFG_MCLK_64	0x0C00
+#define AT91_EMAC_CFG_RTY	0x1000
+#define AT91_EMAC_CFG_RMII	0x2000
+
+#define AT91_EMAC_SR_LINK	0x0001
+#define AT91_EMAC_SR_MDIO	0x0002
+#define AT91_EMAC_SR_IDLE	0x0004
+
+#define AT91_EMAC_TCR_LEN(x)	(x & 0x7FF)
+#define AT91_EMAC_TCR_NCRC	0x8000
+
+#define AT91_EMAC_TSR_OVR	0x0001
+#define AT91_EMAC_TSR_COL	0x0002
+#define AT91_EMAC_TSR_RLE	0x0004
+#define AT91_EMAC_TSR_TXIDLE	0x0008
+#define AT91_EMAC_TSR_BNQ	0x0010
+#define AT91_EMAC_TSR_COMP	0x0020
+#define AT91_EMAC_TSR_UND	0x0040
+
+#define AT91_EMAC_RSR_BNA	0x0001
+#define AT91_EMAC_RSR_REC	0x0002
+#define AT91_EMAC_RSR_OVR	0x0004
+
+/*  ISR, IER, IDR, IMR use the same bits */
+#define AT91_EMAC_IxR_DONE	0x0001
+#define AT91_EMAC_IxR_RCOM	0x0002
+#define AT91_EMAC_IxR_RBNA	0x0004
+#define AT91_EMAC_IxR_TOVR	0x0008
+#define AT91_EMAC_IxR_TUND	0x0010
+#define AT91_EMAC_IxR_RTRY	0x0020
+#define AT91_EMAC_IxR_TBRE	0x0040
+#define AT91_EMAC_IxR_TCOM	0x0080
+#define AT91_EMAC_IxR_TIDLE	0x0100
+#define AT91_EMAC_IxR_LINK	0x0200
+#define AT91_EMAC_IxR_ROVR	0x0400
+#define AT91_EMAC_IxR_HRESP	0x0800
+
+#define AT91_EMAC_MAN_DATA_MASK		0xFFFF
+#define AT91_EMAC_MAN_CODE_802_3	0x00020000
+#define AT91_EMAC_MAN_REGA(reg)		((reg & 0x1F) << 18)
+#define AT91_EMAC_MAN_PHYA(phy)		((phy & 0x1F) << 23)
+#define AT91_EMAC_MAN_RW_R		0x20000000
+#define AT91_EMAC_MAN_RW_W		0x10000000
+#define AT91_EMAC_MAN_HIGH		0x40000000
+#define AT91_EMAC_MAN_LOW		0x80000000
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_gpbr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_gpbr.h
new file mode 100644
index 000000000..e781481e8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_gpbr.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * General Purpose Backup Registers
+ * Based on AT91SAM9XE datasheet
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_GPBR_H
+#define AT91_GPBR_H
+
+/*
+ * The Atmel AT91SAM9 series has a small resource of 4 nonvolatile
+ * 32 Bit registers (buffered by the Vbu power).
+ *
+ * Please consider carefully before using this resource for tasks
+ * that do not really need nonvolatile registers. Maybe you can
+ * store information in EEPROM or FLASH instead.
+ *
+ * However, if you use a GPBR please document its use here and
+ * reference the define in your code!
+ *
+ * known typical uses of the GPBRs:
+ * GPBR[0]: offset for RTT timekeeping (u-boot, kernel)
+ * GPBR[1]: unused
+ * GPBR[2]: unused
+ * GPBR[3]: bootcount (u-boot)
+ */
+#define AT91_GPBR_INDEX_TIMEOFF 0
+#define AT91_GPBR_INDEX_BOOTCOUNT 3
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_gpbr {
+	u32 reg[4];
+} at91_gpbr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_matrix.h
new file mode 100644
index 000000000..2379dd40f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_matrix.h
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_MATRIX_H
+#define AT91_MATRIX_H
+
+#ifdef __ASSEMBLY__
+
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x11C)
+#elif defined(CONFIG_AT91SAM9261)
+#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x30)
+#elif defined(CONFIG_AT91SAM9263)
+#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x120)
+#elif defined(CONFIG_AT91SAM9G45)
+#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x128)
+#else
+#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
+#endif
+
+#define AT91_ASM_MATRIX_MCFG	ATMEL_BASE_MATRIX
+
+#else
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#define AT91_MATRIX_MASTERS	6
+#define AT91_MATRIX_SLAVES	5
+#elif defined(CONFIG_AT91SAM9261)
+#define AT91_MATRIX_MASTERS	1
+#define AT91_MATRIX_SLAVES	5
+#elif defined(CONFIG_AT91SAM9263)
+#define AT91_MATRIX_MASTERS	9
+#define AT91_MATRIX_SLAVES	7
+#elif defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MASTERS	11
+#define AT91_MATRIX_SLAVES	8
+#else
+#error CPU not supported. Please update at91_matrix.h
+#endif
+
+typedef struct at91_priority {
+	u32	a;
+	u32	b;
+} at91_priority_t;
+
+typedef struct at91_matrix {
+	u32		mcfg[AT91_MATRIX_MASTERS];
+#if defined(CONFIG_AT91SAM9261)
+	u32		scfg[AT91_MATRIX_SLAVES];
+	u32		res61_1[3];
+	u32		tcr;
+	u32		res61_2[2];
+	u32		csa;
+	u32		pucr;
+	u32		res61_3[114];
+#else
+	u32		reserve1[16 - AT91_MATRIX_MASTERS];
+	u32		scfg[AT91_MATRIX_SLAVES];
+	u32		reserve2[16 - AT91_MATRIX_SLAVES];
+	at91_priority_t	pr[AT91_MATRIX_SLAVES];
+	u32		reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
+	u32		mrcr;		/* 0x100 Master Remap Control */
+	u32		reserve4[3];
+#if	defined(CONFIG_AT91SAM9G45)
+	u32		ccr[52];	/* 0x110 - 0x1E0 Chip Configuration */
+	u32		womr;		/* 0x1E4 Write Protect Mode  */
+	u32		wpsr;		/* 0x1E8 Write Protect Status */
+	u32		resg45_1[10];
+#elif defined(CONFIG_AT91SAM9260)  || defined(CONFIG_AT91SAM9G20)
+	u32		res60_1[3];
+	u32		csa;
+	u32		res60_2[56];
+#elif defined(CONFIG_AT91SAM9263)
+	u32		res63_1;
+	u32		tcmr;
+	u32		res63_2[2];
+	u32		csa[2];
+	u32		res63_3[54];
+#else
+	u32		reserve5[60];
+#endif
+#endif
+} at91_matrix_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_CSA_DBPUC		0x00000100
+#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V	0x00000000
+#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V	0x00010000
+
+#define AT91_MATRIX_CSA_EBI_CS1A	0x00000002
+#define AT91_MATRIX_CSA_EBI_CS3A	0x00000008
+#define AT91_MATRIX_CSA_EBI_CS4A	0x00000010
+#define AT91_MATRIX_CSA_EBI_CS5A	0x00000020
+
+#define AT91_MATRIX_CSA_EBI1_CS2A	0x00000008
+
+#if defined CONFIG_AT91SAM9261
+/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define	AT91_MATRIX_MCFG_RCB0	(1 << 0)
+/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define	AT91_MATRIX_MCFG_RCB1	(1 << 1)
+#endif
+
+/* Undefined Length Burst Type */
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
+	defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MCFG_ULBT_INFINITE	0x00000000
+#define AT91_MATRIX_MCFG_ULBT_SINGLE	0x00000001
+#define AT91_MATRIX_MCFG_ULBT_FOUR	0x00000002
+#define AT91_MATRIX_MCFG_ULBT_EIGHT	0x00000003
+#define AT91_MATRIX_MCFG_ULBT_SIXTEEN	0x00000004
+#endif
+#if defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO	0x00000005
+#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR	0x00000006
+#define AT91_MATRIX_MCFG_ULBT_128	0x00000007
+#endif
+
+/* Default Master Type */
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE	0x00000000
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST	0x00010000
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	0x00020000
+
+/* Fixed Index of Default Master */
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
+#define	AT91_MATRIX_SCFG_FIXED_DEFMSTR(x)	((x & 0xf) << 18)
+#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
+#define	AT91_MATRIX_SCFG_FIXED_DEFMSTR(x)	((x & 7) << 18)
+#endif
+
+/* Maximum Number of Allowed Cycles for a Burst */
+#if defined(CONFIG_AT91SAM9G45)
+#define	AT91_MATRIX_SCFG_SLOT_CYCLE(x)	((x & 0x1ff) << 0)
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
+	defined(CONFIG_AT91SAM9263)
+#define	AT91_MATRIX_SCFG_SLOT_CYCLE(x)	((x & 0xff) << 0)
+#endif
+
+/* Arbitration Type */
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
+#define	AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN	0x00000000
+#define	AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	0x01000000
+#endif
+
+/* Master Remap Control Register */
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
+	defined(CONFIG_AT91SAM9G45)
+/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define	AT91_MATRIX_MRCR_RCB0	(1 << 0)
+/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define	AT91_MATRIX_MRCR_RCB1	(1 << 1)
+#endif
+#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
+#define	AT91_MATRIX_MRCR_RCB2	0x00000004
+#define	AT91_MATRIX_MRCR_RCB3	0x00000008
+#define	AT91_MATRIX_MRCR_RCB4	0x00000010
+#define	AT91_MATRIX_MRCR_RCB5	0x00000020
+#define	AT91_MATRIX_MRCR_RCB6	0x00000040
+#define	AT91_MATRIX_MRCR_RCB7	0x00000080
+#define	AT91_MATRIX_MRCR_RCB8	0x00000100
+#endif
+#if defined(CONFIG_AT91SAM9G45)
+#define	AT91_MATRIX_MRCR_RCB9	0x00000200
+#define	AT91_MATRIX_MRCR_RCB10	0x00000400
+#define	AT91_MATRIX_MRCR_RCB11	0x00000800
+#endif
+
+/* TCM Configuration Register */
+#if defined(CONFIG_AT91SAM9G45)
+/* Size of ITCM enabled memory block */
+#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
+#define	AT91_MATRIX_TCMR_ITCM_32	0x00000040
+/* Size of DTCM enabled memory block */
+#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
+#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
+#define	AT91_MATRIX_TCMR_DTCM_64	0x00000070
+/* Wait state TCM register */
+#define	AT91_MATRIX_TCMR_TCM_NO_WS	0x00000000
+#define	AT91_MATRIX_TCMR_TCM_ONE_WS	0x00000800
+#endif
+#if defined(CONFIG_AT91SAM9263)
+/* Size of ITCM enabled memory block */
+#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
+#define	AT91_MATRIX_TCMR_ITCM_16	0x00000005
+#define	AT91_MATRIX_TCMR_ITCM_32	0x00000006
+/* Size of DTCM enabled memory block */
+#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
+#define	AT91_MATRIX_TCMR_DTCM_16	0x00000050
+#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
+#endif
+#if defined(CONFIG_AT91SAM9261)
+/* Size of ITCM enabled memory block */
+#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
+#define	AT91_MATRIX_TCMR_ITCM_16	0x00000005
+#define	AT91_MATRIX_TCMR_ITCM_32	0x00000006
+#define	AT91_MATRIX_TCMR_ITCM_64	0x00000007
+/* Size of DTCM enabled memory block */
+#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
+#define	AT91_MATRIX_TCMR_DTCM_16	0x00000050
+#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
+#define	AT91_MATRIX_TCMR_DTCM_64	0x00000070
+#endif
+
+#if defined(CONFIG_AT91SAM9G45)
+/* Video Mode Configuration Register */
+#define	AT91C_MATRIX_VDEC_SEL_OFF	0x00000000
+#define	AT91C_MATRIX_VDEC_SEL_ON	0x00000001
+/* Write Protect Mode Register */
+#define	AT91_MATRIX_WPMR_WP_WPDIS	0x00000000
+#define	AT91_MATRIX_WPMR_WP_WPEN	0x00000001
+#define	AT91_MATRIX_WPMR_WPKEY		0xFFFFFF00	/* Write Protect KEY */
+/* Write Protect Status Register */
+#define	AT91_MATRIX_WPSR_NO_WPV		0x00000000
+#define	AT91_MATRIX_WPSR_WPV		0x00000001
+#define	AT91_MATRIX_WPSR_WPVSRC		0x00FFFF00	/* Write Protect Violation Source */
+#endif
+
+/* USB Pad Pull-Up Control Register */
+#if defined(CONFIG_AT91SAM9261)
+#define	AT91_MATRIX_USBPUCR_PUON	0x40000000
+#endif
+
+#define AT91_MATRIX_PRA_M0(x)	((x & 3) << 0)	/* Master 0 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M1(x)	((x & 3) << 4)	/* Master 1 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M2(x)	((x & 3) << 8)	/* Master 2 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M3(x)	((x & 3) << 12)	/* Master 3 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M4(x)	((x & 3) << 16)	/* Master 4 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M5(x)	((x & 3) << 20)	/* Master 5 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M6(x)	((x & 3) << 24)	/* Master 6 Priority Reg. A*/
+#define AT91_MATRIX_PRA_M7(x)	((x & 3) << 28)	/* Master 7 Priority Reg. A*/
+#define AT91_MATRIX_PRB_M8(x)	((x & 3) << 0)	/* Master 8 Priority Reg. B) */
+#define AT91_MATRIX_PRB_M9(x)	((x & 3) << 4)	/* Master 9 Priority Reg. B) */
+#define AT91_MATRIX_PRB_M10(x)	((x & 3) << 8)	/* Master 10 Priority Reg. B) */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_mc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_mc.h
new file mode 100644
index 000000000..2ace77931
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_mc.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_MC_H
+#define AT91_MC_H
+
+#define AT91_ASM_MC_EBI_CSA	(ATMEL_BASE_MC + 0x60)
+#define AT91_ASM_MC_EBI_CFG	(ATMEL_BASE_MC + 0x64)
+#define AT91_ASM_MC_SMC_CSR0	(ATMEL_BASE_MC + 0x70)
+#define AT91_ASM_MC_SDRAMC_MR	(ATMEL_BASE_MC + 0x90)
+#define AT91_ASM_MC_SDRAMC_TR	(ATMEL_BASE_MC + 0x94)
+#define AT91_ASM_MC_SDRAMC_CR	(ATMEL_BASE_MC + 0x98)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_ebi {
+	u32 	csa;		/* 0x00 Chip Select Assignment Register */
+	u32	cfgr;		/* 0x04 Configuration Register */
+	u32	reserved[2];
+} at91_ebi_t;
+
+#define AT91_EBI_CSA_CS0A	0x0001
+#define AT91_EBI_CSA_CS1A	0x0002
+
+#define AT91_EBI_CSA_CS3A	0x0008
+#define AT91_EBI_CSA_CS4A	0x0010
+
+typedef struct at91_sdramc {
+	u32	mr; 	/* 0x00 SDRAMC Mode Register */
+	u32	tr; 	/* 0x04 SDRAMC Refresh Timer Register */
+	u32	cr; 	/* 0x08 SDRAMC Configuration Register */
+	u32	ssr; 	/* 0x0C SDRAMC Self Refresh Register */
+	u32	lpr; 	/* 0x10 SDRAMC Low Power Register */
+	u32	ier; 	/* 0x14 SDRAMC Interrupt Enable Register */
+	u32	idr; 	/* 0x18 SDRAMC Interrupt Disable Register */
+	u32	imr; 	/* 0x1C SDRAMC Interrupt Mask Register */
+	u32	icr; 	/* 0x20 SDRAMC Interrupt Status Register */
+	u32	reserved[3];
+} at91_sdramc_t;
+
+typedef struct at91_smc {
+	u32	csr[8]; 	/* 0x00 SDRAMC Mode Register */
+} at91_smc_t;
+
+#define AT91_SMC_CSR_RWHOLD(x)		((x & 0x7) << 28)
+#define AT91_SMC_CSR_RWSETUP(x)		((x & 0x7) << 24)
+#define AT91_SMC_CSR_ACSS_STANDARD	0x00000000
+#define AT91_SMC_CSR_ACSS_1CYCLE	0x00010000
+#define AT91_SMC_CSR_ACSS_2CYCLE	0x00020000
+#define AT91_SMC_CSR_ACSS_3CYCLE	0x00030000
+#define AT91_SMC_CSR_DRP		0x00008000
+#define AT91_SMC_CSR_DBW_8		0x00004000
+#define AT91_SMC_CSR_DBW_16		0x00002000
+#define AT91_SMC_CSR_BAT_8		0x00000000
+#define AT91_SMC_CSR_BAT_16		0x00001000
+#define AT91_SMC_CSR_TDF(x)		((x & 0xF) << 8)
+#define AT91_SMC_CSR_WSEN		0x00000080
+#define AT91_SMC_CSR_NWS(x)		(x & 0x7F)
+
+typedef struct at91_bfc {
+	u32	mr; 	/* 0x00 SDRAMC Mode Register */
+} at91_bfc_t;
+
+typedef struct at91_mc {
+	u32		rcr;		/* 0x00 MC Remap Control Register */
+	u32		asr;		/* 0x04 MC Abort Status Register */
+	u32		aasr;		/* 0x08 MC Abort Address Status Reg */
+	u32		mpr;		/* 0x0C MC Master Priority Register */
+	u32		reserved1[20];	/* 0x10-0x5C */
+	at91_ebi_t	ebi;		/* 0x60	- 0x6C EBI */
+	at91_smc_t	smc;		/* 0x70 - 0x8C SMC User Interface */
+	at91_sdramc_t	sdramc;		/* 0x90 - 0xBC SDRAMC User Interface */
+	at91_bfc_t	bfc;		/* 0xC0 BFC User Interface */
+	u32		reserved2[15];
+} at91_mc_t;
+
+#endif
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pdc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pdc.h
new file mode 100644
index 000000000..832ebb51c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pdc.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_PDC_H
+#define AT91_PDC_H
+
+typedef struct at91_pdc {
+	u32	rpr;		/* 0x100 Receive Pointer Register */
+	u32	rcr;		/* 0x104 Receive Counter Register */
+	u32	tpr;		/* 0x108 Transmit Pointer Register */
+	u32	tcr;		/* 0x10C Transmit Counter Register */
+	u32	pnpr;		/* 0x110 Receive Next Pointer Register */
+	u32	pncr;		/* 0x114 Receive Next Counter Register */
+	u32	tnpr;		/* 0x118 Transmit Next Pointer Register */
+	u32	tncr;		/* 0x11C Transmit Next Counter Register */
+	u32	ptcr;		/* 0x120 Transfer Control Register */
+	u32	ptsr;		/* 0x124 Transfer Status Register */
+} at91_pdc_t;
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pio.h
new file mode 100644
index 000000000..50464ffe8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -0,0 +1,154 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * Parallel I/O Controller (PIO) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_PIO_H
+#define AT91_PIO_H
+
+
+#define AT91_ASM_PIO_RANGE	0x200
+#define AT91_ASM_PIOC_ASR	\
+	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
+#define AT91_ASM_PIOC_BSR	\
+	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
+#define AT91_ASM_PIOC_PDR	\
+	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
+#define AT91_ASM_PIOC_PUDR	\
+	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
+
+#define AT91_ASM_PIOD_PDR	\
+	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
+#define AT91_ASM_PIOD_PUDR	\
+	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
+#define AT91_ASM_PIOD_ASR	\
+	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_port {
+	u32	per;		/* 0x00 PIO Enable Register */
+	u32	pdr;		/* 0x04 PIO Disable Register */
+	u32	psr;		/* 0x08 PIO Status Register */
+	u32	reserved0;
+	u32	oer;		/* 0x10 Output Enable Register */
+	u32	odr;		/* 0x14 Output Disable Registerr */
+	u32	osr;		/* 0x18 Output Status Register */
+	u32	reserved1;
+	u32	ifer;		/* 0x20 Input Filter Enable Register */
+	u32	ifdr;		/* 0x24 Input Filter Disable Register */
+	u32	ifsr;		/* 0x28 Input Filter Status Register */
+	u32	reserved2;
+	u32	sodr;		/* 0x30 Set Output Data Register */
+	u32	codr;		/* 0x34 Clear Output Data Register */
+	u32	odsr;		/* 0x38 Output Data Status Register */
+	u32	pdsr;		/* 0x3C Pin Data Status Register */
+	u32	ier;		/* 0x40 Interrupt Enable Register */
+	u32	idr;		/* 0x44 Interrupt Disable Register */
+	u32	imr;		/* 0x48 Interrupt Mask Register */
+	u32	isr;		/* 0x4C Interrupt Status Register */
+	u32	mder;		/* 0x50 Multi-driver Enable Register */
+	u32	mddr;		/* 0x54 Multi-driver Disable Register */
+	u32	mdsr;		/* 0x58 Multi-driver Status Register */
+	u32	reserved3;
+	u32	pudr;		/* 0x60 Pull-up Disable Register */
+	u32	puer;		/* 0x64 Pull-up Enable Register */
+	u32	pusr;		/* 0x68 Pad Pull-up Status Register */
+	u32	reserved4;
+#if defined(CPU_HAS_PIO3)
+	u32	abcdsr1;	/* 0x70 Peripheral ABCD Select Register 1 */
+	u32	abcdsr2;	/* 0x74 Peripheral ABCD Select Register 2 */
+	u32	reserved5[2];
+	u32	ifscdr;		/* 0x80 Input Filter SCLK Disable Register */
+	u32	ifscer;		/* 0x84 Input Filter SCLK Enable Register */
+	u32	ifscsr;		/* 0x88 Input Filter SCLK Status Register */
+	u32	scdr;		/* 0x8C SCLK Divider Debouncing Register */
+	u32	ppddr;		/* 0x90 Pad Pull-down Disable Register */
+	u32	ppder;		/* 0x94 Pad Pull-down Enable Register */
+	u32	ppdsr;		/* 0x98 Pad Pull-down Status Register */
+	u32	reserved6;	/*  */
+#else
+	u32	asr;		/* 0x70 Select A Register */
+	u32	bsr;		/* 0x74 Select B Register */
+	u32	absr;		/* 0x78 AB Select Status Register */
+	u32	reserved5[9];	/*  */
+#endif
+	u32	ower;		/* 0xA0 Output Write Enable Register */
+	u32	owdr;		/* 0xA4 Output Write Disable Register */
+	u32	owsr;		/* OxA8 Output Write Status Register */
+#if defined(CPU_HAS_PIO3)
+	u32	reserved7;	/*  */
+	u32	aimer;		/* 0xB0 Additional INT Modes Enable Register */
+	u32	aimdr;		/* 0xB4 Additional INT Modes Disable Register */
+	u32	aimmr;		/* 0xB8 Additional INT Modes Mask Register */
+	u32	reserved8;	/* */
+	u32	esr;		/* 0xC0 Edge Select Register */
+	u32	lsr;		/* 0xC4 Level Select Register */
+	u32	elsr;		/* 0xC8 Edge/Level Status Register */
+	u32	reserved9;	/* 0xCC */
+	u32	fellsr;		/* 0xD0 Falling /Low Level Select Register */
+	u32	rehlsr;		/* 0xD4 Rising /High Level Select Register */
+	u32	frlhsr;		/* 0xD8 Fall/Rise - Low/High Status Register */
+	u32	reserved10;	/* */
+	u32	locksr;		/* 0xE0 Lock Status */
+	u32	wpmr;		/* 0xE4 Write Protect Mode Register */
+	u32	wpsr;		/* 0xE8 Write Protect Status Register */
+	u32	reserved11[5];	/* */
+	u32	schmitt;	/* 0x100 Schmitt Trigger Register */
+	u32	reserved12[63];
+#else
+	u32	reserved6[85];
+#endif
+} at91_port_t;
+
+typedef union at91_pio {
+	struct {
+		at91_port_t	pioa;
+		at91_port_t	piob;
+		at91_port_t	pioc;
+	#if (ATMEL_PIO_PORTS > 3)
+		at91_port_t	piod;
+	#endif
+	#if (ATMEL_PIO_PORTS > 4)
+		at91_port_t	pioe;
+	#endif
+	} ;
+	at91_port_t port[ATMEL_PIO_PORTS];
+} at91_pio_t;
+
+#ifdef CONFIG_AT91_GPIO
+int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+#if defined(CPU_HAS_PIO3)
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
+#endif
+int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_output(unsigned port, unsigned pin, int value);
+int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_value(unsigned port, unsigned pin, int value);
+int at91_get_pio_value(unsigned port, unsigned pin);
+#endif
+#endif
+
+#define	AT91_PIO_PORTA		0x0
+#define	AT91_PIO_PORTB		0x1
+#define	AT91_PIO_PORTC		0x2
+#define	AT91_PIO_PORTD		0x3
+#define	AT91_PIO_PORTE		0x4
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pit.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pit.h
new file mode 100644
index 000000000..56724f15e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pit.h
@@ -0,0 +1,28 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h]
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Periodic Interval Timer (PIT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_PIT_H
+#define AT91_PIT_H
+
+typedef struct at91_pit {
+	u32	mr;	/* 0x00 Mode Register */
+	u32	sr;	/* 0x04 Status Register */
+	u32	pivr;	/* 0x08 Periodic Interval Value Register */
+	u32	piir;	/* 0x0C Periodic Interval Image Register */
+} at91_pit_t;
+
+#define		AT91_PIT_MR_IEN		0x02000000
+#define		AT91_PIT_MR_EN		0x01000000
+#define		AT91_PIT_MR_PIV_MASK(x)	(x & 0x000fffff)
+#define		AT91_PIT_MR_PIV(x)	(x & AT91_PIT_MR_PIV_MASK)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pmc.h
new file mode 100644
index 000000000..453560843
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -0,0 +1,230 @@
+/*
+ * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * Power Management Controller (PMC) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_PMC_H
+#define AT91_PMC_H
+
+#ifdef __ASSEMBLY__
+
+#define	AT91_ASM_PMC_MOR	(ATMEL_BASE_PMC + 0x20)
+#define	AT91_ASM_PMC_PLLAR	(ATMEL_BASE_PMC + 0x28)
+#define	AT91_ASM_PMC_PLLBR	(ATMEL_BASE_PMC + 0x2c)
+#define AT91_ASM_PMC_MCKR	(ATMEL_BASE_PMC + 0x30)
+#define AT91_ASM_PMC_SR		(ATMEL_BASE_PMC + 0x68)
+
+#else
+
+#include <asm/types.h>
+
+typedef struct at91_pmc {
+	u32	scer;		/* 0x00 System Clock Enable Register */
+	u32	scdr;		/* 0x04 System Clock Disable Register */
+	u32	scsr;		/* 0x08 System Clock Status Register */
+	u32	reserved0;
+	u32	pcer;		/* 0x10 Peripheral Clock Enable Register */
+	u32	pcdr;		/* 0x14 Peripheral Clock Disable Register */
+	u32	pcsr;		/* 0x18 Peripheral Clock Status Register */
+	u32	uckr;		/* 0x1C UTMI Clock Register */
+	u32	mor;		/* 0x20 Main Oscilator Register */
+	u32	mcfr;		/* 0x24 Main Clock Frequency Register */
+	u32	pllar;		/* 0x28 PLL A Register */
+	u32	pllbr;		/* 0x2C PLL B Register */
+	u32	mckr;		/* 0x30 Master Clock Register */
+	u32	reserved1;
+	u32	usb;		/* 0x38 USB Clock Register */
+	u32	reserved2;
+	u32	pck[4];		/* 0x40 Programmable Clock Register 0 - 3 */
+	u32	reserved3[4];
+	u32	ier;		/* 0x60 Interrupt Enable Register */
+	u32	idr;		/* 0x64 Interrupt Disable Register */
+	u32	sr;		/* 0x68 Status Register */
+	u32	imr;		/* 0x6C Interrupt Mask Register */
+	u32	reserved4[4];
+	u32	pllicpr;	/* 0x80 Change Pump Current Register (SAM9) */
+	u32	reserved5[21];
+	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
+	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
+#ifdef CONFIG_SAMA5D3
+	u32	reserved6[8];
+	u32	pcer1;		/* 0x100 Periperial Clock Enable Register 1 */
+	u32	pcdr1;		/* 0x104 Periperial Clock Disable Register 1 */
+	u32	pcsr1;		/* 0x108 Periperial Clock Status Register 1 */
+	u32	pcr;		/* 0x10c Periperial Control Register */
+	u32	ocr;		/* 0x110 Oscillator Calibration Register */
+#else
+	u32	reserved8[5];
+#endif
+} at91_pmc_t;
+
+#endif	/* end not assembly */
+
+#define AT91_PMC_MOR_MOSCEN		0x01
+#define AT91_PMC_MOR_OSCBYPASS		0x02
+#define AT91_PMC_MOR_OSCOUNT(x)		((x & 0xff) << 8)
+
+#define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
+#define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
+#define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7F) << 18)
+#else
+#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)
+#endif
+#define AT91_PMC_PLLAR_29		0x20000000
+#define AT91_PMC_PLLBR_USBDIV_1		0x00000000
+#define AT91_PMC_PLLBR_USBDIV_2		0x10000000
+#define AT91_PMC_PLLBR_USBDIV_4		0x20000000
+
+#define AT91_PMC_MCFR_MAINRDY		0x00010000
+#define AT91_PMC_MCFR_MAINF_MASK	0x0000FFFF
+
+#define AT91_PMC_MCKR_CSS_SLOW		0x00000000
+#define AT91_PMC_MCKR_CSS_MAIN		0x00000001
+#define AT91_PMC_MCKR_CSS_PLLA		0x00000002
+#define AT91_PMC_MCKR_CSS_PLLB		0x00000003
+#define AT91_PMC_MCKR_CSS_MASK		0x00000003
+
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_MCKR_PRES_1		0x00000000
+#define AT91_PMC_MCKR_PRES_2		0x00000010
+#define AT91_PMC_MCKR_PRES_4		0x00000020
+#define AT91_PMC_MCKR_PRES_8		0x00000030
+#define AT91_PMC_MCKR_PRES_16		0x00000040
+#define AT91_PMC_MCKR_PRES_32		0x00000050
+#define AT91_PMC_MCKR_PRES_64		0x00000060
+#define AT91_PMC_MCKR_PRES_MASK		0x00000070
+#else
+#define AT91_PMC_MCKR_PRES_1		0x00000000
+#define AT91_PMC_MCKR_PRES_2		0x00000004
+#define AT91_PMC_MCKR_PRES_4		0x00000008
+#define AT91_PMC_MCKR_PRES_8		0x0000000C
+#define AT91_PMC_MCKR_PRES_16		0x00000010
+#define AT91_PMC_MCKR_PRES_32		0x00000014
+#define AT91_PMC_MCKR_PRES_64		0x00000018
+#define AT91_PMC_MCKR_PRES_MASK		0x0000001C
+#endif
+
+#ifdef CONFIG_AT91RM9200
+#define AT91_PMC_MCKR_MDIV_1		0x00000000
+#define AT91_PMC_MCKR_MDIV_2		0x00000100
+#define AT91_PMC_MCKR_MDIV_3		0x00000200
+#define AT91_PMC_MCKR_MDIV_4		0x00000300
+#define AT91_PMC_MCKR_MDIV_MASK		0x00000300
+#else
+#define AT91_PMC_MCKR_MDIV_1		0x00000000
+#define AT91_PMC_MCKR_MDIV_2		0x00000100
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_MCKR_MDIV_3		0x00000300
+#endif
+#define AT91_PMC_MCKR_MDIV_4		0x00000200
+#define AT91_PMC_MCKR_MDIV_MASK		0x00000300
+#endif
+
+#define AT91_PMC_MCKR_PLLADIV_1		0x00000000
+#define AT91_PMC_MCKR_PLLADIV_2		0x00001000
+
+#define AT91_PMC_IXR_MOSCS		0x00000001
+#define AT91_PMC_IXR_LOCKA		0x00000002
+#define AT91_PMC_IXR_LOCKB		0x00000004
+#define AT91_PMC_IXR_MCKRDY		0x00000008
+#define AT91_PMC_IXR_LOCKU		0x00000040
+#define AT91_PMC_IXR_PCKRDY0		0x00000100
+#define AT91_PMC_IXR_PCKRDY1		0x00000200
+#define AT91_PMC_IXR_PCKRDY2		0x00000400
+#define AT91_PMC_IXR_PCKRDY3		0x00000800
+
+#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
+#define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
+#define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
+#define		AT91CAP9_PMC_DDR	(1 <<  2)		/* DDR Clock [AT91CAP9 revC only] */
+#define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
+#define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
+#define		AT91CAP9_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91CAP9 only] */
+#define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */
+#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
+#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
+#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
+#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
+#define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
+#define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
+
+#define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
+#define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
+#define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
+#define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI PLL Start-up Time */
+
+#define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
+#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x, CAP9] */
+#define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
+
+#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
+#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
+
+#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
+#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
+#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
+#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
+#define		AT91_PMC_USBDIV		(3     << 28)		/* USB Divisor (PLLB only) */
+#define			AT91_PMC_USBDIV_1		(0 << 28)
+#define			AT91_PMC_USBDIV_2		(1 << 28)
+#define			AT91_PMC_USBDIV_4		(2 << 28)
+#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
+#define		AT91_PMC_PLLA_WR_ERRATA	(1     << 29)		/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
+
+#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
+#define			AT91_PMC_CSS_SLOW		(0 << 0)
+#define			AT91_PMC_CSS_MAIN		(1 << 0)
+#define			AT91_PMC_CSS_PLLA		(2 << 0)
+#define			AT91_PMC_CSS_PLLB		(3 << 0)
+#define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */
+#define			AT91_PMC_PRES_1			(0 << 2)
+#define			AT91_PMC_PRES_2			(1 << 2)
+#define			AT91_PMC_PRES_4			(2 << 2)
+#define			AT91_PMC_PRES_8			(3 << 2)
+#define			AT91_PMC_PRES_16		(4 << 2)
+#define			AT91_PMC_PRES_32		(5 << 2)
+#define			AT91_PMC_PRES_64		(6 << 2)
+#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
+#define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
+#define			AT91RM9200_PMC_MDIV_2		(1 << 8)
+#define			AT91RM9200_PMC_MDIV_3		(2 << 8)
+#define			AT91RM9200_PMC_MDIV_4		(3 << 8)
+#define			AT91SAM9_PMC_MDIV_1		(0 << 8)	/* [SAM9,CAP9 only] */
+#define			AT91SAM9_PMC_MDIV_2		(1 << 8)
+#define			AT91SAM9_PMC_MDIV_4		(2 << 8)
+#define			AT91SAM9_PMC_MDIV_3		(3 << 8)	/* [some SAM9 only] */
+#define			AT91SAM9_PMC_MDIV_6		(3 << 8)
+#define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
+#define			AT91_PMC_PDIV_1			(0 << 12)
+#define			AT91_PMC_PDIV_2			(1 << 12)
+
+#define		AT91_PMC_USBS_USB_PLLA		(0x0)		/* USB Clock Input is PLLA */
+#define		AT91_PMC_USBS_USB_UPLL		(0x1)		/* USB Clock Input is UPLL */
+#define		AT91_PMC_USBS_USB_PLLB		(0x1)		/* USB Clock Input is PLLB, AT91SAM9N12 only */
+#define		AT91_PMC_USB_DIV_2		(0x1 <<  8)	/* USB Clock divided by 2 */
+#define		AT91_PMC_USBDIV_8		(0x7 <<  8)	/* USB Clock divided by 8 */
+#define		AT91_PMC_USBDIV_10		(0x9 <<  8)	/* USB Clock divided by 10 */
+
+#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
+#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
+#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
+#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
+#define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock [AT91CAP9 only] */
+#define		AT91_PMC_OSCSEL		(1 <<  7)		/* Slow Clock Oscillator [AT91CAP9 revC only] */
+#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
+#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
+#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
+#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
+
+#define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rstc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rstc.h
new file mode 100644
index 000000000..a9423428e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rstc.h
@@ -0,0 +1,48 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h]
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Reset Controller (RSTC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_RSTC_H
+#define AT91_RSTC_H
+
+#define AT91_ASM_RSTC_MR	(ATMEL_BASE_RSTC + 0x08)
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_rstc {
+	u32	cr;	/* Reset Controller Control Register */
+	u32	sr;	/* Reset Controller Status Register */
+	u32	mr;	/* Reset Controller Mode Register */
+} at91_rstc_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_RSTC_KEY		0xA5000000
+
+#define AT91_RSTC_CR_PROCRST	0x00000001
+#define AT91_RSTC_CR_PERRST	0x00000004
+#define AT91_RSTC_CR_EXTRST	0x00000008
+
+#define AT91_RSTC_MR_URSTEN	0x00000001
+#define AT91_RSTC_MR_URSTIEN	0x00000010
+#define AT91_RSTC_MR_ERSTL(x)	((x & 0xf) << 8)
+#define AT91_RSTC_MR_ERSTL_MASK	0x0000FF00
+
+#define AT91_RSTC_SR_NRSTL	0x00010000
+
+#define AT91_RSTC_RSTTYP		(7 << 8)	/* Reset Type */
+#define AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
+#define AT91_RSTC_RSTTYP_WAKEUP	(1 << 8)
+#define AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
+#define AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
+#define AT91_RSTC_RSTTYP_USER		(4 << 8)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rtt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rtt.h
new file mode 100644
index 000000000..fe7619a93
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_rtt.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Real-time Timer
+ * Based on AT91SAM9XE datasheet
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_RTT_H
+#define AT91_RTT_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_rtt {
+	u32	mr;	/* Mode Register   RW 0x00008000 */
+	u32	ar;	/* Alarm Register  RW 0xFFFFFFFF */
+	u32	vr;	/* Value Register  RO 0x00000000 */
+	u32	sr;	/* Status Register RO 0x00000000 */
+} at91_rtt_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_RTT_MR_RTPRES	0x0000ffff
+#define AT91_RTT_MR_ALMIEN	0x00010000
+#define AT91_RTT_RTTINCIEN	0x00020000
+#define AT91_RTT_RTTRST	0x00040000
+
+#define AT91_RTT_SR_ALMS	0x00000001
+#define AT91_RTT_SR_RTTINC	0x00000002
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_shdwn.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_shdwn.h
new file mode 100644
index 000000000..18d9ea690
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_shdwn.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ *
+ * Shutdown Controller
+ * Based on AT91SAM9XE datasheet
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_SHDWN_H
+#define AT91_SHDWN_H
+
+#ifndef __ASSEMBLY__
+
+struct at91_shdwn {
+	u32	cr;	/* Control Rer.    WO */
+	u32	mr;	/* Mode Register   RW 0x00000003 */
+	u32	sr;	/* Status Register RO 0x00000000 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_SHDW_CR_KEY	0xa5000000
+#define AT91_SHDW_CR_SHDW	0x00000001
+
+#define AT91_SHDW_MR_RTTWKEN	0x00010000
+#define AT91_SHDW_MR_CPTWK0	0x000000f0
+#define AT91_SHDW_MR_WKMODE0H2L	0x00000002
+#define AT91_SHDW_MR_WKMODE0L2H	0x00000001
+
+#define AT91_SHDW_SR_RTTWK	0x00010000
+#define AT91_SHDW_SR_WAKEUP0	0x00000001
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_spi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_spi.h
new file mode 100644
index 000000000..b18665b62
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_spi.h
@@ -0,0 +1,123 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Serial Peripheral Interface (SPI) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_SPI_H
+#define AT91_SPI_H
+
+#include <asm/arch/at91_pdc.h>
+
+typedef struct at91_spi {
+	u32		cr;		/* 0x00 Control Register */
+	u32		mr;		/* 0x04 Mode Register */
+	u32		rdr;		/* 0x08 Receive Data Register */
+	u32		tdr;		/* 0x0C Transmit Data Register */
+	u32		sr;		/* 0x10 Status Register */
+	u32		ier;		/* 0x14 Interrupt Enable Register */
+	u32		idr;		/* 0x18 Interrupt Disable Register */
+	u32		imr;		/* 0x1C Interrupt Mask Register */
+	u32		reserve1[4];
+	u32		csr[4];		/* 0x30 Chip Select Register 0-3 */
+	u32		reserve2[48];
+	at91_pdc_t	pdc;
+} at91_spi_t;
+
+#ifdef CONFIG_ATMEL_LEGACY
+
+#define AT91_SPI_CR			0x00		/* Control Register */
+#define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
+#define		AT91_SPI_SPIDIS		(1 <<  1)		/* SPI Disable */
+#define		AT91_SPI_SWRST		(1 <<  7)		/* SPI Software Reset */
+#define		AT91_SPI_LASTXFER	(1 << 24)		/* Last Transfer [SAM9261 only] */
+
+#define AT91_SPI_MR			0x04		/* Mode Register */
+#define		AT91_SPI_MSTR		(1    <<  0)		/* Master/Slave Mode */
+#define		AT91_SPI_PS		(1    <<  1)		/* Peripheral Select */
+#define			AT91_SPI_PS_FIXED	(0 << 1)
+#define			AT91_SPI_PS_VARIABLE	(1 << 1)
+#define		AT91_SPI_PCSDEC		(1    <<  2)		/* Chip Select Decode */
+#define		AT91_SPI_DIV32		(1    <<  3)		/* Clock Selection [AT91RM9200 only] */
+#define		AT91_SPI_MODFDIS	(1    <<  4)		/* Mode Fault Detection */
+#define		AT91_SPI_LLB		(1    <<  7)		/* Local Loopback Enable */
+#define		AT91_SPI_PCS		(0xf  << 16)		/* Peripheral Chip Select */
+#define		AT91_SPI_DLYBCS		(0xff << 24)		/* Delay Between Chip Selects */
+
+#define AT91_SPI_RDR		0x08			/* Receive Data Register */
+#define		AT91_SPI_RD		(0xffff <<  0)		/* Receive Data */
+#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
+
+#define AT91_SPI_TDR		0x0c			/* Transmit Data Register */
+#define		AT91_SPI_TD		(0xffff <<  0)		/* Transmit Data */
+#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
+#define		AT91_SPI_LASTXFER	(1	<< 24)		/* Last Transfer [SAM9261 only] */
+
+#define AT91_SPI_SR		0x10			/* Status Register */
+#define		AT91_SPI_RDRF		(1 <<  0)		/* Receive Data Register Full */
+#define		AT91_SPI_TDRE		(1 <<  1)		/* Transmit Data Register Full */
+#define		AT91_SPI_MODF		(1 <<  2)		/* Mode Fault Error */
+#define		AT91_SPI_OVRES		(1 <<  3)		/* Overrun Error Status */
+#define		AT91_SPI_ENDRX		(1 <<  4)		/* End of RX buffer */
+#define		AT91_SPI_ENDTX		(1 <<  5)		/* End of TX buffer */
+#define		AT91_SPI_RXBUFF		(1 <<  6)		/* RX Buffer Full */
+#define		AT91_SPI_TXBUFE		(1 <<  7)		/* TX Buffer Empty */
+#define		AT91_SPI_NSSR		(1 <<  8)		/* NSS Rising [SAM9261 only] */
+#define		AT91_SPI_TXEMPTY	(1 <<  9)		/* Transmission Register Empty [SAM9261 only] */
+#define		AT91_SPI_SPIENS		(1 << 16)		/* SPI Enable Status */
+
+#define AT91_SPI_IER		0x14			/* Interrupt Enable Register */
+#define AT91_SPI_IDR		0x18			/* Interrupt Disable Register */
+#define AT91_SPI_IMR		0x1c			/* Interrupt Mask Register */
+
+#define AT91_SPI_CSR(n)		(0x30 + ((n) * 4))	/* Chip Select Registers 0-3 */
+#define		AT91_SPI_CPOL		(1    <<  0)		/* Clock Polarity */
+#define		AT91_SPI_NCPHA		(1    <<  1)		/* Clock Phase */
+#define		AT91_SPI_CSAAT		(1    <<  3)		/* Chip Select Active After Transfer [SAM9261 only] */
+#define		AT91_SPI_BITS		(0xf  <<  4)		/* Bits Per Transfer */
+#define			AT91_SPI_BITS_8		(0 << 4)
+#define			AT91_SPI_BITS_9		(1 << 4)
+#define			AT91_SPI_BITS_10	(2 << 4)
+#define			AT91_SPI_BITS_11	(3 << 4)
+#define			AT91_SPI_BITS_12	(4 << 4)
+#define			AT91_SPI_BITS_13	(5 << 4)
+#define			AT91_SPI_BITS_14	(6 << 4)
+#define			AT91_SPI_BITS_15	(7 << 4)
+#define			AT91_SPI_BITS_16	(8 << 4)
+#define		AT91_SPI_SCBR		(0xff <<  8)		/* Serial Clock Baud Rate */
+#define		AT91_SPI_DLYBS		(0xff << 16)		/* Delay before SPCK */
+#define		AT91_SPI_DLYBCT		(0xff << 24)		/* Delay between Consecutive Transfers */
+
+#define AT91_SPI_RPR		0x0100			/* Receive Pointer Register */
+
+#define AT91_SPI_RCR		0x0104			/* Receive Counter Register */
+
+#define AT91_SPI_TPR		0x0108			/* Transmit Pointer Register */
+
+#define AT91_SPI_TCR		0x010c			/* Transmit Counter Register */
+
+#define AT91_SPI_RNPR		0x0110			/* Receive Next Pointer Register */
+
+#define AT91_SPI_RNCR		0x0114			/* Receive Next Counter Register */
+
+#define AT91_SPI_TNPR		0x0118			/* Transmit Next Pointer Register */
+
+#define AT91_SPI_TNCR		0x011c			/* Transmit Next Counter Register */
+
+#define AT91_SPI_PTCR		0x0120			/* PDC Transfer Control Register */
+#define		AT91_SPI_RXTEN		(0x1 << 0)		/* Receiver Transfer Enable */
+#define		AT91_SPI_RXTDIS		(0x1 << 1)		/* Receiver Transfer Disable */
+#define		AT91_SPI_TXTEN		(0x1 << 8)		/* Transmitter Transfer Enable */
+#define		AT91_SPI_TXTDIS		(0x1 << 9)		/* Transmitter Transfer Disable */
+
+#define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
+
+#endif /* CONFIG_ATMEL_LEGACY */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_st.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_st.h
new file mode 100644
index 000000000..b1ee1472e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_st.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_ST_H
+#define AT91_ST_H
+
+typedef struct at91_st {
+
+	u32	cr;
+	u32	pimr;
+	u32	wdmr;
+	u32	rtmr;
+	u32	sr;
+	u32	ier;
+	u32	idr;
+	u32	imr;
+	u32	rtar;
+	u32	crtr;
+} at91_st_t ;
+
+#define AT91_ST_CR_WDRST	1
+
+#define AT91_ST_WDMR_WDV(x)	(x & 0xFFFF)
+#define AT91_ST_WDMR_RSTEN	0x00010000
+#define AT91_ST_WDMR_EXTEN 	0x00020000
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_tc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_tc.h
new file mode 100644
index 000000000..de0e26656
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_tc.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_TC_H
+#define AT91_TC_H
+
+typedef struct at91_tcc {
+	u32		ccr;	/* 0x00 Channel Control Register */
+	u32		cmr;	/* 0x04 Channel Mode Register */
+	u32		reserved1[2];
+	u32		cv;	/* 0x10 Counter Value */
+	u32		ra;	/* 0x14 Register A */
+	u32		rb;	/* 0x18 Register B */
+	u32		rc;	/* 0x1C Register C */
+	u32		sr;	/* 0x20 Status Register */
+	u32		ier;	/* 0x24 Interrupt Enable Register */
+	u32		idr;	/* 0x28 Interrupt Disable Register */
+	u32		imr;	/* 0x2C Interrupt Mask Register */
+	u32		reserved3[4];
+} at91_tcc_t;
+
+#define AT91_TC_CCR_CLKEN		0x00000001
+#define AT91_TC_CCR_CLKDIS		0x00000002
+#define AT91_TC_CCR_SWTRG		0x00000004
+
+#define AT91_TC_CMR_CPCTRG		0x00004000
+
+#define AT91_TC_CMR_TCCLKS_CLOCK1	0x00000000
+#define AT91_TC_CMR_TCCLKS_CLOCK2	0x00000001
+#define AT91_TC_CMR_TCCLKS_CLOCK3	0x00000002
+#define AT91_TC_CMR_TCCLKS_CLOCK4	0x00000003
+#define AT91_TC_CMR_TCCLKS_CLOCK5	0x00000004
+#define AT91_TC_CMR_TCCLKS_XC0		0x00000005
+#define AT91_TC_CMR_TCCLKS_XC1		0x00000006
+#define AT91_TC_CMR_TCCLKS_XC2		0x00000007
+
+typedef struct at91_tc {
+	at91_tcc_t	tc[3];	/* 0x00 TC Channel 0-2 */
+	u32		bcr;	/* 0xC0 TC Block Control Register */
+	u32		bmr;	/* 0xC4 TC Block Mode Register */
+} at91_tc_t;
+
+#define AT91_TC_BMR_TC0XC0S_TCLK0	0x00000000
+#define AT91_TC_BMR_TC0XC0S_NONE	0x00000001
+#define AT91_TC_BMR_TC0XC0S_TIOA1	0x00000002
+#define AT91_TC_BMR_TC0XC0S_TIOA2	0x00000003
+
+#define AT91_TC_BMR_TC1XC1S_TCLK1	0x00000000
+#define AT91_TC_BMR_TC1XC1S_NONE	0x00000004
+#define AT91_TC_BMR_TC1XC1S_TIOA0	0x00000008
+#define AT91_TC_BMR_TC1XC1S_TIOA2	0x0000000C
+
+#define AT91_TC_BMR_TC2XC2S_TCLK2	0x00000000
+#define AT91_TC_BMR_TC2XC2S_NONE	0x00000010
+#define AT91_TC_BMR_TC2XC2S_TIOA0	0x00000020
+#define AT91_TC_BMR_TC2XC2S_TIOA1	0x00000030
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_wdt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_wdt.h
new file mode 100644
index 000000000..0644bbf3c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_wdt.h
@@ -0,0 +1,43 @@
+/*
+ * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
+ *
+ * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Watchdog Timer (WDT) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91_WDT_H
+#define AT91_WDT_H
+
+#ifdef __ASSEMBLY__
+
+#define AT91_ASM_WDT_MR	(ATMEL_BASE_WDT +  0x04)
+
+#else
+
+typedef struct at91_wdt {
+	u32	cr;
+	u32	mr;
+	u32	sr;
+} at91_wdt_t;
+
+#endif
+
+#define AT91_WDT_CR_WDRSTT		1
+#define AT91_WDT_CR_KEY			0xa5000000	/* KEY Password */
+
+#define AT91_WDT_MR_WDV(x)		(x & 0xfff)
+#define AT91_WDT_MR_WDFIEN		0x00001000
+#define AT91_WDT_MR_WDRSTEN		0x00002000
+#define AT91_WDT_MR_WDRPROC		0x00004000
+#define AT91_WDT_MR_WDDIS		0x00008000
+#define AT91_WDT_MR_WDD(x)		((x & 0xfff) << 16)
+#define AT91_WDT_MR_WDDBGHLT		0x10000000
+#define AT91_WDT_MR_WDIDLEHLT		0x20000000
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9.h
new file mode 100644
index 000000000..63870bc65
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9.h
@@ -0,0 +1,78 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h]
+ *
+ *  Copyright (C) 2007 Stelian Pop <stelian@popies.net>
+ *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
+ *  Copyright (C) 2007 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91CAP9 datasheet revision B (Preliminary).
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91CAP9_H
+#define AT91CAP9_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS		1	/* System Peripherals */
+#define AT91CAP9_ID_PIOABCD	2	/* Parallel IO Controller A, B, C and D */
+#define AT91CAP9_ID_MPB0	3	/* MP Block Peripheral 0 */
+#define AT91CAP9_ID_MPB1	4	/* MP Block Peripheral 1 */
+#define AT91CAP9_ID_MPB2	5	/* MP Block Peripheral 2 */
+#define AT91CAP9_ID_MPB3	6	/* MP Block Peripheral 3 */
+#define AT91CAP9_ID_MPB4	7	/* MP Block Peripheral 4 */
+#define AT91CAP9_ID_US0		8	/* USART 0 */
+#define AT91CAP9_ID_US1		9	/* USART 1 */
+#define AT91CAP9_ID_US2		10	/* USART 2 */
+#define AT91CAP9_ID_MCI0	11	/* Multimedia Card Interface 0 */
+#define AT91CAP9_ID_MCI1	12	/* Multimedia Card Interface 1 */
+#define AT91CAP9_ID_CAN		13	/* CAN */
+#define AT91CAP9_ID_TWI		14	/* Two-Wire Interface */
+#define AT91CAP9_ID_SPI0	15	/* Serial Peripheral Interface 0 */
+#define AT91CAP9_ID_SPI1	16	/* Serial Peripheral Interface 0 */
+#define AT91CAP9_ID_SSC0	17	/* Serial Synchronous Controller 0 */
+#define AT91CAP9_ID_SSC1	18	/* Serial Synchronous Controller 1 */
+#define AT91CAP9_ID_AC97C	19	/* AC97 Controller */
+#define AT91CAP9_ID_TCB		20	/* Timer Counter 0, 1 and 2 */
+#define AT91CAP9_ID_PWMC	21	/* Pulse Width Modulation Controller */
+#define AT91CAP9_ID_EMAC	22	/* Ethernet */
+#define AT91CAP9_ID_AESTDES	23	/* Advanced Encryption Standard, Triple DES */
+#define AT91CAP9_ID_ADC		24	/* Analog-to-Digital Converter */
+#define AT91CAP9_ID_ISI		25	/* Image Sensor Interface */
+#define AT91CAP9_ID_LCDC	26	/* LCD Controller */
+#define AT91CAP9_ID_DMA		27	/* DMA Controller */
+#define AT91CAP9_ID_UDPHS	28	/* USB High Speed Device Port */
+#define AT91CAP9_ID_UHP		29	/* USB Host Port */
+#define AT91CAP9_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
+#define AT91CAP9_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
+
+#define AT91_PIO_BASE	0xfffff200
+#define AT91_PMC_BASE	0xfffffc00
+#define AT91_RSTC_BASE	0xfffffd00
+#define AT91_PIT_BASE	0xfffffd30
+
+/*
+ * Internal Memory.
+ */
+#define AT91CAP9_SRAM_BASE	0x00100000	/* Internal SRAM base address */
+#define AT91CAP9_SRAM_SIZE	(32 * SZ_1K)	/* Internal SRAM size (32Kb) */
+
+#define AT91CAP9_ROM_BASE	0x00400000	/* Internal ROM base address */
+#define AT91CAP9_ROM_SIZE	(32 * SZ_1K)	/* Internal ROM size (32Kb) */
+
+#define AT91CAP9_LCDC_BASE	0x00500000	/* LCD Controller */
+#define AT91CAP9_UDPHS_BASE	0x00600000	/* USB High Speed Device Port */
+#define AT91CAP9_UHP_BASE	0x00700000	/* USB Host controller */
+
+#define CONFIG_DRAM_BASE	AT91_CHIPSELECT_6
+
+/*
+ * Cpu Name
+ */
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91CAP9"
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
new file mode 100644
index 000000000..009a19daf
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
@@ -0,0 +1,129 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h]
+ *
+ *  Copyright (C) 2007 Stelian Pop <stelian@popies.net>
+ *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
+ *  Copyright (C) 2006 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91CAP9 datasheet revision B (Preliminary).
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91CAP9_MATRIX_H
+#define AT91CAP9_MATRIX_H
+
+#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6	(AT91_MATRIX + 0x18)	/* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7	(AT91_MATRIX + 0x1C)	/* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8	(AT91_MATRIX + 0x20)	/* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9	(AT91_MATRIX + 0x24)	/* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10	(AT91_MATRIX + 0x28)	/* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11	(AT91_MATRIX + 0x2C)	/* Master Configuration Register 11 */
+#define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
+#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
+#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
+#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
+#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
+#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+
+#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6	(AT91_MATRIX + 0x58)	/* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7	(AT91_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG8	(AT91_MATRIX + 0x60)	/* Slave Configuration Register 8 */
+#define AT91_MATRIX_SCFG9	(AT91_MATRIX + 0x64)	/* Slave Configuration Register 9 */
+#define		AT91_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
+#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
+#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
+#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
+#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
+#define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
+#define		AT91_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
+#define			AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
+#define			AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
+
+#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0	(AT91_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1	(AT91_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2	(AT91_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3	(AT91_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4	(AT91_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5	(AT91_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6	(AT91_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6	(AT91_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7	(AT91_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7	(AT91_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS8	(AT91_MATRIX + 0xC0)	/* Priority Register A for Slave 8 */
+#define AT91_MATRIX_PRBS8	(AT91_MATRIX + 0xC4)	/* Priority Register B for Slave 8 */
+#define AT91_MATRIX_PRAS9	(AT91_MATRIX + 0xC8)	/* Priority Register A for Slave 9 */
+#define AT91_MATRIX_PRBS9	(AT91_MATRIX + 0xCC)	/* Priority Register B for Slave 9 */
+#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
+#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
+#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
+#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
+#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
+#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
+#define		AT91_MATRIX_M6PR		(3 << 24)	/* Master 6 Priority */
+#define		AT91_MATRIX_M7PR		(3 << 28)	/* Master 7 Priority */
+#define		AT91_MATRIX_M8PR		(3 << 0)	/* Master 8 Priority (in Register B) */
+#define		AT91_MATRIX_M9PR		(3 << 4)	/* Master 9 Priority (in Register B) */
+#define		AT91_MATRIX_M10PR		(3 << 8)	/* Master 10 Priority (in Register B) */
+#define		AT91_MATRIX_M11PR		(3 << 12)	/* Master 11 Priority (in Register B) */
+
+#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
+#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define		AT91_MATRIX_RCB2		(1 << 2)
+#define		AT91_MATRIX_RCB3		(1 << 3)
+#define		AT91_MATRIX_RCB4		(1 << 4)
+#define		AT91_MATRIX_RCB5		(1 << 5)
+#define		AT91_MATRIX_RCB6		(1 << 6)
+#define		AT91_MATRIX_RCB7		(1 << 7)
+#define		AT91_MATRIX_RCB8		(1 << 8)
+#define		AT91_MATRIX_RCB9		(1 << 9)
+#define		AT91_MATRIX_RCB10		(1 << 10)
+#define		AT91_MATRIX_RCB11		(1 << 11)
+
+#define AT91_MPBS0_SFR		(AT91_MATRIX + 0x114)	/* MPBlock Slave 0 Special Function Register */
+#define AT91_MPBS1_SFR		(AT91_MATRIX + 0x11C)	/* MPBlock Slave 1 Special Function Register */
+
+#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x120)	/* EBI Chip Select Assignment Register */
+#define		AT91_MATRIX_EBI_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
+#define			AT91_MATRIX_EBI_CS1A_SMC		(0 << 1)
+#define			AT91_MATRIX_EBI_CS1A_BCRAMC		(1 << 1)
+#define		AT91_MATRIX_EBI_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
+#define			AT91_MATRIX_EBI_CS3A_SMC		(0 << 3)
+#define			AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA	(1 << 3)
+#define		AT91_MATRIX_EBI_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
+#define			AT91_MATRIX_EBI_CS4A_SMC		(0 << 4)
+#define			AT91_MATRIX_EBI_CS4A_SMC_CF1		(1 << 4)
+#define		AT91_MATRIX_EBI_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
+#define			AT91_MATRIX_EBI_CS5A_SMC		(0 << 5)
+#define			AT91_MATRIX_EBI_CS5A_SMC_CF2		(1 << 5)
+#define		AT91_MATRIX_EBI_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
+#define		AT91_MATRIX_EBI_DQSPDC		(1 << 9)	/* Data Qualifier Strobe Pull-Down Configuration */
+#define		AT91_MATRIX_EBI_VDDIOMSEL	(1 << 16)	/* Memory voltage selection */
+#define			AT91_MATRIX_EBI_VDDIOMSEL_1_8V		(0 << 16)
+#define			AT91_MATRIX_EBI_VDDIOMSEL_3_3V		(1 << 16)
+
+#define AT91_MPBS2_SFR		(AT91_MATRIX + 0x12C)	/* MPBlock Slave 2 Special Function Register */
+#define AT91_MPBS3_SFR		(AT91_MATRIX + 0x130)	/* MPBlock Slave 3 Special Function Register */
+#define AT91_APB_SFR		(AT91_MATRIX + 0x134)	/* APB Bridge Special Function Register */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91rm9200.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91rm9200.h
new file mode 100644
index 000000000..25bb071e9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91rm9200.h
@@ -0,0 +1,137 @@
+/*
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AT91RM9200_H__
+#define __AT91RM9200_H__
+
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 family */
+#define CONFIG_ARM920T		/* it's an ARM920T Core */
+#define CONFIG_ARCH_CPU_INIT	/* we need arch_cpu_init() for hw timers */
+#define CONFIG_AT91_GPIO	/* and require always gpio features */
+
+/* Periperial Identifiers */
+
+#define ATMEL_ID_SYS	1	/* System Peripheral */
+#define ATMEL_ID_PIOA	2	/* PIO port A */
+#define ATMEL_ID_PIOB	3	/* PIO port B */
+#define ATMEL_ID_PIOC	4	/* PIO port C */
+#define ATMEL_ID_PIOD	5	/* PIO port D BGA only */
+#define ATMEL_ID_USART0	6	/* USART 0 */
+#define ATMEL_ID_USART1	7	/* USART 1 */
+#define ATMEL_ID_USART2	8	/* USART 2 */
+#define ATMEL_ID_USART3	9	/* USART 3 */
+#define ATMEL_ID_MCI	10	/* Multimedia Card Interface */
+#define ATMEL_ID_UDP	11	/* USB Device Port */
+#define ATMEL_ID_TWI	12	/* Two Wire Interface */
+#define ATMEL_ID_SPI	13	/* Serial Peripheral Interface */
+#define ATMEL_ID_SSC0	14	/* Synch. Serial Controller 0 */
+#define ATMEL_ID_SSC1	15	/* Synch. Serial Controller 1 */
+#define ATMEL_ID_SSC2	16	/* Synch. Serial Controller 2 */
+#define ATMEL_ID_TC0	17	/* Timer Counter 0 */
+#define ATMEL_ID_TC1	18	/* Timer Counter 1 */
+#define ATMEL_ID_TC2	19	/* Timer Counter 2 */
+#define ATMEL_ID_TC3	20	/* Timer Counter 3 */
+#define ATMEL_ID_TC4	21	/* Timer Counter 4 */
+#define ATMEL_ID_TC5	22	/* Timer Counter 5 */
+#define ATMEL_ID_UHP	23	/* OHCI USB Host Port */
+#define ATMEL_ID_EMAC	24	/* Ethernet MAC */
+#define ATMEL_ID_IRQ0	25	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ1	26	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ2	27	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ3	28	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ4	29	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ5	30	/* Advanced Interrupt Controller */
+#define ATMEL_ID_IRQ6	31	/* Advanced Interrupt Controller */
+
+#define ATMEL_USB_HOST_BASE	0x00300000
+
+#define ATMEL_BASE_TC		0xFFFA0000
+#define ATMEL_BASE_UDP		0xFFFB0000
+#define ATMEL_BASE_MCI		0xFFFB4000
+#define ATMEL_BASE_TWI		0xFFFB8000
+#define ATMEL_BASE_EMAC		0xFFFBC000
+#define ATMEL_BASE_USART	0xFFFC0000	/* 4x 0x4000 Offset */
+#define ATMEL_BASE_USART0	ATMEL_BASE_USART
+#define ATMEL_BASE_USART1	(ATMEL_BASE_USART + 0x4000)
+#define ATMEL_BASE_USART2	(ATMEL_BASE_USART + 0x8000)
+#define ATMEL_BASE_USART3	(ATMEL_BASE_USART + 0xC000)
+
+#define ATMEL_BASE_SCC		0xFFFD0000	/* 4x 0x4000 Offset */
+#define ATMEL_BASE_SPI		0xFFFE0000
+
+#define ATMEL_BASE_AIC		0xFFFFF000
+#define ATMEL_BASE_DBGU		0xFFFFF200
+#define ATMEL_BASE_PIO		0xFFFFF400	/* 4x 0x200 Offset */
+#define ATMEL_BASE_PIOA		0xFFFFF400
+#define ATMEL_BASE_PIOB		0xFFFFF600
+#define ATMEL_BASE_PIOC		0xFFFFF800
+#define ATMEL_BASE_PIOD		0xFFFFFA00
+#define ATMEL_BASE_PMC		0xFFFFFC00
+#define ATMEL_BASE_ST		0xFFFFFD00
+#define ATMEL_BASE_RTC		0xFFFFFE00
+#define ATMEL_BASE_MC		0xFFFFFF00
+
+#define AT91_PIO_BASE	ATMEL_BASE_PIO
+
+/* AT91RM9200 Periperial Multiplexing A */
+/* Port A */
+#define ATMEL_PMX_AA_EREFCK	0x00000080
+#define ATMEL_PMX_AA_ETXCK	0x00000080
+#define ATMEL_PMX_AA_ETXEN	0x00000100
+#define ATMEL_PMX_AA_ETX0	0x00000200
+#define ATMEL_PMX_AA_ETX1	0x00000400
+#define ATMEL_PMX_AA_ECRS	0x00000800
+#define ATMEL_PMX_AA_ECRSDV	0x00000800
+#define ATMEL_PMX_AA_ERX0	0x00001000
+#define ATMEL_PMX_AA_ERX1	0x00002000
+#define ATMEL_PMX_AA_ERXER	0x00004000
+#define ATMEL_PMX_AA_EMDC	0x00008000
+#define ATMEL_PMX_AA_EMDIO	0x00010000
+
+#define ATMEL_PMX_AA_TXD2	0x00800000
+
+#define ATMEL_PMX_AA_TWD	0x02000000
+#define ATMEL_PMX_AA_TWCK	0x04000000
+
+/* Port B */
+#define ATMEL_PMX_BA_ERXCK	0x00080000
+#define ATMEL_PMX_BA_ECOL	0x00040000
+#define ATMEL_PMX_BA_ERXDV	0x00020000
+#define ATMEL_PMX_BA_ERX3	0x00010000
+#define ATMEL_PMX_BA_ERX2	0x00008000
+#define ATMEL_PMX_BA_ETXER	0x00004000
+#define ATMEL_PMX_BA_ETX3	0x00002000
+#define ATMEL_PMX_BA_ETX2	0x00001000
+
+/* Port B */
+
+#define ATMEL_PMX_CA_BFCK	0x00000001
+#define ATMEL_PMX_CA_BFRDY	0x00000002
+#define ATMEL_PMX_CA_SMOE	0x00000002
+#define ATMEL_PMX_CA_BFAVD	0x00000004
+#define ATMEL_PMX_CA_BFBAA	0x00000008
+#define ATMEL_PMX_CA_SMWE	0x00000008
+#define ATMEL_PMX_CA_BFOE	0x00000010
+#define ATMEL_PMX_CA_BFWE	0x00000020
+#define ATMEL_PMX_CA_NWAIT	0x00000040
+#define ATMEL_PMX_CA_A23	0x00000080
+#define ATMEL_PMX_CA_A24	0x00000100
+#define ATMEL_PMX_CA_A25	0x00000200
+#define ATMEL_PMX_CA_CFRNW	0x00000200
+#define ATMEL_PMX_CA_NCS4	0x00000400
+#define ATMEL_PMX_CA_CFCS	0x00000400
+#define ATMEL_PMX_CA_NCS5	0x00000800
+#define ATMEL_PMX_CA_CFCE1	0x00001000
+#define ATMEL_PMX_CA_NCS6	0x00001000
+#define ATMEL_PMX_CA_CFCE2	0x00002000
+#define ATMEL_PMX_CA_NCS7	0x00002000
+#define ATMEL_PMX_CA_D16_31	0xFFFF0000
+
+#define ATMEL_PIO_PORTS		4	/* theese SoCs have 4 PIO */
+#define ATMEL_PMC_UHP		AT91RM9200_PMC_UHP
+
+#define CONFIG_SYS_ATMEL_CPU_NAME	"AT91RM9200"
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260.h
new file mode 100644
index 000000000..2e902eef3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260.h
@@ -0,0 +1,170 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h]
+ *
+ * (C) 2006 Andrew Victor
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * Definitions for the SoCs:
+ * AT91SAM9260, AT91SAM9G20, AT91SAM9XE
+ *
+ * Note that those SoCs are mostly software and pin compatible,
+ * therefore this file applies to all of them. Differences between
+ * those SoCs are concentrated at the end of this file.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91SAM9260_H
+#define AT91SAM9260_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_ARM926EJS	/* ARM926EJS Core */
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS	1	/* System Peripherals */
+#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
+#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
+#define ATMEL_ID_PIOC	4	/* Parallel IO Controller C */
+#define ATMEL_ID_ADC	5	/* Analog-to-Digital Converter */
+#define ATMEL_ID_USART0	6	/* USART 0 */
+#define ATMEL_ID_USART1	7	/* USART 1 */
+#define ATMEL_ID_USART2	8	/* USART 2 */
+#define ATMEL_ID_MCI	9	/* Multimedia Card Interface */
+#define ATMEL_ID_UDP	10	/* USB Device Port */
+#define ATMEL_ID_TWI0	11	/* Two-Wire Interface 0 */
+#define ATMEL_ID_SPI0	12	/* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1	13	/* Serial Peripheral Interface 1 */
+#define ATMEL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
+/* Reserved:		15 */
+/* Reserved:		16 */
+#define ATMEL_ID_TC0	17	/* Timer Counter 0 */
+#define ATMEL_ID_TC1	18	/* Timer Counter 1 */
+#define ATMEL_ID_TC2	19	/* Timer Counter 2 */
+#define ATMEL_ID_UHP	20	/* USB Host port */
+#define ATMEL_ID_EMAC0	21	/* Ethernet 0 */
+#define ATMEL_ID_ISI	22	/* Image Sensor Interface */
+#define ATMEL_ID_USART3	23	/* USART 3 */
+#define ATMEL_ID_USART4	24	/* USART 4 */
+/* USART5 or TWI1:	25 */
+#define ATMEL_ID_TC3	26	/* Timer Counter 3 */
+#define ATMEL_ID_TC4	27	/* Timer Counter 4 */
+#define ATMEL_ID_TC5	28	/* Timer Counter 5 */
+#define ATMEL_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
+#define ATMEL_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
+#define ATMEL_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_TCB0		0xfffa0000
+#define ATMEL_BASE_TC0		0xfffa0000
+#define ATMEL_BASE_TC1		0xfffa0040
+#define ATMEL_BASE_TC2		0xfffa0080
+#define ATMEL_BASE_UDP0		0xfffa4000
+#define ATMEL_BASE_MCI		0xfffa8000
+#define ATMEL_BASE_TWI0		0xfffac000
+#define ATMEL_BASE_USART0	0xfffb0000
+#define ATMEL_BASE_USART1	0xfffb4000
+#define ATMEL_BASE_USART2	0xfffb8000
+#define ATMEL_BASE_SSC0		0xfffbc000
+#define ATMEL_BASE_ISI0		0xfffc0000
+#define ATMEL_BASE_EMAC0	0xfffc4000
+#define ATMEL_BASE_SPI0		0xfffc8000
+#define ATMEL_BASE_SPI1		0xfffcc000
+#define ATMEL_BASE_USART3	0xfffd0000
+#define ATMEL_BASE_USART4	0xfffd4000
+/* USART5 or TWI1:		0xfffd8000 */
+#define ATMEL_BASE_TCB1		0xfffdc000
+#define ATMEL_BASE_TC3		0xfffdc000
+#define ATMEL_BASE_TC4		0xfffdc040
+#define ATMEL_BASE_TC5		0xfffdc080
+#define ATMEL_BASE_ADC		0xfffe0000
+/* Reserved:	0xfffe4000 - 0xffffe7ff */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS		0xffffe800
+#define ATMEL_BASE_SDRAMC	0xffffea00
+#define ATMEL_BASE_SMC		0xffffec00
+#define ATMEL_BASE_MATRIX	0xffffee00
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_DBGU		0xfffff200
+#define ATMEL_BASE_PIOA		0xfffff400
+#define ATMEL_BASE_PIOB		0xfffff600
+#define ATMEL_BASE_PIOC		0xfffff800
+/* EEFC:			0xfffffa00 */
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffd00
+#define ATMEL_BASE_SHDWN	0xfffffd10
+#define ATMEL_BASE_RTT		0xfffffd20
+#define ATMEL_BASE_PIT		0xfffffd30
+#define ATMEL_BASE_WDT		0xfffffd40
+/* GPBR(non-XE SoCs):		0xfffffd50 */
+/* GPBR(XE SoCs):		0xfffffd60 */
+/* Reserved:	0xfffffd70 - 0xffffffff */
+
+/*
+ * Internal Memory common on all these SoCs
+ */
+#define ATMEL_BASE_BOOT		0x00000000	/* Boot mapped area */
+#define ATMEL_BASE_ROM		0x00100000	/* Internal ROM base address */
+/* SRAM or FLASH:		0x00200000 */
+/* SRAM:			0x00300000 */
+/* Reserved:			0x00400000 */
+#define ATMEL_UHP_BASE		0x00500000	/* USB Host controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000	/* typically NOR */
+#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
+#define ATMEL_BASE_CS2		0x30000000
+#define ATMEL_BASE_CS3		0x40000000	/* typically NAND */
+#define ATMEL_BASE_CS4		0x50000000
+#define ATMEL_BASE_CS5		0x60000000
+#define ATMEL_BASE_CS6		0x70000000
+#define ATMEL_BASE_CS7		0x80000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS		3		/* these SoCs have 3 PIO */
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
+#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
+
+/*
+ * SoC specific defines
+ */
+#if defined(CONFIG_AT91SAM9XE)
+# define ATMEL_CPU_NAME		"AT91SAM9XE"
+# define ATMEL_ID_TWI1		25	/* TWI 1 */
+# define ATMEL_BASE_FLASH	0x00200000	/* Internal FLASH */
+# define ATMEL_BASE_SRAM	0x00300000	/* Internal SRAM */
+# define ATMEL_BASE_TWI1	0xfffd8000
+# define ATMEL_BASE_EEFC	0xfffffa00
+# define ATMEL_BASE_GPBR	0xfffffd60
+#elif defined(CONFIG_AT91SAM9260)
+# define ATMEL_CPU_NAME		"AT91SAM9260"
+# define ATMEL_ID_USART5	25	/* USART 5 */
+# define ATMEL_BASE_SRAM0	0x00200000	/* Internal SRAM 0 */
+# define ATMEL_BASE_SRAM1	0x00300000	/* Internal SRAM 1 */
+# define ATMEL_BASE_USART5	0xfffd8000
+# define ATMEL_BASE_GPBR	0xfffffd50
+#elif defined(CONFIG_AT91SAM9G20)
+# define ATMEL_CPU_NAME		"AT91SAM9G20"
+# define ATMEL_ID_USART5	25	/* USART 5 */
+# define ATMEL_BASE_SRAM0	0x00200000	/* Internal SRAM 0 */
+# define ATMEL_BASE_SRAM1	0x00300000	/* Internal SRAM 1 */
+# define ATMEL_BASE_USART5	0xfffd8000
+# define ATMEL_BASE_GPBR	0xfffffd50
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h
new file mode 100644
index 000000000..4755fa10b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h
@@ -0,0 +1,65 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9260 datasheet revision B.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91SAM9260_MATRIX_H
+#define AT91SAM9260_MATRIX_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines access to the matrix' maximum of
+ * 16 masters and 16 slaves.
+ * However, on the AT91SAM9260/9G20/9XE there exist only
+ * 6 Masters and 5 Slaves!
+ */
+struct at91_matrix {
+	u32	mcfg[16];	/* Master Configuration Registers */
+	u32	scfg[16];	/* Slave Configuration Registers */
+	u32	pras[16][2];	/* Priority Assignment Slave Registers */
+	u32	mrcr;		/* Master Remap Control Register */
+	u32	filler[0x06];
+	u32	ebicsa;		/* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
+#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT	18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
+
+#define AT91_MATRIX_M0PR_SHIFT		0
+#define AT91_MATRIX_M1PR_SHIFT		4
+#define AT91_MATRIX_M2PR_SHIFT		8
+#define AT91_MATRIX_M3PR_SHIFT		12
+#define AT91_MATRIX_M4PR_SHIFT		16
+#define AT91_MATRIX_M5PR_SHIFT		20
+
+#define AT91_MATRIX_RCB0		(1 << 0)
+#define AT91_MATRIX_RCB1		(1 << 1)
+
+#define AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
+#define AT91_MATRIX_DBPUC		(1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261.h
new file mode 100644
index 000000000..f7ad11349
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261.h
@@ -0,0 +1,137 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
+ *
+ * Copyright (C) SAN People
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * Definitions for the SoCs:
+ * AT91SAM9261, AT91SAM9G10
+ *
+ * Note that those SoCs are mostly software and pin compatible,
+ * therefore this file applies to all of them. Differences between
+ * those SoCs are concentrated at the end of this file.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91SAM9261_H
+#define AT91SAM9261_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_ARM926EJS	/* ARM926EJS Core */
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS	1	/* System Peripherals */
+#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
+#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
+#define ATMEL_ID_PIOC	4	/* Parallel IO Controller C */
+/* Reserved:		5 */
+#define ATMEL_ID_USART0	6	/* USART 0 */
+#define ATMEL_ID_USART1	7	/* USART 1 */
+#define ATMEL_ID_USART2	8	/* USART 2 */
+#define ATMEL_ID_MCI	9	/* Multimedia Card Interface */
+#define ATMEL_ID_UDP	10	/* USB Device Port */
+#define ATMEL_ID_TWI0	11	/* Two-Wire Interface 0 */
+#define ATMEL_ID_SPI0	12	/* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1	13	/* Serial Peripheral Interface 1 */
+#define ATMEL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1	15	/* Serial Synchronous Controller 1 */
+#define ATMEL_ID_SSC2	16	/* Serial Synchronous Controller 2 */
+#define ATMEL_ID_TC0	17	/* Timer Counter 0 */
+#define ATMEL_ID_TC1	18	/* Timer Counter 1 */
+#define ATMEL_ID_TC2	19	/* Timer Counter 2 */
+#define ATMEL_ID_UHP	20	/* USB Host port */
+#define ATMEL_ID_LCDC	21	/* LDC Controller */
+/* Reserved:		22-28 */
+#define ATMEL_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
+#define ATMEL_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
+#define ATMEL_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_TCB0		0xfffa0000
+#define ATMEL_BASE_TC0		0xfffa0000
+#define ATMEL_BASE_TC1		0xfffa0040
+#define ATMEL_BASE_TC2		0xfffa0080
+#define ATMEL_BASE_UDP0		0xfffa4000
+#define ATMEL_BASE_MCI		0xfffa8000
+#define ATMEL_BASE_TWI0		0xfffac000
+#define ATMEL_BASE_USART0	0xfffb0000
+#define ATMEL_BASE_USART1	0xfffb4000
+#define ATMEL_BASE_USART2	0xfffb8000
+#define ATMEL_BASE_SSC0		0xfffbc000
+#define ATMEL_BASE_SSC1		0xfffc0000
+#define ATMEL_BASE_SSC2		0xfffc4000
+#define ATMEL_BASE_SPI0		0xfffc8000
+#define ATMEL_BASE_SPI1		0xfffcc000
+/* Reserved:	0xfffc4000 - 0xffffe9ff */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS		0xffffea00
+#define ATMEL_BASE_SDRAMC	0xffffea00
+#define ATMEL_BASE_SMC		0xffffec00
+#define ATMEL_BASE_MATRIX	0xffffee00
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_DBGU		0xfffff200
+#define ATMEL_BASE_PIOA		0xfffff400
+#define ATMEL_BASE_PIOB		0xfffff600
+#define ATMEL_BASE_PIOC		0xfffff800
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffd00
+#define ATMEL_BASE_SHDWN	0xfffffd10
+#define ATMEL_BASE_RTT		0xfffffd20
+#define ATMEL_BASE_PIT		0xfffffd30
+#define ATMEL_BASE_WDT		0xfffffd40
+#define ATMEL_BASE_GPBR		0xfffffd50
+
+/*
+ * Internal Memory common on all these SoCs
+ */
+#define ATMEL_BASE_SRAM		0x00300000	/* Internal SRAM base address */
+#define ATMEL_SIZE_SRAM		0x00028000	/* Internal SRAM size (160Kb) */
+
+#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM base address */
+#define ATMEL_SIZE_ROM		0x00008000	/* Internal ROM size (32Kb) */
+
+#define ATMEL_BASE_UHP		0x00500000	/* USB Host controller */
+#define ATMEL_BASE_LCDC		0x00600000	/* LDC controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000	/* typically NOR */
+#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
+#define ATMEL_BASE_CS2		0x30000000
+#define ATMEL_BASE_CS3		0x40000000	/* typically NAND */
+#define ATMEL_BASE_CS4		0x50000000
+#define ATMEL_BASE_CS5		0x60000000
+#define ATMEL_BASE_CS6		0x70000000
+#define ATMEL_BASE_CS7		0x80000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS		3		/* theese SoCs have 3 PIO */
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
+#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
+
+/*
+ * SoC specific defines
+ */
+#if defined(CONFIG_AT91SAM9261)
+# define ATMEL_CPU_NAME		"AT91SAM9261"
+#elif defined(CONFIG_AT91SAM9G10)
+# define ATMEL_CPU_NAME		"AT91SAM9G10"
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
new file mode 100644
index 000000000..fc5f0831b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
@@ -0,0 +1,56 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91SAM9261_MATRIX_H
+#define AT91SAM9261_MATRIX_H
+
+#ifndef __ASSEMBLY__
+
+struct at91_matrix {
+	u32	mcfg;	/* Master Configuration Registers */
+	u32	scfg[5];	/* Slave Configuration Registers */
+	u32	filler[6];
+	u32	ebicsa;		/* EBI Chip Select Assignment Register */
+};
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_M0PR_SHIFT          0
+#define AT91_MATRIX_M1PR_SHIFT          4
+#define AT91_MATRIX_M2PR_SHIFT          8
+#define AT91_MATRIX_M3PR_SHIFT          12
+#define AT91_MATRIX_M4PR_SHIFT          16
+#define AT91_MATRIX_M5PR_SHIFT          20
+
+#define AT91_MATRIX_RCB0                (1 << 0)
+#define AT91_MATRIX_RCB1                (1 << 1)
+
+#define AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define AT91_MATRIX_DBPUC               (1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263.h
new file mode 100644
index 000000000..3206af8c3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263.h
@@ -0,0 +1,148 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h]
+ *
+ * (C) 2007 Atmel Corporation.
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * Definitions for the SoC:
+ * AT91SAM9263
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91SAM9263_H
+#define AT91SAM9263_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_ARM926EJS	/* ARM926EJS Core */
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS	1	/* System Peripherals */
+#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
+#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
+#define ATMEL_ID_PIOCDE	4	/* Parallel IO Controller C, D and E */
+/* Reserved:		5 */
+/* Reserved:		6 */
+#define ATMEL_ID_USART0	7	/* USART 0 */
+#define ATMEL_ID_USART1	8	/* USART 1 */
+#define ATMEL_ID_USART2	9	/* USART 2 */
+#define ATMEL_ID_MCI0	10	/* Multimedia Card Interface 0 */
+#define ATMEL_ID_MCI1	11	/* Multimedia Card Interface 1 */
+#define ATMEL_ID_CAN	12	/* CAN */
+#define ATMEL_ID_TWI	13	/* Two-Wire Interface */
+#define ATMEL_ID_SPI0	14	/* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1	15	/* Serial Peripheral Interface 1 */
+#define ATMEL_ID_SSC0	16	/* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1	17	/* Serial Synchronous Controller 1 */
+#define ATMEL_ID_AC97C	18	/* AC97 Controller */
+#define ATMEL_ID_TCB	19	/* Timer Counter 0, 1 and 2 */
+#define ATMEL_ID_PWMC	20	/* Pulse Width Modulation Controller */
+#define ATMEL_ID_EMAC	21	/* Ethernet */
+/* Reserved:		22 */
+#define ATMEL_ID_2DGE	23	/* 2D Graphic Engine */
+#define ATMEL_ID_UDP	24	/* USB Device Port */
+#define ATMEL_ID_ISI	25	/* Image Sensor Interface */
+#define ATMEL_ID_LCDC	26	/* LCD Controller */
+#define ATMEL_ID_DMA	27	/* DMA Controller */
+/* Reserved:		28 */
+#define ATMEL_ID_UHP	29	/* USB Host port */
+#define ATMEL_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
+#define ATMEL_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_UDP		0xfff78000
+#define ATMEL_BASE_TCB0		0xfff7c000
+#define ATMEL_BASE_TC0		0xfff7c000
+#define ATMEL_BASE_TC1		0xfff7c040
+#define ATMEL_BASE_TC2		0xfff7c080
+#define ATMEL_BASE_MCI0		0xfff80000
+#define ATMEL_BASE_MCI1		0xfff84000
+#define ATMEL_BASE_TWI		0xfff88000
+#define ATMEL_BASE_USART0	0xfff8c000
+#define ATMEL_BASE_USART1	0xfff90000
+#define ATMEL_BASE_USART2	0xfff94000
+#define ATMEL_BASE_SSC0		0xfff98000
+#define ATMEL_BASE_SSC1		0xfff9c000
+#define ATMEL_BASE_AC97C	0xfffa0000
+#define ATMEL_BASE_SPI0		0xfffa4000
+#define ATMEL_BASE_SPI1		0xfffa8000
+#define ATMEL_BASE_CAN		0xfffac000
+#define ATMEL_BASE_PWMC		0xfffb8000
+#define ATMEL_BASE_EMAC		0xfffbc000
+#define ATMEL_BASE_ISI		0xfffc4000
+#define ATMEL_BASE_2DGE		0xfffc8000
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_ECC0		0xffffe000
+#define ATMEL_BASE_SDRAMC0	0xffffe200
+#define ATMEL_BASE_SMC0		0xffffe400
+#define ATMEL_BASE_ECC1		0xffffe600
+#define ATMEL_BASE_SDRAMC1	0xffffe800
+#define ATMEL_BASE_SMC1		0xffffea00
+#define ATMEL_BASE_MATRIX	0xffffec00
+#define ATMEL_BASE_CCFG		0xffffed10
+#define ATMEL_BASE_DBGU		0xffffee00
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_PIOA		0xfffff200
+#define ATMEL_BASE_PIOB		0xfffff400
+#define ATMEL_BASE_PIOC		0xfffff600
+#define ATMEL_BASE_PIOD		0xfffff800
+#define ATMEL_BASE_PIOE		0xfffffa00
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffd00
+#define ATMEL_BASE_SHDWC	0xfffffd10
+#define ATMEL_BASE_RTT0		0xfffffd20
+#define ATMEL_BASE_PIT		0xfffffd30
+#define ATMEL_BASE_WDT		0xfffffd40
+#define ATMEL_BASE_RTT1		0xfffffd50
+#define ATMEL_BASE_GPBR		0xfffffd60
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_SRAM0	0x00300000	/* Internal SRAM 0 */
+
+#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM */
+
+#define ATMEL_BASE_SRAM1	0x00500000	/* Internal SRAM 1 */
+
+#define ATMEL_BASE_LCDC		0x00700000	/* LCD Controller */
+#define ATMEL_BASE_DMAC		0x00800000	/* DMA Controller */
+#define ATMEL_BASE_UHP		0x00a00000	/* USB Host controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000	/* typically NOR */
+#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
+#define ATMEL_BASE_CS2		0x30000000
+#define ATMEL_BASE_CS3		0x40000000	/* typically NAND */
+#define ATMEL_BASE_CS4		0x50000000
+#define ATMEL_BASE_CS5		0x60000000
+#define ATMEL_BASE_CS6		0x70000000
+#define ATMEL_BASE_CS7		0x80000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS		5		/* this SoCs has 5 PIO */
+#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
+
+/*
+ * Cpu Name
+ */
+#define ATMEL_CPU_NAME		"AT91SAM9263"
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
new file mode 100644
index 000000000..54d862287
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
@@ -0,0 +1,64 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h]
+ *
+ *  Copyright (C) 2006 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9263 datasheet revision B (Preliminary).
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91SAM9263_MATRIX_H
+#define AT91SAM9263_MATRIX_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines access to the matrix' maximum of
+ * 16 masters and 16 slaves.
+ * Note: not all masters/slaves are available
+ */
+struct at91_matrix {
+	u32	mcfg[16];	/* Master Configuration Registers */
+	u32	scfg[16];	/* Slave Configuration Registers */
+	u32	pras[16][2];	/* Priority Assignment Slave Registers */
+	u32	mrcr;		/* Master Remap Control Register */
+	u32	filler[0x06];
+	u32	ebicsa;		/* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
+#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT	18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
+
+#define AT91_MATRIX_M0PR_SHIFT		0
+#define AT91_MATRIX_M1PR_SHIFT		4
+#define AT91_MATRIX_M2PR_SHIFT		8
+#define AT91_MATRIX_M3PR_SHIFT		12
+#define AT91_MATRIX_M4PR_SHIFT		16
+#define AT91_MATRIX_M5PR_SHIFT		20
+
+#define AT91_MATRIX_RCB0		(1 << 0)
+#define AT91_MATRIX_RCB1		(1 << 1)
+
+#define AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
+#define AT91_MATRIX_DBPUC		(1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
new file mode 100644
index 000000000..1b59cc6e4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H
+#define __ASM_ARCH_AT91SAM9_MATRIX_H
+
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#include <asm/arch/at91sam9260_matrix.h>
+#elif defined(CONFIG_AT91SAM9261)
+#include <asm/arch/at91sam9261_matrix.h>
+#elif defined(CONFIG_AT91SAM9263)
+#include <asm/arch/at91sam9263_matrix.h>
+#elif defined(CONFIG_AT91SAM9RL)
+#include <asm/arch/at91sam9rl_matrix.h>
+#elif defined(CONFIG_AT91CAP9)
+#include <asm/arch/at91cap9_matrix.h>
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#include <asm/arch/at91sam9g45_matrix.h>
+#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
+#include <asm/arch/at91sam9x5_matrix.h>
+#else
+#error "Unsupported AT91SAM9/CAP9 processor"
+#endif
+
+#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
new file mode 100644
index 000000000..5c98cc70d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
@@ -0,0 +1,97 @@
+/*
+ * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * SDRAM Controllers (SDRAMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91SAM9_SDRAMC_H
+#define AT91SAM9_SDRAMC_H
+
+#ifdef __ASSEMBLY__
+
+#ifndef ATMEL_BASE_SDRAMC
+#define ATMEL_BASE_SDRAMC	ATMEL_BASE_SDRAMC0
+#endif
+
+#define AT91_ASM_SDRAMC_MR	ATMEL_BASE_SDRAMC
+#define AT91_ASM_SDRAMC_TR	(ATMEL_BASE_SDRAMC + 0x04)
+#define AT91_ASM_SDRAMC_CR	(ATMEL_BASE_SDRAMC + 0x08)
+#define AT91_ASM_SDRAMC_MDR	(ATMEL_BASE_SDRAMC + 0x24)
+
+#endif
+
+/* SDRAM Controller (SDRAMC) registers */
+#define AT91_SDRAMC_MR		(ATMEL_BASE_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
+#define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
+#define			AT91_SDRAMC_MODE_NORMAL		0
+#define			AT91_SDRAMC_MODE_NOP		1
+#define			AT91_SDRAMC_MODE_PRECHARGE	2
+#define			AT91_SDRAMC_MODE_LMR		3
+#define			AT91_SDRAMC_MODE_REFRESH	4
+#define			AT91_SDRAMC_MODE_EXT_LMR	5
+#define			AT91_SDRAMC_MODE_DEEP		6
+
+#define AT91_SDRAMC_TR		(ATMEL_BASE_SDRAMC + 0x04)	/* SDRAM Controller Refresh Timer Register */
+#define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */
+
+#define AT91_SDRAMC_CR		(ATMEL_BASE_SDRAMC + 0x08)	/* SDRAM Controller Configuration Register */
+#define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
+#define			AT91_SDRAMC_NC_8	(0 << 0)
+#define			AT91_SDRAMC_NC_9	(1 << 0)
+#define			AT91_SDRAMC_NC_10	(2 << 0)
+#define			AT91_SDRAMC_NC_11	(3 << 0)
+#define		AT91_SDRAMC_NR		(3 << 2)		/* Number of Row Bits */
+#define			AT91_SDRAMC_NR_11	(0 << 2)
+#define			AT91_SDRAMC_NR_12	(1 << 2)
+#define			AT91_SDRAMC_NR_13	(2 << 2)
+#define		AT91_SDRAMC_NB		(1 << 4)		/* Number of Banks */
+#define			AT91_SDRAMC_NB_2	(0 << 4)
+#define			AT91_SDRAMC_NB_4	(1 << 4)
+#define		AT91_SDRAMC_CAS		(3 << 5)		/* CAS Latency */
+#define			AT91_SDRAMC_CAS_1	(1 << 5)
+#define			AT91_SDRAMC_CAS_2	(2 << 5)
+#define			AT91_SDRAMC_CAS_3	(3 << 5)
+#define		AT91_SDRAMC_DBW		(1 << 7)		/* Data Bus Width */
+#define			AT91_SDRAMC_DBW_32	(0 << 7)
+#define			AT91_SDRAMC_DBW_16	(1 << 7)
+#define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
+#define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
+#define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
+#define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
+#define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
+#define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
+
+#define AT91_SDRAMC_LPR		(ATMEL_BASE_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
+#define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
+#define			AT91_SDRAMC_LPCB_DISABLE		0
+#define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
+#define			AT91_SDRAMC_LPCB_POWER_DOWN		2
+#define			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
+#define		AT91_SDRAMC_PASR		(7 << 4)	/* Partial Array Self Refresh */
+#define		AT91_SDRAMC_TCSR		(3 << 8)	/* Temperature Compensated Self Refresh */
+#define		AT91_SDRAMC_DS			(3 << 10)	/* Drive Strength */
+#define		AT91_SDRAMC_TIMEOUT		(3 << 12)	/* Time to define when Low Power Mode is enabled */
+#define			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	(0 << 12)
+#define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
+#define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)
+
+#define AT91_SDRAMC_IER		(ATMEL_BASE_SDRAMC + 0x14)	/* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR		(ATMEL_BASE_SDRAMC + 0x18)	/* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR		(ATMEL_BASE_SDRAMC + 0x1C)	/* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR		(ATMEL_BASE_SDRAMC + 0x20)	/* SDRAM Controller Interrupt Status Register */
+#define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */
+
+#define AT91_SDRAMC_MDR		(ATMEL_BASE_SDRAMC + 0x24)	/* SDRAM Memory Device Register */
+#define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
+#define			AT91_SDRAMC_MD_SDRAM		0
+#define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
+
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_smc.h
new file mode 100644
index 000000000..d29e98e71
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9_smc.h
@@ -0,0 +1,76 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h]
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91SAM9_SMC_H
+#define AT91SAM9_SMC_H
+
+#ifdef __ASSEMBLY__
+
+#ifndef ATMEL_BASE_SMC
+#define ATMEL_BASE_SMC	ATMEL_BASE_SMC0
+#endif
+
+#define AT91_ASM_SMC_SETUP0	ATMEL_BASE_SMC
+#define AT91_ASM_SMC_PULSE0	(ATMEL_BASE_SMC + 0x04)
+#define AT91_ASM_SMC_CYCLE0	(ATMEL_BASE_SMC + 0x08)
+#define AT91_ASM_SMC_MODE0	(ATMEL_BASE_SMC + 0x0C)
+
+#else
+
+typedef struct	at91_cs {
+	u32	setup;		/* 0x00 SMC Setup Register */
+	u32	pulse;		/* 0x04 SMC Pulse Register */
+	u32	cycle;		/* 0x08 SMC Cycle Register */
+	u32	mode;		/* 0x0C SMC Mode Register */
+} at91_cs_t;
+
+typedef struct	at91_smc {
+	at91_cs_t	cs[8];
+} at91_smc_t;
+
+#endif /*  __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x)		(x & 0x7f)
+#define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x7f) << 8)
+#define AT91_SMC_PULSE_NRD(x)		((x & 0x7f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x7f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)
+
+#define AT91_SMC_MODE_RM_NCS		0x00000000
+#define AT91_SMC_MODE_RM_NRD		0x00000001
+#define AT91_SMC_MODE_WM_NCS		0x00000000
+#define AT91_SMC_MODE_WM_NWE		0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE	0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN	0x00000020
+#define AT91_SMC_MODE_EXNW_READY	0x00000030
+
+#define AT91_SMC_MODE_BAT		0x00000100
+#define AT91_SMC_MODE_DBW_8		0x00000000
+#define AT91_SMC_MODE_DBW_16		0x00001000
+#define AT91_SMC_MODE_DBW_32		0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF		0x00100000
+#define AT91_SMC_MODE_PMEN		0x01000000
+#define AT91_SMC_MODE_PS_4		0x00000000
+#define AT91_SMC_MODE_PS_8		0x10000000
+#define AT91_SMC_MODE_PS_16		0x20000000
+#define AT91_SMC_MODE_PS_32		0x30000000
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45.h
new file mode 100644
index 000000000..9cbfc277b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45.h
@@ -0,0 +1,152 @@
+/*
+ * Chip-specific header file for the AT91SAM9M1x family
+ *
+ * (C) 2008 Atmel Corporation.
+ *
+ * Definitions for the SoC:
+ * AT91SAM9G45
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91SAM9G45_H
+#define AT91SAM9G45_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_ARM926EJS	/* ARM926EJS Core */
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS	1	/* System Controller Interrupt */
+#define ATMEL_ID_PIOA	2	/* Parallel I/O Controller A */
+#define ATMEL_ID_PIOB	3	/* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC	4	/* Parallel I/O Controller C */
+#define ATMEL_ID_PIODE	5	/* Parallel I/O Controller D and E */
+#define ATMEL_ID_TRNG	6	/* True Random Number Generator */
+#define ATMEL_ID_USART0	7	/* USART 0 */
+#define ATMEL_ID_USART1	8	/* USART 1 */
+#define ATMEL_ID_USART2	9	/* USART 2 */
+#define ATMEL_ID_USART3	10	/* USART 3 */
+#define ATMEL_ID_MCI0	11	/* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_TWI0	12	/* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1	13	/* Two-Wire Interface 1 */
+#define ATMEL_ID_SPI0	14	/* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1	15	/* Serial Peripheral Interface 1 */
+#define ATMEL_ID_SSC0	16	/* Synchronous Serial Controller 0 */
+#define ATMEL_ID_SSC1	17	/* Synchronous Serial Controller 1 */
+#define ATMEL_ID_TCB	18	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define ATMEL_ID_PWMC	19	/* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC	20	/* Touch Screen ADC Controller */
+#define ATMEL_ID_DMA	21	/* DMA Controller */
+#define ATMEL_ID_UHPHS	22	/* USB Host High Speed */
+#define ATMEL_ID_LCDC	23	/* LCD Controller */
+#define ATMEL_ID_AC97C	24	/* AC97 Controller */
+#define ATMEL_ID_EMAC	25	/* Ethernet MAC */
+#define ATMEL_ID_ISI	26	/* Image Sensor Interface */
+#define ATMEL_ID_UDPHS	27	/* USB Device High Speed */
+#define ATMEL_ID_AESTDESSHA 28	/* AES + T-DES + SHA */
+#define ATMEL_ID_MCI1	29	/* High Speed Multimedia Card Interface 1 */
+#define ATMEL_ID_VDEC	30	/* Video Decoder */
+#define ATMEL_ID_IRQ0	31	/* Advanced Interrupt Controller */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_UDPHS	0xfff78000
+#define ATMEL_BASE_TC0		0xfff7c000
+#define ATMEL_BASE_TC1		0xfff7c040
+#define ATMEL_BASE_TC2		0xfff7c080
+#define ATMEL_BASE_MCI0		0xfff80000
+#define ATMEL_BASE_TWI0		0xfff84000
+#define ATMEL_BASE_TWI1		0xfff88000
+#define ATMEL_BASE_USART0	0xfff8c000
+#define ATMEL_BASE_USART1	0xfff90000
+#define ATMEL_BASE_USART2	0xfff94000
+#define ATMEL_BASE_USART3	0xfff98000
+#define ATMEL_BASE_SSC0		0xfff9c000
+#define ATMEL_BASE_SSC1		0xfffa0000
+#define ATMEL_BASE_SPI0		0xfffa4000
+#define ATMEL_BASE_SPI1		0xfffa8000
+#define ATMEL_BASE_AC97C	0xfffac000
+#define ATMEL_BASE_TSC		0xfffb0000
+#define ATMEL_BASE_ISI		0xfffb4000
+#define ATMEL_BASE_PWMC		0xfffb8000
+#define ATMEL_BASE_EMAC		0xfffbc000
+#define ATMEL_BASE_AES		0xfffc0000
+#define ATMEL_BASE_TDES		0xfffc4000
+#define ATMEL_BASE_SHA		0xfffc8000
+#define ATMEL_BASE_TRNG		0xfffcc000
+#define ATMEL_BASE_MCI1		0xfffd0000
+#define ATMEL_BASE_TC3		0xfffd4000
+#define ATMEL_BASE_TC4		0xfffd4040
+#define ATMEL_BASE_TC5		0xfffd4080
+/* Reserved:	0xfffd8000 - 0xffffe1ff */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS		0xffffe200
+#define ATMEL_BASE_ECC		0xffffe200
+#define ATMEL_BASE_DDRSDRC1	0xffffe400
+#define ATMEL_BASE_DDRSDRC0	0xffffe600
+#define ATMEL_BASE_SMC		0xffffe800
+#define ATMEL_BASE_MATRIX	0xffffea00
+#define ATMEL_BASE_DMA		0xffffec00
+#define ATMEL_BASE_DBGU		0xffffee00
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_PIOA		0xfffff200
+#define ATMEL_BASE_PIOB		0xfffff400
+#define ATMEL_BASE_PIOC		0xfffff600
+#define ATMEL_BASE_PIOD		0xfffff800
+#define ATMEL_BASE_PIOE		0xfffffa00
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffd00
+#define ATMEL_BASE_SHDWN	0xfffffd10
+#define ATMEL_BASE_RTT		0xfffffd20
+#define ATMEL_BASE_PIT		0xfffffd30
+#define ATMEL_BASE_WDT		0xfffffd40
+#define ATMEL_BASE_GPBR		0xfffffd60
+#define ATMEL_BASE_RTC		0xfffffdb0
+/* Reserved:	0xfffffdc0 - 0xffffffff */
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_SRAM		0x00300000	/* Internal SRAM base address */
+#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM base address */
+#define ATMEL_BASE_LCDC		0x00500000	/* LCD Controller */
+#define ATMEL_BASE_UDPHS_FIFO	0x00600000	/* USB Device HS controller */
+#define ATMEL_BASE_HCI		0x00700000	/* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI		0x00800000	/* USB Host controller (EHCI) */
+#define ATMEL_BASE_VDEC		0x00900000	/* Video Decoder Controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000
+#define ATMEL_BASE_CS1		0x20000000
+#define ATMEL_BASE_CS2		0x30000000
+#define ATMEL_BASE_CS3		0x40000000
+#define ATMEL_BASE_CS4		0x50000000
+#define ATMEL_BASE_CS5		0x60000000
+#define ATMEL_BASE_CS6		0x70000000
+#define ATMEL_BASE_CS7		0x80000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS		5		/* this SoCs has 5 PIO */
+#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
+#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
+/*
+ * Cpu Name
+ */
+#define ATMEL_CPU_NAME		"AT91SAM9G45"
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
new file mode 100644
index 000000000..80e49e343
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
@@ -0,0 +1,92 @@
+/*
+ * Matrix-centric header file for the AT91SAM9M1x family
+ *
+ *  Copyright (C) 2008 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9G45 preliminary datasheet.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef AT91SAM9G45_MATRIX_H
+#define AT91SAM9G45_MATRIX_H
+
+#ifndef __ASSEMBLY__
+
+struct at91_matrix {
+	u32	mcfg[16];
+	u32	scfg[16];
+	u32	pras[16][2];
+	u32	mrcr;           /* 0x100 Master Remap Control */
+	u32	filler[3];
+	u32	tcmr;
+	u32	filler2;
+	u32	ddrmpr;
+	u32	filler3[3];
+	u32	ebicsa;
+	u32	filler4[47];
+	u32	wpmr;
+	u32	wpsr;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define	AT91_MATRIX_ULBT_INFINITE	(0 << 0)
+#define	AT91_MATRIX_ULBT_SINGLE		(1 << 0)
+#define	AT91_MATRIX_ULBT_FOUR		(2 << 0)
+#define	AT91_MATRIX_ULBT_EIGHT		(3 << 0)
+#define	AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+#define	AT91_MATRIX_ULBT_THIRTYTWO	(5 << 0)
+#define	AT91_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
+#define	AT91_MATRIX_ULBT_128		(7 << 0)
+
+#define	AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
+#define	AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
+#define	AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+
+#define AT91_MATRIX_M0PR_SHIFT          0
+#define AT91_MATRIX_M1PR_SHIFT          4
+#define AT91_MATRIX_M2PR_SHIFT          8
+#define AT91_MATRIX_M3PR_SHIFT          12
+#define AT91_MATRIX_M4PR_SHIFT          16
+#define AT91_MATRIX_M5PR_SHIFT          20
+#define AT91_MATRIX_M6PR_SHIFT          24
+#define AT91_MATRIX_M7PR_SHIFT          28
+
+#define AT91_MATRIX_M8PR_SHIFT          0  /* register B */
+#define AT91_MATRIX_M9PR_SHIFT          4  /* register B */
+#define AT91_MATRIX_M10PR_SHIFT         8  /* register B */
+#define AT91_MATRIX_M11PR_SHIFT         12 /* register B */
+
+#define AT91_MATRIX_RCB0                (1 << 0)
+#define AT91_MATRIX_RCB1                (1 << 1)
+#define AT91_MATRIX_RCB2                (1 << 2)
+#define AT91_MATRIX_RCB3                (1 << 3)
+#define AT91_MATRIX_RCB4                (1 << 4)
+#define AT91_MATRIX_RCB5                (1 << 5)
+#define AT91_MATRIX_RCB6                (1 << 6)
+#define AT91_MATRIX_RCB7                (1 << 7)
+#define AT91_MATRIX_RCB8                (1 << 8)
+#define AT91_MATRIX_RCB9                (1 << 9)
+#define AT91_MATRIX_RCB10               (1 << 10)
+
+#define AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
+#define AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
+#define AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
+#define AT91_MATRIX_EBI_CS4A_SMC_CF0            (1 << 4)
+#define AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
+#define AT91_MATRIX_EBI_CS5A_SMC_CF1            (1 << 5)
+#define AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
+#define AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
+#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
+#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
+#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
+#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl.h
new file mode 100644
index 000000000..00b6aa469
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl.h
@@ -0,0 +1,131 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * Common definitions.
+ * Based on AT91SAM9RL datasheet revision A. (Preliminary)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef AT91SAM9RL_H
+#define AT91SAM9RL_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_ARM926EJS	/* ARM926EJS Core */
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS	1	/* System Peripherals */
+#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
+#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
+#define ATMEL_ID_PIOC	4	/* Parallel IO Controller C */
+#define ATMEL_ID_PIOD	5	/* Parallel IO Controller D */
+#define ATMEL_ID_USART0	6	/* USART 0 */
+#define ATMEL_ID_USART1	7	/* USART 1 */
+#define ATMEL_ID_USART2	8	/* USART 2 */
+#define ATMEL_ID_USART3	9	/* USART 3 */
+#define ATMEL_ID_MCI	10	/* Multimedia Card Interface */
+#define ATMEL_ID_TWI0	11	/* TWI 0 */
+#define ATMEL_ID_TWI1	12	/* TWI 1 */
+#define ATMEL_ID_SPI	13	/* Serial Peripheral Interface */
+#define ATMEL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1	15	/* Serial Synchronous Controller 1 */
+#define ATMEL_ID_TC0	16	/* Timer Counter 0 */
+#define ATMEL_ID_TC1	17	/* Timer Counter 1 */
+#define ATMEL_ID_TC2	18	/* Timer Counter 2 */
+#define ATMEL_ID_PWMC	19	/* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC	20	/* Touch Screen Controller */
+#define ATMEL_ID_DMA	21	/* DMA Controller */
+#define ATMEL_ID_UDPHS	22	/* USB Device HS */
+#define ATMEL_ID_LCDC	23	/* LCD Controller */
+#define ATMEL_ID_AC97C	24	/* AC97 Controller */
+#define ATMEL_ID_IRQ0	31	/* Advanced Interrupt Controller (IRQ0) */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define ATMEL_BASE_TCB0		0xfffa0000
+#define ATMEL_BASE_TC0		0xfffa0000
+#define ATMEL_BASE_TC1		0xfffa0040
+#define ATMEL_BASE_TC2		0xfffa0080
+#define ATMEL_BASE_MCI		0xfffa4000
+#define ATMEL_BASE_TWI0		0xfffa8000
+#define ATMEL_BASE_TWI1		0xfffac000
+#define ATMEL_BASE_USART0	0xfffb0000
+#define ATMEL_BASE_USART1	0xfffb4000
+#define ATMEL_BASE_USART2	0xfffb8000
+#define ATMEL_BASE_USART3	0xfffbc000
+#define ATMEL_BASE_SSC0		0xfffc0000
+#define ATMEL_BASE_SSC1		0xfffc4000
+#define ATMEL_BASE_PWMC		0xfffc8000
+#define ATMEL_BASE_SPI0		0xfffcc000
+#define ATMEL_BASE_TSC		0xfffd0000
+#define ATMEL_BASE_UDPHS	0xfffd4000
+#define ATMEL_BASE_AC97C	0xfffd8000
+#define ATMEL_BASE_SYS		0xffffc000
+
+/*
+ * System Peripherals
+ */
+#define ATMEL_BASE_DMA		0xffffe600
+#define ATMEL_BASE_ECC		0xffffe800
+#define ATMEL_BASE_SDRAMC	0xffffea00
+#define ATMEL_BASE_SMC		0xffffec00
+#define ATMEL_BASE_MATRIX	0xffffee00
+#define ATMEL_BASE_CCFG		0xffffef10
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_DBGU		0xfffff200
+#define ATMEL_BASE_PIOA		0xfffff400
+#define ATMEL_BASE_PIOB		0xfffff600
+#define ATMEL_BASE_PIOC		0xfffff800
+#define ATMEL_BASE_PIOD		0xfffffa00
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffd00
+#define ATMEL_BASE_SHDWC	0xfffffd10
+#define ATMEL_BASE_RTT		0xfffffd20
+#define ATMEL_BASE_PIT		0xfffffd30
+#define ATMEL_BASE_WDT		0xfffffd40
+#define ATMEL_BASE_SCKCR	0xfffffd50
+#define ATMEL_BASE_GPBR		0xfffffd60
+#define ATMEL_BASE_RTC		0xfffffe00
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_SRAM		0x00300000	/* Internal SRAM base address */
+#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM base address */
+
+#define ATMEL_BASE_LCDC		0x00500000	/* LCD Controller */
+#define ATMEL_UHP_BASE		0x00600000	/* USB Device HS controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000
+#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
+#define ATMEL_BASE_CS2		0x30000000
+#define ATMEL_BASE_CS3		0x40000000	/* NAND */
+#define ATMEL_BASE_CS4		0x50000000	/* Compact Flash Slot 0 */
+#define ATMEL_BASE_CS5		0x60000000	/* Compact Flash Slot 1 */
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS		4		/* this SoC has 4 PIO */
+#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
+
+/*
+ * Cpu Name
+ */
+#define ATMEL_CPU_NAME		"AT91SAM9RL"
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
new file mode 100644
index 000000000..295f768b5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
@@ -0,0 +1,61 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h]
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9RL datasheet revision A. (Preliminary)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef AT91SAM9RL_MATRIX_H
+#define AT91SAM9RL_MATRIX_H
+
+#ifndef __ASSEMBLY__
+
+struct at91_matrix {
+	u32	mcfg[16];	/* Master Configuration Registers */
+	u32	scfg[16];	/* Slave Configuration Registers */
+	u32	pras[16][2];	/* Priority Assignment Slave Registers */
+	u32	mrcr;		/* Master Remap Control Register */
+	u32	filler[7];
+	u32	ebicsa;		/* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
+#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT	18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
+
+#define AT91_MATRIX_M0PR_SHIFT		0
+#define AT91_MATRIX_M1PR_SHIFT		4
+#define AT91_MATRIX_M2PR_SHIFT		8
+#define AT91_MATRIX_M3PR_SHIFT		12
+#define AT91_MATRIX_M4PR_SHIFT		16
+#define AT91_MATRIX_M5PR_SHIFT		20
+
+#define AT91_MATRIX_RCB0		(1 << 0)
+#define AT91_MATRIX_RCB1		(1 << 1)
+
+#define AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
+#define AT91_MATRIX_DBPUC		(1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5.h
new file mode 100644
index 000000000..a47103851
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5.h
@@ -0,0 +1,182 @@
+/*
+ * Chip-specific header file for the AT91SAM9x5 family
+ *
+ *  Copyright (C) 2012-2013 Atmel Corporation.
+ *
+ * Definitions for the SoC:
+ * AT91SAM9x5 & AT91SAM9N12
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AT91SAM9X5_H__
+#define __AT91SAM9X5_H__
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS	1	/* System Controller Interrupt */
+#define ATMEL_ID_PIOAB	2	/* Parallel I/O Controller A and B */
+#define ATMEL_ID_PIOCD	3	/* Parallel I/O Controller C and D */
+#define ATMEL_ID_SMD	4	/* SMD Soft Modem (SMD), only for AT91SAM9X5 */
+#define ATMEL_ID_FUSE	4	/* FUSE Controller, only for AT91SAM9N12 */
+#define ATMEL_ID_USART0	5	/* USART 0 */
+#define ATMEL_ID_USART1	6	/* USART 1 */
+#define ATMEL_ID_USART2	7	/* USART 2 */
+#define ATMEL_ID_USART3	8	/* USART 3 */
+#define ATMEL_ID_TWI0	9	/* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1	10	/* Two-Wire Interface 1 */
+#define ATMEL_ID_TWI2	11	/* Two-Wire Interface 2 */
+#define ATMEL_ID_HSMCI0	12	/* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_SPI0	13	/* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1	14	/* Serial Peripheral Interface 1 */
+#define ATMEL_ID_UART0	15	/* UART 0 */
+#define ATMEL_ID_UART1	16	/* UART 1 */
+#define ATMEL_ID_TC01	17	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define ATMEL_ID_PWM	18	/* Pulse Width Modulation Controller */
+#define ATMEL_ID_ADC	19	/* ADC Controller */
+#define ATMEL_ID_DMAC0	20	/* DMA Controller 0 */
+#define ATMEL_ID_DMAC1	21	/* DMA Controller 1 */
+#define ATMEL_ID_UHPHS	22	/* USB Host High Speed */
+#define ATMEL_ID_UDPHS	23	/* USB Device High Speed */
+#define ATMEL_ID_EMAC0	24	/* Ethernet MAC0 */
+#define ATMEL_ID_LCDC	25	/* LCD Controller */
+#define ATMEL_ID_HSMCI1	26	/* High Speed Multimedia Card Interface 1 */
+#define ATMEL_ID_EMAC1	27	/* Ethernet MAC1 */
+#define ATMEL_ID_SSC	28	/* Synchronous Serial Controller */
+#define ATMEL_ID_TRNG	30	/* True Random Number Generator */
+#define ATMEL_ID_IRQ	31	/* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define ATMEL_BASE_SPI0		0xf0000000
+#define ATMEL_BASE_SPI1		0xf0004000
+#define ATMEL_BASE_HSMCI0	0xf0008000
+#define ATMEL_BASE_HSMCI1	0xf000c000
+#define ATMEL_BASE_SSC		0xf0010000
+#define ATMEL_BASE_CAN0		0xf8000000
+#define ATMEL_BASE_CAN1		0xf8004000
+#define ATMEL_BASE_TC0		0xf8008000
+#define ATMEL_BASE_TC1		0xf8008040
+#define ATMEL_BASE_TC2		0xf8008080
+#define ATMEL_BASE_TC3		0xf800c000
+#define ATMEL_BASE_TC4		0xf800c040
+#define ATMEL_BASE_TC5		0xf800c080
+#define ATMEL_BASE_TWI0		0xf8010000
+#define ATMEL_BASE_TWI1		0xf8014000
+#define ATMEL_BASE_TWI2		0xf8018000
+#define ATMEL_BASE_USART0	0xf801c000
+#define ATMEL_BASE_USART1	0xf8020000
+#define ATMEL_BASE_USART2	0xf8024000
+#define ATMEL_BASE_USART3	0xf8028000
+#define ATMEL_BASE_EMAC0	0xf802c000
+#define ATMEL_BASE_EMAC1	0xf8030000
+#define ATMEL_BASE_PWM		0xf8034000
+#define ATMEL_BASE_LCDC		0xf8038000
+#define ATMEL_BASE_UDPHS	0xf803c000
+#define ATMEL_BASE_UART0	0xf8040000
+#define ATMEL_BASE_UART1	0xf8044000
+#define ATMEL_BASE_ISI		0xf8048000
+#define ATMEL_BASE_ADC		0xf804c000
+#define ATMEL_BASE_SYS		0xffffc000
+
+/*
+ * System Peripherals
+ */
+#define ATMEL_BASE_FUSE		0xffffdc00
+#define ATMEL_BASE_MATRIX	0xffffde00
+#define ATMEL_BASE_PMECC	0xffffe000
+#define ATMEL_BASE_PMERRLOC	0xffffe600
+#define ATMEL_BASE_DDRSDRC	0xffffe800
+#define ATMEL_BASE_SMC		0xffffea00
+#define ATMEL_BASE_DMAC0	0xffffec00
+#define ATMEL_BASE_DMAC1	0xffffee00
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_DBGU		0xfffff200
+#define ATMEL_BASE_PIOA		0xfffff400
+#define ATMEL_BASE_PIOB		0xfffff600
+#define ATMEL_BASE_PIOC		0xfffff800
+#define ATMEL_BASE_PIOD		0xfffffa00
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffe00
+#define ATMEL_BASE_SHDWC	0xfffffe10
+#define ATMEL_BASE_PIT		0xfffffe30
+#define ATMEL_BASE_WDT		0xfffffe40
+#define ATMEL_BASE_GPBR		0xfffffe60
+#define ATMEL_BASE_RTC		0xfffffeb0
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_ROM		0x00100000 /* Internal ROM base address */
+#define ATMEL_BASE_SRAM		0x00300000 /* Internal SRAM base address */
+
+#ifdef CONFIG_AT91SAM9N12
+#define ATMEL_BASE_OHCI		0x00500000 /* USB Host controller */
+#else	/* AT91SAM9X5 */
+#define ATMEL_BASE_SMD		0x00400000 /* SMD Controller */
+#define ATMEL_BASE_UDPHS_FIFO	0x00500000 /* USB Device HS controller */
+#define ATMEL_BASE_OHCI		0x00600000 /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI		0x00700000 /* USB Host controller (EHCI) */
+#endif
+
+/* 9x5 series chip id definitions */
+#define ARCH_ID_AT91SAM9X5	0x819a05a0
+#define ARCH_ID_VERSION_MASK	0x1f
+#define ARCH_EXID_AT91SAM9G15	0x00000000
+#define ARCH_EXID_AT91SAM9G35	0x00000001
+#define ARCH_EXID_AT91SAM9X35	0x00000002
+#define ARCH_EXID_AT91SAM9G25	0x00000003
+#define ARCH_EXID_AT91SAM9X25	0x00000004
+
+#define cpu_is_at91sam9x5()	(get_chip_id() == ARCH_ID_AT91SAM9X5)
+#define cpu_is_at91sam9g15()	(cpu_is_at91sam9x5() && \
+			(get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
+#define cpu_is_at91sam9g25()	(cpu_is_at91sam9x5() && \
+			(get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
+#define cpu_is_at91sam9g35()	(cpu_is_at91sam9x5() && \
+			(get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
+#define cpu_is_at91sam9x25()	(cpu_is_at91sam9x5() && \
+			(get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
+#define cpu_is_at91sam9x35()	(cpu_is_at91sam9x5() && \
+			(get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
+
+/*
+ * Cpu Name
+ */
+#ifdef CONFIG_AT91SAM9N12
+#define ATMEL_CPU_NAME	"AT91SAM9N12"
+#else	/* AT91SAM9X5 */
+#define ATMEL_CPU_NAME	get_cpu_name()
+#endif
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS         4
+#define CPU_HAS_PIO3
+#define PIO_SCDR_DIV            (0x3fff <<  0)  /* Slow Clock Divider Mask */
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
+#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
+
+/*
+ * PMECC table in ROM
+ */
+#define ATMEL_PMECC_INDEX_OFFSET_512	0x8000
+#define ATMEL_PMECC_INDEX_OFFSET_1024	0x10000
+
+/*
+ * at91sam9x5 specific prototypes
+ */
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_emac1(void);
+unsigned int has_emac0(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
new file mode 100644
index 000000000..bd0b25adc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
@@ -0,0 +1,99 @@
+/*
+ * Matrix-centric header file for the AT91SAM9X5 family
+ *
+ *  Copyright (C) 2012-2013 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9X5 & AT91SAM9N12 preliminary datasheet.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AT91SAM9X5_MATRIX_H__
+#define __AT91SAM9X5_MATRIX_H__
+
+#ifndef __ASSEMBLY__
+
+/* AT91SAM9N12 Matrix definition is a subset of AT91SAM9X5. */
+struct at91_matrix {
+	u32	mcfg[16];
+	u32	scfg[16];
+	u32	pras[16][2];
+	u32	mrcr;           /* 0x100 Master Remap Control */
+	u32	filler[5];
+#ifdef CONFIG_AT91SAM9X5
+	u32	filler1[2];
+#endif
+	/* EBI Chip Select Assignment Register
+	 * 0x118: AT91SAM9N12
+	 * 0x120: AT91SAM9X5
+	 */
+	u32	ebicsa;
+	u32	filler4[47];
+#ifdef CONFIG_AT91SAM9N12
+	u32	filler5[2];
+#endif
+	u32	wpmr;
+	u32	wpsr;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
+#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+#define AT91_MATRIX_ULBT_THIRTYTWO	(5 << 0)
+#define AT91_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
+#define AT91_MATRIX_ULBT_128		(7 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+
+#define AT91_MATRIX_M0PR_SHIFT          0
+#define AT91_MATRIX_M1PR_SHIFT          4
+#define AT91_MATRIX_M2PR_SHIFT          8
+#define AT91_MATRIX_M3PR_SHIFT          12
+#define AT91_MATRIX_M4PR_SHIFT          16
+#define AT91_MATRIX_M5PR_SHIFT          20
+#define AT91_MATRIX_M6PR_SHIFT          24
+#define AT91_MATRIX_M7PR_SHIFT          28
+
+#define AT91_MATRIX_M8PR_SHIFT          0  /* register B */
+#define AT91_MATRIX_M9PR_SHIFT          4  /* register B */
+#define AT91_MATRIX_M10PR_SHIFT         8  /* register B */
+#define AT91_MATRIX_M11PR_SHIFT         12 /* register B */
+
+#define AT91_MATRIX_RCB0                (1 << 0)
+#define AT91_MATRIX_RCB1                (1 << 1)
+#define AT91_MATRIX_RCB2                (1 << 2)
+#define AT91_MATRIX_RCB3                (1 << 3)
+#define AT91_MATRIX_RCB4                (1 << 4)
+#define AT91_MATRIX_RCB5                (1 << 5)
+#define AT91_MATRIX_RCB6                (1 << 6)
+#define AT91_MATRIX_RCB7                (1 << 7)
+#define AT91_MATRIX_RCB8                (1 << 8)
+#define AT91_MATRIX_RCB9                (1 << 9)
+#define AT91_MATRIX_RCB10               (1 << 10)
+
+#define AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
+#define AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
+#define AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
+#define AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
+#define AT91_MATRIX_EBI_DBPD_ON                 (0 << 9)
+#define AT91_MATRIX_EBI_DBPD_OFF                (1 << 9)
+#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
+#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
+#define AT91_MATRIX_NFD0_ON_D0                  (0 << 24)
+#define AT91_MATRIX_NFD0_ON_D16                 (1 << 24)
+#define AT91_MATRIX_MP_OFF                      (0 << 25)
+#define AT91_MATRIX_MP_ON                       (1 << 25)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_mpddrc.h
new file mode 100644
index 000000000..5741f6e94
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_mpddrc.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ATMEL_MPDDRC_H__
+#define __ATMEL_MPDDRC_H__
+
+/*
+ * Only define the needed register in mpddr
+ * If other register needed, will add them later
+ */
+struct atmel_mpddr {
+	u32 mr;
+	u32 rtr;
+	u32 cr;
+	u32 tpr0;
+	u32 tpr1;
+	u32 tpr2;
+	u32 reserved[2];
+	u32 md;
+};
+
+int ddr2_init(const unsigned int ram_address,
+	       const struct atmel_mpddr *mpddr);
+
+/* Bit field in mode register */
+#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD		0x0
+#define ATMEL_MPDDRC_MR_MODE_NOP_CMD		0x1
+#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD	0x2
+#define ATMEL_MPDDRC_MR_MODE_LMR_CMD		0x3
+#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD		0x4
+#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD	0x5
+#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD		0x6
+#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD		0x7
+
+/* Bit field in configuration register */
+#define ATMEL_MPDDRC_CR_NC_MASK			0x3
+#define ATMEL_MPDDRC_CR_NC_COL_9		0x0
+#define ATMEL_MPDDRC_CR_NC_COL_10		0x1
+#define ATMEL_MPDDRC_CR_NC_COL_11		0x2
+#define ATMEL_MPDDRC_CR_NC_COL_12		0x3
+#define ATMEL_MPDDRC_CR_NR_MASK			(0x3 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_11		(0x0 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_12		(0x1 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_13		(0x2 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_14		(0x3 << 2)
+#define ATMEL_MPDDRC_CR_CAS_MASK		(0x7 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2		(0x2 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3		(0x3 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4		(0x4 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5		(0x5 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6		(0x6 << 4)
+#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED	(0x1 << 7)
+#define ATMEL_MPDDRC_CR_DIC_DS			(0x1 << 8)
+#define ATMEL_MPDDRC_CR_DIS_DLL			(0x1 << 9)
+#define ATMEL_MPDDRC_CR_OCD_DEFAULT		(0x7 << 12)
+#define ATMEL_MPDDRC_CR_ENRDM_ON		(0x1 << 17)
+#define ATMEL_MPDDRC_CR_NB_8BANKS		(0x1 << 20)
+#define ATMEL_MPDDRC_CR_NDQS_DISABLED		(0x1 << 21)
+#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED	(0x1 << 22)
+#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED		(0x1 << 23)
+
+/* Bit field in timing parameter 0 register */
+#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET		0
+#define ATMEL_MPDDRC_TPR0_TRAS_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET		4
+#define ATMEL_MPDDRC_TPR0_TRCD_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TWR_OFFSET		8
+#define ATMEL_MPDDRC_TPR0_TWR_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRC_OFFSET		12
+#define ATMEL_MPDDRC_TPR0_TRC_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRP_OFFSET		16
+#define ATMEL_MPDDRC_TPR0_TRP_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET		20
+#define ATMEL_MPDDRC_TPR0_TRRD_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET		24
+#define ATMEL_MPDDRC_TPR0_TWTR_MASK		0x7
+#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET	27
+#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK		0x1
+#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET		28
+#define ATMEL_MPDDRC_TPR0_TMRD_MASK		0xf
+
+/* Bit field in timing parameter 1 register */
+#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET		0
+#define ATMEL_MPDDRC_TPR1_TRFC_MASK		0x7f
+#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET		8
+#define ATMEL_MPDDRC_TPR1_TXSNR_MASK		0xff
+#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET		16
+#define ATMEL_MPDDRC_TPR1_TXSRD_MASK		0xff
+#define ATMEL_MPDDRC_TPR1_TXP_OFFSET		24
+#define ATMEL_MPDDRC_TPR1_TXP_MASK		0xf
+
+/* Bit field in timing parameter 2 register */
+#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET		0
+#define ATMEL_MPDDRC_TPR2_TXARD_MASK		0xf
+#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET		4
+#define ATMEL_MPDDRC_TPR2_TXARDS_MASK		0xf
+#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET		8
+#define ATMEL_MPDDRC_TPR2_TRPA_MASK		0xf
+#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET		12
+#define ATMEL_MPDDRC_TPR2_TRTP_MASK		0x7
+#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET		16
+#define ATMEL_MPDDRC_TPR2_TFAW_MASK		0xf
+
+/* Bit field in Memory Device Register */
+#define ATMEL_MPDDRC_MD_LPDDR_SDRAM	0x3
+#define ATMEL_MPDDRC_MD_DDR2_SDRAM	0x6
+#define ATMEL_MPDDRC_MD_DBW_MASK	(0x1 << 4)
+#define ATMEL_MPDDRC_MD_DBW_32_BITS	(0x0 << 4)
+#define ATMEL_MPDDRC_MD_DBW_16_BITS	(0x1 << 4)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_usba_udc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
new file mode 100644
index 000000000..6f540d23a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2005-2013 Atmel Corporation
+ *			   Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ATMEL_USBA_UDC_H__
+#define __ATMEL_USBA_UDC_H__
+
+#include <linux/usb/atmel_usba_udc.h>
+
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc)		\
+	[idx] = {					\
+		.name	= nam,				\
+		.index	= idx,				\
+		.fifo_size	= maxpkt,		\
+		.nr_banks	= maxbk,		\
+		.can_dma	= dma,			\
+		.can_isoc	= isoc,			\
+	}
+
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
+	defined(CONFIG_AT91SAM9X5)
+static struct usba_ep_data usba_udc_ep[] = {
+	EP("ep0", 0, 64, 1, 0, 0),
+	EP("ep1", 1, 1024, 2, 1, 1),
+	EP("ep2", 2, 1024, 2, 1, 1),
+	EP("ep3", 3, 1024, 3, 1, 0),
+	EP("ep4", 4, 1024, 3, 1, 0),
+	EP("ep5", 5, 1024, 3, 1, 1),
+	EP("ep6", 6, 1024, 3, 1, 1),
+};
+#elif defined(CONFIG_SAMA5D3)
+static struct usba_ep_data usba_udc_ep[] = {
+	EP("ep0", 0, 64, 1, 0, 0),
+	EP("ep1", 1, 1024, 3, 1, 0),
+	EP("ep2", 2, 1024, 3, 1, 0),
+	EP("ep3", 3, 1024, 2, 1, 0),
+	EP("ep4", 4, 1024, 2, 1, 0),
+	EP("ep5", 5, 1024, 2, 1, 0),
+	EP("ep6", 6, 1024, 2, 1, 0),
+	EP("ep7", 7, 1024, 2, 1, 0),
+	EP("ep8", 8, 1024, 2, 0, 0),
+	EP("ep9", 9, 1024, 2, 0, 0),
+	EP("ep10", 10, 1024, 2, 0, 0),
+	EP("ep11", 11, 1024, 2, 0, 0),
+	EP("ep12", 12, 1024, 2, 0, 0),
+	EP("ep13", 13, 1024, 2, 0, 0),
+	EP("ep14", 14, 1024, 2, 0, 0),
+	EP("ep15", 15, 1024, 2, 0, 0),
+};
+#else
+# error "NO usba_udc_ep defined"
+#endif
+
+#undef EP
+
+struct usba_platform_data pdata = {
+	.num_ep	= ARRAY_SIZE(usba_udc_ep),
+	.ep	= usba_udc_ep,
+};
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/clk.h
new file mode 100644
index 000000000..ce9e28f11
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/clk.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARM_ARCH_CLK_H__
+#define __ASM_ARM_ARCH_CLK_H__
+
+#include <asm/arch/hardware.h>
+#include <asm/global_data.h>
+
+static inline unsigned long get_cpu_clk_rate(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	return gd->arch.cpu_clk_rate_hz;
+}
+
+static inline unsigned long get_main_clk_rate(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	return gd->arch.main_clk_rate_hz;
+}
+
+static inline unsigned long get_mck_clk_rate(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	return gd->arch.mck_rate_hz;
+}
+
+static inline unsigned long get_plla_clk_rate(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	return gd->arch.plla_rate_hz;
+}
+
+static inline unsigned long get_pllb_clk_rate(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	return gd->arch.pllb_rate_hz;
+}
+
+static inline u32 get_pllb_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	return gd->arch.at91_pllb_usb_init;
+}
+
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+	return get_mck_clk_rate();
+}
+
+static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
+{
+	return get_mck_clk_rate();
+}
+
+static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
+{
+	return get_mck_clk_rate();
+}
+
+static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
+{
+	return get_mck_clk_rate();
+}
+
+static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
+{
+	return get_mck_clk_rate();
+}
+
+static inline unsigned long get_mci_clk_rate(void)
+{
+	return get_mck_clk_rate();
+}
+
+int at91_clock_init(unsigned long main_clock);
+void at91_periph_clk_enable(int id);
+#endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/gpio.h
new file mode 100644
index 000000000..71213883d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/gpio.h
@@ -0,0 +1,256 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h]
+ *
+ *  Copyright (C) 2005 HP Labs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_AT91_GPIO_H
+#define __ASM_ARCH_AT91_GPIO_H
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_ATMEL_LEGACY
+
+#define PIN_BASE		0
+
+#define MAX_GPIO_BANKS		5
+
+/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
+
+#define	AT91_PIN_PA0	(PIN_BASE + 0x00 + 0)
+#define	AT91_PIN_PA1	(PIN_BASE + 0x00 + 1)
+#define	AT91_PIN_PA2	(PIN_BASE + 0x00 + 2)
+#define	AT91_PIN_PA3	(PIN_BASE + 0x00 + 3)
+#define	AT91_PIN_PA4	(PIN_BASE + 0x00 + 4)
+#define	AT91_PIN_PA5	(PIN_BASE + 0x00 + 5)
+#define	AT91_PIN_PA6	(PIN_BASE + 0x00 + 6)
+#define	AT91_PIN_PA7	(PIN_BASE + 0x00 + 7)
+#define	AT91_PIN_PA8	(PIN_BASE + 0x00 + 8)
+#define	AT91_PIN_PA9	(PIN_BASE + 0x00 + 9)
+#define	AT91_PIN_PA10	(PIN_BASE + 0x00 + 10)
+#define	AT91_PIN_PA11	(PIN_BASE + 0x00 + 11)
+#define	AT91_PIN_PA12	(PIN_BASE + 0x00 + 12)
+#define	AT91_PIN_PA13	(PIN_BASE + 0x00 + 13)
+#define	AT91_PIN_PA14	(PIN_BASE + 0x00 + 14)
+#define	AT91_PIN_PA15	(PIN_BASE + 0x00 + 15)
+#define	AT91_PIN_PA16	(PIN_BASE + 0x00 + 16)
+#define	AT91_PIN_PA17	(PIN_BASE + 0x00 + 17)
+#define	AT91_PIN_PA18	(PIN_BASE + 0x00 + 18)
+#define	AT91_PIN_PA19	(PIN_BASE + 0x00 + 19)
+#define	AT91_PIN_PA20	(PIN_BASE + 0x00 + 20)
+#define	AT91_PIN_PA21	(PIN_BASE + 0x00 + 21)
+#define	AT91_PIN_PA22	(PIN_BASE + 0x00 + 22)
+#define	AT91_PIN_PA23	(PIN_BASE + 0x00 + 23)
+#define	AT91_PIN_PA24	(PIN_BASE + 0x00 + 24)
+#define	AT91_PIN_PA25	(PIN_BASE + 0x00 + 25)
+#define	AT91_PIN_PA26	(PIN_BASE + 0x00 + 26)
+#define	AT91_PIN_PA27	(PIN_BASE + 0x00 + 27)
+#define	AT91_PIN_PA28	(PIN_BASE + 0x00 + 28)
+#define	AT91_PIN_PA29	(PIN_BASE + 0x00 + 29)
+#define	AT91_PIN_PA30	(PIN_BASE + 0x00 + 30)
+#define	AT91_PIN_PA31	(PIN_BASE + 0x00 + 31)
+
+#define	AT91_PIN_PB0	(PIN_BASE + 0x20 + 0)
+#define	AT91_PIN_PB1	(PIN_BASE + 0x20 + 1)
+#define	AT91_PIN_PB2	(PIN_BASE + 0x20 + 2)
+#define	AT91_PIN_PB3	(PIN_BASE + 0x20 + 3)
+#define	AT91_PIN_PB4	(PIN_BASE + 0x20 + 4)
+#define	AT91_PIN_PB5	(PIN_BASE + 0x20 + 5)
+#define	AT91_PIN_PB6	(PIN_BASE + 0x20 + 6)
+#define	AT91_PIN_PB7	(PIN_BASE + 0x20 + 7)
+#define	AT91_PIN_PB8	(PIN_BASE + 0x20 + 8)
+#define	AT91_PIN_PB9	(PIN_BASE + 0x20 + 9)
+#define	AT91_PIN_PB10	(PIN_BASE + 0x20 + 10)
+#define	AT91_PIN_PB11	(PIN_BASE + 0x20 + 11)
+#define	AT91_PIN_PB12	(PIN_BASE + 0x20 + 12)
+#define	AT91_PIN_PB13	(PIN_BASE + 0x20 + 13)
+#define	AT91_PIN_PB14	(PIN_BASE + 0x20 + 14)
+#define	AT91_PIN_PB15	(PIN_BASE + 0x20 + 15)
+#define	AT91_PIN_PB16	(PIN_BASE + 0x20 + 16)
+#define	AT91_PIN_PB17	(PIN_BASE + 0x20 + 17)
+#define	AT91_PIN_PB18	(PIN_BASE + 0x20 + 18)
+#define	AT91_PIN_PB19	(PIN_BASE + 0x20 + 19)
+#define	AT91_PIN_PB20	(PIN_BASE + 0x20 + 20)
+#define	AT91_PIN_PB21	(PIN_BASE + 0x20 + 21)
+#define	AT91_PIN_PB22	(PIN_BASE + 0x20 + 22)
+#define	AT91_PIN_PB23	(PIN_BASE + 0x20 + 23)
+#define	AT91_PIN_PB24	(PIN_BASE + 0x20 + 24)
+#define	AT91_PIN_PB25	(PIN_BASE + 0x20 + 25)
+#define	AT91_PIN_PB26	(PIN_BASE + 0x20 + 26)
+#define	AT91_PIN_PB27	(PIN_BASE + 0x20 + 27)
+#define	AT91_PIN_PB28	(PIN_BASE + 0x20 + 28)
+#define	AT91_PIN_PB29	(PIN_BASE + 0x20 + 29)
+#define	AT91_PIN_PB30	(PIN_BASE + 0x20 + 30)
+#define	AT91_PIN_PB31	(PIN_BASE + 0x20 + 31)
+
+#define	AT91_PIN_PC0	(PIN_BASE + 0x40 + 0)
+#define	AT91_PIN_PC1	(PIN_BASE + 0x40 + 1)
+#define	AT91_PIN_PC2	(PIN_BASE + 0x40 + 2)
+#define	AT91_PIN_PC3	(PIN_BASE + 0x40 + 3)
+#define	AT91_PIN_PC4	(PIN_BASE + 0x40 + 4)
+#define	AT91_PIN_PC5	(PIN_BASE + 0x40 + 5)
+#define	AT91_PIN_PC6	(PIN_BASE + 0x40 + 6)
+#define	AT91_PIN_PC7	(PIN_BASE + 0x40 + 7)
+#define	AT91_PIN_PC8	(PIN_BASE + 0x40 + 8)
+#define	AT91_PIN_PC9	(PIN_BASE + 0x40 + 9)
+#define	AT91_PIN_PC10	(PIN_BASE + 0x40 + 10)
+#define	AT91_PIN_PC11	(PIN_BASE + 0x40 + 11)
+#define	AT91_PIN_PC12	(PIN_BASE + 0x40 + 12)
+#define	AT91_PIN_PC13	(PIN_BASE + 0x40 + 13)
+#define	AT91_PIN_PC14	(PIN_BASE + 0x40 + 14)
+#define	AT91_PIN_PC15	(PIN_BASE + 0x40 + 15)
+#define	AT91_PIN_PC16	(PIN_BASE + 0x40 + 16)
+#define	AT91_PIN_PC17	(PIN_BASE + 0x40 + 17)
+#define	AT91_PIN_PC18	(PIN_BASE + 0x40 + 18)
+#define	AT91_PIN_PC19	(PIN_BASE + 0x40 + 19)
+#define	AT91_PIN_PC20	(PIN_BASE + 0x40 + 20)
+#define	AT91_PIN_PC21	(PIN_BASE + 0x40 + 21)
+#define	AT91_PIN_PC22	(PIN_BASE + 0x40 + 22)
+#define	AT91_PIN_PC23	(PIN_BASE + 0x40 + 23)
+#define	AT91_PIN_PC24	(PIN_BASE + 0x40 + 24)
+#define	AT91_PIN_PC25	(PIN_BASE + 0x40 + 25)
+#define	AT91_PIN_PC26	(PIN_BASE + 0x40 + 26)
+#define	AT91_PIN_PC27	(PIN_BASE + 0x40 + 27)
+#define	AT91_PIN_PC28	(PIN_BASE + 0x40 + 28)
+#define	AT91_PIN_PC29	(PIN_BASE + 0x40 + 29)
+#define	AT91_PIN_PC30	(PIN_BASE + 0x40 + 30)
+#define	AT91_PIN_PC31	(PIN_BASE + 0x40 + 31)
+
+#define	AT91_PIN_PD0	(PIN_BASE + 0x60 + 0)
+#define	AT91_PIN_PD1	(PIN_BASE + 0x60 + 1)
+#define	AT91_PIN_PD2	(PIN_BASE + 0x60 + 2)
+#define	AT91_PIN_PD3	(PIN_BASE + 0x60 + 3)
+#define	AT91_PIN_PD4	(PIN_BASE + 0x60 + 4)
+#define	AT91_PIN_PD5	(PIN_BASE + 0x60 + 5)
+#define	AT91_PIN_PD6	(PIN_BASE + 0x60 + 6)
+#define	AT91_PIN_PD7	(PIN_BASE + 0x60 + 7)
+#define	AT91_PIN_PD8	(PIN_BASE + 0x60 + 8)
+#define	AT91_PIN_PD9	(PIN_BASE + 0x60 + 9)
+#define	AT91_PIN_PD10	(PIN_BASE + 0x60 + 10)
+#define	AT91_PIN_PD11	(PIN_BASE + 0x60 + 11)
+#define	AT91_PIN_PD12	(PIN_BASE + 0x60 + 12)
+#define	AT91_PIN_PD13	(PIN_BASE + 0x60 + 13)
+#define	AT91_PIN_PD14	(PIN_BASE + 0x60 + 14)
+#define	AT91_PIN_PD15	(PIN_BASE + 0x60 + 15)
+#define	AT91_PIN_PD16	(PIN_BASE + 0x60 + 16)
+#define	AT91_PIN_PD17	(PIN_BASE + 0x60 + 17)
+#define	AT91_PIN_PD18	(PIN_BASE + 0x60 + 18)
+#define	AT91_PIN_PD19	(PIN_BASE + 0x60 + 19)
+#define	AT91_PIN_PD20	(PIN_BASE + 0x60 + 20)
+#define	AT91_PIN_PD21	(PIN_BASE + 0x60 + 21)
+#define	AT91_PIN_PD22	(PIN_BASE + 0x60 + 22)
+#define	AT91_PIN_PD23	(PIN_BASE + 0x60 + 23)
+#define	AT91_PIN_PD24	(PIN_BASE + 0x60 + 24)
+#define	AT91_PIN_PD25	(PIN_BASE + 0x60 + 25)
+#define	AT91_PIN_PD26	(PIN_BASE + 0x60 + 26)
+#define	AT91_PIN_PD27	(PIN_BASE + 0x60 + 27)
+#define	AT91_PIN_PD28	(PIN_BASE + 0x60 + 28)
+#define	AT91_PIN_PD29	(PIN_BASE + 0x60 + 29)
+#define	AT91_PIN_PD30	(PIN_BASE + 0x60 + 30)
+#define	AT91_PIN_PD31	(PIN_BASE + 0x60 + 31)
+
+#define	AT91_PIN_PE0	(PIN_BASE + 0x80 + 0)
+#define	AT91_PIN_PE1	(PIN_BASE + 0x80 + 1)
+#define	AT91_PIN_PE2	(PIN_BASE + 0x80 + 2)
+#define	AT91_PIN_PE3	(PIN_BASE + 0x80 + 3)
+#define	AT91_PIN_PE4	(PIN_BASE + 0x80 + 4)
+#define	AT91_PIN_PE5	(PIN_BASE + 0x80 + 5)
+#define	AT91_PIN_PE6	(PIN_BASE + 0x80 + 6)
+#define	AT91_PIN_PE7	(PIN_BASE + 0x80 + 7)
+#define	AT91_PIN_PE8	(PIN_BASE + 0x80 + 8)
+#define	AT91_PIN_PE9	(PIN_BASE + 0x80 + 9)
+#define	AT91_PIN_PE10	(PIN_BASE + 0x80 + 10)
+#define	AT91_PIN_PE11	(PIN_BASE + 0x80 + 11)
+#define	AT91_PIN_PE12	(PIN_BASE + 0x80 + 12)
+#define	AT91_PIN_PE13	(PIN_BASE + 0x80 + 13)
+#define	AT91_PIN_PE14	(PIN_BASE + 0x80 + 14)
+#define	AT91_PIN_PE15	(PIN_BASE + 0x80 + 15)
+#define	AT91_PIN_PE16	(PIN_BASE + 0x80 + 16)
+#define	AT91_PIN_PE17	(PIN_BASE + 0x80 + 17)
+#define	AT91_PIN_PE18	(PIN_BASE + 0x80 + 18)
+#define	AT91_PIN_PE19	(PIN_BASE + 0x80 + 19)
+#define	AT91_PIN_PE20	(PIN_BASE + 0x80 + 20)
+#define	AT91_PIN_PE21	(PIN_BASE + 0x80 + 21)
+#define	AT91_PIN_PE22	(PIN_BASE + 0x80 + 22)
+#define	AT91_PIN_PE23	(PIN_BASE + 0x80 + 23)
+#define	AT91_PIN_PE24	(PIN_BASE + 0x80 + 24)
+#define	AT91_PIN_PE25	(PIN_BASE + 0x80 + 25)
+#define	AT91_PIN_PE26	(PIN_BASE + 0x80 + 26)
+#define	AT91_PIN_PE27	(PIN_BASE + 0x80 + 27)
+#define	AT91_PIN_PE28	(PIN_BASE + 0x80 + 28)
+#define	AT91_PIN_PE29	(PIN_BASE + 0x80 + 29)
+#define	AT91_PIN_PE30	(PIN_BASE + 0x80 + 30)
+#define	AT91_PIN_PE31	(PIN_BASE + 0x80 + 31)
+
+static unsigned long at91_pios[] = {
+	ATMEL_BASE_PIOA,
+	ATMEL_BASE_PIOB,
+	ATMEL_BASE_PIOC,
+#ifdef ATMEL_BASE_PIOD
+	ATMEL_BASE_PIOD,
+#ifdef ATMEL_BASE_PIOE
+	ATMEL_BASE_PIOE
+#endif
+#endif
+};
+
+static inline void *pin_to_controller(unsigned pin)
+{
+	pin -= PIN_BASE;
+	pin /= 32;
+	return (void *)(at91_pios[pin]);
+}
+
+static inline unsigned pin_to_mask(unsigned pin)
+{
+	pin -= PIN_BASE;
+	return 1 << (pin % 32);
+}
+
+/* The following macros are need for backward compatibility */
+#define at91_set_GPIO_periph(x, y) \
+	at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_A_periph(x, y) \
+	at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_B_periph(x, y) \
+	at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_output(x, y) \
+	at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_input(x, y) \
+	at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_value(x, y) \
+	at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_get_gpio_value(x) \
+	at91_get_pio_value((x - PIN_BASE) / 32,(x % 32))
+#else
+#define at91_set_gpio_value(x, y)	at91_set_pio_value(x, y)
+#define at91_get_gpio_value(x)		at91_get_pio_value(x)
+#endif
+
+#define GPIO_PIOA_BASE  (0)
+#define GPIO_PIOB_BASE  (GPIO_PIOA_BASE + 32)
+#define GPIO_PIOC_BASE  (GPIO_PIOB_BASE + 32)
+#define GPIO_PIOD_BASE  (GPIO_PIOC_BASE + 32)
+#define GPIO_PIOE_BASE  (GPIO_PIOD_BASE + 32)
+#define GPIO_PIN_PA(x)  (GPIO_PIOA_BASE + (x))
+#define GPIO_PIN_PB(x)  (GPIO_PIOB_BASE + (x))
+#define GPIO_PIN_PC(x)  (GPIO_PIOC_BASE + (x))
+#define GPIO_PIN_PD(x)  (GPIO_PIOD_BASE + (x))
+#define GPIO_PIN_PE(x)  (GPIO_PIOE_BASE + (x))
+
+static inline unsigned at91_gpio_to_port(unsigned gpio)
+{
+	return gpio / 32;
+}
+
+static inline unsigned at91_gpio_to_pin(unsigned gpio)
+{
+	return gpio % 32;
+}
+
+#endif /* __ASM_ARCH_AT91_GPIO_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/hardware.h
new file mode 100644
index 000000000..a63f97406
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/hardware.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARM_ARCH_HARDWARE_H__
+#define __ASM_ARM_ARCH_HARDWARE_H__
+
+#if defined(CONFIG_AT91RM9200)
+# include <asm/arch/at91rm9200.h>
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) || \
+	defined(CONFIG_AT91SAM9XE)
+# include <asm/arch/at91sam9260.h>
+#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
+# include <asm/arch/at91sam9261.h>
+#elif defined(CONFIG_AT91SAM9263)
+# include <asm/arch/at91sam9263.h>
+#elif defined(CONFIG_AT91SAM9RL)
+# include <asm/arch/at91sam9rl.h>
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+# include <asm/arch/at91sam9g45.h>
+#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
+# include <asm/arch/at91sam9x5.h>
+#elif defined(CONFIG_AT91CAP9)
+# include <asm/arch/at91cap9.h>
+#elif defined(CONFIG_AT91X40)
+# include <asm/arch/at91x40.h>
+#elif defined(CONFIG_SAMA5D3)
+# include <asm/arch/sama5d3.h>
+#else
+# error "Unsupported AT91 processor"
+#endif
+
+#endif /* __ASM_ARM_ARCH_HARDWARE_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3.h
new file mode 100644
index 000000000..6d936f47f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3.h
@@ -0,0 +1,210 @@
+/*
+ * Chip-specific header file for the SAMA5D3 family
+ *
+ * (C) 2012 - 2013 Atmel Corporation.
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * Definitions for the SoC:
+ * SAMA5D3
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef SAMA5D3_H
+#define SAMA5D3_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_ARMV7		/* ARM A5 Core */
+#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS	1	/* System Controller Interrupt */
+#define ATMEL_ID_DBGU	2	/* Debug Unit Interrupt */
+#define ATMEL_ID_PIT	3	/* Periodic Interval Timer Interrupt */
+#define ATMEL_ID_WDT	4	/* Watchdog timer Interrupt */
+#define ATMEL_ID_SMC	5	/* Multi-bit ECC Interrupt */
+#define ATMEL_ID_PIOA	6	/* Parallel I/O Controller A */
+#define ATMEL_ID_PIOB	7	/* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC	8	/* Parallel I/O Controller C */
+#define ATMEL_ID_PIOD	9	/* Parallel I/O Controller D */
+#define ATMEL_ID_PIOE	10	/* Parallel I/O Controller E */
+#define ATMEL_ID_SMD	11	/* SMD Soft Modem */
+#define ATMEL_ID_USART0	12	/* USART 0 */
+#define ATMEL_ID_USART1	13	/* USART 1 */
+#define ATMEL_ID_USART2	14	/* USART 2 */
+#define ATMEL_ID_USART3	15	/* USART 3 */
+#define ATMEL_ID_UART0	16
+#define ATMEL_ID_UART1	17
+#define ATMEL_ID_TWI0	18	/* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1	19	/* Two-Wire Interface 1 */
+#define ATMEL_ID_TWI2	20	/* Two-Wire Interface 2 */
+#define ATMEL_ID_MCI0	21	/* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_MCI1	22	/*  */
+#define ATMEL_ID_MCI2	23	/*  */
+#define ATMEL_ID_SPI0	24	/* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1	25	/* Serial Peripheral Interface 1 */
+#define ATMEL_ID_TC0	26	/* */
+#define ATMEL_ID_TC1	27	/* */
+#define ATMEL_ID_PWMC	28	/* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC	29	/* Touch Screen ADC Controller */
+#define ATMEL_ID_DMA0	30	/* DMA Controller */
+#define ATMEL_ID_DMA1	31	/* DMA Controller */
+#define ATMEL_ID_UHPHS	32	/* USB Host High Speed */
+#define ATMEL_ID_UDPHS	33	/* USB Device High Speed */
+#define ATMEL_ID_GMAC	34
+#define ATMEL_ID_EMAC	35	/* Ethernet MAC */
+#define ATMEL_ID_LCDC	36	/* LCD Controller */
+#define ATMEL_ID_ISI	37	/* Image Sensor Interface */
+#define ATMEL_ID_SSC0	38	/* Synchronous Serial Controller 0 */
+#define ATMEL_ID_SSC1	39	/* Synchronous Serial Controller 1 */
+#define ATMEL_ID_CAN0	40
+#define ATMEL_ID_CAN1	41
+#define ATMEL_ID_SHA	42
+#define ATMEL_ID_AES	43
+#define ATMEL_ID_TDES	44
+#define ATMEL_ID_TRNG	45
+#define ATMEL_ID_ARM	46
+#define ATMEL_ID_IRQ0	47	/* Advanced Interrupt Controller */
+#define ATMEL_ID_FUSE	48
+#define ATMEL_ID_MPDDRC	49
+
+/* sama5d3 series chip id definitions */
+#define ARCH_ID_SAMA5D3		0x8a5c07c0
+#define ARCH_EXID_SAMA5D31	0x00444300
+#define ARCH_EXID_SAMA5D33	0x00414300
+#define ARCH_EXID_SAMA5D34	0x00414301
+#define ARCH_EXID_SAMA5D35	0x00584300
+#define ARCH_EXID_SAMA5D36	0x00004301
+
+#define cpu_is_sama5d3()	(get_chip_id() == ARCH_ID_SAMA5D3)
+#define cpu_is_sama5d31()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D31))
+#define cpu_is_sama5d33()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D33))
+#define cpu_is_sama5d34()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D34))
+#define cpu_is_sama5d35()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D35))
+#define cpu_is_sama5d36()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D36))
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_MCI0		0xf0000000
+#define ATMEL_BASE_SPI0		0xf0004000
+#define ATMEL_BASE_SSC0		0xf000C000
+#define ATMEL_BASE_TC2		0xf0010000
+#define ATMEL_BASE_TWI0		0xf0014000
+#define ATMEL_BASE_TWI1		0xf0018000
+#define ATMEL_BASE_USART0	0xf001c000
+#define ATMEL_BASE_USART1	0xf0020000
+#define ATMEL_BASE_UART0	0xf0024000
+#define ATMEL_BASE_GMAC		0xf0028000
+#define ATMEL_BASE_PWMC		0xf002c000
+#define ATMEL_BASE_LCDC		0xf0030000
+#define ATMEL_BASE_ISI		0xf0034000
+#define ATMEL_BASE_SFR		0xf0038000
+/* Reserved: 0xf003c000 - 0xf8000000 */
+#define ATMEL_BASE_MCI1		0xf8000000
+#define ATMEL_BASE_MCI2		0xf8004000
+#define ATMEL_BASE_SPI1		0xf8008000
+#define ATMEL_BASE_SSC1		0xf800c000
+#define ATMEL_BASE_CAN1		0xf8010000
+#define ATMEL_BASE_TC3		0xf8014000
+#define ATMEL_BASE_TSADC	0xf8018000
+#define ATMEL_BASE_TWI2		0xf801c000
+#define ATMEL_BASE_USART2	0xf8020000
+#define ATMEL_BASE_USART3	0xf8024000
+#define ATMEL_BASE_UART1	0xf8028000
+#define ATMEL_BASE_EMAC		0xf802c000
+#define ATMEL_BASE_UDPHS	0xf8030000
+#define ATMEL_BASE_SHA		0xf8034000
+#define ATMEL_BASE_AES		0xf8038000
+#define ATMEL_BASE_TDES		0xf803c000
+#define ATMEL_BASE_TRNG		0xf8040000
+/* Reserved:	0xf804400 - 0xffffc00 */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS		0xffffc000
+#define ATMEL_BASE_SMC		0xffffc000
+#define ATMEL_BASE_PMECC	(ATMEL_BASE_SMC + 0x070)
+#define ATMEL_BASE_PMERRLOC	(ATMEL_BASE_SMC + 0x500)
+#define ATMEL_BASE_FUSE		0xffffe400
+#define ATMEL_BASE_DMAC0	0xffffe600
+#define ATMEL_BASE_DMAC1	0xffffe800
+#define ATMEL_BASE_MPDDRC	0xffffea00
+#define ATMEL_BASE_MATRIX	0xffffec00
+#define ATMEL_BASE_DBGU		0xffffee00
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_PIOA		0xfffff200
+#define ATMEL_BASE_PIOB		0xfffff400
+#define ATMEL_BASE_PIOC		0xfffff600
+#define ATMEL_BASE_PIOD		0xfffff800
+#define ATMEL_BASE_PIOE		0xfffffa00
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffe00
+#define ATMEL_BASE_SHDWN	0xfffffe10
+#define ATMEL_BASE_PIT		0xfffffe30
+#define ATMEL_BASE_WDT		0xfffffe40
+#define ATMEL_BASE_SCKCR	0xfffffe50
+#define ATMEL_BASE_GPBR		0xfffffe60
+#define ATMEL_BASE_RTC		0xfffffeb0
+/* Reserved:	0xfffffee0 - 0xffffffff */
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_ROM		0x00100000	/* Internal ROM base address */
+#define ATMEL_BASE_SRAM		0x00200000	/* Internal ROM base address */
+#define ATMEL_BASE_SRAM0	0x00300000	/* Internal SRAM base address */
+#define ATMEL_BASE_SRAM1	0x00310000	/* Internal SRAM base address */
+#define ATMEL_BASE_SMD		0x00400000	/* Internal ROM base address */
+#define ATMEL_BASE_UDPHS_FIFO	0x00500000	/* USB Device HS controller */
+#define ATMEL_BASE_OHCI		0x00600000	/* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI		0x00700000	/* USB Host controller (EHCI) */
+#define ATMEL_BASE_AXI		0x00800000	/* Video Decoder Controller */
+#define ATMEL_BASE_DAP		0x00900000	/* Video Decoder Controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0		0x10000000
+#define ATMEL_BASE_DDRCS	0x20000000
+#define ATMEL_BASE_CS1		0x40000000
+#define ATMEL_BASE_CS2		0x50000000
+#define ATMEL_BASE_CS3		0x60000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS		5
+#define CPU_HAS_PIO3
+#define PIO_SCDR_DIV		0x3fff
+
+/*
+ * PMECC table in ROM
+ */
+#define ATMEL_PMECC_INDEX_OFFSET_512	0x10000
+#define ATMEL_PMECC_INDEX_OFFSET_1024	0x18000
+
+/*
+ * SAMA5D3 specific prototypes
+ */
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_emac(void);
+unsigned int has_gmac(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3_smc.h
new file mode 100644
index 000000000..6caa9b6ed
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/sama5d3_smc.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on SAMA5D3 datasheet.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef SAMA5D3_SMC_H
+#define SAMA5D3_SMC_H
+
+#ifdef __ASSEMBLY__
+#define AT91_ASM_SMC_SETUP0	(ATMEL_BASE_SMC + 0x600)
+#define AT91_ASM_SMC_PULSE0	(ATMEL_BASE_SMC + 0x604)
+#define AT91_ASM_SMC_CYCLE0	(ATMEL_BASE_SMC + 0x608)
+#define AT91_ASM_SMC_MODE0	(ATMEL_BASE_SMC + 0x60C)
+#else
+struct at91_cs {
+	u32	setup;		/* 0x600 SMC Setup Register */
+	u32	pulse;		/* 0x604 SMC Pulse Register */
+	u32	cycle;		/* 0x608 SMC Cycle Register */
+	u32	timings;	/* 0x60C SMC Cycle Register */
+	u32	mode;		/* 0x610 SMC Mode Register */
+};
+
+struct at91_smc {
+	u32 reserved[384];
+	struct at91_cs cs[4];
+};
+#endif /*  __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x)		(x & 0x3f)
+#define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x3f) << 8)
+#define AT91_SMC_PULSE_NRD(x)		((x & 0x3f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x3f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)
+
+#define AT91_SMC_TIMINGS_TCLR(x)	(x & 0xf)
+#define AT91_SMC_TIMINGS_TADL(x)	((x & 0xf) << 4)
+#define AT91_SMC_TIMINGS_TAR(x)		((x & 0xf) << 8)
+#define AT91_SMC_TIMINGS_OCMS(x)	((x & 0x1) << 12)
+#define AT91_SMC_TIMINGS_TRR(x)		((x & 0xf) << 16)
+#define AT91_SMC_TIMINGS_TWB(x)		((x & 0xf) << 24)
+#define AT91_SMC_TIMINGS_RBNSEL(x)	((x & 0xf) << 28)
+#define AT91_SMC_TIMINGS_NFSEL(x)	((x & 0x1) << 31)
+
+#define AT91_SMC_MODE_RM_NCS		0x00000000
+#define AT91_SMC_MODE_RM_NRD		0x00000001
+#define AT91_SMC_MODE_WM_NCS		0x00000000
+#define AT91_SMC_MODE_WM_NWE		0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE	0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN	0x00000020
+#define AT91_SMC_MODE_EXNW_READY	0x00000030
+
+#define AT91_SMC_MODE_BAT		0x00000100
+#define AT91_SMC_MODE_DBW_8		0x00000000
+#define AT91_SMC_MODE_DBW_16		0x00001000
+#define AT91_SMC_MODE_DBW_32		0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF		0x00100000
+#define AT91_SMC_MODE_PMEN		0x01000000
+#define AT91_SMC_MODE_PS_4		0x00000000
+#define AT91_SMC_MODE_PS_8		0x10000000
+#define AT91_SMC_MODE_PS_16		0x20000000
+#define AT91_SMC_MODE_PS_32		0x30000000
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/spl.h
new file mode 100644
index 000000000..d8a87daa4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-at91/spl.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+enum {
+	BOOT_DEVICE_NONE,
+#ifdef CONFIG_SYS_USE_MMC
+	BOOT_DEVICE_MMC1,
+	BOOT_DEVICE_MMC2,
+	BOOT_DEVICE_MMC2_2,
+#elif CONFIG_SYS_USE_NANDFLASH
+	BOOT_DEVICE_NAND,
+#elif CONFIG_SYS_USE_SERIALFLASH
+	BOOT_DEVICE_SPI,
+#endif
+};
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h
new file mode 100644
index 000000000..1b40a96ad
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM281XX_GPIO_H
+#define __ARCH_BCM281XX_GPIO_H
+
+/*
+ * Empty file - cmd_gpio.c requires this. The implementation
+ * is in drivers/gpio/kona_gpio.c instead of inlined here.
+ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h
new file mode 100644
index 000000000..880b4e090
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM281XX_SYSMAP_H
+
+#define BSC1_BASE_ADDR		0x3e016000
+#define BSC2_BASE_ADDR		0x3e017000
+#define BSC3_BASE_ADDR		0x3e018000
+#define GPIO2_BASE_ADDR		0x35003000
+#define KONA_MST_CLK_BASE_ADDR	0x3f001000
+#define KONA_SLV_CLK_BASE_ADDR	0x3e011000
+#define PMU_BSC_BASE_ADDR	0x3500d000
+#define PWRMGR_BASE_ADDR	0x35010000
+#define SDIO1_BASE_ADDR		0x3f180000
+#define SDIO2_BASE_ADDR		0x3f190000
+#define SDIO3_BASE_ADDR		0x3f1a0000
+#define SDIO4_BASE_ADDR		0x3f1b0000
+#define SECWD_BASE_ADDR		0x3500c000
+#define SECWD2_BASE_ADDR	0x35002f40
+#define TIMER_BASE_ADDR		0x3e00d000
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/gpio.h
new file mode 100644
index 000000000..9a49b6e05
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/gpio.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2012 Vikram Narayananan
+ * <vikram186@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BCM2835_GPIO_H_
+#define _BCM2835_GPIO_H_
+
+#define BCM2835_GPIO_BASE		0x20200000
+#define BCM2835_GPIO_COUNT		54
+
+#define BCM2835_GPIO_FSEL_MASK		0x7
+#define BCM2835_GPIO_INPUT		0x0
+#define BCM2835_GPIO_OUTPUT		0x1
+#define BCM2835_GPIO_ALT0		0x4
+#define BCM2835_GPIO_ALT1		0x5
+#define BCM2835_GPIO_ALT2		0x6
+#define BCM2835_GPIO_ALT3		0x7
+#define BCM2835_GPIO_ALT4		0x3
+#define BCM2835_GPIO_ALT5		0x2
+
+#define BCM2835_GPIO_COMMON_BANK(gpio)	((gpio < 32) ? 0 : 1)
+#define BCM2835_GPIO_COMMON_SHIFT(gpio)	(gpio & 0x1f)
+
+#define BCM2835_GPIO_FSEL_BANK(gpio)	(gpio / 10)
+#define BCM2835_GPIO_FSEL_SHIFT(gpio)	((gpio % 10) * 3)
+
+struct bcm2835_gpio_regs {
+	u32 gpfsel[6];
+	u32 reserved1;
+	u32 gpset[2];
+	u32 reserved2;
+	u32 gpclr[2];
+	u32 reserved3;
+	u32 gplev[2];
+	u32 reserved4;
+	u32 gpeds[2];
+	u32 reserved5;
+	u32 gpren[2];
+	u32 reserved6;
+	u32 gpfen[2];
+	u32 reserved7;
+	u32 gphen[2];
+	u32 reserved8;
+	u32 gplen[2];
+	u32 reserved9;
+	u32 gparen[2];
+	u32 reserved10;
+	u32 gppud;
+	u32 gppudclk[2];
+};
+
+#endif /* _BCM2835_GPIO_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h
new file mode 100644
index 000000000..dded857c3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -0,0 +1,471 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BCM2835_MBOX_H
+#define _BCM2835_MBOX_H
+
+#include <linux/compiler.h>
+
+/*
+ * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
+ * and the ARM CPU. The ARM CPU is often thought of as the main CPU.
+ * However, the VideoCore actually controls the initial SoC boot, and hides
+ * much of the hardware behind a protocol. This protocol is transported
+ * using the SoC's mailbox hardware module.
+ *
+ * The mailbox hardware supports passing 32-bit values back and forth.
+ * Presumably by software convention of the firmware, the bottom 4 bits of the
+ * value are used to indicate a logical channel, and the upper 28 bits are the
+ * actual payload. Various channels exist using these simple raw messages. See
+ * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an
+ * example, the messages on the power management channel are a bitmask of
+ * devices whose power should be enabled.
+ *
+ * The property mailbox channel passes messages that contain the (16-byte
+ * aligned) ARM physical address of a memory buffer. This buffer is passed to
+ * the VC for processing, is modified in-place by the VC, and the address then
+ * passed back to the ARM CPU as the response mailbox message to indicate
+ * request completion. The buffers have a generic and extensible format; each
+ * buffer contains a standard header, a list of "tags", and a terminating zero
+ * entry. Each tag contains an ID indicating its type, and length fields for
+ * generic parsing. With some limitations, an arbitrary set of tags may be
+ * combined together into a single message buffer. This file defines structs
+ * representing the header and many individual tag layouts and IDs.
+ */
+
+/* Raw mailbox HW */
+
+#define BCM2835_MBOX_PHYSADDR	0x2000b880
+
+struct bcm2835_mbox_regs {
+	u32 read;
+	u32 rsvd0[5];
+	u32 status;
+	u32 config;
+	u32 write;
+};
+
+#define BCM2835_MBOX_STATUS_WR_FULL	0x80000000
+#define BCM2835_MBOX_STATUS_RD_EMPTY	0x40000000
+
+/* Lower 4-bits are channel ID */
+#define BCM2835_CHAN_MASK		0xf
+#define BCM2835_MBOX_PACK(chan, data)	(((data) & (~BCM2835_CHAN_MASK)) | \
+					 (chan & BCM2835_CHAN_MASK))
+#define BCM2835_MBOX_UNPACK_CHAN(val)	((val) & BCM2835_CHAN_MASK)
+#define BCM2835_MBOX_UNPACK_DATA(val)	((val) & (~BCM2835_CHAN_MASK))
+
+/* Property mailbox buffer structures */
+
+#define BCM2835_MBOX_PROP_CHAN		8
+
+/* All message buffers must start with this header */
+struct bcm2835_mbox_hdr {
+	u32 buf_size;
+	u32 code;
+};
+
+#define BCM2835_MBOX_REQ_CODE		0
+#define BCM2835_MBOX_RESP_CODE_SUCCESS	0x80000000
+
+#define BCM2835_MBOX_INIT_HDR(_m_) { \
+		memset((_m_), 0, sizeof(*(_m_))); \
+		(_m_)->hdr.buf_size = sizeof(*(_m_)); \
+		(_m_)->hdr.code = 0; \
+		(_m_)->end_tag = 0; \
+	}
+
+/*
+ * A message buffer contains a list of tags. Each tag must also start with
+ * a standardized header.
+ */
+struct bcm2835_mbox_tag_hdr {
+	u32 tag;
+	u32 val_buf_size;
+	u32 val_len;
+};
+
+#define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \
+		(_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
+		(_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
+		(_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \
+	}
+
+#define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \
+		(_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
+		(_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
+		(_t_)->tag_hdr.val_len = 0; \
+	}
+
+/* When responding, the VC sets this bit in val_len to indicate a response */
+#define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE	0x80000000
+
+/*
+ * Below we define the ID and struct for many possible tags. This header only
+ * defines individual tag structs, not entire message structs, since in
+ * general an arbitrary set of tags may be combined into a single message.
+ * Clients of the mbox API are expected to define their own overall message
+ * structures by combining the header, a set of tags, and a terminating
+ * entry. For example,
+ *
+ * struct msg {
+ *     struct bcm2835_mbox_hdr hdr;
+ *     struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
+ *     ... perhaps other tags here ...
+ *     u32 end_tag;
+ * };
+ */
+
+#define BCM2835_MBOX_TAG_GET_ARM_MEMORY		0x00010005
+
+struct bcm2835_mbox_tag_get_arm_mem {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+		} req;
+		struct {
+			u32 mem_base;
+			u32 mem_size;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_POWER_DEVID_SDHCI		0
+#define BCM2835_MBOX_POWER_DEVID_UART0		1
+#define BCM2835_MBOX_POWER_DEVID_UART1		2
+#define BCM2835_MBOX_POWER_DEVID_USB_HCD	3
+#define BCM2835_MBOX_POWER_DEVID_I2C0		4
+#define BCM2835_MBOX_POWER_DEVID_I2C1		5
+#define BCM2835_MBOX_POWER_DEVID_I2C2		6
+#define BCM2835_MBOX_POWER_DEVID_SPI		7
+#define BCM2835_MBOX_POWER_DEVID_CCP2TX		8
+
+#define BCM2835_MBOX_POWER_STATE_RESP_ON	(1 << 0)
+/* Device doesn't exist */
+#define BCM2835_MBOX_POWER_STATE_RESP_NODEV	(1 << 1)
+
+#define BCM2835_MBOX_TAG_GET_POWER_STATE	0x00020001
+
+struct bcm2835_mbox_tag_get_power_state {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			u32 device_id;
+		} req;
+		struct {
+			u32 device_id;
+			u32 state;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_SET_POWER_STATE	0x00028001
+
+#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON	(1 << 0)
+#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT	(1 << 1)
+
+struct bcm2835_mbox_tag_set_power_state {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			u32 device_id;
+			u32 state;
+		} req;
+		struct {
+			u32 device_id;
+			u32 state;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_GET_CLOCK_RATE	0x00030002
+
+#define BCM2835_MBOX_CLOCK_ID_EMMC	1
+#define BCM2835_MBOX_CLOCK_ID_UART	2
+#define BCM2835_MBOX_CLOCK_ID_ARM	3
+#define BCM2835_MBOX_CLOCK_ID_CORE	4
+#define BCM2835_MBOX_CLOCK_ID_V3D	5
+#define BCM2835_MBOX_CLOCK_ID_H264	6
+#define BCM2835_MBOX_CLOCK_ID_ISP	7
+#define BCM2835_MBOX_CLOCK_ID_SDRAM	8
+#define BCM2835_MBOX_CLOCK_ID_PIXEL	9
+#define BCM2835_MBOX_CLOCK_ID_PWM	10
+
+struct bcm2835_mbox_tag_get_clock_rate {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			u32 clock_id;
+		} req;
+		struct {
+			u32 clock_id;
+			u32 rate_hz;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_ALLOCATE_BUFFER	0x00040001
+
+struct bcm2835_mbox_tag_allocate_buffer {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			u32 alignment;
+		} req;
+		struct {
+			u32 fb_address;
+			u32 fb_size;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_RELEASE_BUFFER		0x00048001
+
+struct bcm2835_mbox_tag_release_buffer {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+		} req;
+		struct {
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_BLANK_SCREEN		0x00040002
+
+struct bcm2835_mbox_tag_blank_screen {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			/* bit 0 means on, other bots reserved */
+			u32 state;
+		} req;
+		struct {
+			u32 state;
+		} resp;
+	} body;
+};
+
+/* Physical means output signal */
+#define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H	0x00040003
+#define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H	0x00044003
+#define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H	0x00048003
+
+struct bcm2835_mbox_tag_physical_w_h {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		/* req not used for get */
+		struct {
+			u32 width;
+			u32 height;
+		} req;
+		struct {
+			u32 width;
+			u32 height;
+		} resp;
+	} body;
+};
+
+/* Virtual means display buffer */
+#define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H	0x00040004
+#define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H	0x00044004
+#define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H	0x00048004
+
+struct bcm2835_mbox_tag_virtual_w_h {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		/* req not used for get */
+		struct {
+			u32 width;
+			u32 height;
+		} req;
+		struct {
+			u32 width;
+			u32 height;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_GET_DEPTH		0x00040005
+#define BCM2835_MBOX_TAG_TEST_DEPTH		0x00044005
+#define BCM2835_MBOX_TAG_SET_DEPTH		0x00048005
+
+struct bcm2835_mbox_tag_depth {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		/* req not used for get */
+		struct {
+			u32 bpp;
+		} req;
+		struct {
+			u32 bpp;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_GET_PIXEL_ORDER	0x00040006
+#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER	0x00044005
+#define BCM2835_MBOX_TAG_SET_PIXEL_ORDER	0x00048006
+
+#define BCM2835_MBOX_PIXEL_ORDER_BGR		0
+#define BCM2835_MBOX_PIXEL_ORDER_RGB		1
+
+struct bcm2835_mbox_tag_pixel_order {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		/* req not used for get */
+		struct {
+			u32 order;
+		} req;
+		struct {
+			u32 order;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_GET_ALPHA_MODE		0x00040007
+#define BCM2835_MBOX_TAG_TEST_ALPHA_MODE	0x00044007
+#define BCM2835_MBOX_TAG_SET_ALPHA_MODE		0x00048007
+
+#define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE	0
+#define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT	1
+#define BCM2835_MBOX_ALPHA_MODE_IGNORED		2
+
+struct bcm2835_mbox_tag_alpha_mode {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		/* req not used for get */
+		struct {
+			u32 alpha;
+		} req;
+		struct {
+			u32 alpha;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_GET_PITCH		0x00040008
+
+struct bcm2835_mbox_tag_pitch {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+		} req;
+		struct {
+			u32 pitch;
+		} resp;
+	} body;
+};
+
+/* Offset of display window within buffer */
+#define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET	0x00040009
+#define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET	0x00044009
+#define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET	0x00048009
+
+struct bcm2835_mbox_tag_virtual_offset {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		/* req not used for get */
+		struct {
+			u32 x;
+			u32 y;
+		} req;
+		struct {
+			u32 x;
+			u32 y;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_GET_OVERSCAN		0x0004000a
+#define BCM2835_MBOX_TAG_TEST_OVERSCAN		0x0004400a
+#define BCM2835_MBOX_TAG_SET_OVERSCAN		0x0004800a
+
+struct bcm2835_mbox_tag_overscan {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		/* req not used for get */
+		struct {
+			u32 top;
+			u32 bottom;
+			u32 left;
+			u32 right;
+		} req;
+		struct {
+			u32 top;
+			u32 bottom;
+			u32 left;
+			u32 right;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_GET_PALETTE		0x0004000b
+
+struct bcm2835_mbox_tag_get_palette {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+		} req;
+		struct {
+			u32 data[1024];
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_TEST_PALETTE		0x0004400b
+
+struct bcm2835_mbox_tag_test_palette {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			u32 offset;
+			u32 num_entries;
+			u32 data[256];
+		} req;
+		struct {
+			u32 is_invalid;
+		} resp;
+	} body;
+};
+
+#define BCM2835_MBOX_TAG_SET_PALETTE		0x0004800b
+
+struct bcm2835_mbox_tag_set_palette {
+	struct bcm2835_mbox_tag_hdr tag_hdr;
+	union {
+		struct {
+			u32 offset;
+			u32 num_entries;
+			u32 data[256];
+		} req;
+		struct {
+			u32 is_invalid;
+		} resp;
+	} body;
+};
+
+/*
+ * Pass a raw u32 message to the VC, and receive a raw u32 back.
+ *
+ * Returns 0 for success, any other value for error.
+ */
+int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv);
+
+/*
+ * Pass a complete property-style buffer to the VC, and wait until it has
+ * been processed.
+ *
+ * This function expects a pointer to the mbox_hdr structure in an attempt
+ * to ensure some degree of type safety. However, some number of tags and
+ * a termination value are expected to immediately follow the header in
+ * memory, as required by the property protocol.
+ *
+ * Returns 0 for success, any other value for error.
+ */
+int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/sdhci.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/sdhci.h
new file mode 100644
index 000000000..a4f867b2e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/sdhci.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BCM2835_SDHCI_H_
+#define _BCM2835_SDHCI_H_
+
+#define BCM2835_SDHCI_BASE 0x20300000
+
+int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/timer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/timer.h
new file mode 100644
index 000000000..c2001b6f9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/timer.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BCM2835_TIMER_H
+#define _BCM2835_TIMER_H
+
+#define BCM2835_TIMER_PHYSADDR	0x20003000
+
+struct bcm2835_timer_regs {
+	u32 cs;
+	u32 clo;
+	u32 chi;
+	u32 c0;
+	u32 c1;
+	u32 c2;
+	u32 c3;
+};
+
+#define BCM2835_TIMER_CS_M3	(1 << 3)
+#define BCM2835_TIMER_CS_M2	(1 << 2)
+#define BCM2835_TIMER_CS_M1	(1 << 1)
+#define BCM2835_TIMER_CS_M0	(1 << 0)
+
+extern ulong get_timer_us(ulong base);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/wdog.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/wdog.h
new file mode 100644
index 000000000..303a65f32
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-bcm2835/wdog.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BCM2835_TIMER_H
+#define _BCM2835_TIMER_H
+
+#define BCM2835_WDOG_PHYSADDR			0x20100000
+
+struct bcm2835_wdog_regs {
+	u32 unknown0[7];
+	u32 rstc;
+	u32 unknown1;
+	u32 wdog;
+};
+
+#define BCM2835_WDOG_PASSWORD			0x5a000000
+
+#define BCM2835_WDOG_RSTC_WRCFG_MASK		0x00000030
+#define BCM2835_WDOG_RSTC_WRCFG_FULL_RESET	0x00000020
+
+#define BCM2835_WDOG_WDOG_TIMEOUT_MASK		0x0000ffff
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h
new file mode 100644
index 000000000..5063e3964
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/aintc_defs.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _DV_AINTC_DEFS_H_
+#define _DV_AINTC_DEFS_H_
+
+struct dv_aintc_regs {
+	unsigned int	fiq0;		/* 0x00 */
+	unsigned int	fiq1;		/* 0x04 */
+	unsigned int	irq0;		/* 0x08 */
+	unsigned int	irq1;		/* 0x0c */
+	unsigned int	fiqentry;	/* 0x10 */
+	unsigned int	irqentry;	/* 0x14 */
+	unsigned int	eint0;		/* 0x18 */
+	unsigned int	eint1;		/* 0x1c */
+	unsigned int	intctl;		/* 0x20 */
+	unsigned int	eabase;		/* 0x24 */
+	unsigned char	rsvd0[8];	/* 0x28 */
+	unsigned int	intpri0;	/* 0x30 */
+	unsigned int	intpri1;	/* 0x34 */
+	unsigned int	intpri2;	/* 0x38 */
+	unsigned int	intpri3;	/* 0x3c */
+	unsigned int	intpri4;	/* 0x40 */
+	unsigned int	intpri5;	/* 0x44 */
+	unsigned int	intpri6;	/* 0x48 */
+	unsigned int	intpri7;	/* 0x4c */
+};
+
+#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
+
+#define DV_AINTC_INTCTL_IDMODE	(1 << 2)
+
+#endif /* _DV_AINTC_DEFS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da850_lowlevel.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
new file mode 100644
index 000000000..45a325c12
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
@@ -0,0 +1,35 @@
+/*
+ * SoC-specific lowlevel code for DA850
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __DA850_LOWLEVEL_H
+#define __DA850_LOWLEVEL_H
+
+#include <asm/arch/pinmux_defs.h>
+
+/* pinmux_resource[] vector is defined in the board specific file */
+extern const struct pinmux_resource pinmuxes[];
+extern const int pinmuxes_size;
+
+extern const struct lpsc_resource lpsc[];
+extern const int lpsc_size;
+
+/* NOR Boot Configuration Word Field Descriptions */
+#define DA850_NORBOOT_COPY_XK(X)	((X - 1) << 8)
+#define DA850_NORBOOT_METHOD_DIRECT	(1 << 4)
+#define DA850_NORBOOT_16BIT		(1 << 0)
+
+#define dv_maskbits(addr, val) \
+	writel((readl(addr) & val), addr)
+
+void da850_lpc_transition(unsigned char pscnum, unsigned char module,
+		unsigned char domain, unsigned char state);
+void da850_psc_init(void);
+void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
+	unsigned long value);
+
+#endif /* #ifndef __DA850_LOWLEVEL_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da8xx-usb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da8xx-usb.h
new file mode 100644
index 000000000..f091e4989
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/da8xx-usb.h
@@ -0,0 +1,93 @@
+/*
+ * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
+ *
+ * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ *
+ * Based on drivers/usb/musb/davinci.h
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __DA8XX_MUSB_H__
+#define __DA8XX_MUSB_H__
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+
+/* Base address of da8xx usb0 wrapper */
+#define DA8XX_USB_OTG_BASE  0x01E00000
+
+/* Base address of da8xx musb core */
+#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
+
+/* Timeout for DA8xx usb module */
+#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
+
+/*
+ * DA8xx platform USB wrapper register overlay.
+ */
+struct da8xx_usb_regs {
+	dv_reg	revision;
+	dv_reg	control;
+	dv_reg 	status;
+	dv_reg 	emulation;
+	dv_reg 	mode;
+	dv_reg 	autoreq;
+	dv_reg 	srpfixtime;
+	dv_reg 	teardown;
+	dv_reg 	intsrc;
+	dv_reg 	intsrc_set;
+	dv_reg 	intsrc_clr;
+	dv_reg 	intmsk;
+	dv_reg 	intmsk_set;
+	dv_reg 	intmsk_clr;
+	dv_reg 	intsrcmsk;
+	dv_reg 	eoi;
+	dv_reg 	intvector;
+	dv_reg 	grndis_size[4];
+};
+
+#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
+
+/* DA8XX interrupt bits definitions */
+#define DA8XX_USB_TX_ENDPTS_MASK  0x1f	/* ep0 + 4 tx */
+#define DA8XX_USB_RX_ENDPTS_MASK  0x1e	/* 4 rx */
+#define DA8XX_USB_TXINT_SHIFT	  0
+#define DA8XX_USB_RXINT_SHIFT	  8
+
+#define DA8XX_USB_USBINT_MASK	  0x01ff0000	/* 8 Mentor, DRVVBUS */
+#define DA8XX_USB_TXINT_MASK \
+		(DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT)
+#define DA8XX_USB_RXINT_MASK \
+		(DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT)
+
+/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
+#define CFGCHIP2_PHYCLKGD	(1 << 17)
+#define CFGCHIP2_VBUSSENSE	(1 << 16)
+#define CFGCHIP2_RESET		(1 << 15)
+#define CFGCHIP2_OTGMODE	(3 << 13)
+#define CFGCHIP2_NO_OVERRIDE	(0 << 13)
+#define CFGCHIP2_FORCE_HOST	(1 << 13)
+#define CFGCHIP2_FORCE_DEVICE 	(2 << 13)
+#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
+#define CFGCHIP2_USB1PHYCLKMUX	(1 << 12)
+#define CFGCHIP2_USB2PHYCLKMUX	(1 << 11)
+#define CFGCHIP2_PHYPWRDN	(1 << 10)
+#define CFGCHIP2_OTGPWRDN	(1 << 9)
+#define CFGCHIP2_DATPOL 	(1 << 8)
+#define CFGCHIP2_USB1SUSPENDM	(1 << 7)
+#define CFGCHIP2_PHY_PLLON	(1 << 6)	/* override PLL suspend */
+#define CFGCHIP2_SESENDEN	(1 << 5)	/* Vsess_end comparator */
+#define CFGCHIP2_VBDTCTEN	(1 << 4)	/* Vbus comparator */
+#define CFGCHIP2_REFFREQ	(0xf << 0)
+#define CFGCHIP2_REFFREQ_12MHZ	(1 << 0)
+#define CFGCHIP2_REFFREQ_24MHZ	(2 << 0)
+#define CFGCHIP2_REFFREQ_48MHZ	(3 << 0)
+
+#define DA8XX_USB_VBUS_GPIO	(1 << 15)
+
+int usb_phy_on(void);
+void usb_phy_off(void);
+
+#endif	/* __DA8XX_MUSB_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/davinci_misc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/davinci_misc.h
new file mode 100644
index 000000000..03be3882f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/davinci_misc.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MISC_H
+#define __MISC_H
+
+/* pin muxer definitions */
+#define PIN_MUX_NUM_FIELDS	8	/* Per register */
+#define PIN_MUX_FIELD_SIZE	4	/* n in bits */
+#define PIN_MUX_FIELD_MASK	((1 << PIN_MUX_FIELD_SIZE) - 1)
+
+/* pin definition */
+struct pinmux_config {
+	dv_reg		*mux;		/* Address of mux register */
+	unsigned char	value;		/* Value to set in field */
+	unsigned char	field;		/* field number */
+};
+
+/* pin table definition */
+struct pinmux_resource {
+	const struct pinmux_config	*pins;
+	const int 			n_pins;
+};
+
+#define PINMUX_ITEM(item) { \
+				.pins = item, \
+				.n_pins = ARRAY_SIZE(item) \
+			  }
+
+struct lpsc_resource {
+	const int	lpsc_no;
+};
+
+int dvevm_read_mac_address(uint8_t *buf);
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
+int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+				    int n_items);
+#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX)
+void davinci_emac_mii_mode_sel(int mode_sel);
+#endif
+#if defined(CONFIG_SOC_DA8XX)
+void irq_init(void);
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+				    const int n_items);
+#endif
+
+#endif /* __MISC_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/ddr2_defs.h
new file mode 100644
index 000000000..24afd9d52
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/ddr2_defs.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _DV_DDR2_DEFS_H_
+#define _DV_DDR2_DEFS_H_
+
+/*
+ * DDR2 Memory Ctrl Register structure
+ * See sprueh7d.pdf for more details.
+ */
+struct dv_ddr2_regs_ctrl {
+	unsigned char	rsvd0[4];	/* 0x00 */
+	unsigned int	sdrstat;	/* 0x04 */
+	unsigned int	sdbcr;		/* 0x08 */
+	unsigned int	sdrcr;		/* 0x0C */
+	unsigned int	sdtimr;		/* 0x10 */
+	unsigned int	sdtimr2;	/* 0x14 */
+	unsigned char	rsvd1[4];	/* 0x18 */
+	unsigned int	sdbcr2;		/* 0x1C */
+	unsigned int	pbbpr;		/* 0x20 */
+	unsigned char	rsvd2[156];	/* 0x24 */
+	unsigned int	irr;		/* 0xC0 */
+	unsigned int	imr;		/* 0xC4 */
+	unsigned int	imsr;		/* 0xC8 */
+	unsigned int	imcr;		/* 0xCC */
+	unsigned char	rsvd3[20];	/* 0xD0 */
+	unsigned int	ddrphycr;	/* 0xE4 */
+	unsigned int	ddrphycr2;	/* 0xE8 */
+	unsigned char	rsvd4[4];	/* 0xEC */
+};
+
+#define DV_DDR_PHY_PWRDNEN		0x40
+#define DV_DDR_PHY_EXT_STRBEN	0x80
+#define DV_DDR_PHY_RD_LATENCY_SHIFT	0
+
+#define DV_DDR_SDTMR1_RFC_SHIFT	25
+#define DV_DDR_SDTMR1_RP_SHIFT	22
+#define DV_DDR_SDTMR1_RCD_SHIFT	19
+#define DV_DDR_SDTMR1_WR_SHIFT	16
+#define DV_DDR_SDTMR1_RAS_SHIFT	11
+#define DV_DDR_SDTMR1_RC_SHIFT	6
+#define DV_DDR_SDTMR1_RRD_SHIFT	3
+#define DV_DDR_SDTMR1_WTR_SHIFT	0
+
+#define DV_DDR_SDTMR2_RASMAX_SHIFT	27
+#define DV_DDR_SDTMR2_XP_SHIFT	25
+#define DV_DDR_SDTMR2_ODT_SHIFT	23
+#define DV_DDR_SDTMR2_XSNR_SHIFT	16
+#define DV_DDR_SDTMR2_XSRD_SHIFT	8
+#define DV_DDR_SDTMR2_RTP_SHIFT	5
+#define DV_DDR_SDTMR2_CKE_SHIFT	0
+
+#define DV_DDR_SDCR_DDR2TERM1_SHIFT	27
+#define DV_DDR_SDCR_IBANK_POS_SHIFT	26
+#define DV_DDR_SDCR_MSDRAMEN_SHIFT	25
+#define DV_DDR_SDCR_DDRDRIVE1_SHIFT	24
+#define DV_DDR_SDCR_BOOTUNLOCK_SHIFT	23
+#define DV_DDR_SDCR_DDR_DDQS_SHIFT	22
+#define DV_DDR_SDCR_DDR2EN_SHIFT	20
+#define DV_DDR_SDCR_DDRDRIVE0_SHIFT	18
+#define DV_DDR_SDCR_DDREN_SHIFT	17
+#define DV_DDR_SDCR_SDRAMEN_SHIFT	16
+#define DV_DDR_SDCR_TIMUNLOCK_SHIFT	15
+#define DV_DDR_SDCR_BUS_WIDTH_SHIFT	14
+#define DV_DDR_SDCR_CL_SHIFT		9
+#define DV_DDR_SDCR_IBANK_SHIFT	4
+#define DV_DDR_SDCR_PAGESIZE_SHIFT	0
+
+#define DV_DDR_SDRCR_LPMODEN	(1 << 31)
+#define DV_DDR_SDRCR_MCLKSTOPEN	(1 << 30)
+
+#define DV_DDR_SRCR_LPMODEN_SHIFT	31
+#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT	30
+
+#define DV_DDR_BOOTUNLOCK	(1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT)
+#define DV_DDR_TIMUNLOCK	(1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)
+
+#define dv_ddr2_regs_ctrl \
+	((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
+
+#endif /* _DV_DDR2_DEFS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h
new file mode 100644
index 000000000..6c0275efa
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h
@@ -0,0 +1,25 @@
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __DM365_LOWLEVEL_H
+#define __DM365_LOWLEVEL_H
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+void dm365_waitloop(unsigned long loopcnt);
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
+int dm365_ddr_setup(void);
+void dm365_psc_init(void);
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+	unsigned long value);
+void dm36x_lowlevel_init(ulong bootflag);
+
+#endif /* #ifndef __DM365_LOWLEVEL_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emac_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emac_defs.h
new file mode 100644
index 000000000..c3f046efa
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emac_defs.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * dm644x_emac.h
+ *
+ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
+ *
+ * Copyright (C) 2005 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Modifications:
+ * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
+ */
+
+#ifndef _DM644X_EMAC_H_
+#define _DM644X_EMAC_H_
+
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_SOC_DM365
+#define EMAC_BASE_ADDR			(0x01d07000)
+#define EMAC_WRAPPER_BASE_ADDR		(0x01d0a000)
+#define EMAC_WRAPPER_RAM_ADDR		(0x01d08000)
+#define EMAC_MDIO_BASE_ADDR		(0x01d0b000)
+#define DAVINCI_EMAC_VERSION2
+#elif defined(CONFIG_SOC_DA8XX)
+#define EMAC_BASE_ADDR			DAVINCI_EMAC_CNTRL_REGS_BASE
+#define EMAC_WRAPPER_BASE_ADDR		DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
+#define EMAC_WRAPPER_RAM_ADDR		DAVINCI_EMAC_WRAPPER_RAM_BASE
+#define EMAC_MDIO_BASE_ADDR		DAVINCI_MDIO_CNTRL_REGS_BASE
+#define DAVINCI_EMAC_VERSION2
+#else
+#define EMAC_BASE_ADDR			(0x01c80000)
+#define EMAC_WRAPPER_BASE_ADDR		(0x01c81000)
+#define EMAC_WRAPPER_RAM_ADDR		(0x01c82000)
+#define EMAC_MDIO_BASE_ADDR		(0x01c84000)
+#endif
+
+#ifdef CONFIG_SOC_DM646X
+#define DAVINCI_EMAC_VERSION2
+#define DAVINCI_EMAC_GIG_ENABLE
+#endif
+
+#ifdef CONFIG_SOC_DM646X
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ		76500000
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ		2500000		/* 2.5 MHz */
+#elif defined(CONFIG_SOC_DM365)
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ		121500000
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ		2200000		/* 2.2 MHz */
+#elif defined(CONFIG_SOC_DA8XX)
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ		clk_get(DAVINCI_MDIO_CLKID)
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
+#else
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ		99000000	/* PLL/6 - 99 MHz */
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
+#endif
+
+#define PHY_KSZ8873	(0x00221450)
+int ksz8873_is_phy_connected(int phy_addr);
+int ksz8873_get_link_speed(int phy_addr);
+int ksz8873_init_phy(int phy_addr);
+int ksz8873_auto_negotiate(int phy_addr);
+
+#define PHY_LXT972	(0x001378e2)
+int lxt972_is_phy_connected(int phy_addr);
+int lxt972_get_link_speed(int phy_addr);
+int lxt972_init_phy(int phy_addr);
+int lxt972_auto_negotiate(int phy_addr);
+
+#define PHY_DP83848	(0x20005c90)
+int dp83848_is_phy_connected(int phy_addr);
+int dp83848_get_link_speed(int phy_addr);
+int dp83848_init_phy(int phy_addr);
+int dp83848_auto_negotiate(int phy_addr);
+
+#define PHY_ET1011C	(0x282f013)
+int et1011c_get_link_speed(int phy_addr);
+
+#endif  /* _DM644X_EMAC_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emif_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emif_defs.h
new file mode 100644
index 000000000..7e19cfeed
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/emif_defs.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _EMIF_DEFS_H_
+#define _EMIF_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+struct davinci_emif_regs {
+	u_int32_t	ercsr;
+	u_int32_t	awccr;
+	u_int32_t	sdbcr;
+	u_int32_t	sdrcr;
+	u_int32_t	ab1cr;
+	u_int32_t	ab2cr;
+	u_int32_t	ab3cr;
+	u_int32_t	ab4cr;
+	u_int32_t	sdtimr;
+	u_int32_t	ddrsr;
+	u_int32_t	ddrphycr;
+	u_int32_t	ddrphysr;
+	u_int32_t	totar;
+	u_int32_t	totactr;
+	u_int32_t	ddrphyid_rev;
+	u_int32_t	sdsretr;
+	u_int32_t	eirr;
+	u_int32_t	eimr;
+	u_int32_t	eimsr;
+	u_int32_t	eimcr;
+	u_int32_t	ioctrlr;
+	u_int32_t	iostatr;
+	u_int8_t	rsvd0[8];
+	u_int32_t	nandfcr;
+	u_int32_t	nandfsr;
+	u_int8_t	rsvd1[8];
+	u_int32_t	nandfecc[4];
+	u_int8_t	rsvd2[60];
+	u_int32_t	nand4biteccload;
+	u_int32_t	nand4bitecc[4];
+	u_int32_t	nanderradd1;
+	u_int32_t	nanderradd2;
+	u_int32_t	nanderrval1;
+	u_int32_t	nanderrval2;
+};
+
+#define davinci_emif_regs \
+	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
+
+#define DAVINCI_NANDFCR_NAND_ENABLE(n)			(1 << (n-2))
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK		(3 << 4)
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n)			((n-2) << 4)
+#define DAVINCI_NANDFCR_1BIT_ECC_START(n)		(1 << (8 + (n-2)))
+#define DAVINCI_NANDFCR_4BIT_ECC_START			(1 << 12)
+#define DAVINCI_NANDFCR_4BIT_CALC_START			(1 << 13)
+#define DAVINCI_NANDFCR_CS2NAND				(1 << 0)
+
+/* Chip Select setup */
+#define DAVINCI_ABCR_STROBE_SELECT			(1 << 31)
+#define DAVINCI_ABCR_EXT_WAIT				(1 << 30)
+#define DAVINCI_ABCR_WSETUP(n)				(n << 26)
+#define DAVINCI_ABCR_WSTROBE(n)				(n << 20)
+#define DAVINCI_ABCR_WHOLD(n)				(n << 17)
+#define DAVINCI_ABCR_RSETUP(n)				(n << 13)
+#define DAVINCI_ABCR_RSTROBE(n)				(n << 7)
+#define DAVINCI_ABCR_RHOLD(n)				(n << 4)
+#define DAVINCI_ABCR_TA(n)				(n << 2)
+#define DAVINCI_ABCR_ASIZE_16BIT			1
+#define DAVINCI_ABCR_ASIZE_8BIT				0
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/gpio.h
new file mode 100644
index 000000000..7da0060cd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/gpio.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _GPIO_DEFS_H_
+#define _GPIO_DEFS_H_
+
+#ifndef CONFIG_SOC_DA8XX
+#define DAVINCI_GPIO_BINTEN	0x01C67008
+#define DAVINCI_GPIO_BANK01	0x01C67010
+#define DAVINCI_GPIO_BANK23	0x01C67038
+#define DAVINCI_GPIO_BANK45	0x01C67060
+#define DAVINCI_GPIO_BANK67	0x01C67088
+
+#else /* CONFIG_SOC_DA8XX */
+#define DAVINCI_GPIO_BINTEN	0x01E26008
+#define DAVINCI_GPIO_BANK01	0x01E26010
+#define DAVINCI_GPIO_BANK23	0x01E26038
+#define DAVINCI_GPIO_BANK45	0x01E26060
+#define DAVINCI_GPIO_BANK67	0x01E26088
+#define DAVINCI_GPIO_BANK8	0x01E260B0
+#endif /* CONFIG_SOC_DA8XX */
+
+struct davinci_gpio {
+	unsigned int dir;
+	unsigned int out_data;
+	unsigned int set_data;
+	unsigned int clr_data;
+	unsigned int in_data;
+	unsigned int set_rising;
+	unsigned int clr_rising;
+	unsigned int set_falling;
+	unsigned int clr_falling;
+	unsigned int intstat;
+};
+
+struct davinci_gpio_bank {
+	int num_gpio;
+	unsigned int irq_num;
+	unsigned int irq_mask;
+	unsigned long *in_use;
+	unsigned long base;
+};
+
+#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
+#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
+#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
+#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
+#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
+
+#define gpio_status()		gpio_info()
+#define GPIO_NAME_SIZE		20
+#if defined(CONFIG_SOC_DM644X)
+/* GPIO0 to GPIO53, omit the V3.3 volts one */
+#define MAX_NUM_GPIOS		70
+#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
+#define MAX_NUM_GPIOS		128
+#else
+#define MAX_NUM_GPIOS		144
+#endif
+#define GPIO_BANK(gp)		(davinci_gpio_bank01 + ((gp) >> 5))
+#define GPIO_BIT(gp)		((gp) & 0x1F)
+
+void gpio_info(void);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/hardware.h
new file mode 100644
index 000000000..98fe56e68
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/hardware.h
@@ -0,0 +1,617 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * -------------------------------------------------------------------------
+ *
+ *  linux/include/asm-arm/arch-davinci/hardware.h
+ *
+ *  Copyright (C) 2006 Texas Instruments.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <config.h>
+#include <linux/sizes.h>
+
+#define	REG(addr)	(*(volatile unsigned int *)(addr))
+#define REG_P(addr)	((volatile unsigned int *)(addr))
+
+typedef volatile unsigned int	dv_reg;
+typedef volatile unsigned int *	dv_reg_p;
+
+/*
+ * Base register addresses
+ *
+ * NOTE:  some of these DM6446-specific addresses DO NOT WORK
+ * on other DaVinci chips.  Double check them before you try
+ * using the addresses ... or PSC module identifiers, etc.
+ */
+#ifndef CONFIG_SOC_DA8XX
+
+#define DAVINCI_DMA_3PCC_BASE			(0x01c00000)
+#define DAVINCI_DMA_3PTC0_BASE			(0x01c10000)
+#define DAVINCI_DMA_3PTC1_BASE			(0x01c10400)
+#define DAVINCI_UART0_BASE			(0x01c20000)
+#define DAVINCI_UART1_BASE			(0x01c20400)
+#define DAVINCI_TIMER3_BASE			(0x01c20800)
+#define DAVINCI_I2C_BASE			(0x01c21000)
+#define DAVINCI_TIMER0_BASE			(0x01c21400)
+#define DAVINCI_TIMER1_BASE			(0x01c21800)
+#define DAVINCI_WDOG_BASE			(0x01c21c00)
+#define DAVINCI_PWM0_BASE			(0x01c22000)
+#define DAVINCI_PWM1_BASE			(0x01c22400)
+#define DAVINCI_PWM2_BASE			(0x01c22800)
+#define DAVINCI_TIMER4_BASE			(0x01c23800)
+#define DAVINCI_SYSTEM_MODULE_BASE		(0x01c40000)
+#define DAVINCI_PLL_CNTRL0_BASE			(0x01c40800)
+#define DAVINCI_PLL_CNTRL1_BASE			(0x01c40c00)
+#define DAVINCI_PWR_SLEEP_CNTRL_BASE		(0x01c41000)
+#define DAVINCI_ARM_INTC_BASE			(0x01c48000)
+#define DAVINCI_USB_OTG_BASE			(0x01c64000)
+#define DAVINCI_CFC_ATA_BASE			(0x01c66000)
+#define DAVINCI_SPI_BASE			(0x01c66800)
+#define DAVINCI_GPIO_BASE			(0x01c67000)
+#define DAVINCI_VPSS_REGS_BASE			(0x01c70000)
+#if !defined(CONFIG_SOC_DM646X)
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x02000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
+#endif
+#define DAVINCI_DDR_BASE			(0x80000000)
+
+#ifdef CONFIG_SOC_DM644X
+#define DAVINCI_UART2_BASE			0x01c20800
+#define DAVINCI_UHPI_BASE			0x01c67800
+#define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01c80000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01c81000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01c82000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01c84000
+#define DAVINCI_IMCOP_BASE			0x01cc0000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e00000
+#define DAVINCI_VLYNQ_BASE			0x01e01000
+#define DAVINCI_ASP_BASE			0x01e02000
+#define DAVINCI_MMC_SD_BASE			0x01e10000
+#define DAVINCI_MS_BASE				0x01e20000
+#define DAVINCI_VLYNQ_REMOTE_BASE		0x0c000000
+
+#elif defined(CONFIG_SOC_DM355)
+#define DAVINCI_MMC_SD1_BASE			0x01e00000
+#define DAVINCI_ASP0_BASE			0x01e02000
+#define DAVINCI_ASP1_BASE			0x01e04000
+#define DAVINCI_UART2_BASE			0x01e06000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e10000
+#define DAVINCI_MMC_SD0_BASE			0x01e11000
+
+#elif defined(CONFIG_SOC_DM365)
+#define DAVINCI_MMC_SD1_BASE			0x01d00000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01d10000
+#define DAVINCI_MMC_SD0_BASE			0x01d11000
+#define DAVINCI_DDR_EMIF_CTRL_BASE		0x20000000
+#define DAVINCI_SPI0_BASE			0x01c66000
+#define DAVINCI_SPI1_BASE			0x01c66800
+
+#elif defined(CONFIG_SOC_DM646X)
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x20008000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x42000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	0x44000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x46000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
+
+#endif
+
+#else /* CONFIG_SOC_DA8XX */
+
+#define DAVINCI_UART0_BASE			0x01c42000
+#define DAVINCI_UART1_BASE			0x01d0c000
+#define DAVINCI_UART2_BASE			0x01d0d000
+#define DAVINCI_I2C0_BASE			0x01c22000
+#define DAVINCI_I2C1_BASE			0x01e28000
+#define DAVINCI_TIMER0_BASE			0x01c20000
+#define DAVINCI_TIMER1_BASE			0x01c21000
+#define DAVINCI_WDOG_BASE			0x01c21000
+#define DAVINCI_RTC_BASE			0x01c23000
+#define DAVINCI_PLL_CNTRL0_BASE			0x01c11000
+#define DAVINCI_PLL_CNTRL1_BASE			0x01e1a000
+#define DAVINCI_PSC0_BASE			0x01c10000
+#define DAVINCI_PSC1_BASE			0x01e27000
+#define DAVINCI_SPI0_BASE			0x01c41000
+#define DAVINCI_USB_OTG_BASE			0x01e00000
+#define DAVINCI_SPI1_BASE			(cpu_is_da830() ? \
+						0x01e12000 : 0x01f0e000)
+#define DAVINCI_GPIO_BASE			0x01e26000
+#define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01e23000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01e22000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01e20000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01e24000
+#define DAVINCI_SYSCFG1_BASE			0x01e2c000
+#define DAVINCI_MMC_SD0_BASE			0x01c40000
+#define DAVINCI_MMC_SD1_BASE			0x01e1b000
+#define DAVINCI_TIMER2_BASE			0x01f0c000
+#define DAVINCI_TIMER3_BASE			0x01f0d000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x68000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x40000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x60000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	0x62000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE	0x64000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE	0x66000000
+#define DAVINCI_DDR_EMIF_CTRL_BASE		0xb0000000
+#define DAVINCI_DDR_EMIF_DATA_BASE		0xc0000000
+#define DAVINCI_INTC_BASE			0xfffee000
+#define DAVINCI_BOOTCFG_BASE			0x01c14000
+#define DAVINCI_LCD_CNTL_BASE			0x01e13000
+#define DAVINCI_L3CBARAM_BASE			0x80000000
+#define JTAG_ID_REG                            (DAVINCI_BOOTCFG_BASE + 0x18)
+#define CHIP_REV_ID_REG				(DAVINCI_BOOTCFG_BASE + 0x24)
+#define HOST1CFG				(DAVINCI_BOOTCFG_BASE + 0x44)
+#define PSC0_MDCTL				(DAVINCI_PSC0_BASE + 0xa00)
+
+#define GPIO_BANK0_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x10)
+#define GPIO_BANK0_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x14)
+#define GPIO_BANK0_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x18)
+#define GPIO_BANK0_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x1c)
+#define GPIO_BANK2_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x38)
+#define GPIO_BANK2_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x3c)
+#define GPIO_BANK2_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x40)
+#define GPIO_BANK2_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x44)
+#define GPIO_BANK6_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x88)
+#define GPIO_BANK6_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x8c)
+#define GPIO_BANK6_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x90)
+#define GPIO_BANK6_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x94)
+#endif /* CONFIG_SOC_DA8XX */
+
+/* Power and Sleep Controller (PSC) Domains */
+#define DAVINCI_GPSC_ARMDOMAIN		0
+#define DAVINCI_GPSC_DSPDOMAIN		1
+
+#ifndef CONFIG_SOC_DA8XX
+
+#define DAVINCI_LPSC_VPSSMSTR		0
+#define DAVINCI_LPSC_VPSSSLV		1
+#define DAVINCI_LPSC_TPCC		2
+#define DAVINCI_LPSC_TPTC0		3
+#define DAVINCI_LPSC_TPTC1		4
+#define DAVINCI_LPSC_EMAC		5
+#define DAVINCI_LPSC_EMAC_WRAPPER	6
+#define DAVINCI_LPSC_MDIO		7
+#define DAVINCI_LPSC_IEEE1394		8
+#define DAVINCI_LPSC_USB		9
+#define DAVINCI_LPSC_ATA		10
+#define DAVINCI_LPSC_VLYNQ		11
+#define DAVINCI_LPSC_UHPI		12
+#define DAVINCI_LPSC_DDR_EMIF		13
+#define DAVINCI_LPSC_AEMIF		14
+#define DAVINCI_LPSC_MMC_SD		15
+#define DAVINCI_LPSC_MEMSTICK		16
+#define DAVINCI_LPSC_McBSP		17
+#define DAVINCI_LPSC_I2C		18
+#define DAVINCI_LPSC_UART0		19
+#define DAVINCI_LPSC_UART1		20
+#define DAVINCI_LPSC_UART2		21
+#define DAVINCI_LPSC_SPI		22
+#define DAVINCI_LPSC_PWM0		23
+#define DAVINCI_LPSC_PWM1		24
+#define DAVINCI_LPSC_PWM2		25
+#define DAVINCI_LPSC_GPIO		26
+#define DAVINCI_LPSC_TIMER0		27
+#define DAVINCI_LPSC_TIMER1		28
+#define DAVINCI_LPSC_TIMER2		29
+#define DAVINCI_LPSC_SYSTEM_SUBSYS	30
+#define DAVINCI_LPSC_ARM		31
+#define DAVINCI_LPSC_SCR2		32
+#define DAVINCI_LPSC_SCR3		33
+#define DAVINCI_LPSC_SCR4		34
+#define DAVINCI_LPSC_CROSSBAR		35
+#define DAVINCI_LPSC_CFG27		36
+#define DAVINCI_LPSC_CFG3		37
+#define DAVINCI_LPSC_CFG5		38
+#define DAVINCI_LPSC_GEM		39
+#define DAVINCI_LPSC_IMCOP		40
+#define DAVINCI_LPSC_VPSSMASTER		47
+#define DAVINCI_LPSC_MJCP		50
+#define DAVINCI_LPSC_HDVICP		51
+
+#define DAVINCI_DM646X_LPSC_EMAC	14
+#define DAVINCI_DM646X_LPSC_UART0	26
+#define DAVINCI_DM646X_LPSC_I2C		31
+#define DAVINCI_DM646X_LPSC_TIMER0	34
+
+#else /* CONFIG_SOC_DA8XX */
+
+#define DAVINCI_LPSC_TPCC		0
+#define DAVINCI_LPSC_TPTC0		1
+#define DAVINCI_LPSC_TPTC1		2
+#define DAVINCI_LPSC_AEMIF		3
+#define DAVINCI_LPSC_SPI0		4
+#define DAVINCI_LPSC_MMC_SD		5
+#define DAVINCI_LPSC_AINTC		6
+#define DAVINCI_LPSC_ARM_RAM_ROM	7
+#define DAVINCI_LPSC_SECCTL_KEYMGR	8
+#define DAVINCI_LPSC_UART0		9
+#define DAVINCI_LPSC_SCR0		10
+#define DAVINCI_LPSC_SCR1		11
+#define DAVINCI_LPSC_SCR2		12
+#define DAVINCI_LPSC_DMAX		13
+#define DAVINCI_LPSC_ARM		14
+#define DAVINCI_LPSC_GEM		15
+
+/* for LPSCs in PSC1, offset from 32 for differentiation */
+#define DAVINCI_LPSC_PSC1_BASE		32
+#define DAVINCI_LPSC_USB20		(DAVINCI_LPSC_PSC1_BASE + 1)
+#define DAVINCI_LPSC_USB11		(DAVINCI_LPSC_PSC1_BASE + 2)
+#define DAVINCI_LPSC_GPIO		(DAVINCI_LPSC_PSC1_BASE + 3)
+#define DAVINCI_LPSC_UHPI		(DAVINCI_LPSC_PSC1_BASE + 4)
+#define DAVINCI_LPSC_EMAC		(DAVINCI_LPSC_PSC1_BASE + 5)
+#define DAVINCI_LPSC_DDR_EMIF		(DAVINCI_LPSC_PSC1_BASE + 6)
+#define DAVINCI_LPSC_McASP0		(DAVINCI_LPSC_PSC1_BASE + 7)
+#define DAVINCI_LPSC_SPI1		(DAVINCI_LPSC_PSC1_BASE + 10)
+#define DAVINCI_LPSC_I2C1		(DAVINCI_LPSC_PSC1_BASE + 11)
+#define DAVINCI_LPSC_UART1		(DAVINCI_LPSC_PSC1_BASE + 12)
+#define DAVINCI_LPSC_UART2		(DAVINCI_LPSC_PSC1_BASE + 13)
+#define DAVINCI_LPSC_LCDC		(DAVINCI_LPSC_PSC1_BASE + 16)
+#define DAVINCI_LPSC_ePWM		(DAVINCI_LPSC_PSC1_BASE + 17)
+#define DAVINCI_LPSC_MMCSD1		(DAVINCI_LPSC_PSC1_BASE + 18)
+#define DAVINCI_LPSC_eCAP		(DAVINCI_LPSC_PSC1_BASE + 20)
+#define DAVINCI_LPSC_L3_CBA_RAM		(DAVINCI_LPSC_PSC1_BASE + 31)
+
+/* DA830-specific peripherals */
+#define DAVINCI_LPSC_McASP1		(DAVINCI_LPSC_PSC1_BASE + 8)
+#define DAVINCI_LPSC_McASP2		(DAVINCI_LPSC_PSC1_BASE + 9)
+#define DAVINCI_LPSC_eQEP		(DAVINCI_LPSC_PSC1_BASE + 21)
+#define DAVINCI_LPSC_SCR8		(DAVINCI_LPSC_PSC1_BASE + 24)
+#define DAVINCI_LPSC_SCR7		(DAVINCI_LPSC_PSC1_BASE + 25)
+#define DAVINCI_LPSC_SCR12		(DAVINCI_LPSC_PSC1_BASE + 26)
+
+/* DA850-specific peripherals */
+#define DAVINCI_LPSC_TPCC1		(DAVINCI_LPSC_PSC1_BASE + 0)
+#define DAVINCI_LPSC_SATA		(DAVINCI_LPSC_PSC1_BASE + 8)
+#define DAVINCI_LPSC_VPIF		(DAVINCI_LPSC_PSC1_BASE + 9)
+#define DAVINCI_LPSC_McBSP0		(DAVINCI_LPSC_PSC1_BASE + 14)
+#define DAVINCI_LPSC_McBSP1		(DAVINCI_LPSC_PSC1_BASE + 15)
+#define DAVINCI_LPSC_MMC_SD1		(DAVINCI_LPSC_PSC1_BASE + 18)
+#define DAVINCI_LPSC_uPP		(DAVINCI_LPSC_PSC1_BASE + 19)
+#define DAVINCI_LPSC_TPTC2		(DAVINCI_LPSC_PSC1_BASE + 21)
+#define DAVINCI_LPSC_SCR_F0		(DAVINCI_LPSC_PSC1_BASE + 24)
+#define DAVINCI_LPSC_SCR_F1		(DAVINCI_LPSC_PSC1_BASE + 25)
+#define DAVINCI_LPSC_SCR_F2		(DAVINCI_LPSC_PSC1_BASE + 26)
+#define DAVINCI_LPSC_SCR_F6		(DAVINCI_LPSC_PSC1_BASE + 27)
+#define DAVINCI_LPSC_SCR_F7		(DAVINCI_LPSC_PSC1_BASE + 28)
+#define DAVINCI_LPSC_SCR_F8		(DAVINCI_LPSC_PSC1_BASE + 29)
+#define DAVINCI_LPSC_BR_F7		(DAVINCI_LPSC_PSC1_BASE + 30)
+
+#endif /* CONFIG_SOC_DA8XX */
+
+void lpsc_on(unsigned int id);
+void lpsc_syncreset(unsigned int id);
+void lpsc_disable(unsigned int id);
+void dsp_on(void);
+
+void davinci_enable_uart0(void);
+void davinci_enable_emac(void);
+void davinci_enable_i2c(void);
+void davinci_errata_workarounds(void);
+
+#ifndef CONFIG_SOC_DA8XX
+
+/* Some PSC defines */
+#define PSC_CHP_SHRTSW			(0x01c40038)
+#define PSC_GBLCTL			(0x01c41010)
+#define PSC_EPCPR			(0x01c41070)
+#define PSC_EPCCR			(0x01c41078)
+#define PSC_PTCMD			(0x01c41120)
+#define PSC_PTSTAT			(0x01c41128)
+#define PSC_PDSTAT			(0x01c41200)
+#define PSC_PDSTAT1			(0x01c41204)
+#define PSC_PDCTL			(0x01c41300)
+#define PSC_PDCTL1			(0x01c41304)
+
+#define PSC_MDCTL_BASE			(0x01c41a00)
+#define PSC_MDSTAT_BASE			(0x01c41800)
+
+#define VDD3P3V_PWDN			(0x01c40048)
+#define UART0_PWREMU_MGMT		(0x01c20030)
+
+#define PSC_SILVER_BULLET		(0x01c41a20)
+
+#else /* CONFIG_SOC_DA8XX */
+
+#define	PSC_ENABLE		0x3
+#define	PSC_DISABLE		0x2
+#define	PSC_SYNCRESET		0x1
+#define	PSC_SWRSTDISABLE	0x0
+
+#define PSC_PSC0_MODULE_ID_CNT		16
+#define PSC_PSC1_MODULE_ID_CNT		32
+
+#define UART0_PWREMU_MGMT		(0x01c42030)
+
+struct davinci_psc_regs {
+	dv_reg	revid;
+	dv_reg	rsvd0[71];
+	dv_reg	ptcmd;
+	dv_reg	rsvd1;
+	dv_reg	ptstat;
+	dv_reg	rsvd2[437];
+	union {
+		struct {
+			dv_reg	mdstat[PSC_PSC0_MODULE_ID_CNT];
+			dv_reg	rsvd3[112];
+			dv_reg	mdctl[PSC_PSC0_MODULE_ID_CNT];
+		} psc0;
+		struct {
+			dv_reg	mdstat[PSC_PSC1_MODULE_ID_CNT];
+			dv_reg	rsvd3[96];
+			dv_reg	mdctl[PSC_PSC1_MODULE_ID_CNT];
+		} psc1;
+	};
+};
+
+#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
+#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
+
+#endif /* CONFIG_SOC_DA8XX */
+
+#define PSC_MDSTAT_STATE		0x3f
+#define PSC_MDCTL_NEXT			0x07
+
+#ifndef CONFIG_SOC_DA8XX
+
+/* Miscellania... */
+#define VBPR				(0x20000020)
+
+/* NOTE:  system control modules are *highly* chip-specific, both
+ * as to register content (e.g. for muxing) and which registers exist.
+ */
+#define PINMUX0				0x01c40000
+#define PINMUX1				0x01c40004
+#define PINMUX2				0x01c40008
+#define PINMUX3				0x01c4000c
+#define PINMUX4				0x01c40010
+
+struct davinci_uart_ctrl_regs {
+	dv_reg	revid1;
+	dv_reg	res;
+	dv_reg	pwremu_mgmt;
+	dv_reg	mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE	(1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)
+
+#else /* CONFIG_SOC_DA8XX */
+
+struct davinci_pllc_regs {
+	dv_reg	revid;
+	dv_reg	rsvd1[56];
+	dv_reg	rstype;
+	dv_reg	rsvd2[6];
+	dv_reg	pllctl;
+	dv_reg	ocsel;
+	dv_reg	rsvd3[2];
+	dv_reg	pllm;
+	dv_reg	prediv;
+	dv_reg	plldiv1;
+	dv_reg	plldiv2;
+	dv_reg	plldiv3;
+	dv_reg	oscdiv;
+	dv_reg	postdiv;
+	dv_reg	rsvd4[3];
+	dv_reg	pllcmd;
+	dv_reg	pllstat;
+	dv_reg	alnctl;
+	dv_reg	dchange;
+	dv_reg	cken;
+	dv_reg	ckstat;
+	dv_reg	systat;
+	dv_reg	rsvd5[3];
+	dv_reg	plldiv4;
+	dv_reg	plldiv5;
+	dv_reg	plldiv6;
+	dv_reg	plldiv7;
+	dv_reg	rsvd6[32];
+	dv_reg	emucnt0;
+	dv_reg	emucnt1;
+};
+
+#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
+#define DAVINCI_PLLC_DIV_MASK	0x1f
+
+/*
+ * A clock ID is a 32-bit number where bit 16 represents the PLL controller
+ * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
+ * counting from 1. Clock IDs may be passed to clk_get().
+ */
+
+/* flags to select PLL controller */
+#define DAVINCI_PLLC0_FLAG			(0)
+#define DAVINCI_PLLC1_FLAG			(1 << 16)
+
+enum davinci_clk_ids {
+	/*
+	 * Clock IDs for PLL outputs. Each may be switched on/off
+	 * independently, and each may map to one or more peripherals.
+	 */
+	DAVINCI_PLL0_SYSCLK2			= DAVINCI_PLLC0_FLAG | 2,
+	DAVINCI_PLL0_SYSCLK4			= DAVINCI_PLLC0_FLAG | 4,
+	DAVINCI_PLL0_SYSCLK6			= DAVINCI_PLLC0_FLAG | 6,
+	DAVINCI_PLL1_SYSCLK1			= DAVINCI_PLLC1_FLAG | 1,
+	DAVINCI_PLL1_SYSCLK2			= DAVINCI_PLLC1_FLAG | 2,
+
+	/* map peripherals to clock IDs */
+	DAVINCI_ARM_CLKID			= DAVINCI_PLL0_SYSCLK6,
+	DAVINCI_DDR_CLKID			= DAVINCI_PLL1_SYSCLK1,
+	DAVINCI_MDIO_CLKID			= DAVINCI_PLL0_SYSCLK4,
+	DAVINCI_MMC_CLKID			= DAVINCI_PLL0_SYSCLK2,
+	DAVINCI_SPI0_CLKID			= DAVINCI_PLL0_SYSCLK2,
+	DAVINCI_MMCSD_CLKID			= DAVINCI_PLL0_SYSCLK2,
+
+	/* special clock ID - output of PLL multiplier */
+	DAVINCI_PLLM_CLKID			= 0x0FF,
+
+	/* special clock ID - output of PLL post divisor */
+	DAVINCI_PLLC_CLKID			= 0x100,
+
+	/* special clock ID - PLL bypass */
+	DAVINCI_AUXCLK_CLKID			= 0x101,
+};
+
+#define DAVINCI_UART2_CLKID	(cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+						: get_async3_src())
+
+#define DAVINCI_SPI1_CLKID	(cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+						: get_async3_src())
+
+int clk_get(enum davinci_clk_ids id);
+
+/* Boot config */
+struct davinci_syscfg_regs {
+	dv_reg	revid;
+	dv_reg	rsvd[13];
+	dv_reg	kick0;
+	dv_reg	kick1;
+	dv_reg	rsvd1[52];
+	dv_reg	mstpri[3];
+	dv_reg  rsvd2;
+	dv_reg	pinmux[20];
+	dv_reg	suspsrc;
+	dv_reg	chipsig;
+	dv_reg	chipsig_clr;
+	dv_reg	cfgchip0;
+	dv_reg	cfgchip1;
+	dv_reg	cfgchip2;
+	dv_reg	cfgchip3;
+	dv_reg	cfgchip4;
+};
+
+#define davinci_syscfg_regs \
+	((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
+
+#define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
+
+/* Emulation suspend bits */
+#define DAVINCI_SYSCFG_SUSPSRC_EMAC		(1 << 5)
+#define DAVINCI_SYSCFG_SUSPSRC_I2C		(1 << 16)
+#define DAVINCI_SYSCFG_SUSPSRC_SPI0		(1 << 21)
+#define DAVINCI_SYSCFG_SUSPSRC_SPI1		(1 << 22)
+#define DAVINCI_SYSCFG_SUSPSRC_UART0		(1 << 18)
+#define DAVINCI_SYSCFG_SUSPSRC_UART2		(1 << 20)
+#define DAVINCI_SYSCFG_SUSPSRC_TIMER0		(1 << 27)
+
+struct davinci_syscfg1_regs {
+	dv_reg	vtpio_ctl;
+	dv_reg	ddr_slew;
+	dv_reg	deepsleep;
+	dv_reg	pupd_ena;
+	dv_reg	pupd_sel;
+	dv_reg	rxactive;
+	dv_reg	pwrdwn;
+};
+
+#define davinci_syscfg1_regs \
+	((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
+
+#define DDR_SLEW_CMOSEN_BIT	4
+#define DDR_SLEW_DDR_PDENA_BIT	5
+
+#define VTP_POWERDWN		(1 << 6)
+#define VTP_LOCK		(1 << 7)
+#define VTP_CLKRZ		(1 << 13)
+#define VTP_READY		(1 << 15)
+#define VTP_IOPWRDWN		(1 << 14)
+
+#define DV_SYSCFG_KICK0_UNLOCK	0x83e70b13
+#define DV_SYSCFG_KICK1_UNLOCK	0x95a4f1e0
+
+/* Interrupt controller */
+struct davinci_aintc_regs {
+	dv_reg	revid;
+	dv_reg	cr;
+	dv_reg	dummy0[2];
+	dv_reg	ger;
+	dv_reg	dummy1[219];
+	dv_reg	ecr1;
+	dv_reg	ecr2;
+	dv_reg	ecr3;
+	dv_reg	dummy2[1117];
+	dv_reg	hier;
+};
+
+#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
+
+struct davinci_uart_ctrl_regs {
+	dv_reg	revid1;
+	dv_reg	revid2;
+	dv_reg	pwremu_mgmt;
+	dv_reg	mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
+
+#define davinci_uart0_ctrl_regs \
+	((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
+#define davinci_uart1_ctrl_regs \
+	((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
+#define davinci_uart2_ctrl_regs \
+	((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE	(1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)
+
+static inline int cpu_is_da830(void)
+{
+	unsigned int jtag_id	= REG(JTAG_ID_REG);
+	unsigned short part_no	= (jtag_id >> 12) & 0xffff;
+
+	return ((part_no == 0xb7df) ? 1 : 0);
+}
+static inline int cpu_is_da850(void)
+{
+	unsigned int jtag_id    = REG(JTAG_ID_REG);
+	unsigned short part_no  = (jtag_id >> 12) & 0xffff;
+
+	return ((part_no == 0xb7d1) ? 1 : 0);
+}
+
+static inline enum davinci_clk_ids get_async3_src(void)
+{
+	return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
+			DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
+}
+
+#endif /* CONFIG_SOC_DA8XX */
+
+#if defined(CONFIG_SOC_DM365)
+#include <asm/arch/aintc_defs.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pll_defs.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/syscfg_defs.h>
+#include <asm/arch/timer_defs.h>
+
+#define TMPBUF			0x00017ff8
+#define TMPSTATUS		0x00017ff0
+#define DV_TMPBUF_VAL		0x591b3ed7
+#define FLAG_PORRST		0x00000001
+#define FLAG_WDTRST		0x00000002
+#define FLAG_FLGON		0x00000004
+#define FLAG_FLGOFF		0x00000010
+
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/i2c_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/i2c_defs.h
new file mode 100644
index 000000000..06da8947b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/i2c_defs.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2004-2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _I2C_DEFS_H_
+#define _I2C_DEFS_H_
+
+#ifndef CONFIG_SOC_DA8XX
+#define I2C_BASE		0x01c21000
+#else
+#define I2C_BASE		0x01c22000
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/nand_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/nand_defs.h
new file mode 100644
index 000000000..dee1c6f81
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/nand_defs.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts shamelesly stolen from Linux Kernel source tree.
+ *
+ * ------------------------------------------------------------
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_SOC_DM646X
+#define	MASK_CLE	0x80000
+#define	MASK_ALE	0x40000
+#else
+#define	MASK_CLE	0x10
+#define	MASK_ALE	0x08
+#endif
+
+#ifdef CONFIG_SYS_NAND_MASK_CLE
+#undef MASK_CLE
+#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#endif
+#ifdef CONFIG_SYS_NAND_MASK_ALE
+#undef MASK_ALE
+#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#endif
+
+#define NAND_READ_START		0x00
+#define NAND_READ_END		0x30
+#define NAND_STATUS		0x70
+
+extern void davinci_nand_init(struct nand_chip *nand);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pinmux_defs.h
new file mode 100644
index 000000000..2d82af554
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pinmux_defs.h
@@ -0,0 +1,57 @@
+/*
+ * Pinmux configurations for the DAxxx SoCs
+ *
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_PINMUX_DEFS_H
+#define __ASM_ARCH_PINMUX_DEFS_H
+
+#include <asm/arch/davinci_misc.h>
+#include <config.h>
+
+/* SPI0 pin muxer settings */
+extern const struct pinmux_config spi0_pins_base[3];
+extern const struct pinmux_config spi0_pins_scs0[1];
+extern const struct pinmux_config spi0_pins_ena[1];
+
+/* SPI1 pin muxer settings */
+extern const struct pinmux_config spi1_pins_base[3];
+extern const struct pinmux_config spi1_pins_scs0[1];
+
+/* UART pin muxer settings */
+extern const struct pinmux_config uart0_pins_txrx[2];
+extern const struct pinmux_config uart0_pins_rtscts[2];
+extern const struct pinmux_config uart1_pins_txrx[2];
+extern const struct pinmux_config uart2_pins_txrx[2];
+extern const struct pinmux_config uart2_pins_rtscts[2];
+
+/* EMAC pin muxer settings*/
+extern const struct pinmux_config emac_pins_rmii[8];
+extern const struct pinmux_config emac_pins_rmii_clk_source[1];
+extern const struct pinmux_config emac_pins_mii[15];
+extern const struct pinmux_config emac_pins_mdio[2];
+
+/* I2C pin muxer settings */
+extern const struct pinmux_config i2c0_pins[2];
+extern const struct pinmux_config i2c1_pins[2];
+
+/* EMIFA pin muxer settings */
+extern const struct pinmux_config emifa_pins[40];
+extern const struct pinmux_config emifa_pins_cs0[1];
+extern const struct pinmux_config emifa_pins_cs2[1];
+extern const struct pinmux_config emifa_pins_cs3[1];
+extern const struct pinmux_config emifa_pins_cs4[1];
+extern const struct pinmux_config emifa_pins_nand[12];
+extern const struct pinmux_config emifa_pins_nor[43];
+
+/* USB pin mux setting */
+extern const struct pinmux_config usb_pins[1];
+
+/* MMC pin muxer settings */
+extern const struct pinmux_config mmc0_pins_8bit[10];
+extern const struct pinmux_config mmc0_pins[6];
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pll_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pll_defs.h
new file mode 100644
index 000000000..d083cccad
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _DV_PLL_DEFS_H_
+#define _DV_PLL_DEFS_H_
+
+struct dv_pll_regs {
+	unsigned int	pid;		/* 0x00 */
+	unsigned char	rsvd0[224];	/* 0x04 */
+	unsigned int	rstype;		/* 0xe4 */
+	unsigned char	rsvd1[24];	/* 0xe8 */
+	unsigned int	pllctl;		/* 0x100 */
+	unsigned char	rsvd2[4];	/* 0x104 */
+	unsigned int	secctl;		/* 0x108 */
+	unsigned int	rv;		/* 0x10c */
+	unsigned int	pllm;		/* 0x110 */
+	unsigned int	prediv;		/* 0x114 */
+	unsigned int	plldiv1;	/* 0x118 */
+	unsigned int	plldiv2;	/* 0x11c */
+	unsigned int	plldiv3;	/* 0x120 */
+	unsigned int	oscdiv1;	/* 0x124 */
+	unsigned int	postdiv;	/* 0x128 */
+	unsigned int	bpdiv;		/* 0x12c */
+	unsigned char	rsvd5[8];	/* 0x130 */
+	unsigned int	pllcmd;		/* 0x138 */
+	unsigned int	pllstat;	/* 0x13c */
+	unsigned int	alnctl;		/* 0x140 */
+	unsigned int	dchange;	/* 0x144 */
+	unsigned int	cken;		/* 0x148 */
+	unsigned int	ckstat;		/* 0x14c */
+	unsigned int	systat;		/* 0x150 */
+	unsigned char	rsvd6[12];	/* 0x154 */
+	unsigned int	plldiv4;	/* 0x160 */
+	unsigned int	plldiv5;	/* 0x164 */
+	unsigned int	plldiv6;	/* 0x168 */
+	unsigned int	plldiv7;	/* 0x16C */
+	unsigned int	plldiv8;	/* 0x170 */
+	unsigned int	plldiv9;	/* 0x174 */
+};
+
+#define PLL_MASTER_LOCK	(1 << 4)
+
+#define PLLCTL_CLOCK_MODE_SHIFT	8
+#define PLLCTL_PLLEN	(1 << 0)
+#define PLLCTL_PLLPWRDN	(1 << 1)
+#define PLLCTL_PLLRST	(1 << 3)
+#define PLLCTL_PLLDIS	(1 << 4)
+#define PLLCTL_PLLENSRC	(1 << 5)
+#define PLLCTL_RES_9	(1 << 8)
+#define PLLCTL_EXTCLKSRC	(1 << 9)
+
+#define PLL_DIVEN	(1 << 15)
+#define PLL_POSTDEN	PLL_DIVEN
+
+#define PLL_SCSCFG3_DIV45PENA	(1 << 2)
+#define PLL_SCSCFG3_EMA_CLKSRC	(1 << 1)
+
+#define PLL_RSTYPE_POR		(1 << 0)
+#define PLL_RSTYPE_XWRST	(1 << 1)
+
+#define PLLSECCTL_TINITZ	(1 << 16)
+#define PLLSECCTL_TENABLE	(1 << 17)
+#define PLLSECCTL_TENABLEDIV	(1 << 18)
+#define PLLSECCTL_STOPMODE	(1 << 22)
+
+#define PLLCMD_GOSET		(1 << 0)
+#define PLLCMD_GOSTAT		(1 << 0)
+
+#define PLL0_LOCK		0x07000000
+#define PLL1_LOCK		0x07000000
+
+#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
+
+#define ARM_PLLDIV	(offsetof(struct dv_pll_regs, plldiv2))
+#define DDR_PLLDIV	(offsetof(struct dv_pll_regs, plldiv7))
+#define SPI_PLLDIV	(offsetof(struct dv_pll_regs, plldiv4))
+
+unsigned int davinci_clk_get(unsigned int div);
+#endif /* _DV_PLL_DEFS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/psc_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/psc_defs.h
new file mode 100644
index 000000000..bcb558049
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/psc_defs.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _DV_PSC_DEFS_H_
+#define _DV_PSC_DEFS_H_
+
+/*
+ * Power/Sleep Ctrl Register structure
+ * See sprufb3.pdf, Chapter 7
+ */
+struct dv_psc_regs {
+	unsigned int	pid;		/* 0x000 */
+	unsigned char	rsvd0[16];	/* 0x004 */
+	unsigned char	rsvd1[4];	/* 0x014 */
+	unsigned int	inteval;	/* 0x018 */
+	unsigned char	rsvd2[36];	/* 0x01C */
+	unsigned int	merrpr0;	/* 0x040 */
+	unsigned int	merrpr1;	/* 0x044 */
+	unsigned char	rsvd3[8];	/* 0x048 */
+	unsigned int	merrcr0;	/* 0x050 */
+	unsigned int	merrcr1;	/* 0x054 */
+	unsigned char	rsvd4[8];	/* 0x058 */
+	unsigned int	perrpr;		/* 0x060 */
+	unsigned char	rsvd5[4];	/* 0x064 */
+	unsigned int	perrcr;		/* 0x068 */
+	unsigned char	rsvd6[4];	/* 0x06C */
+	unsigned int	epcpr;		/* 0x070 */
+	unsigned char	rsvd7[4];	/* 0x074 */
+	unsigned int	epccr;		/* 0x078 */
+	unsigned char	rsvd8[144];	/* 0x07C */
+	unsigned char	rsvd9[20];	/* 0x10C */
+	unsigned int	ptcmd;		/* 0x120 */
+	unsigned char	rsvd10[4];	/* 0x124 */
+	unsigned int	ptstat;		/* 0x128 */
+	unsigned char	rsvd11[212];	/* 0x12C */
+	unsigned int	pdstat0;	/* 0x200 */
+	unsigned int	pdstat1;	/* 0x204 */
+	unsigned char	rsvd12[248];	/* 0x208 */
+	unsigned int	pdctl0;		/* 0x300 */
+	unsigned int	pdctl1;		/* 0x304 */
+	unsigned char	rsvd13[536];	/* 0x308 */
+	unsigned int	mckout0;	/* 0x520 */
+	unsigned int	mckout1;	/* 0x524 */
+	unsigned char	rsvd14[728];	/* 0x528 */
+	unsigned int	mdstat[52];	/* 0x800 */
+	unsigned char	rsvd15[304];	/* 0x8D0 */
+	unsigned int	mdctl[52];	/* 0xA00 */
+};
+
+/* PSC constants */
+#define EMURSTIE_MASK	(0x00000200)
+
+#define PD0		(0)
+
+#define PSC_ENABLE		(0x3)
+#define PSC_DISABLE		(0x2)
+#define PSC_SYNCRESET		(0x1)
+#define PSC_SWRSTDISABLE	(0x0)
+
+#define PSC_GOSTAT		(1 << 0)
+#define PSC_MD_STATE_MSK	(0x1f)
+
+#define PSC_CMD_GO		(1 << 0)
+
+#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
+
+#endif /* _DV_PSC_DEFS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
new file mode 100644
index 000000000..9aa3f4ab2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
@@ -0,0 +1,164 @@
+/*
+ * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SDMMC_DEFS_H_
+#define _SDMMC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+/* MMC Control Reg fields */
+#define MMCCTL_DATRST		(1 << 0)
+#define MMCCTL_CMDRST		(1 << 1)
+#define MMCCTL_WIDTH_4_BIT	(1 << 2)
+#define MMCCTL_DATEG_DISABLED	(0 << 6)
+#define MMCCTL_DATEG_RISING	(1 << 6)
+#define MMCCTL_DATEG_FALLING	(2 << 6)
+#define MMCCTL_DATEG_BOTH	(3 << 6)
+#define MMCCTL_PERMDR_LE	(0 << 9)
+#define MMCCTL_PERMDR_BE	(1 << 9)
+#define MMCCTL_PERMDX_LE	(0 << 10)
+#define MMCCTL_PERMDX_BE	(1 << 10)
+
+/* MMC Clock Control Reg fields */
+#define MMCCLK_CLKEN		(1 << 8)
+#define MMCCLK_CLKRT_MASK	(0xFF << 0)
+
+/* MMC Status Reg0 fields */
+#define MMCST0_DATDNE		(1 << 0)
+#define MMCST0_BSYDNE		(1 << 1)
+#define MMCST0_RSPDNE		(1 << 2)
+#define MMCST0_TOUTRD		(1 << 3)
+#define MMCST0_TOUTRS		(1 << 4)
+#define MMCST0_CRCWR		(1 << 5)
+#define MMCST0_CRCRD		(1 << 6)
+#define MMCST0_CRCRS		(1 << 7)
+#define MMCST0_DXRDY		(1 << 9)
+#define MMCST0_DRRDY		(1 << 10)
+#define MMCST0_DATED		(1 << 11)
+#define MMCST0_TRNDNE		(1 << 12)
+
+#define MMCST0_ERR_MASK		(0x00F8)
+
+/* MMC Status Reg1 fields */
+#define MMCST1_BUSY		(1 << 0)
+#define MMCST1_CLKSTP		(1 << 1)
+#define MMCST1_DXEMP		(1 << 2)
+#define MMCST1_DRFUL		(1 << 3)
+#define MMCST1_DAT3ST		(1 << 4)
+#define MMCST1_FIFOEMP		(1 << 5)
+#define MMCST1_FIFOFUL		(1 << 6)
+
+/* MMC INT Mask Reg fields */
+#define MMCIM_EDATDNE		(1 << 0)
+#define MMCIM_EBSYDNE		(1 << 1)
+#define MMCIM_ERSPDNE		(1 << 2)
+#define MMCIM_ETOUTRD		(1 << 3)
+#define MMCIM_ETOUTRS		(1 << 4)
+#define MMCIM_ECRCWR		(1 << 5)
+#define MMCIM_ECRCRD		(1 << 6)
+#define MMCIM_ECRCRS		(1 << 7)
+#define MMCIM_EDXRDY		(1 << 9)
+#define MMCIM_EDRRDY		(1 << 10)
+#define MMCIM_EDATED		(1 << 11)
+#define MMCIM_ETRNDNE		(1 << 12)
+
+#define MMCIM_MASKALL		(0xFFFFFFFF)
+
+/* MMC Resp Tout Reg fields */
+#define MMCTOR_TOR_MASK		(0xFF)		/* dont write to reg, | it */
+#define MMCTOR_TOD_20_16_SHIFT  (8)
+
+/* MMC Data Read Tout Reg fields */
+#define MMCTOD_TOD_0_15_MASK	(0xFFFF)
+
+/* MMC Block len Reg fields */
+#define MMCBLEN_BLEN_MASK	(0xFFF)
+
+/* MMC Num Blocks Reg fields */
+#define MMCNBLK_NBLK_MASK	(0xFFFF)
+#define MMCNBLK_NBLK_MAX	(0xFFFF)
+
+/* MMC Num Blocks Counter Reg fields */
+#define MMCNBLC_NBLC_MASK	(0xFFFF)
+
+/* MMC Cmd Reg fields */
+#define MMCCMD_CMD_MASK		(0x3F)
+#define MMCCMD_PPLEN		(1 << 7)
+#define MMCCMD_BSYEXP		(1 << 8)
+#define MMCCMD_RSPFMT_NONE	(0 << 9)
+#define MMCCMD_RSPFMT_R1567	(1 << 9)
+#define MMCCMD_RSPFMT_R2	(2 << 9)
+#define MMCCMD_RSPFMT_R3	(3 << 9)
+#define MMCCMD_DTRW		(1 << 11)
+#define MMCCMD_STRMTP		(1 << 12)
+#define MMCCMD_WDATX		(1 << 13)
+#define MMCCMD_INITCK		(1 << 14)
+#define MMCCMD_DCLR		(1 << 15)
+#define MMCCMD_DMATRIG		(1 << 16)
+
+/* FIFO control Reg fields */
+#define MMCFIFOCTL_FIFORST	(1 << 0)
+#define MMCFIFOCTL_FIFODIR	(1 << 1)
+#define MMCFIFOCTL_FIFOLEV	(1 << 2)
+#define MMCFIFOCTL_ACCWD_4	(0 << 3)	/* access width of 4 bytes */
+#define MMCFIFOCTL_ACCWD_3	(1 << 3)	/* access width of 3 bytes */
+#define MMCFIFOCTL_ACCWD_2	(2 << 3)	/* access width of 2 bytes */
+#define MMCFIFOCTL_ACCWD_1	(3 << 3)	/* access width of 1 byte */
+
+/* Davinci MMC Register definitions */
+struct davinci_mmc_regs {
+	dv_reg mmcctl;
+	dv_reg mmcclk;
+	dv_reg mmcst0;
+	dv_reg mmcst1;
+	dv_reg mmcim;
+	dv_reg mmctor;
+	dv_reg mmctod;
+	dv_reg mmcblen;
+	dv_reg mmcnblk;
+	dv_reg mmcnblc;
+	dv_reg mmcdrr;
+	dv_reg mmcdxr;
+	dv_reg mmccmd;
+	dv_reg mmcarghl;
+	dv_reg mmcrsp01;
+	dv_reg mmcrsp23;
+	dv_reg mmcrsp45;
+	dv_reg mmcrsp67;
+	dv_reg mmcdrsp;
+	dv_reg mmcetok;
+	dv_reg mmccidx;
+	dv_reg mmcckc;
+	dv_reg mmctorc;
+	dv_reg mmctodc;
+	dv_reg mmcblnc;
+	dv_reg sdioctl;
+	dv_reg sdiost0;
+	dv_reg sdioien;
+	dv_reg sdioist;
+	dv_reg mmcfifoctl;
+};
+
+/* Davinci MMC board definitions */
+struct davinci_mmc {
+	struct davinci_mmc_regs *reg_base;	/* Register base address */
+	uint input_clk;		/* Input clock to MMC controller */
+	uint host_caps;		/* Host capabilities */
+	uint voltages;		/* Host supported voltages */
+	uint version;		/* MMC Controller version */
+	struct mmc_config cfg;
+};
+
+enum {
+	MMC_CTLR_VERSION_1 = 0,	/* DM644x and DM355 */
+	MMC_CTLR_VERSION_2,	/* DA830 */
+};
+
+int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
+
+#endif /* _SDMMC_DEFS_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/spl.h
new file mode 100644
index 000000000..5afe0d4ba
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/spl.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NAND	1
+#define BOOT_DEVICE_SPI		2
+#define BOOT_DEVICE_MMC1	3
+#define BOOT_DEVICE_MMC2	4	/* dummy */
+#define BOOT_DEVICE_MMC2_2	5	/* dummy */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/syscfg_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/syscfg_defs.h
new file mode 100644
index 000000000..812088f37
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/syscfg_defs.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _DV_SYSCFG_DEFS_H_
+#define _DV_SYSCFG_DEFS_H_
+
+#ifndef CONFIG_SOC_DA8XX
+/* System Control Module register structure for DM365 */
+struct dv_sys_module_regs {
+	unsigned int	pinmux[5];	/* 0x00 */
+	unsigned int	bootcfg;	/* 0x14 */
+	unsigned int	arm_intmux;	/* 0x18 */
+	unsigned int	edma_evtmux;	/* 0x1C */
+	unsigned int	ddr_slew;	/* 0x20 */
+	unsigned int	clkout;		/* 0x24 */
+	unsigned int	device_id;	/* 0x28 */
+	unsigned int	vdac_config;	/* 0x2C */
+	unsigned int	timer64_ctl;	/* 0x30 */
+	unsigned int	usbbphy_ctl;	/* 0x34 */
+	unsigned int	misc;		/* 0x38 */
+	unsigned int	mstpri[2];	/* 0x3C */
+	unsigned int	vpss_clkctl;	/* 0x44 */
+	unsigned int	peri_clkctl;	/* 0x48 */
+	unsigned int	deepsleep;	/* 0x4C */
+	unsigned int	dft_enable;	/* 0x50 */
+	unsigned int	debounce[8];	/* 0x54 */
+	unsigned int	vtpiocr;	/* 0x74 */
+	unsigned int	pupdctl0;	/* 0x78 */
+	unsigned int	pupdctl1;	/* 0x7C */
+	unsigned int	hdimcopbt;	/* 0x80 */
+	unsigned int	pll0_config;	/* 0x84 */
+	unsigned int	pll1_config;	/* 0x88 */
+};
+
+#define VPTIO_RDY	(1 << 15)
+#define VPTIO_IOPWRDN	(1 << 14)
+#define VPTIO_CLRZ	(1 << 13)
+#define VPTIO_LOCK	(1 << 7)
+#define VPTIO_PWRDN	(1 << 6)
+
+#define VPSS_CLK_CTL_VPSS_CLKMD	(1 << 7)
+
+#define dv_sys_module_regs \
+	((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
+
+#endif /* !CONFIG_SOC_DA8XX */
+#endif /* _DV_SYSCFG_DEFS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/timer_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/timer_defs.h
new file mode 100644
index 000000000..94d18320d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-davinci/timer_defs.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2011 DENX Software Engineering GmbH
+ * Heiko Schocher <hs@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _TIMER_DEFS_H_
+#define _TIMER_DEFS_H_
+
+struct davinci_timer {
+	u_int32_t	pid12;
+	u_int32_t	emumgt;
+	u_int32_t	na1;
+	u_int32_t	na2;
+	u_int32_t	tim12;
+	u_int32_t	tim34;
+	u_int32_t	prd12;
+	u_int32_t	prd34;
+	u_int32_t	tcr;
+	u_int32_t	tgcr;
+	u_int32_t	wdtcr;
+};
+
+#define DV_TIMER_TCR_ENAMODE_MASK		3
+
+#define DV_TIMER_TCR_ENAMODE12_SHIFT		6
+#define DV_TIMER_TCR_CLKSRC12_SHIFT		8
+#define DV_TIMER_TCR_READRSTMODE12_SHIFT	10
+#define DV_TIMER_TCR_CAPMODE12_SHIFT		11
+#define DV_TIMER_TCR_CAPVTMODE12_SHIFT		12
+#define DV_TIMER_TCR_ENAMODE34_SHIFT		22
+#define DV_TIMER_TCR_CLKSRC34_SHIFT		24
+#define DV_TIMER_TCR_READRSTMODE34_SHIFT	26
+#define DV_TIMER_TCR_CAPMODE34_SHIFT		27
+#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT		28
+
+#define DV_WDT_ENABLE_SYS_RESET		0x00020000
+#define DV_WDT_TRIGGER_SYS_RESET	0x00020002
+
+#ifdef CONFIG_HW_WATCHDOG
+void davinci_hw_watchdog_enable(void);
+void davinci_hw_watchdog_reset(void);
+#endif
+#endif /* _TIMER_DEFS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h
new file mode 100644
index 000000000..9e7f2f348
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-ep93xx/ep93xx.h
@@ -0,0 +1,582 @@
+/*
+ * Cirrus Logic EP93xx register definitions.
+ *
+ * Copyright (C) 2009
+ * Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006
+ * Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
+ *
+ * Copyright (C) 2004 Ray Lehtiniemi
+ * Copyright (C) 2003 Cirrus Logic, Inc
+ * Copyright (C) 1999 ARM Limited.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define EP93XX_AHB_BASE			0x80000000
+#define EP93XX_APB_BASE			0x80800000
+
+/*
+ * 0x80000000 - 0x8000FFFF: DMA
+ */
+#define DMA_OFFSET			0x000000
+#define DMA_BASE			(EP93XX_AHB_BASE | DMA_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct dma_channel {
+	uint32_t control;
+	uint32_t interrupt;
+	uint32_t ppalloc;
+	uint32_t status;
+	uint32_t reserved0;
+	uint32_t remain;
+	uint32_t reserved1[2];
+	uint32_t maxcnt0;
+	uint32_t base0;
+	uint32_t current0;
+	uint32_t reserved2;
+	uint32_t maxcnt1;
+	uint32_t base1;
+	uint32_t current1;
+	uint32_t reserved3;
+};
+
+struct dma_regs {
+	struct dma_channel m2p_channel_0;
+	struct dma_channel m2p_channel_1;
+	struct dma_channel m2p_channel_2;
+	struct dma_channel m2p_channel_3;
+	struct dma_channel m2m_channel_0;
+	struct dma_channel m2m_channel_1;
+	struct dma_channel reserved0[2];
+	struct dma_channel m2p_channel_5;
+	struct dma_channel m2p_channel_4;
+	struct dma_channel m2p_channel_7;
+	struct dma_channel m2p_channel_6;
+	struct dma_channel m2p_channel_9;
+	struct dma_channel m2p_channel_8;
+	uint32_t channel_arbitration;
+	uint32_t reserved[15];
+	uint32_t global_interrupt;
+};
+#endif
+
+/*
+ * 0x80010000 - 0x8001FFFF: Ethernet MAC
+ */
+#define MAC_OFFSET			0x010000
+#define MAC_BASE			(EP93XX_AHB_BASE | MAC_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct mac_queue {
+	uint32_t badd;
+	union { /* deal with half-word aligned registers */
+		uint32_t blen;
+		union {
+			uint16_t filler;
+			uint16_t curlen;
+		};
+	};
+	uint32_t curadd;
+};
+
+struct mac_regs {
+	uint32_t rxctl;
+	uint32_t txctl;
+	uint32_t testctl;
+	uint32_t reserved0;
+	uint32_t miicmd;
+	uint32_t miidata;
+	uint32_t miists;
+	uint32_t reserved1;
+	uint32_t selfctl;
+	uint32_t inten;
+	uint32_t intstsp;
+	uint32_t intstsc;
+	uint32_t reserved2[2];
+	uint32_t diagad;
+	uint32_t diagdata;
+	uint32_t gt;
+	uint32_t fct;
+	uint32_t fcf;
+	uint32_t afp;
+	union {
+		struct {
+			uint32_t indad;
+			uint32_t indad_upper;
+		};
+		uint32_t hashtbl;
+	};
+	uint32_t reserved3[2];
+	uint32_t giintsts;
+	uint32_t giintmsk;
+	uint32_t giintrosts;
+	uint32_t giintfrc;
+	uint32_t txcollcnt;
+	uint32_t rxmissnct;
+	uint32_t rxruntcnt;
+	uint32_t reserved4;
+	uint32_t bmctl;
+	uint32_t bmsts;
+	uint32_t rxbca;
+	uint32_t reserved5;
+	struct mac_queue rxdq;
+	uint32_t rxdqenq;
+	struct mac_queue rxstsq;
+	uint32_t rxstsqenq;
+	struct mac_queue txdq;
+	uint32_t txdqenq;
+	struct mac_queue txstsq;
+	uint32_t reserved6;
+	uint32_t rxbufthrshld;
+	uint32_t txbufthrshld;
+	uint32_t rxststhrshld;
+	uint32_t txststhrshld;
+	uint32_t rxdthrshld;
+	uint32_t txdthrshld;
+	uint32_t maxfrmlen;
+	uint32_t maxhdrlen;
+};
+#endif
+
+#define SELFCTL_RWP		(1 << 7)
+#define SELFCTL_GPO0		(1 << 5)
+#define SELFCTL_PUWE		(1 << 4)
+#define SELFCTL_PDWE		(1 << 3)
+#define SELFCTL_MIIL		(1 << 2)
+#define SELFCTL_RESET		(1 << 0)
+
+#define INTSTS_RWI		(1 << 30)
+#define INTSTS_RXMI		(1 << 29)
+#define INTSTS_RXBI		(1 << 28)
+#define INTSTS_RXSQI		(1 << 27)
+#define INTSTS_TXLEI		(1 << 26)
+#define INTSTS_ECIE		(1 << 25)
+#define INTSTS_TXUHI		(1 << 24)
+#define INTSTS_MOI		(1 << 18)
+#define INTSTS_TXCOI		(1 << 17)
+#define INTSTS_RXROI		(1 << 16)
+#define INTSTS_MIII		(1 << 12)
+#define INTSTS_PHYI		(1 << 11)
+#define INTSTS_TI		(1 << 10)
+#define INTSTS_AHBE		(1 << 8)
+#define INTSTS_OTHER		(1 << 4)
+#define INTSTS_TXSQ		(1 << 3)
+#define INTSTS_RXSQ		(1 << 2)
+
+#define BMCTL_MT		(1 << 13)
+#define BMCTL_TT		(1 << 12)
+#define BMCTL_UNH		(1 << 11)
+#define BMCTL_TXCHR		(1 << 10)
+#define BMCTL_TXDIS		(1 << 9)
+#define BMCTL_TXEN		(1 << 8)
+#define BMCTL_EH2		(1 << 6)
+#define BMCTL_EH1		(1 << 5)
+#define BMCTL_EEOB		(1 << 4)
+#define BMCTL_RXCHR		(1 << 2)
+#define BMCTL_RXDIS		(1 << 1)
+#define BMCTL_RXEN		(1 << 0)
+
+#define BMSTS_TXACT		(1 << 7)
+#define BMSTS_TP		(1 << 4)
+#define BMSTS_RXACT		(1 << 3)
+#define BMSTS_QID_MASK		0x07
+#define BMSTS_QID_RXDATA	0x00
+#define BMSTS_QID_TXDATA	0x01
+#define BMSTS_QID_RXSTS		0x02
+#define BMSTS_QID_TXSTS		0x03
+#define BMSTS_QID_RXDESC	0x04
+#define BMSTS_QID_TXDESC	0x05
+
+#define AFP_MASK		0x07
+#define AFP_IAPRIMARY		0x00
+#define AFP_IASECONDARY1	0x01
+#define AFP_IASECONDARY2	0x02
+#define AFP_IASECONDARY3	0x03
+#define AFP_TX			0x06
+#define AFP_HASH		0x07
+
+#define RXCTL_PAUSEA		(1 << 20)
+#define RXCTL_RXFCE1		(1 << 19)
+#define RXCTL_RXFCE0		(1 << 18)
+#define RXCTL_BCRC		(1 << 17)
+#define RXCTL_SRXON		(1 << 16)
+#define RXCTL_RCRCA		(1 << 13)
+#define RXCTL_RA		(1 << 12)
+#define RXCTL_PA		(1 << 11)
+#define RXCTL_BA		(1 << 10)
+#define RXCTL_MA		(1 << 9)
+#define RXCTL_IAHA		(1 << 8)
+#define RXCTL_IA3		(1 << 3)
+#define RXCTL_IA2		(1 << 2)
+#define RXCTL_IA1		(1 << 1)
+#define RXCTL_IA0		(1 << 0)
+
+#define TXCTL_DEFDIS		(1 << 7)
+#define TXCTL_MBE		(1 << 6)
+#define TXCTL_ICRC		(1 << 5)
+#define TXCTL_TPD		(1 << 4)
+#define TXCTL_OCOLL		(1 << 3)
+#define TXCTL_SP		(1 << 2)
+#define TXCTL_PB		(1 << 1)
+#define TXCTL_STXON		(1 << 0)
+
+#define MIICMD_REGAD_MASK	(0x001F)
+#define MIICMD_PHYAD_MASK	(0x03E0)
+#define MIICMD_OPCODE_MASK	(0xC000)
+#define MIICMD_PHYAD_8950	(0x0000)
+#define MIICMD_OPCODE_READ	(0x8000)
+#define MIICMD_OPCODE_WRITE	(0x4000)
+
+#define MIISTS_BUSY		(1 << 0)
+
+/*
+ * 0x80020000 - 0x8002FFFF: USB OHCI
+ */
+#define USB_OFFSET			0x020000
+#define USB_BASE			(EP93XX_AHB_BASE | USB_OFFSET)
+
+/*
+ * 0x80030000 - 0x8003FFFF: Raster engine
+ */
+#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
+#define RASTER_OFFSET			0x030000
+#define RASTER_BASE			(EP93XX_AHB_BASE | RASTER_OFFSET)
+#endif
+
+/*
+ * 0x80040000 - 0x8004FFFF: Graphics accelerator
+ */
+#if defined(CONFIG_EP9315)
+#define GFX_OFFSET			0x040000
+#define GFX_BASE			(EP93XX_AHB_BASE | GFX_OFFSET)
+#endif
+
+/*
+ * 0x80050000 - 0x8005FFFF: Reserved
+ */
+
+/*
+ * 0x80060000 - 0x8006FFFF: SDRAM controller
+ */
+#define SDRAM_OFFSET			0x060000
+#define SDRAM_BASE			(EP93XX_AHB_BASE | SDRAM_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct sdram_regs {
+	uint32_t reserved;
+	uint32_t glconfig;
+	uint32_t refrshtimr;
+	uint32_t bootsts;
+	uint32_t devcfg0;
+	uint32_t devcfg1;
+	uint32_t devcfg2;
+	uint32_t devcfg3;
+};
+#endif
+
+#define SDRAM_DEVCFG_EXTBUSWIDTH	(1 << 2)
+#define SDRAM_DEVCFG_BANKCOUNT		(1 << 3)
+#define SDRAM_DEVCFG_SROMLL		(1 << 5)
+#define SDRAM_DEVCFG_CASLAT_2		0x00010000
+#define SDRAM_DEVCFG_RASTOCAS_2		0x00200000
+
+#define GLCONFIG_INIT			(1 << 0)
+#define GLCONFIG_MRS			(1 << 1)
+#define GLCONFIG_SMEMBUSY		(1 << 5)
+#define GLCONFIG_LCR			(1 << 6)
+#define GLCONFIG_REARBEN		(1 << 7)
+#define GLCONFIG_CLKSHUTDOWN		(1 << 30)
+#define GLCONFIG_CKE			(1 << 31)
+
+/*
+ * 0x80070000 - 0x8007FFFF: Reserved
+ */
+
+/*
+ * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
+ */
+#define SMC_OFFSET			0x080000
+#define SMC_BASE			(EP93XX_AHB_BASE | SMC_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct smc_regs {
+	uint32_t bcr0;
+	uint32_t bcr1;
+	uint32_t bcr2;
+	uint32_t bcr3;
+	uint32_t reserved0[2];
+	uint32_t bcr6;
+	uint32_t bcr7;
+#if defined(CONFIG_EP9315)
+	uint32_t pcattribute;
+	uint32_t pccommon;
+	uint32_t pcio;
+	uint32_t reserved1[5];
+	uint32_t pcmciactrl;
+#endif
+};
+#endif
+
+#define SMC_BCR_IDCY_SHIFT	0
+#define SMC_BCR_WST1_SHIFT	5
+#define SMC_BCR_BLE		(1 << 10)
+#define SMC_BCR_WST2_SHIFT	11
+#define SMC_BCR_MW_SHIFT	28
+
+/*
+ * 0x80090000 - 0x8009FFFF: Boot ROM
+ */
+
+/*
+ * 0x800A0000 - 0x800AFFFF: IDE interface
+ */
+
+/*
+ * 0x800B0000 - 0x800BFFFF: VIC1
+ */
+
+/*
+ * 0x800C0000 - 0x800CFFFF: VIC2
+ */
+
+/*
+ * 0x800D0000 - 0x800FFFFF: Reserved
+ */
+
+/*
+ * 0x80800000 - 0x8080FFFF: Reserved
+ */
+
+/*
+ * 0x80810000 - 0x8081FFFF: Timers
+ */
+#define TIMER_OFFSET		0x010000
+#define TIMER_BASE		(EP93XX_APB_BASE | TIMER_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct timer {
+	uint32_t load;
+	uint32_t value;
+	uint32_t control;
+	uint32_t clear;
+};
+
+struct timer4 {
+	uint32_t value_low;
+	uint32_t value_high;
+};
+
+struct timer_regs {
+	struct timer timer1;
+	uint32_t reserved0[4];
+	struct timer timer2;
+	uint32_t reserved1[12];
+	struct timer4 timer4;
+	uint32_t reserved2[6];
+	struct timer timer3;
+};
+#endif
+
+/*
+ * 0x80820000 - 0x8082FFFF: I2S
+ */
+#define I2S_OFFSET		0x020000
+#define I2S_BASE		(EP93XX_APB_BASE | I2S_OFFSET)
+
+/*
+ * 0x80830000 - 0x8083FFFF: Security
+ */
+#define SECURITY_OFFSET		0x030000
+#define SECURITY_BASE		(EP93XX_APB_BASE | SECURITY_OFFSET)
+
+#define EXTENSIONID		(SECURITY_BASE + 0x2714)
+
+/*
+ * 0x80840000 - 0x8084FFFF: GPIO
+ */
+#define GPIO_OFFSET		0x040000
+#define GPIO_BASE		(EP93XX_APB_BASE | GPIO_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct gpio_int {
+	uint32_t inttype1;
+	uint32_t inttype2;
+	uint32_t eoi;
+	uint32_t inten;
+	uint32_t intsts;
+	uint32_t rawintsts;
+	uint32_t db;
+};
+
+struct gpio_regs {
+	uint32_t padr;
+	uint32_t pbdr;
+	uint32_t pcdr;
+	uint32_t pddr;
+	uint32_t paddr;
+	uint32_t pbddr;
+	uint32_t pcddr;
+	uint32_t pdddr;
+	uint32_t pedr;
+	uint32_t peddr;
+	uint32_t reserved0[2];
+	uint32_t pfdr;
+	uint32_t pfddr;
+	uint32_t pgdr;
+	uint32_t pgddr;
+	uint32_t phdr;
+	uint32_t phddr;
+	uint32_t reserved1;
+	uint32_t finttype1;
+	uint32_t finttype2;
+	uint32_t reserved2;
+	struct gpio_int pfint;
+	uint32_t reserved3[10];
+	struct gpio_int paint;
+	struct gpio_int pbint;
+	uint32_t eedrive;
+};
+#endif
+
+/*
+ * 0x80850000 - 0x8087FFFF: Reserved
+ */
+
+/*
+ * 0x80880000 - 0x8088FFFF: AAC
+ */
+#define AAC_OFFSET		0x080000
+#define AAC_BASE		(EP93XX_APB_BASE | AAC_OFFSET)
+
+/*
+ * 0x80890000 - 0x8089FFFF: Reserved
+ */
+
+/*
+ * 0x808A0000 - 0x808AFFFF: SPI
+ */
+#define SPI_OFFSET		0x0A0000
+#define SPI_BASE		(EP93XX_APB_BASE | SPI_OFFSET)
+
+/*
+ * 0x808B0000 - 0x808BFFFF: IrDA
+ */
+#define IRDA_OFFSET		0x0B0000
+#define IRDA_BASE		(EP93XX_APB_BASE | IRDA_OFFSET)
+
+/*
+ * 0x808C0000 - 0x808CFFFF: UART1
+ */
+#define UART1_OFFSET		0x0C0000
+#define UART1_BASE		(EP93XX_APB_BASE | UART1_OFFSET)
+
+/*
+ * 0x808D0000 - 0x808DFFFF: UART2
+ */
+#define UART2_OFFSET		0x0D0000
+#define UART2_BASE		(EP93XX_APB_BASE | UART2_OFFSET)
+
+/*
+ * 0x808E0000 - 0x808EFFFF: UART3
+ */
+#define UART3_OFFSET		0x0E0000
+#define UART3_BASE		(EP93XX_APB_BASE | UART3_OFFSET)
+
+/*
+ * 0x808F0000 - 0x808FFFFF: Key Matrix
+ */
+#define KEY_OFFSET		0x0F0000
+#define KEY_BASE		(EP93XX_APB_BASE | KEY_OFFSET)
+
+/*
+ * 0x80900000 - 0x8090FFFF: Touchscreen
+ */
+#define TOUCH_OFFSET		0x900000
+#define TOUCH_BASE		(EP93XX_APB_BASE | TOUCH_OFFSET)
+
+/*
+ * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
+ */
+#define PWM_OFFSET		0x910000
+#define PWM_BASE		(EP93XX_APB_BASE | PWM_OFFSET)
+
+/*
+ * 0x80920000 - 0x8092FFFF: Real time clock
+ */
+#define RTC_OFFSET		0x920000
+#define RTC_BASE		(EP93XX_APB_BASE | RTC_OFFSET)
+
+/*
+ * 0x80930000 - 0x8093FFFF: Syscon
+ */
+#define SYSCON_OFFSET		0x930000
+#define SYSCON_BASE		(EP93XX_APB_BASE | SYSCON_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct syscon_regs {
+	uint32_t pwrsts;
+	uint32_t pwrcnt;
+	uint32_t halt;
+	uint32_t stby;
+	uint32_t reserved0[2];
+	uint32_t teoi;
+	uint32_t stfclr;
+	uint32_t clkset1;
+	uint32_t clkset2;
+	uint32_t reserved1[6];
+	uint32_t scratch0;
+	uint32_t scratch1;
+	uint32_t reserved2[2];
+	uint32_t apbwait;
+	uint32_t bustmstrarb;
+	uint32_t bootmodeclr;
+	uint32_t reserved3[9];
+	uint32_t devicecfg;
+	uint32_t vidclkdiv;
+	uint32_t mirclkdiv;
+	uint32_t i2sclkdiv;
+	uint32_t keytchclkdiv;
+	uint32_t chipid;
+	uint32_t reserved4;
+	uint32_t syscfg;
+	uint32_t reserved5[8];
+	uint32_t sysswlock;
+};
+#else
+#define SYSCON_SCRATCH0		(SYSCON_BASE + 0x0040)
+#endif
+
+#define SYSCON_PWRCNT_UART_BAUD			(1 << 29)
+
+#define SYSCON_CLKSET_PLL_X2IPD_SHIFT		0
+#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT		5
+#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT		11
+#define SYSCON_CLKSET_PLL_PS_SHIFT		16
+#define SYSCON_CLKSET1_PCLK_DIV_SHIFT		18
+#define SYSCON_CLKSET1_HCLK_DIV_SHIFT		20
+#define SYSCON_CLKSET1_NBYP1			(1 << 23)
+#define SYSCON_CLKSET1_FCLK_DIV_SHIFT		25
+
+#define SYSCON_CLKSET2_PLL2_EN			(1 << 18)
+#define SYSCON_CLKSET2_NBYP2			(1 << 19)
+#define SYSCON_CLKSET2_USB_DIV_SHIFT		28
+
+#define SYSCON_CHIPID_REV_MASK			0xF0000000
+#define SYSCON_DEVICECFG_SWRST			(1 << 31)
+
+/*
+ * 0x80930000 - 0x8093FFFF: Watchdog Timer
+ */
+#define WATCHDOG_OFFSET		0x940000
+#define WATCHDOG_BASE		(EP93XX_APB_BASE | WATCHDOG_OFFSET)
+
+/*
+ * 0x80950000 - 0x9000FFFF: Reserved
+ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/adc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/adc.h
new file mode 100644
index 000000000..a0e26d705
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/adc.h
@@ -0,0 +1,26 @@
+/*
+ *  Copyright (C) 2010 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_ADC_H_
+#define __ASM_ARM_ARCH_ADC_H_
+
+#ifndef __ASSEMBLY__
+struct s5p_adc {
+	unsigned int adccon;
+	unsigned int adctsc;
+	unsigned int adcdly;
+	unsigned int adcdat0;
+	unsigned int adcdat1;
+	unsigned int adcupdn;
+	unsigned int adcclrint;
+	unsigned int adcmux;
+	unsigned int adcclrintpndnup;
+};
+#endif
+
+#endif /* __ASM_ARM_ARCH_ADC_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/board.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/board.h
new file mode 100644
index 000000000..1b1cd0dd9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/board.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EXYNOS_BOARD_H
+#define _EXYNOS_BOARD_H
+
+/*
+ * Exynos baord specific changes for
+ * board_init
+ */
+int exynos_init(void);
+
+/*
+ * Exynos board specific changes for
+ * board_early_init_f
+ */
+int exynos_early_init_f(void);
+
+/*
+ * Exynos board specific changes for
+ * board_power_init
+ */
+int exynos_power_init(void);
+
+#endif	/* EXYNOS_BOARD_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clk.h
new file mode 100644
index 000000000..cdeef324c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clk.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_CLK_H_
+#define __ASM_ARM_ARCH_CLK_H_
+
+#define APLL	0
+#define MPLL	1
+#define EPLL	2
+#define HPLL	3
+#define VPLL	4
+#define BPLL	5
+#define RPLL	6
+
+enum pll_src_bit {
+	EXYNOS_SRC_MPLL = 6,
+	EXYNOS_SRC_EPLL,
+	EXYNOS_SRC_VPLL,
+};
+
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_i2c_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+unsigned long get_mmc_clk(int dev_index);
+void set_mmc_clk(int dev_index, unsigned int div);
+unsigned long get_lcd_clk(void);
+void set_lcd_clk(void);
+void set_mipi_clk(void);
+int set_i2s_clk_source(unsigned int i2s_id);
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
+				unsigned int i2s_id);
+int set_epll_clk(unsigned long rate);
+int set_spi_clk(int periph_id, unsigned int rate);
+
+/**
+ * get the clk frequency of the required peripheral
+ *
+ * @param peripheral	Peripheral id
+ *
+ * @return frequency of the peripheral clk
+ */
+unsigned long clock_get_periph_rate(int peripheral);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clock.h
new file mode 100644
index 000000000..8259b92b8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/clock.h
@@ -0,0 +1,1393 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H_
+#define __ASM_ARM_ARCH_CLOCK_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_clock {
+	unsigned char	res1[0x4200];
+	unsigned int	src_leftbus;
+	unsigned char	res2[0x1fc];
+	unsigned int	mux_stat_leftbus;
+	unsigned char	res4[0xfc];
+	unsigned int	div_leftbus;
+	unsigned char	res5[0xfc];
+	unsigned int	div_stat_leftbus;
+	unsigned char	res6[0x1fc];
+	unsigned int	gate_ip_leftbus;
+	unsigned char	res7[0x1fc];
+	unsigned int	clkout_leftbus;
+	unsigned int	clkout_leftbus_div_stat;
+	unsigned char	res8[0x37f8];
+	unsigned int	src_rightbus;
+	unsigned char	res9[0x1fc];
+	unsigned int	mux_stat_rightbus;
+	unsigned char	res10[0xfc];
+	unsigned int	div_rightbus;
+	unsigned char	res11[0xfc];
+	unsigned int	div_stat_rightbus;
+	unsigned char	res12[0x1fc];
+	unsigned int	gate_ip_rightbus;
+	unsigned char	res13[0x1fc];
+	unsigned int	clkout_rightbus;
+	unsigned int	clkout_rightbus_div_stat;
+	unsigned char	res14[0x3608];
+	unsigned int	epll_lock;
+	unsigned char	res15[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res16[0xec];
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned char	res17[0x8];
+	unsigned int	vpll_con0;
+	unsigned int	vpll_con1;
+	unsigned char	res18[0xe8];
+	unsigned int	src_top0;
+	unsigned int	src_top1;
+	unsigned char	res19[0x8];
+	unsigned int	src_cam;
+	unsigned int	src_tv;
+	unsigned int	src_mfc;
+	unsigned int	src_g3d;
+	unsigned int	src_image;
+	unsigned int	src_lcd0;
+	unsigned int	src_lcd1;
+	unsigned int	src_maudio;
+	unsigned int	src_fsys;
+	unsigned char	res20[0xc];
+	unsigned int	src_peril0;
+	unsigned int	src_peril1;
+	unsigned char	res21[0xb8];
+	unsigned int	src_mask_top;
+	unsigned char	res22[0xc];
+	unsigned int	src_mask_cam;
+	unsigned int	src_mask_tv;
+	unsigned char	res23[0xc];
+	unsigned int	src_mask_lcd0;
+	unsigned int	src_mask_lcd1;
+	unsigned int	src_mask_maudio;
+	unsigned int	src_mask_fsys;
+	unsigned char	res24[0xc];
+	unsigned int	src_mask_peril0;
+	unsigned int	src_mask_peril1;
+	unsigned char	res25[0xb8];
+	unsigned int	mux_stat_top;
+	unsigned char	res26[0x14];
+	unsigned int	mux_stat_mfc;
+	unsigned int	mux_stat_g3d;
+	unsigned int	mux_stat_image;
+	unsigned char	res27[0xdc];
+	unsigned int	div_top;
+	unsigned char	res28[0xc];
+	unsigned int	div_cam;
+	unsigned int	div_tv;
+	unsigned int	div_mfc;
+	unsigned int	div_g3d;
+	unsigned int	div_image;
+	unsigned int	div_lcd0;
+	unsigned int	div_lcd1;
+	unsigned int	div_maudio;
+	unsigned int	div_fsys0;
+	unsigned int	div_fsys1;
+	unsigned int	div_fsys2;
+	unsigned int	div_fsys3;
+	unsigned int	div_peril0;
+	unsigned int	div_peril1;
+	unsigned int	div_peril2;
+	unsigned int	div_peril3;
+	unsigned int	div_peril4;
+	unsigned int	div_peril5;
+	unsigned char	res29[0x18];
+	unsigned int	div2_ratio;
+	unsigned char	res30[0x8c];
+	unsigned int	div_stat_top;
+	unsigned char	res31[0xc];
+	unsigned int	div_stat_cam;
+	unsigned int	div_stat_tv;
+	unsigned int	div_stat_mfc;
+	unsigned int	div_stat_g3d;
+	unsigned int	div_stat_image;
+	unsigned int	div_stat_lcd0;
+	unsigned int	div_stat_lcd1;
+	unsigned int	div_stat_maudio;
+	unsigned int	div_stat_fsys0;
+	unsigned int	div_stat_fsys1;
+	unsigned int	div_stat_fsys2;
+	unsigned int	div_stat_fsys3;
+	unsigned int	div_stat_peril0;
+	unsigned int	div_stat_peril1;
+	unsigned int	div_stat_peril2;
+	unsigned int	div_stat_peril3;
+	unsigned int	div_stat_peril4;
+	unsigned int	div_stat_peril5;
+	unsigned char	res32[0x18];
+	unsigned int	div2_stat;
+	unsigned char	res33[0x29c];
+	unsigned int	gate_ip_cam;
+	unsigned int	gate_ip_tv;
+	unsigned int	gate_ip_mfc;
+	unsigned int	gate_ip_g3d;
+	unsigned int	gate_ip_image;
+	unsigned int	gate_ip_lcd0;
+	unsigned int	gate_ip_lcd1;
+	unsigned char	res34[0x4];
+	unsigned int	gate_ip_fsys;
+	unsigned char	res35[0x8];
+	unsigned int	gate_ip_gps;
+	unsigned int	gate_ip_peril;
+	unsigned char	res36[0xc];
+	unsigned int	gate_ip_perir;
+	unsigned char	res37[0xc];
+	unsigned int	gate_block;
+	unsigned char	res38[0x8c];
+	unsigned int	clkout_cmu_top;
+	unsigned int	clkout_cmu_top_div_stat;
+	unsigned char	res39[0x37f8];
+	unsigned int	src_dmc;
+	unsigned char	res40[0xfc];
+	unsigned int	src_mask_dmc;
+	unsigned char	res41[0xfc];
+	unsigned int	mux_stat_dmc;
+	unsigned char	res42[0xfc];
+	unsigned int	div_dmc0;
+	unsigned int	div_dmc1;
+	unsigned char	res43[0xf8];
+	unsigned int	div_stat_dmc0;
+	unsigned int	div_stat_dmc1;
+	unsigned char	res44[0x2f8];
+	unsigned int	gate_ip_dmc;
+	unsigned char	res45[0xfc];
+	unsigned int	clkout_cmu_dmc;
+	unsigned int	clkout_cmu_dmc_div_stat;
+	unsigned char	res46[0x5f8];
+	unsigned int	dcgidx_map0;
+	unsigned int	dcgidx_map1;
+	unsigned int	dcgidx_map2;
+	unsigned char	res47[0x14];
+	unsigned int	dcgperf_map0;
+	unsigned int	dcgperf_map1;
+	unsigned char	res48[0x18];
+	unsigned int	dvcidx_map;
+	unsigned char	res49[0x1c];
+	unsigned int	freq_cpu;
+	unsigned int	freq_dpm;
+	unsigned char	res50[0x18];
+	unsigned int	dvsemclk_en;
+	unsigned int	maxperf;
+	unsigned char	res51[0x2f78];
+	unsigned int	apll_lock;
+	unsigned char	res52[0x4];
+	unsigned int	mpll_lock;
+	unsigned char	res53[0xf4];
+	unsigned int	apll_con0;
+	unsigned int	apll_con1;
+	unsigned int	mpll_con0;
+	unsigned int	mpll_con1;
+	unsigned char	res54[0xf0];
+	unsigned int	src_cpu;
+	unsigned char	res55[0x1fc];
+	unsigned int	mux_stat_cpu;
+	unsigned char	res56[0xfc];
+	unsigned int	div_cpu0;
+	unsigned int	div_cpu1;
+	unsigned char	res57[0xf8];
+	unsigned int	div_stat_cpu0;
+	unsigned int	div_stat_cpu1;
+	unsigned char	res58[0x3f8];
+	unsigned int	clkout_cmu_cpu;
+	unsigned int	clkout_cmu_cpu_div_stat;
+	unsigned char	res59[0x5f8];
+	unsigned int	armclk_stopctrl;
+	unsigned int	atclk_stopctrl;
+	unsigned char	res60[0x8];
+	unsigned int	parityfail_status;
+	unsigned int	parityfail_clear;
+	unsigned char	res61[0xe8];
+	unsigned int	apll_con0_l8;
+	unsigned int	apll_con0_l7;
+	unsigned int	apll_con0_l6;
+	unsigned int	apll_con0_l5;
+	unsigned int	apll_con0_l4;
+	unsigned int	apll_con0_l3;
+	unsigned int	apll_con0_l2;
+	unsigned int	apll_con0_l1;
+	unsigned int	iem_control;
+	unsigned char	res62[0xdc];
+	unsigned int	apll_con1_l8;
+	unsigned int	apll_con1_l7;
+	unsigned int	apll_con1_l6;
+	unsigned int	apll_con1_l5;
+	unsigned int	apll_con1_l4;
+	unsigned int	apll_con1_l3;
+	unsigned int	apll_con1_l2;
+	unsigned int	apll_con1_l1;
+	unsigned char	res63[0xe0];
+	unsigned int	div_iem_l8;
+	unsigned int	div_iem_l7;
+	unsigned int	div_iem_l6;
+	unsigned int	div_iem_l5;
+	unsigned int	div_iem_l4;
+	unsigned int	div_iem_l3;
+	unsigned int	div_iem_l2;
+	unsigned int	div_iem_l1;
+};
+
+struct exynos4x12_clock {
+	unsigned char	res1[0x4200];
+	unsigned int	src_leftbus;
+	unsigned char	res2[0x1fc];
+	unsigned int	mux_stat_leftbus;
+	unsigned char	res3[0xfc];
+	unsigned int	div_leftbus;
+	unsigned char	res4[0xfc];
+	unsigned int	div_stat_leftbus;
+	unsigned char	res5[0x1fc];
+	unsigned int	gate_ip_leftbus;
+	unsigned char	res6[0x12c];
+	unsigned int	gate_ip_image;
+	unsigned char	res7[0xcc];
+	unsigned int	clkout_leftbus;
+	unsigned int	clkout_leftbus_div_stat;
+	unsigned char	res8[0x37f8];
+	unsigned int	src_rightbus;
+	unsigned char	res9[0x1fc];
+	unsigned int	mux_stat_rightbus;
+	unsigned char	res10[0xfc];
+	unsigned int	div_rightbus;
+	unsigned char	res11[0xfc];
+	unsigned int	div_stat_rightbus;
+	unsigned char	res12[0x1fc];
+	unsigned int	gate_ip_rightbus;
+	unsigned char	res13[0x15c];
+	unsigned int	gate_ip_perir;
+	unsigned char	res14[0x9c];
+	unsigned int	clkout_rightbus;
+	unsigned int	clkout_rightbus_div_stat;
+	unsigned char	res15[0x3608];
+	unsigned int	epll_lock;
+	unsigned char	res16[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res17[0xec];
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned int	epll_con2;
+	unsigned char	res18[0x4];
+	unsigned int	vpll_con0;
+	unsigned int	vpll_con1;
+	unsigned int	vpll_con2;
+	unsigned char	res19[0xe4];
+	unsigned int	src_top0;
+	unsigned int	src_top1;
+	unsigned char	res20[0x8];
+	unsigned int	src_cam;
+	unsigned int	src_tv;
+	unsigned int	src_mfc;
+	unsigned int	src_g3d;
+	unsigned char	res21[0x4];
+	unsigned int	src_lcd;
+	unsigned int	src_isp;
+	unsigned int	src_maudio;
+	unsigned int	src_fsys;
+	unsigned char	res22[0xc];
+	unsigned int	src_peril0;
+	unsigned int	src_peril1;
+	unsigned int	src_cam1;
+	unsigned char	res23[0xb4];
+	unsigned int	src_mask_top;
+	unsigned char	res24[0xc];
+	unsigned int	src_mask_cam;
+	unsigned int	src_mask_tv;
+	unsigned char	res25[0xc];
+	unsigned int	src_mask_lcd;
+	unsigned int	src_mask_isp;
+	unsigned int	src_mask_maudio;
+	unsigned int	src_mask_fsys;
+	unsigned char	res26[0xc];
+	unsigned int	src_mask_peril0;
+	unsigned int	src_mask_peril1;
+	unsigned char	res27[0xb8];
+	unsigned int	mux_stat_top0;
+	unsigned int	mux_stat_top1;
+	unsigned char	res28[0x10];
+	unsigned int	mux_stat_mfc;
+	unsigned int	mux_stat_g3d;
+	unsigned char	res29[0x28];
+	unsigned int	mux_stat_cam1;
+	unsigned char	res30[0xb4];
+	unsigned int	div_top;
+	unsigned char	res31[0xc];
+	unsigned int	div_cam;
+	unsigned int	div_tv;
+	unsigned int	div_mfc;
+	unsigned int	div_g3d;
+	unsigned char	res32[0x4];
+	unsigned int	div_lcd;
+	unsigned int	div_isp;
+	unsigned int	div_maudio;
+	unsigned int	div_fsys0;
+	unsigned int	div_fsys1;
+	unsigned int	div_fsys2;
+	unsigned int	div_fsys3;
+	unsigned int	div_peril0;
+	unsigned int	div_peril1;
+	unsigned int	div_peril2;
+	unsigned int	div_peril3;
+	unsigned int	div_peril4;
+	unsigned int	div_peril5;
+	unsigned int	div_cam1;
+	unsigned char	res33[0x14];
+	unsigned int	div2_ratio;
+	unsigned char	res34[0x8c];
+	unsigned int	div_stat_top;
+	unsigned char	res35[0xc];
+	unsigned int	div_stat_cam;
+	unsigned int	div_stat_tv;
+	unsigned int	div_stat_mfc;
+	unsigned int	div_stat_g3d;
+	unsigned char	res36[0x4];
+	unsigned int	div_stat_lcd;
+	unsigned int	div_stat_isp;
+	unsigned int	div_stat_maudio;
+	unsigned int	div_stat_fsys0;
+	unsigned int	div_stat_fsys1;
+	unsigned int	div_stat_fsys2;
+	unsigned int	div_stat_fsys3;
+	unsigned int	div_stat_peril0;
+	unsigned int	div_stat_peril1;
+	unsigned int	div_stat_peril2;
+	unsigned int	div_stat_peril3;
+	unsigned int	div_stat_peril4;
+	unsigned int	div_stat_peril5;
+	unsigned int	div_stat_cam1;
+	unsigned char	res37[0x14];
+	unsigned int	div2_stat;
+	unsigned char	res38[0x29c];
+	unsigned int	gate_ip_cam;
+	unsigned int	gate_ip_tv;
+	unsigned int	gate_ip_mfc;
+	unsigned int	gate_ip_g3d;
+	unsigned char	res39[0x4];
+	unsigned int	gate_ip_lcd;
+	unsigned int	gate_ip_isp;
+	unsigned char	res40[0x4];
+	unsigned int	gate_ip_fsys;
+	unsigned char	res41[0x8];
+	unsigned int	gate_ip_gps;
+	unsigned int	gate_ip_peril;
+	unsigned char	res42[0xc];
+	unsigned char	res43[0x4];
+	unsigned char	res44[0xc];
+	unsigned int	gate_block;
+	unsigned char	res45[0x8c];
+	unsigned int	clkout_cmu_top;
+	unsigned int	clkout_cmu_top_div_stat;
+	unsigned char	res46[0x3600];
+	unsigned int	mpll_lock;
+	unsigned char	res47[0xfc];
+	unsigned int	mpll_con0;
+	unsigned int	mpll_con1;
+	unsigned char	res48[0xf0];
+	unsigned int	src_dmc;
+	unsigned char	res49[0xfc];
+	unsigned int	src_mask_dmc;
+	unsigned char	res50[0xfc];
+	unsigned int	mux_stat_dmc;
+	unsigned char	res51[0xfc];
+	unsigned int	div_dmc0;
+	unsigned int	div_dmc1;
+	unsigned char	res52[0xf8];
+	unsigned int	div_stat_dmc0;
+	unsigned int	div_stat_dmc1;
+	unsigned char	res53[0xf8];
+	unsigned int	gate_bus_dmc0;
+	unsigned int	gate_bus_dmc1;
+	unsigned char	res54[0x1f8];
+	unsigned int	gate_ip_dmc0;
+	unsigned int	gate_ip_dmc1;
+	unsigned char	res55[0xf8];
+	unsigned int	clkout_cmu_dmc;
+	unsigned int	clkout_cmu_dmc_div_stat;
+	unsigned char	res56[0x5f8];
+	unsigned int	dcgidx_map0;
+	unsigned int	dcgidx_map1;
+	unsigned int	dcgidx_map2;
+	unsigned char	res57[0x14];
+	unsigned int	dcgperf_map0;
+	unsigned int	dcgperf_map1;
+	unsigned char	res58[0x18];
+	unsigned int	dvcidx_map;
+	unsigned char	res59[0x1c];
+	unsigned int	freq_cpu;
+	unsigned int	freq_dpm;
+	unsigned char	res60[0x18];
+	unsigned int	dvsemclk_en;
+	unsigned int	maxperf;
+	unsigned char	res61[0x8];
+	unsigned int	dmc_freq_ctrl;
+	unsigned int	dmc_pause_ctrl;
+	unsigned int	dddrphy_lock_ctrl;
+	unsigned int	c2c_state;
+	unsigned char	res62[0x2f60];
+	unsigned int	apll_lock;
+	unsigned char	res63[0x8];
+	unsigned char	res64[0xf4];
+	unsigned int	apll_con0;
+	unsigned int	apll_con1;
+	unsigned char	res65[0xf8];
+	unsigned int	src_cpu;
+	unsigned char	res66[0x1fc];
+	unsigned int	mux_stat_cpu;
+	unsigned char	res67[0xfc];
+	unsigned int	div_cpu0;
+	unsigned int	div_cpu1;
+	unsigned char	res68[0xf8];
+	unsigned int	div_stat_cpu0;
+	unsigned int	div_stat_cpu1;
+	unsigned char	res69[0x2f8];
+	unsigned int	clk_gate_ip_cpu;
+	unsigned char	res70[0xfc];
+	unsigned int	clkout_cmu_cpu;
+	unsigned int	clkout_cmu_cpu_div_stat;
+	unsigned char	res71[0x5f8];
+	unsigned int	armclk_stopctrl;
+	unsigned int	atclk_stopctrl;
+	unsigned char	res72[0x10];
+	unsigned char	res73[0x8];
+	unsigned int	pwr_ctrl;
+	unsigned int	pwr_ctrl2;
+	unsigned char	res74[0xd8];
+	unsigned int	apll_con0_l8;
+	unsigned int	apll_con0_l7;
+	unsigned int	apll_con0_l6;
+	unsigned int	apll_con0_l5;
+	unsigned int	apll_con0_l4;
+	unsigned int	apll_con0_l3;
+	unsigned int	apll_con0_l2;
+	unsigned int	apll_con0_l1;
+	unsigned int	iem_control;
+	unsigned char	res75[0xdc];
+	unsigned int	apll_con1_l8;
+	unsigned int	apll_con1_l7;
+	unsigned int	apll_con1_l6;
+	unsigned int	apll_con1_l5;
+	unsigned int	apll_con1_l4;
+	unsigned int	apll_con1_l3;
+	unsigned int	apll_con1_l2;
+	unsigned int	apll_con1_l1;
+	unsigned char	res76[0xe0];
+	unsigned int	div_iem_l8;
+	unsigned int	div_iem_l7;
+	unsigned int	div_iem_l6;
+	unsigned int	div_iem_l5;
+	unsigned int	div_iem_l4;
+	unsigned int	div_iem_l3;
+	unsigned int	div_iem_l2;
+	unsigned int	div_iem_l1;
+	unsigned char	res77[0xe0];
+	unsigned int	l2_status;
+	unsigned char	res78[0xc];
+	unsigned int	cpu_status;
+	unsigned char	res79[0xc];
+	unsigned int	ptm_status;
+	unsigned char	res80[0x2edc];
+	unsigned int	div_isp0;
+	unsigned int	div_isp1;
+	unsigned char	res81[0xf8];
+	unsigned int	div_stat_isp0;
+	unsigned int	div_stat_isp1;
+	unsigned char	res82[0x3f8];
+	unsigned int	gate_ip_isp0;
+	unsigned int	gate_ip_isp1;
+	unsigned char	res83[0x1f8];
+	unsigned int	clkout_cmu_isp;
+	unsigned int	clkout_cmu_ispd_div_stat;
+	unsigned char	res84[0xf8];
+	unsigned int	cmu_isp_spar0;
+	unsigned int	cmu_isp_spar1;
+	unsigned int	cmu_isp_spar2;
+	unsigned int	cmu_isp_spar3;
+};
+
+struct exynos5_clock {
+	unsigned int	apll_lock;
+	unsigned char	res1[0xfc];
+	unsigned int	apll_con0;
+	unsigned int	apll_con1;
+	unsigned char	res2[0xf8];
+	unsigned int	src_cpu;
+	unsigned char	res3[0x1fc];
+	unsigned int	mux_stat_cpu;
+	unsigned char	res4[0xfc];
+	unsigned int	div_cpu0;
+	unsigned int	div_cpu1;
+	unsigned char	res5[0xf8];
+	unsigned int	div_stat_cpu0;
+	unsigned int	div_stat_cpu1;
+	unsigned char	res6[0x1f8];
+	unsigned int	gate_sclk_cpu;
+	unsigned char	res7[0x1fc];
+	unsigned int	clkout_cmu_cpu;
+	unsigned int	clkout_cmu_cpu_div_stat;
+	unsigned char	res8[0x5f8];
+	unsigned int	armclk_stopctrl;
+	unsigned char	res9[0x0c];
+	unsigned int	parityfail_status;
+	unsigned int	parityfail_clear;
+	unsigned char	res10[0x8];
+	unsigned int	pwr_ctrl;
+	unsigned int	pwr_ctr2;
+	unsigned char	res11[0xd8];
+	unsigned int	apll_con0_l8;
+	unsigned int	apll_con0_l7;
+	unsigned int	apll_con0_l6;
+	unsigned int	apll_con0_l5;
+	unsigned int	apll_con0_l4;
+	unsigned int	apll_con0_l3;
+	unsigned int	apll_con0_l2;
+	unsigned int	apll_con0_l1;
+	unsigned int	iem_control;
+	unsigned char	res12[0xdc];
+	unsigned int	apll_con1_l8;
+	unsigned int	apll_con1_l7;
+	unsigned int	apll_con1_l6;
+	unsigned int	apll_con1_l5;
+	unsigned int	apll_con1_l4;
+	unsigned int	apll_con1_l3;
+	unsigned int	apll_con1_l2;
+	unsigned int	apll_con1_l1;
+	unsigned char	res13[0xe0];
+	unsigned int	div_iem_l8;
+	unsigned int	div_iem_l7;
+	unsigned int	div_iem_l6;
+	unsigned int	div_iem_l5;
+	unsigned int	div_iem_l4;
+	unsigned int	div_iem_l3;
+	unsigned int	div_iem_l2;
+	unsigned int	div_iem_l1;
+	unsigned char	res14[0x2ce0];
+	unsigned int	mpll_lock;
+	unsigned char	res15[0xfc];
+	unsigned int	mpll_con0;
+	unsigned int	mpll_con1;
+	unsigned char	res16[0xf8];
+	unsigned int	src_core0;
+	unsigned int	src_core1;
+	unsigned char	res17[0xf8];
+	unsigned int	src_mask_core;
+	unsigned char	res18[0x100];
+	unsigned int	mux_stat_core1;
+	unsigned char	res19[0xf8];
+	unsigned int	div_core0;
+	unsigned int	div_core1;
+	unsigned int	div_sysrgt;
+	unsigned char	res20[0xf4];
+	unsigned int	div_stat_core0;
+	unsigned int	div_stat_core1;
+	unsigned int	div_stat_sysrgt;
+	unsigned char	res21[0x2f4];
+	unsigned int	gate_ip_core;
+	unsigned int	gate_ip_sysrgt;
+	unsigned char	res22[0x8];
+	unsigned int	c2c_monitor;
+	unsigned char	res23[0xec];
+	unsigned int	clkout_cmu_core;
+	unsigned int	clkout_cmu_core_div_stat;
+	unsigned char	res24[0x5f8];
+	unsigned int	dcgidx_map0;
+	unsigned int	dcgidx_map1;
+	unsigned int	dcgidx_map2;
+	unsigned char	res25[0x14];
+	unsigned int	dcgperf_map0;
+	unsigned int	dcgperf_map1;
+	unsigned char	res26[0x18];
+	unsigned int	dvcidx_map;
+	unsigned char	res27[0x1c];
+	unsigned int	freq_cpu;
+	unsigned int	freq_dpm;
+	unsigned char	res28[0x18];
+	unsigned int	dvsemclk_en;
+	unsigned int	maxperf;
+	unsigned char	res29[0xf78];
+	unsigned int	c2c_config;
+	unsigned char	res30[0x24fc];
+	unsigned int	div_acp;
+	unsigned char	res31[0xfc];
+	unsigned int	div_stat_acp;
+	unsigned char	res32[0x1fc];
+	unsigned int	gate_ip_acp;
+	unsigned char	res33[0xfc];
+	unsigned int	div_syslft;
+	unsigned char	res34[0xc];
+	unsigned int	div_stat_syslft;
+	unsigned char	res35[0x1c];
+	unsigned int	gate_ip_syslft;
+	unsigned char	res36[0xcc];
+	unsigned int	clkout_cmu_acp;
+	unsigned int	clkout_cmu_acp_div_stat;
+	unsigned char	res37[0x8];
+	unsigned int	ufmc_config;
+	unsigned char	res38[0x38ec];
+	unsigned int	div_isp0;
+	unsigned int	div_isp1;
+	unsigned int	div_isp2;
+	unsigned char	res39[0xf4];
+	unsigned int	div_stat_isp0;
+	unsigned int	div_stat_isp1;
+	unsigned int	div_stat_isp2;
+	unsigned char	res40[0x3f4];
+	unsigned int	gate_ip_isp0;
+	unsigned int	gate_ip_isp1;
+	unsigned char	res41[0xf8];
+	unsigned int	gate_sclk_isp;
+	unsigned char	res42[0xc];
+	unsigned int	mcuisp_pwr_ctrl;
+	unsigned char	res43[0xec];
+	unsigned int	clkout_cmu_isp;
+	unsigned int	clkout_cmu_isp_div_stat;
+	unsigned char	res44[0x3618];
+	unsigned int	cpll_lock;
+	unsigned char	res45[0xc];
+	unsigned int	epll_lock;
+	unsigned char	res46[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res47[0xc];
+	unsigned int	gpll_lock;
+	unsigned char	res48[0xcc];
+	unsigned int	cpll_con0;
+	unsigned int	cpll_con1;
+	unsigned char	res49[0x8];
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned int	epll_con2;
+	unsigned char	res50[0x4];
+	unsigned int	vpll_con0;
+	unsigned int	vpll_con1;
+	unsigned int	vpll_con2;
+	unsigned char	res51[0x4];
+	unsigned int	gpll_con0;
+	unsigned int	gpll_con1;
+	unsigned char	res52[0xb8];
+	unsigned int	src_top0;
+	unsigned int	src_top1;
+	unsigned int	src_top2;
+	unsigned int	src_top3;
+	unsigned int	src_gscl;
+	unsigned char	res53[0x8];
+	unsigned int	src_disp1_0;
+	unsigned char	res54[0x10];
+	unsigned int	src_mau;
+	unsigned int	src_fsys;
+	unsigned int	src_gen;
+	unsigned char	res55[0x4];
+	unsigned int	src_peric0;
+	unsigned int	src_peric1;
+	unsigned char	res56[0x18];
+	unsigned int	sclk_src_isp;
+	unsigned char	res57[0x9c];
+	unsigned int	src_mask_top;
+	unsigned char	res58[0xc];
+	unsigned int	src_mask_gscl;
+	unsigned char	res59[0x8];
+	unsigned int	src_mask_disp1_0;
+	unsigned char	res60[0x4];
+	unsigned int	src_mask_mau;
+	unsigned char	res61[0x8];
+	unsigned int	src_mask_fsys;
+	unsigned int	src_mask_gen;
+	unsigned char	res62[0x8];
+	unsigned int	src_mask_peric0;
+	unsigned int	src_mask_peric1;
+	unsigned char	res63[0x18];
+	unsigned int	src_mask_isp;
+	unsigned char	res67[0x9c];
+	unsigned int	mux_stat_top0;
+	unsigned int	mux_stat_top1;
+	unsigned int	mux_stat_top2;
+	unsigned int	mux_stat_top3;
+	unsigned char	res68[0xf0];
+	unsigned int	div_top0;
+	unsigned int	div_top1;
+	unsigned char	res69[0x8];
+	unsigned int	div_gscl;
+	unsigned char	res70[0x8];
+	unsigned int	div_disp1_0;
+	unsigned char	res71[0xc];
+	unsigned int	div_gen;
+	unsigned char	res72[0x4];
+	unsigned int	div_mau;
+	unsigned int	div_fsys0;
+	unsigned int	div_fsys1;
+	unsigned int	div_fsys2;
+	unsigned char	res73[0x4];
+	unsigned int	div_peric0;
+	unsigned int	div_peric1;
+	unsigned int	div_peric2;
+	unsigned int	div_peric3;
+	unsigned int	div_peric4;
+	unsigned int	div_peric5;
+	unsigned char	res74[0x10];
+	unsigned int	sclk_div_isp;
+	unsigned char	res75[0xc];
+	unsigned int	div2_ratio0;
+	unsigned int	div2_ratio1;
+	unsigned char	res76[0x8];
+	unsigned int	div4_ratio;
+	unsigned char	res77[0x6c];
+	unsigned int	div_stat_top0;
+	unsigned int	div_stat_top1;
+	unsigned char	res78[0x8];
+	unsigned int	div_stat_gscl;
+	unsigned char	res79[0x8];
+	unsigned int	div_stat_disp1_0;
+	unsigned char	res80[0xc];
+	unsigned int	div_stat_gen;
+	unsigned char	res81[0x4];
+	unsigned int	div_stat_mau;
+	unsigned int	div_stat_fsys0;
+	unsigned int	div_stat_fsys1;
+	unsigned int	div_stat_fsys2;
+	unsigned char	res82[0x4];
+	unsigned int	div_stat_peric0;
+	unsigned int	div_stat_peric1;
+	unsigned int	div_stat_peric2;
+	unsigned int	div_stat_peric3;
+	unsigned int	div_stat_peric4;
+	unsigned int	div_stat_peric5;
+	unsigned char	res83[0x10];
+	unsigned int	sclk_div_stat_isp;
+	unsigned char	res84[0xc];
+	unsigned int	div2_stat0;
+	unsigned int	div2_stat1;
+	unsigned char	res85[0x8];
+	unsigned int	div4_stat;
+	unsigned char	res86[0x184];
+	unsigned int	gate_top_sclk_disp1;
+	unsigned int	gate_top_sclk_gen;
+	unsigned char	res87[0xc];
+	unsigned int	gate_top_sclk_mau;
+	unsigned int	gate_top_sclk_fsys;
+	unsigned char	res88[0xc];
+	unsigned int	gate_top_sclk_peric;
+	unsigned char	res89[0x1c];
+	unsigned int	gate_top_sclk_isp;
+	unsigned char	res90[0xac];
+	unsigned int	gate_ip_gscl;
+	unsigned char	res91[0x4];
+	unsigned int	gate_ip_disp1;
+	unsigned int	gate_ip_mfc;
+	unsigned int	gate_ip_g3d;
+	unsigned int	gate_ip_gen;
+	unsigned char	res92[0xc];
+	unsigned int	gate_ip_fsys;
+	unsigned char	res93[0x8];
+	unsigned int	gate_ip_peric;
+	unsigned char	res94[0xc];
+	unsigned int	gate_ip_peris;
+	unsigned char	res95[0x1c];
+	unsigned int	gate_block;
+	unsigned char	res96[0x1c];
+	unsigned int	mcuiop_pwr_ctrl;
+	unsigned char	res97[0x5c];
+	unsigned int	clkout_cmu_top;
+	unsigned int	clkout_cmu_top_div_stat;
+	unsigned char	res98[0x37f8];
+	unsigned int	src_lex;
+	unsigned char	res99[0x1fc];
+	unsigned int	mux_stat_lex;
+	unsigned char	res100[0xfc];
+	unsigned int	div_lex;
+	unsigned char	res101[0xfc];
+	unsigned int	div_stat_lex;
+	unsigned char	res102[0x1fc];
+	unsigned int	gate_ip_lex;
+	unsigned char	res103[0x1fc];
+	unsigned int	clkout_cmu_lex;
+	unsigned int	clkout_cmu_lex_div_stat;
+	unsigned char	res104[0x3af8];
+	unsigned int	div_r0x;
+	unsigned char	res105[0xfc];
+	unsigned int	div_stat_r0x;
+	unsigned char	res106[0x1fc];
+	unsigned int	gate_ip_r0x;
+	unsigned char	res107[0x1fc];
+	unsigned int	clkout_cmu_r0x;
+	unsigned int	clkout_cmu_r0x_div_stat;
+	unsigned char	res108[0x3af8];
+	unsigned int	div_r1x;
+	unsigned char	res109[0xfc];
+	unsigned int	div_stat_r1x;
+	unsigned char	res110[0x1fc];
+	unsigned int	gate_ip_r1x;
+	unsigned char	res111[0x1fc];
+	unsigned int	clkout_cmu_r1x;
+	unsigned int	clkout_cmu_r1x_div_stat;
+	unsigned char	res112[0x3608];
+	unsigned int	bpll_lock;
+	unsigned char	res113[0xfc];
+	unsigned int	bpll_con0;
+	unsigned int	bpll_con1;
+	unsigned char	res114[0xe8];
+	unsigned int	src_cdrex;
+	unsigned char	res115[0x1fc];
+	unsigned int	mux_stat_cdrex;
+	unsigned char	res116[0xfc];
+	unsigned int	div_cdrex;
+	unsigned char	res117[0xfc];
+	unsigned int	div_stat_cdrex;
+	unsigned char	res118[0x2fc];
+	unsigned int	gate_ip_cdrex;
+	unsigned char	res119[0x10];
+	unsigned int	dmc_freq_ctrl;
+	unsigned char	res120[0x4];
+	unsigned int	drex2_pause;
+	unsigned char	res121[0xe0];
+	unsigned int	clkout_cmu_cdrex;
+	unsigned int	clkout_cmu_cdrex_div_stat;
+	unsigned char	res122[0x8];
+	unsigned int	lpddr3phy_ctrl;
+	unsigned int	lpddr3phy_con0;
+	unsigned int	lpddr3phy_con1;
+	unsigned int	lpddr3phy_con2;
+	unsigned int	lpddr3phy_con3;
+	unsigned int	pll_div2_sel;
+	unsigned char	res123[0xf5d8];
+};
+
+struct exynos5420_clock {
+	unsigned int	apll_lock;			/* 0x10010000 */
+	unsigned char	res1[0xfc];
+	unsigned int	apll_con0;
+	unsigned int	apll_con1;
+	unsigned char	res2[0xf8];
+	unsigned int	src_cpu;
+	unsigned char	res3[0x1fc];
+	unsigned int	mux_stat_cpu;
+	unsigned char	res4[0xfc];
+	unsigned int	div_cpu0;		/* 0x10010500 */
+	unsigned int	div_cpu1;
+	unsigned char	res5[0xf8];
+	unsigned int	div_stat_cpu0;
+	unsigned int	div_stat_cpu1;
+	unsigned char	res6[0xf8];
+	unsigned int	gate_bus_cpu;
+	unsigned char	res7[0xfc];
+	unsigned int	gate_sclk_cpu;
+	unsigned char	res8[0x1fc];
+	unsigned int	clkout_cmu_cpu;		/* 0x10010a00 */
+	unsigned int	clkout_cmu_cpu_div_stat;
+	unsigned char	res9[0x5f8];
+	unsigned int	armclk_stopctrl;
+	unsigned char	res10[0x4];
+	unsigned int	arm_ema_ctrl;
+	unsigned int	arm_ema_status;
+	unsigned char	res11[0x10];
+	unsigned int	pwr_ctrl;
+	unsigned int	pwr_ctrl2;
+	unsigned char	res12[0xd8];
+	unsigned int	apll_con0_l8;		/* 0x1001100 */
+	unsigned int	apll_con0_l7;
+	unsigned int	apll_con0_l6;
+	unsigned int	apll_con0_l5;
+	unsigned int	apll_con0_l4;
+	unsigned int	apll_con0_l3;
+	unsigned int	apll_con0_l2;
+	unsigned int	apll_con0_l1;
+	unsigned int	iem_control;
+	unsigned char	res13[0xdc];
+	unsigned int	apll_con1_l8;		/* 0x10011200 */
+	unsigned int	apll_con1_l7;
+	unsigned int	apll_con1_l6;
+	unsigned int	apll_con1_l5;
+	unsigned int	apll_con1_l4;
+	unsigned int	apll_con1_l3;
+	unsigned int	apll_con1_l2;
+	unsigned int	apll_con1_l1;
+	unsigned char	res14[0xe0];
+	unsigned int	clkdiv_iem_l8;
+	unsigned int	clkdiv_iem_l7;		/* 0x10011304 */
+	unsigned int	clkdiv_iem_l6;
+	unsigned int	clkdiv_iem_l5;
+	unsigned int	clkdiv_iem_l4;
+	unsigned int	clkdiv_iem_l3;
+	unsigned int	clkdiv_iem_l2;
+	unsigned int	clkdiv_iem_l1;
+	unsigned char	res15[0xe0];
+	unsigned int	l2_status;
+	unsigned char	res16[0x0c];
+	unsigned int	cpu_status;		/* 0x10011410 */
+	unsigned char	res17[0x0c];
+	unsigned int	ptm_status;
+	unsigned char	res18[0xbdc];
+	unsigned int	cmu_cpu_spare0;
+	unsigned int	cmu_cpu_spare1;
+	unsigned int	cmu_cpu_spare2;
+	unsigned int	cmu_cpu_spare3;
+	unsigned int	cmu_cpu_spare4;
+	unsigned char	res19[0x1fdc];
+	unsigned int	cmu_cpu_version;
+	unsigned char	res20[0x20c];
+	unsigned int	src_cperi0;		/* 0x10014200 */
+	unsigned int	src_cperi1;
+	unsigned char	res21[0xf8];
+	unsigned int	src_mask_cperi;
+	unsigned char	res22[0x100];
+	unsigned int	mux_stat_cperi1;
+	unsigned char	res23[0xfc];
+	unsigned int	div_cperi1;
+	unsigned char	res24[0xfc];
+	unsigned int	div_stat_cperi1;
+	unsigned char	res25[0xf8];
+	unsigned int	gate_bus_cperi0;	/* 0x10014700 */
+	unsigned int	gate_bus_cperi1;
+	unsigned char	res26[0xf8];
+	unsigned int	gate_sclk_cperi;
+	unsigned char	res27[0xfc];
+	unsigned int	gate_ip_cperi;
+	unsigned char	res28[0xfc];
+	unsigned int	clkout_cmu_cperi;
+	unsigned int	clkout_cmu_cperi_div_stat;
+	unsigned char	res29[0x5f8];
+	unsigned int	dcgidx_map0;		/* 0x10015000 */
+	unsigned int	dcgidx_map1;
+	unsigned int	dcgidx_map2;
+	unsigned char	res30[0x14];
+	unsigned int	dcgperf_map0;
+	unsigned int	dcgperf_map1;
+	unsigned char	res31[0x18];
+	unsigned int	dvcidx_map;
+	unsigned char	res32[0x1c];
+	unsigned int	freq_cpu;
+	unsigned int	freq_dpm;
+	unsigned char	res33[0x18];
+	unsigned int	dvsemclk_en;		/* 0x10015080 */
+	unsigned int	maxperf;
+	unsigned char	res34[0x2e78];
+	unsigned int	cmu_cperi_spare0;
+	unsigned int	cmu_cperi_spare1;
+	unsigned int	cmu_cperi_spare2;
+	unsigned int	cmu_cperi_spare3;
+	unsigned int	cmu_cperi_spare4;
+	unsigned int	cmu_cperi_spare5;
+	unsigned int	cmu_cperi_spare6;
+	unsigned int	cmu_cperi_spare7;
+	unsigned int	cmu_cperi_spare8;
+	unsigned char	res35[0xcc];
+	unsigned int	cmu_cperi_version;		/* 0x10017ff0 */
+	unsigned char	res36[0x50c];
+	unsigned int	div_g2d;
+	unsigned char	res37[0xfc];
+	unsigned int	div_stat_g2d;
+	unsigned char	res38[0xfc];
+	unsigned int	gate_bus_g2d;
+	unsigned char	res39[0xfc];
+	unsigned int	gate_ip_g2d;
+	unsigned char	res40[0x1fc];
+	unsigned int	clkout_cmu_g2d;
+	unsigned int	clkout_cmu_g2d_div_stat;	/* 0x10018a04 */
+	unsigned char	res41[0xf8];
+	unsigned int	cmu_g2d_spare0;
+	unsigned int	cmu_g2d_spare1;
+	unsigned int	cmu_g2d_spare2;
+	unsigned int	cmu_g2d_spare3;
+	unsigned int	cmu_g2d_spare4;
+	unsigned char	res42[0x34dc];
+	unsigned int	cmu_g2d_version;
+	unsigned char	res43[0x30c];
+	unsigned int	div_cmu_isp0;
+	unsigned int	div_cmu_isp1;
+	unsigned int	div_isp2;		/* 0x1001c308 */
+	unsigned char	res44[0xf4];
+	unsigned int	div_stat_cmu_isp0;
+	unsigned int	div_stat_cmu_isp1;
+	unsigned int	div_stat_isp2;
+	unsigned char	res45[0x2f4];
+	unsigned int	gate_bus_isp0;
+	unsigned int	gate_bus_isp1;
+	unsigned int	gate_bus_isp2;
+	unsigned int	gate_bus_isp3;
+	unsigned char	res46[0xf0];
+	unsigned int	gate_ip_isp0;
+	unsigned int	gate_ip_isp1;
+	unsigned char	res47[0xf8];
+	unsigned int	gate_sclk_isp;
+	unsigned char	res48[0x0c];
+	unsigned int	mcuisp_pwr_ctrl;		/* 0x1001c910 */
+	unsigned char	res49[0x0ec];
+	unsigned int	clkout_cmu_isp;
+	unsigned int	clkout_cmu_isp_div_stat;
+	unsigned char	res50[0xf8];
+	unsigned int	cmu_isp_spare0;
+	unsigned int	cmu_isp_spare1;
+	unsigned int	cmu_isp_spare2;
+	unsigned int	cmu_isp_spare3;
+	unsigned char	res51[0x34e0];
+	unsigned int	cmu_isp_version;
+	unsigned char	res52[0x2c];
+	unsigned int	cpll_lock;			/* 10020020 */
+	unsigned char	res53[0xc];
+	unsigned int	dpll_lock;
+	unsigned char	res54[0xc];
+	unsigned int	epll_lock;
+	unsigned char	res55[0xc];
+	unsigned int	rpll_lock;
+	unsigned char	res56[0xc];
+	unsigned int	ipll_lock;
+	unsigned char	res57[0xc];
+	unsigned int	spll_lock;
+	unsigned char	res58[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res59[0xc];
+	unsigned int	mpll_lock;
+	unsigned char	res60[0x8c];
+	unsigned int	cpll_con0;			/* 10020120 */
+	unsigned int	cpll_con1;
+	unsigned int	dpll_con0;
+	unsigned int	dpll_con1;
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned int	epll_con2;
+	unsigned char	res601[0x4];
+	unsigned int	rpll_con0;
+	unsigned int	rpll_con1;
+	unsigned int	rpll_con2;
+	unsigned char	res602[0x4];
+	unsigned int	ipll_con0;
+	unsigned int	ipll_con1;
+	unsigned char	res61[0x8];
+	unsigned int	spll_con0;
+	unsigned int	spll_con1;
+	unsigned char	res62[0x8];
+	unsigned int	vpll_con0;
+	unsigned int	vpll_con1;
+	unsigned char	res63[0x8];
+	unsigned int	mpll_con0;
+	unsigned int	mpll_con1;
+	unsigned char	res64[0x78];
+	unsigned int	src_top0;		/* 0x10020200 */
+	unsigned int	src_top1;
+	unsigned int	src_top2;
+	unsigned int	src_top3;
+	unsigned int	src_top4;
+	unsigned int	src_top5;
+	unsigned int	src_top6;
+	unsigned int	src_top7;
+	unsigned char	res65[0xc];
+	unsigned int	src_disp10;		/* 0x1002022c */
+	unsigned char	res66[0x10];
+	unsigned int	src_mau;
+	unsigned int	src_fsys;
+	unsigned char	res67[0x8];
+	unsigned int	src_peric0;
+	unsigned int	src_peric1;
+	unsigned char	res68[0x18];
+	unsigned int	src_isp;
+	unsigned char	res69[0x0c];
+	unsigned int	src_top10;
+	unsigned int	src_top11;
+	unsigned int	src_top12;
+	unsigned char	res70[0x74];
+	unsigned int	src_mask_top0;
+	unsigned int	src_mask_top1;
+	unsigned int	src_mask_top2;
+	unsigned char	res71[0x10];
+	unsigned int	src_mask_top7;
+	unsigned char	res72[0xc];
+	unsigned int	src_mask_disp10;	/* 0x1002032c */
+	unsigned char	res73[0x4];
+	unsigned int	src_mask_mau;
+	unsigned char	res74[0x8];
+	unsigned int	src_mask_fsys;
+	unsigned char	res75[0xc];
+	unsigned int	src_mask_peric0;
+	unsigned int	src_mask_peric1;
+	unsigned char	res76[0x18];
+	unsigned int	src_mask_isp;
+	unsigned char	res77[0x8c];
+	unsigned int	mux_stat_top0;		/* 0x10020400 */
+	unsigned int	mux_stat_top1;
+	unsigned int	mux_stat_top2;
+	unsigned int	mux_stat_top3;
+	unsigned int	mux_stat_top4;
+	unsigned int	mux_stat_top5;
+	unsigned int	mux_stat_top6;
+	unsigned int	mux_stat_top7;
+	unsigned char	res78[0x60];
+	unsigned int	mux_stat_top10;
+	unsigned int	mux_stat_top11;
+	unsigned int	mux_stat_top12;
+	unsigned char	res79[0x74];
+	unsigned int	div_top0;		/* 0x10020500 */
+	unsigned int	div_top1;
+	unsigned int	div_top2;
+	unsigned char	res80[0x20];
+	unsigned int	div_disp10;
+	unsigned char	res81[0x14];
+	unsigned int	div_mau;
+	unsigned int	div_fsys0;
+	unsigned int	div_fsys1;
+	unsigned int	div_fsys2;
+	unsigned char	res82[0x4];
+	unsigned int	div_peric0;
+	unsigned int	div_peric1;
+	unsigned int	div_peric2;
+	unsigned int	div_peric3;
+	unsigned int	div_peric4;		/* 0x10020568 */
+	unsigned char	res83[0x14];
+	unsigned int	div_isp0;
+	unsigned int	div_isp1;
+	unsigned char	res84[0x8];
+	unsigned int	clkdiv2_ratio;
+	unsigned char	res850[0xc];
+	unsigned int	clkdiv4_ratio;
+	unsigned char	res85[0x5c];
+	unsigned int	div_stat_top0;
+	unsigned int	div_stat_top1;
+	unsigned int	div_stat_top2;
+	unsigned char	res86[0x20];
+	unsigned int	div_stat_disp10;
+	unsigned char	res87[0x14];
+	unsigned int	div_stat_mau;		/* 0x10020644 */
+	unsigned int	div_stat_fsys0;
+	unsigned int	div_stat_fsys1;
+	unsigned int	div_stat_fsys2;
+	unsigned char	res88[0x4];
+	unsigned int	div_stat_peric0;
+	unsigned int	div_stat_peric1;
+	unsigned int	div_stat_peric2;
+	unsigned int	div_stat_peric3;
+	unsigned int	div_stat_peric4;
+	unsigned char	res89[0x14];
+	unsigned int	div_stat_isp0;
+	unsigned int	div_stat_isp1;
+	unsigned char	res90[0x8];
+	unsigned int	clkdiv2_stat0;
+	unsigned char	res91[0xc];
+	unsigned int	clkdiv4_stat;
+	unsigned char	res92[0x5c];
+	unsigned int	gate_bus_top;		/* 0x10020700 */
+	unsigned char	res93[0xc];
+	unsigned int	gate_bus_gscl0;
+	unsigned char	res94[0xc];
+	unsigned int	gate_bus_gscl1;
+	unsigned char	res95[0x4];
+	unsigned int	gate_bus_disp1;
+	unsigned char	res96[0x4];
+	unsigned int	gate_bus_wcore;
+	unsigned int	gate_bus_mfc;
+	unsigned int	gate_bus_g3d;
+	unsigned int	gate_bus_gen;
+	unsigned int	gate_bus_fsys0;
+	unsigned int	gate_bus_fsys1;
+	unsigned int	gate_bus_fsys2;
+	unsigned int	gate_bus_mscl;
+	unsigned int	gate_bus_peric;
+	unsigned int	gate_bus_peric1;
+	unsigned char	res97[0x8];
+	unsigned int	gate_bus_peris0;
+	unsigned int	gate_bus_peris1;	/* 0x10020764 */
+	unsigned char	res98[0x8];
+	unsigned int	gate_bus_noc;
+	unsigned char	res99[0xac];
+	unsigned int	gate_top_sclk_gscl;
+	unsigned char	res1000[0x4];
+	unsigned int	gate_top_sclk_disp1;
+	unsigned char	res100[0x10];
+	unsigned int	gate_top_sclk_mau;
+	unsigned int	gate_top_sclk_fsys;
+	unsigned char	res101[0xc];
+	unsigned int	gate_top_sclk_peric;
+	unsigned char	res102[0xc];
+	unsigned int	gate_top_sclk_cperi;
+	unsigned char	res103[0xc];
+	unsigned int	gate_top_sclk_isp;
+	unsigned char	res104[0x9c];
+	unsigned int	gate_ip_gscl0;
+	unsigned char	res105[0xc];
+	unsigned int	gate_ip_gscl1;
+	unsigned char	res106[0x4];
+	unsigned int	gate_ip_disp1;
+	unsigned int	gate_ip_mfc;
+	unsigned int	gate_ip_g3d;
+	unsigned int	gate_ip_gen;		/* 0x10020934 */
+	unsigned char	res107[0xc];
+	unsigned int	gate_ip_fsys;
+	unsigned char	res108[0x8];
+	unsigned int	gate_ip_peric;
+	unsigned char	res109[0xc];
+	unsigned int	gate_ip_peris;
+	unsigned char	res110[0xc];
+	unsigned int	gate_ip_mscl;
+	unsigned char	res111[0xc];
+	unsigned int	gate_ip_block;
+	unsigned char	res112[0xc];
+	unsigned int	bypass;
+	unsigned char	res113[0x6c];
+	unsigned int	clkout_cmu_top;
+	unsigned int	clkout_cmu_top_div_stat;
+	unsigned char	res114[0xf8];
+	unsigned int	clkout_top_spare0;
+	unsigned int	clkout_top_spare1;
+	unsigned int	clkout_top_spare2;
+	unsigned int	clkout_top_spare3;
+	unsigned char	res115[0x34e0];
+	unsigned int	clkout_top_version;
+	unsigned char	res116[0xc01c];
+	unsigned int	bpll_lock;			/* 0x10030010 */
+	unsigned char	res117[0xfc];
+	unsigned int	bpll_con0;
+	unsigned int	bpll_con1;
+	unsigned char	res118[0xe8];
+	unsigned int	src_cdrex;
+	unsigned char	res119[0x1fc];
+	unsigned int	mux_stat_cdrex;
+	unsigned char	res120[0xfc];
+	unsigned int	div_cdrex0;
+	unsigned int	div_cdrex1;
+	unsigned char	res121[0xf8];
+	unsigned int	div_stat_cdrex;
+	unsigned char	res1211[0xfc];
+	unsigned int	gate_bus_cdrex;
+	unsigned int	gate_bus_cdrex1;
+	unsigned char	res122[0x1f8];
+	unsigned int	gate_ip_cdrex;
+	unsigned char	res123[0x10];
+	unsigned int	dmc_freq_ctrl;		/* 0x10030914 */
+	unsigned char	res124[0x4];
+	unsigned int	pause;
+	unsigned int	ddrphy_lock_ctrl;
+	unsigned char	res125[0xdc];
+	unsigned int	clkout_cmu_cdrex;
+	unsigned int	clkout_cmu_cdrex_div_stat;
+	unsigned char	res126[0x8];
+	unsigned int	lpddr3phy_ctrl;
+	unsigned int	lpddr3phy_con0;
+	unsigned int	lpddr3phy_con1;
+	unsigned int	lpddr3phy_con2;
+	unsigned int	lpddr3phy_con3;
+	unsigned int	lpddr3phy_con4;
+	unsigned int	lpddr3phy_con5;		/* 0x10030a28 */
+	unsigned int	pll_div2_sel;
+	unsigned char	res127[0xd0];
+	unsigned int	cmu_cdrex_spare0;
+	unsigned int	cmu_cdrex_spare1;
+	unsigned int	cmu_cdrex_spare2;
+	unsigned int	cmu_cdrex_spare3;
+	unsigned int	cmu_cdrex_spare4;
+	unsigned char	res128[0x34dc];
+	unsigned int	cmu_cdrex_version;		/* 0x10033ff0 */
+	unsigned char	res129[0x400c];
+	unsigned int	kpll_lock;
+	unsigned char	res130[0xfc];
+	unsigned int	kpll_con0;
+	unsigned int	kpll_con1;
+	unsigned char	res131[0xf8];
+	unsigned int	src_kfc;
+	unsigned char	res132[0x1fc];
+	unsigned int	mux_stat_kfc;		/* 0x10038400 */
+	unsigned char	res133[0xfc];
+	unsigned int	div_kfc0;
+	unsigned char	res134[0xfc];
+	unsigned int	div_stat_kfc0;
+	unsigned char	res135[0xfc];
+	unsigned int	gate_bus_cpu_kfc;
+	unsigned char	res136[0xfc];
+	unsigned int	gate_sclk_cpu_kfc;
+	unsigned char	res137[0x1fc];
+	unsigned int	clkout_cmu_kfc;
+	unsigned int	clkout_cmu_kfc_div_stat;	/* 0x10038a04 */
+	unsigned char	res138[0x5f8];
+	unsigned int	armclk_stopctrl_kfc;
+	unsigned char	res139[0x4];
+	unsigned int	armclk_ema_ctrl_kfc;
+	unsigned int	armclk_ema_status_kfc;
+	unsigned char	res140[0x10];
+	unsigned int	pwr_ctrl_kfc;
+	unsigned int	pwr_ctrl2_kfc;
+	unsigned char	res141[0xd8];
+	unsigned int	kpll_con0_l8;
+	unsigned int	kpll_con0_l7;
+	unsigned int	kpll_con0_l6;
+	unsigned int	kpll_con0_l5;
+	unsigned int	kpll_con0_l4;
+	unsigned int	kpll_con0_l3;
+	unsigned int	kpll_con0_l2;
+	unsigned int	kpll_con0_l1;
+	unsigned int	iem_control_kfc;		/* 0x10039120 */
+	unsigned char	res142[0xdc];
+	unsigned int	kpll_con1_l8;
+	unsigned int	kpll_con1_l7;
+	unsigned int	kpll_con1_l6;
+	unsigned int	kpll_con1_l5;
+	unsigned int	kpll_con1_l4;
+	unsigned int	kpll_con1_l3;
+	unsigned int	kpll_con1_l2;
+	unsigned int	kpll_con1_l1;
+	unsigned char	res143[0xe0];
+	unsigned int	clkdiv_iem_l8_kfc;		/* 0x10039300 */
+	unsigned int	clkdiv_iem_l7_kfc;
+	unsigned int	clkdiv_iem_l6_kfc;
+	unsigned int	clkdiv_iem_l5_kfc;
+	unsigned int	clkdiv_iem_l4_kfc;
+	unsigned int	clkdiv_iem_l3_kfc;
+	unsigned int	clkdiv_iem_l2_kfc;
+	unsigned int	clkdiv_iem_l1_kfc;
+	unsigned char	res144[0xe0];
+	unsigned int	l2_status_kfc;
+	unsigned char	res145[0xc];
+	unsigned int	cpu_status_kfc;		/* 0x10039410 */
+	unsigned char	res146[0xc];
+	unsigned int	ptm_status_kfc;
+	unsigned char	res147[0xbdc];
+	unsigned int	cmu_kfc_spare0;
+	unsigned int	cmu_kfc_spare1;
+	unsigned int	cmu_kfc_spare2;
+	unsigned int	cmu_kfc_spare3;
+	unsigned int	cmu_kfc_spare4;
+	unsigned char	res148[0x1fdc];
+	unsigned int	cmu_kfc_version;		/* 0x1003bff0 */
+};
+
+/* structure for epll configuration used in audio clock configuration */
+struct set_epll_con_val {
+	unsigned int freq_out;		/* frequency out */
+	unsigned int en_lock_det;	/* enable lock detect */
+	unsigned int m_div;		/* m divider value */
+	unsigned int p_div;		/* p divider value */
+	unsigned int s_div;		/* s divider value */
+	unsigned int k_dsm;		/* k value of delta signal modulator */
+};
+#endif
+
+#define MPLL_FOUT_SEL_SHIFT	4
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT	29  /* EPLL Locked bit position*/
+#define TIMEOUT_EPLL_LOCK		1000
+
+#define AUDIO_0_RATIO_MASK		0x0f
+#define AUDIO_1_RATIO_MASK		0x0f
+
+#define AUDIO0_SEL_MASK			0xf
+#define AUDIO1_SEL_MASK			0xf
+
+#define CLK_SRC_SCLK_EPLL		0x7
+#define CLK_SRC_MOUT_EPLL		(1<<12)
+#define AUDIO_CLKMUX_ASS		(1<<0)
+
+/* CON0 bit-fields */
+#define EPLL_CON0_MDIV_MASK		0x1ff
+#define EPLL_CON0_PDIV_MASK		0x3f
+#define EPLL_CON0_SDIV_MASK		0x7
+#define EPLL_CON0_MDIV_SHIFT		16
+#define EPLL_CON0_PDIV_SHIFT		8
+#define EPLL_CON0_SDIV_SHIFT		0
+#define EPLL_CON0_LOCK_DET_EN_SHIFT	28
+#define EPLL_CON0_LOCK_DET_EN_MASK	1
+
+#define MPLL_FOUT_SEL_MASK	0x1
+#define BPLL_FOUT_SEL_SHIFT	0
+#define BPLL_FOUT_SEL_MASK	0x1
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/cpu.h
new file mode 100644
index 000000000..fdf73b507
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/cpu.h
@@ -0,0 +1,297 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EXYNOS4_CPU_H
+#define _EXYNOS4_CPU_H
+
+#define DEVICE_NOT_AVAILABLE		0
+
+#define EXYNOS_CPU_NAME			"Exynos"
+#define EXYNOS4_ADDR_BASE		0x10000000
+
+/* EXYNOS4 Common*/
+#define EXYNOS4_I2C_SPACING		0x10000
+
+#define EXYNOS4_GPIO_PART3_BASE		0x03860000
+#define EXYNOS4_PRO_ID			0x10000000
+#define EXYNOS4_SYSREG_BASE		0x10010000
+#define EXYNOS4_POWER_BASE		0x10020000
+#define EXYNOS4_SWRESET			0x10020400
+#define EXYNOS4_CLOCK_BASE		0x10030000
+#define EXYNOS4_SYSTIMER_BASE		0x10050000
+#define EXYNOS4_WATCHDOG_BASE		0x10060000
+#define EXYNOS4_TZPC_BASE		0x10110000
+#define EXYNOS4_DMC_CTRL_BASE		0x10400000
+#define EXYNOS4_MIU_BASE		0x10600000
+#define EXYNOS4_ACE_SFR_BASE		0x10830000
+#define EXYNOS4_GPIO_PART2_BASE		0x11000000
+#define EXYNOS4_GPIO_PART1_BASE		0x11400000
+#define EXYNOS4_FIMD_BASE		0x11C00000
+#define EXYNOS4_MIPI_DSIM_BASE		0x11C80000
+#define EXYNOS4_USBOTG_BASE		0x12480000
+#define EXYNOS4_MMC_BASE		0x12510000
+#define EXYNOS4_SROMC_BASE		0x12570000
+#define EXYNOS4_USB_HOST_EHCI_BASE	0x12580000
+#define EXYNOS4_USBPHY_BASE		0x125B0000
+#define EXYNOS4_UART_BASE		0x13800000
+#define EXYNOS4_I2C_BASE		0x13860000
+#define EXYNOS4_ADC_BASE		0x13910000
+#define EXYNOS4_SPI_BASE		0x13920000
+#define EXYNOS4_PWMTIMER_BASE		0x139D0000
+#define EXYNOS4_MODEM_BASE		0x13A00000
+#define EXYNOS4_USBPHY_CONTROL		0x10020704
+#define EXYNOS4_I2S_BASE		0xE2100000
+
+#define EXYNOS4_GPIO_PART4_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DP_BASE			DEVICE_NOT_AVAILABLE
+#define EXYNOS4_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_AUDIOSS_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_USB_HOST_XHCI_BASE	DEVICE_NOT_AVAILABLE
+#define EXYNOS4_USB3PHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DMC_TZASC_BASE		DEVICE_NOT_AVAILABLE
+
+/* EXYNOS4X12 */
+#define EXYNOS4X12_GPIO_PART3_BASE	0x03860000
+#define EXYNOS4X12_PRO_ID		0x10000000
+#define EXYNOS4X12_SYSREG_BASE		0x10010000
+#define EXYNOS4X12_POWER_BASE		0x10020000
+#define EXYNOS4X12_SWRESET		0x10020400
+#define EXYNOS4X12_USBPHY_CONTROL	0x10020704
+#define EXYNOS4X12_CLOCK_BASE		0x10030000
+#define EXYNOS4X12_SYSTIMER_BASE	0x10050000
+#define EXYNOS4X12_WATCHDOG_BASE	0x10060000
+#define EXYNOS4X12_TZPC_BASE		0x10110000
+#define EXYNOS4X12_DMC_CTRL_BASE	0x10600000
+#define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
+#define EXYNOS4X12_ACE_SFR_BASE		0x10830000
+#define EXYNOS4X12_GPIO_PART2_BASE	0x11000000
+#define EXYNOS4X12_GPIO_PART1_BASE	0x11400000
+#define EXYNOS4X12_FIMD_BASE		0x11C00000
+#define EXYNOS4X12_MIPI_DSIM_BASE	0x11C80000
+#define EXYNOS4X12_USBOTG_BASE		0x12480000
+#define EXYNOS4X12_MMC_BASE		0x12510000
+#define EXYNOS4X12_SROMC_BASE		0x12570000
+#define EXYNOS4X12_USB_HOST_EHCI_BASE	0x12580000
+#define EXYNOS4X12_USBPHY_BASE		0x125B0000
+#define EXYNOS4X12_UART_BASE		0x13800000
+#define EXYNOS4X12_I2C_BASE		0x13860000
+#define EXYNOS4X12_PWMTIMER_BASE	0x139D0000
+
+#define EXYNOS4X12_ADC_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DP_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_MODEM_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_AUDIOSS_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_USB_HOST_XHCI_BASE	DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_USB3PHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DMC_TZASC_BASE	DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 */
+#define EXYNOS5_I2C_SPACING		0x10000
+
+#define EXYNOS5_AUDIOSS_BASE		0x03810000
+#define EXYNOS5_GPIO_PART4_BASE		0x03860000
+#define EXYNOS5_PRO_ID			0x10000000
+#define EXYNOS5_CLOCK_BASE		0x10010000
+#define EXYNOS5_POWER_BASE		0x10040000
+#define EXYNOS5_SWRESET			0x10040400
+#define EXYNOS5_SYSREG_BASE		0x10050000
+#define EXYNOS5_TZPC_BASE		0x10100000
+#define EXYNOS5_WATCHDOG_BASE		0x101D0000
+#define EXYNOS5_ACE_SFR_BASE		0x10830000
+#define EXYNOS5_DMC_PHY_BASE		0x10C00000
+#define EXYNOS5_GPIO_PART3_BASE		0x10D10000
+#define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
+#define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
+#define EXYNOS5_USB_HOST_XHCI_BASE	0x12000000
+#define EXYNOS5_USB3PHY_BASE		0x12100000
+#define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
+#define EXYNOS5_USBPHY_BASE		0x12130000
+#define EXYNOS5_USBOTG_BASE		0x12140000
+#define EXYNOS5_MMC_BASE		0x12200000
+#define EXYNOS5_SROMC_BASE		0x12250000
+#define EXYNOS5_UART_BASE		0x12C00000
+#define EXYNOS5_I2C_BASE		0x12C60000
+#define EXYNOS5_SPI_BASE		0x12D20000
+#define EXYNOS5_I2S_BASE		0x12D60000
+#define EXYNOS5_PWMTIMER_BASE		0x12DD0000
+#define EXYNOS5_SPI_ISP_BASE		0x131A0000
+#define EXYNOS5_GPIO_PART2_BASE		0x13400000
+#define EXYNOS5_FIMD_BASE		0x14400000
+#define EXYNOS5_DP_BASE			0x145B0000
+
+#define EXYNOS5_ADC_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5_MODEM_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5_DMC_TZASC_BASE		DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5420 */
+#define EXYNOS5420_AUDIOSS_BASE		0x03810000
+#define EXYNOS5420_GPIO_PART5_BASE	0x03860000
+#define EXYNOS5420_PRO_ID		0x10000000
+#define EXYNOS5420_CLOCK_BASE		0x10010000
+#define EXYNOS5420_POWER_BASE		0x10040000
+#define EXYNOS5420_SWRESET		0x10040400
+#define EXYNOS5420_SYSREG_BASE		0x10050000
+#define EXYNOS5420_TZPC_BASE		0x100E0000
+#define EXYNOS5420_WATCHDOG_BASE	0x101D0000
+#define EXYNOS5420_ACE_SFR_BASE		0x10830000
+#define EXYNOS5420_DMC_PHY_BASE		0x10C00000
+#define EXYNOS5420_DMC_CTRL_BASE	0x10C20000
+#define EXYNOS5420_DMC_TZASC_BASE	0x10D40000
+#define EXYNOS5420_USB_HOST_EHCI_BASE	0x12110000
+#define EXYNOS5420_MMC_BASE		0x12200000
+#define EXYNOS5420_SROMC_BASE		0x12250000
+#define EXYNOS5420_UART_BASE		0x12C00000
+#define EXYNOS5420_I2C_BASE		0x12C60000
+#define EXYNOS5420_I2C_8910_BASE	0x12E00000
+#define EXYNOS5420_SPI_BASE		0x12D20000
+#define EXYNOS5420_I2S_BASE		0x12D60000
+#define EXYNOS5420_PWMTIMER_BASE	0x12DD0000
+#define EXYNOS5420_SPI_ISP_BASE		0x131A0000
+#define EXYNOS5420_GPIO_PART2_BASE	0x13400000
+#define EXYNOS5420_GPIO_PART3_BASE	0x13410000
+#define EXYNOS5420_GPIO_PART4_BASE	0x14000000
+#define EXYNOS5420_GPIO_PART1_BASE	0x14010000
+#define EXYNOS5420_MIPI_DSIM_BASE	0x14500000
+#define EXYNOS5420_DP_BASE		0x145B0000
+
+#define EXYNOS5420_USBPHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USBOTG_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_FIMD_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_ADC_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_MODEM_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USB3PHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USB_HOST_XHCI_BASE	DEVICE_NOT_AVAILABLE
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+/* CPU detection macros */
+extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+	return s5p_cpu_rev;
+}
+
+static inline void s5p_set_cpu_id(void)
+{
+	unsigned int pro_id = readl(EXYNOS4_PRO_ID);
+	unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
+	unsigned int cpu_rev = pro_id & 0x000000FF;
+
+	switch (cpu_id) {
+	case 0x200:
+		/* Exynos4210 EVT0 */
+		s5p_cpu_id = 0x4210;
+		s5p_cpu_rev = 0;
+		break;
+	case 0x210:
+		/* Exynos4210 EVT1 */
+		s5p_cpu_id = 0x4210;
+		s5p_cpu_rev = cpu_rev;
+		break;
+	case 0x412:
+		/* Exynos4412 */
+		s5p_cpu_id = 0x4412;
+		s5p_cpu_rev = cpu_rev;
+		break;
+	case 0x520:
+		/* Exynos5250 */
+		s5p_cpu_id = 0x5250;
+		break;
+	case 0x420:
+		/* Exynos5420 */
+		s5p_cpu_id = 0x5420;
+		break;
+	}
+}
+
+static inline char *s5p_get_cpu_name(void)
+{
+	return EXYNOS_CPU_NAME;
+}
+
+#define IS_SAMSUNG_TYPE(type, id)			\
+static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
+{							\
+	return (s5p_cpu_id >> 12) == id;		\
+}
+
+IS_SAMSUNG_TYPE(exynos4, 0x4)
+IS_SAMSUNG_TYPE(exynos5, 0x5)
+
+#define IS_EXYNOS_TYPE(type, id)			\
+static inline int __attribute__((no_instrument_function)) \
+	proid_is_##type(void)				\
+{							\
+	return s5p_cpu_id == id;			\
+}
+
+IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
+IS_EXYNOS_TYPE(exynos5250, 0x5250)
+IS_EXYNOS_TYPE(exynos5420, 0x5420)
+
+#define SAMSUNG_BASE(device, base)				\
+static inline unsigned int __attribute__((no_instrument_function)) \
+	samsung_get_base_##device(void) \
+{								\
+	if (cpu_is_exynos4()) {				\
+		if (proid_is_exynos4412())			\
+			return EXYNOS4X12_##base;		\
+		return EXYNOS4_##base;				\
+	} else if (cpu_is_exynos5()) {				\
+		if (proid_is_exynos5420())			\
+			return EXYNOS5420_##base;		\
+		return EXYNOS5_##base;				\
+	}							\
+	return 0;						\
+}
+
+SAMSUNG_BASE(adc, ADC_BASE)
+SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
+SAMSUNG_BASE(dp, DP_BASE)
+SAMSUNG_BASE(sysreg, SYSREG_BASE)
+SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(i2c, I2C_BASE)
+SAMSUNG_BASE(i2s, I2S_BASE)
+SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
+SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
+SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
+SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
+SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
+SAMSUNG_BASE(pro_id, PRO_ID)
+SAMSUNG_BASE(mmc, MMC_BASE)
+SAMSUNG_BASE(modem, MODEM_BASE)
+SAMSUNG_BASE(sromc, SROMC_BASE)
+SAMSUNG_BASE(swreset, SWRESET)
+SAMSUNG_BASE(timer, PWMTIMER_BASE)
+SAMSUNG_BASE(uart, UART_BASE)
+SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb3_phy, USB3PHY_BASE)
+SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
+SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE)
+SAMSUNG_BASE(usb_otg, USBOTG_BASE)
+SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
+SAMSUNG_BASE(power, POWER_BASE)
+SAMSUNG_BASE(spi, SPI_BASE)
+SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+SAMSUNG_BASE(tzpc, TZPC_BASE)
+SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
+SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
+SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE)
+SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
+#endif
+
+#endif	/* _EXYNOS4_CPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dmc.h
new file mode 100644
index 000000000..d78536d2d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dmc.h
@@ -0,0 +1,497 @@
+#ifndef __DMC_H__
+#define __DMC_H__
+
+#ifndef __ASSEMBLY__
+struct exynos4_dmc {
+	unsigned int concontrol;
+	unsigned int memcontrol;
+	unsigned int memconfig0;
+	unsigned int memconfig1;
+	unsigned int directcmd;
+	unsigned int prechconfig;
+	unsigned int phycontrol0;
+	unsigned int phycontrol1;
+	unsigned int phycontrol2;
+	unsigned int phycontrol3;
+	unsigned int pwrdnconfig;
+	unsigned char res1[0x4];
+	unsigned int timingref;
+	unsigned int timingrow;
+	unsigned int timingdata;
+	unsigned int timingpower;
+	unsigned int phystatus;
+	unsigned int phyzqcontrol;
+	unsigned int chip0status;
+	unsigned int chip1status;
+	unsigned int arefstatus;
+	unsigned int mrstatus;
+	unsigned int phytest0;
+	unsigned int phytest1;
+	unsigned int qoscontrol0;
+	unsigned int qosconfig0;
+	unsigned int qoscontrol1;
+	unsigned int qosconfig1;
+	unsigned int qoscontrol2;
+	unsigned int qosconfig2;
+	unsigned int qoscontrol3;
+	unsigned int qosconfig3;
+	unsigned int qoscontrol4;
+	unsigned int qosconfig4;
+	unsigned int qoscontrol5;
+	unsigned int qosconfig5;
+	unsigned int qoscontrol6;
+	unsigned int qosconfig6;
+	unsigned int qoscontrol7;
+	unsigned int qosconfig7;
+	unsigned int qoscontrol8;
+	unsigned int qosconfig8;
+	unsigned int qoscontrol9;
+	unsigned int qosconfig9;
+	unsigned int qoscontrol10;
+	unsigned int qosconfig10;
+	unsigned int qoscontrol11;
+	unsigned int qosconfig11;
+	unsigned int qoscontrol12;
+	unsigned int qosconfig12;
+	unsigned int qoscontrol13;
+	unsigned int qosconfig13;
+	unsigned int qoscontrol14;
+	unsigned int qosconfig14;
+	unsigned int qoscontrol15;
+	unsigned int qosconfig15;
+	unsigned int qostimeout0;
+	unsigned int qostimeout1;
+	unsigned char res2[0x8];
+	unsigned int ivcontrol;
+	unsigned char res3[0x8];
+	unsigned int perevconfig;
+	unsigned char res4[0xDF00];
+	unsigned int pmnc_ppc_a;
+	unsigned char res5[0xC];
+	unsigned int cntens_ppc_a;
+	unsigned char res6[0xC];
+	unsigned int cntenc_ppc_a;
+	unsigned char res7[0xC];
+	unsigned int intens_ppc_a;
+	unsigned char res8[0xC];
+	unsigned int intenc_ppc_a;
+	unsigned char res9[0xC];
+	unsigned int flag_ppc_a;
+	unsigned char res10[0xAC];
+	unsigned int ccnt_ppc_a;
+	unsigned char res11[0xC];
+	unsigned int pmcnt0_ppc_a;
+	unsigned char res12[0xC];
+	unsigned int pmcnt1_ppc_a;
+	unsigned char res13[0xC];
+	unsigned int pmcnt2_ppc_a;
+	unsigned char res14[0xC];
+	unsigned int pmcnt3_ppc_a;
+	unsigned char res15[0xEBC];
+	unsigned int pmnc_ppc_m;
+	unsigned char res16[0xC];
+	unsigned int cntens_ppc_m;
+	unsigned char res17[0xC];
+	unsigned int cntenc_ppc_m;
+	unsigned char res18[0xC];
+	unsigned int intens_ppc_m;
+	unsigned char res19[0xC];
+	unsigned int intenc_ppc_m;
+	unsigned char res20[0xC];
+	unsigned int flag_ppc_m;
+	unsigned char res21[0xAC];
+	unsigned int ccnt_ppc_m;
+	unsigned char res22[0xC];
+	unsigned int pmcnt0_ppc_m;
+	unsigned char res23[0xC];
+	unsigned int pmcnt1_ppc_m;
+	unsigned char res24[0xC];
+	unsigned int pmcnt2_ppc_m;
+	unsigned char res25[0xC];
+	unsigned int pmcnt3_ppc_m;
+};
+
+struct exynos5_dmc {
+	unsigned int concontrol;
+	unsigned int memcontrol;
+	unsigned int memconfig0;
+	unsigned int memconfig1;
+	unsigned int directcmd;
+	unsigned int prechconfig;
+	unsigned int phycontrol0;
+	unsigned char res1[0xc];
+	unsigned int pwrdnconfig;
+	unsigned int timingpzq;
+	unsigned int timingref;
+	unsigned int timingrow;
+	unsigned int timingdata;
+	unsigned int timingpower;
+	unsigned int phystatus;
+	unsigned char res2[0x4];
+	unsigned int chipstatus_ch0;
+	unsigned int chipstatus_ch1;
+	unsigned char res3[0x4];
+	unsigned int mrstatus;
+	unsigned char res4[0x8];
+	unsigned int qoscontrol0;
+	unsigned char resr5[0x4];
+	unsigned int qoscontrol1;
+	unsigned char res6[0x4];
+	unsigned int qoscontrol2;
+	unsigned char res7[0x4];
+	unsigned int qoscontrol3;
+	unsigned char res8[0x4];
+	unsigned int qoscontrol4;
+	unsigned char res9[0x4];
+	unsigned int qoscontrol5;
+	unsigned char res10[0x4];
+	unsigned int qoscontrol6;
+	unsigned char res11[0x4];
+	unsigned int qoscontrol7;
+	unsigned char res12[0x4];
+	unsigned int qoscontrol8;
+	unsigned char res13[0x4];
+	unsigned int qoscontrol9;
+	unsigned char res14[0x4];
+	unsigned int qoscontrol10;
+	unsigned char res15[0x4];
+	unsigned int qoscontrol11;
+	unsigned char res16[0x4];
+	unsigned int qoscontrol12;
+	unsigned char res17[0x4];
+	unsigned int qoscontrol13;
+	unsigned char res18[0x4];
+	unsigned int qoscontrol14;
+	unsigned char res19[0x4];
+	unsigned int qoscontrol15;
+	unsigned char res20[0x14];
+	unsigned int ivcontrol;
+	unsigned int wrtra_config;
+	unsigned int rdlvl_config;
+	unsigned char res21[0x8];
+	unsigned int brbrsvconfig;
+	unsigned int brbqosconfig;
+	unsigned int membaseconfig0;
+	unsigned int membaseconfig1;
+	unsigned char res22[0xc];
+	unsigned int wrlvl_config;
+	unsigned char res23[0xc];
+	unsigned int perevcontrol;
+	unsigned int perev0config;
+	unsigned int perev1config;
+	unsigned int perev2config;
+	unsigned int perev3config;
+	unsigned char res24[0xdebc];
+	unsigned int pmnc_ppc_a;
+	unsigned char res25[0xc];
+	unsigned int cntens_ppc_a;
+	unsigned char res26[0xc];
+	unsigned int cntenc_ppc_a;
+	unsigned char res27[0xc];
+	unsigned int intens_ppc_a;
+	unsigned char res28[0xc];
+	unsigned int intenc_ppc_a;
+	unsigned char res29[0xc];
+	unsigned int flag_ppc_a;
+	unsigned char res30[0xac];
+	unsigned int ccnt_ppc_a;
+	unsigned char res31[0xc];
+	unsigned int pmcnt0_ppc_a;
+	unsigned char res32[0xc];
+	unsigned int pmcnt1_ppc_a;
+	unsigned char res33[0xc];
+	unsigned int pmcnt2_ppc_a;
+	unsigned char res34[0xc];
+	unsigned int pmcnt3_ppc_a;
+};
+
+struct exynos5420_dmc {
+	unsigned int concontrol;
+	unsigned int memcontrol;
+	unsigned int cgcontrol;
+	unsigned char res500[0x4];
+	unsigned int directcmd;
+	unsigned int prechconfig0;
+	unsigned int phycontrol0;
+	unsigned int prechconfig1;
+	unsigned char res1[0x8];
+	unsigned int pwrdnconfig;
+	unsigned int timingpzq;
+	unsigned int timingref;
+	unsigned int timingrow0;
+	unsigned int timingdata0;
+	unsigned int timingpower0;
+	unsigned int phystatus;
+	unsigned int etctiming;
+	unsigned int chipstatus;
+	unsigned char res3[0x8];
+	unsigned int mrstatus;
+	unsigned char res4[0x8];
+	unsigned int qoscontrol0;
+	unsigned char resr5[0x4];
+	unsigned int qoscontrol1;
+	unsigned char res6[0x4];
+	unsigned int qoscontrol2;
+	unsigned char res7[0x4];
+	unsigned int qoscontrol3;
+	unsigned char res8[0x4];
+	unsigned int qoscontrol4;
+	unsigned char res9[0x4];
+	unsigned int qoscontrol5;
+	unsigned char res10[0x4];
+	unsigned int qoscontrol6;
+	unsigned char res11[0x4];
+	unsigned int qoscontrol7;
+	unsigned char res12[0x4];
+	unsigned int qoscontrol8;
+	unsigned char res13[0x4];
+	unsigned int qoscontrol9;
+	unsigned char res14[0x4];
+	unsigned int qoscontrol10;
+	unsigned char res15[0x4];
+	unsigned int qoscontrol11;
+	unsigned char res16[0x4];
+	unsigned int qoscontrol12;
+	unsigned char res17[0x4];
+	unsigned int qoscontrol13;
+	unsigned char res18[0x4];
+	unsigned int qoscontrol14;
+	unsigned char res19[0x4];
+	unsigned int qoscontrol15;
+	unsigned char res20[0x4];
+	unsigned int timing_set_sw;
+	unsigned int timingrow1;
+	unsigned int timingdata1;
+	unsigned int timingpower1;
+	unsigned char res300[0x4];
+	unsigned int wrtra_config;
+	unsigned int rdlvl_config;
+	unsigned char res21[0x4];
+	unsigned int brbrsvcontrol;
+	unsigned int brbrsvconfig;
+	unsigned int brbqosconfig;
+	unsigned char res301[0x14];
+	unsigned int wrlvl_config0;
+	unsigned int wrlvl_config1;
+	unsigned int wrlvl_status;
+	unsigned char res23[0x4];
+	unsigned int ppcclockon;
+	unsigned int perevconfig0;
+	unsigned int perevconfig1;
+	unsigned int perevconfig2;
+	unsigned int perevconfig3;
+	unsigned char res24[0xc];
+	unsigned int control_io_rdata;
+	unsigned char res240[0xc];
+	unsigned int cacal_config0;
+	unsigned int cacal_config1;
+	unsigned int cacal_status;
+	unsigned char res302[0xa4];
+	unsigned int bp_control0;
+	unsigned int bp_config0_r;
+	unsigned int bp_config0_w;
+	unsigned char res303[0x4];
+	unsigned int bp_control1;
+	unsigned int bp_config1_r;
+	unsigned int bp_config1_w;
+	unsigned char res304[0x4];
+	unsigned int bp_control2;
+	unsigned int bp_config2_r;
+	unsigned int bp_config2_w;
+	unsigned char res305[0x4];
+	unsigned int bp_control3;
+	unsigned int bp_config3_r;
+	unsigned int bp_config3_w;
+	unsigned char res306[0xddb4];
+	unsigned int pmnc_ppc;
+	unsigned char res25[0xc];
+	unsigned int cntens_ppc;
+	unsigned char res26[0xc];
+	unsigned int cntenc_ppc;
+	unsigned char res27[0xc];
+	unsigned int intens_ppc;
+	unsigned char res28[0xc];
+	unsigned int intenc_ppc;
+	unsigned char res29[0xc];
+	unsigned int flag_ppc;
+	unsigned char res30[0xac];
+	unsigned int ccnt_ppc;
+	unsigned char res31[0xc];
+	unsigned int pmcnt0_ppc;
+	unsigned char res32[0xc];
+	unsigned int pmcnt1_ppc;
+	unsigned char res33[0xc];
+	unsigned int pmcnt2_ppc;
+	unsigned char res34[0xc];
+	unsigned int pmcnt3_ppc;
+};
+
+struct exynos5_phy_control {
+	unsigned int phy_con0;
+	unsigned int phy_con1;
+	unsigned int phy_con2;
+	unsigned int phy_con3;
+	unsigned int phy_con4;
+	unsigned char res1[4];
+	unsigned int phy_con6;
+	unsigned char res2[4];
+	unsigned int phy_con8;
+	unsigned int phy_con9;
+	unsigned int phy_con10;
+	unsigned char res3[4];
+	unsigned int phy_con12;
+	unsigned int phy_con13;
+	unsigned int phy_con14;
+	unsigned int phy_con15;
+	unsigned int phy_con16;
+	unsigned char res4[4];
+	unsigned int phy_con17;
+	unsigned int phy_con18;
+	unsigned int phy_con19;
+	unsigned int phy_con20;
+	unsigned int phy_con21;
+	unsigned int phy_con22;
+	unsigned int phy_con23;
+	unsigned int phy_con24;
+	unsigned int phy_con25;
+	unsigned int phy_con26;
+	unsigned int phy_con27;
+	unsigned int phy_con28;
+	unsigned int phy_con29;
+	unsigned int phy_con30;
+	unsigned int phy_con31;
+	unsigned int phy_con32;
+	unsigned int phy_con33;
+	unsigned int phy_con34;
+	unsigned int phy_con35;
+	unsigned int phy_con36;
+	unsigned int phy_con37;
+	unsigned int phy_con38;
+	unsigned int phy_con39;
+	unsigned int phy_con40;
+	unsigned int phy_con41;
+	unsigned int phy_con42;
+};
+
+struct exynos5420_phy_control {
+	unsigned int phy_con0;
+	unsigned int phy_con1;
+	unsigned int phy_con2;
+	unsigned int phy_con3;
+	unsigned int phy_con4;
+	unsigned int phy_con5;
+	unsigned int phy_con6;
+	unsigned char res2[0x4];
+	unsigned int phy_con8;
+	unsigned char res5[0x4];
+	unsigned int phy_con10;
+	unsigned int phy_con11;
+	unsigned int phy_con12;
+	unsigned int phy_con13;
+	unsigned int phy_con14;
+	unsigned int phy_con15;
+	unsigned int phy_con16;
+	unsigned char res4[0x4];
+	unsigned int phy_con17;
+	unsigned int phy_con18;
+	unsigned int phy_con19;
+	unsigned int phy_con20;
+	unsigned int phy_con21;
+	unsigned int phy_con22;
+	unsigned int phy_con23;
+	unsigned int phy_con24;
+	unsigned int phy_con25;
+	unsigned int phy_con26;
+	unsigned int phy_con27;
+	unsigned int phy_con28;
+	unsigned int phy_con29;
+	unsigned int phy_con30;
+	unsigned int phy_con31;
+	unsigned int phy_con32;
+	unsigned int phy_con33;
+	unsigned int phy_con34;
+	unsigned char res6[0x8];
+	unsigned int phy_con37;
+	unsigned char res7[0x4];
+	unsigned int phy_con39;
+	unsigned int phy_con40;
+	unsigned int phy_con41;
+	unsigned int phy_con42;
+};
+
+struct exynos5420_tzasc {
+	unsigned char res1[0xf00];
+	unsigned int membaseconfig0;
+	unsigned int membaseconfig1;
+	unsigned char res2[0x8];
+	unsigned int memconfig0;
+	unsigned int memconfig1;
+};
+
+enum ddr_mode {
+	DDR_MODE_DDR2,
+	DDR_MODE_DDR3,
+	DDR_MODE_LPDDR2,
+	DDR_MODE_LPDDR3,
+
+	DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+	MEM_MANUF_AUTODETECT,
+	MEM_MANUF_ELPIDA,
+	MEM_MANUF_SAMSUNG,
+
+	MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT	28
+#define CONCONTROL_RD_FETCH_SHIFT	12
+#define CONCONTROL_RD_FETCH_MASK	(0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT	5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT	24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT	0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT	16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT	17
+#define PHY_CON0_T_WRRDCMD_MASK		(0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT	11
+#define PHY_CON0_CTRL_DDR_MODE_MASK	0x3
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT	0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT	24
+#define PHY_CON12_CTRL_INC_SHIFT	16
+#define PHY_CON12_CTRL_FORCE_SHIFT	8
+#define PHY_CON12_CTRL_START_SHIFT	6
+#define PHY_CON12_CTRL_START_MASK	(1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT	5
+#define PHY_CON12_CTRL_DLL_ON_MASK	(1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT	1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT	24
+#define PHY_CON16_ZQ_MODE_DDS_MASK	(0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK	(0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK	(1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT	8
+#define PHY_CON42_CTRL_BSTLEN_MASK	(0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT	0
+#define PHY_CON42_CTRL_RDLAT_MASK	(0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
+#endif
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp.h
new file mode 100644
index 000000000..0ec58e94c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp.h
@@ -0,0 +1,738 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_DP_H_
+#define __ASM_ARM_ARCH_DP_H_
+
+#ifndef __ASSEMBLY__
+
+struct exynos_dp {
+	unsigned char	res1[0x10];
+	unsigned int	tx_version;
+	unsigned int	tx_sw_reset;
+	unsigned int	func_en1;
+	unsigned int	func_en2;
+	unsigned int	video_ctl1;
+	unsigned int	video_ctl2;
+	unsigned int	video_ctl3;
+	unsigned int	video_ctl4;
+	unsigned int	color_blue_cb;
+	unsigned int	color_green_y;
+	unsigned int	color_red_cr;
+	unsigned int	video_ctl8;
+	unsigned char	res2[0x4];
+	unsigned int	video_ctl10;
+	unsigned int	total_ln_cfg_l;
+	unsigned int	total_ln_cfg_h;
+	unsigned int	active_ln_cfg_l;
+	unsigned int	active_ln_cfg_h;
+	unsigned int	vfp_cfg;
+	unsigned int	vsw_cfg;
+	unsigned int	vbp_cfg;
+	unsigned int	total_pix_cfg_l;
+	unsigned int	total_pix_cfg_h;
+	unsigned int	active_pix_cfg_l;
+	unsigned int	active_pix_cfg_h;
+	unsigned int	hfp_cfg_l;
+	unsigned int	hfp_cfg_h;
+	unsigned int	hsw_cfg_l;
+	unsigned int	hsw_cfg_h;
+	unsigned int	hbp_cfg_l;
+	unsigned int	hbp_cfg_h;
+	unsigned int	video_status;
+	unsigned int	total_ln_sta_l;
+	unsigned int	total_ln_sta_h;
+	unsigned int	active_ln_sta_l;
+	unsigned int	active_ln_sta_h;
+
+	unsigned int	vfp_sta;
+	unsigned int	vsw_sta;
+	unsigned int	vbp_sta;
+
+	unsigned int	total_pix_sta_l;
+	unsigned int	total_pix_sta_h;
+	unsigned int	active_pix_sta_l;
+	unsigned int	active_pix_sta_h;
+
+	unsigned int	hfp_sta_l;
+	unsigned int	hfp_sta_h;
+	unsigned int	hsw_sta_l;
+	unsigned int	hsw_sta_h;
+	unsigned int	hbp_sta_l;
+	unsigned int	hbp_sta_h;
+
+	unsigned char	res3[0x288];
+
+	unsigned int	lane_map;
+	unsigned char	res4[0x10];
+	unsigned int	analog_ctl1;
+	unsigned int	analog_ctl2;
+	unsigned int	analog_ctl3;
+
+	unsigned int	pll_filter_ctl1;
+	unsigned int	amp_tuning_ctl;
+	unsigned char	res5[0xc];
+
+	unsigned int	aux_hw_retry_ctl;
+	unsigned char	res6[0x2c];
+	unsigned int	int_state;
+	unsigned int	common_int_sta1;
+	unsigned int	common_int_sta2;
+	unsigned int	common_int_sta3;
+	unsigned int	common_int_sta4;
+	unsigned char	res7[0x8];
+
+	unsigned int	int_sta;
+	unsigned char	res8[0x1c];
+	unsigned int	int_ctl;
+	unsigned char	res9[0x200];
+	unsigned int	sys_ctl1;
+	unsigned int	sys_ctl2;
+	unsigned int	sys_ctl3;
+	unsigned int	sys_ctl4;
+	unsigned int	vid_ctl;
+	unsigned char	res10[0x2c];
+	unsigned int	pkt_send_ctl;
+	unsigned char	res[0x4];
+	unsigned int	hdcp_ctl;
+	unsigned char	res11[0x34];
+	unsigned int	link_bw_set;
+
+	unsigned int	lane_count_set;
+	unsigned int	training_ptn_set;
+	unsigned int	ln0_link_training_ctl;
+	unsigned int	ln1_link_training_ctl;
+	unsigned int	ln2_link_training_ctl;
+	unsigned int	ln3_link_training_ctl;
+	unsigned int	dn_spread_ctl;
+	unsigned int	hw_link_training_ctl;
+	unsigned char	res12[0x1c];
+
+	unsigned int	debug_ctl;
+	unsigned int	hpd_deglitch_l;
+	unsigned int	hpd_deglitch_h;
+
+	unsigned char	res13[0x14];
+	unsigned int	link_debug_ctl;
+
+	unsigned char	res14[0x1c];
+
+	unsigned int	m_vid0;
+	unsigned int	m_vid1;
+	unsigned int	m_vid2;
+	unsigned int	n_vid0;
+	unsigned int	n_vid1;
+	unsigned int	n_vid2;
+	unsigned int	m_vid_mon;
+	unsigned int	pll_ctl;
+	unsigned int	phy_pd;
+	unsigned int	phy_test;
+	unsigned char	res15[0x8];
+
+	unsigned int	video_fifo_thrd;
+	unsigned char	res16[0x8];
+	unsigned int	audio_margin;
+
+	unsigned int	dn_spread_ctl1;
+	unsigned int	dn_spread_ctl2;
+	unsigned char	res17[0x18];
+	unsigned int	m_cal_ctl;
+	unsigned int	m_vid_gen_filter_th;
+	unsigned char	res18[0x10];
+	unsigned int	m_aud_gen_filter_th;
+	unsigned char	res50[0x4];
+
+	unsigned int	aux_ch_sta;
+	unsigned int	aux_err_num;
+	unsigned int	aux_ch_defer_ctl;
+	unsigned int	aux_rx_comm;
+	unsigned int	buffer_data_ctl;
+
+	unsigned int	aux_ch_ctl1;
+	unsigned int	aux_addr_7_0;
+	unsigned int	aux_addr_15_8;
+	unsigned int	aux_addr_19_16;
+	unsigned int	aux_ch_ctl2;
+	unsigned char	res19[0x18];
+	unsigned int	buf_data0;
+	unsigned char	res20[0x3c];
+
+	unsigned int	soc_general_ctl;
+	unsigned char	res21[0x8c];
+	unsigned int	crc_con;
+	unsigned int	crc_result;
+	unsigned char	res22[0x8];
+
+	unsigned int	common_int_mask1;
+	unsigned int	common_int_mask2;
+	unsigned int	common_int_mask3;
+	unsigned int	common_int_mask4;
+	unsigned int	int_sta_mask1;
+	unsigned int	int_sta_mask2;
+	unsigned int	int_sta_mask3;
+	unsigned int	int_sta_mask4;
+	unsigned int	int_sta_mask;
+	unsigned int	crc_result2;
+	unsigned int	scrambler_reset_cnt;
+
+	unsigned int	pn_inv;
+	unsigned int	psr_config;
+	unsigned int	psr_command0;
+	unsigned int	psr_command1;
+	unsigned int	psr_crc_mon0;
+	unsigned int	psr_crc_mon1;
+
+	unsigned char	res24[0x30];
+	unsigned int	phy_bist_ctrl;
+	unsigned char	res25[0xc];
+	unsigned int	phy_ctrl;
+	unsigned char	res26[0x1c];
+	unsigned int	test_pattern_gen_en;
+	unsigned int	test_pattern_gen_ctrl;
+};
+
+#endif	/* __ASSEMBLY__ */
+
+/* For DP VIDEO CTL 1 */
+#define VIDEO_EN_MASK				(0x01 << 7)
+#define VIDEO_MUTE_MASK				(0x01 << 6)
+
+/* For DP VIDEO CTL 4 */
+#define VIDEO_BIST_MASK				(0x1 << 3)
+
+/* EXYNOS_DP_ANALOG_CTL_1 */
+#define SEL_BG_NEW_BANDGAP			(0x0 << 6)
+#define SEL_BG_INTERNAL_RESISTOR		(0x1 << 6)
+#define TX_TERMINAL_CTRL_73_OHM			(0x0 << 4)
+#define TX_TERMINAL_CTRL_61_OHM			(0x1 << 4)
+#define TX_TERMINAL_CTRL_50_OHM			(0x2 << 4)
+#define TX_TERMINAL_CTRL_45_OHM			(0x3 << 4)
+#define SWING_A_30PER_G_INCREASE		(0x1 << 3)
+#define SWING_A_30PER_G_NORMAL			(0x0 << 3)
+
+/* EXYNOS_DP_ANALOG_CTL_2 */
+#define CPREG_BLEED				(0x1 << 4)
+#define SEL_24M					(0x1 << 3)
+#define TX_DVDD_BIT_1_0000V			(0x3 << 0)
+#define TX_DVDD_BIT_1_0625V			(0x4 << 0)
+#define TX_DVDD_BIT_1_1250V			(0x5 << 0)
+
+/* EXYNOS_DP_ANALOG_CTL_3 */
+#define DRIVE_DVDD_BIT_1_0000V			(0x3 << 5)
+#define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
+#define DRIVE_DVDD_BIT_1_1250V			(0x5 << 5)
+#define SEL_CURRENT_DEFAULT			(0x0 << 3)
+#define VCO_BIT_000_MICRO			(0x0 << 0)
+#define VCO_BIT_200_MICRO			(0x1 << 0)
+#define VCO_BIT_300_MICRO			(0x2 << 0)
+#define VCO_BIT_400_MICRO			(0x3 << 0)
+#define VCO_BIT_500_MICRO			(0x4 << 0)
+#define VCO_BIT_600_MICRO			(0x5 << 0)
+#define VCO_BIT_700_MICRO			(0x6 << 0)
+#define VCO_BIT_900_MICRO			(0x7 << 0)
+
+/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+#define PD_RING_OSC				(0x1 << 6)
+#define AUX_TERMINAL_CTRL_52_OHM		(0x3 << 4)
+#define AUX_TERMINAL_CTRL_69_OHM		(0x2 << 4)
+#define AUX_TERMINAL_CTRL_102_OHM		(0x1 << 4)
+#define AUX_TERMINAL_CTRL_200_OHM		(0x0 << 4)
+#define TX_CUR1_1X				(0x0 << 2)
+#define TX_CUR1_2X				(0x1 << 2)
+#define TX_CUR1_3X				(0x2 << 2)
+#define TX_CUR_1_MA				(0x0 << 0)
+#define TX_CUR_2_MA			        (0x1 << 0)
+#define TX_CUR_3_MA				(0x2 << 0)
+#define TX_CUR_4_MA				(0x3 << 0)
+
+/* EXYNOS_DP_PLL_FILTER_CTL_2 */
+#define CH3_AMP_0_MV				(0x3 << 12)
+#define CH2_AMP_0_MV				(0x3 << 8)
+#define CH1_AMP_0_MV				(0x3 << 4)
+#define CH0_AMP_0_MV				(0x3 << 0)
+
+/* EXYNOS_DP_PLL_CTL */
+#define DP_PLL_PD			        (0x1 << 7)
+#define DP_PLL_RESET				(0x1 << 6)
+#define DP_PLL_LOOP_BIT_DEFAULT		        (0x1 << 4)
+#define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
+#define DP_PLL_REF_BIT_1_2500V		        (0x7 << 0)
+
+/* EXYNOS_DP_INT_CTL */
+#define SOFT_INT_CTRL				(0x1 << 2)
+#define INT_POL					(0x1 << 0)
+
+/* DP TX SW RESET */
+#define RESET_DP_TX				(0x01 << 0)
+
+/* DP FUNC_EN_1 */
+#define MASTER_VID_FUNC_EN_N			(0x1 << 7)
+#define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
+#define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
+#define AUD_FUNC_EN_N				(0x1 << 3)
+#define HDCP_FUNC_EN_N				(0x1 << 2)
+#define CRC_FUNC_EN_N				(0x1 << 1)
+#define SW_FUNC_EN_N				(0x1 << 0)
+
+/* DP FUNC_EN_2 */
+#define SSC_FUNC_EN_N			        (0x1 << 7)
+#define AUX_FUNC_EN_N				(0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N		        (0x1 << 0)
+
+/* EXYNOS_DP_PHY_PD */
+#define PHY_PD					(0x1 << 5)
+#define AUX_PD					(0x1 << 4)
+#define CH3_PD					(0x1 << 3)
+#define CH2_PD					(0x1 << 2)
+#define CH1_PD					(0x1 << 1)
+#define CH0_PD					(0x1 << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_1 */
+#define VSYNC_DET				(0x1 << 7)
+#define PLL_LOCK_CHG				(0x1 << 6)
+#define SPDIF_ERR				(0x1 << 5)
+#define SPDIF_UNSTBL				(0x1 << 4)
+#define VID_FORMAT_CHG				(0x1 << 3)
+#define AUD_CLK_CHG				(0x1 << 2)
+#define VID_CLK_CHG				(0x1 << 1)
+#define SW_INT					(0x1 << 0)
+
+/* EXYNOS_DP_DEBUG_CTL */
+#define PLL_LOCK				(0x1 << 4)
+#define F_PLL_LOCK				(0x1 << 3)
+#define PLL_LOCK_CTRL				(0x1 << 2)
+
+/* EXYNOS_DP_FUNC_EN_2 */
+#define SSC_FUNC_EN_N				(0x1 << 7)
+#define AUX_FUNC_EN_N				(0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_4 */
+#define PSR_ACTIVE				(0x1 << 7)
+#define PSR_INACTIVE				(0x1 << 6)
+#define SPDIF_BI_PHASE_ERR			(0x1 << 5)
+#define HOTPLUG_CHG				(0x1 << 2)
+#define HPD_LOST				(0x1 << 1)
+#define PLUG					(0x1 << 0)
+
+/* EXYNOS_DP_INT_STA */
+#define INT_HPD					(0x1 << 6)
+#define HW_TRAINING_FINISH			(0x1 << 5)
+#define RPLY_RECEIV				(0x1 << 1)
+#define AUX_ERR					(0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_3 */
+#define HPD_STATUS				(0x1 << 6)
+#define F_HPD					(0x1 << 5)
+#define HPD_CTRL				(0x1 << 4)
+#define HDCP_RDY				(0x1 << 3)
+#define STRM_VALID				(0x1 << 2)
+#define F_VALID					(0x1 << 1)
+#define VALID_CTRL				(0x1 << 0)
+
+/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+#define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
+#define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
+#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
+#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS	(0x1 << 3)
+#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS	(0x2 << 3)
+#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
+#define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
+
+/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+#define DEFER_CTRL_EN				(0x1 << 7)
+#define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
+
+#define COMMON_INT_MASK_1			(0)
+#define COMMON_INT_MASK_2			(0)
+#define COMMON_INT_MASK_3			(0)
+#define COMMON_INT_MASK_4			(0)
+#define INT_STA_MASK				(0)
+
+/* EXYNOS_DP_BUFFER_DATA_CTL */
+#define BUF_CLR					(0x1 << 7)
+#define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
+
+/* EXYNOS_DP_AUX_ADDR_7_0 */
+#define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
+
+/* EXYNOS_DP_AUX_ADDR_15_8 */
+#define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
+
+/* EXYNOS_DP_AUX_ADDR_19_16 */
+#define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
+
+/* EXYNOS_DP_AUX_CH_CTL_1 */
+#define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
+#define AUX_TX_COMM_MASK			(0xf << 0)
+#define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
+#define AUX_TX_COMM_I2C_TRANSACTION		(0x0 << 3)
+#define AUX_TX_COMM_MOT				(0x1 << 2)
+#define AUX_TX_COMM_WRITE			(0x0 << 0)
+#define AUX_TX_COMM_READ			(0x1 << 0)
+
+/* EXYNOS_DP_AUX_CH_CTL_2 */
+#define ADDR_ONLY				(0x1 << 1)
+#define AUX_EN					(0x1 << 0)
+
+/* EXYNOS_DP_AUX_CH_STA */
+#define AUX_BUSY				(0x1 << 4)
+#define AUX_STATUS_MASK				(0xf << 0)
+
+/* EXYNOS_DP_AUX_RX_COMM */
+#define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
+#define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
+
+/* EXYNOS_DP_PHY_TEST */
+#define MACRO_RST				(0x1 << 5)
+#define CH1_TEST				(0x1 << 1)
+#define CH0_TEST				(0x1 << 0)
+
+/* EXYNOS_DP_TRAINING_PTN_SET */
+#define SCRAMBLER_TYPE				(0x1 << 9)
+#define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
+#define SCRAMBLING_DISABLE			(0x1 << 5)
+#define SCRAMBLING_ENABLE			(0x0 << 5)
+#define LINK_QUAL_PATTERN_SET_MASK		(0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_PRBS7		(0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_D10_2		(0x1 << 2)
+#define LINK_QUAL_PATTERN_SET_DISABLE		(0x0 << 2)
+#define SW_TRAINING_PATTERN_SET_MASK		(0x3 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN2		(0x2 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
+#define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
+
+/* EXYNOS_DP_TOTAL_LINE_CFG */
+#define TOTAL_LINE_CFG_L(x)			((x) & 0xff)
+#define TOTAL_LINE_CFG_H(x)			((((x) >> 8)) & 0xff)
+#define ACTIVE_LINE_CFG_L(x)			((x) & 0xff)
+#define ACTIVE_LINE_CFG_H(x)			(((x) >> 8) & 0xff)
+#define TOTAL_PIXEL_CFG_L(x)			((x) & 0xff)
+#define TOTAL_PIXEL_CFG_H(x)			((((x) >> 8)) & 0xff)
+#define ACTIVE_PIXEL_CFG_L(x)			((x) & 0xff)
+#define ACTIVE_PIXEL_CFG_H(x)			((((x) >> 8)) & 0xff)
+
+#define H_F_PORCH_CFG_L(x)			((x) & 0xff)
+#define H_F_PORCH_CFG_H(x)			((((x) >> 8)) & 0xff)
+#define H_SYNC_PORCH_CFG_L(x)			((x) & 0xff)
+#define H_SYNC_PORCH_CFG_H(x)			((((x) >> 8)) & 0xff)
+#define H_B_PORCH_CFG_L(x)			((x) & 0xff)
+#define H_B_PORCH_CFG_H(x)			((((x) >> 8)) & 0xff)
+
+/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_0		(0x1 << 5)
+#define PRE_EMPHASIS_SET_0_SET(x)		(((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_0_GET(x)		(((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_0_MASK			(0x3 << 3)
+#define PRE_EMPHASIS_SET_0_SHIFT		(3)
+#define PRE_EMPHASIS_SET_0_LEVEL_3		(0x3 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_2		(0x2 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_1		(0x1 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_0		(0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_0		(0x1 << 2)
+#define DRIVE_CURRENT_SET_0_MASK		(0x3 << 0)
+#define DRIVE_CURRENT_SET_0_SET(x)		(((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_0_GET(x)		(((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_0_LEVEL_3		(0x3 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_2		(0x2 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_1		(0x1 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_0		(0x0 << 0)
+
+/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_1		(0x1 << 5)
+#define PRE_EMPHASIS_SET_1_SET(x)		(((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_1_GET(x)		(((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_1_MASK			(0x3 << 3)
+#define PRE_EMPHASIS_SET_1_SHIFT		(3)
+#define PRE_EMPHASIS_SET_1_LEVEL_3		(0x3 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_2		(0x2 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_1		(0x1 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_0		(0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_1		(0x1 << 2)
+#define DRIVE_CURRENT_SET_1_MASK		(0x3 << 0)
+#define DRIVE_CURRENT_SET_1_SET(x)		(((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_1_GET(x)		(((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_1_LEVEL_3		(0x3 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_2		(0x2 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_1		(0x1 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_0		(0x0 << 0)
+
+/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_2		(0x1 << 5)
+#define PRE_EMPHASIS_SET_2_SET(x)		(((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_2_GET(x)		(((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_2_MASK			(0x3 << 3)
+#define PRE_EMPHASIS_SET_2_SHIFT		(3)
+#define PRE_EMPHASIS_SET_2_LEVEL_3		(0x3 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_2		(0x2 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_1		(0x1 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_0		(0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_2		(0x1 << 2)
+#define DRIVE_CURRENT_SET_2_MASK		(0x3 << 0)
+#define DRIVE_CURRENT_SET_2_SET(x)		(((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_2_GET(x)		(((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_2_LEVEL_3		(0x3 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_2		(0x2 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_1		(0x1 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_0		(0x0 << 0)
+
+/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_3		(0x1 << 5)
+#define PRE_EMPHASIS_SET_3_SET(x)		(((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_3_GET(x)		(((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_3_MASK			(0x3 << 3)
+#define PRE_EMPHASIS_SET_3_SHIFT		(3)
+#define PRE_EMPHASIS_SET_3_LEVEL_3		(0x3 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_2		(0x2 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_1		(0x1 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_0		(0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_3		(0x1 << 2)
+#define DRIVE_CURRENT_SET_3_MASK		(0x3 << 0)
+#define DRIVE_CURRENT_SET_3_SET(x)		(((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_3_GET(x)		(((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_3_LEVEL_3		(0x3 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_2		(0x2 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_1		(0x1 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_0		(0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_10 */
+#define FORMAT_SEL				(0x1 << 4)
+#define INTERACE_SCAN_CFG			(0x1 << 2)
+#define INTERACE_SCAN_CFG_SHIFT			(2)
+#define VSYNC_POLARITY_CFG			(0x1 << 1)
+#define V_S_POLARITY_CFG_SHIFT			(1)
+#define HSYNC_POLARITY_CFG			(0x1 << 0)
+#define H_S_POLARITY_CFG_SHIFT			(0)
+
+/* EXYNOS_DP_SOC_GENERAL_CTL */
+#define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
+#define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
+#define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
+#define VIDEO_MASTER_CLK_SEL			(0x1 << 2)
+#define VIDEO_MASTER_MODE_EN			(0x1 << 1)
+#define VIDEO_MODE_MASK				(0x1 << 0)
+#define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
+#define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_1 */
+#define VIDEO_EN				(0x1 << 7)
+#define HDCP_VIDEO_MUTE				(0x1 << 6)
+
+/* EXYNOS_DP_VIDEO_CTL_2 */
+#define IN_D_RANGE_MASK				(0x1 << 7)
+#define IN_D_RANGE_SHIFT			(7)
+#define IN_D_RANGE_CEA				(0x1 << 7)
+#define IN_D_RANGE_VESA				(0x0 << 7)
+#define IN_BPC_MASK				(0x7 << 4)
+#define IN_BPC_SHIFT				(4)
+#define IN_BPC_12_BITS				(0x3 << 4)
+#define IN_BPC_10_BITS				(0x2 << 4)
+#define IN_BPC_8_BITS				(0x1 << 4)
+#define IN_BPC_6_BITS				(0x0 << 4)
+#define IN_COLOR_F_MASK				(0x3 << 0)
+#define IN_COLOR_F_SHIFT			(0)
+#define IN_COLOR_F_YCBCR444			(0x2 << 0)
+#define IN_COLOR_F_YCBCR422			(0x1 << 0)
+#define IN_COLOR_F_RGB				(0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_3 */
+#define IN_YC_COEFFI_MASK			(0x1 << 7)
+#define IN_YC_COEFFI_SHIFT			(7)
+#define IN_YC_COEFFI_ITU709			(0x1 << 7)
+#define IN_YC_COEFFI_ITU601			(0x0 << 7)
+#define VID_CHK_UPDATE_TYPE_MASK		(0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_SHIFT		(4)
+#define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
+
+/* EXYNOS_DP_TEST_PATTERN_GEN_EN */
+#define TEST_PATTERN_GEN_EN			(0x1 << 0)
+#define TEST_PATTERN_GEN_DIS			(0x0 << 0)
+
+/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */
+#define TEST_PATTERN_MODE_COLOR_SQUARE		(0x3 << 0)
+#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES	(0x2 << 0)
+#define TEST_PATTERN_MODE_COLOR_RAMP		(0x1 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_4 */
+#define BIST_EN					(0x1 << 3)
+#define BIST_WIDTH_MASK				(0x1 << 2)
+#define BIST_WIDTH_BAR_32_PIXEL			(0x0 << 2)
+#define BIST_WIDTH_BAR_64_PIXEL			(0x1 << 2)
+#define BIST_TYPE_MASK				(0x3 << 0)
+#define BIST_TYPE_COLOR_BAR			(0x0 << 0)
+#define BIST_TYPE_WHITE_GRAY_BLACK_BAR		(0x1 << 0)
+#define BIST_TYPE_MOBILE_WHITE_BAR		(0x2 << 0)
+
+/* EXYNOS_DP_SYS_CTL_1 */
+#define DET_STA					(0x1 << 2)
+#define FORCE_DET				(0x1 << 1)
+#define DET_CTRL				(0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_2 */
+#define CHA_CRI(x)				(((x) & 0xf) << 4)
+#define CHA_STA					(0x1 << 2)
+#define FORCE_CHA				(0x1 << 1)
+#define CHA_CTRL				(0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_3 */
+#define HPD_STATUS				(0x1 << 6)
+#define F_HPD					(0x1 << 5)
+#define HPD_CTRL				(0x1 << 4)
+#define HDCP_RDY				(0x1 << 3)
+#define STRM_VALID				(0x1 << 2)
+#define F_VALID					(0x1 << 1)
+#define VALID_CTRL				(0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_4 */
+#define FIX_M_AUD				(0x1 << 4)
+#define ENHANCED				(0x1 << 3)
+#define FIX_M_VID				(0x1 << 2)
+#define M_VID_UPDATE_CTRL			(0x3 << 0)
+
+/* EXYNOS_M_VID_X */
+#define M_VID0_CFG(x)				((x) & 0xff)
+#define M_VID1_CFG(x)				(((x) >> 8) & 0xff)
+#define M_VID2_CFG(x)				(((x) >> 16) & 0xff)
+
+/* EXYNOS_M_VID_X */
+#define N_VID0_CFG(x)				((x) & 0xff)
+#define N_VID1_CFG(x)				(((x) >> 8) & 0xff)
+#define N_VID2_CFG(x)				(((x) >> 16) & 0xff)
+
+/* DPCD_TRAINING_PATTERN_SET */
+#define DPCD_SCRAMBLING_DISABLED		(0x1 << 5)
+#define DPCD_SCRAMBLING_ENABLED			(0x0 << 5)
+#define DPCD_TRAINING_PATTERN_2			(0x2 << 0)
+#define DPCD_TRAINING_PATTERN_1			(0x1 << 0)
+#define DPCD_TRAINING_PATTERN_DISABLED		(0x0 << 0)
+
+/* Definition for DPCD Register */
+#define DPCD_DPCD_REV				(0x0000)
+#define DPCD_MAX_LINK_RATE			(0x0001)
+#define DPCD_MAX_LANE_COUNT			(0x0002)
+#define DPCD_LINK_BW_SET			(0x0100)
+#define DPCD_LANE_COUNT_SET			(0x0101)
+#define DPCD_TRAINING_PATTERN_SET		(0x0102)
+#define DPCD_TRAINING_LANE0_SET			(0x0103)
+#define DPCD_LANE0_1_STATUS			(0x0202)
+#define DPCD_LN_ALIGN_UPDATED			(0x0204)
+#define DPCD_ADJUST_REQUEST_LANE0_1		(0x0206)
+#define DPCD_ADJUST_REQUEST_LANE2_3		(0x0207)
+#define DPCD_TEST_REQUEST			(0x0218)
+#define DPCD_TEST_RESPONSE			(0x0260)
+#define DPCD_TEST_EDID_CHECKSUM			(0x0261)
+#define DPCD_SINK_POWER_STATE			(0x0600)
+
+/* DPCD_TEST_REQUEST */
+#define DPCD_TEST_EDID_READ			(0x1 << 2)
+
+/* DPCD_TEST_RESPONSE */
+#define DPCD_TEST_EDID_CHECKSUM_WRITE		(0x1 << 2)
+
+/* DPCD_SINK_POWER_STATE */
+#define DPCD_SET_POWER_STATE_D0			(0x1 << 0)
+#define DPCD_SET_POWER_STATE_D4			(0x2 << 0)
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			(0x50)
+#define I2C_E_EDID_DEVICE_ADDR			(0x30)
+#define EDID_BLOCK_LENGTH			(0x80)
+#define EDID_HEADER_PATTERN			(0x00)
+#define EDID_EXTENSION_FLAG			(0x7e)
+#define EDID_CHECKSUM				(0x7f)
+
+/* DPCD_LANE0_1_STATUS */
+#define DPCD_LANE1_SYMBOL_LOCKED		(0x1 << 6)
+#define DPCD_LANE1_CHANNEL_EQ_DONE		(0x1 << 5)
+#define DPCD_LANE1_CR_DONE			(0x1 << 4)
+#define DPCD_LANE0_SYMBOL_LOCKED		(0x1 << 2)
+#define DPCD_LANE0_CHANNEL_EQ_DONE		(0x1 << 1)
+#define DPCD_LANE0_CR_DONE			(0x1 << 0)
+
+/* DPCD_ADJUST_REQUEST_LANE0_1 */
+#define DPCD_PRE_EMPHASIS_LANE1_MASK		(0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1(x)		(((x) >> 6) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3		(0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2		(0x2 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1		(0x1 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0		(0x0 << 6)
+#define DPCD_VOLTAGE_SWING_LANE1_MASK		(0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1(x)		(((x) >> 4) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3	(0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2	(0x2 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1	(0x1 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0	(0x0 << 4)
+#define DPCD_PRE_EMPHASIS_LANE0_MASK		(0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0(x)		(((x) >> 2) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3		(0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2		(0x2 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1		(0x1 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0		(0x0 << 2)
+#define DPCD_VOLTAGE_SWING_LANE0_MASK		(0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0(x)		(((x) >> 0) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3	(0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2	(0x2 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1	(0x1 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0	(0x0 << 0)
+
+/* DPCD_ADJUST_REQUEST_LANE2_3 */
+#define DPCD_PRE_EMPHASIS_LANE2_MASK		(0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2(x)		(((x) >> 6) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3		(0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2		(0x2 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1		(0x1 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0		(0x0 << 6)
+#define DPCD_VOLTAGE_SWING_LANE2_MASK		(0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2(x)		(((x) >> 4) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3	(0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2	(0x2 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1	(0x1 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0	(0x0 << 4)
+#define DPCD_PRE_EMPHASIS_LANE3_MASK		(0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3(x)		(((x) >> 2) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3		(0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2		(0x2 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1		(0x1 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0		(0x0 << 2)
+#define DPCD_VOLTAGE_SWING_LANE3_MASK		(0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3(x)		(((x) >> 0) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3	(0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2	(0x2 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1	(0x1 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0	(0x0 << 0)
+
+/* DPCD_LANE_COUNT_SET */
+#define DPCD_ENHANCED_FRAME_EN			(0x1 << 7)
+#define DPCD_LN_COUNT_SET(x)			((x) & 0x1f)
+
+/* DPCD_LANE_ALIGN__STATUS_UPDATED */
+#define DPCD_LINK_STATUS_UPDATED		(0x1 << 7)
+#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED	(0x1 << 6)
+#define DPCD_INTERLANE_ALIGN_DONE		(0x1 << 0)
+
+/* DPCD_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3		(0x3 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2		(0x2 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1		(0x1 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0		(0x0 << 3)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3	(0x3 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2	(0x2 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1	(0x1 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0	(0x0 << 0)
+
+#define DPCD_REQ_ADJ_SWING			(0x00)
+#define DPCD_REQ_ADJ_EMPHASIS			(0x01)
+
+#define DP_LANE_STAT_CR_DONE			(0x01 << 0)
+#define DP_LANE_STAT_CE_DONE			(0x01 << 1)
+#define DP_LANE_STAT_SYM_LOCK			(0x01 << 2)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp_info.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp_info.h
new file mode 100644
index 000000000..3f6750a6b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dp_info.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DP_INFO_H
+#define _DP_INFO_H
+
+#define msleep(a)			udelay(a * 1000)
+
+#define DP_TIMEOUT_LOOP_COUNT		100
+#define MAX_CR_LOOP			5
+#define MAX_EQ_LOOP			4
+
+#define EXYNOS_DP_SUCCESS		0
+
+enum {
+	DP_DISABLE,
+	DP_ENABLE,
+};
+
+struct edp_disp_info {
+	char *name;
+	unsigned int h_total;
+	unsigned int h_res;
+	unsigned int h_sync_width;
+	unsigned int h_back_porch;
+	unsigned int h_front_porch;
+	unsigned int v_total;
+	unsigned int v_res;
+	unsigned int v_sync_width;
+	unsigned int v_back_porch;
+	unsigned int v_front_porch;
+
+	unsigned int v_sync_rate;
+};
+
+struct edp_link_train_info {
+	unsigned int lt_status;
+
+	unsigned int ep_loop;
+	unsigned int cr_loop[4];
+
+};
+
+struct edp_video_info {
+	unsigned int master_mode;
+	unsigned int bist_mode;
+	unsigned int bist_pattern;
+
+	unsigned int h_sync_polarity;
+	unsigned int v_sync_polarity;
+	unsigned int interlaced;
+
+	unsigned int color_space;
+	unsigned int dynamic_range;
+	unsigned int ycbcr_coeff;
+	unsigned int color_depth;
+};
+
+struct edp_device_info {
+	struct edp_disp_info disp_info;
+	struct edp_link_train_info lt_info;
+	struct edp_video_info video_info;
+
+	/*below info get from panel during training*/
+	unsigned char lane_bw;
+	unsigned char lane_cnt;
+	unsigned char dpcd_rev;
+	/*support enhanced frame cap */
+	unsigned char dpcd_efc;
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+enum pll_status {
+	PLL_UNLOCKED = 0,
+	PLL_LOCKED
+};
+
+enum {
+	COLOR_RGB,
+	COLOR_YCBCR422,
+	COLOR_YCBCR444
+};
+
+enum {
+	VESA,
+	CEA
+};
+
+enum {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum {
+	DP_LANE_BW_1_62 = 0x06,
+	DP_LANE_BW_2_70 = 0x0a,
+};
+
+enum {
+	DP_LANE_CNT_1 = 1,
+	DP_LANE_CNT_2 = 2,
+	DP_LANE_CNT_4 = 4,
+};
+
+enum {
+	DP_DPCD_REV_10 = 0x10,
+	DP_DPCD_REV_11 = 0x11,
+};
+
+enum {
+	DP_LT_NONE,
+	DP_LT_START,
+	DP_LT_CR,
+	DP_LT_ET,
+	DP_LT_FINISHED,
+	DP_LT_FAIL,
+};
+
+enum  {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pattern_type {
+	NO_PATTERN,
+	COLOR_RAMP,
+	BALCK_WHITE_V_LINES,
+	COLOR_SQUARE,
+	INVALID_PATTERN,
+	COLORBAR_32,
+	COLORBAR_64,
+	WHITE_GRAY_BALCKBAR_32,
+	WHITE_GRAY_BALCKBAR_64,
+	MOBILE_WHITEBAR_32,
+	MOBILE_WHITEBAR_64
+};
+
+enum {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+
+struct exynos_dp_platform_data {
+	struct edp_device_info *edp_dev_info;
+};
+
+#ifdef CONFIG_EXYNOS_DP
+unsigned int exynos_init_dp(void);
+#else
+unsigned int exynos_init_dp(void)
+{
+	return 0;
+}
+#endif
+
+void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
+
+#endif /* _DP_INFO_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dsim.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dsim.h
new file mode 100644
index 000000000..86ff4da4d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dsim.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_DSIM_H_
+#define __ASM_ARM_ARCH_DSIM_H_
+
+#ifndef __ASSEMBLY__
+
+struct exynos_mipi_dsim {
+	unsigned int	status;
+	unsigned int	swrst;
+	unsigned int	clkctrl;
+	unsigned int	timeout;
+	unsigned int	config;
+	unsigned int	escmode;
+	unsigned int	mdresol;
+	unsigned int	mvporch;
+	unsigned int	mhporch;
+	unsigned int	msync;
+	unsigned int	sdresol;
+	unsigned int	intsrc;
+	unsigned int	intmsk;
+	unsigned int	pkthdr;
+	unsigned int	payload;
+	unsigned int	rxfifo;
+	unsigned int	fifothld;
+	unsigned int	fifoctrl;
+	unsigned int	memacchr;
+	unsigned int	pllctrl;
+	unsigned int	plltmr;
+	unsigned int	phyacchr;
+	unsigned int	phyacchr1;
+};
+
+#endif	/* __ASSEMBLY__ */
+
+/*
+ * Bit Definitions
+ */
+/* DSIM_STATUS */
+#define DSIM_STOP_STATE_DAT(x)	(((x) & 0xf) << 0)
+#define DSIM_STOP_STATE_CLK	(1 << 8)
+#define DSIM_TX_READY_HS_CLK	(1 << 10)
+#define DSIM_PLL_STABLE		(1 << 31)
+
+/* DSIM_SWRST */
+#define DSIM_FUNCRST		(1 << 16)
+#define DSIM_SWRST		(1 << 0)
+
+/* EXYNOS_DSIM_TIMEOUT */
+#define DSIM_LPDR_TOUT_SHIFT	(0)
+#define DSIM_BTA_TOUT_SHIFT	(16)
+
+/* EXYNOS_DSIM_CLKCTRL */
+#define DSIM_LANE_ESC_CLKEN_SHIFT	(19)
+#define DSIM_BYTE_CLKEN_SHIFT		(24)
+#define DSIM_BYTE_CLK_SRC_SHIFT		(25)
+#define DSIM_PLL_BYPASS_SHIFT		(27)
+#define DSIM_ESC_CLKEN_SHIFT		(28)
+#define DSIM_TX_REQUEST_HSCLK_SHIFT	(31)
+#define DSIM_LANE_ESC_CLKEN(x)		(((x) & 0x1f) << \
+						DSIM_LANE_ESC_CLKEN_SHIFT)
+#define DSIM_BYTE_CLK_ENABLE		(1 << DSIM_BYTE_CLKEN_SHIFT)
+#define DSIM_BYTE_CLK_DISABLE		(0 << DSIM_BYTE_CLKEN_SHIFT)
+#define DSIM_PLL_BYPASS_EXTERNAL	(1 << DSIM_PLL_BYPASS_SHIFT)
+#define DSIM_ESC_CLKEN_ENABLE		(1 << DSIM_ESC_CLKEN_SHIFT)
+#define DSIM_ESC_CLKEN_DISABLE		(0 << DSIM_ESC_CLKEN_SHIFT)
+
+/* EXYNOS_DSIM_CONFIG */
+#define DSIM_NUM_OF_DATALANE_SHIFT	(5)
+#define DSIM_SUBPIX_SHIFT		(8)
+#define DSIM_MAINPIX_SHIFT		(12)
+#define DSIM_SUBVC_SHIFT		(16)
+#define DSIM_MAINVC_SHIFT		(18)
+#define DSIM_HSA_MODE_SHIFT		(20)
+#define DSIM_HBP_MODE_SHIFT		(21)
+#define DSIM_HFP_MODE_SHIFT		(22)
+#define DSIM_HSE_MODE_SHIFT		(23)
+#define DSIM_AUTO_MODE_SHIFT		(24)
+#define DSIM_VIDEO_MODE_SHIFT		(25)
+#define DSIM_BURST_MODE_SHIFT		(26)
+#define DSIM_EOT_PACKET_SHIFT		(28)
+#define DSIM_AUTO_FLUSH_SHIFT		(29)
+#define DSIM_LANE_ENx(x)		(((x) & 0x1f) << 0)
+
+#define DSIM_NUM_OF_DATA_LANE(x)	((x) << DSIM_NUM_OF_DATALANE_SHIFT)
+
+/* EXYNOS_DSIM_ESCMODE */
+#define DSIM_TX_LPDT_SHIFT		(6)
+#define DSIM_CMD_LPDT_SHIFT		(7)
+#define DSIM_TX_LPDT_LP			(1 << DSIM_TX_LPDT_SHIFT)
+#define DSIM_CMD_LPDT_LP		(1 << DSIM_CMD_LPDT_SHIFT)
+#define DSIM_STOP_STATE_CNT_SHIFT	(21)
+#define DSIM_FORCE_STOP_STATE_SHIFT	(20)
+
+/* EXYNOS_DSIM_MDRESOL */
+#define DSIM_MAIN_STAND_BY		(1 << 31)
+#define DSIM_MAIN_VRESOL(x)		(((x) & 0x7ff) << 16)
+#define DSIM_MAIN_HRESOL(x)		(((x) & 0X7ff) << 0)
+
+/* EXYNOS_DSIM_MVPORCH */
+#define DSIM_CMD_ALLOW_SHIFT		(28)
+#define DSIM_STABLE_VFP_SHIFT		(16)
+#define DSIM_MAIN_VBP_SHIFT		(0)
+#define DSIM_CMD_ALLOW_MASK		(0xf << DSIM_CMD_ALLOW_SHIFT)
+#define DSIM_STABLE_VFP_MASK		(0x7ff << DSIM_STABLE_VFP_SHIFT)
+#define DSIM_MAIN_VBP_MASK		(0x7ff << DSIM_MAIN_VBP_SHIFT)
+
+/* EXYNOS_DSIM_MHPORCH */
+#define DSIM_MAIN_HFP_SHIFT		(16)
+#define DSIM_MAIN_HBP_SHIFT		(0)
+#define DSIM_MAIN_HFP_MASK		((0xffff) << DSIM_MAIN_HFP_SHIFT)
+#define DSIM_MAIN_HBP_MASK		((0xffff) << DSIM_MAIN_HBP_SHIFT)
+
+/* EXYNOS_DSIM_MSYNC */
+#define DSIM_MAIN_VSA_SHIFT		(22)
+#define DSIM_MAIN_HSA_SHIFT		(0)
+#define DSIM_MAIN_VSA_MASK		((0x3ff) << DSIM_MAIN_VSA_SHIFT)
+#define DSIM_MAIN_HSA_MASK		((0xffff) << DSIM_MAIN_HSA_SHIFT)
+
+/* EXYNOS_DSIM_SDRESOL */
+#define DSIM_SUB_STANDY_SHIFT		(31)
+#define DSIM_SUB_VRESOL_SHIFT		(16)
+#define DSIM_SUB_HRESOL_SHIFT		(0)
+#define DSIM_SUB_STANDY_MASK		((0x1) << DSIM_SUB_STANDY_SHIFT)
+#define DSIM_SUB_VRESOL_MASK		((0x7ff) << DSIM_SUB_VRESOL_SHIFT)
+#define DSIM_SUB_HRESOL_MASK		((0x7ff) << DSIM_SUB_HRESOL_SHIFT)
+
+/* EXYNOS_DSIM_INTSRC */
+#define INTSRC_FRAME_DONE		(1 << 24)
+#define INTSRC_PLL_STABLE		(1 << 31)
+#define INTSRC_SWRST_RELEASE		(1 << 30)
+
+/* EXYNOS_DSIM_INTMSK */
+#define INTMSK_FRAME_DONE		(1 << 24)
+
+/* EXYNOS_DSIM_FIFOCTRL */
+#define SFR_HEADER_EMPTY		(1 << 22)
+
+/* EXYNOS_DSIM_PKTHDR */
+#define DSIM_PKTHDR_DI(x)		(((x) & 0x3f) << 0)
+#define DSIM_PKTHDR_DAT0(x)		((x) << 8)
+#define DSIM_PKTHDR_DAT1(x)		((x) << 16)
+
+/* EXYNOS_DSIM_PHYACCHR */
+#define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
+#define DSIM_AFC_CTL_SHIFT		(5)
+#define DSIM_AFC_EN			(1 << 14)
+
+/* EXYNOS_DSIM_PHYACCHR1 */
+#define DSIM_DPDN_SWAP_DATA_SHIFT	(0)
+
+/* EXYNOS_DSIM_PLLCTRL */
+#define DSIM_SCALER_SHIFT		(1)
+#define DSIM_MAIN_SHIFT			(4)
+#define DSIM_PREDIV_SHIFT		(13)
+#define DSIM_PRECTRL_SHIFT		(20)
+#define DSIM_PLL_EN_SHIFT		(23)
+#define DSIM_FREQ_BAND_SHIFT		(24)
+#define DSIM_ZEROCTRL_SHIFT		(28)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dwmmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dwmmc.h
new file mode 100644
index 000000000..a7ca12c47
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define DWMCI_CLKSEL		0x09C
+#define DWMCI_SET_SAMPLE_CLK(x)	(x)
+#define DWMCI_SET_DRV_CLK(x)	((x) << 16)
+#define DWMCI_SET_DIV_RATIO(x)	((x) << 24)
+
+#define EMMCP_MPSBEGIN0		0x1200
+#define EMMCP_SEND0		0x1204
+#define EMMCP_CTRL0		0x120C
+
+#define MPSCTRL_SECURE_READ_BIT		(0x1<<7)
+#define MPSCTRL_SECURE_WRITE_BIT	(0x1<<6)
+#define MPSCTRL_NON_SECURE_READ_BIT	(0x1<<5)
+#define MPSCTRL_NON_SECURE_WRITE_BIT	(0x1<<4)
+#define MPSCTRL_USE_FUSE_KEY		(0x1<<3)
+#define MPSCTRL_ECB_MODE		(0x1<<2)
+#define MPSCTRL_ENCRYPTION		(0x1<<1)
+#define MPSCTRL_VALID			(0x1<<0)
+
+/* CLKSEL Register */
+#define DWMCI_DIVRATIO_BIT		24
+#define DWMCI_DIVRATIO_MASK		0x7
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/ehci.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/ehci.h
new file mode 100644
index 000000000..d2d70bd82
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/ehci.h
@@ -0,0 +1,67 @@
+/*
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *	Vivek Gautam <gautam.vivek@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_EHCI_H__
+#define __ASM_ARM_ARCH_EHCI_H__
+
+#define CLK_24MHZ		5
+
+#define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
+#define HOST_CTRL0_COMMONON_N			(1 << 9)
+#define HOST_CTRL0_SIDDQ			(1 << 6)
+#define HOST_CTRL0_FORCESLEEP			(1 << 5)
+#define HOST_CTRL0_FORCESUSPEND			(1 << 4)
+#define HOST_CTRL0_WORDINTERFACE		(1 << 3)
+#define HOST_CTRL0_UTMISWRST			(1 << 2)
+#define HOST_CTRL0_LINKSWRST			(1 << 1)
+#define HOST_CTRL0_PHYSWRST			(1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK			(7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN			(1 << 29)
+#define EHCICTRL_ENAINCR4			(1 << 28)
+#define EHCICTRL_ENAINCR8			(1 << 27)
+#define EHCICTRL_ENAINCR16			(1 << 26)
+
+#define HSIC_CTRL_REFCLKSEL                     (0x2)
+#define HSIC_CTRL_REFCLKSEL_MASK                (0x3)
+#define HSIC_CTRL_REFCLKSEL_SHIFT               (23)
+
+#define HSIC_CTRL_REFCLKDIV_12                  (0x24)
+#define HSIC_CTRL_REFCLKDIV_MASK                (0x7f)
+#define HSIC_CTRL_REFCLKDIV_SHIFT               (16)
+
+#define HSIC_CTRL_SIDDQ                         (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP                    (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND                  (0x1 << 4)
+#define HSIC_CTRL_UTMISWRST                     (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST                      (0x1 << 0)
+
+/* Register map for PHY control */
+struct exynos_usb_phy {
+	unsigned int usbphyctrl0;
+	unsigned int usbphytune0;
+	unsigned int reserved1[2];
+	unsigned int hsicphyctrl1;
+	unsigned int hsicphytune1;
+	unsigned int reserved2[2];
+	unsigned int hsicphyctrl2;
+	unsigned int hsicphytune2;
+	unsigned int reserved3[2];
+	unsigned int ehcictrl;
+	unsigned int ohcictrl;
+	unsigned int usbotgsys;
+	unsigned int reserved4;
+	unsigned int usbotgtune;
+};
+
+/* Switch on the VBUS power. */
+int board_usb_vbus_init(void);
+
+#endif /* __ASM_ARM_ARCH_EHCI_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/fb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/fb.h
new file mode 100644
index 000000000..f0d69b730
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/fb.h
@@ -0,0 +1,457 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_FB_H_
+#define __ASM_ARM_ARCH_FB_H_
+
+#ifndef __ASSEMBLY__
+struct exynos_fb {
+	unsigned int vidcon0;
+	unsigned int vidcon1;
+	unsigned int vidcon2;
+	unsigned int vidcon3;
+	unsigned int vidtcon0;
+	unsigned int vidtcon1;
+	unsigned int vidtcon2;
+	unsigned int vidtcon3;
+	unsigned int wincon0;
+	unsigned int wincon1;
+	unsigned int wincon2;
+	unsigned int wincon3;
+	unsigned int wincon4;
+
+	unsigned int winshmap;
+	unsigned int res1;
+
+	unsigned int winchmap2;
+	unsigned int vidosd0a;
+	unsigned int vidosd0b;
+	unsigned int vidosd0c;
+	unsigned int res2;
+
+	unsigned int vidosd1a;
+	unsigned int vidosd1b;
+	unsigned int vidosd1c;
+	unsigned int vidosd1d;
+
+	unsigned int vidosd2a;
+	unsigned int vidosd2b;
+	unsigned int vidosd2c;
+	unsigned int vidosd2d;
+
+	unsigned int vidosd3a;
+	unsigned int vidosd3b;
+	unsigned int vidosd3c;
+	unsigned int res3;
+
+	unsigned int vidosd4a;
+	unsigned int vidosd4b;
+	unsigned int vidosd4c;
+	unsigned int res4[5];
+
+	unsigned int vidw00add0b0;
+	unsigned int vidw00add0b1;
+	unsigned int vidw01add0b0;
+	unsigned int vidw01add0b1;
+
+	unsigned int vidw02add0b0;
+	unsigned int vidw02add0b1;
+	unsigned int vidw03add0b0;
+	unsigned int vidw03add0b1;
+	unsigned int vidw04add0b0;
+	unsigned int vidw04add0b1;
+	unsigned int res5[2];
+
+	unsigned int vidw00add1b0;
+	unsigned int vidw00add1b1;
+	unsigned int vidw01add1b0;
+	unsigned int vidw01add1b1;
+
+	unsigned int vidw02add1b0;
+	unsigned int vidw02add1b1;
+	unsigned int vidw03add1b0;
+	unsigned int vidw03add1b1;
+
+	unsigned int vidw04add1b0;
+	unsigned int vidw04add1b1;
+	unsigned int res7[2];
+
+	unsigned int vidw00add2;
+	unsigned int vidw01add2;
+	unsigned int vidw02add2;
+	unsigned int vidw03add2;
+	unsigned int vidw04add2;
+	unsigned int res8[7];
+
+	unsigned int vidintcon0;
+	unsigned int vidintcon1;
+	unsigned int res9[1];
+
+	unsigned int w1keycon0;
+	unsigned int w1keycon1;
+	unsigned int w2keycon0;
+	unsigned int w2keycon1;
+	unsigned int w3keycon0;
+	unsigned int w3keycon1;
+	unsigned int w4keycon0;
+	unsigned int w4keycon1;
+
+	unsigned int w1keyalpha;
+	unsigned int w2keyalpha;
+	unsigned int w3keyalpha;
+	unsigned int w4keyalpha;
+
+	unsigned int dithmode;
+	unsigned int res10[2];
+
+	unsigned int win0map;
+	unsigned int win1map;
+	unsigned int win2map;
+	unsigned int win3map;
+	unsigned int win4map;
+	unsigned int res11[1];
+
+	unsigned int wpalcon_h;
+	unsigned int wpalcon_l;
+
+	unsigned int trigcon;
+	unsigned int res12[2];
+
+	unsigned int i80ifcona0;
+	unsigned int i80ifcona1;
+	unsigned int i80ifconb0;
+	unsigned int i80ifconb1;
+
+	unsigned int colorgaincon;
+	unsigned int res13[2];
+
+	unsigned int ldi_cmdcon0;
+	unsigned int ldi_cmdcon1;
+	unsigned int res14[1];
+
+	/* To be updated */
+
+	unsigned char res15[156];
+	unsigned int dualrgb;
+	unsigned char res16[16];
+	unsigned int dp_mie_clkcon;
+};
+#endif
+
+/* LCD IF register offset */
+#define EXYNOS4_LCD_IF_BASE_OFFSET			0x0
+#define EXYNOS5_LCD_IF_BASE_OFFSET			0x20000
+
+static inline unsigned int exynos_fimd_get_base_offset(void)
+{
+	if (cpu_is_exynos5())
+		return EXYNOS5_LCD_IF_BASE_OFFSET;
+	else
+		return EXYNOS4_LCD_IF_BASE_OFFSET;
+}
+
+/*
+ *  Register offsets
+*/
+#define EXYNOS_WINCON(x)				(x * 0x04)
+#define EXYNOS_VIDOSD(x)				(x * 0x10)
+#define EXYNOS_BUFFER_OFFSET(x)				(x * 0x08)
+#define EXYNOS_BUFFER_SIZE(x)				(x * 0x04)
+
+/*
+ * Bit Definitions
+*/
+
+/* VIDCON0 */
+#define EXYNOS_VIDCON0_DSI_DISABLE			(0 << 30)
+#define EXYNOS_VIDCON0_DSI_ENABLE			(1 << 30)
+#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE			(0 << 29)
+#define EXYNOS_VIDCON0_SCAN_INTERLACE			(1 << 29)
+#define EXYNOS_VIDCON0_SCAN_MASK			(1 << 29)
+#define EXYNOS_VIDCON0_VIDOUT_RGB			(0 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_ITU			(1 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_I80LDI0			(2 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_I80LDI1			(3 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_RGB			(4 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0		(6 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1		(7 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_MASK			(7 << 26)
+#define EXYNOS_VIDCON0_PNRMODE_RGB_P			(0 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_BGR_P			(1 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_RGB_S			(2 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_BGR_S			(3 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_MASK			(3 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_SHIFT			(17)
+#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS			(0 << 16)
+#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME		(1 << 16)
+#define EXYNOS_VIDCON0_CLKVALUP_MASK			(1 << 16)
+#define EXYNOS_VIDCON0_CLKVAL_F(x)			(((x) & 0xff) << 6)
+#define EXYNOS_VIDCON0_VCLKEN_NORMAL			(0 << 5)
+#define EXYNOS_VIDCON0_VCLKEN_FREERUN			(1 << 5)
+#define EXYNOS_VIDCON0_VCLKEN_MASK			(1 << 5)
+#define EXYNOS_VIDCON0_CLKDIR_DIRECTED			(0 << 4)
+#define EXYNOS_VIDCON0_CLKDIR_DIVIDED			(1 << 4)
+#define EXYNOS_VIDCON0_CLKDIR_MASK			(1 << 4)
+#define EXYNOS_VIDCON0_CLKSEL_HCLK			(0 << 2)
+#define EXYNOS_VIDCON0_CLKSEL_SCLK			(1 << 2)
+#define EXYNOS_VIDCON0_CLKSEL_MASK			(1 << 2)
+#define EXYNOS_VIDCON0_ENVID_ENABLE			(1 << 1)
+#define EXYNOS_VIDCON0_ENVID_DISABLE			(0 << 1)
+#define EXYNOS_VIDCON0_ENVID_F_ENABLE			(1 << 0)
+#define EXYNOS_VIDCON0_ENVID_F_DISABLE			(0 << 0)
+
+/* VIDCON1 */
+#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE		(0 << 7)
+#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE		(1 << 7)
+#define EXYNOS_VIDCON1_IHSYNC_NORMAL			(0 << 6)
+#define EXYNOS_VIDCON1_IHSYNC_INVERT			(1 << 6)
+#define EXYNOS_VIDCON1_IVSYNC_NORMAL			(0 << 5)
+#define EXYNOS_VIDCON1_IVSYNC_INVERT			(1 << 5)
+#define EXYNOS_VIDCON1_IVDEN_NORMAL			(0 << 4)
+#define EXYNOS_VIDCON1_IVDEN_INVERT			(1 << 4)
+
+/* VIDCON2 */
+#define EXYNOS_VIDCON2_EN601_DISABLE			(0 << 23)
+#define EXYNOS_VIDCON2_EN601_ENABLE			(1 << 23)
+#define EXYNOS_VIDCON2_EN601_MASK			(1 << 23)
+#define EXYNOS_VIDCON2_WB_DISABLE			(0 << 15)
+#define EXYNOS_VIDCON2_WB_ENABLE			(1 << 15)
+#define EXYNOS_VIDCON2_WB_MASK				(1 << 15)
+#define EXYNOS_VIDCON2_TVFORMATSEL_HW			(0 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_SW			(1 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_MASK			(1 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422		(1 << 12)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444		(2 << 12)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK		(3 << 12)
+#define EXYNOS_VIDCON2_ORGYUV_YCBCR			(0 << 8)
+#define EXYNOS_VIDCON2_ORGYUV_CBCRY			(1 << 8)
+#define EXYNOS_VIDCON2_ORGYUV_MASK			(1 << 8)
+#define EXYNOS_VIDCON2_YUVORD_CBCR			(0 << 7)
+#define EXYNOS_VIDCON2_YUVORD_CRCB			(1 << 7)
+#define EXYNOS_VIDCON2_YUVORD_MASK			(1 << 7)
+
+/* PRTCON */
+#define EXYNOS_PRTCON_UPDATABLE				(0 << 11)
+#define EXYNOS_PRTCON_PROTECT				(1 << 11)
+
+/* VIDTCON0 */
+#define EXYNOS_VIDTCON0_VBPDE(x)			(((x) & 0xff) << 24)
+#define EXYNOS_VIDTCON0_VBPD(x)				(((x) & 0xff) << 16)
+#define EXYNOS_VIDTCON0_VFPD(x)				(((x) & 0xff) << 8)
+#define EXYNOS_VIDTCON0_VSPW(x)				(((x) & 0xff) << 0)
+
+/* VIDTCON1 */
+#define EXYNOS_VIDTCON1_VFPDE(x)			(((x) & 0xff) << 24)
+#define EXYNOS_VIDTCON1_HBPD(x)				(((x) & 0xff) << 16)
+#define EXYNOS_VIDTCON1_HFPD(x)				(((x) & 0xff) << 8)
+#define EXYNOS_VIDTCON1_HSPW(x)				(((x) & 0xff) << 0)
+
+/* VIDTCON2 */
+#define EXYNOS_VIDTCON2_LINEVAL(x)			(((x) & 0x7ff) << 11)
+#define EXYNOS_VIDTCON2_HOZVAL(x)			(((x) & 0x7ff) << 0)
+#define EXYNOS_VIDTCON2_LINEVAL_E(x)			((((x) & 0x800) >> 11) << 23)
+#define EXYNOS_VIDTCON2_HOZVAL_E(x)			((((x) & 0x800) >> 11) << 22)
+
+/* Window 0~4 Control - WINCONx */
+#define EXYNOS_WINCON_DATAPATH_DMA			(0 << 22)
+#define EXYNOS_WINCON_DATAPATH_LOCAL			(1 << 22)
+#define EXYNOS_WINCON_DATAPATH_MASK			(1 << 22)
+#define EXYNOS_WINCON_BUFSEL_0				(0 << 20)
+#define EXYNOS_WINCON_BUFSEL_1				(1 << 20)
+#define EXYNOS_WINCON_BUFSEL_MASK			(1 << 20)
+#define EXYNOS_WINCON_BUFSEL_SHIFT			(20)
+#define EXYNOS_WINCON_BUFAUTO_DISABLE			(0 << 19)
+#define EXYNOS_WINCON_BUFAUTO_ENABLE			(1 << 19)
+#define EXYNOS_WINCON_BUFAUTO_MASK			(1 << 19)
+#define EXYNOS_WINCON_BITSWP_DISABLE			(0 << 18)
+#define EXYNOS_WINCON_BITSWP_ENABLE			(1 << 18)
+#define EXYNOS_WINCON_BITSWP_SHIFT			(18)
+#define EXYNOS_WINCON_BYTESWP_DISABLE			(0 << 17)
+#define EXYNOS_WINCON_BYTESWP_ENABLE			(1 << 17)
+#define EXYNOS_WINCON_BYTESWP_SHIFT			(17)
+#define EXYNOS_WINCON_HAWSWP_DISABLE			(0 << 16)
+#define EXYNOS_WINCON_HAWSWP_ENABLE			(1 << 16)
+#define EXYNOS_WINCON_HAWSWP_SHIFT			(16)
+#define EXYNOS_WINCON_WSWP_DISABLE			(0 << 15)
+#define EXYNOS_WINCON_WSWP_ENABLE			(1 << 15)
+#define EXYNOS_WINCON_WSWP_SHIFT			(15)
+#define EXYNOS_WINCON_INRGB_RGB				(0 << 13)
+#define EXYNOS_WINCON_INRGB_YUV				(1 << 13)
+#define EXYNOS_WINCON_INRGB_MASK			(1 << 13)
+#define EXYNOS_WINCON_BURSTLEN_16WORD			(0 << 9)
+#define EXYNOS_WINCON_BURSTLEN_8WORD			(1 << 9)
+#define EXYNOS_WINCON_BURSTLEN_4WORD			(2 << 9)
+#define EXYNOS_WINCON_BURSTLEN_MASK			(3 << 9)
+#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE		(0 << 7)
+#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE		(1 << 7)
+#define EXYNOS_WINCON_BLD_PLANE				(0 << 6)
+#define EXYNOS_WINCON_BLD_PIXEL				(1 << 6)
+#define EXYNOS_WINCON_BLD_MASK				(1 << 6)
+#define EXYNOS_WINCON_BPPMODE_1BPP			(0 << 2)
+#define EXYNOS_WINCON_BPPMODE_2BPP			(1 << 2)
+#define EXYNOS_WINCON_BPPMODE_4BPP			(2 << 2)
+#define EXYNOS_WINCON_BPPMODE_8BPP_PAL			(3 << 2)
+#define EXYNOS_WINCON_BPPMODE_8BPP			(4 << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_565			(5 << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_A555		(6 << 2)
+#define EXYNOS_WINCON_BPPMODE_18BPP_666			(8 << 2)
+#define EXYNOS_WINCON_BPPMODE_18BPP_A665		(9 << 2)
+#define EXYNOS_WINCON_BPPMODE_24BPP_888			(0xb << 2)
+#define EXYNOS_WINCON_BPPMODE_24BPP_A887		(0xc << 2)
+#define EXYNOS_WINCON_BPPMODE_32BPP			(0xd << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_A444		(0xe << 2)
+#define EXYNOS_WINCON_BPPMODE_15BPP_555			(0xf << 2)
+#define EXYNOS_WINCON_BPPMODE_MASK			(0xf << 2)
+#define EXYNOS_WINCON_BPPMODE_SHIFT			(2)
+#define EXYNOS_WINCON_ALPHA0_SEL			(0 << 1)
+#define EXYNOS_WINCON_ALPHA1_SEL			(1 << 1)
+#define EXYNOS_WINCON_ALPHA_SEL_MASK			(1 << 1)
+#define EXYNOS_WINCON_ENWIN_DISABLE			(0 << 0)
+#define EXYNOS_WINCON_ENWIN_ENABLE			(1 << 0)
+
+/* WINCON1 special */
+#define EXYNOS_WINCON1_VP_DISABLE			(0 << 24)
+#define EXYNOS_WINCON1_VP_ENABLE			(1 << 24)
+#define EXYNOS_WINCON1_LOCALSEL_FIMC1			(0 << 23)
+#define EXYNOS_WINCON1_LOCALSEL_VP			(1 << 23)
+#define EXYNOS_WINCON1_LOCALSEL_MASK			(1 << 23)
+
+/* WINSHMAP */
+#define EXYNOS_WINSHMAP_PROTECT(x)			(((x) & 0x1f) << 10)
+#define EXYNOS_WINSHMAP_CH_ENABLE(x)			(1 << (x))
+#define EXYNOS_WINSHMAP_CH_DISABLE(x)			(1 << (x))
+#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x)			(0x20 << (x))
+#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x)		(0x20 << (x))
+
+/* VIDOSDxA, VIDOSDxB */
+#define EXYNOS_VIDOSD_LEFT_X(x)				(((x) & 0x7ff) << 11)
+#define EXYNOS_VIDOSD_TOP_Y(x)				(((x) & 0x7ff) << 0)
+#define EXYNOS_VIDOSD_RIGHT_X(x)			(((x) & 0x7ff) << 11)
+#define EXYNOS_VIDOSD_BOTTOM_Y(x)			(((x) & 0x7ff) << 0)
+#define EXYNOS_VIDOSD_RIGHT_X_E(x)			(((x) & 0x1) << 23)
+#define EXYNOS_VIDOSD_BOTTOM_Y_E(x)			(((x) & 0x1) << 22)
+
+/* VIDOSD0C, VIDOSDxD */
+#define EXYNOS_VIDOSD_SIZE(x)				(((x) & 0xffffff) << 0)
+
+/* VIDOSDxC (1~4) */
+#define EXYNOS_VIDOSD_ALPHA0_R(x)			(((x) & 0xf) << 20)
+#define EXYNOS_VIDOSD_ALPHA0_G(x)			(((x) & 0xf) << 16)
+#define EXYNOS_VIDOSD_ALPHA0_B(x)			(((x) & 0xf) << 12)
+#define EXYNOS_VIDOSD_ALPHA1_R(x)			(((x) & 0xf) << 8)
+#define EXYNOS_VIDOSD_ALPHA1_G(x)			(((x) & 0xf) << 4)
+#define EXYNOS_VIDOSD_ALPHA1_B(x)			(((x) & 0xf) << 0)
+#define EXYNOS_VIDOSD_ALPHA0_SHIFT			(12)
+#define EXYNOS_VIDOSD_ALPHA1_SHIFT			(0)
+
+/* Start Address */
+#define EXYNOS_VIDADDR_START_VBANK(x)			(((x) & 0xff) << 24)
+#define EXYNOS_VIDADDR_START_VBASEU(x)			(((x) & 0xffffff) << 0)
+
+/* End Address */
+#define EXYNOS_VIDADDR_END_VBASEL(x)			(((x) & 0xffffff) << 0)
+
+/* Buffer Size */
+#define EXYNOS_VIDADDR_OFFSIZE(x)			(((x) & 0x1fff) << 13)
+#define EXYNOS_VIDADDR_PAGEWIDTH(x)			(((x) & 0x1fff) << 0)
+#define EXYNOS_VIDADDR_OFFSIZE_E(x)			((((x) & 0x2000) >> 13) << 27)
+#define EXYNOS_VIDADDR_PAGEWIDTH_E(x)			((((x) & 0x2000) >> 13) << 26)
+
+/* WIN Color Map */
+#define EXYNOS_WINMAP_COLOR(x)				((x) & 0xffffff)
+
+/* VIDINTCON0 */
+#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE		(0 << 19)
+#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE		(1 << 19)
+#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE		(0 << 18)
+#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE		(1 << 18)
+#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE		(0 << 17)
+#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE		(1 << 17)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK		(0 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC		(1 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE		(2 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT		(3 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK		(3 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE		(0 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK		(1 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC		(2 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT		(3 << 13)
+#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE		(0 << 12)
+#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE		(1 << 12)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4			(1 << 11)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3			(1 << 10)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2			(1 << 9)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1			(1 << 6)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0			(1 << 5)
+#define EXYNOS_VIDINTCON0_FIFOSEL_ALL			(0x73 << 5)
+#define EXYNOS_VIDINTCON0_FIFOSEL_MASK			(0x73 << 5)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_25			(0 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_50			(1 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_75			(2 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY		(3 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL		(4 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK		(7 << 2)
+#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE		(0 << 1)
+#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE		(1 << 1)
+#define EXYNOS_VIDINTCON0_INT_DISABLE			(0 << 0)
+#define EXYNOS_VIDINTCON0_INT_ENABLE			(1 << 0)
+#define EXYNOS_VIDINTCON0_INT_MASK			(1 << 0)
+
+/* VIDINTCON1 */
+#define EXYNOS_VIDINTCON1_INTVPPEND			(1 << 5)
+#define EXYNOS_VIDINTCON1_INTI80PEND			(1 << 2)
+#define EXYNOS_VIDINTCON1_INTFRMPEND			(1 << 1)
+#define EXYNOS_VIDINTCON1_INTFIFOPEND			(1 << 0)
+
+/* WINMAP */
+#define EXYNOS_WINMAP_ENABLE				(1 << 24)
+
+/* WxKEYCON0 (1~4) */
+#define EXYNOS_KEYCON0_KEYBLEN_DISABLE			(0 << 26)
+#define EXYNOS_KEYCON0_KEYBLEN_ENABLE			(1 << 26)
+#define EXYNOS_KEYCON0_KEY_DISABLE			(0 << 25)
+#define EXYNOS_KEYCON0_KEY_ENABLE			(1 << 25)
+#define EXYNOS_KEYCON0_DIRCON_MATCH_FG			(0 << 24)
+#define EXYNOS_KEYCON0_DIRCON_MATCH_BG			(1 << 24)
+#define EXYNOS_KEYCON0_COMPKEY(x)			(((x) & 0xffffff) << 0)
+
+/* WxKEYCON1 (1~4) */
+#define EXYNOS_KEYCON1_COLVAL(x)			(((x) & 0xffffff) << 0)
+
+/* DUALRGB */
+#define EXYNOS_DUALRGB_BYPASS_SINGLE			(0x00 << 0)
+#define EXYNOS_DUALRGB_BYPASS_DUAL			(0x01 << 0)
+#define EXYNOS_DUALRGB_MIE_DUAL				(0x10 << 0)
+#define EXYNOS_DUALRGB_MIE_SINGLE			(0x11 << 0)
+#define EXYNOS_DUALRGB_LINESPLIT			(0x0 << 2)
+#define EXYNOS_DUALRGB_FRAMESPLIT			(0x1 << 2)
+#define EXYNOS_DUALRGB_SUB_CNT(x)			((x & 0xfff) << 4)
+#define EXYNOS_DUALRGB_VDEN_EN_DISABLE			(0x0 << 16)
+#define EXYNOS_DUALRGB_VDEN_EN_ENABLE			(0x1 << 16)
+#define EXYNOS_DUALRGB_MAIN_CNT(x)			((x & 0xfff) << 18)
+
+/* I80IFCONA0 and I80IFCONA1 */
+#define EXYNOS_LCD_CS_SETUP(x)				(((x) & 0xf) << 16)
+#define EXYNOS_LCD_WR_SETUP(x)				(((x) & 0xf) << 12)
+#define EXYNOS_LCD_WR_ACT(x)				(((x) & 0xf) << 8)
+#define EXYNOS_LCD_WR_HOLD(x)				(((x) & 0xf) << 4)
+#define EXYNOS_RSPOL_LOW				(0 << 2)
+#define EXYNOS_RSPOL_HIGH				(1 << 2)
+#define EXYNOS_I80IFEN_DISABLE				(0 << 0)
+#define EXYNOS_I80IFEN_ENABLE				(1 << 0)
+
+/* TRIGCON */
+#define EXYNOS_I80SOFT_TRIG_EN				(1 << 0)
+#define EXYNOS_I80START_TRIG				(1 << 1)
+#define EXYNOS_I80STATUS_TRIG_DONE			(1 << 2)
+
+/* DP_MIE_CLKCON */
+#define EXYNOS_DP_MIE_DISABLE				(0 << 0)
+#define EXYNOS_DP_CLK_ENABLE				(1 << 1)
+#define EXYNOS_MIE_CLK_ENABLE				(3 << 0)
+
+#endif /* _REGS_FB_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/gpio.h
new file mode 100644
index 000000000..d6868fa25
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/gpio.h
@@ -0,0 +1,346 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+struct s5p_gpio_bank {
+	unsigned int	con;
+	unsigned int	dat;
+	unsigned int	pull;
+	unsigned int	drv;
+	unsigned int	pdn_con;
+	unsigned int	pdn_pull;
+	unsigned char	res1[8];
+};
+
+struct exynos4_gpio_part1 {
+	struct s5p_gpio_bank a0;
+	struct s5p_gpio_bank a1;
+	struct s5p_gpio_bank b;
+	struct s5p_gpio_bank c0;
+	struct s5p_gpio_bank c1;
+	struct s5p_gpio_bank d0;
+	struct s5p_gpio_bank d1;
+	struct s5p_gpio_bank e0;
+	struct s5p_gpio_bank e1;
+	struct s5p_gpio_bank e2;
+	struct s5p_gpio_bank e3;
+	struct s5p_gpio_bank e4;
+	struct s5p_gpio_bank f0;
+	struct s5p_gpio_bank f1;
+	struct s5p_gpio_bank f2;
+	struct s5p_gpio_bank f3;
+};
+
+struct exynos4_gpio_part2 {
+	struct s5p_gpio_bank j0;
+	struct s5p_gpio_bank j1;
+	struct s5p_gpio_bank k0;
+	struct s5p_gpio_bank k1;
+	struct s5p_gpio_bank k2;
+	struct s5p_gpio_bank k3;
+	struct s5p_gpio_bank l0;
+	struct s5p_gpio_bank l1;
+	struct s5p_gpio_bank l2;
+	struct s5p_gpio_bank y0;
+	struct s5p_gpio_bank y1;
+	struct s5p_gpio_bank y2;
+	struct s5p_gpio_bank y3;
+	struct s5p_gpio_bank y4;
+	struct s5p_gpio_bank y5;
+	struct s5p_gpio_bank y6;
+	struct s5p_gpio_bank res1[80];
+	struct s5p_gpio_bank x0;
+	struct s5p_gpio_bank x1;
+	struct s5p_gpio_bank x2;
+	struct s5p_gpio_bank x3;
+};
+
+struct exynos4_gpio_part3 {
+	struct s5p_gpio_bank z;
+};
+
+struct exynos4x12_gpio_part1 {
+	struct s5p_gpio_bank a0;
+	struct s5p_gpio_bank a1;
+	struct s5p_gpio_bank b;
+	struct s5p_gpio_bank c0;
+	struct s5p_gpio_bank c1;
+	struct s5p_gpio_bank d0;
+	struct s5p_gpio_bank d1;
+	struct s5p_gpio_bank res1[0x5];
+	struct s5p_gpio_bank f0;
+	struct s5p_gpio_bank f1;
+	struct s5p_gpio_bank f2;
+	struct s5p_gpio_bank f3;
+	struct s5p_gpio_bank res2[0x2];
+	struct s5p_gpio_bank j0;
+	struct s5p_gpio_bank j1;
+};
+
+struct exynos4x12_gpio_part2 {
+	struct s5p_gpio_bank res1[0x2];
+	struct s5p_gpio_bank k0;
+	struct s5p_gpio_bank k1;
+	struct s5p_gpio_bank k2;
+	struct s5p_gpio_bank k3;
+	struct s5p_gpio_bank l0;
+	struct s5p_gpio_bank l1;
+	struct s5p_gpio_bank l2;
+	struct s5p_gpio_bank y0;
+	struct s5p_gpio_bank y1;
+	struct s5p_gpio_bank y2;
+	struct s5p_gpio_bank y3;
+	struct s5p_gpio_bank y4;
+	struct s5p_gpio_bank y5;
+	struct s5p_gpio_bank y6;
+	struct s5p_gpio_bank res2[0x3];
+	struct s5p_gpio_bank m0;
+	struct s5p_gpio_bank m1;
+	struct s5p_gpio_bank m2;
+	struct s5p_gpio_bank m3;
+	struct s5p_gpio_bank m4;
+	struct s5p_gpio_bank res3[0x48];
+	struct s5p_gpio_bank x0;
+	struct s5p_gpio_bank x1;
+	struct s5p_gpio_bank x2;
+	struct s5p_gpio_bank x3;
+};
+
+struct exynos4x12_gpio_part3 {
+	struct s5p_gpio_bank z;
+};
+
+struct exynos4x12_gpio_part4 {
+	struct s5p_gpio_bank v0;
+	struct s5p_gpio_bank v1;
+	struct s5p_gpio_bank res1[0x1];
+	struct s5p_gpio_bank v2;
+	struct s5p_gpio_bank v3;
+	struct s5p_gpio_bank res2[0x1];
+	struct s5p_gpio_bank v4;
+};
+
+struct exynos5420_gpio_part1 {
+	struct s5p_gpio_bank a0;
+	struct s5p_gpio_bank a1;
+	struct s5p_gpio_bank a2;
+	struct s5p_gpio_bank b0;
+	struct s5p_gpio_bank b1;
+	struct s5p_gpio_bank b2;
+	struct s5p_gpio_bank b3;
+	struct s5p_gpio_bank b4;
+	struct s5p_gpio_bank h0;
+};
+
+struct exynos5420_gpio_part2 {
+	struct s5p_gpio_bank y7; /* 0x1340_0000 */
+	struct s5p_gpio_bank res[0x5f]; /*  */
+	struct s5p_gpio_bank x0; /* 0x1340_0C00 */
+	struct s5p_gpio_bank x1; /* 0x1340_0C20 */
+	struct s5p_gpio_bank x2; /* 0x1340_0C40 */
+	struct s5p_gpio_bank x3; /* 0x1340_0C60 */
+};
+
+struct exynos5420_gpio_part3 {
+	struct s5p_gpio_bank c0;
+	struct s5p_gpio_bank c1;
+	struct s5p_gpio_bank c2;
+	struct s5p_gpio_bank c3;
+	struct s5p_gpio_bank c4;
+	struct s5p_gpio_bank d1;
+	struct s5p_gpio_bank y0;
+	struct s5p_gpio_bank y1;
+	struct s5p_gpio_bank y2;
+	struct s5p_gpio_bank y3;
+	struct s5p_gpio_bank y4;
+	struct s5p_gpio_bank y5;
+	struct s5p_gpio_bank y6;
+};
+
+struct exynos5420_gpio_part4 {
+	struct s5p_gpio_bank e0; /* 0x1400_0000 */
+	struct s5p_gpio_bank e1; /* 0x1400_0020 */
+	struct s5p_gpio_bank f0; /* 0x1400_0040 */
+	struct s5p_gpio_bank f1; /* 0x1400_0060 */
+	struct s5p_gpio_bank g0; /* 0x1400_0080 */
+	struct s5p_gpio_bank g1; /* 0x1400_00A0 */
+	struct s5p_gpio_bank g2; /* 0x1400_00C0 */
+	struct s5p_gpio_bank j4; /* 0x1400_00E0 */
+};
+
+struct exynos5420_gpio_part5 {
+	struct s5p_gpio_bank z0; /* 0x0386_0000 */
+};
+
+struct exynos5_gpio_part1 {
+	struct s5p_gpio_bank a0;
+	struct s5p_gpio_bank a1;
+	struct s5p_gpio_bank a2;
+	struct s5p_gpio_bank b0;
+	struct s5p_gpio_bank b1;
+	struct s5p_gpio_bank b2;
+	struct s5p_gpio_bank b3;
+	struct s5p_gpio_bank c0;
+	struct s5p_gpio_bank c1;
+	struct s5p_gpio_bank c2;
+	struct s5p_gpio_bank c3;
+	struct s5p_gpio_bank d0;
+	struct s5p_gpio_bank d1;
+	struct s5p_gpio_bank y0;
+	struct s5p_gpio_bank y1;
+	struct s5p_gpio_bank y2;
+	struct s5p_gpio_bank y3;
+	struct s5p_gpio_bank y4;
+	struct s5p_gpio_bank y5;
+	struct s5p_gpio_bank y6;
+	struct s5p_gpio_bank res1[0x3];
+	struct s5p_gpio_bank c4;
+	struct s5p_gpio_bank res2[0x48];
+	struct s5p_gpio_bank x0;
+	struct s5p_gpio_bank x1;
+	struct s5p_gpio_bank x2;
+	struct s5p_gpio_bank x3;
+};
+
+struct exynos5_gpio_part2 {
+	struct s5p_gpio_bank e0;
+	struct s5p_gpio_bank e1;
+	struct s5p_gpio_bank f0;
+	struct s5p_gpio_bank f1;
+	struct s5p_gpio_bank g0;
+	struct s5p_gpio_bank g1;
+	struct s5p_gpio_bank g2;
+	struct s5p_gpio_bank h0;
+	struct s5p_gpio_bank h1;
+};
+
+struct exynos5_gpio_part3 {
+	struct s5p_gpio_bank v0;
+	struct s5p_gpio_bank v1;
+	struct s5p_gpio_bank res1[0x1];
+	struct s5p_gpio_bank v2;
+	struct s5p_gpio_bank v3;
+	struct s5p_gpio_bank res2[0x1];
+	struct s5p_gpio_bank v4;
+};
+
+struct exynos5_gpio_part4 {
+	struct s5p_gpio_bank z;
+};
+
+/* functions */
+void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
+void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
+void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
+unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+
+/* GPIO pins per bank  */
+#define GPIO_PER_BANK 8
+#define S5P_GPIO_PART_SHIFT	(24)
+#define S5P_GPIO_PART_MASK	(0xff)
+#define S5P_GPIO_BANK_SHIFT	(8)
+#define S5P_GPIO_BANK_MASK	(0xffff)
+#define S5P_GPIO_PIN_MASK	(0xff)
+
+#define S5P_GPIO_SET_PART(x) \
+			(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+
+#define S5P_GPIO_GET_PART(x) \
+			(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+
+#define S5P_GPIO_SET_PIN(x) \
+			((x) & S5P_GPIO_PIN_MASK)
+
+#define EXYNOS4_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos4_gpio_part##part *) \
+			EXYNOS4_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS4_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos4x12_gpio_part##part *) \
+			EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS4X12_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS5_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos5420_gpio_part##part *) \
+			EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS5_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS5420_GPIO_SET_BANK(part, bank) \
+			((((unsigned)&(((struct exynos5420_gpio_part##part *) \
+			EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
+			- EXYNOS5420_GPIO_PART##part##_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define exynos4_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS4_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define exynos4x12_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS4X12_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define exynos5420_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS5420_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define exynos5_gpio_get(part, bank, pin) \
+			(S5P_GPIO_SET_PART(part) | \
+			EXYNOS5_GPIO_SET_BANK(part, bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+static inline unsigned int s5p_gpio_base(int gpio)
+{
+	unsigned gpio_part = S5P_GPIO_GET_PART(gpio);
+
+	switch (gpio_part) {
+	case 1:
+		return samsung_get_base_gpio_part1();
+	case 2:
+		return samsung_get_base_gpio_part2();
+	case 3:
+		return samsung_get_base_gpio_part3();
+	case 4:
+		return samsung_get_base_gpio_part4();
+	default:
+		return 0;
+	}
+}
+#endif
+
+/* Pin configurations */
+#define GPIO_INPUT	0x0
+#define GPIO_OUTPUT	0x1
+#define GPIO_IRQ	0xf
+#define GPIO_FUNC(x)	(x)
+
+/* Pull mode */
+#define GPIO_PULL_NONE	0x0
+#define GPIO_PULL_DOWN	0x1
+#define GPIO_PULL_UP	0x3
+
+/* Drive Strength level */
+#define GPIO_DRV_1X	0x0
+#define GPIO_DRV_3X	0x1
+#define GPIO_DRV_2X	0x2
+#define GPIO_DRV_4X	0x3
+#define GPIO_DRV_FAST	0x0
+#define GPIO_DRV_SLOW	0x1
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/i2s-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/i2s-regs.h
new file mode 100644
index 000000000..4a4a7a00b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/i2s-regs.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __I2S_REGS_H__
+#define __I2S_REGS_H__
+
+#define CON_RESET		(1 << 31)
+#define CON_TXFIFO_FULL		(1 << 8)
+#define CON_TXCH_PAUSE		(1 << 4)
+#define CON_ACTIVE		(1 << 0)
+
+#define MOD_OP_CLK		(3 << 30)
+#define MOD_BLCP_SHIFT		24
+#define MOD_BLCP_16BIT		(0 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_8BIT		(1 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_24BIT		(2 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_MASK		(3 << MOD_BLCP_SHIFT)
+
+#define MOD_BLC_16BIT		(0 << 13)
+#define MOD_BLC_8BIT		(1 << 13)
+#define MOD_BLC_24BIT		(2 << 13)
+#define MOD_BLC_MASK		(3 << 13)
+
+#define MOD_SLAVE		(1 << 11)
+#define MOD_RCLKSRC		(0 << 10)
+#define MOD_MASK		(3 << 8)
+#define MOD_LR_LLOW		(0 << 7)
+#define MOD_LR_RLOW		(1 << 7)
+#define MOD_SDF_IIS		(0 << 5)
+#define MOD_SDF_MSB		(1 << 5)
+#define MOD_SDF_LSB		(2 << 5)
+#define MOD_SDF_MASK		(3 << 5)
+#define MOD_RCLK_256FS		(0 << 3)
+#define MOD_RCLK_512FS		(1 << 3)
+#define MOD_RCLK_384FS		(2 << 3)
+#define MOD_RCLK_768FS		(3 << 3)
+#define MOD_RCLK_MASK		(3 << 3)
+#define MOD_BCLK_32FS		(0 << 1)
+#define MOD_BCLK_48FS		(1 << 1)
+#define MOD_BCLK_16FS		(2 << 1)
+#define MOD_BCLK_24FS		(3 << 1)
+#define MOD_BCLK_MASK		(3 << 1)
+
+#define MOD_CDCLKCON		(1 << 12)
+
+#define FIC_TXFLUSH		(1 << 15)
+#define FIC_RXFLUSH		(1 << 7)
+
+#define PSREN			(1 << 15)
+#define PSVAL			(3 << 8)
+
+#endif /* __I2S_REGS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mipi_dsim.h
new file mode 100644
index 000000000..50e5c258a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mipi_dsim.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DSIM_H
+#define _DSIM_H
+
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <lcd.h>
+
+#define PANEL_NAME_SIZE		(32)
+
+enum mipi_dsim_interface_type {
+	DSIM_COMMAND,
+	DSIM_VIDEO
+};
+
+enum mipi_dsim_virtual_ch_no {
+	DSIM_VIRTUAL_CH_0,
+	DSIM_VIRTUAL_CH_1,
+	DSIM_VIRTUAL_CH_2,
+	DSIM_VIRTUAL_CH_3
+};
+
+enum mipi_dsim_burst_mode_type {
+	DSIM_NON_BURST_SYNC_EVENT,
+	DSIM_BURST_SYNC_EVENT,
+	DSIM_NON_BURST_SYNC_PULSE,
+	DSIM_BURST,
+	DSIM_NON_VIDEO_MODE
+};
+
+enum mipi_dsim_no_of_data_lane {
+	DSIM_DATA_LANE_1,
+	DSIM_DATA_LANE_2,
+	DSIM_DATA_LANE_3,
+	DSIM_DATA_LANE_4
+};
+
+enum mipi_dsim_byte_clk_src {
+	DSIM_PLL_OUT_DIV8,
+	DSIM_EXT_CLK_DIV8,
+	DSIM_EXT_CLK_BYPASS
+};
+
+enum mipi_dsim_pixel_format {
+	DSIM_CMD_3BPP,
+	DSIM_CMD_8BPP,
+	DSIM_CMD_12BPP,
+	DSIM_CMD_16BPP,
+	DSIM_VID_16BPP_565,
+	DSIM_VID_18BPP_666PACKED,
+	DSIM_18BPP_666LOOSELYPACKED,
+	DSIM_24BPP_888
+};
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+	MIPI_DSI_V_SYNC_START				= 0x01,
+	MIPI_DSI_V_SYNC_END				= 0x11,
+	MIPI_DSI_H_SYNC_START				= 0x21,
+	MIPI_DSI_H_SYNC_END				= 0x31,
+
+	MIPI_DSI_COLOR_MODE_OFF				= 0x02,
+	MIPI_DSI_COLOR_MODE_ON				= 0x12,
+	MIPI_DSI_SHUTDOWN_PERIPHERAL			= 0x22,
+	MIPI_DSI_TURN_ON_PERIPHERAL			= 0x32,
+
+	MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM		= 0x03,
+	MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM		= 0x13,
+	MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM		= 0x23,
+
+	MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM		= 0x04,
+	MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM		= 0x14,
+	MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM		= 0x24,
+
+	MIPI_DSI_DCS_SHORT_WRITE			= 0x05,
+	MIPI_DSI_DCS_SHORT_WRITE_PARAM			= 0x15,
+
+	MIPI_DSI_DCS_READ				= 0x06,
+
+	MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE		= 0x37,
+
+	MIPI_DSI_END_OF_TRANSMISSION			= 0x08,
+
+	MIPI_DSI_NULL_PACKET				= 0x09,
+	MIPI_DSI_BLANKING_PACKET			= 0x19,
+	MIPI_DSI_GENERIC_LONG_WRITE			= 0x29,
+	MIPI_DSI_DCS_LONG_WRITE				= 0x39,
+
+	MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20	= 0x0c,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24		= 0x1c,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16		= 0x2c,
+
+	MIPI_DSI_PACKED_PIXEL_STREAM_30			= 0x0d,
+	MIPI_DSI_PACKED_PIXEL_STREAM_36			= 0x1d,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12		= 0x3d,
+
+	MIPI_DSI_PACKED_PIXEL_STREAM_16			= 0x0e,
+	MIPI_DSI_PACKED_PIXEL_STREAM_18			= 0x1e,
+	MIPI_DSI_PIXEL_STREAM_3BYTE_18			= 0x2e,
+	MIPI_DSI_PACKED_PIXEL_STREAM_24			= 0x3e,
+};
+
+/*
+ * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
+ *
+ * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
+ * @eot_disable: enable or disable EoT packet in HS mode.
+ * @auto_vertical_cnt: specifies auto vertical count mode.
+ *	in Video mode, the vertical line transition uses line counter
+ *	configured by VSA, VBP, and Vertical resolution.
+ *	If this bit is set to '1', the line counter does not use VSA and VBP
+ *	registers.(in command mode, this variable is ignored)
+ * @hse: set horizontal sync event mode.
+ *	In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
+ *	start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
+ *	this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
+ *	(in mommand mode, this variable is ignored)
+ * @hfp: specifies HFP disable mode.
+ *	if this variable is set, DSI master ignores HFP area in VIDEO mode.
+ *	(in command mode, this variable is ignored)
+ * @hbp: specifies HBP disable mode.
+ *	if this variable is set, DSI master ignores HBP area in VIDEO mode.
+ *	(in command mode, this variable is ignored)
+ * @hsa: specifies HSA disable mode.
+ *	if this variable is set, DSI master ignores HSA area in VIDEO mode.
+ *	(in command mode, this variable is ignored)
+ * @e_interface: specifies interface to be used.(CPU or RGB interface)
+ * @e_virtual_ch: specifies virtual channel number that main or
+ *	sub diaplsy uses.
+ * @e_pixel_format: specifies pixel stream format for main or sub display.
+ * @e_burst_mode: selects Burst mode in Video mode.
+ *	in Non-burst mode, RGB data area is filled with RGB data and NULL
+ *	packets, according to input bandwidth of RGB interface.
+ *	In Burst mode, RGB data area is filled with RGB data only.
+ * @e_no_data_lane: specifies data lane count to be used by Master.
+ * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
+ *	DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
+ * @pll_stable_time: specifies the PLL Timer for stability of the ganerated
+ *	clock(System clock cycle base)
+ *	if the timer value goes to 0x00000000, the clock stable bit of status
+ *	and interrupt register is set.
+ * @esc_clk: specifies escape clock frequency for getting the escape clock
+ *	prescaler value.
+ * @stop_holding_cnt: specifies the interval value between transmitting
+ *	read packet(or write "set_tear_on" command) and BTA request.
+ *	after transmitting read packet or write "set_tear_on" command,
+ *	BTA requests to D-PHY automatically. this counter value specifies
+ *	the interval between them.
+ * @bta_timeout: specifies the timer for BTA.
+ *	this register specifies time out from BTA request to change
+ *	the direction with respect to Tx escape clock.
+ * @rx_timeout: specifies the timer for LP Rx mode timeout.
+ *	this register specifies time out on how long RxValid deasserts,
+ *	after RxLpdt asserts with respect to Tx escape clock.
+ *	- RxValid specifies Rx data valid indicator.
+ *	- RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
+ *	- RxValid and RxLpdt specifies signal from D-PHY.
+ */
+struct mipi_dsim_config {
+	unsigned char			auto_flush;
+	unsigned char			eot_disable;
+
+	unsigned char			auto_vertical_cnt;
+	unsigned char			hse;
+	unsigned char			hfp;
+	unsigned char			hbp;
+	unsigned char			hsa;
+
+	enum mipi_dsim_interface_type	e_interface;
+	enum mipi_dsim_virtual_ch_no	e_virtual_ch;
+	enum mipi_dsim_pixel_format	e_pixel_format;
+	enum mipi_dsim_burst_mode_type	e_burst_mode;
+	enum mipi_dsim_no_of_data_lane	e_no_data_lane;
+	enum mipi_dsim_byte_clk_src	e_byte_clk;
+
+	/*
+	 * ===========================================
+	 * |    P    |    M    |    S    |    MHz    |
+	 * -------------------------------------------
+	 * |    3    |   100   |    3    |    100    |
+	 * |    3    |   100   |    2    |    200    |
+	 * |    3    |    63   |    1    |    252    |
+	 * |    4    |   100   |    1    |    300    |
+	 * |    4    |   110   |    1    |    330    |
+	 * |   12    |   350   |    1    |    350    |
+	 * |    3    |   100   |    1    |    400    |
+	 * |    4    |   150   |    1    |    450    |
+	 * |    6    |   118   |    1    |    472    |
+	 * |	3    |   120   |    1    |    480    |
+	 * |   12    |   250   |    0    |    500    |
+	 * |    4    |   100   |    0    |    600    |
+	 * |    3    |    81   |    0    |    648    |
+	 * |    3    |    88   |    0    |    704    |
+	 * |    3    |    90   |    0    |    720    |
+	 * |    3    |   100   |    0    |    800    |
+	 * |   12    |   425   |    0    |    850    |
+	 * |    4    |   150   |    0    |    900    |
+	 * |   12    |   475   |    0    |    950    |
+	 * |    6    |   250   |    0    |   1000    |
+	 * -------------------------------------------
+	 */
+
+	/*
+	 * pms could be calculated as the following.
+	 * M * 24 / P * 2 ^ S = MHz
+	 */
+	unsigned char			p;
+	unsigned short			m;
+	unsigned char			s;
+
+	unsigned int			pll_stable_time;
+	unsigned long			esc_clk;
+
+	unsigned short			stop_holding_cnt;
+	unsigned char			bta_timeout;
+	unsigned short			rx_timeout;
+};
+
+/*
+ * struct mipi_dsim_device - global interface for mipi-dsi driver.
+ *
+ * @dsim_config: infomation for configuring mipi-dsi controller.
+ * @master_ops: callbacks to mipi-dsi operations.
+ * @dsim_lcd_dev: pointer to activated ddi device.
+ *	(it would be registered by mipi-dsi driver.)
+ * @dsim_lcd_drv: pointer to activated_ddi driver.
+ *	(it would be registered by mipi-dsi driver.)
+ * @state: specifies status of MIPI-DSI controller.
+ *	the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
+ * @data_lane: specifiec enabled data lane number.
+ *	this variable would be set by driver according to e_no_data_lane
+ *	automatically.
+ * @e_clk_src: select byte clock source.
+ * @pd: pointer to MIPI-DSI driver platform data.
+ */
+struct mipi_dsim_device {
+	struct mipi_dsim_config		*dsim_config;
+	struct mipi_dsim_master_ops	*master_ops;
+	struct mipi_dsim_lcd_device	*dsim_lcd_dev;
+	struct mipi_dsim_lcd_driver	*dsim_lcd_drv;
+
+	unsigned int			state;
+	unsigned int			data_lane;
+	enum mipi_dsim_byte_clk_src	e_clk_src;
+
+	struct exynos_platform_mipi_dsim	*pd;
+};
+
+/*
+ * struct exynos_platform_mipi_dsim - interface to platform data
+ *	for mipi-dsi driver.
+ *
+ * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
+ *	lcd panel driver searched would be actived.
+ * @dsim_config: pointer of structure for configuring mipi-dsi controller.
+ * @lcd_panel_info: pointer for lcd panel specific structure.
+ *	this structure specifies width, height, timing and polarity and so on.
+ * @lcd_power: callback pointer for enabling or disabling lcd power.
+ * @mipi_power: callback pointer for enabling or disabling mipi power.
+ * @phy_enable: pointer to a callback controlling D-PHY enable/reset
+ */
+struct exynos_platform_mipi_dsim {
+	char				lcd_panel_name[PANEL_NAME_SIZE];
+
+	struct mipi_dsim_config		*dsim_config;
+	void				*lcd_panel_info;
+
+	int (*lcd_power)(void);
+	int (*mipi_power)(void);
+	void (*phy_enable)(unsigned int dev_index, unsigned int enable);
+};
+
+/*
+ * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations.
+ *
+ * @cmd_write: transfer command to lcd panel at LP mode.
+ * @cmd_read: read command from rx register.
+ * @get_dsim_frame_done: get the status that all screen data have been
+ *	transferred to mipi-dsi.
+ * @clear_dsim_frame_done: clear frame done status.
+ * @get_fb_frame_done: get frame done status of display controller.
+ * @trigger: trigger display controller.
+ *	- this one would be used only in case of CPU mode.
+ */
+struct mipi_dsim_master_ops {
+	int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
+		const unsigned char *data0, unsigned int data1);
+	int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
+		unsigned int data0, unsigned int data1);
+	int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
+	int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
+
+	int (*get_fb_frame_done)(void);
+	void (*trigger)(struct fb_info *info);
+};
+
+/*
+ * device structure for mipi-dsi based lcd panel.
+ *
+ * @name: name of the device to use with this device, or an
+ *	alias for that name.
+ * @id: id of device to be registered.
+ * @bus_id: bus id for identifing connected bus
+ *	and this bus id should be same as id of mipi_dsim_device.
+ * @master: pointer to mipi-dsi master device object.
+ * @platform_data: lcd panel specific platform data.
+ */
+struct mipi_dsim_lcd_device {
+	char			*name;
+	int			id;
+	int			bus_id;
+	int			reverse_panel;
+
+	struct mipi_dsim_device *master;
+	void			*platform_data;
+};
+
+/*
+ * driver structure for mipi-dsi based lcd panel.
+ *
+ * this structure should be registered by lcd panel driver.
+ * mipi-dsi driver seeks lcd panel registered through name field
+ * and calls these callback functions in appropriate time.
+ *
+ * @name: name of the driver to use with this device, or an
+ *	alias for that name.
+ * @id: id of driver to be registered.
+ *	this id would be used for finding device object registered.
+ * @mipi_panel_init: callback pointer for initializing lcd panel based on mipi
+ *	dsi interface.
+ * @mipi_display_on: callback pointer for lcd panel display on.
+ */
+struct mipi_dsim_lcd_driver {
+	char			*name;
+	int			id;
+
+	int	(*mipi_panel_init)(struct mipi_dsim_device *dsim_dev);
+	void	(*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
+};
+
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
+int exynos_mipi_dsi_init(void);
+#else
+static inline int exynos_mipi_dsi_init(void)
+{
+	return 0;
+}
+#endif
+
+/*
+ * register mipi_dsim_lcd_driver object defined by lcd panel driver
+ * to mipi-dsi driver.
+ */
+int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
+						*lcd_drv);
+
+/*
+ * register mipi_dsim_lcd_device to mipi-dsi master.
+ */
+int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
+						*lcd_dev);
+
+void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
+void exynos_init_dsim_platform_data(vidinfo_t *vid);
+
+/* panel driver init based on mipi dsi interface */
+void s6e8ax0_init(void);
+
+#ifdef CONFIG_OF_CONTROL
+extern int mipi_power(void);
+#endif
+#endif /* _DSIM_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mmc.h
new file mode 100644
index 000000000..0fb6461c0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/mmc.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MMC_H_
+#define __ASM_ARCH_MMC_H_
+
+#define S5P_MMC_DEV_OFFSET	0x10000
+
+#define SDHCI_CONTROL2		0x80
+#define SDHCI_CONTROL3		0x84
+#define SDHCI_CONTROL4		0x8C
+
+#define SDHCI_CTRL2_ENSTAASYNCCLR	(1 << 31)
+#define SDHCI_CTRL2_ENCMDCNFMSK		(1 << 30)
+#define SDHCI_CTRL2_CDINVRXD3		(1 << 29)
+#define SDHCI_CTRL2_SLCARDOUT		(1 << 28)
+
+#define SDHCI_CTRL2_FLTCLKSEL_MASK	(0xf << 24)
+#define SDHCI_CTRL2_FLTCLKSEL_SHIFT	(24)
+#define SDHCI_CTRL2_FLTCLKSEL(_x)	((_x) << 24)
+
+#define SDHCI_CTRL2_LVLDAT_MASK		(0xff << 16)
+#define SDHCI_CTRL2_LVLDAT_SHIFT	(16)
+#define SDHCI_CTRL2_LVLDAT(_x)		((_x) << 16)
+
+#define SDHCI_CTRL2_ENFBCLKTX		(1 << 15)
+#define SDHCI_CTRL2_ENFBCLKRX		(1 << 14)
+#define SDHCI_CTRL2_SDCDSEL		(1 << 13)
+#define SDHCI_CTRL2_SDSIGPC		(1 << 12)
+#define SDHCI_CTRL2_ENBUSYCHKTXSTART	(1 << 11)
+
+#define SDHCI_CTRL2_DFCNT_MASK(_x)	((_x) << 9)
+#define SDHCI_CTRL2_DFCNT_SHIFT		(9)
+
+#define SDHCI_CTRL2_ENCLKOUTHOLD	(1 << 8)
+#define SDHCI_CTRL2_RWAITMODE		(1 << 7)
+#define SDHCI_CTRL2_DISBUFRD		(1 << 6)
+#define SDHCI_CTRL2_SELBASECLK_MASK(_x)	((_x) << 4)
+#define SDHCI_CTRL2_SELBASECLK_SHIFT	(4)
+#define SDHCI_CTRL2_PWRSYNC		(1 << 3)
+#define SDHCI_CTRL2_ENCLKOUTMSKCON	(1 << 1)
+#define SDHCI_CTRL2_HWINITFIN		(1 << 0)
+
+#define SDHCI_CTRL3_FCSEL3		(1 << 31)
+#define SDHCI_CTRL3_FCSEL2		(1 << 23)
+#define SDHCI_CTRL3_FCSEL1		(1 << 15)
+#define SDHCI_CTRL3_FCSEL0		(1 << 7)
+
+#define SDHCI_CTRL4_DRIVE_MASK(_x)	((_x) << 16)
+#define SDHCI_CTRL4_DRIVE_SHIFT		(16)
+
+#define SDHCI_MAX_HOSTS 4
+
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
+
+static inline int s5p_mmc_init(int index, int bus_width)
+{
+	unsigned int base = samsung_get_base_mmc() +
+				(S5P_MMC_DEV_OFFSET * index);
+
+	return s5p_sdhci_init(base, index, bus_width);
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_mmc_init(const void *blob);
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/periph.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/periph.h
new file mode 100644
index 000000000..5c1c3d4a9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/periph.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+	PERIPH_ID_UART0 = 51,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+	PERIPH_ID_UART3,
+	PERIPH_ID_I2C0 = 56,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_I2C4,
+	PERIPH_ID_I2C5,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_I2C7,
+	PERIPH_ID_SPI0 = 68,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SPI2,
+	PERIPH_ID_SDMMC0 = 75,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_I2C8 = 87,
+	PERIPH_ID_I2C9,
+	PERIPH_ID_I2S0 = 98,
+	PERIPH_ID_I2S1 = 99,
+
+	/* Since following peripherals do
+	 * not have shared peripheral interrupts (SPIs)
+	 * they are numbered arbitiraly after the maximum
+	 * SPIs Exynos has (128)
+	 */
+	PERIPH_ID_SROMC = 128,
+	PERIPH_ID_SPI3,
+	PERIPH_ID_SPI4,
+	PERIPH_ID_SDMMC4,
+	PERIPH_ID_PWM0,
+	PERIPH_ID_PWM1,
+	PERIPH_ID_PWM2,
+	PERIPH_ID_PWM3,
+	PERIPH_ID_PWM4,
+	PERIPH_ID_I2C10 = 203,
+
+	PERIPH_ID_NONE = -1,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pinmux.h
new file mode 100644
index 000000000..0b91ef658
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pinmux.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PINMUX_H
+#define __ASM_ARM_ARCH_PINMUX_H
+
+#include "periph.h"
+
+/*
+ * Flags for setting specific configarations of peripherals.
+ * List will grow with support for more devices getting added.
+ */
+enum {
+	PINMUX_FLAG_NONE	= 0x00000000,
+
+	/* Flags for eMMC */
+	PINMUX_FLAG_8BIT_MODE	= 1 << 0,       /* SDMMC 8-bit mode */
+
+	/* Flags for SROM controller */
+	PINMUX_FLAG_BANK	= 3 << 0,       /* bank number (0-3) */
+	PINMUX_FLAG_16BIT	= 1 << 2,       /* 16-bit width */
+};
+
+/**
+ * Configures the pinmux for a particular peripheral.
+ *
+ * Each gpio can be configured in many different ways (4 bits on exynos)
+ * such as "input", "output", "special function", "external interrupt"
+ * etc. This function will configure the peripheral pinmux along with
+ * pull-up/down and drive strength.
+ *
+ * @param peripheral	peripheral to be configured
+ * @param flags		configure flags
+ * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
+ */
+int exynos_pinmux_config(int peripheral, int flags);
+
+/**
+ * Decode the peripheral id using the interrpt numbers.
+ *
+ * @param blob  Device tree blob
+ * @param node  FDT I2C node to find
+ * @return peripheral id if ok, PERIPH_ID_NONE on error
+ */
+int pinmux_decode_periph_id(const void *blob, int node);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/power.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/power.h
new file mode 100644
index 000000000..c9609a23f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/power.h
@@ -0,0 +1,1729 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_POWER_H_
+#define __ASM_ARM_ARCH_POWER_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_power {
+	unsigned int	om_stat;
+	unsigned char	res1[0x8];
+	unsigned int	rtc_clko_sel;
+	unsigned int	gnss_rtc_out_ctrl;
+	unsigned char	res2[0x1ec];
+	unsigned int	system_power_down_ctrl;
+	unsigned int	res3;
+	unsigned int	system_power_down_option;
+	unsigned char	res4[0x1f4];
+	unsigned int	swreset;
+	unsigned int	rst_stat;
+	unsigned char	res5[0x1f8];
+	unsigned int	wakeup_stat;
+	unsigned int	eint_wakeup_mask;
+	unsigned int	wakeup_mask;
+	unsigned char	res6[0xf4];
+	unsigned int	hdmi_phy_control;
+	unsigned int	usbdevice_phy_control;
+	unsigned int	usbhost_phy_control;
+	unsigned int	dac_phy_control;
+	unsigned int	mipi_phy0_control;
+	unsigned int	mipi_phy1_control;
+	unsigned int	adc_phy_control;
+	unsigned int	pcie_phy_control;
+	unsigned int	sata_phy_control;
+	unsigned char	res7[0xdc];
+	unsigned int	inform0;
+	unsigned int	inform1;
+	unsigned int	inform2;
+	unsigned int	inform3;
+	unsigned int	inform4;
+	unsigned int	inform5;
+	unsigned int	inform6;
+	unsigned int	inform7;
+	unsigned char	res8[0x1e0];
+	unsigned int	pmu_debug;
+	unsigned char	res9[0x5fc];
+	unsigned int	arm_core0_sys_pwr_reg;
+	unsigned char	res10[0xc];
+	unsigned int	arm_core1_sys_pwr_reg;
+	unsigned char	res11[0x6c];
+	unsigned int	arm_common_sys_pwr_reg;
+	unsigned char	res12[0x3c];
+	unsigned int	arm_cpu_l2_0_sys_pwr_reg;
+	unsigned int	arm_cpu_l2_1_sys_pwr_reg;
+	unsigned char	res13[0x38];
+	unsigned int	cmu_aclkstop_sys_pwr_reg;
+	unsigned int	cmu_sclkstop_sys_pwr_reg;
+	unsigned char	res14[0x4];
+	unsigned int	cmu_reset_sys_pwr_reg;
+	unsigned char	res15[0x10];
+	unsigned int	apll_sysclk_sys_pwr_reg;
+	unsigned int	mpll_sysclk_sys_pwr_reg;
+	unsigned int	vpll_sysclk_sys_pwr_reg;
+	unsigned int	epll_sysclk_sys_pwr_reg;
+	unsigned char	res16[0x8];
+	unsigned int	cmu_clkstop_gps_alive_sys_pwr_reg;
+	unsigned int	cmu_reset_gps_alive_sys_pwr_reg;
+	unsigned int	cmu_clkstop_cam_sys_pwr_reg;
+	unsigned int	cmu_clkstop_tv_sys_pwr_reg;
+	unsigned int	cmu_clkstop_mfc_sys_pwr_reg;
+	unsigned int	cmu_clkstop_g3d_sys_pwr_reg;
+	unsigned int	cmu_clkstop_lcd0_sys_pwr_reg;
+	unsigned int	cmu_clkstop_lcd1_sys_pwr_reg;
+	unsigned int	cmu_clkstop_maudio_sys_pwr_reg;
+	unsigned int	cmu_clkstop_gps_sys_pwr_reg;
+	unsigned int	cmu_reset_cam_sys_pwr_reg;
+	unsigned int	cmu_reset_tv_sys_pwr_reg;
+	unsigned int	cmu_reset_mfc_sys_pwr_reg;
+	unsigned int	cmu_reset_g3d_sys_pwr_reg;
+	unsigned int	cmu_reset_lcd0_sys_pwr_reg;
+	unsigned int	cmu_reset_lcd1_sys_pwr_reg;
+	unsigned int	cmu_reset_maudio_sys_pwr_reg;
+	unsigned int	cmu_reset_gps_sys_pwr_reg;
+	unsigned int	top_bus_sys_pwr_reg;
+	unsigned int	top_retention_sys_pwr_reg;
+	unsigned int	top_pwr_sys_pwr_reg;
+	unsigned char	res17[0x1c];
+	unsigned int	logic_reset_sys_pwr_reg;
+	unsigned char	res18[0x14];
+	unsigned int	onenandxl_mem_sys_pwr_reg;
+	unsigned int	modemif_mem_sys_pwr_reg;
+	unsigned char	res19[0x4];
+	unsigned int	usbdevice_mem_sys_pwr_reg;
+	unsigned int	sdmmc_mem_sys_pwr_reg;
+	unsigned int	cssys_mem_sys_pwr_reg;
+	unsigned int	secss_mem_sys_pwr_reg;
+	unsigned char	res20[0x4];
+	unsigned int	pcie_mem_sys_pwr_reg;
+	unsigned int	sata_mem_sys_pwr_reg;
+	unsigned char	res21[0x18];
+	unsigned int	pad_retention_dram_sys_pwr_reg;
+	unsigned int	pad_retention_maudio_sys_pwr_reg;
+	unsigned char	res22[0x18];
+	unsigned int	pad_retention_gpio_sys_pwr_reg;
+	unsigned int	pad_retention_uart_sys_pwr_reg;
+	unsigned int	pad_retention_mmca_sys_pwr_reg;
+	unsigned int	pad_retention_mmcb_sys_pwr_reg;
+	unsigned int	pad_retention_ebia_sys_pwr_reg;
+	unsigned int	pad_retention_ebib_sys_pwr_reg;
+	unsigned char	res23[0x8];
+	unsigned int	pad_isolation_sys_pwr_reg;
+	unsigned char	res24[0x1c];
+	unsigned int	pad_alv_sel_sys_pwr_reg;
+	unsigned char	res25[0x1c];
+	unsigned int	xusbxti_sys_pwr_reg;
+	unsigned int	xxti_sys_pwr_reg;
+	unsigned char	res26[0x38];
+	unsigned int	ext_regulator_sys_pwr_reg;
+	unsigned char	res27[0x3c];
+	unsigned int	gpio_mode_sys_pwr_reg;
+	unsigned char	res28[0x3c];
+	unsigned int	gpio_mode_maudio_sys_pwr_reg;
+	unsigned char	res29[0x3c];
+	unsigned int	cam_sys_pwr_reg;
+	unsigned int	tv_sys_pwr_reg;
+	unsigned int	mfc_sys_pwr_reg;
+	unsigned int	g3d_sys_pwr_reg;
+	unsigned int	lcd0_sys_pwr_reg;
+	unsigned int	lcd1_sys_pwr_reg;
+	unsigned int	maudio_sys_pwr_reg;
+	unsigned int	gps_sys_pwr_reg;
+	unsigned int	gps_alive_sys_pwr_reg;
+	unsigned char	res30[0xc5c];
+	unsigned int	arm_core0_configuration;
+	unsigned int	arm_core0_status;
+	unsigned int	arm_core0_option;
+	unsigned char	res31[0x74];
+	unsigned int	arm_core1_configuration;
+	unsigned int	arm_core1_status;
+	unsigned int	arm_core1_option;
+	unsigned char	res32[0x37c];
+	unsigned int	arm_common_option;
+	unsigned char	res33[0x1f4];
+	unsigned int	arm_cpu_l2_0_configuration;
+	unsigned int	arm_cpu_l2_0_status;
+	unsigned char	res34[0x18];
+	unsigned int	arm_cpu_l2_1_configuration;
+	unsigned int	arm_cpu_l2_1_status;
+	unsigned char	res35[0xa00];
+	unsigned int	pad_retention_maudio_option;
+	unsigned char	res36[0xdc];
+	unsigned int	pad_retention_gpio_option;
+	unsigned char	res37[0x1c];
+	unsigned int	pad_retention_uart_option;
+	unsigned char	res38[0x1c];
+	unsigned int	pad_retention_mmca_option;
+	unsigned char	res39[0x1c];
+	unsigned int	pad_retention_mmcb_option;
+	unsigned char	res40[0x1c];
+	unsigned int	pad_retention_ebia_option;
+	unsigned char	res41[0x1c];
+	unsigned int	pad_retention_ebib_option;
+	unsigned char	res42[0x160];
+	unsigned int	ps_hold_control;
+	unsigned char	res43[0xf0];
+	unsigned int	xusbxti_configuration;
+	unsigned int	xusbxti_status;
+	unsigned char	res44[0x14];
+	unsigned int	xusbxti_duration;
+	unsigned int	xxti_configuration;
+	unsigned int	xxti_status;
+	unsigned char	res45[0x14];
+	unsigned int	xxti_duration;
+	unsigned char	res46[0x1dc];
+	unsigned int	ext_regulator_duration;
+	unsigned char	res47[0x5e0];
+	unsigned int	cam_configuration;
+	unsigned int	cam_status;
+	unsigned int	cam_option;
+	unsigned char	res48[0x14];
+	unsigned int	tv_configuration;
+	unsigned int	tv_status;
+	unsigned int	tv_option;
+	unsigned char	res49[0x14];
+	unsigned int	mfc_configuration;
+	unsigned int	mfc_status;
+	unsigned int	mfc_option;
+	unsigned char	res50[0x14];
+	unsigned int	g3d_configuration;
+	unsigned int	g3d_status;
+	unsigned int	g3d_option;
+	unsigned char	res51[0x14];
+	unsigned int	lcd0_configuration;
+	unsigned int	lcd0_status;
+	unsigned int	lcd0_option;
+	unsigned char	res52[0x14];
+	unsigned int	lcd1_configuration;
+	unsigned int	lcd1_status;
+	unsigned int	lcd1_option;
+	unsigned char	res53[0x34];
+	unsigned int	gps_configuration;
+	unsigned int	gps_status;
+	unsigned int	gps_option;
+	unsigned char	res54[0x14];
+	unsigned int	gps_alive_configuration;
+	unsigned int	gps_alive_status;
+	unsigned int	gps_alive_option;
+};
+
+struct exynos5_power {
+	unsigned int	om_stat;
+	unsigned char	res1[0x18];
+	unsigned int	rtc_clko_sel;
+	unsigned int	gnss_rtc_out_ctrl;
+	unsigned char	res2[0x1dc];
+	unsigned int	central_seq_configuration;
+	unsigned int	central_seq_status;
+	unsigned int	central_seq_option;
+	unsigned char	res3[0x14];
+	unsigned int	seq_transition0;
+	unsigned int	seq_transition1;
+	unsigned int	seq_transition2;
+	unsigned int	seq_transition3;
+	unsigned int	seq_transition4;
+	unsigned int	seq_transition5;
+	unsigned int	seq_transition6;
+	unsigned int	seq_transition7;
+	unsigned int	central_seq_dmc_configuration;
+	unsigned int	central_seq_dmc_status;
+	unsigned int	central_seq_dmc_option;
+	unsigned char	res4[0x14];
+	unsigned int	seq_dmc_transition0;
+	unsigned int	seq_dmc_transition1;
+	unsigned int	seq_dmc_transition2;
+	unsigned int	seq_dmc_transition3;
+	unsigned int	seq_dmc_transition4;
+	unsigned int	seq_dmc_transition5;
+	unsigned int	seq_dmc_transition6;
+	unsigned int	seq_dmc_transition7;
+	unsigned char	res5[0x180];
+	unsigned int	swreset;
+	unsigned int	rst_stat;
+	unsigned int	automatic_wdt_reset_disable;
+	unsigned int	mask_wdt_reset_request;
+	unsigned int	mask_wreset_request;
+	unsigned char	res6[0xec];
+	unsigned int	reset_sequencer_configuration;
+	unsigned int	reset_sequencer_status;
+	unsigned int	reset_sequencer_option;
+	unsigned char	res7[0xf4];
+	unsigned int	wakeup_stat;
+	unsigned int	eint_wakeup_mask;
+	unsigned int	wakeup_mask;
+	unsigned int	wakeup_interrupt;
+	unsigned char	res8[0x10];
+	unsigned int	wakeup_stat_dmc;
+	unsigned int	eint_wakeup_mask_dmc;
+	unsigned int	wakeup_mask_dmc;
+	unsigned int	wakeup_interrupt_dmc;
+	unsigned char	res9[0xd0];
+	unsigned int	hdmi_phy_control;
+	unsigned int	usbdrd_phy_control;
+	unsigned int	usbhost_phy_control;
+	unsigned int	efnand_phy_control;
+	unsigned int	mipi_phy0_control;
+	unsigned int	mipi_phy1_control;
+	unsigned int	adc_phy_control;
+	unsigned int	mtcadc_phy_control;
+	unsigned int	dptx_phy_control;
+	unsigned int	sata_phy_control;
+	unsigned char	res10[0xd8];
+	unsigned int	inform0;
+	unsigned int	inform1;
+	unsigned int	inform2;
+	unsigned int	inform3;
+	unsigned int	sysip_dat0;
+	unsigned int	sysip_dat1;
+	unsigned int	sysip_dat2;
+	unsigned int	sysip_dat3;
+	unsigned char	res11[0xe0];
+	unsigned int	pmu_spare0;
+	unsigned int	pmu_spare1;
+	unsigned int	pmu_spare2;
+	unsigned int	pmu_spare3;
+	unsigned char	res12[0x70];
+	unsigned int	irom_data_reg0;
+	unsigned int	irom_data_reg1;
+	unsigned int	irom_data_reg2;
+	unsigned int	irom_data_reg3;
+	unsigned char	res13[0x70];
+	unsigned int	pmu_debug;
+	unsigned char	res14[0x5fc];
+	unsigned int	arm_core0_sys_pwr_reg;
+	unsigned int	dis_irq_arm_core0_local_sys_pwr_reg;
+	unsigned int	dis_irq_arm_core0_central_sys_pwr_reg;
+	unsigned char	res15[0x4];
+	unsigned int	arm_core1_sys_pwr_reg;
+	unsigned int	dis_irq_arm_core1_local_sys_pwr_reg;
+	unsigned int	dis_irq_arm_core1_central_sys_pwr_reg;
+	unsigned char	res16[0x24];
+	unsigned int	fsys_arm_sys_pwr_reg;
+	unsigned int	dis_irq_fsys_arm_local_sys_pwr_reg;
+	unsigned int	dis_irq_fsys_arm_central_sys_pwr_reg;
+	unsigned char	res17[0x4];
+	unsigned int	isp_arm_sys_pwr_reg;
+	unsigned int	dis_irq_isp_arm_local_sys_pwr_reg;
+	unsigned int	dis_irq_isp_arm_central_sys_pwr_reg;
+	unsigned char	res18[0x24];
+	unsigned int	arm_common_sys_pwr_reg;
+	unsigned char	res19[0x3c];
+	unsigned int	arm_l2_sys_pwr_reg;
+	unsigned char	res20[0x3c];
+	unsigned int	cmu_aclkstop_sys_pwr_reg;
+	unsigned int	cmu_sclkstop_sys_pwr_reg;
+	unsigned char	res21[0x4];
+	unsigned int	cmu_reset_sys_pwr_reg;
+	unsigned char	res22[0x10];
+	unsigned int	cmu_aclkstop_dmc_sys_pwr_reg;
+	unsigned int	cmu_sclkstop_dmc_sys_pwr_reg;
+	unsigned char	res23[0x4];
+	unsigned int	cmu_reset_dmc_sys_pwr_reg;
+	unsigned char	res24[0x8];
+	unsigned int	ddrphy_dlllock_sys_pwr_reg;
+	unsigned char	res25[0x4];
+	unsigned int	apll_sysclk_sys_pwr_reg;
+	unsigned int	mpll_sysclk_sys_pwr_reg;
+	unsigned int	vpll_sysclk_sys_pwr_reg;
+	unsigned int	epll_sysclk_sys_pwr_reg;
+	unsigned int	bpll_sysclk_sys_pwr_reg;
+	unsigned int	cpll_sysclk_sys_pwr_reg;
+	unsigned int	gpll_sysclk_sys_pwr_reg;
+	unsigned char	res26[0x8];
+	unsigned int	mplluser_sysclk_sys_pwr_reg;
+	unsigned char	res27[0x8];
+	unsigned int	bplluser_sysclk_sys_pwr_reg;
+	unsigned char	res28[0xc];
+	unsigned int	top_bus_sys_pwr_reg;
+	unsigned int	top_retention_sys_pwr_reg;
+	unsigned int	top_pwr_sys_pwr_reg;
+	unsigned char	res29[0x4];
+	unsigned int	top_bus_dmc_sys_pwr_reg;
+	unsigned int	top_retention_dmc_sys_pwr_reg;
+	unsigned int	top_pwr_dmc_sys_pwr_reg;
+	unsigned char	res30[0x4];
+	unsigned int	logic_reset_sys_pwr_reg;
+	unsigned int	oscclk_gate_sys_pwr_reg;
+	unsigned char	res31[0x8];
+	unsigned int	logic_reset_dmc_sys_pwr_reg;
+	unsigned int	oscclk_gate_dmc_sys_pwr_reg;
+	unsigned char	res32[0x8];
+	unsigned int	usbotg_mem_sys_pwr_reg;
+	unsigned char	res33[0x4];
+	unsigned int	g2d_mem_sys_pwr_reg;
+	unsigned int	usbdrd_mem_sys_pwr_reg;
+	unsigned int	efnand_mem_sys_pwr_reg;
+	unsigned int	cssys_mem_sys_pwr_reg;
+	unsigned int	secss_mem_sys_pwr_reg;
+	unsigned int	rotator_mem_sys_pwr_reg;
+	unsigned int	intram_mem_sys_pwr_reg;
+	unsigned int	introm_mem_sys_pwr_reg;
+	unsigned int	jpeg_mem_sys_pwr_reg;
+	unsigned int	hsi_mem_sys_pwr_reg;
+	unsigned char	res34[0x4];
+	unsigned int	mcuiop_mem_sys_pwr_reg;
+	unsigned char	res35[0x4];
+	unsigned int	sata_mem_sys_pwr_reg;
+	unsigned int	pad_retention_dram_sys_pwr_reg;
+	unsigned int	pad_retention_mau_sys_pwr_reg;
+	unsigned int	pad_retention_jtag_sys_pwr_reg;
+	unsigned char	res36[0xc];
+	unsigned int	pad_retention_mmc2_sys_pwr_reg;
+	unsigned int	pad_retention_mmc3_sys_pwr_reg;
+	unsigned int	pad_retention_gpio_sys_pwr_reg;
+	unsigned int	pad_retention_uart_sys_pwr_reg;
+	unsigned int	pad_retention_mmc0_sys_pwr_reg;
+	unsigned int	pad_retention_mmc1_sys_pwr_reg;
+	unsigned int	pad_retention_ebia_sys_pwr_reg;
+	unsigned int	pad_retention_ebib_sys_pwr_reg;
+	unsigned int	pad_retention_spi_sys_pwr_reg;
+	unsigned int	pad_retention_gpio_dmc_sys_pwr_reg;
+	unsigned int	pad_isolation_sys_pwr_reg;
+	unsigned char	res37[0xc];
+	unsigned int	pad_isolation_dmc_sys_pwr_reg;
+	unsigned char	res38[0xc];
+	unsigned int	pad_alv_sel_sys_pwr_reg;
+	unsigned char	res39[0x20];
+	unsigned int	xxti_sys_pwr_reg;
+	unsigned char	res40[0x38];
+	unsigned int	ext_regulator_sys_pwr_reg;
+	unsigned char	res41[0x3c];
+	unsigned int	gpio_mode_sys_pwr_reg;
+	unsigned char	res42[0x1c];
+	unsigned int	gpio_mode_dmc_sys_pwr_reg;
+	unsigned char	res43[0x1c];
+	unsigned int	gpio_mode_mau_sys_pwr_reg;
+	unsigned int	top_asb_reset_sys_pwr_reg;
+	unsigned int	top_asb_isolation_sys_pwr_reg;
+	unsigned char	res44[0xb4];
+	unsigned int	gscl_sys_pwr_reg;
+	unsigned int	isp_sys_pwr_reg;
+	unsigned int	mfc_sys_pwr_reg;
+	unsigned int	g3d_sys_pwr_reg;
+	unsigned char	res45[0x4];
+	unsigned int	disp1_sys_pwr_reg;
+	unsigned int	mau_sys_pwr_reg;
+	unsigned char	res46[0x64];
+	unsigned int	cmu_clkstop_gscl_sys_pwr_reg;
+	unsigned int	cmu_clkstop_isp_sys_pwr_reg;
+	unsigned int	cmu_clkstop_mfc_sys_pwr_reg;
+	unsigned int	cmu_clkstop_g3d_sys_pwr_reg;
+	unsigned char	res47[0x4];
+	unsigned int	cmu_clkstop_disp1_sys_pwr_reg;
+	unsigned int	cmu_clkstop_mau_sys_pwr_reg;
+	unsigned char	res48[0x24];
+	unsigned int	cmu_sysclk_gscl_sys_pwr_reg;
+	unsigned int	cmu_sysclk_isp_sys_pwr_reg;
+	unsigned int	cmu_sysclk_mfc_sys_pwr_reg;
+	unsigned int	cmu_sysclk_g3d_sys_pwr_reg;
+	unsigned char	res49[0x4];
+	unsigned int	cmu_sysclk_disp1_sys_pwr_reg;
+	unsigned int	cmu_sysclk_mau_sys_pwr_reg;
+	unsigned char	res50[0xa4];
+	unsigned int	cmu_reset_gscl_sys_pwr_reg;
+	unsigned int	cmu_reset_isp_sys_pwr_reg;
+	unsigned int	cmu_reset_mfc_sys_pwr_reg;
+	unsigned int	cmu_reset_g3d_sys_pwr_reg;
+	unsigned char	res51[0x4];
+	unsigned int	cmu_reset_disp1_sys_pwr_reg;
+	unsigned int	cmu_reset_mau_sys_pwr_reg;
+	unsigned char	res52[0xa64];
+	unsigned int	arm_core0_configuration;
+	unsigned int	arm_core0_status;
+	unsigned int	arm_core0_option;
+	unsigned char	res53[0x14];
+	unsigned int	dis_irq_arm_core0_local_configuration;
+	unsigned int	dis_irq_arm_core0_local_status;
+	unsigned int	dis_irq_arm_core0_local_option;
+	unsigned char	res54[0x14];
+	unsigned int	dis_irq_arm_core0_central_configuration;
+	unsigned int	dis_irq_arm_core0_central_status;
+	unsigned int	dis_irq_arm_core0_central_option;
+	unsigned char	res55[0x34];
+	unsigned int	arm_core1_configuration;
+	unsigned int	arm_core1_status;
+	unsigned int	arm_core1_option;
+	unsigned char	res56[0x14];
+	unsigned int	dis_irq_arm_core1_local_configuration;
+	unsigned int	dis_irq_arm_core1_local_status;
+	unsigned int	dis_irq_arm_core1_local_option;
+	unsigned char	res57[0x14];
+	unsigned int	dis_irq_arm_core1_central_configuration;
+	unsigned int	dis_irq_arm_core1_central_status;
+	unsigned int	dis_irq_arm_core1_central_option;
+	unsigned char	res58[0x134];
+	unsigned int	fsys_arm_configuration;
+	unsigned int	fsys_arm_status;
+	unsigned int	fsys_arm_option;
+	unsigned char	res59[0x14];
+	unsigned int	dis_irq_fsys_arm_local_configuration;
+	unsigned int	dis_irq_fsys_arm_local_status;
+	unsigned int	dis_irq_fsys_arm_local_option;
+	unsigned char	res60[0x14];
+	unsigned int	dis_irq_fsys_arm_central_configuration;
+	unsigned int	dis_irq_fsys_arm_central_status;
+	unsigned int	dis_irq_fsys_arm_central_option;
+	unsigned char	res61[0x34];
+	unsigned int	isp_arm_configuration;
+	unsigned int	isp_arm_status;
+	unsigned int	isp_arm_option;
+	unsigned char	res62[0x14];
+	unsigned int	dis_irq_isp_arm_local_configuration;
+	unsigned int	dis_irq_isp_arm_local_status;
+	unsigned int	dis_irq_isp_arm_local_option;
+	unsigned char	res63[0x14];
+	unsigned int	dis_irq_isp_arm_central_configuration;
+	unsigned int	dis_irq_isp_arm_central_status;
+	unsigned int	dis_irq_isp_arm_central_option;
+	unsigned char	res64[0x134];
+	unsigned int	arm_common_configuration;
+	unsigned int	arm_common_status;
+	unsigned int	arm_common_option;
+	unsigned char	res65[0x1f4];
+	unsigned int	arm_l2_configuration;
+	unsigned int	arm_l2_status;
+	unsigned int	arm_l2_option;
+	unsigned char	res66[0x1f4];
+	unsigned int	cmu_aclkstop_configuration;
+	unsigned int	cmu_aclkstop_status;
+	unsigned int	cmu_aclkstop_option;
+	unsigned char	res67[0x14];
+	unsigned int	cmu_sclkstop_configuration;
+	unsigned int	cmu_sclkstop_status;
+	unsigned int	cmu_sclkstop_option;
+	unsigned char	res68[0x34];
+	unsigned int	cmu_reset_configuration;
+	unsigned int	cmu_reset_status;
+	unsigned int	cmu_reset_option;
+	unsigned char	res69[0x94];
+	unsigned int	cmu_aclkstop_dmc_configuration;
+	unsigned int	cmu_aclkstop_dmc_status;
+	unsigned int	cmu_aclkstop_dmc_option;
+	unsigned char	res70[0x14];
+	unsigned int	cmu_sclkstop_dmc_configuration;
+	unsigned int	cmu_sclkstop_dmc_status;
+	unsigned int	cmu_sclkstop_dmc_option;
+	unsigned char	res71[0x34];
+	unsigned int	cmu_reset_dmc_configuration;
+	unsigned int	cmu_reset_dmc_status;
+	unsigned int	cmu_reset_dmc_option;
+	unsigned char	res72[0x54];
+	unsigned int	ddrphy_dlllock_configuration;
+	unsigned int	ddrphy_dlllock_status;
+	unsigned int	ddrphy_dlllock_option;
+	unsigned char	res73[0x34];
+	unsigned int	apll_sysclk_configuration;
+	unsigned int	apll_sysclk_status;
+	unsigned int	apll_sysclk_option;
+	unsigned char	res74[0x18];
+	unsigned int	mpll_sysclk_status;
+	unsigned int	mpll_sysclk_option;
+	unsigned char	res75[0x14];
+	unsigned int	vpll_sysclk_configuration;
+	unsigned int	vpll_sysclk_status;
+	unsigned int	vpll_sysclk_option;
+	unsigned char	res76[0x14];
+	unsigned int	epll_sysclk_configuration;
+	unsigned int	epll_sysclk_status;
+	unsigned int	epll_sysclk_option;
+	unsigned char	res77[0x14];
+	unsigned int	bpll_sysclk_configuration;
+	unsigned int	bpll_sysclk_status;
+	unsigned int	bpll_sysclk_option;
+	unsigned char	res78[0x14];
+	unsigned int	cpll_sysclk_configuration;
+	unsigned int	cpll_sysclk_status;
+	unsigned int	cpll_sysclk_option;
+	unsigned char	res79[0x14];
+	unsigned int	gpll_sysclk_configuration;
+	unsigned int	gpll_sysclk_status;
+	unsigned int	gpll_sysclk_option;
+	unsigned char	res80[0x54];
+	unsigned int	mplluser_sysclk_configuration;
+	unsigned int	mplluser_sysclk_status;
+	unsigned int	mplluser_sysclk_option;
+	unsigned char	res81[0x54];
+	unsigned int	bplluser_sysclk_configuration;
+	unsigned int	bplluser_sysclk_status;
+	unsigned int	bplluser_sysclk_option;
+	unsigned char	res82[0x74];
+	unsigned int	top_bus_configuration;
+	unsigned int	top_bus_status;
+	unsigned int	top_bus_option;
+	unsigned char	res83[0x14];
+	unsigned int	top_retention_configuration;
+	unsigned int	top_retention_status;
+	unsigned int	top_retention_option;
+	unsigned char	res84[0x14];
+	unsigned int	top_pwr_configuration;
+	unsigned int	top_pwr_status;
+	unsigned int	top_pwr_option;
+	unsigned char	res85[0x34];
+	unsigned int	top_bus_dmc_configuration;
+	unsigned int	top_bus_dmc_status;
+	unsigned int	top_bus_dmc_option;
+	unsigned char	res86[0x14];
+	unsigned int	top_retention_dmc_configuration;
+	unsigned int	top_retention_dmc_status;
+	unsigned int	top_retention_dmc_option;
+	unsigned char	res87[0x14];
+	unsigned int	top_pwr_dmc_configuration;
+	unsigned int	top_pwr_dmc_status;
+	unsigned int	top_pwr_dmc_option;
+	unsigned char	res88[0x34];
+	unsigned int	logic_reset_configuration;
+	unsigned int	logic_reset_status;
+	unsigned int	logic_reset_option;
+	unsigned char	res89[0x14];
+	unsigned int	oscclk_gate_configuration;
+	unsigned int	oscclk_gate_status;
+	unsigned int	oscclk_gate_option;
+	unsigned char	res90[0x54];
+	unsigned int	logic_reset_dmc_configuration;
+	unsigned int	logic_reset_dmc_status;
+	unsigned int	logic_reset_dmc_option;
+	unsigned char	res91[0x14];
+	unsigned int	oscclk_gate_dmc_configuration;
+	unsigned int	oscclk_gate_dmc_status;
+	unsigned int	oscclk_gate_dmc_option;
+	unsigned char	res92[0x54];
+	unsigned int	usbotg_mem_configuration;
+	unsigned int	usbotg_mem_status;
+	unsigned int	usbotg_mem_option;
+	unsigned char	res93[0x34];
+	unsigned int	g2d_mem_configuration;
+	unsigned int	g2d_mem_status;
+	unsigned int	g2d_mem_option;
+	unsigned char	res94[0x14];
+	unsigned int	usbdrd_mem_configuration;
+	unsigned int	usbdrd_mem_status;
+	unsigned int	usbdrd_mem_option;
+	unsigned char	res95[0x14];
+	unsigned int	efnand_mem_configuration;
+	unsigned int	efnand_mem_status;
+	unsigned int	efnand_mem_option;
+	unsigned char	res96[0x14];
+	unsigned int	cssys_mem_configuration;
+	unsigned int	cssys_mem_status;
+	unsigned int	cssys_mem_option;
+	unsigned char	res97[0x14];
+	unsigned int	secss_mem_configuration;
+	unsigned int	secss_mem_status;
+	unsigned int	secss_mem_option;
+	unsigned char	res98[0x14];
+	unsigned int	rotator_mem_configuration;
+	unsigned int	rotator_mem_status;
+	unsigned int	rotator_mem_option;
+	unsigned char	res99[0x14];
+	unsigned int	intram_mem_configuration;
+	unsigned int	intram_mem_status;
+	unsigned int	intram_mem_option;
+	unsigned char	res100[0x14];
+	unsigned int	introm_mem_configuration;
+	unsigned int	introm_mem_status;
+	unsigned int	introm_mem_option;
+	unsigned char	res101[0x14];
+	unsigned int	jpeg_mem_configuration;
+	unsigned int	jpeg_mem_status;
+	unsigned int	jpeg_mem_option;
+	unsigned char	res102[0x14];
+	unsigned int	hsi_mem_configuration;
+	unsigned int	hsi_mem_status;
+	unsigned int	hsi_mem_option;
+	unsigned char	res103[0x34];
+	unsigned int	mcuiop_mem_configuration;
+	unsigned int	mcuiop_mem_status;
+	unsigned int	mcuiop_mem_option;
+	unsigned char	res104[0x14];
+	unsigned int	sata_mem_configuration;
+	unsigned int	sata_mem_status;
+	unsigned int	sata_mem_option;
+	unsigned char	res105[0x34];
+	unsigned int	pad_retention_dram_configuration;
+	unsigned int	pad_retention_dram_status;
+	unsigned int	pad_retention_dram_option;
+	unsigned char	res106[0x14];
+	unsigned int	pad_retention_mau_configuration;
+	unsigned int	pad_retention_mau_status;
+	unsigned int	pad_retention_mau_option;
+	unsigned char	res107[0x14];
+	unsigned int	pad_retention_jtag_configuration;
+	unsigned int	pad_retention_jtag_status;
+	unsigned int	pad_retention_jtag_option;
+	unsigned char	res108[0x74];
+	unsigned int	pad_retention_mmc2_configuration;
+	unsigned int	pad_retention_mmc2_status;
+	unsigned int	pad_retention_mmc2_option;
+	unsigned char	res109[0x14];
+	unsigned int	pad_retention_mmc3_configuration;
+	unsigned int	pad_retention_mmc3_status;
+	unsigned int	pad_retention_mmc3_option;
+	unsigned char	res110[0x14];
+	unsigned int	pad_retention_gpio_configuration;
+	unsigned int	pad_retention_gpio_status;
+	unsigned int	pad_retention_gpio_option;
+	unsigned char	res111[0x14];
+	unsigned int	pad_retention_uart_configuration;
+	unsigned int	pad_retention_uart_status;
+	unsigned int	pad_retention_uart_option;
+	unsigned char	res112[0x14];
+	unsigned int	pad_retention_mmc0_configuration;
+	unsigned int	pad_retention_mmc0_status;
+	unsigned int	pad_retention_mmc0_option;
+	unsigned char	res113[0x14];
+	unsigned int	pad_retention_mmc1_configuration;
+	unsigned int	pad_retention_mmc1_status;
+	unsigned int	pad_retention_mmc1_option;
+	unsigned char	res114[0x14];
+	unsigned int	pad_retention_ebia_configuration;
+	unsigned int	pad_retention_ebia_status;
+	unsigned int	pad_retention_ebia_option;
+	unsigned char	res115[0x14];
+	unsigned int	pad_retention_ebib_configuration;
+	unsigned int	pad_retention_ebib_status;
+	unsigned int	pad_retention_ebib_option;
+	unsigned char	res116[0x14];
+	unsigned int	pad_retention_spi_configuration;
+	unsigned int	pad_retention_spi_status;
+	unsigned int	pad_retention_spi_option;
+	unsigned char	res117[0x14];
+	unsigned int	pad_retention_gpio_dmc_configuration;
+	unsigned int	pad_retention_gpio_dmc_status;
+	unsigned int	pad_retention_gpio_dmc_option;
+	unsigned char	res118[0x14];
+	unsigned int	pad_isolation_configuration;
+	unsigned int	pad_isolation_status;
+	unsigned int	pad_isolation_option;
+	unsigned char	res119[0x74];
+	unsigned int	pad_isolation_dmc_configuration;
+	unsigned int	pad_isolation_dmc_status;
+	unsigned int	pad_isolation_dmc_option;
+	unsigned char	res120[0x74];
+	unsigned int	pad_alv_sel_configuration;
+	unsigned int	pad_alv_sel_status;
+	unsigned int	pad_alv_sel_option0;
+	unsigned int	ps_hold_control;
+	unsigned char	res130[0x110];
+	unsigned int	xxti_configuration;
+	unsigned int	xxti_status;
+	unsigned int	xxti_option;
+	unsigned char	res131[0x10];
+	unsigned int	xxti_duration3;
+	unsigned char	res132[0x1c0];
+	unsigned int	ext_regulator_configuration;
+	unsigned int	ext_regulator_status;
+	unsigned int	ext_regulator_option;
+	unsigned char	res133[0x10];
+	unsigned int	ext_regulator_duration3;
+	unsigned char	res134[0x1e0];
+	unsigned int	gpio_mode_configuration;
+	unsigned int	gpio_mode_status;
+	unsigned int	gpio_mode_option;
+	unsigned char	res135[0xf4];
+	unsigned int	gpio_mode_dmc_configuration;
+	unsigned int	gpio_mode_dmc_status;
+	unsigned int	gpio_mode_dmc_option;
+	unsigned char	res136[0xd4];
+	unsigned int	gpio_mode_mau_configuration;
+	unsigned int	gpio_mode_mau_status;
+	unsigned int	gpio_mode_mau_option;
+	unsigned char	res137[0x14];
+	unsigned int	top_asb_reset_configuration;
+	unsigned int	top_asb_reset_status;
+	unsigned int	top_asb_reset_option;
+	unsigned char	res138[0x14];
+	unsigned int	top_asb_isolation_configuration;
+	unsigned int	top_asb_isolation_status;
+	unsigned int	top_asb_isolation_option;
+	unsigned char	res139[0x5d4];
+	unsigned int	gscl_configuration;
+	unsigned int	gscl_status;
+	unsigned int	gscl_option;
+	unsigned char	res140[0x14];
+	unsigned int	isp_configuration;
+	unsigned int	isp_status;
+	unsigned int	isp_option;
+	unsigned char	res141[0x14];
+	unsigned int	mfc_configuration;
+	unsigned int	mfc_status;
+	unsigned int	mfc_option;
+	unsigned char	res142[0x14];
+	unsigned int	g3d_configuration;
+	unsigned int	g3d_status;
+	unsigned int	g3d_option;
+	unsigned char	res143[0x34];
+	unsigned int	disp1_configuration;
+	unsigned int	disp1_status;
+	unsigned int	disp1_option;
+	unsigned char	res144[0x14];
+	unsigned int	mau_configuration;
+	unsigned int	mau_status;
+	unsigned int	mau_option;
+	unsigned char	res145[0x334];
+	unsigned int	cmu_clkstop_gscl_configuration;
+	unsigned int	cmu_clkstop_gscl_status;
+	unsigned int	cmu_clkstop_gscl_option;
+	unsigned char	res146[0x14];
+	unsigned int	cmu_clkstop_isp_configuration;
+	unsigned int	cmu_clkstop_isp_status;
+	unsigned int	cmu_clkstop_isp_option;
+	unsigned char	res147[0x14];
+	unsigned int	cmu_clkstop_mfc_configuration;
+	unsigned int	cmu_clkstop_mfc_status;
+	unsigned int	cmu_clkstop_mfc_option;
+	unsigned char	res148[0x14];
+	unsigned int	cmu_clkstop_g3d_configuration;
+	unsigned int	cmu_clkstop_g3d_status;
+	unsigned int	cmu_clkstop_g3d_option;
+	unsigned char	res149[0x34];
+	unsigned int	cmu_clkstop_disp1_configuration;
+	unsigned int	cmu_clkstop_disp1_status;
+	unsigned int	cmu_clkstop_disp1_option;
+	unsigned char	res150[0x14];
+	unsigned int	cmu_clkstop_mau_configuration;
+	unsigned int	cmu_clkstop_mau_status;
+	unsigned int	cmu_clkstop_mau_option;
+	unsigned char	res151[0x134];
+	unsigned int	cmu_sysclk_gscl_configuration;
+	unsigned int	cmu_sysclk_gscl_status;
+	unsigned int	cmu_sysclk_gscl_option;
+	unsigned char	res152[0x18];
+	unsigned int	cmu_sysclk_isp_status;
+	unsigned int	cmu_sysclk_isp_option;
+	unsigned char	res153[0x18];
+	unsigned int	cmu_sysclk_mfc_status;
+	unsigned int	cmu_sysclk_mfc_option;
+	unsigned char	res154[0x18];
+	unsigned int	cmu_sysclk_g3d_status;
+	unsigned int	cmu_sysclk_g3d_option;
+	unsigned char	res155[0x38];
+	unsigned int	cmu_sysclk_disp1_status;
+	unsigned int	cmu_sysclk_disp1_option;
+	unsigned char	res156[0x18];
+	unsigned int	cmu_sysclk_mau_status;
+	unsigned int	cmu_sysclk_mau_option;
+	unsigned char	res157[0x534];
+	unsigned int	cmu_reset_gscl_configuration;
+	unsigned int	cmu_reset_gscl_status;
+	unsigned int	cmu_reset_gscl_option;
+	unsigned char	res158[0x14];
+	unsigned int	cmu_reset_isp_configuration;
+	unsigned int	cmu_reset_isp_status;
+	unsigned int	cmu_reset_isp_option;
+	unsigned char	res159[0x14];
+	unsigned int	cmu_reset_mfc_configuration;
+	unsigned int	cmu_reset_mfc_status;
+	unsigned int	cmu_reset_mfc_option;
+	unsigned char	res160[0x14];
+	unsigned int	cmu_reset_g3d_configuration;
+	unsigned int	cmu_reset_g3d_status;
+	unsigned int	cmu_reset_g3d_option;
+	unsigned char	res161[0x34];
+	unsigned int	cmu_reset_disp1_configuration;
+	unsigned int	cmu_reset_disp1_status;
+	unsigned int	cmu_reset_disp1_option;
+	unsigned char	res162[0x14];
+	unsigned int	cmu_reset_mau_configuration;
+	unsigned int	cmu_reset_mau_status;
+	unsigned int	cmu_reset_mau_option;
+	unsigned char	res163[0x24];
+};
+
+struct exynos5420_power {
+	unsigned int	om_stat;
+	unsigned int	lpi_mask0;
+	unsigned int	lpi_mask1;
+	unsigned char	res1[0x10];
+	unsigned int	rtc_clko_sel;
+	unsigned char	res2[0x1e0];
+	unsigned int	central_seq_configuration;
+	unsigned int	central_seq_status;
+	unsigned int	central_seq_option;
+	unsigned char	res3[0x14];
+	unsigned int	seq_transition0;
+	unsigned int	seq_transition1;
+	unsigned int	seq_transition2;
+	unsigned int	seq_transition3;
+	unsigned int	seq_transition4;
+	unsigned int	seq_transition5;
+	unsigned int	seq_transition6;
+	unsigned int	seq_transition7;
+	unsigned int	central_seq_coreblk_configuration;
+	unsigned int	central_seq_coreblk_status;
+	unsigned int	central_seq_coreblk_option;
+	unsigned char	res4[0x14];
+	unsigned int	seq_coreblk_transition0;
+	unsigned int	seq_coreblk_transition1;
+	unsigned int	seq_coreblk_transition2;
+	unsigned int	seq_coreblk_transition3;
+	unsigned int	seq_coreblk_transition4;
+	unsigned int	seq_coreblk_transition5;
+	unsigned int	seq_coreblk_transition6;
+	unsigned int	seq_coreblk_transition7;
+	unsigned char	res5[0x180];
+	unsigned int	swreset;
+	unsigned int	rst_stat;
+	unsigned int	automatic_wdt_reset_disable;
+	unsigned int	mask_wdt_reset_request;
+	unsigned int	mask_wreset_request;
+	unsigned char	res6[0xec];
+	unsigned int	reset_sequencer_configuration;
+	unsigned int	reset_sequencer_status;
+	unsigned int	reset_sequencer_option;
+	unsigned char	res7[0xf4];
+	unsigned int	wakeup_stat;
+	unsigned int	eint_wakeup_mask;
+	unsigned int	wakeup_mask;
+	unsigned int	wakeup_interrupt;
+	unsigned char	res8[0x10];
+	unsigned int	wakeup_stat_coreblk;
+	unsigned int	eint_wakeup_mask_coreblk;
+	unsigned int	wakeup_mask_coreblk;
+	unsigned int	wakeup_interrupt_coreblk;
+	unsigned char	res9[0xd0];
+	unsigned int	hdmi_phy_control;
+	unsigned int	usbdev_phy_control;
+	unsigned int	usbdev1_phy_control;
+	unsigned int	usbhost_phy_control;
+	unsigned char	res104[0x4];
+	unsigned int	mipi_phy0_control;
+	unsigned int	mipi_phy1_control;
+	unsigned int	mipi_phy2_control;
+	unsigned int	adc_phy_control;
+	unsigned int	mtcadc_phy_control;
+	unsigned int	dptx_phy_control;
+	unsigned char	res10[0xd4];
+	unsigned int	inform0;
+	unsigned int	inform1;
+	unsigned int	inform2;
+	unsigned int	inform3;
+	unsigned int	sysip_dat0;
+	unsigned int	sysip_dat1;
+	unsigned int	sysip_dat2;
+	unsigned int	sysip_dat3;
+	unsigned char	res11[0xe0];
+	unsigned int	pmu_spare0;
+	unsigned int	pmu_spare1;
+	unsigned int	pmu_spare2;
+	unsigned int	pmu_spare3;
+	unsigned char	res12[0x4];
+	unsigned int	cg_status0;
+	unsigned int	cg_status1;
+	unsigned int	cg_status2;
+	unsigned int	cg_status3;
+	unsigned int	cg_status4;
+	unsigned char	res200[0x58];
+	unsigned int	irom_data_reg0;
+	unsigned int	irom_data_reg1;
+	unsigned int	irom_data_reg2;
+	unsigned int	irom_data_reg3;
+	unsigned char	res13[0x70];
+	unsigned int	pmu_debug;
+	unsigned char	res14[0x5fc];
+	unsigned int	arm_core0_sys_pwr_reg;
+	unsigned char	res500[0xc];
+	unsigned int	arm_core1_sys_pwr_reg;
+	unsigned char	res501[0xc];
+	unsigned int	arm_core2_sys_pwr_reg;
+	unsigned char	res502[0xc];
+	unsigned int	arm_core3_sys_pwr_reg;
+	unsigned char	res503[0xc];
+	unsigned int	kfc_core0_sys_pwr_reg;
+	unsigned char	res504[0xc];
+	unsigned int	kfc_core1_sys_pwr_reg;
+	unsigned char	res505[0xc];
+	unsigned int	kfc_core2_sys_pwr_reg;
+	unsigned char	res506[0xc];
+	unsigned int	kfc_core3_sys_pwr_reg;
+	unsigned char	res507[0x1c];
+	unsigned int	isp_arm_sys_pwr_reg;
+	unsigned char	res18[0xc];
+	unsigned int	arm_common_sys_pwr_reg;
+	unsigned char	res508[0xc];
+	unsigned int	kfc_common_sys_pwr_reg;
+	unsigned char	res19[0xc];
+	unsigned int	arm_l2_sys_pwr_reg;
+	unsigned char	res509[0xc];
+	unsigned int	kfc_l2_sys_pwr_reg;
+	unsigned char	res20[0xc];
+	unsigned int	cmu_cpu_aclkstop_sys_pwr_reg;
+	unsigned int	cmu_cpu_sclkstop_sys_pwr_reg;
+	unsigned char	res510[0x8];
+	unsigned int	cmu_kfc_aclkstop_sys_pwr_reg;
+	unsigned char	res511[0xc];
+	unsigned int	cmu_aclkstop_sys_pwr_reg;
+	unsigned int	cmu_sclkstop_sys_pwr_reg;
+	unsigned char	res21[0x4];
+	unsigned int	cmu_reset_sys_pwr_reg;
+	unsigned char	res22[0x10];
+	unsigned int	cmu_aclkstop_coreblk_sys_pwr_reg;
+	unsigned int	cmu_sclkstop_coreblk_sys_pwr_reg;
+	unsigned char	res23[0x4];
+	unsigned int	cmu_reset_coreblk_sys_pwr_reg;
+	unsigned int	dram_freq_down_sys_pwr_reg;
+	unsigned int	ddrphy_dlloff_sys_pwr_reg;
+	unsigned int	ddrphy_dlllock_sys_pwr_reg;
+	unsigned char	res25[0x4];
+	unsigned int	apll_sysclk_sys_pwr_reg;
+	unsigned int	mpll_sysclk_sys_pwr_reg;
+	unsigned int	vpll_sysclk_sys_pwr_reg;
+	unsigned int	epll_sysclk_sys_pwr_reg;
+	unsigned int	bpll_sysclk_sys_pwr_reg;
+	unsigned int	cpll_sysclk_sys_pwr_reg;
+	unsigned int	dpll_sysclk_sys_pwr_reg;
+	unsigned int	ipll_sysclk_sys_pwr_reg;
+	unsigned int	kpll_sysclk_sys_pwr_reg;
+	unsigned int	mplluser_sysclk_sys_pwr_reg;
+	unsigned char	res512[0x8];
+	unsigned int	bplluser_sysclk_sys_pwr_reg;
+	unsigned int	rpll_sysclk_sys_pwr_reg;
+	unsigned int	spll_sysclk_sys_pwr_reg;
+	unsigned char	res26[0x4];
+	unsigned int	top_bus_sys_pwr_reg;
+	unsigned int	top_retention_sys_pwr_reg;
+	unsigned int	top_pwr_sys_pwr_reg;
+	unsigned char	res29[0x4];
+	unsigned int	top_bus_coreblk_sys_pwr_reg;
+	unsigned int	top_retention_coreblk_sys_pwr_reg;
+	unsigned int	top_pwr_coreblk_sys_pwr_reg;
+	unsigned char	res30[0x4];
+	unsigned int	logic_reset_sys_pwr_reg;
+	unsigned int	oscclk_gate_sys_pwr_reg;
+	unsigned char	res31[0x8];
+	unsigned int	logic_reset_coreblk_sys_pwr_reg;
+	unsigned int	oscclk_gate_coreblk_sys_pwr_reg;
+	unsigned int	intram_mem_sys_pwr_reg;
+	unsigned int	introm_mem_sys_pwr_reg;
+	unsigned char	res32[0x44];
+	unsigned int	pad_retention_mau_sys_pwr_reg;
+	unsigned int	pad_retention_jtag_sys_pwr_reg;
+	unsigned char	res36[0x4];
+	unsigned int	pad_retention_dram_sys_pwr_reg;
+	unsigned int	pad_retention_uart_sys_pwr_reg;
+	unsigned int	pad_retention_mmca_sys_pwr_reg;
+	unsigned int	pad_retention_mmcb_sys_pwr_reg;
+	unsigned int	pad_retention_mmcc_sys_pwr_reg;
+	unsigned int	pad_retention_hsi_sys_pwr_reg;
+	unsigned int	pad_retention_ebia_sys_pwr_reg;
+	unsigned int	pad_retention_ebib_sys_pwr_reg;
+	unsigned int	pad_retention_spi_sys_pwr_reg;
+	unsigned int	pad_retention_dram_coreblk_sys_pwr_reg;
+	unsigned char	res28[0x8];
+	unsigned int	pad_isolation_sys_pwr_reg;
+	unsigned char	res37[0xc];
+	unsigned int	pad_isolation_coreblk_sys_pwr_reg;
+	unsigned char	res38[0xc];
+	unsigned int	pad_alv_sel_sys_pwr_reg;
+	unsigned char	res39[0x1c];
+	unsigned int	xusbxti_sys_pwr_reg;
+	unsigned int	xxti_sys_pwr_reg;
+	unsigned char	res40[0x38];
+	unsigned int	ext_regulator_sys_pwr_reg;
+	unsigned char	res41[0x3c];
+	unsigned int	gpio_mode_sys_pwr_reg;
+	unsigned char	res42[0x1c];
+	unsigned int	gpio_mode_coreblk_sys_pwr_reg;
+	unsigned char	res43[0x1c];
+	unsigned int	gpio_mode_mau_sys_pwr_reg;
+	unsigned int	top_asb_reset_sys_pwr_reg;
+	unsigned int	top_asb_isolation_sys_pwr_reg;
+	unsigned char	res44[0xb4];
+	unsigned int	gscl_sys_pwr_reg;
+	unsigned int	isp_sys_pwr_reg;
+	unsigned int	mfc_sys_pwr_reg;
+	unsigned int	g3d_sys_pwr_reg;
+	unsigned int	disp1_sys_pwr_reg;
+	unsigned int	mau_sys_pwr_reg;
+	unsigned int	g2d_sys_pwr_reg;
+	unsigned int	msc_sys_pwr_reg;
+	unsigned int	fsys_sys_pwr_reg;
+	unsigned int	fsys2_sys_pwr_reg;
+	unsigned int	psgen_sys_pwr_reg;
+	unsigned int	peric_sys_pwr_reg;
+	unsigned int	wcore_sys_pwr_reg;
+	unsigned char	res46[0x4c];
+	unsigned int	cmu_clkstop_gscl_sys_pwr_reg;
+	unsigned int	cmu_clkstop_isp_sys_pwr_reg;
+	unsigned int	cmu_clkstop_mfc_sys_pwr_reg;
+	unsigned int	cmu_clkstop_g3d_sys_pwr_reg;
+	unsigned int	cmu_clkstop_disp1_sys_pwr_reg;
+	unsigned int	cmu_clkstop_mau_sys_pwr_reg;
+	unsigned int	cmu_clkstop_g2d_sys_pwr_reg;
+	unsigned int	cmu_clkstop_msc_sys_pwr_reg;
+	unsigned int	cmu_clkstop_fsys_sys_pwr_reg;
+	unsigned int	cmu_clkstop_fsys2_sys_pwr_reg;
+	unsigned int	cmu_clkstop_psgen_sys_pwr_reg;
+	unsigned int	cmu_clkstop_peric_sys_pwr_reg;
+	unsigned int	cmu_clkstop_wcore_sys_pwr_reg;
+	unsigned char	res48[0x8];
+	unsigned int	cmu_sysclk_toppwr_sys_pwr_reg;
+	unsigned int	cmu_sysclk_gscl_sys_pwr_reg;
+	unsigned int	cmu_sysclk_isp_sys_pwr_reg;
+	unsigned int	cmu_sysclk_mfc_sys_pwr_reg;
+	unsigned int	cmu_sysclk_g3d_sys_pwr_reg;
+	unsigned int	cmu_sysclk_disp1_sys_pwr_reg;
+	unsigned int	cmu_sysclk_mau_sys_pwr_reg;
+	unsigned int	cmu_sysclk_g2d_sys_pwr_reg;
+	unsigned int	cmu_sysclk_msc_sys_pwr_reg;
+	unsigned int	cmu_sysclk_fsys_sys_pwr_reg;
+	unsigned int	cmu_sysclk_fsys2_sys_pwr_reg;
+	unsigned int	cmu_sysclk_psgen_sys_pwr_reg;
+	unsigned int	cmu_sysclk_peric_sys_pwr_reg;
+	unsigned int	cmu_sysclk_wcore_sys_pwr_reg;
+	unsigned int	cmu_sysclk_coreblk_toppwr_sys_pwr_reg;
+	unsigned char	res50[0x78];
+	unsigned int	cmu_reset_fsys2_sys_pwr_reg;
+	unsigned int	cmu_reset_psgen_sys_pwr_reg;
+	unsigned int	cmu_reset_peric_sys_pwr_reg;
+	unsigned int	cmu_reset_wcore_sys_pwr_reg;
+	unsigned int	cmu_reset_gscl_sys_pwr_reg;
+	unsigned int	cmu_reset_isp_sys_pwr_reg;
+	unsigned int	cmu_reset_mfc_sys_pwr_reg;
+	unsigned int	cmu_reset_g3d_sys_pwr_reg;
+	unsigned int	cmu_reset_disp1_sys_pwr_reg;
+	unsigned int	cmu_reset_mau_sys_pwr_reg;
+	unsigned int	cmu_reset_g2d_sys_pwr_reg;
+	unsigned int	cmu_reset_msc_sys_pwr_reg;
+	unsigned int	cmu_reset_fsys_sys_pwr_reg;
+	unsigned char	res52[0xa5c];
+	unsigned int	arm_core0_configuration;
+	unsigned int	arm_core0_status;
+	unsigned int	arm_core0_option;
+	unsigned char	res53[0x14];
+	unsigned int	dis_irq_arm_core0_local_configuration;
+	unsigned int	dis_irq_arm_core0_local_status;
+	unsigned int	dis_irq_arm_core0_local_option;
+	unsigned char	res54[0x14];
+	unsigned int	dis_irq_arm_core0_central_configuration;
+	unsigned int	dis_irq_arm_core0_central_status;
+	unsigned int	dis_irq_arm_core0_central_option;
+	unsigned char	res55[0x34];
+	unsigned int	arm_core1_configuration;
+	unsigned int	arm_core1_status;
+	unsigned int	arm_core1_option;
+	unsigned char	res56[0x14];
+	unsigned int	dis_irq_arm_core1_local_configuration;
+	unsigned int	dis_irq_arm_core1_local_status;
+	unsigned int	dis_irq_arm_core1_local_option;
+	unsigned char	res57[0x14];
+	unsigned int	dis_irq_arm_core1_central_configuration;
+	unsigned int	dis_irq_arm_core1_central_status;
+	unsigned int	dis_irq_arm_core1_central_option;
+	unsigned char	res600[0x34];
+	unsigned int	arm_core2_configuration;
+	unsigned int	arm_core2_status;
+	unsigned int	arm_core2_option;
+	unsigned char	res601[0x14];
+	unsigned int	dis_irq_arm_core2_local_configuration;
+	unsigned int	dis_irq_arm_core2_local_status;
+	unsigned int	dis_irq_arm_core2_local_option;
+	unsigned char	res602[0x14];
+	unsigned int	dis_irq_arm_core2_central_configuration;
+	unsigned int	dis_irq_arm_core2_central_status;
+	unsigned int	dis_irq_arm_core2_central_option;
+	unsigned char	res603[0x34];
+	unsigned int	arm_core3_configuration;
+	unsigned int	arm_core3_status;
+	unsigned int	arm_core3_option;
+	unsigned char	res900[0x14];
+	unsigned int	dis_irq_arm_core3_local_configuration;
+	unsigned int	dis_irq_arm_core3_local_status;
+	unsigned int	dis_irq_arm_core3_local_option;
+	unsigned char	res901[0x14];
+	unsigned int	dis_irq_arm_core3_central_configuration;
+	unsigned int	dis_irq_arm_core3_central_status;
+	unsigned int	dis_irq_arm_core3_central_option;
+	unsigned char	res604[0x34];
+	unsigned int	kfc_core0_configuration;
+	unsigned int	kfc_core0_status;
+	unsigned int	kfc_core0_option;
+	unsigned char	res605[0x14];
+	unsigned int	dis_irq_kfc_core0_local_configuration;
+	unsigned int	dis_irq_kfc_core0_local_status;
+	unsigned int	dis_irq_kfc_core0_local_option;
+	unsigned char	res606[0x14];
+	unsigned int	dis_irq_kfc_core0_central_configuration;
+	unsigned int	dis_irq_kfc_core0_central_status;
+	unsigned int	dis_irq_kfc_core0_central_option;
+	unsigned char	res607[0x34];
+	unsigned int	kfc_core1_configuration;
+	unsigned int	kfc_core1_status;
+	unsigned int	kfc_core1_option;
+	unsigned char	res608[0x14];
+	unsigned int	dis_irq_kfc_core1_local_configuration;
+	unsigned int	dis_irq_kfc_core1_local_status;
+	unsigned int	dis_irq_kfc_core1_local_option;
+	unsigned char	res609[0x14];
+	unsigned int	dis_irq_kfc_core1_central_configuration;
+	unsigned int	dis_irq_kfc_core1_central_status;
+	unsigned int	dis_irq_kfc_core1_central_option;
+	unsigned char	res610[0x34];
+	unsigned int	kfc_core2_configuration;
+	unsigned int	kfc_core2_status;
+	unsigned int	kfc_core2_option;
+	unsigned char	res611[0x14];
+	unsigned int	dis_irq_kfc_core2_local_configuration;
+	unsigned int	dis_irq_kfc_core2_local_status;
+	unsigned int	dis_irq_kfc_core2_local_option;
+	unsigned char	res612[0x14];
+	unsigned int	dis_irq_kfc_core2_central_configuration;
+	unsigned int	dis_irq_kfc_core2_central_status;
+	unsigned int	dis_irq_kfc_core2_central_option;
+	unsigned char	res613[0x34];
+	unsigned int	kfc_core3_configuration;
+	unsigned int	kfc_core3_status;
+	unsigned int	kfc_core3_option;
+	unsigned char	res614[0x14];
+	unsigned int	dis_irq_kfc_core3_local_configuration;
+	unsigned int	dis_irq_kfc_core3_local_status;
+	unsigned int	dis_irq_kfc_core3_local_option;
+	unsigned char	res615[0x14];
+	unsigned int	dis_irq_kfc_core3_central_configuration;
+	unsigned int	dis_irq_kfc_core3_central_status;
+	unsigned int	dis_irq_kfc_core3_central_option;
+	unsigned char	res61[0xb4];
+	unsigned int	isp_arm_configuration;
+	unsigned int	isp_arm_status;
+	unsigned int	isp_arm_option;
+	unsigned char	res62[0x14];
+	unsigned int	dis_irq_isp_arm_local_configuration;
+	unsigned int	dis_irq_isp_arm_local_status;
+	unsigned int	dis_irq_isp_arm_local_option;
+	unsigned char	res63[0x14];
+	unsigned int	dis_irq_isp_arm_central_configuration;
+	unsigned int	dis_irq_isp_arm_central_status;
+	unsigned int	dis_irq_isp_arm_central_option;
+	unsigned char	res64[0x34];
+	unsigned int	arm_common_configuration;
+	unsigned int	arm_common_status;
+	unsigned int	arm_common_option;
+	unsigned char	res616[0x74];
+	unsigned int	kfc_common_configuration;
+	unsigned int	kfc_common_status;
+	unsigned int	kfc_common_option;
+	unsigned char	res65[0x74];
+	unsigned int	arm_l2_configuration;
+	unsigned int	arm_l2_status;
+	unsigned int	arm_l2_option;
+	unsigned char	res617[0x74];
+	unsigned int	kfc_l2_configuration;
+	unsigned int	kfc_l2_status;
+	unsigned int	kfc_l2_option;
+	unsigned char	res66[0x74];
+	unsigned int	cmu_cpu_aclkstop_configuration;
+	unsigned int	cmu_cpu_aclkstop_status;
+	unsigned int	cmu_cpu_aclkstop_option;
+	unsigned char	res67[0x14];
+	unsigned int	cmu_cpu_sclkstop_configuration;
+	unsigned int	cmu_cpu_sclkstop_status;
+	unsigned int	cmu_cpu_sclkstop_option;
+	unsigned char	res618[0x4];
+	unsigned int	cmu_kfc_aclkstop_configuration;
+	unsigned int	cmu_kfc_aclkstop_status;
+	unsigned int	cmu_kfc_aclkstop_option;
+	unsigned char	res619[0xc4];
+	unsigned int	cmu_aclkstop_configuration;
+	unsigned int	cmu_aclkstop_status;
+	unsigned int	cmu_aclkstop_option;
+	unsigned char	res620[0x14];
+	unsigned int	cmu_sclkstop_configuration;
+	unsigned int	cmu_sclkstop_status;
+	unsigned int	cmu_sclkstop_option;
+	unsigned char	res68[0x34];
+	unsigned int	cmu_reset_configuration;
+	unsigned int	cmu_reset_status;
+	unsigned int	cmu_reset_option;
+	unsigned char	res69[0x94];
+	unsigned int	cmu_aclkstop_coreblk_configuration;
+	unsigned int	cmu_aclkstop_coreblk_status;
+	unsigned int	cmu_aclkstop_coreblk_option;
+	unsigned char	res70[0x14];
+	unsigned int	cmu_sclkstop_coreblk_configuration;
+	unsigned int	cmu_sclkstop_coreblk_status;
+	unsigned int	cmu_sclkstop_coreblk_option;
+	unsigned char	res71[0x34];
+	unsigned int	cmu_reset_coreblk_configuration;
+	unsigned int	cmu_reset_coreblk_status;
+	unsigned int	cmu_reset_coreblk_option;
+	unsigned char	res621[0x14];
+	unsigned int	dram_freq_down_configuration;
+	unsigned int	dram_freq_down_status;
+	unsigned int	dram_freq_down_option;
+	unsigned char	res622[0x14];
+	unsigned int	ddrphy_dlloff_configuration;
+	unsigned int	ddrphy_dlloff_status;
+	unsigned int	ddrphy_dlloff_option;
+	unsigned char	res72[0x14];
+	unsigned int	ddrphy_dlllock_configuration;
+	unsigned int	ddrphy_dlllock_status;
+	unsigned int	ddrphy_dlllock_option;
+	unsigned char	res73[0x34];
+	unsigned int	apll_sysclk_configuration;
+	unsigned int	apll_sysclk_status;
+	unsigned int	apll_sysclk_option;
+	unsigned char	res74[0x18];
+	unsigned int	mpll_sysclk_status;
+	unsigned int	mpll_sysclk_option;
+	unsigned char	res75[0x14];
+	unsigned int	vpll_sysclk_configuration;
+	unsigned int	vpll_sysclk_status;
+	unsigned int	vpll_sysclk_option;
+	unsigned char	res76[0x14];
+	unsigned int	epll_sysclk_configuration;
+	unsigned int	epll_sysclk_status;
+	unsigned int	epll_sysclk_option;
+	unsigned char	res77[0x14];
+	unsigned int	bpll_sysclk_configuration;
+	unsigned int	bpll_sysclk_status;
+	unsigned int	bpll_sysclk_option;
+	unsigned char	res78[0x14];
+	unsigned int	cpll_sysclk_configuration;
+	unsigned int	cpll_sysclk_status;
+	unsigned int	cpll_sysclk_option;
+	unsigned char	res79[0x14];
+	unsigned int	dpll_sysclk_configuration;
+	unsigned int	dpll_sysclk_status;
+	unsigned int	dpll_sysclk_option;
+	unsigned char	res700[0x14];
+	unsigned int	ipll_sysclk_configuration;
+	unsigned int	ipll_sysclk_status;
+	unsigned int	ipll_sysclk_option;
+	unsigned char	res903[0x14];
+	unsigned int	kpll_sysclk_configuration;
+	unsigned int	kpll_sysclk_status;
+	unsigned int	kpll_sysclk_option;
+	unsigned char	res80[0x14];
+	unsigned int	mplluser_sysclk_configuration;
+	unsigned int	mplluser_sysclk_status;
+	unsigned int	mplluser_sysclk_option;
+	unsigned char	res81[0x54];
+	unsigned int	bplluser_sysclk_configuration;
+	unsigned int	bplluser_sysclk_status;
+	unsigned int	bplluser_sysclk_option;
+	unsigned char	res701[0x14];
+	unsigned int	rplluser_sysclk_configuration;
+	unsigned int	rplluser_sysclk_status;
+	unsigned int	rplluser_sysclk_option;
+	unsigned char	res702[0x14];
+	unsigned int	splluser_sysclk_configuration;
+	unsigned int	splluser_sysclk_status;
+	unsigned int	splluser_sysclk_option;
+	unsigned char	res82[0x34];
+	unsigned int	top_bus_configuration;
+	unsigned int	top_bus_status;
+	unsigned int	top_bus_option;
+	unsigned char	res83[0x14];
+	unsigned int	top_retention_configuration;
+	unsigned int	top_retention_status;
+	unsigned int	top_retention_option;
+	unsigned char	res84[0x14];
+	unsigned int	top_pwr_configuration;
+	unsigned int	top_pwr_status;
+	unsigned int	top_pwr_option;
+	unsigned char	res85[0x34];
+	unsigned int	top_bus_coreblk_configuration;
+	unsigned int	top_bus_coreblk_status;
+	unsigned int	top_bus_coreblk_option;
+	unsigned char	res86[0x14];
+	unsigned int	top_retention_coreblk_configuration;
+	unsigned int	top_retention_coreblk_status;
+	unsigned int	top_retention_coreblk_option;
+	unsigned char	res87[0x14];
+	unsigned int	top_pwr_coreblk_configuration;
+	unsigned int	top_pwr_coreblk_status;
+	unsigned int	top_pwr_coreblk_option;
+	unsigned char	res88[0x34];
+	unsigned int	logic_reset_configuration;
+	unsigned int	logic_reset_status;
+	unsigned int	logic_reset_option;
+	unsigned char	res89[0x14];
+	unsigned int	oscclk_gate_configuration;
+	unsigned int	oscclk_gate_status;
+	unsigned int	oscclk_gate_option;
+	unsigned char	res90[0x54];
+	unsigned int	logic_reset_coreblk_configuration;
+	unsigned int	logic_reset_coreblk_status;
+	unsigned int	logic_reset_coreblk_option;
+	unsigned char	res91[0x14];
+	unsigned int	oscclk_gate_coreblk_configuration;
+	unsigned int	oscclk_gate_coreblk_status;
+	unsigned int	oscclk_gate_coreblk_option;
+	unsigned char	res99[0x174];
+	unsigned int	intram_mem_configuration;
+	unsigned int	intram_mem_status;
+	unsigned int	intram_mem_option;
+	unsigned char	res100[0x14];
+	unsigned int	introm_mem_configuration;
+	unsigned int	introm_mem_status;
+	unsigned int	introm_mem_option;
+	unsigned char	res101[0xb4];
+	unsigned int	pad_retention_dram_configuration;
+	unsigned int	pad_retention_dram_status;
+	unsigned int	pad_retention_dram_option;
+	unsigned char	res106[0x14];
+	unsigned int	pad_retention_mau_configuration;
+	unsigned int	pad_retention_mau_status;
+	unsigned int	pad_retention_mau_option;
+	unsigned char	res107[0x14];
+	unsigned int	pad_retention_jtag_configuration;
+	unsigned int	pad_retention_jtag_status;
+	unsigned int	pad_retention_jtag_option;
+	unsigned char	res92[0x74];
+	unsigned int	pad_retention_dram_configuration_2;
+	unsigned int	pad_retention_dram_status_2;
+	unsigned int	pad_retention_dram_option_2;
+	unsigned char	res111[0x14];
+	unsigned int	pad_retention_uart_configuration;
+	unsigned int	pad_retention_uart_status;
+	unsigned int	pad_retention_uart_option;
+	unsigned char	res112[0x14];
+	unsigned int	pad_retention_mmca_configuration;
+	unsigned int	pad_retention_mmca_status;
+	unsigned int	pad_retention_mmca_option;
+	unsigned char	res113[0x14];
+	unsigned int	pad_retention_mmcb_configuration;
+	unsigned int	pad_retention_mmcb_status;
+	unsigned int	pad_retention_mmcb_option;
+	unsigned char	res93[0x14];
+	unsigned int	pad_retention_mmcc_configuration;
+	unsigned int	pad_retention_mmcc_status;
+	unsigned int	pad_retention_mmcc_option;
+	unsigned char	res94[0x14];
+	unsigned int	pad_retention_hsi_configuration;
+	unsigned int	pad_retention_hsi_status;
+	unsigned int	pad_retention_hsi_option;
+	unsigned char	res114[0x14];
+	unsigned int	pad_retention_ebia_configuration;
+	unsigned int	pad_retention_ebia_status;
+	unsigned int	pad_retention_ebia_option;
+	unsigned char	res115[0x14];
+	unsigned int	pad_retention_ebib_configuration;
+	unsigned int	pad_retention_ebib_status;
+	unsigned int	pad_retention_ebib_option;
+	unsigned char	res116[0x14];
+	unsigned int	pad_retention_spi_configuration;
+	unsigned int	pad_retention_spi_status;
+	unsigned int	pad_retention_spi_option;
+	unsigned char	res117[0x14];
+	unsigned int	pad_retention_dram_coreblk_configuration;
+	unsigned int	pad_retention_dram_coreblk_status;
+	unsigned int	pad_retention_dram_coreblk_option;
+	unsigned char	res118[0x14];
+	unsigned int	pad_isolation_configuration;
+	unsigned int	pad_isolation_status;
+	unsigned int	pad_isolation_option;
+	unsigned char	res119[0x74];
+	unsigned int	pad_isolation_coreblk_configuration;
+	unsigned int	pad_isolation_coreblk_status;
+	unsigned int	pad_isolation_coreblk_option;
+	unsigned char	res120[0x74];
+	unsigned int	pad_alv_sel_configuration;
+	unsigned int	pad_alv_sel_status;
+	unsigned int	pad_alv_sel_option0;
+	unsigned int	ps_hold_control;
+	unsigned char	res130[0xf0];
+	unsigned int	xusbxti_configuration;
+	unsigned int	xusbxti_status;
+	unsigned int	xusbxti_option;
+	unsigned char	res910[0x10];
+	unsigned int	xusbxti_duration3;
+	unsigned int	xxti_configuration;
+	unsigned int	xxti_status;
+	unsigned int	xxti_option;
+	unsigned char	res131[0x10];
+	unsigned int	xxti_duration3;
+	unsigned char	res132[0x1c0];
+	unsigned int	ext_regulator_configuration;
+	unsigned int	ext_regulator_status;
+	unsigned int	ext_regulator_option;
+	unsigned char	res133[0x10];
+	unsigned int	ext_regulator_duration3;
+	unsigned char	res134[0x1e0];
+	unsigned int	gpio_mode_configuration;
+	unsigned int	gpio_mode_status;
+	unsigned int	gpio_mode_option;
+	unsigned char	res135[0xf4];
+	unsigned int	gpio_mode_coreblk_configuration;
+	unsigned int	gpio_mode_coreblk_status;
+	unsigned int	gpio_mode_coreblk_option;
+	unsigned char	res136[0xd4];
+	unsigned int	gpio_mode_mau_configuration;
+	unsigned int	gpio_mode_mau_status;
+	unsigned int	gpio_mode_mau_option;
+	unsigned char	res137[0x14];
+	unsigned int	top_asb_reset_configuration;
+	unsigned int	top_asb_reset_status;
+	unsigned int	top_asb_reset_option;
+	unsigned char	res138[0x14];
+	unsigned int	top_asb_isolation_configuration;
+	unsigned int	top_asb_isolation_status;
+	unsigned int	top_asb_isolation_option;
+	unsigned char	res139[0x5d4];
+	unsigned int	gscl_configuration;
+	unsigned int	gscl_status;
+	unsigned int	gscl_option;
+	unsigned char	res140[0x14];
+	unsigned int	isp_configuration;
+	unsigned int	isp_status;
+	unsigned int	isp_option;
+	unsigned char	res141[0x34];
+	unsigned int	mfc_configuration;
+	unsigned int	mfc_status;
+	unsigned int	mfc_option;
+	unsigned char	res142[0x14];
+	unsigned int	g3d_configuration;
+	unsigned int	g3d_status;
+	unsigned int	g3d_option;
+	unsigned char	res143[0x34];
+	unsigned int	disp1_configuration;
+	unsigned int	disp1_status;
+	unsigned int	disp1_option;
+	unsigned char	res144[0x14];
+	unsigned int	mau_configuration;
+	unsigned int	mau_status;
+	unsigned int	mau_option;
+	unsigned char	res800[0x14];
+	unsigned int	g2d_configuration;
+	unsigned int	g2d_status;
+	unsigned int	g2d_option;
+	unsigned char	res801[0x14];
+	unsigned int	msc_configuration;
+	unsigned int	msc_status;
+	unsigned int	msc_option;
+	unsigned char	res802[0x14];
+	unsigned int	fsys_configuration;
+	unsigned int	fsys_status;
+	unsigned int	fsys_option;
+	unsigned char	res803[0x14];
+	unsigned int	fsys2_configuration;
+	unsigned int	fsys2_status;
+	unsigned int	fsys2_option;
+	unsigned char	res804[0x14];
+	unsigned int	psgen_configuration;
+	unsigned int	psgen_status;
+	unsigned int	psgen_option;
+	unsigned char	res805[0x14];
+	unsigned int	peric_configuration;
+	unsigned int	peric_status;
+	unsigned int	peric_option;
+	unsigned char	res806[0x14];
+	unsigned int	wcore_configuration;
+	unsigned int	wcore_status;
+	unsigned int	wcore_option;
+	unsigned char	res145[0x234];
+	unsigned int	cmu_clkstop_gscl_configuration;
+	unsigned int	cmu_clkstop_gscl_status;
+	unsigned int	cmu_clkstop_gscl_option;
+	unsigned char	res146[0x14];
+	unsigned int	cmu_clkstop_isp_configuration;
+	unsigned int	cmu_clkstop_isp_status;
+	unsigned int	cmu_clkstop_isp_option;
+	unsigned char	res147[0x34];
+	unsigned int	cmu_clkstop_mfc_configuration;
+	unsigned int	cmu_clkstop_mfc_status;
+	unsigned int	cmu_clkstop_mfc_option;
+	unsigned char	res148[0x14];
+	unsigned int	cmu_clkstop_g3d_configuration;
+	unsigned int	cmu_clkstop_g3d_status;
+	unsigned int	cmu_clkstop_g3d_option;
+	unsigned char	res149[0x34];
+	unsigned int	cmu_clkstop_disp1_configuration;
+	unsigned int	cmu_clkstop_disp1_status;
+	unsigned int	cmu_clkstop_disp1_option;
+	unsigned char	res150[0x14];
+	unsigned int	cmu_clkstop_mau_configuration;
+	unsigned int	cmu_clkstop_mau_status;
+	unsigned int	cmu_clkstop_mau_option;
+	unsigned char	res807[0x14];
+	unsigned int	cmu_clkstop_g2d_configuration;
+	unsigned int	cmu_clkstop_g2d_status;
+	unsigned int	cmu_clkstop_g2d_option;
+	unsigned char	res808[0x14];
+	unsigned int	cmu_clkstop_msc_configuration;
+	unsigned int	cmu_clkstop_msc_status;
+	unsigned int	cmu_clkstop_msc_option;
+	unsigned char	res809[0x14];
+	unsigned int	cmu_clkstop_fsys_configuration;
+	unsigned int	cmu_clkstop_fsys_status;
+	unsigned int	cmu_clkstop_fsys_option;
+	unsigned char	res810[0x14];
+	unsigned int	cmu_clkstop_fsys2_configuration;
+	unsigned int	cmu_clkstop_fsys2_status;
+	unsigned int	cmu_clkstop_fsys2_option;
+	unsigned char	res811[0x14];
+	unsigned int	cmu_clkstop_psgen_configuration;
+	unsigned int	cmu_clkstop_psgen_status;
+	unsigned int	cmu_clkstop_psgen_option;
+	unsigned char	res812[0x14];
+	unsigned int	cmu_clkstop_peric_configuration;
+	unsigned int	cmu_clkstop_peric_status;
+	unsigned int	cmu_clkstop_peric_option;
+	unsigned char	res813[0x14];
+	unsigned int	cmu_clkstop_wcore_configuration;
+	unsigned int	cmu_clkstop_wcore_status;
+	unsigned int	cmu_clkstop_wcore_option;
+	unsigned char	res151[0x14];
+	unsigned int	cmu_sysclk_toppwr_configuration;
+	unsigned int	cmu_sysclk_toppwr_status;
+	unsigned int	cmu_sysclk_toppwr_option;
+	unsigned char	res920[0x18];
+	unsigned int	cmu_sysclk_gscl_status;
+	unsigned int	cmu_sysclk_gscl_option;
+	unsigned char	res152[0x18];
+	unsigned int	cmu_sysclk_isp_status;
+	unsigned int	cmu_sysclk_isp_option;
+	unsigned char	res153[0x38];
+	unsigned int	cmu_sysclk_mfc_status;
+	unsigned int	cmu_sysclk_mfc_option;
+	unsigned char	res154[0x18];
+	unsigned int	cmu_sysclk_g3d_status;
+	unsigned int	cmu_sysclk_g3d_option;
+	unsigned char	res155[0x38];
+	unsigned int	cmu_sysclk_disp1_status;
+	unsigned int	cmu_sysclk_disp1_option;
+	unsigned char	res156[0x18];
+	unsigned int	cmu_sysclk_mau_status;
+	unsigned int	cmu_sysclk_mau_option;
+	unsigned char	res814[0x18];
+	unsigned int	cmu_sysclk_g2d_status;
+	unsigned int	cmu_sysclk_g2d_option;
+	unsigned char	res815[0x18];
+	unsigned int	cmu_sysclk_msc_status;
+	unsigned int	cmu_sysclk_msc_option;
+	unsigned char	res922[0x18];
+	unsigned int	cmu_sysclk_fsys_status;
+	unsigned int	cmu_sysclk_fsys_option;
+	unsigned char	res816[0x18];
+	unsigned int	cmu_sysclk_fsys2_status;
+	unsigned int	cmu_sysclk_fsys2_option;
+	unsigned char	res817[0x18];
+	unsigned int	cmu_sysclk_psgen_status;
+	unsigned int	cmu_sysclk_psgen_option;
+	unsigned char	res950[0x18];
+	unsigned int	cmu_sysclk_peric_status;
+	unsigned int	cmu_sysclk_peric_option;
+	unsigned char	res818[0x18];
+	unsigned int	cmu_sysclk_wcore_status;
+	unsigned int	cmu_sysclk_wcore_option;
+	unsigned char	res819[0x18];
+	unsigned int	cmu_sysclk_coreblk_toppwr_status;
+	unsigned int	cmu_sysclk_coreblk_toppwr_option;
+	unsigned char	res157[0x414];
+	unsigned int	cmu_reset_gscl_configuration;
+	unsigned int	cmu_reset_gscl_status;
+	unsigned int	cmu_reset_gscl_option;
+	unsigned char	res158[0x14];
+	unsigned int	cmu_reset_isp_configuration;
+	unsigned int	cmu_reset_isp_status;
+	unsigned int	cmu_reset_isp_option;
+	unsigned char	res159[0x34];
+	unsigned int	cmu_reset_mfc_configuration;
+	unsigned int	cmu_reset_mfc_status;
+	unsigned int	cmu_reset_mfc_option;
+	unsigned char	res160[0x14];
+	unsigned int	cmu_reset_g3d_configuration;
+	unsigned int	cmu_reset_g3d_status;
+	unsigned int	cmu_reset_g3d_option;
+	unsigned char	res161[0x34];
+	unsigned int	cmu_reset_disp1_configuration;
+	unsigned int	cmu_reset_disp1_status;
+	unsigned int	cmu_reset_disp1_option;
+	unsigned char	res162[0x14];
+	unsigned int	cmu_reset_mau_configuration;
+	unsigned int	cmu_reset_mau_status;
+	unsigned int	cmu_reset_mau_option;
+	unsigned char	res163[0x14];
+	unsigned int	version_info;
+	unsigned int	i2s_bypass;
+	unsigned int	kfc_swreset_mask_from_eagle;
+	unsigned char	res164[0xf4];
+	unsigned int	cmu_reset_g2d_configuration;
+	unsigned int	cmu_reset_g2d_status;
+	unsigned int	cmu_reset_g2d_option;
+	unsigned char	res165[0x14];
+	unsigned int	cmu_reset_msc_configuration;
+	unsigned int	cmu_reset_msc_status;
+	unsigned int	cmu_reset_msc_option;
+	unsigned char	res166[0x14];
+	unsigned int	cmu_reset_fsys_configuration;
+	unsigned int	cmu_reset_fsys_status;
+	unsigned int	cmu_reset_fsys_option;
+	unsigned char	res167[0x14];
+	unsigned int	cmu_reset_fsys2_configuration;
+	unsigned int	cmu_reset_fsys2_status;
+	unsigned int	cmu_reset_fsys2_option;
+	unsigned char	res168[0x14];
+	unsigned int	cmu_reset_psgen_configuration;
+	unsigned int	cmu_reset_psgen_status;
+	unsigned int	cmu_reset_psgen_option;
+	unsigned char	res169[0x14];
+	unsigned int	cmu_reset_peric_configuration;
+	unsigned int	cmu_reset_peric_status;
+	unsigned int	cmu_reset_peric_option;
+	unsigned char	res170[0x14];
+	unsigned int	cmu_reset_wcore_configuration;
+	unsigned int	cmu_reset_wcore_status;
+	unsigned int	cmu_reset_wcore_option;
+};
+#endif	/* __ASSEMBLY__ */
+
+void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
+
+#define EXYNOS_MIPI_PHY_ENABLE		(1 << 0)
+#define EXYNOS_MIPI_PHY_SRESETN		(1 << 1)
+#define EXYNOS_MIPI_PHY_MRESETN		(1 << 2)
+
+void set_usbhost_phy_ctrl(unsigned int enable);
+
+/* Enables hardware tripping to power off the system when TMU fails */
+void set_hw_thermal_trip(void);
+
+#define POWER_USB_HOST_PHY_CTRL_EN		(1 << 0)
+#define POWER_USB_HOST_PHY_CTRL_DISABLE		(0 << 0)
+
+void set_usbdrd_phy_ctrl(unsigned int enable);
+
+#define POWER_USB_DRD_PHY_CTRL_EN		(1 << 0)
+#define POWER_USB_DRD_PHY_CTRL_DISABLE		(0 << 0)
+
+void set_dp_phy_ctrl(unsigned int enable);
+
+#define EXYNOS_DP_PHY_ENABLE		(1 << 0)
+
+#define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH	(1 << 8)
+#define POWER_ENABLE_HW_TRIP			(1UL << 31)
+
+/*
+ * Set ps_hold data driving value high
+ * This enables the machine to stay powered on
+ * after the initial power-on condition goes away
+ * (e.g. power button).
+ */
+void set_ps_hold_ctrl(void);
+
+/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */
+#define PMU_DEBUG_XXTI                          0x1000
+/* Mask bit[12:8] for xxti clock selection */
+#define PMU_DEBUG_CLKOUT_SEL_MASK               0x1f00
+
+/*
+ * Pmu debug is used for xclkout, enable xclkout with
+ * source as XXTI
+ */
+void set_xclkout(void);
+
+/*
+ *  Read inform1 to get the reset status.
+ *  @return: the value can be either S5P_CHECK_SLEEP or
+ *  S5P_CHECK_DIDLE or S5P_CHECK_LPA as stored in inform1
+ *  if none of these then its normal booting.
+ */
+uint32_t get_reset_status(void);
+
+
+/* Read the resume function and call it */
+void power_exit_wakeup(void);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm.h
new file mode 100644
index 000000000..43474c34b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+#define PRESCALER_0		(8 - 1)		/* prescaler of timer 0, 1 */
+#define PRESCALER_1		(16 - 1)	/* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1		0		/* 1/1 period */
+#define MUX_DIV_2		1		/* 1/2 period */
+#define MUX_DIV_4		2		/* 1/4 period */
+#define MUX_DIV_8		3		/* 1/8 period */
+#define MUX_DIV_16		4		/* 1/16 period */
+
+#define MUX_DIV_SHIFT(x)	(x * 4)
+
+#define TCON_OFFSET(x)		((x + 1) * (!!x) << 2)
+
+#define TCON_START(x)		(1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x)		(1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x)	(1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x)	(1 << (TCON_OFFSET(x) + 3))
+#define TCON4_AUTO_RELOAD	(1 << 22)
+
+#ifndef __ASSEMBLY__
+struct s5p_timer {
+	unsigned int	tcfg0;
+	unsigned int	tcfg1;
+	unsigned int	tcon;
+	unsigned int	tcntb0;
+	unsigned int	tcmpb0;
+	unsigned int	tcnto0;
+	unsigned int	tcntb1;
+	unsigned int	tcmpb1;
+	unsigned int	tcnto1;
+	unsigned int	tcntb2;
+	unsigned int	tcmpb2;
+	unsigned int	tcnto2;
+	unsigned int	tcntb3;
+	unsigned int	tcmpb3;
+	unsigned int	tcnto3;
+	unsigned int	tcntb4;
+	unsigned int	tcnto4;
+	unsigned int	tintcstat;
+};
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm_backlight.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm_backlight.h
new file mode 100644
index 000000000..4f54fa737
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/pwm_backlight.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PWM_BACKLIGHT_H_
+#define _PWM_BACKLIGHT_H_
+
+struct pwm_backlight_data {
+	int pwm_id;
+	int period;
+	int max_brightness;
+	int brightness;
+};
+
+extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd);
+
+#endif /* _PWM_BACKLIGHT_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sound.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sound.h
new file mode 100644
index 000000000..bff57c691
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sound.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __SOUND_ARCH_H__
+#define __SOUND_ARCH_H__
+
+/* I2S values */
+#define I2S_PLL_CLK		192000000
+#define I2S_SAMPLING_RATE	48000
+#define I2S_BITS_PER_SAMPLE	16
+#define I2S_CHANNELS		2
+#define I2S_RFS			256
+#define I2S_BFS			32
+
+/* I2C values */
+#define AUDIO_I2C_BUS		1
+#define AUDIO_I2C_REG		0x1a
+
+/* Audio Codec */
+#define AUDIO_CODEC		"wm8994"
+
+#define AUDIO_COMPAT		1
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spi.h
new file mode 100644
index 000000000..0ba931b7e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spi.h
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Padmavathi Venna <padma.v@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+
+#ifndef __ASSEMBLY__
+
+/* SPI peripheral register map; padded to 64KB */
+struct exynos_spi {
+	unsigned int		ch_cfg;		/* 0x00 */
+	unsigned char		reserved0[4];
+	unsigned int		mode_cfg;	/* 0x08 */
+	unsigned int		cs_reg;		/* 0x0c */
+	unsigned char		reserved1[4];
+	unsigned int		spi_sts;	/* 0x14 */
+	unsigned int		tx_data;	/* 0x18 */
+	unsigned int		rx_data;	/* 0x1c */
+	unsigned int		pkt_cnt;	/* 0x20 */
+	unsigned char		reserved2[4];
+	unsigned int		swap_cfg;	/* 0x28 */
+	unsigned int		fb_clk;		/* 0x2c */
+	unsigned char		padding[0xffd0];
+};
+
+#define EXYNOS_SPI_MAX_FREQ	50000000
+
+#define SPI_TIMEOUT_MS		10
+#define SF_READ_DATA_CMD	0x3
+
+/* SPI_CHCFG */
+#define SPI_CH_HS_EN		(1 << 6)
+#define SPI_CH_RST		(1 << 5)
+#define SPI_SLAVE_MODE		(1 << 4)
+#define SPI_CH_CPOL_L		(1 << 3)
+#define SPI_CH_CPHA_B		(1 << 2)
+#define SPI_RX_CH_ON		(1 << 1)
+#define SPI_TX_CH_ON		(1 << 0)
+
+/* SPI_MODECFG */
+#define SPI_MODE_CH_WIDTH_WORD	(0x2 << 29)
+#define SPI_MODE_BUS_WIDTH_WORD	(0x2 << 17)
+
+/* SPI_CSREG */
+#define SPI_SLAVE_SIG_INACT	(1 << 0)
+
+/* SPI_STS */
+#define SPI_ST_TX_DONE		(1 << 25)
+#define SPI_FIFO_LVL_MASK	0x1ff
+#define SPI_TX_LVL_OFFSET	6
+#define SPI_RX_LVL_OFFSET	15
+
+/* Feedback Delay */
+#define SPI_CLK_BYPASS		(0 << 0)
+#define SPI_FB_DELAY_90		(1 << 0)
+#define SPI_FB_DELAY_180	(2 << 0)
+#define SPI_FB_DELAY_270	(3 << 0)
+
+/* Packet Count */
+#define SPI_PACKET_CNT_EN	(1 << 16)
+
+/* Swap config */
+#define SPI_TX_SWAP_EN		(1 << 0)
+#define SPI_TX_BYTE_SWAP	(1 << 2)
+#define SPI_TX_HWORD_SWAP	(1 << 3)
+#define SPI_TX_BYTE_SWAP	(1 << 2)
+#define SPI_RX_SWAP_EN		(1 << 4)
+#define SPI_RX_BYTE_SWAP	(1 << 6)
+#define SPI_RX_HWORD_SWAP	(1 << 7)
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spl.h
new file mode 100644
index 000000000..b1d68c3d2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/spl.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include <asm/arch-exynos/dmc.h>
+
+enum boot_mode {
+	/*
+	 * Assign the OM pin values for respective boot modes.
+	 * Exynos4 does not support spi boot and the mmc boot OM
+	 * pin values are the same across Exynos4 and Exynos5.
+	 */
+	BOOT_MODE_MMC = 4,
+	BOOT_MODE_EMMC = 8,     /* EMMC4.4 */
+	BOOT_MODE_SERIAL = 20,
+	/* Boot based on Operating Mode pin settings */
+	BOOT_MODE_OM = 32,
+	BOOT_MODE_USB,	/* Boot using USB download */
+};
+
+#ifndef __ASSEMBLY__
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+	/* Add fields as and when required */
+	u32		signature;
+	u32		version;	/* Version number */
+	u32		size;		/* Size of block */
+	/**
+	 * Parameters we expect, in order, terminated with \0. Each parameter
+	 * is a single character representing one 32-bit word in this
+	 * structure.
+	 *
+	 * Valid characters in this string are:
+	 *
+	 * Code		Name
+	 * v		mem_iv_size
+	 * m		mem_type
+	 * u		uboot_size
+	 * b		boot_source
+	 * f		frequency_mhz (memory frequency in MHz)
+	 * a		ARM clock frequency in MHz
+	 * s		serial base address
+	 * i		i2c base address for early access (meant for PMIC)
+	 * r		board rev GPIO numbers used to read board revision
+	 *			(lower halfword=bit 0, upper=bit 1)
+	 * M		Memory Manufacturer name
+	 * \0		termination
+	 */
+	char		params[12];	/* Length must be word-aligned */
+	u32		mem_iv_size;	/* Memory channel interleaving size */
+	enum ddr_mode	mem_type;	/* Type of on-board memory */
+	/*
+	 * U-boot size - The iROM mmc copy function used by the SPL takes a
+	 * block count paramter to describe the u-boot size unlike the spi
+	 * boot copy function which just uses the u-boot size directly. Align
+	 * the u-boot size to block size (512 bytes) when populating the SPL
+	 * table only for mmc boot.
+	 */
+	u32		uboot_size;
+	enum boot_mode	boot_source;	/* Boot device */
+	unsigned	frequency_mhz;	/* Frequency of memory in MHz */
+	unsigned	arm_freq_mhz;	/* ARM Frequency in MHz */
+	u32		serial_base;	/* Serial base address */
+	u32		i2c_base;	/* i2c base address */
+	u32		board_rev_gpios;	/* Board revision GPIOs */
+	enum mem_manuf	mem_manuf;	/* Memory Manufacturer */
+} __attribute__((__packed__));
+#endif
+
+/**
+ * Validate signature and return a pointer to the parameter table.  If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sromc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sromc.h
new file mode 100644
index 000000000..7f584033b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sromc.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Note: This file contains the register description for SROMC
+ */
+
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
+
+#define SROMC_DATA16_WIDTH(x)    (1<<((x*4)+0))
+#define SROMC_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/
+						/* 1-> Byte base address*/
+#define SROMC_WAIT_ENABLE(x)     (1<<((x*4)+2))
+#define SROMC_BYTE_ENABLE(x)     (1<<((x*4)+3))
+
+#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
+#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
+#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
+#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
+#define SROMC_BC_TAH(x)  (x << 8)  /* address holding time */
+#define SROMC_BC_TACP(x) (x << 4)  /* page mode access cycle */
+#define SROMC_BC_PMC(x)  (x << 0)  /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5p_sromc {
+	unsigned int	bw;
+	unsigned int	bc[4];
+};
+#endif	/* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+enum {
+	FDT_SROM_PMC,
+	FDT_SROM_TACP,
+	FDT_SROM_TAH,
+	FDT_SROM_TCOH,
+	FDT_SROM_TACC,
+	FDT_SROM_TCOS,
+	FDT_SROM_TACS,
+
+	FDT_SROM_TIMING_COUNT,
+};
+
+struct fdt_sromc {
+	u8 bank;	/* srom bank number */
+	u8 width;	/* bus width in bytes */
+	unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
+};
+
+#endif /* __ASM_ARCH_SROMC_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sys_proto.h
new file mode 100644
index 000000000..83ae42a74
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/sys_proto.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2010 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_device_type(void);
+void invalidate_dcache(u32);
+void l2_cache_disable(void);
+void l2_cache_enable(void);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/system.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/system.h
new file mode 100644
index 000000000..7e2057ca6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/system.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_SYSTEM_H_
+#define __ASM_ARM_ARCH_SYSTEM_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_sysreg {
+	unsigned char	res1[0x210];
+	unsigned int	display_ctrl;
+	unsigned int	display_ctrl2;
+	unsigned int	camera_control;
+	unsigned int	audio_endian;
+	unsigned int	jtag_con;
+};
+
+struct exynos5_sysreg {
+	unsigned char	res1[0x214];
+	unsigned int	disp1blk_cfg;
+	unsigned int	disp2blk_cfg;
+	unsigned int	hdcp_e_fuse;
+	unsigned int	gsclblk_cfg0;
+	unsigned int	gsclblk_cfg1;
+	unsigned int	reserved;
+	unsigned int	ispblk_cfg;
+	unsigned int	usb20phy_cfg;
+	unsigned char	res2[0x29c];
+	unsigned int	mipi_dphy;
+	unsigned int	dptx_dphy;
+	unsigned int	phyclk_sel;
+};
+#endif
+
+#define USB20_PHY_CFG_HOST_LINK_EN	(1 << 0)
+
+void set_usbhost_mode(unsigned int mode);
+void set_system_display_ctrl(void);
+
+#endif	/* _EXYNOS4_SYSTEM_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tmu.h
new file mode 100644
index 000000000..cad35694f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tmu.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *      http://www.samsung.com
+ * Akshay Saraswat <akshay.s@samsung.com>
+ *
+ * EXYNOS - Thermal Management Unit
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TMU_H
+#define __ASM_ARCH_TMU_H
+
+struct exynos5_tmu_reg {
+	u32 triminfo;
+	u32 rsvd1[4];
+	u32 triminfo_control;
+	u32 rsvd5[2];
+	u32 tmu_control;
+	u32 rsvd7;
+	u32 tmu_status;
+	u32 sampling_internal;
+	u32 counter_value0;
+	u32 counter_value1;
+	u32 rsvd8[2];
+	u32 current_temp;
+	u32 rsvd10[3];
+	u32 threshold_temp_rise;
+	u32 threshold_temp_fall;
+	u32 rsvd13[2];
+	u32 past_temp3_0;
+	u32 past_temp7_4;
+	u32 past_temp11_8;
+	u32 past_temp15_12;
+	u32 inten;
+	u32 intstat;
+	u32 intclear;
+	u32 rsvd15;
+	u32 emul_con;
+};
+#endif /* __ASM_ARCH_TMU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tzpc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tzpc.h
new file mode 100644
index 000000000..0a4be2391
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/tzpc.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TZPC_H_
+#define __TZPC_H_
+
+#ifndef __ASSEMBLY__
+struct exynos_tzpc {
+	unsigned int r0size;
+	char res1[0x7FC];
+	unsigned int decprot0stat;
+	unsigned int decprot0set;
+	unsigned int decprot0clr;
+	unsigned int decprot1stat;
+	unsigned int decprot1set;
+	unsigned int decprot1clr;
+	unsigned int decprot2stat;
+	unsigned int decprot2set;
+	unsigned int decprot2clr;
+	unsigned int decprot3stat;
+	unsigned int decprot3set;
+	unsigned int decprot3clr;
+	char res2[0x7B0];
+	unsigned int periphid0;
+	unsigned int periphid1;
+	unsigned int periphid2;
+	unsigned int periphid3;
+	unsigned int pcellid0;
+	unsigned int pcellid1;
+	unsigned int pcellid2;
+	unsigned int pcellid3;
+};
+
+#define EXYNOS4_NR_TZPC_BANKS		6
+#define EXYNOS5_NR_TZPC_BANKS		10
+
+/* TZPC : Register Offsets */
+#define TZPC_BASE_OFFSET		0x10000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE			0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET		0xFF
+void tzpc_init(void);
+
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/uart.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/uart.h
new file mode 100644
index 000000000..33d6ba3b6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/uart.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+/* baudrate rest value */
+union br_rest {
+	unsigned short	slot;		/* udivslot */
+	unsigned char	value;		/* ufracval */
+};
+
+struct s5p_uart {
+	unsigned int	ulcon;
+	unsigned int	ucon;
+	unsigned int	ufcon;
+	unsigned int	umcon;
+	unsigned int	utrstat;
+	unsigned int	uerstat;
+	unsigned int	ufstat;
+	unsigned int	umstat;
+	unsigned char	utxh;
+	unsigned char	res1[3];
+	unsigned char	urxh;
+	unsigned char	res2[3];
+	unsigned int	ubrdiv;
+	union br_rest	rest;
+	unsigned char	res3[0xffd0];
+};
+
+static inline int s5p_uart_divslot(void)
+{
+	return 0;
+}
+
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/watchdog.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/watchdog.h
new file mode 100644
index 000000000..eb6410906
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/watchdog.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_WATCHDOG_H_
+#define __ASM_ARM_ARCH_WATCHDOG_H_
+
+#define WTCON_RESET_OFFSET	0
+#define WTCON_INTEN_OFFSET	2
+#define WTCON_CLKSEL_OFFSET	3
+#define WTCON_EN_OFFSET		5
+#define WTCON_PRE_OFFSET	8
+
+#define WTCON_CLK_16		0x0
+#define WTCON_CLK_32		0x1
+#define WTCON_CLK_64		0x2
+#define WTCON_CLK_128		0x3
+
+#define WTCON_CLK(x)		((x & 0x3) << WTCON_CLKSEL_OFFSET)
+#define WTCON_PRESCALER(x)	((x) << WTCON_PRE_OFFSET)
+#define WTCON_EN		(0x1 << WTCON_EN_OFFSET)
+#define WTCON_RESET		(0x1 << WTCON_RESET_OFFSET)
+#define WTCON_INT		(0x1 << WTCON_INTEN_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct s5p_watchdog {
+	unsigned int wtcon;
+	unsigned int wtdat;
+	unsigned int wtcnt;
+	unsigned int wtclrint;
+};
+
+/* functions */
+void wdt_stop(void);
+void wdt_start(unsigned int timeout);
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/xhci-exynos.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/xhci-exynos.h
new file mode 100644
index 000000000..92b90a462
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-exynos/xhci-exynos.h
@@ -0,0 +1,88 @@
+/* Copyright (c) 2012 Samsung Electronics Co. Ltd
+ *
+ * Exynos Phy register definitions
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_EXYNOS_H_
+#define _ASM_ARCH_XHCI_EXYNOS_H_
+
+/* Phy register MACRO definitions */
+
+#define LINKSYSTEM_FLADJ_MASK			(0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x)			((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL		(0x1 << 27)
+
+#define PHYUTMI_OTGDISABLE			(1 << 6)
+#define PHYUTMI_FORCESUSPEND			(1 << 1)
+#define PHYUTMI_FORCESLEEP			(1 << 0)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK		(0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x)		((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK		(0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x)			((_x) << 21)
+
+#define PHYCLKRST_SSC_EN			(0x1 << 20)
+#define PHYCLKRST_REF_SSP_EN			(0x1 << 19)
+#define PHYCLKRST_REF_CLKDIV2			(0x1 << 18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK		(0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF	(0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF	(0x02 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF	(0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF	(0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF	(0x02 << 11)
+
+#define PHYCLKRST_FSEL_MASK			(0x3f << 5)
+#define PHYCLKRST_FSEL(_x)			((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ		(0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ		(0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ		(0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ		(0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN			(0x1 << 4)
+
+#define PHYCLKRST_REFCLKSEL_MASK		(0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK		(0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK		(0x3 << 2)
+
+#define PHYCLKRST_PORTRESET			(0x1 << 1)
+#define PHYCLKRST_COMMONONN			(0x1 << 0)
+
+#define PHYPARAM0_REF_USE_PAD			(0x1 << 31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK		(0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL			(0x9 << 26)
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK		(0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH			(0x1c)
+
+#define PHYTEST_POWERDOWN_SSP			(0x1 << 3)
+#define PHYTEST_POWERDOWN_HSP			(0x1 << 2)
+
+#define PHYBATCHG_UTMI_CLKSEL			(0x1 << 2)
+
+#define FSEL_CLKSEL_24M				(0x5)
+
+/* XHCI PHY register structure */
+struct exynos_usb3_phy {
+	unsigned int reserve1;
+	unsigned int link_system;
+	unsigned int phy_utmi;
+	unsigned int phy_pipe;
+	unsigned int phy_clk_rst;
+	unsigned int phy_reg0;
+	unsigned int phy_reg1;
+	unsigned int phy_param0;
+	unsigned int phy_param1;
+	unsigned int phy_term;
+	unsigned int phy_test;
+	unsigned int phy_adp;
+	unsigned int phy_batchg;
+	unsigned int phy_resume;
+	unsigned int reserve2[3];
+	unsigned int link_port;
+};
+
+#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h
new file mode 100644
index 000000000..a35940e64
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/cpu.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define MXC_CPU_MX51		0x51
+#define MXC_CPU_MX53		0x53
+#define MXC_CPU_MX6SL		0x60
+#define MXC_CPU_MX6DL		0x61
+#define MXC_CPU_MX6SOLO		0x62
+#define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6D		0x64
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/imx-regs.h
new file mode 100644
index 000000000..4de0779d2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-imx/imx-regs.h
@@ -0,0 +1,637 @@
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+
+#define ARCH_MXC
+
+/* ------------------------------------------------------------------------
+ *  Motorola IMX system registers
+ * ------------------------------------------------------------------------
+ *
+ */
+
+#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
+
+# ifndef __ASSEMBLY__
+# define __REG(x)	(*((volatile u32 *)IO_ADDRESS(x)))
+# define __REG2(x,y)        (*(volatile u32 *)((u32)&__REG(x) + (y)))
+# else
+#  define __REG(x) (x)
+#  define __REG2(x,y) ((x)+(y))
+#endif
+
+#define IMX_IO_BASE		0x00200000
+
+/*
+ *  Register BASEs, based on OFFSETs
+ *
+ */
+#define IMX_AIPI1_BASE             (0x00000 + IMX_IO_BASE)
+#define IMX_WDT_BASE               (0x01000 + IMX_IO_BASE)
+#define IMX_TIM1_BASE              (0x02000 + IMX_IO_BASE)
+#define IMX_TIM2_BASE              (0x03000 + IMX_IO_BASE)
+#define IMX_RTC_BASE               (0x04000 + IMX_IO_BASE)
+#define IMX_LCDC_BASE              (0x05000 + IMX_IO_BASE)
+#define IMX_UART1_BASE             (0x06000 + IMX_IO_BASE)
+#define IMX_UART2_BASE             (0x07000 + IMX_IO_BASE)
+#define IMX_PWM_BASE               (0x08000 + IMX_IO_BASE)
+#define IMX_DMAC_BASE              (0x09000 + IMX_IO_BASE)
+#define IMX_AIPI2_BASE             (0x10000 + IMX_IO_BASE)
+#define IMX_SIM_BASE               (0x11000 + IMX_IO_BASE)
+#define IMX_USBD_BASE              (0x12000 + IMX_IO_BASE)
+#define IMX_SPI1_BASE              (0x13000 + IMX_IO_BASE)
+#define IMX_MMC_BASE               (0x14000 + IMX_IO_BASE)
+#define IMX_ASP_BASE               (0x15000 + IMX_IO_BASE)
+#define IMX_BTA_BASE               (0x16000 + IMX_IO_BASE)
+#define IMX_I2C_BASE               (0x17000 + IMX_IO_BASE)
+#define IMX_SSI_BASE               (0x18000 + IMX_IO_BASE)
+#define IMX_SPI2_BASE              (0x19000 + IMX_IO_BASE)
+#define IMX_MSHC_BASE              (0x1A000 + IMX_IO_BASE)
+#define IMX_PLL_BASE               (0x1B000 + IMX_IO_BASE)
+#define IMX_SYSCTRL_BASE           (0x1B800 + IMX_IO_BASE)
+#define IMX_GPIO_BASE              (0x1C000 + IMX_IO_BASE)
+#define IMX_EIM_BASE               (0x20000 + IMX_IO_BASE)
+#define IMX_SDRAMC_BASE            (0x21000 + IMX_IO_BASE)
+#define IMX_MMA_BASE               (0x22000 + IMX_IO_BASE)
+#define IMX_AITC_BASE              (0x23000 + IMX_IO_BASE)
+#define IMX_CSI_BASE               (0x24000 + IMX_IO_BASE)
+
+/* Watchdog Registers*/
+
+#define WCR  __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
+#define WSR  __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
+#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register  */
+
+/* SYSCTRL Registers */
+#define SIDR   __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register		    */
+#define FMCR   __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
+#define GPCR   __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
+
+/* Chip Select Registers */
+#define CS0U __REG(IMX_EIM_BASE)        /* Chip Select 0 Upper Register */
+#define CS0L __REG(IMX_EIM_BASE + 0x4)  /* Chip Select 0 Lower Register */
+#define CS1U __REG(IMX_EIM_BASE + 0x8)  /* Chip Select 1 Upper Register */
+#define CS1L __REG(IMX_EIM_BASE + 0xc)  /* Chip Select 1 Lower Register */
+#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
+#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
+#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
+#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
+#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
+#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
+#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
+#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
+#define EIM  __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
+
+/* SDRAM controller registers */
+
+#define SDCTL0 __REG(IMX_SDRAMC_BASE)        /* SDRAM 0 Control Register */
+#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4)  /* SDRAM 1 Control Register */
+#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
+#define SDRST  __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
+
+/* PLL registers */
+#define CSCR   __REG(IMX_PLL_BASE)        /* Clock Source Control Register */
+#define CSCR_SPLL_RESTART	(1<<22)
+#define CSCR_MPLL_RESTART	(1<<21)
+#define CSCR_SYSTEM_SEL		(1<<16)
+#define CSCR_BCLK_DIV		(0xf<<10)
+#define CSCR_MPU_PRESC		(1<<15)
+#define CSCR_SPEN		(1<<1)
+#define CSCR_MPEN		(1<<0)
+
+#define MPCTL0 __REG(IMX_PLL_BASE + 0x4)  /* MCU PLL Control Register 0 */
+#define MPCTL1 __REG(IMX_PLL_BASE + 0x8)  /* MCU PLL and System Clock Register 1 */
+#define SPCTL0 __REG(IMX_PLL_BASE + 0xc)  /* System PLL Control Register 0 */
+#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
+#define PCDR   __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
+
+/*
+ *  GPIO Module and I/O Multiplexer
+ *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
+ */
+#define DDIR(x)    __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
+#define OCR1(x)    __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
+#define OCR2(x)    __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
+#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
+#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
+#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
+#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
+#define DR(x)      __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
+#define GIUS(x)    __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
+#define SSR(x)     __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
+#define ICR1(x)    __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
+#define ICR2(x)    __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
+#define IMR(x)     __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
+#define ISR(x)     __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
+#define GPR(x)     __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
+#define SWR(x)     __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
+#define PUEN(x)    __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
+
+#define GPIO_PORT_MAX  3
+
+#define GPIO_PIN_MASK 0x1f
+#define GPIO_PORT_MASK (0x3 << 5)
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORTA (0<<5)
+#define GPIO_PORTB (1<<5)
+#define GPIO_PORTC (2<<5)
+#define GPIO_PORTD (3<<5)
+
+#define GPIO_OUT   (1<<7)
+#define GPIO_IN    (0<<7)
+#define GPIO_PUEN  (1<<8)
+
+#define GPIO_PF    (0<<9)
+#define GPIO_AF    (1<<9)
+
+#define GPIO_OCR_SHIFT 10
+#define GPIO_OCR_MASK (3<<10)
+#define GPIO_AIN   (0<<10)
+#define GPIO_BIN   (1<<10)
+#define GPIO_CIN   (2<<10)
+#define GPIO_DR    (3<<10)
+
+#define GPIO_AOUT_SHIFT 12
+#define GPIO_AOUT_MASK (3<<12)
+#define GPIO_AOUT     (0<<12)
+#define GPIO_AOUT_ISR (1<<12)
+#define GPIO_AOUT_0   (2<<12)
+#define GPIO_AOUT_1   (3<<12)
+
+#define GPIO_BOUT_SHIFT 14
+#define GPIO_BOUT_MASK (3<<14)
+#define GPIO_BOUT      (0<<14)
+#define GPIO_BOUT_ISR  (1<<14)
+#define GPIO_BOUT_0    (2<<14)
+#define GPIO_BOUT_1    (3<<14)
+
+#define GPIO_GIUS      (1<<16)
+
+/* assignements for GPIO alternate/primary functions */
+
+/* FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#define PA0_AIN_SPI2_CLK     ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
+#define PA0_AF_ETMTRACESYNC  ( GPIO_PORTA | GPIO_AF | 0 )
+#define PA1_AOUT_SPI2_RXD    ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
+#define PA1_PF_TIN           ( GPIO_PORTA | GPIO_PF | 1 )
+#define PA2_PF_PWM0          ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
+#define PA3_PF_CSI_MCLK      ( GPIO_PORTA | GPIO_PF | 3 )
+#define PA4_PF_CSI_D0        ( GPIO_PORTA | GPIO_PF | 4 )
+#define PA5_PF_CSI_D1        ( GPIO_PORTA | GPIO_PF | 5 )
+#define PA6_PF_CSI_D2        ( GPIO_PORTA | GPIO_PF | 6 )
+#define PA7_PF_CSI_D3        ( GPIO_PORTA | GPIO_PF | 7 )
+#define PA8_PF_CSI_D4        ( GPIO_PORTA | GPIO_PF | 8 )
+#define PA9_PF_CSI_D5        ( GPIO_PORTA | GPIO_PF | 9 )
+#define PA10_PF_CSI_D6       ( GPIO_PORTA | GPIO_PF | 10 )
+#define PA11_PF_CSI_D7       ( GPIO_PORTA | GPIO_PF | 11 )
+#define PA12_PF_CSI_VSYNC    ( GPIO_PORTA | GPIO_PF | 12 )
+#define PA13_PF_CSI_HSYNC    ( GPIO_PORTA | GPIO_PF | 13 )
+#define PA14_PF_CSI_PIXCLK   ( GPIO_PORTA | GPIO_PF | 14 )
+#define PA15_PF_I2C_SDA      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
+#define PA16_PF_I2C_SCL      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
+#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
+#define PA17_AIN_SPI2_SS     ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
+#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
+#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
+#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
+#define PA21_PF_A0           ( GPIO_PORTA | GPIO_PF | 21 )
+#define PA22_PF_CS4          ( GPIO_PORTA | GPIO_PF | 22 )
+#define PA23_PF_CS5          ( GPIO_PORTA | GPIO_PF | 23 )
+#define PA24_PF_A16          ( GPIO_PORTA | GPIO_PF | 24 )
+#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
+#define PA25_PF_A17          ( GPIO_PORTA | GPIO_PF | 25 )
+#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
+#define PA26_PF_A18          ( GPIO_PORTA | GPIO_PF | 26 )
+#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
+#define PA27_PF_A19          ( GPIO_PORTA | GPIO_PF | 27 )
+#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
+#define PA28_PF_A20          ( GPIO_PORTA | GPIO_PF | 28 )
+#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
+#define PA29_PF_A21          ( GPIO_PORTA | GPIO_PF | 29 )
+#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
+#define PA30_PF_A22          ( GPIO_PORTA | GPIO_PF | 30 )
+#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
+#define PA31_PF_A23          ( GPIO_PORTA | GPIO_PF | 31 )
+#define PA31_AF_ETMTRACECLK  ( GPIO_PORTA | GPIO_AF | 31 )
+#define PB8_PF_SD_DAT0       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
+#define PB8_AF_MS_PIO        ( GPIO_PORTB | GPIO_AF | 8 )
+#define PB9_PF_SD_DAT1       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9 )
+#define PB9_AF_MS_PI1        ( GPIO_PORTB | GPIO_AF | 9 )
+#define PB10_PF_SD_DAT2      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10 )
+#define PB10_AF_MS_SCLKI     ( GPIO_PORTB | GPIO_AF | 10 )
+#define PB11_PF_SD_DAT3      ( GPIO_PORTB | GPIO_PF | 11 )
+#define PB11_AF_MS_SDIO      ( GPIO_PORTB | GPIO_AF | 11 )
+#define PB12_PF_SD_CLK       ( GPIO_PORTB | GPIO_PF | 12 )
+#define PB12_AF_MS_SCLK0     ( GPIO_PORTB | GPIO_AF | 12 )
+#define PB13_PF_SD_CMD       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
+#define PB13_AF_MS_BS        ( GPIO_PORTB | GPIO_AF | 13 )
+#define PB14_AF_SSI_RXFS     ( GPIO_PORTB | GPIO_AF | 14 )
+#define PB15_AF_SSI_RXCLK    ( GPIO_PORTB | GPIO_AF | 15 )
+#define PB16_AF_SSI_RXDAT    ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
+#define PB17_AF_SSI_TXDAT    ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
+#define PB18_AF_SSI_TXFS     ( GPIO_PORTB | GPIO_AF | 18 )
+#define PB19_AF_SSI_TXCLK    ( GPIO_PORTB | GPIO_AF | 19 )
+#define PB20_PF_USBD_AFE     ( GPIO_PORTB | GPIO_PF | 20 )
+#define PB21_PF_USBD_OE      ( GPIO_PORTB | GPIO_PF | 21 )
+#define PB22_PFUSBD_RCV      ( GPIO_PORTB | GPIO_PF | 22 )
+#define PB23_PF_USBD_SUSPND  ( GPIO_PORTB | GPIO_PF | 23 )
+#define PB24_PF_USBD_VP      ( GPIO_PORTB | GPIO_PF | 24 )
+#define PB25_PF_USBD_VM      ( GPIO_PORTB | GPIO_PF | 25 )
+#define PB26_PF_USBD_VPO     ( GPIO_PORTB | GPIO_PF | 26 )
+#define PB27_PF_USBD_VMO     ( GPIO_PORTB | GPIO_PF | 27 )
+#define PB28_PF_UART2_CTS    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
+#define PB29_PF_UART2_RTS    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
+#define PB30_PF_UART2_TXD    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
+#define PB31_PF_UART2_RXD    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
+#define PC3_PF_SSI_RXFS      ( GPIO_PORTC | GPIO_PF | 3 )
+#define PC4_PF_SSI_RXCLK     ( GPIO_PORTC | GPIO_PF | 4 )
+#define PC5_PF_SSI_RXDAT     ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
+#define PC6_PF_SSI_TXDAT     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
+#define PC7_PF_SSI_TXFS      ( GPIO_PORTC | GPIO_PF | 7 )
+#define PC8_PF_SSI_TXCLK     ( GPIO_PORTC | GPIO_PF | 8 )
+#define PC9_PF_UART1_CTS     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
+#define PC10_PF_UART1_RTS    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
+#define PC11_PF_UART1_TXD    ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
+#define PC12_PF_UART1_RXD    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
+#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
+#define PC14_PF_SPI1_SCLK    ( GPIO_PORTC | GPIO_PF | 14 )
+#define PC15_PF_SPI1_SS      ( GPIO_PORTC | GPIO_PF | 15 )
+#define PC16_PF_SPI1_MISO    ( GPIO_PORTC | GPIO_PF | 16 )
+#define PC17_PF_SPI1_MOSI    ( GPIO_PORTC | GPIO_PF | 17 )
+#define PC24_BIN_UART3_RI    ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
+#define PC25_BIN_UART3_DSR   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
+#define PC26_AOUT_UART3_DTR  ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
+#define PC27_BIN_UART3_DCD   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
+#define PC28_BIN_UART3_CTS   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
+#define PC29_AOUT_UART3_RTS  ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
+#define PC30_BIN_UART3_TX    ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
+#define PC31_AOUT_UART3_RX   ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
+#define PD6_PF_LSCLK         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
+#define PD7_PF_REV           ( GPIO_PORTD | GPIO_PF | 7 )
+#define PD7_AF_UART2_DTR     ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
+#define PD7_AIN_SPI2_SCLK    ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
+#define PD8_PF_CLS           ( GPIO_PORTD | GPIO_PF | 8 )
+#define PD8_AF_UART2_DCD     ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
+#define PD8_AIN_SPI2_SS      ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
+#define PD9_PF_PS            ( GPIO_PORTD | GPIO_PF | 9 )
+#define PD9_AF_UART2_RI      ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
+#define PD9_AOUT_SPI2_RXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
+#define PD10_PF_SPL_SPR      ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
+#define PD10_AF_UART2_DSR    ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
+#define PD10_AIN_SPI2_TXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
+#define PD11_PF_CONTRAST     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
+#define PD12_PF_ACD_OE       ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
+#define PD13_PF_LP_HSYNC     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
+#define PD14_PF_FLM_VSYNC    ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
+#define PD15_PF_LD0          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
+#define PD16_PF_LD1          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
+#define PD17_PF_LD2          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
+#define PD18_PF_LD3          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
+#define PD19_PF_LD4          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
+#define PD20_PF_LD5          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
+#define PD21_PF_LD6          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
+#define PD22_PF_LD7          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
+#define PD23_PF_LD8          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
+#define PD24_PF_LD9          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
+#define PD25_PF_LD10         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
+#define PD26_PF_LD11         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
+#define PD27_PF_LD12         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
+#define PD28_PF_LD13         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
+#define PD29_PF_LD14         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
+#define PD30_PF_LD15         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
+#define PD31_PF_TMR2OUT      ( GPIO_PORTD | GPIO_PF | 31 )
+#define PD31_BIN_SPI2_TXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
+
+/*
+ * PWM controller
+ */
+#define PWMC	__REG(IMX_PWM_BASE + 0x00)	/* PWM Control Register		*/
+#define PWMS	__REG(IMX_PWM_BASE + 0x04)	/* PWM Sample Register		*/
+#define PWMP	__REG(IMX_PWM_BASE + 0x08)	/* PWM Period Register		*/
+#define PWMCNT	__REG(IMX_PWM_BASE + 0x0C)	/* PWM Counter Register		*/
+
+#define PWMC_HCTR		(0x01<<18)		/* Halfword FIFO Data Swapping	*/
+#define PWMC_BCTR		(0x01<<17)		/* Byte FIFO Data Swapping	*/
+#define PWMC_SWR		(0x01<<16)		/* Software Reset		*/
+#define PWMC_CLKSRC		(0x01<<15)		/* Clock Source			*/
+#define PWMC_PRESCALER(x)	(((x-1) & 0x7F) << 8)	/* PRESCALER			*/
+#define PWMC_IRQ		(0x01<< 7)		/* Interrupt Request		*/
+#define PWMC_IRQEN		(0x01<< 6)		/* Interrupt Request Enable	*/
+#define PWMC_FIFOAV		(0x01<< 5)		/* FIFO Available		*/
+#define PWMC_EN			(0x01<< 4)		/* Enables/Disables the PWM	*/
+#define PWMC_REPEAT(x)		(((x) & 0x03) << 2)	/* Sample Repeats		*/
+#define PWMC_CLKSEL(x)		(((x) & 0x03) << 0)	/* Clock Selection		*/
+
+#define PWMS_SAMPLE(x)		((x) & 0xFFFF)		/* Contains a two-sample word	*/
+#define PWMP_PERIOD(x)		((x) & 0xFFFF)		/* Represents the PWM's period	*/
+#define PWMC_COUNTER(x)		((x) & 0xFFFF)		/* Represents the current count value	*/
+
+/*
+ *  DMA Controller
+ */
+#define DCR     __REG(IMX_DMAC_BASE +0x00)	/* DMA Control Register */
+#define DISR    __REG(IMX_DMAC_BASE +0x04)	/* DMA Interrupt status Register */
+#define DIMR    __REG(IMX_DMAC_BASE +0x08)	/* DMA Interrupt mask Register */
+#define DBTOSR  __REG(IMX_DMAC_BASE +0x0c)	/* DMA Burst timeout status Register */
+#define DRTOSR  __REG(IMX_DMAC_BASE +0x10)	/* DMA Request timeout Register */
+#define DSESR   __REG(IMX_DMAC_BASE +0x14)	/* DMA Transfer Error Status Register */
+#define DBOSR   __REG(IMX_DMAC_BASE +0x18)	/* DMA Buffer overflow status Register */
+#define DBTOCR  __REG(IMX_DMAC_BASE +0x1c)	/* DMA Burst timeout control Register */
+#define WSRA    __REG(IMX_DMAC_BASE +0x40)	/* W-Size Register A */
+#define XSRA    __REG(IMX_DMAC_BASE +0x44)	/* X-Size Register A */
+#define YSRA    __REG(IMX_DMAC_BASE +0x48)	/* Y-Size Register A */
+#define WSRB    __REG(IMX_DMAC_BASE +0x4c)	/* W-Size Register B */
+#define XSRB    __REG(IMX_DMAC_BASE +0x50)	/* X-Size Register B */
+#define YSRB    __REG(IMX_DMAC_BASE +0x54)	/* Y-Size Register B */
+#define SAR(x)  __REG2( IMX_DMAC_BASE + 0x80, (x) << 6)	/* Source Address Registers */
+#define DAR(x)  __REG2( IMX_DMAC_BASE + 0x84, (x) << 6)	/* Destination Address Registers */
+#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6)	/* Count Registers */
+#define CCR(x)  __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6)	/* Control Registers */
+#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6)	/* Request source select Registers */
+#define BLR(x)  __REG2( IMX_DMAC_BASE + 0x94, (x) << 6)	/* Burst length Registers */
+#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Request timeout Registers */
+#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Bus Utilization Registers */
+
+/* TODO: define DMA_REQ lines */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff )
+#define CNTR_CNT(x)        ((x) & 0xffffff )
+#define CCR_DMOD_LINEAR    ( 0x0 << 12 )
+#define CCR_DMOD_2D        ( 0x1 << 12 )
+#define CCR_DMOD_FIFO      ( 0x2 << 12 )
+#define CCR_DMOD_EOBFIFO   ( 0x3 << 12 )
+#define CCR_SMOD_LINEAR    ( 0x0 << 10 )
+#define CCR_SMOD_2D        ( 0x1 << 10 )
+#define CCR_SMOD_FIFO      ( 0x2 << 10 )
+#define CCR_SMOD_EOBFIFO   ( 0x3 << 10 )
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        ( 0x0 << 6 )
+#define CCR_DSIZ_8         ( 0x1 << 6 )
+#define CCR_DSIZ_16        ( 0x2 << 6 )
+#define CCR_SSIZ_32        ( 0x0 << 4 )
+#define CCR_SSIZ_8         ( 0x1 << 4 )
+#define CCR_SSIZ_16        ( 0x2 << 4 )
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
+
+/*
+ * LCD Controller
+ */
+
+#define LCDC_SSA	__REG(IMX_LCDC_BASE+0x00)
+
+#define LCDC_SIZE	__REG(IMX_LCDC_BASE+0x04)
+#define SIZE_XMAX(x)	((((x) >> 4) & 0x3f) << 20)
+#define SIZE_YMAX(y)    ( (y) & 0x1ff )
+
+#define LCDC_VPW	__REG(IMX_LCDC_BASE+0x08)
+#define VPW_VPW(x)	( (x) & 0x3ff )
+
+#define LCDC_CPOS	__REG(IMX_LCDC_BASE+0x0C)
+#define CPOS_CC1        (1<<31)
+#define CPOS_CC0        (1<<30)
+#define CPOS_OP         (1<<28)
+#define CPOS_CXP(x)     (((x) & 3ff) << 16)
+#define CPOS_CYP(y)     ((y) & 0x1ff)
+
+#define LCDC_LCWHB	__REG(IMX_LCDC_BASE+0x10)
+#define LCWHB_BK_EN     (1<<31)
+#define LCWHB_CW(w)     (((w) & 0x1f) << 24)
+#define LCWHB_CH(h)     (((h) & 0x1f) << 16)
+#define LCWHB_BD(x)     ((x) & 0xff)
+
+#define LCDC_LCHCC	__REG(IMX_LCDC_BASE+0x14)
+#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
+#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
+#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
+
+#define LCDC_PCR	__REG(IMX_LCDC_BASE+0x18)
+#define PCR_TFT         (1<<31)
+#define PCR_COLOR       (1<<30)
+#define PCR_PBSIZ_1     (0<<28)
+#define PCR_PBSIZ_2     (1<<28)
+#define PCR_PBSIZ_4     (2<<28)
+#define PCR_PBSIZ_8     (3<<28)
+#define PCR_BPIX_1      (0<<25)
+#define PCR_BPIX_2      (1<<25)
+#define PCR_BPIX_4      (2<<25)
+#define PCR_BPIX_8      (3<<25)
+#define PCR_BPIX_12     (4<<25)
+#define PCR_BPIX_16     (4<<25)
+#define PCR_PIXPOL      (1<<24)
+#define PCR_FLMPOL      (1<<23)
+#define PCR_LPPOL       (1<<22)
+#define PCR_CLKPOL      (1<<21)
+#define PCR_OEPOL       (1<<20)
+#define PCR_SCLKIDLE    (1<<19)
+#define PCR_END_SEL     (1<<18)
+#define PCR_END_BYTE_SWAP (1<<17)
+#define PCR_REV_VS      (1<<16)
+#define PCR_ACD_SEL     (1<<15)
+#define PCR_ACD(x)      (((x) & 0x7f) << 8)
+#define PCR_SCLK_SEL    (1<<7)
+#define PCR_SHARP       (1<<6)
+#define PCR_PCD(x)      ((x) & 0x3f)
+
+#define LCDC_HCR	__REG(IMX_LCDC_BASE+0x1C)
+#define HCR_H_WIDTH(x)  (((x) & 0x3f) << 26)
+#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
+#define HCR_H_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_VCR	__REG(IMX_LCDC_BASE+0x20)
+#define VCR_V_WIDTH(x)  (((x) & 0x3f) << 26)
+#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
+#define VCR_V_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_POS	__REG(IMX_LCDC_BASE+0x24)
+#define POS_POS(x)      ((x) & 1f)
+
+#define LCDC_LSCR1	__REG(IMX_LCDC_BASE+0x28)
+#define LSCR1_PS_RISE_DELAY(x)    (((x) & 0x7f) << 26)
+#define LSCR1_CLS_RISE_DELAY(x)   (((x) & 0x3f) << 16)
+#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
+#define LSCR1_GRAY2(x)            (((x) & 0xf) << 4)
+#define LSCR1_GRAY1(x)            (((x) & 0xf))
+
+#define LCDC_PWMR	__REG(IMX_LCDC_BASE+0x2C)
+#define PWMR_CLS(x)     (((x) & 0x1ff) << 16)
+#define PWMR_LDMSK      (1<<15)
+#define PWMR_SCR1       (1<<10)
+#define PWMR_SCR0       (1<<9)
+#define PWMR_CC_EN      (1<<8)
+#define PWMR_PW(x)      ((x) & 0xff)
+
+#define LCDC_DMACR	__REG(IMX_LCDC_BASE+0x30)
+#define DMACR_BURST     (1<<31)
+#define DMACR_HM(x)     (((x) & 0xf) << 16)
+#define DMACR_TM(x)     ((x) &0xf)
+
+#define LCDC_RMCR	__REG(IMX_LCDC_BASE+0x34)
+#define RMCR_LCDC_EN		(1<<1)
+#define RMCR_SELF_REF		(1<<0)
+
+#define LCDC_LCDICR	__REG(IMX_LCDC_BASE+0x38)
+#define LCDICR_INT_SYN  (1<<2)
+#define LCDICR_INT_CON  (1)
+
+#define LCDC_LCDISR	__REG(IMX_LCDC_BASE+0x40)
+#define LCDISR_UDR_ERR (1<<3)
+#define LCDISR_ERR_RES (1<<2)
+#define LCDISR_EOF     (1<<1)
+#define LCDISR_BOF     (1<<0)
+/*
+ *  UART Module
+ */
+#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12)	/* Receiver Register */
+#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12)	/* Transmitter Register */
+#define UCR1(x)  __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12)	/* Control Register 1 */
+#define UCR2(x)  __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12)	/* Control Register 2 */
+#define UCR3(x)  __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12)	/* Control Register 3 */
+#define UCR4(x)  __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12)	/* Control Register 4 */
+#define UFCR(x)  __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12)	/* FIFO Control Register */
+#define USR1(x)  __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12)	/* Status Register 1 */
+#define USR2(x)  __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12)	/* Status Register 2 */
+#define UESC(x)  __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12)	/* Escape Character Register */
+#define UTIM(x)  __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12)	/* Escape Timer Register */
+#define UBIR(x)  __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12)	/* BRM Incremental Register */
+#define UBMR(x)  __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12)	/* BRM Modulator Register */
+#define UBRC(x)  __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12)	/* Baud Rate Count Register */
+#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12)	/* Incremental Preset Register 1 */
+#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12)	/* Incremental Preset Register 2 */
+#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12)	/* Incremental Preset Register 3 */
+#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12)	/* Incremental Preset Register 4 */
+#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12)	/* BRM Modulator Register 1 */
+#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12)	/* BRM Modulator Register 2 */
+#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12)	/* BRM Modulator Register 3 */
+#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12)	/* BRM Modulator Register 4 */
+#define UTS(x)   __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12)	/* UART Test Register */
+
+/* UART Control Register Bit Fields.*/
+#define  URXD_CHARRDY    (1<<15)
+#define  URXD_ERR        (1<<14)
+#define  URXD_OVRRUN     (1<<13)
+#define  URXD_FRMERR     (1<<12)
+#define  URXD_BRK        (1<<11)
+#define  URXD_PRERR      (1<<10)
+#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
+#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
+#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
+#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
+#define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
+#define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
+#define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
+#define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
+#define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
+#define  UCR1_SNDBRK     (1<<4)	 /* Send break */
+#define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
+#define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
+#define  UCR1_DOZE       (1<<1)	 /* Doze */
+#define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
+#define  UCR2_ESCI	 (1<<15) /* Escape seq interrupt enable */
+#define  UCR2_IRTS	 (1<<14) /* Ignore RTS pin */
+#define  UCR2_CTSC	 (1<<13) /* CTS pin control */
+#define  UCR2_CTS        (1<<12) /* Clear to send */
+#define  UCR2_ESCEN      (1<<11) /* Escape enable */
+#define  UCR2_PREN       (1<<8) /* Parity enable */
+#define  UCR2_PROE       (1<<7) /* Parity odd/even */
+#define  UCR2_STPB       (1<<6)	/* Stop */
+#define  UCR2_WS         (1<<5)	/* Word size */
+#define  UCR2_RTSEN      (1<<4)	/* Request to send interrupt enable */
+#define  UCR2_TXEN       (1<<2)	/* Transmitter enabled */
+#define  UCR2_RXEN       (1<<1)	/* Receiver enabled */
+#define  UCR2_SRST	 (1<<0)	/* SW reset */
+#define  UCR3_DTREN	 (1<<13) /* DTR interrupt enable */
+#define  UCR3_PARERREN   (1<<12) /* Parity enable */
+#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
+#define  UCR3_DSR        (1<<10) /* Data set ready */
+#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
+#define  UCR3_RI         (1<<8)  /* Ring indicator */
+#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
+#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
+#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
+#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
+#define  UCR3_REF25	 (1<<3)  /* Ref freq 25 MHz */
+#define  UCR3_REF30	 (1<<2)  /* Ref Freq 30 MHz */
+#define  UCR3_INVT	 (1<<1)  /* Inverted Infrared transmission */
+#define  UCR3_BPEN	 (1<<0)  /* Preset registers enable */
+#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
+#define  UCR4_INVR	 (1<<9)  /* Inverted infrared reception */
+#define  UCR4_ENIRI	 (1<<8)  /* Serial infrared interrupt enable */
+#define  UCR4_WKEN	 (1<<7)  /* Wake interrupt enable */
+#define  UCR4_REF16	 (1<<6)  /* Ref freq 16 MHz */
+#define  UCR4_IRSC	 (1<<5) /* IR special case */
+#define  UCR4_TCEN	 (1<<3) /* Transmit complete interrupt enable */
+#define  UCR4_BKEN	 (1<<2) /* Break condition interrupt enable */
+#define  UCR4_OREN	 (1<<1) /* Receiver overrun interrupt enable */
+#define  UCR4_DREN	 (1<<0) /* Recv data ready interrupt enable */
+#define  UFCR_RXTL_SHF   0      /* Receiver trigger level shift */
+#define  UFCR_RFDIV      (7<<7) /* Reference freq divider mask */
+#define  UFCR_TXTL_SHF   10     /* Transmitter trigger level shift */
+#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
+#define  USR1_RTSS	 (1<<14) /* RTS pin status */
+#define  USR1_TRDY	 (1<<13) /* Transmitter ready interrupt/dma flag */
+#define  USR1_RTSD	 (1<<12) /* RTS delta */
+#define  USR1_ESCF	 (1<<11) /* Escape seq interrupt flag */
+#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
+#define  USR1_RRDY       (1<<9)	/* Receiver ready interrupt/dma flag */
+#define  USR1_TIMEOUT    (1<<7)	/* Receive timeout interrupt status */
+#define  USR1_RXDS	 (1<<6)	/* Receiver idle interrupt flag */
+#define  USR1_AIRINT	 (1<<5)	/* Async IR wake interrupt flag */
+#define  USR1_AWAKE	 (1<<4)	/* Aysnc wake interrupt flag */
+#define  USR2_ADET	 (1<<15) /* Auto baud rate detect complete */
+#define  USR2_TXFE	 (1<<14) /* Transmit buffer FIFO empty */
+#define  USR2_DTRF	 (1<<13) /* DTR edge interrupt flag */
+#define  USR2_IDLE	 (1<<12) /* Idle condition */
+#define  USR2_IRINT	 (1<<8)	/* Serial infrared interrupt flag */
+#define  USR2_WAKE	 (1<<7)	/* Wake */
+#define  USR2_RTSF	 (1<<4)	/* RTS edge interrupt flag */
+#define  USR2_TXDC	 (1<<3)	/* Transmitter complete */
+#define  USR2_BRCD	 (1<<2)	/* Break condition */
+#define  USR2_ORE        (1<<1)	/* Overrun error */
+#define  USR2_RDR        (1<<0)	/* Recv data ready */
+#define  UTS_FRCPERR	 (1<<13) /* Force parity error */
+#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
+#define  UTS_TXEMPTY	 (1<<6)	/* TxFIFO empty */
+#define  UTS_RXEMPTY	 (1<<5)	/* RxFIFO empty */
+#define  UTS_TXFULL	 (1<<4)	/* TxFIFO full */
+#define  UTS_RXFULL	 (1<<3)	/* RxFIFO full */
+#define  UTS_SOFTRST	 (1<<0)	/* Software reset */
+
+/* General purpose timers registers */
+#define TCTL1   __REG(IMX_TIM1_BASE)
+#define TPRER1  __REG(IMX_TIM1_BASE + 0x4)
+#define TCMP1   __REG(IMX_TIM1_BASE + 0x8)
+#define TCR1    __REG(IMX_TIM1_BASE + 0xc)
+#define TCN1    __REG(IMX_TIM1_BASE + 0x10)
+#define TSTAT1  __REG(IMX_TIM1_BASE + 0x14)
+#define TCTL2   __REG(IMX_TIM2_BASE)
+#define TPRER2  __REG(IMX_TIM2_BASE + 0x4)
+#define TCMP2   __REG(IMX_TIM2_BASE + 0x8)
+#define TCR2    __REG(IMX_TIM2_BASE + 0xc)
+#define TCN2    __REG(IMX_TIM2_BASE + 0x10)
+#define TSTAT2  __REG(IMX_TIM2_BASE + 0x14)
+
+/* General purpose timers bitfields */
+#define TCTL_SWR       (1<<15) /* Software reset */
+#define TCTL_FRR       (1<<8)  /* Freerun / restart */
+#define TCTL_CAP       (3<<6)  /* Capture Edge */
+#define TCTL_OM        (1<<5)  /* output mode */
+#define TCTL_IRQEN     (1<<4)  /* interrupt enable */
+#define TCTL_CLKSOURCE (7<<1)  /* Clock source */
+#define TCTL_TEN       (1)     /* Timer enable */
+#define TPRER_PRES     (0xff)  /* Prescale */
+#define TSTAT_CAPT     (1<<1)  /* Capture event */
+#define TSTAT_COMP     (1)     /* Compare event */
+
+#endif				/* _IMX_REGS_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock-k2hk.h
new file mode 100644
index 000000000..6a69a8d2b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -0,0 +1,109 @@
+/*
+ * K2HK: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2HK_H
+#define __ASM_ARCH_CLOCK_K2HK_H
+
+#include <asm/arch/hardware.h>
+
+#ifndef __ASSEMBLY__
+
+enum ext_clk_e {
+	sys_clk,
+	alt_core_clk,
+	pa_clk,
+	tetris_clk,
+	ddr3a_clk,
+	ddr3b_clk,
+	mcm_clk,
+	pcie_clk,
+	sgmii_srio_clk,
+	xgmii_clk,
+	usb_clk,
+	rp1_clk,
+	ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+enum clk_e {
+	core_pll_clk,
+	pass_pll_clk,
+	tetris_pll_clk,
+	ddr3a_pll_clk,
+	ddr3b_pll_clk,
+	sys_clk0_clk,
+	sys_clk0_1_clk,
+	sys_clk0_2_clk,
+	sys_clk0_3_clk,
+	sys_clk0_4_clk,
+	sys_clk0_6_clk,
+	sys_clk0_8_clk,
+	sys_clk0_12_clk,
+	sys_clk0_24_clk,
+	sys_clk1_clk,
+	sys_clk1_3_clk,
+	sys_clk1_4_clk,
+	sys_clk1_6_clk,
+	sys_clk1_12_clk,
+	sys_clk2_clk,
+	sys_clk3_clk
+};
+
+#define K2HK_CLK1_6 sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+	CORE_PLL,
+	PASS_PLL,
+	TETRIS_PLL,
+	DDR3A_PLL,
+	DDR3B_PLL,
+};
+#define MAIN_PLL CORE_PLL
+
+/* PLL configuration data */
+struct pll_init_data {
+	int pll;
+	int pll_m;		/* PLL Multiplier */
+	int pll_d;		/* PLL divider */
+	int pll_od;		/* PLL output divider    */
+};
+
+#define CORE_PLL_799    {CORE_PLL,	13,	1,	2}
+#define CORE_PLL_983    {CORE_PLL,	16,	1,	2}
+#define CORE_PLL_1167   {CORE_PLL,	19,	1,	2}
+#define CORE_PLL_1228   {CORE_PLL,	20,	1,	2}
+#define PASS_PLL_1228   {PASS_PLL,	20,	1,	2}
+#define PASS_PLL_983    {PASS_PLL,	16,	1,	2}
+#define PASS_PLL_1050   {PASS_PLL,	205,    12,	2}
+#define TETRIS_PLL_500  {TETRIS_PLL,	8,	1,	2}
+#define TETRIS_PLL_750  {TETRIS_PLL,	12,	1,	2}
+#define TETRIS_PLL_687  {TETRIS_PLL,	11,	1,	2}
+#define TETRIS_PLL_625  {TETRIS_PLL,	10,	1,	2}
+#define TETRIS_PLL_812  {TETRIS_PLL,	13,	1,	2}
+#define TETRIS_PLL_875  {TETRIS_PLL,	14,	1,	2}
+#define TETRIS_PLL_1188 {TETRIS_PLL,	19,	2,	1}
+#define TETRIS_PLL_1200 {TETRIS_PLL,	48,	5,	1}
+#define TETRIS_PLL_1375 {TETRIS_PLL,	22,	2,	1}
+#define TETRIS_PLL_1400 {TETRIS_PLL,	56,	5,	1}
+#define DDR3_PLL_200(x)	{DDR3##x##_PLL,	4,	1,	2}
+#define DDR3_PLL_400(x)	{DDR3##x##_PLL,	16,	1,	4}
+#define DDR3_PLL_800(x)	{DDR3##x##_PLL,	16,	1,	2}
+#define DDR3_PLL_333(x)	{DDR3##x##_PLL,	20,	1,	6}
+
+void init_plls(int num_pll, struct pll_init_data *config);
+void init_pll(const struct pll_init_data *data);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock.h
new file mode 100644
index 000000000..324501b75
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock.h
@@ -0,0 +1,17 @@
+/*
+ * keystone2: common clock header file
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#ifdef CONFIG_SOC_K2HK
+#include <asm/arch/clock-k2hk.h>
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock_defs.h
new file mode 100644
index 000000000..b251aff38
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/clock_defs.h
@@ -0,0 +1,111 @@
+/*
+ * keystone2: common pll clock definitions
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _CLOCK_DEFS_H_
+#define _CLOCK_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+#define BIT(x)			(1 << (x))
+
+/* PLL Control Registers */
+struct pllctl_regs {
+	u32	ctl;		/* 00 */
+	u32	ocsel;		/* 04 */
+	u32	secctl;		/* 08 */
+	u32	resv0;
+	u32	mult;		/* 10 */
+	u32	prediv;		/* 14 */
+	u32	div1;		/* 18 */
+	u32	div2;		/* 1c */
+	u32	div3;		/* 20 */
+	u32	oscdiv1;	/* 24 */
+	u32	resv1;		/* 28 */
+	u32	bpdiv;		/* 2c */
+	u32	wakeup;		/* 30 */
+	u32	resv2;
+	u32	cmd;		/* 38 */
+	u32	stat;		/* 3c */
+	u32	alnctl;		/* 40 */
+	u32	dchange;	/* 44 */
+	u32	cken;		/* 48 */
+	u32	ckstat;		/* 4c */
+	u32	systat;		/* 50 */
+	u32	ckctl;		/* 54 */
+	u32	resv3[2];
+	u32	div4;		/* 60 */
+	u32	div5;		/* 64 */
+	u32	div6;		/* 68 */
+	u32	div7;		/* 6c */
+	u32	div8;		/* 70 */
+	u32	div9;		/* 74 */
+	u32	div10;		/* 78 */
+	u32	div11;		/* 7c */
+	u32	div12;		/* 80 */
+};
+
+static struct pllctl_regs *pllctl_regs[] = {
+	(struct pllctl_regs *)(CLOCK_BASE + 0x100)
+};
+
+#define pllctl_reg(pll, reg)            (&(pllctl_regs[pll]->reg))
+#define pllctl_reg_read(pll, reg)       __raw_readl(pllctl_reg(pll, reg))
+#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
+
+#define pllctl_reg_rmw(pll, reg, mask, val) \
+	pllctl_reg_write(pll, reg, \
+		(pllctl_reg_read(pll, reg) & ~(mask)) | val)
+
+#define pllctl_reg_setbits(pll, reg, mask) \
+	pllctl_reg_rmw(pll, reg, 0, mask)
+
+#define pllctl_reg_clrbits(pll, reg, mask) \
+	pllctl_reg_rmw(pll, reg, mask, 0)
+
+#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
+
+/* PLLCTL Bits */
+#define PLLCTL_BYPASS           BIT(23)
+#define PLL_PLLRST              BIT(14)
+#define PLLCTL_PAPLL            BIT(13)
+#define PLLCTL_CLKMODE          BIT(8)
+#define PLLCTL_PLLSELB          BIT(7)
+#define PLLCTL_ENSAT            BIT(6)
+#define PLLCTL_PLLENSRC         BIT(5)
+#define PLLCTL_PLLDIS           BIT(4)
+#define PLLCTL_PLLRST           BIT(3)
+#define PLLCTL_PLLPWRDN         BIT(1)
+#define PLLCTL_PLLEN            BIT(0)
+#define PLLSTAT_GO              BIT(0)
+
+#define MAIN_ENSAT_OFFSET       6
+
+#define PLLDIV_ENABLE           BIT(15)
+
+#define PLL_DIV_MASK            0x3f
+#define PLL_MULT_MASK           0x1fff
+#define PLL_MULT_SHIFT          6
+#define PLLM_MULT_HI_MASK       0x7f
+#define PLLM_MULT_HI_SHIFT      12
+#define PLLM_MULT_HI_SMASK      (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
+#define PLLM_MULT_LO_MASK       0x3f
+#define PLL_CLKOD_MASK          0xf
+#define PLL_CLKOD_SHIFT         19
+#define PLL_CLKOD_SMASK         (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
+#define PLL_BWADJ_LO_MASK       0xff
+#define PLL_BWADJ_LO_SHIFT      24
+#define PLL_BWADJ_LO_SMASK      (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
+#define PLL_BWADJ_HI_MASK       0xf
+
+#define PLLM_RATIO_DIV1         (PLLDIV_ENABLE | 0)
+#define PLLM_RATIO_DIV2         (PLLDIV_ENABLE | 0)
+#define PLLM_RATIO_DIV3         (PLLDIV_ENABLE | 1)
+#define PLLM_RATIO_DIV4         (PLLDIV_ENABLE | 4)
+#define PLLM_RATIO_DIV5         (PLLDIV_ENABLE | 17)
+
+#endif  /* _CLOCK_DEFS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emac_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emac_defs.h
new file mode 100644
index 000000000..0aa2f89d7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emac_defs.h
@@ -0,0 +1,240 @@
+/*
+ * emac definitions for keystone2 devices
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _EMAC_DEFS_H_
+#define _EMAC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define DEVICE_REG32_R(a)               readl(a)
+#define DEVICE_REG32_W(a, v)            writel(v, a)
+
+#define EMAC_EMACSL_BASE_ADDR           (KS2_PASS_BASE + 0x00090900)
+#define EMAC_MDIO_BASE_ADDR             (KS2_PASS_BASE + 0x00090300)
+#define EMAC_SGMII_BASE_ADDR            (KS2_PASS_BASE + 0x00090100)
+
+#define KEYSTONE2_EMAC_GIG_ENABLE
+
+#define MAC_ID_BASE_ADDR                (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+
+#ifdef CONFIG_SOC_K2HK
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ              (clk_get_rate(pass_pll_clk))
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ            1000000		/* 1.0 MHz */
+#endif
+
+/* MII Status Register */
+#define MII_STATUS_REG                  1
+#define MII_STATUS_LINK_MASK            (0x4)
+
+/* Marvell 88E1111 PHY ID */
+#define PHY_MARVELL_88E1111             (0x01410cc0)
+
+#define MDIO_CONTROL_IDLE               (0x80000000)
+#define MDIO_CONTROL_ENABLE             (0x40000000)
+#define MDIO_CONTROL_FAULT_ENABLE       (0x40000)
+#define MDIO_CONTROL_FAULT              (0x80000)
+#define MDIO_USERACCESS0_GO             (0x80000000)
+#define MDIO_USERACCESS0_WRITE_READ     (0x0)
+#define MDIO_USERACCESS0_WRITE_WRITE    (0x40000000)
+#define MDIO_USERACCESS0_ACK            (0x20000000)
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE       (0x20)
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE  (0x1)
+#define EMAC_MACCONTROL_GIGABIT_ENABLE     (1 << 7)
+#define EMAC_MACCONTROL_GIGFORCE           (1 << 17)
+#define EMAC_MACCONTROL_RMIISPEED_100      (1 << 15)
+
+#define EMAC_MIN_ETHERNET_PKT_SIZE         60
+
+struct mac_sl_cfg {
+	u_int32_t max_rx_len;	/* Maximum receive packet length. */
+	u_int32_t ctl;		/* Control bitfield */
+};
+
+/*
+ * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
+ */
+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES       (1 << 24)
+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES         (1 << 23)
+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES         (1 << 22)
+#define GMACSL_RX_ENABLE_EXT_CTL                  (1 << 18)
+#define GMACSL_RX_ENABLE_GIG_FORCE                (1 << 17)
+#define GMACSL_RX_ENABLE_IFCTL_B                  (1 << 16)
+#define GMACSL_RX_ENABLE_IFCTL_A                  (1 << 15)
+#define GMACSL_RX_ENABLE_CMD_IDLE                 (1 << 11)
+#define GMACSL_TX_ENABLE_SHORT_GAP                (1 << 10)
+#define GMACSL_ENABLE_GIG_MODE                    (1 <<  7)
+#define GMACSL_TX_ENABLE_PACE                     (1 <<  6)
+#define GMACSL_ENABLE                             (1 <<  5)
+#define GMACSL_TX_ENABLE_FLOW_CTL                 (1 <<  4)
+#define GMACSL_RX_ENABLE_FLOW_CTL                 (1 <<  3)
+#define GMACSL_ENABLE_LOOPBACK                    (1 <<  1)
+#define GMACSL_ENABLE_FULL_DUPLEX                 (1 <<  0)
+
+/*
+ * DEFINTITION: function return values
+ */
+#define GMACSL_RET_OK                        0
+#define GMACSL_RET_INVALID_PORT             -1
+#define GMACSL_RET_WARN_RESET_INCOMPLETE    -2
+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG      -3
+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
+
+/* Register offsets */
+#define CPGMACSL_REG_ID         0x00
+#define CPGMACSL_REG_CTL        0x04
+#define CPGMACSL_REG_STATUS     0x08
+#define CPGMACSL_REG_RESET      0x0c
+#define CPGMACSL_REG_MAXLEN     0x10
+#define CPGMACSL_REG_BOFF       0x14
+#define CPGMACSL_REG_RX_PAUSE   0x18
+#define CPGMACSL_REG_TX_PAURSE  0x1c
+#define CPGMACSL_REG_EM_CTL     0x20
+#define CPGMACSL_REG_PRI        0x24
+
+/* Soft reset register values */
+#define CPGMAC_REG_RESET_VAL_RESET_MASK      (1 << 0)
+#define CPGMAC_REG_RESET_VAL_RESET           (1 << 0)
+
+/* Maxlen register values */
+#define CPGMAC_REG_MAXLEN_LEN                0x3fff
+
+/* Control bitfields */
+#define CPSW_CTL_P2_PASS_PRI_TAGGED     (1 << 5)
+#define CPSW_CTL_P1_PASS_PRI_TAGGED     (1 << 4)
+#define CPSW_CTL_P0_PASS_PRI_TAGGED     (1 << 3)
+#define CPSW_CTL_P0_ENABLE              (1 << 2)
+#define CPSW_CTL_VLAN_AWARE             (1 << 1)
+#define CPSW_CTL_FIFO_LOOPBACK          (1 << 0)
+
+#define DEVICE_CPSW_NUM_PORTS       5                    /* 5 switch ports */
+#define DEVICE_CPSW_BASE            (0x02090800)
+#define target_get_switch_ctl()     CPSW_CTL_P0_ENABLE   /* Enable port 0 */
+#define SWITCH_MAX_PKT_SIZE         9000
+
+/* Register offsets */
+#define CPSW_REG_CTL                0x004
+#define CPSW_REG_STAT_PORT_EN       0x00c
+#define CPSW_REG_MAXLEN             0x040
+#define CPSW_REG_ALE_CONTROL        0x608
+#define CPSW_REG_ALE_PORTCTL(x)     (0x640 + (x)*4)
+
+/* Register values */
+#define CPSW_REG_VAL_STAT_ENABLE_ALL             0xf
+#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE    ((u_int32_t)0xc0000000)
+#define CPSW_REG_VAL_ALE_CTL_BYPASS              ((u_int32_t)0x00000010)
+#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE        0x3
+
+#define SGMII_REG_STATUS_LOCK           BIT(4)
+#define SGMII_REG_STATUS_LINK           BIT(0)
+#define SGMII_REG_STATUS_AUTONEG        BIT(2)
+#define SGMII_REG_CONTROL_AUTONEG       BIT(0)
+#define SGMII_REG_CONTROL_MASTER        BIT(5)
+#define	SGMII_REG_MR_ADV_ENABLE         BIT(0)
+#define	SGMII_REG_MR_ADV_LINK           BIT(15)
+#define	SGMII_REG_MR_ADV_FULL_DUPLEX    BIT(12)
+#define SGMII_REG_MR_ADV_GIG_MODE       BIT(11)
+
+#define SGMII_LINK_MAC_MAC_AUTONEG      0
+#define SGMII_LINK_MAC_PHY              1
+#define SGMII_LINK_MAC_MAC_FORCED       2
+#define SGMII_LINK_MAC_FIBER            3
+#define SGMII_LINK_MAC_PHY_FORCED       4
+
+#define TARGET_SGMII_BASE              KS2_PASS_BASE + 0x00090100
+#define TARGET_SGMII_BASE_ADDRESSES    {KS2_PASS_BASE + 0x00090100, \
+					KS2_PASS_BASE + 0x00090200, \
+					KS2_PASS_BASE + 0x00090400, \
+					KS2_PASS_BASE + 0x00090500}
+
+#define SGMII_OFFSET(x)	((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
+
+/*
+ * SGMII registers
+ */
+#define SGMII_IDVER_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x)   (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x)      (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x)   (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x)    (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x)   (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
+
+#define DEVICE_EMACSL_BASE(x)      (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
+#define DEVICE_N_GMACSL_PORTS           4
+#define DEVICE_EMACSL_RESET_POLL_COUNT  100
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR                 (KS2_PASS_BASE + 0x604)
+
+#ifdef CONFIG_SOC_K2HK
+#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI      0x06060606
+#endif
+
+#define hw_config_streaming_switch() \
+	DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, \
+		       DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI);
+
+/* EMAC MDIO Registers Structure */
+struct mdio_regs {
+	dv_reg		version;
+	dv_reg		control;
+	dv_reg		alive;
+	dv_reg		link;
+	dv_reg		linkintraw;
+	dv_reg		linkintmasked;
+	u_int8_t	rsvd0[8];
+	dv_reg		userintraw;
+	dv_reg		userintmasked;
+	dv_reg		userintmaskset;
+	dv_reg		userintmaskclear;
+	u_int8_t	rsvd1[80];
+	dv_reg		useraccess0;
+	dv_reg		userphysel0;
+	dv_reg		useraccess1;
+	dv_reg		userphysel1;
+};
+
+/* Ethernet MAC Registers Structure */
+struct emac_regs {
+	dv_reg		idver;
+	dv_reg		maccontrol;
+	dv_reg		macstatus;
+	dv_reg		soft_reset;
+	dv_reg		rx_maxlen;
+	u32		rsvd0;
+	dv_reg		rx_pause;
+	dv_reg		tx_pause;
+	dv_reg		emcontrol;
+	dv_reg		pri_map;
+	u32		rsvd1[6];
+};
+
+#define SGMII_ACCESS(port, reg) \
+	*((volatile unsigned int *)(sgmiis[port] + reg))
+
+struct eth_priv_t {
+	char	int_name[32];
+	int	rx_flow;
+	int	phy_addr;
+	int	slave_port;
+	int	sgmii_link_type;
+};
+
+extern struct eth_priv_t eth_priv_cfg[];
+
+int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
+void sgmii_serdes_setup_156p25mhz(void);
+void sgmii_serdes_shutdown(void);
+
+#endif  /* _EMAC_DEFS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emif_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emif_defs.h
new file mode 100644
index 000000000..a3378aa30
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/emif_defs.h
@@ -0,0 +1,73 @@
+/*
+ * emif definitions to re-use davinci emif driver on Keystone2
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _EMIF_DEFS_H_
+#define _EMIF_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+struct davinci_emif_regs {
+	uint32_t	ercsr;
+	uint32_t	awccr;
+	uint32_t	sdbcr;
+	uint32_t	sdrcr;
+	uint32_t	abncr[4];
+	uint32_t	sdtimr;
+	uint32_t	ddrsr;
+	uint32_t	ddrphycr;
+	uint32_t	ddrphysr;
+	uint32_t	totar;
+	uint32_t	totactr;
+	uint32_t	ddrphyid_rev;
+	uint32_t	sdsretr;
+	uint32_t	eirr;
+	uint32_t	eimr;
+	uint32_t	eimsr;
+	uint32_t	eimcr;
+	uint32_t	ioctrlr;
+	uint32_t	iostatr;
+	uint32_t	rsvd0;
+	uint32_t	one_nand_cr;
+	uint32_t	nandfcr;
+	uint32_t	nandfsr;
+	uint32_t	rsvd1[2];
+	uint32_t	nandfecc[4];
+	uint32_t	rsvd2[15];
+	uint32_t	nand4biteccload;
+	uint32_t	nand4bitecc[4];
+	uint32_t	nanderradd1;
+	uint32_t	nanderradd2;
+	uint32_t	nanderrval1;
+	uint32_t	nanderrval2;
+};
+
+#define davinci_emif_regs \
+	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
+
+#define DAVINCI_NANDFCR_NAND_ENABLE(n)			(1 << ((n) - 2))
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK		(3 << 4)
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n)			(((n) - 2) << 4)
+#define DAVINCI_NANDFCR_1BIT_ECC_START(n)		(1 << (8 + ((n) - 2)))
+#define DAVINCI_NANDFCR_4BIT_ECC_START			(1 << 12)
+#define DAVINCI_NANDFCR_4BIT_CALC_START			(1 << 13)
+
+/* Chip Select setup */
+#define DAVINCI_ABCR_STROBE_SELECT			(1 << 31)
+#define DAVINCI_ABCR_EXT_WAIT				(1 << 30)
+#define DAVINCI_ABCR_WSETUP(n)				((n) << 26)
+#define DAVINCI_ABCR_WSTROBE(n)				((n) << 20)
+#define DAVINCI_ABCR_WHOLD(n)				((n) << 17)
+#define DAVINCI_ABCR_RSETUP(n)				((n) << 13)
+#define DAVINCI_ABCR_RSTROBE(n)				((n) << 7)
+#define DAVINCI_ABCR_RHOLD(n)				((n) << 4)
+#define DAVINCI_ABCR_TA(n)				((n) << 2)
+#define DAVINCI_ABCR_ASIZE_16BIT			1
+#define DAVINCI_ABCR_ASIZE_8BIT				0
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
new file mode 100644
index 000000000..50ff13a3b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -0,0 +1,150 @@
+/*
+ * K2HK: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_K2HK_H
+#define __ASM_ARCH_HARDWARE_K2HK_H
+
+#define K2HK_ASYNC_EMIF_CNTRL_BASE      0x21000a00
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE   K2HK_ASYNC_EMIF_CNTRL_BASE
+#define K2HK_ASYNC_EMIF_DATA_CE0_BASE   0x30000000
+#define K2HK_ASYNC_EMIF_DATA_CE1_BASE   0x34000000
+#define K2HK_ASYNC_EMIF_DATA_CE2_BASE   0x38000000
+#define K2HK_ASYNC_EMIF_DATA_CE3_BASE   0x3c000000
+
+#define K2HK_PLL_CNTRL_BASE             0x02310000
+#define CLOCK_BASE                      K2HK_PLL_CNTRL_BASE
+#define KS2_RSTCTRL                     (K2HK_PLL_CNTRL_BASE + 0xe8)
+#define KS2_RSTCTRL_KEY                 0x5a69
+#define KS2_RSTCTRL_MASK                0xffff0000
+#define KS2_RSTCTRL_SWRST               0xfffe0000
+
+#define K2HK_PSC_BASE                   0x02350000
+#define KS2_DEVICE_STATE_CTRL_BASE      0x02620000
+#define JTAG_ID_REG                     (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
+#define K2HK_DEVSTAT                    (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+
+#define K2HK_MISC_CTRL                  (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
+
+#define ARM_PLL_EN                      BIT(13)
+
+#define K2HK_SPI0_BASE                  0x21000400
+#define K2HK_SPI1_BASE                  0x21000600
+#define K2HK_SPI2_BASE                  0x21000800
+#define K2HK_SPI_BASE                   K2HK_SPI0_BASE
+
+/* Chip configuration unlock codes and registers */
+#define KEYSTONE_KICK0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
+#define KEYSTONE_KICK1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
+#define KEYSTONE_KICK0_MAGIC           0x83e70b13
+#define KEYSTONE_KICK1_MAGIC           0x95a4f1e0
+
+/* PA SS Registers */
+#define KS2_PASS_BASE                  0x02000000
+
+/* PLL control registers */
+#define K2HK_MAINPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
+#define K2HK_MAINPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
+#define K2HK_PASSPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
+#define K2HK_PASSPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
+#define K2HK_DDR3APLLCTL0              (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
+#define K2HK_DDR3APLLCTL1              (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define K2HK_DDR3BPLLCTL0              (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define K2HK_DDR3BPLLCTL1              (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
+#define K2HK_ARMPLLCTL0	               (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
+#define K2HK_ARMPLLCTL1                (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+
+/* Power and Sleep Controller (PSC) Domains */
+#define K2HK_LPSC_MOD                  0
+#define K2HK_LPSC_DUMMY1               1
+#define K2HK_LPSC_USB                  2
+#define K2HK_LPSC_EMIF25_SPI           3
+#define K2HK_LPSC_TSIP                 4
+#define K2HK_LPSC_DEBUGSS_TRC          5
+#define K2HK_LPSC_TETB_TRC             6
+#define K2HK_LPSC_PKTPROC              7
+#define KS2_LPSC_PA                    K2HK_LPSC_PKTPROC
+#define K2HK_LPSC_SGMII                8
+#define KS2_LPSC_CPGMAC                K2HK_LPSC_SGMII
+#define K2HK_LPSC_CRYPTO               9
+#define K2HK_LPSC_PCIE                 10
+#define K2HK_LPSC_SRIO                 11
+#define K2HK_LPSC_VUSR0                12
+#define K2HK_LPSC_CHIP_SRSS            13
+#define K2HK_LPSC_MSMC                 14
+#define K2HK_LPSC_GEM_0                15
+#define K2HK_LPSC_GEM_1                16
+#define K2HK_LPSC_GEM_2                17
+#define K2HK_LPSC_GEM_3                18
+#define K2HK_LPSC_GEM_4                19
+#define K2HK_LPSC_GEM_5                20
+#define K2HK_LPSC_GEM_6                21
+#define K2HK_LPSC_GEM_7                22
+#define K2HK_LPSC_EMIF4F_DDR3A         23
+#define K2HK_LPSC_EMIF4F_DDR3B         24
+#define K2HK_LPSC_TAC                  25
+#define K2HK_LPSC_RAC                  26
+#define K2HK_LPSC_RAC_1                27
+#define K2HK_LPSC_FFTC_A               28
+#define K2HK_LPSC_FFTC_B               29
+#define K2HK_LPSC_FFTC_C               30
+#define K2HK_LPSC_FFTC_D               31
+#define K2HK_LPSC_FFTC_E               32
+#define K2HK_LPSC_FFTC_F               33
+#define K2HK_LPSC_AI2                  34
+#define K2HK_LPSC_TCP3D_0              35
+#define K2HK_LPSC_TCP3D_1              36
+#define K2HK_LPSC_TCP3D_2              37
+#define K2HK_LPSC_TCP3D_3              38
+#define K2HK_LPSC_VCP2X4_A             39
+#define K2HK_LPSC_CP2X4_B              40
+#define K2HK_LPSC_VCP2X4_C             41
+#define K2HK_LPSC_VCP2X4_D             42
+#define K2HK_LPSC_VCP2X4_E             43
+#define K2HK_LPSC_VCP2X4_F             44
+#define K2HK_LPSC_VCP2X4_G             45
+#define K2HK_LPSC_VCP2X4_H             46
+#define K2HK_LPSC_BCP                  47
+#define K2HK_LPSC_DXB                  48
+#define K2HK_LPSC_VUSR1                49
+#define K2HK_LPSC_XGE                  50
+#define K2HK_LPSC_ARM_SREFLEX          51
+#define K2HK_LPSC_TETRIS               52
+
+#define K2HK_UART0_BASE                0x02530c00
+
+/* DDR3A definitions */
+#define K2HK_DDR3A_EMIF_CTRL_BASE      0x21010000
+#define K2HK_DDR3A_EMIF_DATA_BASE      0x80000000
+#define K2HK_DDR3A_DDRPHYC             0x02329000
+/* DDR3B definitions */
+#define K2HK_DDR3B_EMIF_CTRL_BASE      0x21020000
+#define K2HK_DDR3B_EMIF_DATA_BASE      0x60000000
+#define K2HK_DDR3B_DDRPHYC             0x02328000
+
+/* Queue manager */
+#define DEVICE_QM_MANAGER_BASE         0x02a02000
+#define DEVICE_QM_DESC_SETUP_BASE      0x02a03000
+#define DEVICE_QM_MANAGER_QUEUES_BASE  0x02a80000
+#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
+#define DEVICE_QM_QUEUE_STATUS_BASE    0x02a40000
+#define DEVICE_QM_NUM_LINKRAMS         2
+#define DEVICE_QM_NUM_MEMREGIONS       20
+
+#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE  0x02004000
+#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
+#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE	0x02004800
+#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE	0x02005000
+
+#define DEVICE_PA_CDMA_RX_NUM_CHANNELS  24
+#define DEVICE_PA_CDMA_RX_NUM_FLOWS     32
+#define DEVICE_PA_CDMA_TX_NUM_CHANNELS  9
+
+/* MSMC control */
+#define K2HK_MSMC_CTRL_BASE             0x0bc00000
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware.h
new file mode 100644
index 000000000..a305a0cc0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/hardware.h
@@ -0,0 +1,175 @@
+/*
+ * Keystone2: Common SoC definitions, structures etc.
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <config.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+
+#define	REG(addr)        (*(volatile unsigned int *)(addr))
+#define REG_P(addr)      ((volatile unsigned int *)(addr))
+
+typedef volatile unsigned int   dv_reg;
+typedef volatile unsigned int   *dv_reg_p;
+
+#define ASYNC_EMIF_NUM_CS               4
+#define ASYNC_EMIF_MODE_NOR             0
+#define ASYNC_EMIF_MODE_NAND            1
+#define ASYNC_EMIF_MODE_ONENAND         2
+#define ASYNC_EMIF_PRESERVE             -1
+
+struct async_emif_config {
+	unsigned mode;
+	unsigned select_strobe;
+	unsigned extend_wait;
+	unsigned wr_setup;
+	unsigned wr_strobe;
+	unsigned wr_hold;
+	unsigned rd_setup;
+	unsigned rd_strobe;
+	unsigned rd_hold;
+	unsigned turn_around;
+	enum {
+		ASYNC_EMIF_8	= 0,
+		ASYNC_EMIF_16	= 1,
+		ASYNC_EMIF_32	= 2,
+	} width;
+};
+
+void init_async_emif(int num_cs, struct async_emif_config *config);
+
+struct ddr3_phy_config {
+	unsigned int pllcr;
+	unsigned int pgcr1_mask;
+	unsigned int pgcr1_val;
+	unsigned int ptr0;
+	unsigned int ptr1;
+	unsigned int ptr2;
+	unsigned int ptr3;
+	unsigned int ptr4;
+	unsigned int dcr_mask;
+	unsigned int dcr_val;
+	unsigned int dtpr0;
+	unsigned int dtpr1;
+	unsigned int dtpr2;
+	unsigned int mr0;
+	unsigned int mr1;
+	unsigned int mr2;
+	unsigned int dtcr;
+	unsigned int pgcr2;
+	unsigned int zq0cr1;
+	unsigned int zq1cr1;
+	unsigned int zq2cr1;
+	unsigned int pir_v1;
+	unsigned int pir_v2;
+};
+
+struct ddr3_emif_config {
+	unsigned int sdcfg;
+	unsigned int sdtim1;
+	unsigned int sdtim2;
+	unsigned int sdtim3;
+	unsigned int sdtim4;
+	unsigned int zqcfg;
+	unsigned int sdrfc;
+};
+
+#endif
+
+#define		BIT(x)	(1 << (x))
+
+#define KS2_DDRPHY_PIR_OFFSET           0x04
+#define KS2_DDRPHY_PGCR0_OFFSET         0x08
+#define KS2_DDRPHY_PGCR1_OFFSET         0x0C
+#define KS2_DDRPHY_PGSR0_OFFSET         0x10
+#define KS2_DDRPHY_PGSR1_OFFSET         0x14
+#define KS2_DDRPHY_PLLCR_OFFSET         0x18
+#define KS2_DDRPHY_PTR0_OFFSET          0x1C
+#define KS2_DDRPHY_PTR1_OFFSET          0x20
+#define KS2_DDRPHY_PTR2_OFFSET          0x24
+#define KS2_DDRPHY_PTR3_OFFSET          0x28
+#define KS2_DDRPHY_PTR4_OFFSET          0x2C
+#define KS2_DDRPHY_DCR_OFFSET           0x44
+
+#define KS2_DDRPHY_DTPR0_OFFSET         0x48
+#define KS2_DDRPHY_DTPR1_OFFSET         0x4C
+#define KS2_DDRPHY_DTPR2_OFFSET         0x50
+
+#define KS2_DDRPHY_MR0_OFFSET           0x54
+#define KS2_DDRPHY_MR1_OFFSET           0x58
+#define KS2_DDRPHY_MR2_OFFSET           0x5C
+#define KS2_DDRPHY_DTCR_OFFSET          0x68
+#define KS2_DDRPHY_PGCR2_OFFSET         0x8C
+
+#define KS2_DDRPHY_ZQ0CR1_OFFSET        0x184
+#define KS2_DDRPHY_ZQ1CR1_OFFSET        0x194
+#define KS2_DDRPHY_ZQ2CR1_OFFSET        0x1A4
+#define KS2_DDRPHY_ZQ3CR1_OFFSET        0x1B4
+
+#define KS2_DDRPHY_DATX8_8_OFFSET       0x3C0
+
+#define IODDRM_MASK                     0x00000180
+#define ZCKSEL_MASK                     0x01800000
+#define CL_MASK                         0x00000072
+#define WR_MASK                         0x00000E00
+#define BL_MASK                         0x00000003
+#define RRMODE_MASK                     0x00040000
+#define UDIMM_MASK                      0x20000000
+#define BYTEMASK_MASK                   0x0003FC00
+#define MPRDQ_MASK                      0x00000080
+#define PDQ_MASK                        0x00000070
+#define NOSRA_MASK                      0x08000000
+#define ECC_MASK                        0x00000001
+
+#define KS2_DDR3_MIDR_OFFSET            0x00
+#define KS2_DDR3_STATUS_OFFSET          0x04
+#define KS2_DDR3_SDCFG_OFFSET           0x08
+#define KS2_DDR3_SDRFC_OFFSET           0x10
+#define KS2_DDR3_SDTIM1_OFFSET          0x18
+#define KS2_DDR3_SDTIM2_OFFSET          0x1C
+#define KS2_DDR3_SDTIM3_OFFSET          0x20
+#define KS2_DDR3_SDTIM4_OFFSET          0x28
+#define KS2_DDR3_PMCTL_OFFSET           0x38
+#define KS2_DDR3_ZQCFG_OFFSET           0xC8
+
+#ifdef CONFIG_SOC_K2HK
+#include <asm/arch/hardware-k2hk.h>
+#endif
+
+#ifndef __ASSEMBLY__
+static inline int cpu_is_k2hk(void)
+{
+	unsigned int jtag_id	= __raw_readl(JTAG_ID_REG);
+	unsigned int part_no	= (jtag_id >> 12) & 0xffff;
+
+	return (part_no == 0xb981) ? 1 : 0;
+}
+
+static inline int cpu_revision(void)
+{
+	unsigned int jtag_id	= __raw_readl(JTAG_ID_REG);
+	unsigned int rev	= (jtag_id >> 28) & 0xf;
+
+	return rev;
+}
+
+void share_all_segments(int priv_id);
+int cpu_to_bus(u32 *ptr, u32 length);
+void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
+void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+void init_ddr3(void);
+void sdelay(unsigned long);
+
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/i2c_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/i2c_defs.h
new file mode 100644
index 000000000..d4256526c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/i2c_defs.h
@@ -0,0 +1,17 @@
+/*
+ * keystone: i2c driver definitions
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _I2C_DEFS_H_
+#define _I2C_DEFS_H_
+
+#define I2C0_BASE		0x02530000
+#define I2C1_BASE		0x02530400
+#define I2C2_BASE		0x02530800
+#define I2C_BASE		I2C0_BASE
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/keystone_nav.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/keystone_nav.h
new file mode 100644
index 000000000..ab81eaf1f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/keystone_nav.h
@@ -0,0 +1,193 @@
+/*
+ * Multicore Navigator definitions
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _KEYSTONE_NAV_H_
+#define _KEYSTONE_NAV_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+enum soc_type_t {
+	k2hk
+};
+
+#define QM_OK                    0
+#define QM_ERR                  -1
+#define QM_DESC_TYPE_HOST        0
+#define QM_DESC_PSINFO_IN_DESCR  0
+#define QM_DESC_DEFAULT_DESCINFO    (QM_DESC_TYPE_HOST << 30) | \
+					(QM_DESC_PSINFO_IN_DESCR << 22)
+
+/* Packet Info */
+#define QM_DESC_PINFO_EPIB              1
+#define QM_DESC_PINFO_RETURN_OWN        1
+#define QM_DESC_DEFAULT_PINFO           (QM_DESC_PINFO_EPIB << 31) | \
+					(QM_DESC_PINFO_RETURN_OWN << 15)
+
+struct qm_cfg_reg {
+	u32	revision;
+	u32	__pad1;
+	u32	divert;
+	u32	link_ram_base0;
+	u32	link_ram_size0;
+	u32	link_ram_base1;
+	u32	link_ram_size1;
+	u32	link_ram_base2;
+	u32	starvation[0];
+};
+
+struct	descr_mem_setup_reg {
+	u32	base_addr;
+	u32	start_idx;
+	u32	desc_reg_size;
+	u32	_res0;
+};
+
+struct qm_reg_queue {
+	u32	entry_count;
+	u32	byte_count;
+	u32	packet_size;
+	u32	ptr_size_thresh;
+};
+
+struct qm_config {
+	/* QM module addresses */
+	u32	stat_cfg;	/* status and config		*/
+	struct qm_reg_queue *queue;	/* management region	*/
+	u32	mngr_vbusm;	/* management region (VBUSM)	*/
+	u32	i_lram;		/* internal linking RAM		*/
+	struct qm_reg_queue *proxy;
+	u32	status_ram;
+	struct qm_cfg_reg *mngr_cfg;
+				/* Queue manager config region	*/
+	u32	intd_cfg;	/* QMSS INTD config region	*/
+	struct	descr_mem_setup_reg *desc_mem;
+				/* descritor memory setup region*/
+	u32	region_num;
+	u32	pdsp_cmd;	/* PDSP1 command interface	*/
+	u32	pdsp_ctl;	/* PDSP1 control registers	*/
+	u32	pdsp_iram;
+	/* QM configuration parameters */
+
+	u32	qpool_num;	/* */
+};
+
+struct qm_host_desc {
+	u32 desc_info;
+	u32 tag_info;
+	u32 packet_info;
+	u32 buff_len;
+	u32 buff_ptr;
+	u32 next_bdptr;
+	u32 orig_buff_len;
+	u32 orig_buff_ptr;
+	u32 timestamp;
+	u32 swinfo[3];
+	u32 ps_data[20];
+};
+
+#define HDESC_NUM        256
+
+int	qm_init(void);
+void	qm_close(void);
+void	qm_push(struct qm_host_desc *hd, u32 qnum);
+struct qm_host_desc *qm_pop(u32 qnum);
+
+void	qm_buff_push(struct qm_host_desc *hd, u32 qnum,
+		     void *buff_ptr, u32 buff_len);
+
+struct	qm_host_desc *qm_pop_from_free_pool(void);
+void	queue_close(u32 qnum);
+
+/*
+ * DMA API
+ */
+#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \
+				     psloc, sopoff, qmgr, qnum) \
+	(((einfo & 1) << 30)  | \
+	 ((psinfo & 1) << 29) | \
+	 ((rxerr & 1) << 28)  | \
+	 ((desc & 3) << 26)   | \
+	 ((psloc & 1) << 25)  | \
+	 ((sopoff & 0x1ff) << 16) | \
+	 ((qmgr & 3) << 12)   | \
+	 ((qnum & 0xfff) << 0))
+
+#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \
+	(((fd0qm & 3) << 28)  | \
+	 ((fd0qnum & 0xfff) << 16) | \
+	 ((fd1qm & 3) << 12)  | \
+	 ((fd1qnum & 0xfff) <<  0))
+
+#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31)
+#define CPDMA_CHAN_A_TDOWN  (1 << 30)
+#define TDOWN_TIMEOUT_COUNT  100
+
+struct global_ctl_regs {
+	u32	revision;
+	u32	perf_control;
+	u32	emulation_control;
+	u32	priority_control;
+	u32	qm_base_addr[4];
+};
+
+struct tx_chan_regs {
+	u32	cfg_a;
+	u32	cfg_b;
+	u32	res[6];
+};
+
+struct rx_chan_regs {
+	u32	cfg_a;
+	u32	res[7];
+};
+
+struct rx_flow_regs {
+	u32	control;
+	u32	tags;
+	u32	tag_sel;
+	u32	fdq_sel[2];
+	u32	thresh[3];
+};
+
+struct pktdma_cfg {
+	struct global_ctl_regs	*global;
+	struct tx_chan_regs	*tx_ch;
+	u32			tx_ch_num;
+	struct rx_chan_regs	*rx_ch;
+	u32			rx_ch_num;
+	u32			*tx_sched;
+	struct rx_flow_regs	*rx_flows;
+	u32			rx_flow_num;
+
+	u32			rx_free_q;
+	u32			rx_rcv_q;
+	u32			tx_snd_q;
+
+	u32			rx_flow; /* flow that is used for RX */
+};
+
+/*
+ * packet dma user allocates memory for rx buffers
+ * and describe it in the following structure
+ */
+struct rx_buff_desc {
+	u8	*buff_ptr;
+	u32	num_buffs;
+	u32	buff_len;
+	u32	rx_flow;
+};
+
+int netcp_close(void);
+int netcp_init(struct rx_buff_desc *rx_buffers);
+int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2);
+void *netcp_recv(u32 **pkt, int *num_bytes);
+void netcp_release_rxhd(void *hd);
+
+#endif  /* _KEYSTONE_NAV_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/nand_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/nand_defs.h
new file mode 100644
index 000000000..58417dbc0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/nand_defs.h
@@ -0,0 +1,23 @@
+/*
+ * nand driver definitions to re-use davinci nand driver on Keystone2
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <linux/mtd/nand.h>
+
+#define MASK_CLE         0x4000
+#define	MASK_ALE         0x2000
+
+#define NAND_READ_START  0x00
+#define NAND_READ_END    0x30
+#define NAND_STATUS      0x70
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/psc_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/psc_defs.h
new file mode 100644
index 000000000..70d22cf21
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/psc_defs.h
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef _PSC_DEFS_H_
+#define _PSC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+/*
+ * FILE PURPOSE: Local Power Sleep Controller definitions
+ *
+ * FILE NAME: psc_defs.h
+ *
+ * DESCRIPTION: Provides local definitions for the power saver controller
+ *
+ */
+
+/* Register offsets */
+#define PSC_REG_PTCMD           0x120
+#define PSC_REG_PSTAT	        0x128
+#define PSC_REG_PDSTAT(x)       (0x200 + (4 * (x)))
+#define PSC_REG_PDCTL(x)        (0x300 + (4 * (x)))
+#define PSC_REG_MDCFG(x)        (0x600 + (4 * (x)))
+#define PSC_REG_MDSTAT(x)       (0x800 + (4 * (x)))
+#define PSC_REG_MDCTL(x)        (0xa00 + (4 * (x)))
+
+#define BOOTBITMASK(x, y)     ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
+				  (u32)1)) << ((u32)y)))
+
+#define BOOT_READ_BITFIELD(z, x, y)    (((u32)z) & BOOTBITMASK(x, y)) >> (y)
+#define BOOT_SET_BITFIELD(z, f, x, y)  (((u32)z) & ~BOOTBITMASK(x, y)) | \
+					 ((((u32)f) << (y)) & BOOTBITMASK(x, y))
+
+/* PDCTL */
+#define PSC_REG_PDCTL_SET_NEXT(x, y)        BOOT_SET_BITFIELD((x), (y), 0, 0)
+#define PSC_REG_PDCTL_SET_PDMODE(x, y)      BOOT_SET_BITFIELD((x), (y), 15, 12)
+
+/* PDSTAT */
+#define PSC_REG_PDSTAT_GET_STATE(x)         BOOT_READ_BITFIELD((x), 4, 0)
+
+/* MDCFG */
+#define PSC_REG_MDCFG_GET_PD(x)             BOOT_READ_BITFIELD((x), 20, 16)
+#define PSC_REG_MDCFG_GET_RESET_ISO(x)      BOOT_READ_BITFIELD((x), 14, 14)
+
+/* MDCTL */
+#define PSC_REG_MDCTL_SET_NEXT(x, y)        BOOT_SET_BITFIELD((x), (y), 4, 0)
+#define PSC_REG_MDCTL_SET_LRSTZ(x, y)       BOOT_SET_BITFIELD((x), (y), 8, 8)
+#define PSC_REG_MDCTL_GET_LRSTZ(x)          BOOT_READ_BITFIELD((x), 8, 8)
+#define PSC_REG_MDCTL_SET_RESET_ISO(x, y)   BOOT_SET_BITFIELD((x), (y), \
+								  12, 12)
+
+/* MDSTAT */
+#define PSC_REG_MDSTAT_GET_STATUS(x)        BOOT_READ_BITFIELD((x), 5, 0)
+#define PSC_REG_MDSTAT_GET_LRSTZ(x)         BOOT_READ_BITFIELD((x), 8, 8)
+#define PSC_REG_MDSTAT_GET_LRSTDONE(x)      BOOT_READ_BITFIELD((x), 9, 9)
+
+/* PDCTL states */
+#define PSC_REG_VAL_PDCTL_NEXT_ON           1
+#define PSC_REG_VAL_PDCTL_NEXT_OFF          0
+
+#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP      0
+
+/* MDCTL states */
+#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE     0
+#define PSC_REG_VAL_MDCTL_NEXT_OFF              2
+#define PSC_REG_VAL_MDCTL_NEXT_ON               3
+
+/* MDSTAT states */
+#define PSC_REG_VAL_MDSTAT_STATE_ON             3
+#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
+#define PSC_REG_VAL_MDSTAT_STATE_OFF            2
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1       0x20
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2       0x21
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3       0x22
+
+/*
+ * Timeout limit on checking PTSTAT. This is the number of times the
+ * wait function will be called before giving up.
+ */
+#define PSC_PTSTAT_TIMEOUT_LIMIT    100
+
+u32 psc_get_domain_num(u32 mod_num);
+int psc_enable_module(u32 mod_num);
+int psc_disable_module(u32 mod_num);
+int psc_disable_domain(u32 domain_num);
+
+#endif /* _PSC_DEFS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/spl.h
new file mode 100644
index 000000000..7012ea7ff
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-keystone/spl.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2012-2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_SPL_H_
+
+#define BOOT_DEVICE_SPI        2
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/config.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/config.h
new file mode 100644
index 000000000..7a688e46b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/config.h
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for Kirkwood platform
+ */
+
+#ifndef _KW_CONFIG_H
+#define _KW_CONFIG_H
+
+#if defined (CONFIG_KW88F6281)
+#include <asm/arch/kw88f6281.h>
+#elif defined (CONFIG_KW88F6192)
+#include <asm/arch/kw88f6192.h>
+#else
+#error "SOC Name not defined"
+#endif /* CONFIG_KW88F6281 */
+
+#include <asm/arch/kirkwood.h>
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+				/* default Dcache Line length for kirkwood */
+#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define	CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Kirkwood has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#define CONFIG_I2C_MVTWSI_BASE	KW_TWSI_BASE
+#define MV_UART_CONSOLE_BASE	KW_UART0_BASE
+#define MV_SATA_BASE		KW_SATA_BASE
+#define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
+#define MV_SATA_PORT1_OFFSET	KW_SATA_PORT1_OFFSET
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL		1
+#endif
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI			1
+#define CONFIG_KIRKWOOD_SPI		1
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS		0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS		0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ		50000000
+#endif
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * IDE Support on SATA ports
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_CMD_EXT2
+#define CONFIG_MVSATA_IDE
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#ifndef CONFIG_SYS_I2C_SOFT
+#define CONFIG_I2C_MVTWSI
+#endif
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#endif /* _KW_CONFIG_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/cpu.h
new file mode 100644
index 000000000..97daa403c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _KWCPU_H
+#define _KWCPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+			| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
+
+#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
+		((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
+
+#define KW_REG_PCIE_DEVID		(KW_REG_PCIE_BASE + 0x00)
+#define KW_REG_PCIE_REVID		(KW_REG_PCIE_BASE + 0x08)
+#define KW_REG_DEVICE_ID		(KW_MPP_BASE + 0x34)
+#define KW_REG_SYSRST_CNT		(KW_MPP_BASE + 0x50)
+#define SYSRST_CNT_1SEC_VAL		(25*1000000)
+#define KW_REG_MPP_OUT_DRV_REG		(KW_MPP_BASE + 0xE0)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+	BANK2,
+	BANK3
+};
+
+enum kwcpu_winen {
+	KWCPU_WIN_DISABLE,
+	KWCPU_WIN_ENABLE
+};
+
+enum kwcpu_target {
+	KWCPU_TARGET_RESERVED,
+	KWCPU_TARGET_MEMORY,
+	KWCPU_TARGET_1RESERVED,
+	KWCPU_TARGET_SASRAM,
+	KWCPU_TARGET_PCIE
+};
+
+enum kwcpu_attrib {
+	KWCPU_ATTR_SASRAM = 0x01,
+	KWCPU_ATTR_DRAM_CS0 = 0x0e,
+	KWCPU_ATTR_DRAM_CS1 = 0x0d,
+	KWCPU_ATTR_DRAM_CS2 = 0x0b,
+	KWCPU_ATTR_DRAM_CS3 = 0x07,
+	KWCPU_ATTR_NANDFLASH = 0x2f,
+	KWCPU_ATTR_SPIFLASH = 0x1e,
+	KWCPU_ATTR_BOOTROM = 0x1d,
+	KWCPU_ATTR_PCIE_IO = 0xe0,
+	KWCPU_ATTR_PCIE_MEM = 0xe8
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define KW_DEFADR_PCI_MEM	0x90000000
+#define KW_DEFADR_PCI_IO	0xC0000000
+#define KW_DEFADR_PCI_IO_REMAP	0xC0000000
+#define KW_DEFADR_SASRAM	0xC8010000
+#define KW_DEFADR_NANDF		0xD8000000
+#define KW_DEFADR_SPIF		0xE8000000
+#define KW_DEFADR_BOOTROM	0xF8000000
+
+/*
+ * read feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+	unsigned int val;
+	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
+			(val)::"cc");
+	return val;
+}
+
+/*
+ * write feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
+			(val):"cc");
+	isb();
+}
+
+/*
+ * MBus-L to Mbus Bridge Registers
+ * Ref: Datasheet sec:A.3
+ */
+struct kwwin_registers {
+	u32 ctrl;
+	u32 base;
+	u32 remap_lo;
+	u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ * Ref: Datasheet sec:A.3.2
+ */
+struct kwcpu_registers {
+	u32 config;	/*0x20100 */
+	u32 ctrl_stat;	/*0x20104 */
+	u32 rstoutn_mask; /* 0x20108 */
+	u32 sys_soft_rst; /* 0x2010C */
+	u32 ahb_mbus_cause_irq; /* 0x20110 */
+	u32 ahb_mbus_mask_irq; /* 0x20114 */
+	u32 pad1[2];
+	u32 ftdll_config; /* 0x20120 */
+	u32 pad2;
+	u32 l2_cfg;	/* 0x20128 */
+};
+
+/*
+ * GPIO Registers
+ * Ref: Datasheet sec:A.19
+ */
+struct kwgpio_registers {
+	u32 dout;
+	u32 oe;
+	u32 blink_en;
+	u32 din_pol;
+	u32 din;
+	u32 irq_cause;
+	u32 irq_mask;
+	u32 irq_level;
+};
+
+/*
+ * functions
+ */
+unsigned char get_random_hex(void);
+unsigned int kw_sdram_bar(enum memory_bank bank);
+unsigned int kw_sdram_bs(enum memory_bank bank);
+void kw_sdram_size_adjust(enum memory_bank bank);
+int kw_config_adr_windows(void);
+void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
+		unsigned int gpp0_oe, unsigned int gpp1_oe);
+int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
+		unsigned int mpp16_23, unsigned int mpp24_31,
+		unsigned int mpp32_39, unsigned int mpp40_47,
+		unsigned int mpp48_55);
+unsigned int kw_winctrl_calcsize(unsigned int sizeval);
+#endif /* __ASSEMBLY__ */
+#endif /* _KWCPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/gpio.h
new file mode 100644
index 000000000..5f4d78608
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/gpio.h
@@ -0,0 +1,49 @@
+/*
+ * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed kernel level irq handling. Took some macros from kernel to
+ * allow build.
+ *
+ * Dieter Kiermaier dk-arm-linux@gmx.de
+ */
+
+#ifndef __KIRKWOOD_GPIO_H
+#define __KIRKWOOD_GPIO_H
+
+/* got from kernel include/linux/bitops.h */
+#define BITS_PER_BYTE 8
+#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+
+#define GPIO_MAX		50
+#define GPIO_OFF(pin)		(((pin) >> 5) ? 0x0040 : 0x0000)
+#define GPIO_OUT(pin)		(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
+#define GPIO_IO_CONF(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
+#define GPIO_BLINK_EN(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
+#define GPIO_IN_POL(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
+#define GPIO_DATA_IN(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
+#define GPIO_EDGE_CAUSE(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
+#define GPIO_EDGE_MASK(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
+#define GPIO_LEVEL_MASK(pin)	(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
+
+/*
+ * Kirkwood-specific GPIO API
+ */
+
+void kw_gpio_set_valid(unsigned pin, int mode);
+int kw_gpio_is_valid(unsigned pin, int mode);
+int kw_gpio_direction_input(unsigned pin);
+int kw_gpio_direction_output(unsigned pin, int value);
+int kw_gpio_get_value(unsigned pin);
+void kw_gpio_set_value(unsigned pin, int value);
+void kw_gpio_set_blink(unsigned pin, int blink);
+void kw_gpio_set_unused(unsigned pin);
+
+#define GPIO_INPUT_OK		(1 << 0)
+#define GPIO_OUTPUT_OK		(1 << 1)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kirkwood.h
new file mode 100644
index 000000000..bc207f536
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for the Marvell's Feroceon CPU core.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_KIRKWOOD_H
+#define _ASM_ARCH_KIRKWOOD_H
+
+#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131)
+
+/* SOC specific definations */
+#define INTREG_BASE			0xd0000000
+#define KW_REGISTER(x)			(KW_REGS_PHY_BASE + x)
+#define KW_OFFSET_REG			(INTREG_BASE + 0x20080)
+
+/* undocumented registers */
+#define KW_REG_UNDOC_0x1470		(KW_REGISTER(0x1470))
+#define KW_REG_UNDOC_0x1478		(KW_REGISTER(0x1478))
+
+#define KW_TWSI_BASE			(KW_REGISTER(0x11000))
+#define KW_UART0_BASE			(KW_REGISTER(0x12000))
+#define KW_UART1_BASE			(KW_REGISTER(0x12100))
+#define KW_MPP_BASE			(KW_REGISTER(0x10000))
+#define KW_GPIO0_BASE			(KW_REGISTER(0x10100))
+#define KW_GPIO1_BASE			(KW_REGISTER(0x10140))
+#define KW_RTC_BASE			(KW_REGISTER(0x10300))
+#define KW_NANDF_BASE			(KW_REGISTER(0x10418))
+#define KW_SPI_BASE			(KW_REGISTER(0x10600))
+#define KW_CPU_WIN_BASE			(KW_REGISTER(0x20000))
+#define KW_CPU_REG_BASE			(KW_REGISTER(0x20100))
+#define KW_TIMER_BASE			(KW_REGISTER(0x20300))
+#define KW_REG_PCIE_BASE		(KW_REGISTER(0x40000))
+#define KW_USB20_BASE			(KW_REGISTER(0x50000))
+#define KW_EGIGA0_BASE			(KW_REGISTER(0x72000))
+#define KW_EGIGA1_BASE			(KW_REGISTER(0x76000))
+#define KW_SATA_BASE			(KW_REGISTER(0x80000))
+
+/* Kirkwood Sata controller has two ports */
+#define KW_SATA_PORT0_OFFSET		0x2000
+#define KW_SATA_PORT1_OFFSET		0x4000
+
+/* Kirkwood GbE controller has two ports */
+#define MAX_MVGBE_DEVS	2
+#define MVGBE0_BASE	KW_EGIGA0_BASE
+#define MVGBE1_BASE	KW_EGIGA1_BASE
+
+/* Kirkwood USB Host controller */
+#define MVUSB0_BASE			KW_USB20_BASE
+#define MVUSB0_CPU_ATTR_DRAM_CS0	KWCPU_ATTR_DRAM_CS0
+#define MVUSB0_CPU_ATTR_DRAM_CS1	KWCPU_ATTR_DRAM_CS1
+#define MVUSB0_CPU_ATTR_DRAM_CS2	KWCPU_ATTR_DRAM_CS2
+#define MVUSB0_CPU_ATTR_DRAM_CS3	KWCPU_ATTR_DRAM_CS3
+
+/* Kirkwood CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA	KWCPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE	KWCPU_WIN_ENABLE
+#define MVCPU_WIN_DISABLE	KWCPU_WIN_DISABLE
+
+#if defined (CONFIG_KW88F6281)
+#include <asm/arch/kw88f6281.h>
+#elif defined (CONFIG_KW88F6192)
+#include <asm/arch/kw88f6192.h>
+#else
+#error "SOC Name not defined"
+#endif /* CONFIG_KW88F6281 */
+#endif /* CONFIG_FEROCEON_88FR131 */
+#endif /* _ASM_ARCH_KIRKWOOD_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6192.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6192.h
new file mode 100644
index 000000000..de220d57d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6192.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_KW88F6192_H
+#define _CONFIG_KW88F6192_H
+
+/* SOC specific definations */
+#define KW88F6192_REGS_PHYS_BASE	0xf1000000
+#define KW_REGS_PHY_BASE		KW88F6192_REGS_PHYS_BASE
+
+/* TCLK Core Clock defination */
+#define CONFIG_SYS_TCLK	  166000000 /* 166MHz */
+
+#endif /* _CONFIG_KW88F6192_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6281.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6281.h
new file mode 100644
index 000000000..ca88a300e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/kw88f6281.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_KW88F6281_H
+#define _ASM_ARCH_KW88F6281_H
+
+/* SOC specific definitions */
+#define KW88F6281_REGS_PHYS_BASE	0xf1000000
+#define KW_REGS_PHY_BASE		KW88F6281_REGS_PHYS_BASE
+
+/* TCLK Core Clock definition */
+#ifndef CONFIG_SYS_TCLK
+#define CONFIG_SYS_TCLK	200000000 /* 200MHz */
+#endif
+
+#endif /* _ASM_ARCH_KW88F6281_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/mpp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/mpp.h
new file mode 100644
index 000000000..7c8f6eba9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/mpp.h
@@ -0,0 +1,301 @@
+/*
+ * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
+ *
+ * Copyright 2009: Marvell Technology Group Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __KIRKWOOD_MPP_H
+#define __KIRKWOOD_MPP_H
+
+#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
+	/* MPP number */		((_num) & 0xff) | \
+	/* MPP select value */		(((_sel) & 0xf) << 8) | \
+	/* may be input signal */	((!!(_in)) << 12) | \
+	/* may be output signal */	((!!(_out)) << 13) | \
+	/* available on F6180 */	((!!(_F6180)) << 14) | \
+	/* available on F6190 */	((!!(_F6190)) << 15) | \
+	/* available on F6192 */	((!!(_F6192)) << 16) | \
+	/* available on F6281 */	((!!(_F6281)) << 17))
+
+#define MPP_NUM(x)	((x) & 0xff)
+#define MPP_SEL(x)	(((x) >> 8) & 0xf)
+
+				/*   num sel  i  o  6180 6190 6192 6281 */
+
+#define MPP_INPUT_MASK		MPP(  0, 0x0, 1, 0, 0,   0,   0,   0    )
+#define MPP_OUTPUT_MASK		MPP(  0, 0x0, 0, 1, 0,   0,   0,   0    )
+
+#define MPP_F6180_MASK		MPP(  0, 0x0, 0, 0, 1,   0,   0,   0    )
+#define MPP_F6190_MASK		MPP(  0, 0x0, 0, 0, 0,   1,   0,   0    )
+#define MPP_F6192_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   1,   0    )
+#define MPP_F6281_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   0,   1    )
+
+#define MPP0_GPIO		MPP(  0, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP0_NF_IO2		MPP(  0, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP0_SPI_SCn		MPP(  0, 0x2, 0, 1, 1,   1,   1,   1    )
+
+#define MPP1_GPO		MPP(  1, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP1_NF_IO3		MPP(  1, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP1_SPI_MOSI		MPP(  1, 0x2, 0, 1, 1,   1,   1,   1    )
+
+#define MPP2_GPO		MPP(  2, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP2_NF_IO4		MPP(  2, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP2_SPI_SCK		MPP(  2, 0x2, 0, 1, 1,   1,   1,   1    )
+
+#define MPP3_GPO		MPP(  3, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP3_NF_IO5		MPP(  3, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP3_SPI_MISO		MPP(  3, 0x2, 1, 0, 1,   1,   1,   1    )
+
+#define MPP4_GPIO		MPP(  4, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP4_NF_IO6		MPP(  4, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP4_UART0_RXD		MPP(  4, 0x2, 1, 0, 1,   1,   1,   1    )
+#define MPP4_SATA1_ACTn		MPP(  4, 0x5, 0, 1, 0,   0,   1,   1    )
+#define MPP4_PTP_CLK		MPP(  4, 0xd, 1, 0, 1,   1,   1,   1    )
+
+#define MPP5_GPO		MPP(  5, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP5_NF_IO7		MPP(  5, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP5_UART0_TXD		MPP(  5, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP5_PTP_TRIG_GEN	MPP(  5, 0x4, 0, 1, 1,   1,   1,   1    )
+#define MPP5_SATA0_ACTn		MPP(  5, 0x5, 0, 1, 0,   1,   1,   1    )
+
+#define MPP6_SYSRST_OUTn	MPP(  6, 0x1, 0, 1, 1,   1,   1,   1    )
+#define MPP6_SPI_MOSI		MPP(  6, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP6_PTP_TRIG_GEN	MPP(  6, 0x3, 0, 1, 1,   1,   1,   1    )
+
+#define MPP7_GPO		MPP(  7, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP7_PEX_RST_OUTn	MPP(  7, 0x1, 0, 1, 1,   1,   1,   1    )
+#define MPP7_SPI_SCn		MPP(  7, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP7_PTP_TRIG_GEN	MPP(  7, 0x3, 0, 1, 1,   1,   1,   1    )
+
+#define MPP8_GPIO		MPP(  8, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP8_TW_SDA		MPP(  8, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP8_UART0_RTS		MPP(  8, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP8_UART1_RTS		MPP(  8, 0x3, 0, 1, 1,   1,   1,   1    )
+#define MPP8_MII0_RXERR		MPP(  8, 0x4, 1, 0, 0,   1,   1,   1    )
+#define MPP8_SATA1_PRESENTn	MPP(  8, 0x5, 0, 1, 0,   0,   1,   1    )
+#define MPP8_PTP_CLK		MPP(  8, 0xc, 1, 0, 1,   1,   1,   1    )
+#define MPP8_MII0_COL		MPP(  8, 0xd, 1, 0, 1,   1,   1,   1    )
+
+#define MPP9_GPIO		MPP(  9, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP9_TW_SCK		MPP(  9, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP9_UART0_CTS		MPP(  9, 0x2, 1, 0, 1,   1,   1,   1    )
+#define MPP9_UART1_CTS		MPP(  9, 0x3, 1, 0, 1,   1,   1,   1    )
+#define MPP9_SATA0_PRESENTn	MPP(  9, 0x5, 0, 1, 0,   1,   1,   1    )
+#define MPP9_PTP_EVENT_REQ	MPP(  9, 0xc, 1, 0, 1,   1,   1,   1    )
+#define MPP9_MII0_CRS		MPP(  9, 0xd, 1, 0, 1,   1,   1,   1    )
+
+#define MPP10_GPO		MPP( 10, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP10_SPI_SCK		MPP( 10, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP10_UART0_TXD		MPP( 10, 0X3, 0, 1, 1,   1,   1,   1    )
+#define MPP10_SATA1_ACTn	MPP( 10, 0x5, 0, 1, 0,   0,   1,   1    )
+#define MPP10_PTP_TRIG_GEN	MPP( 10, 0xc, 0, 1, 1,   1,   1,   1    )
+
+#define MPP11_GPIO		MPP( 11, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP11_SPI_MISO		MPP( 11, 0x2, 1, 0, 1,   1,   1,   1    )
+#define MPP11_UART0_RXD		MPP( 11, 0x3, 1, 0, 1,   1,   1,   1    )
+#define MPP11_PTP_EVENT_REQ	MPP( 11, 0x4, 1, 0, 1,   1,   1,   1    )
+#define MPP11_PTP_TRIG_GEN	MPP( 11, 0xc, 0, 1, 1,   1,   1,   1    )
+#define MPP11_PTP_CLK		MPP( 11, 0xd, 1, 0, 1,   1,   1,   1    )
+#define MPP11_SATA0_ACTn	MPP( 11, 0x5, 0, 1, 0,   1,   1,   1    )
+
+#define MPP12_GPO		MPP( 12, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP12_SD_CLK		MPP( 12, 0x1, 0, 1, 1,   1,   1,   1    )
+
+#define MPP13_GPIO		MPP( 13, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP13_SD_CMD		MPP( 13, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP13_UART1_TXD		MPP( 13, 0x3, 0, 1, 1,   1,   1,   1    )
+
+#define MPP14_GPIO		MPP( 14, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP14_SD_D0		MPP( 14, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP14_UART1_RXD		MPP( 14, 0x3, 1, 0, 1,   1,   1,   1    )
+#define MPP14_SATA1_PRESENTn	MPP( 14, 0x4, 0, 1, 0,   0,   1,   1    )
+#define MPP14_MII0_COL		MPP( 14, 0xd, 1, 0, 1,   1,   1,   1    )
+
+#define MPP15_GPIO		MPP( 15, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP15_SD_D1		MPP( 15, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP15_UART0_RTS		MPP( 15, 0x2, 0, 1, 1,   1,   1,   1    )
+#define MPP15_UART1_TXD		MPP( 15, 0x3, 0, 1, 1,   1,   1,   1    )
+#define MPP15_SATA0_ACTn	MPP( 15, 0x4, 0, 1, 0,   1,   1,   1    )
+
+#define MPP16_GPIO		MPP( 16, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP16_SD_D2		MPP( 16, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP16_UART0_CTS		MPP( 16, 0x2, 1, 0, 1,   1,   1,   1    )
+#define MPP16_UART1_RXD		MPP( 16, 0x3, 1, 0, 1,   1,   1,   1    )
+#define MPP16_SATA1_ACTn	MPP( 16, 0x4, 0, 1, 0,   0,   1,   1    )
+#define MPP16_MII0_CRS		MPP( 16, 0xd, 1, 0, 1,   1,   1,   1    )
+
+#define MPP17_GPIO		MPP( 17, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP17_SD_D3		MPP( 17, 0x1, 1, 1, 1,   1,   1,   1    )
+#define MPP17_SATA0_PRESENTn	MPP( 17, 0x4, 0, 1, 0,   1,   1,   1    )
+
+#define MPP18_GPO		MPP( 18, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP18_NF_IO0		MPP( 18, 0x1, 1, 1, 1,   1,   1,   1    )
+
+#define MPP19_GPO		MPP( 19, 0x0, 0, 1, 1,   1,   1,   1    )
+#define MPP19_NF_IO1		MPP( 19, 0x1, 1, 1, 1,   1,   1,   1    )
+
+#define MPP20_GPIO		MPP( 20, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP20_TSMP0		MPP( 20, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP20_TDM_CH0_TX_QL	MPP( 20, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP20_GE1_0		MPP( 20, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP20_AUDIO_SPDIFI	MPP( 20, 0x4, 1, 0, 0,   0,   1,   1    )
+#define MPP20_SATA1_ACTn	MPP( 20, 0x5, 0, 1, 0,   0,   1,   1    )
+
+#define MPP21_GPIO		MPP( 21, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP21_TSMP1		MPP( 21, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP21_TDM_CH0_RX_QL	MPP( 21, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP21_GE1_1		MPP( 21, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP21_AUDIO_SPDIFO	MPP( 21, 0x4, 0, 1, 0,   0,   1,   1    )
+#define MPP21_SATA0_ACTn	MPP( 21, 0x5, 0, 1, 0,   1,   1,   1    )
+
+#define MPP22_GPIO		MPP( 22, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP22_TSMP2		MPP( 22, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP22_TDM_CH2_TX_QL	MPP( 22, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP22_GE1_2		MPP( 22, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP22_AUDIO_SPDIFRMKCLK	MPP( 22, 0x4, 0, 1, 0,   0,   1,   1    )
+#define MPP22_SATA1_PRESENTn	MPP( 22, 0x5, 0, 1, 0,   0,   1,   1    )
+
+#define MPP23_GPIO		MPP( 23, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP23_TSMP3		MPP( 23, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP23_TDM_CH2_RX_QL	MPP( 23, 0x2, 1, 0, 0,   0,   1,   1    )
+#define MPP23_GE1_3		MPP( 23, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP23_AUDIO_I2SBCLK	MPP( 23, 0x4, 0, 1, 0,   0,   1,   1    )
+#define MPP23_SATA0_PRESENTn	MPP( 23, 0x5, 0, 1, 0,   1,   1,   1    )
+
+#define MPP24_GPIO		MPP( 24, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP24_TSMP4		MPP( 24, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP24_TDM_SPI_CS0	DEV( 24, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP24_GE1_4		MPP( 24, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP24_AUDIO_I2SDO	MPP( 24, 0x4, 0, 1, 0,   0,   1,   1    )
+
+#define MPP25_GPIO		MPP( 25, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP25_TSMP5		MPP( 25, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP25_TDM_SPI_SCK	MPP( 25, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP25_GE1_5		MPP( 25, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP25_AUDIO_I2SLRCLK	MPP( 25, 0x4, 0, 1, 0,   0,   1,   1    )
+
+#define MPP26_GPIO		MPP( 26, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP26_TSMP6		MPP( 26, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP26_TDM_SPI_MISO	MPP( 26, 0x2, 1, 0, 0,   0,   1,   1    )
+#define MPP26_GE1_6		MPP( 26, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP26_AUDIO_I2SMCLK	MPP( 26, 0x4, 0, 1, 0,   0,   1,   1    )
+
+#define MPP27_GPIO		MPP( 27, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP27_TSMP7		MPP( 27, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP27_TDM_SPI_MOSI	MPP( 27, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP27_GE1_7		MPP( 27, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP27_AUDIO_I2SDI	MPP( 27, 0x4, 1, 0, 0,   0,   1,   1    )
+
+#define MPP28_GPIO		MPP( 28, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP28_TSMP8		MPP( 28, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP28_TDM_CODEC_INTn	MPP( 28, 0x2, 0, 0, 0,   0,   1,   1    )
+#define MPP28_GE1_8		MPP( 28, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP28_AUDIO_EXTCLK	MPP( 28, 0x4, 1, 0, 0,   0,   1,   1    )
+
+#define MPP29_GPIO		MPP( 29, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP29_TSMP9		MPP( 29, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP29_TDM_CODEC_RSTn	MPP( 29, 0x2, 0, 0, 0,   0,   1,   1    )
+#define MPP29_GE1_9		MPP( 29, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP30_GPIO		MPP( 30, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP30_TSMP10		MPP( 30, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP30_TDM_PCLK		MPP( 30, 0x2, 1, 1, 0,   0,   1,   1    )
+#define MPP30_GE1_10		MPP( 30, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP31_GPIO		MPP( 31, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP31_TSMP11		MPP( 31, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP31_TDM_FS		MPP( 31, 0x2, 1, 1, 0,   0,   1,   1    )
+#define MPP31_GE1_11		MPP( 31, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP32_GPIO		MPP( 32, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP32_TSMP12		MPP( 32, 0x1, 1, 1, 0,   0,   1,   1    )
+#define MPP32_TDM_DRX		MPP( 32, 0x2, 1, 0, 0,   0,   1,   1    )
+#define MPP32_GE1_12		MPP( 32, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP33_GPIO		MPP( 33, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP33_TDM_DTX		MPP( 33, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP33_GE1_13		MPP( 33, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP34_GPIO		MPP( 34, 0x0, 1, 1, 0,   1,   1,   1    )
+#define MPP34_TDM_SPI_CS1	MPP( 34, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP34_GE1_14		MPP( 34, 0x3, 0, 0, 0,   1,   1,   1    )
+
+#define MPP35_GPIO		MPP( 35, 0x0, 1, 1, 1,   1,   1,   1    )
+#define MPP35_TDM_CH0_TX_QL	MPP( 35, 0x2, 0, 1, 0,   0,   1,   1    )
+#define MPP35_GE1_15		MPP( 35, 0x3, 0, 0, 0,   1,   1,   1    )
+#define MPP35_SATA0_ACTn	MPP( 35, 0x5, 0, 1, 0,   1,   1,   1    )
+#define MPP35_MII0_RXERR	MPP( 35, 0xc, 1, 0, 1,   1,   1,   1    )
+
+#define MPP36_GPIO		MPP( 36, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP36_TSMP0		MPP( 36, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP36_TDM_SPI_CS1	MPP( 36, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP36_AUDIO_SPDIFI	MPP( 36, 0x4, 1, 0, 1,   0,   0,   1    )
+
+#define MPP37_GPIO		MPP( 37, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP37_TSMP1		MPP( 37, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP37_TDM_CH2_TX_QL	MPP( 37, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP37_AUDIO_SPDIFO	MPP( 37, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP38_GPIO		MPP( 38, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP38_TSMP2		MPP( 38, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP38_TDM_CH2_RX_QL	MPP( 38, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP38_AUDIO_SPDIFRMLCLK	MPP( 38, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP39_GPIO		MPP( 39, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP39_TSMP3		MPP( 39, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP39_TDM_SPI_CS0	MPP( 39, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP39_AUDIO_I2SBCLK	MPP( 39, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP40_GPIO		MPP( 40, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP40_TSMP4		MPP( 40, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP40_TDM_SPI_SCK	MPP( 40, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP40_AUDIO_I2SDO	MPP( 40, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP41_GPIO		MPP( 41, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP41_TSMP5		MPP( 41, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP41_TDM_SPI_MISO	MPP( 41, 0x2, 1, 0, 0,   0,   0,   1    )
+#define MPP41_AUDIO_I2SLRC	MPP( 41, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP42_GPIO		MPP( 42, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP42_TSMP6		MPP( 42, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP42_TDM_SPI_MOSI	MPP( 42, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP42_AUDIO_I2SMCLK	MPP( 42, 0x4, 0, 1, 1,   0,   0,   1    )
+
+#define MPP43_GPIO		MPP( 43, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP43_TSMP7		MPP( 43, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP43_TDM_CODEC_INTn	MPP( 43, 0x2, 0, 0, 0,   0,   0,   1    )
+#define MPP43_AUDIO_I2SDI	MPP( 43, 0x4, 1, 0, 1,   0,   0,   1    )
+
+#define MPP44_GPIO		MPP( 44, 0x0, 1, 1, 1,   0,   0,   1    )
+#define MPP44_TSMP8		MPP( 44, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP44_TDM_CODEC_RSTn	MPP( 44, 0x2, 0, 0, 0,   0,   0,   1    )
+#define MPP44_AUDIO_EXTCLK	MPP( 44, 0x4, 1, 0, 1,   0,   0,   1    )
+
+#define MPP45_GPIO		MPP( 45, 0x0, 1, 1, 0,   0,   0,   1    )
+#define MPP45_TSMP9		MPP( 45, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP45_TDM_PCLK		MPP( 45, 0x2, 1, 1, 0,   0,   0,   1    )
+
+#define MPP46_GPIO		MPP( 46, 0x0, 1, 1, 0,   0,   0,   1    )
+#define MPP46_TSMP10		MPP( 46, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP46_TDM_FS		MPP( 46, 0x2, 1, 1, 0,   0,   0,   1    )
+
+#define MPP47_GPIO		MPP( 47, 0x0, 1, 1, 0,   0,   0,   1    )
+#define MPP47_TSMP11		MPP( 47, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP47_TDM_DRX		MPP( 47, 0x2, 1, 0, 0,   0,   0,   1    )
+
+#define MPP48_GPIO		MPP( 48, 0x0, 1, 1, 0,   0,   0,   1    )
+#define MPP48_TSMP12		MPP( 48, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP48_TDM_DTX		MPP( 48, 0x2, 0, 1, 0,   0,   0,   1    )
+
+#define MPP49_GPIO		MPP( 49, 0x0, 1, 1, 0,   0,   0,   1    )
+#define MPP49_TSMP9		MPP( 49, 0x1, 1, 1, 0,   0,   0,   1    )
+#define MPP49_TDM_CH0_RX_QL	MPP( 49, 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP49_PTP_CLK		MPP( 49, 0x5, 1, 0, 0,   0,   0,   1    )
+
+#define MPP_MAX			49
+
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/spi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/spi.h
new file mode 100644
index 000000000..b1cf614ca
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-kirkwood/spi.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Derived from drivers/spi/mpc8xxx_spi.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __KW_SPI_H__
+#define __KW_SPI_H__
+
+/* SPI Registers on kirkwood SOC */
+struct kwspi_registers {
+	u32 ctrl;	/* 0x10600 */
+	u32 cfg;	/* 0x10604 */
+	u32 dout;	/* 0x10608 */
+	u32 din;	/* 0x1060c */
+	u32 irq_cause;	/* 0x10610 */
+	u32 irq_mask;	/* 0x10614 */
+};
+
+/* They are used to define CONFIG_SYS_KW_SPI_MPP
+ * each of the below #defines selects which mpp is
+ * configured for each SPI signal in spi_claim_bus
+ * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1)
+ * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1)
+ * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1)
+ */
+#define MOSI_MPP6	(1 << 0)
+#define SCK_MPP10	(1 << 1)
+#define MISO_MPP11	(1 << 2)
+
+#define KWSPI_CLKPRESCL_MASK	0x1f
+#define KWSPI_CLKPRESCL_MIN	0x12
+#define KWSPI_CSN_ACT		1 /* Activates serial memory interface */
+#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
+#define KWSPI_XFERLEN_1BYTE	0
+#define KWSPI_XFERLEN_2BYTE	(1 << 5)
+#define KWSPI_XFERLEN_MASK	(1 << 5)
+#define KWSPI_ADRLEN_1BYTE	0
+#define KWSPI_ADRLEN_2BYTE	1 << 8
+#define KWSPI_ADRLEN_3BYTE	2 << 8
+#define KWSPI_ADRLEN_4BYTE	3 << 8
+#define KWSPI_ADRLEN_MASK	3 << 8
+#define KWSPI_TIMEOUT		10000
+
+#endif /* __KW_SPI_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-ks8695/platform.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-ks8695/platform.h
new file mode 100644
index 000000000..02f604926
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-ks8695/platform.h
@@ -0,0 +1,294 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __address_h
+#define __address_h			1
+
+#define KS8695_SDRAM_START	    0x00000000
+#define KS8695_SDRAM_SIZE	    0x01000000
+#define KS8695_MEM_SIZE		    KS8695_SDRAM_SIZE
+#define KS8695_MEM_START	    KS8695_SDRAM_START
+
+#define KS8695_PCMCIA_IO_BASE	    0x03800000
+#define KS8695_PCMCIA_IO_SIZE	    0x00040000
+
+#define KS8695_IO_BASE		    0x03FF0000
+#define KS8695_IO_SIZE		    0x00010000
+
+#define KS8695_SYSTEN_CONFIG	    0x00
+#define KS8695_SYSTEN_BUS_CLOCK	    0x04
+
+#define KS8695_FLASH_START	    0x02800000
+#define KS8695_FLASH_SIZE	    0x00400000
+
+/*i/o control registers offset difinitions*/
+#define KS8695_IO_CTRL0		    0x4000
+#define KS8695_IO_CTRL1		    0x4004
+#define KS8695_IO_CTRL2		    0x4008
+#define KS8695_IO_CTRL3		    0x400C
+
+/*memory control registers offset difinitions*/
+#define KS8695_MEM_CTRL0	    0x4010
+#define KS8695_MEM_CTRL1	    0x4014
+#define KS8695_MEM_CTRL2	    0x4018
+#define KS8695_MEM_CTRL3	    0x401C
+#define KS8695_MEM_GENERAL	    0x4020
+#define KS8695_SDRAM_CTRL0	    0x4030
+#define KS8695_SDRAM_CTRL1	    0x4034
+#define KS8695_SDRAM_GENERAL	    0x4038
+#define KS8695_SDRAM_BUFFER	    0x403C
+#define KS8695_SDRAM_REFRESH	    0x4040
+
+/*WAN control registers offset difinitions*/
+#define KS8695_WAN_DMA_TX	    0x6000
+#define KS8695_WAN_DMA_RX	    0x6004
+#define KS8695_WAN_DMA_TX_START	    0x6008
+#define KS8695_WAN_DMA_RX_START	    0x600C
+#define KS8695_WAN_TX_LIST	    0x6010
+#define KS8695_WAN_RX_LIST	    0x6014
+#define KS8695_WAN_MAC_LOW	    0x6018
+#define KS8695_WAN_MAC_HIGH	    0x601C
+#define KS8695_WAN_MAC_ELOW	    0x6080
+#define KS8695_WAN_MAC_EHIGH	    0x6084
+
+/*LAN control registers offset difinitions*/
+#define KS8695_LAN_DMA_TX	    0x8000
+#define KS8695_LAN_DMA_RX	    0x8004
+#define KS8695_LAN_DMA_TX_START	    0x8008
+#define KS8695_LAN_DMA_RX_START	    0x800C
+#define KS8695_LAN_TX_LIST	    0x8010
+#define KS8695_LAN_RX_LIST	    0x8014
+#define KS8695_LAN_MAC_LOW	    0x8018
+#define KS8695_LAN_MAC_HIGH	    0x801C
+#define KS8695_LAN_MAC_ELOW	    0X8080
+#define KS8695_LAN_MAC_EHIGH	    0X8084
+
+/*HPNA control registers offset difinitions*/
+#define KS8695_HPNA_DMA_TX	    0xA000
+#define KS8695_HPNA_DMA_RX	    0xA004
+#define KS8695_HPNA_DMA_TX_START    0xA008
+#define KS8695_HPNA_DMA_RX_START    0xA00C
+#define KS8695_HPNA_TX_LIST	    0xA010
+#define KS8695_HPNA_RX_LIST	    0xA014
+#define KS8695_HPNA_MAC_LOW	    0xA018
+#define KS8695_HPNA_MAC_HIGH	    0xA01C
+#define KS8695_HPNA_MAC_ELOW	    0xA080
+#define KS8695_HPNA_MAC_EHIGH	    0xA084
+
+/*UART control registers offset difinitions*/
+#define KS8695_UART_RX_BUFFER	    0xE000
+#define KS8695_UART_TX_HOLDING	    0xE004
+
+#define KS8695_UART_FIFO_CTRL	    0xE008
+#define KS8695_UART_FIFO_TRIG01	    0x00
+#define KS8695_UART_FIFO_TRIG04	    0x80
+#define KS8695_UART_FIFO_TXRST	    0x03
+#define KS8695_UART_FIFO_RXRST	    0x02
+#define KS8695_UART_FIFO_FEN	    0x01
+
+#define KS8695_UART_LINE_CTRL	    0xE00C
+#define KS8695_UART_LINEC_BRK	    0x40
+#define KS8695_UART_LINEC_EPS	    0x10
+#define KS8695_UART_LINEC_PEN	    0x08
+#define KS8695_UART_LINEC_STP2	    0x04
+#define KS8695_UART_LINEC_WLEN8	    0x03
+#define KS8695_UART_LINEC_WLEN7	    0x02
+#define KS8695_UART_LINEC_WLEN6	    0x01
+#define KS8695_UART_LINEC_WLEN5	    0x00
+
+#define KS8695_UART_MODEM_CTRL	    0xE010
+#define KS8695_UART_MODEMC_RTS	    0x02
+#define KS8695_UART_MODEMC_DTR	    0x01
+
+#define KS8695_UART_LINE_STATUS	    0xE014
+#define KS8695_UART_LINES_TXFE	    0x20
+#define KS8695_UART_LINES_BE	    0x10
+#define KS8695_UART_LINES_FE	    0x08
+#define KS8695_UART_LINES_PE	    0x04
+#define KS8695_UART_LINES_OE	    0x02
+#define KS8695_UART_LINES_RXFE	    0x01
+#define KS8695_UART_LINES_ANY	    (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
+
+#define KS8695_UART_MODEM_STATUS    0xE018
+#define KS8695_UART_MODEM_DCD	    0x80
+#define KS8695_UART_MODEM_DSR	    0x20
+#define KS8695_UART_MODEM_CTS	    0x10
+#define KS8695_UART_MODEM_DDCD	    0x08
+#define KS8695_UART_MODEM_DDSR	    0x02
+#define KS8695_UART_MODEM_DCTS	    0x01
+#define UART8695_MODEM_ANY	    0xFF
+
+#define KS8695_UART_DIVISOR	    0xE01C
+#define KS8695_UART_STATUS	    0xE020
+
+/*Interrupt controlller registers offset difinitions*/
+#define KS8695_INT_CONTL	    0xE200
+#define KS8695_INT_ENABLE	    0xE204
+#define KS8695_INT_ENABLE_MODEM	    0x0800
+#define KS8695_INT_ENABLE_ERR	    0x0400
+#define KS8695_INT_ENABLE_RX	    0x0200
+#define KS8695_INT_ENABLE_TX	    0x0100
+
+#define KS8695_INT_STATUS	    0xE208
+#define KS8695_INT_WAN_PRIORITY	    0xE20C
+#define KS8695_INT_HPNA_PRIORITY    0xE210
+#define KS8695_INT_LAN_PRIORITY	    0xE214
+#define KS8695_INT_TIMER_PRIORITY   0xE218
+#define KS8695_INT_UART_PRIORITY    0xE21C
+#define KS8695_INT_EXT_PRIORITY	    0xE220
+#define KS8695_INT_CHAN_PRIORITY    0xE224
+#define KS8695_INT_BUSERROR_PRO	    0xE228
+#define KS8695_INT_MASK_STATUS	    0xE22C
+#define KS8695_FIQ_PEND_PRIORITY    0xE230
+#define KS8695_IRQ_PEND_PRIORITY    0xE234
+
+/*timer registers offset difinitions*/
+#define KS8695_TIMER_CTRL	    0xE400
+#define KS8695_TIMER1		    0xE404
+#define KS8695_TIMER0		    0xE408
+#define KS8695_TIMER1_PCOUNT	    0xE40C
+#define KS8695_TIMER0_PCOUNT	    0xE410
+
+/*GPIO registers offset difinitions*/
+#define KS8695_GPIO_MODE	    0xE600
+#define KS8695_GPIO_CTRL	    0xE604
+#define KS8695_GPIO_DATA	    0xE608
+
+/*SWITCH registers offset difinitions*/
+#define KS8695_SWITCH_CTRL0	    0xE800
+#define KS8695_SWITCH_CTRL1	    0xE804
+#define KS8695_SWITCH_PORT1	    0xE808
+#define KS8695_SWITCH_PORT2	    0xE80C
+#define KS8695_SWITCH_PORT3	    0xE810
+#define KS8695_SWITCH_PORT4	    0xE814
+#define KS8695_SWITCH_PORT5	    0xE818
+#define KS8695_SWITCH_AUTO0	    0xE81C
+#define KS8695_SWITCH_AUTO1	    0xE820
+#define KS8695_SWITCH_LUE_CTRL	    0xE824
+#define KS8695_SWITCH_LUE_HIGH	    0xE828
+#define KS8695_SWITCH_LUE_LOW	    0xE82C
+#define KS8695_SWITCH_ADVANCED	    0xE830
+
+#define KS8695_SWITCH_LPPM12	    0xE874
+#define KS8695_SWITCH_LPPM34	    0xE878
+
+/*host communication registers difinitions*/
+#define KS8695_DSCP_HIGH	    0xE834
+#define KS8695_DSCP_LOW		    0xE838
+#define KS8695_SWITCH_MAC_HIGH	    0xE83C
+#define KS8695_SWITCH_MAC_LOW	    0xE840
+
+/*miscellaneours registers difinitions*/
+#define KS8695_MANAGE_COUNTER	    0xE844
+#define KS8695_MANAGE_DATA	    0xE848
+#define KS8695_LAN12_POWERMAGR	    0xE84C
+#define KS8695_LAN34_POWERMAGR	    0xE850
+
+#define KS8695_DEVICE_ID	    0xEA00
+#define KS8695_REVISION_ID	    0xEA04
+
+#define KS8695_MISC_CONTROL	    0xEA08
+#define KS8695_WAN_CONTROL	    0xEA0C
+#define KS8695_WAN_POWERMAGR	    0xEA10
+#define KS8695_WAN_PHY_CONTROL	    0xEA14
+#define KS8695_WAN_PHY_STATUS	    0xEA18
+
+/* bus clock definitions*/
+#define KS8695_BUS_CLOCK_125MHZ	    0x0
+#define KS8695_BUS_CLOCK_100MHZ	    0x1
+#define KS8695_BUS_CLOCK_62MHZ	    0x2
+#define KS8695_BUS_CLOCK_50MHZ	    0x3
+#define KS8695_BUS_CLOCK_41MHZ	    0x4
+#define KS8695_BUS_CLOCK_33MHZ	    0x5
+#define KS8695_BUS_CLOCK_31MHZ	    0x6
+#define KS8695_BUS_CLOCK_25MHZ	    0x7
+
+/* -------------------------------------------------------------------------------
+ *  definations for IRQ
+ * -------------------------------------------------------------------------------*/
+
+#define KS8695_INT_EXT_INT0		       2
+#define KS8695_INT_EXT_INT1		       3
+#define KS8695_INT_EXT_INT2		       4
+#define KS8695_INT_EXT_INT3		       5
+#define KS8695_INT_TIMERINT0		       6
+#define KS8695_INT_TIMERINT1		       7
+#define KS8695_INT_UART_TX		       8
+#define KS8695_INT_UART_RX		       9
+#define KS8695_INT_UART_LINE_ERR	       10
+#define KS8695_INT_UART_MODEMS		       11
+#define KS8695_INT_LAN_STOP_RX		       12
+#define KS8695_INT_LAN_STOP_TX		       13
+#define KS8695_INT_LAN_BUF_RX_STATUS	       14
+#define KS8695_INT_LAN_BUF_TX_STATUS	       15
+#define KS8695_INT_LAN_RX_STATUS	       16
+#define KS8695_INT_LAN_TX_STATUS	       17
+#define KS8695_INT_HPAN_STOP_RX		       18
+#define KS8695_INT_HPNA_STOP_TX		       19
+#define KS8695_INT_HPNA_BUF_RX_STATUS	       20
+#define KS8695_INT_HPNA_BUF_TX_STATUS	       21
+#define KS8695_INT_HPNA_RX_STATUS	       22
+#define KS8695_INT_HPNA_TX_STATUS	       23
+#define KS8695_INT_BUS_ERROR		       24
+#define KS8695_INT_WAN_STOP_RX		       25
+#define KS8695_INT_WAN_STOP_TX		       26
+#define KS8695_INT_WAN_BUF_RX_STATUS	       27
+#define KS8695_INT_WAN_BUF_TX_STATUS	       28
+#define KS8695_INT_WAN_RX_STATUS	       29
+#define KS8695_INT_WAN_TX_STATUS	       30
+
+#define KS8695_INT_UART			       KS8695_INT_UART_TX
+
+/* -------------------------------------------------------------------------------
+ *  Interrupt bit positions
+ *
+ * -------------------------------------------------------------------------------
+ */
+
+#define KS8695_INTMASK_EXT_INT0		       ( 1 << KS8695_INT_EXT_INT0 )
+#define KS8695_INTMASK_EXT_INT1		       ( 1 << KS8695_INT_EXT_INT1 )
+#define KS8695_INTMASK_EXT_INT2		       ( 1 << KS8695_INT_EXT_INT2 )
+#define KS8695_INTMASK_EXT_INT3		       ( 1 << KS8695_INT_EXT_INT3 )
+#define KS8695_INTMASK_TIMERINT0	       ( 1 << KS8695_INT_TIMERINT0 )
+#define KS8695_INTMASK_TIMERINT1	       ( 1 << KS8695_INT_TIMERINT1 )
+#define KS8695_INTMASK_UART_TX		       ( 1 << KS8695_INT_UART_TX  )
+#define KS8695_INTMASK_UART_RX		       ( 1 << KS8695_INT_UART_RX  )
+#define KS8695_INTMASK_UART_LINE_ERR	       ( 1 << KS8695_INT_UART_LINE_ERR )
+#define KS8695_INTMASK_UART_MODEMS	       ( 1 << KS8695_INT_UART_MODEMS )
+#define KS8695_INTMASK_LAN_STOP_RX	       ( 1 << KS8695_INT_LAN_STOP_RX )
+#define KS8695_INTMASK_LAN_STOP_TX	       ( 1 << KS8695_INT_LAN_STOP_TX )
+#define KS8695_INTMASK_LAN_BUF_RX_STATUS       ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
+#define KS8695_INTMASK_LAN_BUF_TX_STATUS       ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
+#define KS8695_INTMASK_LAN_RX_STATUS	       ( 1 << KS8695_INT_LAN_RX_STATUS )
+#define KS8695_INTMASK_LAN_TX_STATUS	       ( 1 << KS8695_INT_LAN_RX_STATUS )
+#define KS8695_INTMASK_HPAN_STOP_RX	       ( 1 << KS8695_INT_HPAN_STOP_RX )
+#define KS8695_INTMASK_HPNA_STOP_TX	       ( 1 << KS8695_INT_HPNA_STOP_TX )
+#define KS8695_INTMASK_HPNA_BUF_RX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
+#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
+#define KS8695_INTMASK_HPNA_RX_STATUS	       ( 1 << KS8695_INT_HPNA_RX_STATUS )
+#define KS8695_INTMASK_HPNA_TX_STATUS	       ( 1 << KS8695_INT_HPNA_TX_STATUS )
+#define KS8695_INTMASK_BUS_ERROR	       ( 1 << KS8695_INT_BUS_ERROR )
+#define KS8695_INTMASK_WAN_STOP_RX	       ( 1 << KS8695_INT_WAN_STOP_RX )
+#define KS8695_INTMASK_WAN_STOP_TX	       ( 1 << KS8695_INT_WAN_STOP_TX )
+#define KS8695_INTMASK_WAN_BUF_RX_STATUS       ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
+#define KS8695_INTMASK_WAN_BUF_TX_STATUS       ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
+#define KS8695_INTMASK_WAN_RX_STATUS	       ( 1 << KS8695_INT_WAN_RX_STATUS )
+#define KS8695_INTMASK_WAN_TX_STATUS	       ( 1 << KS8695_INT_WAN_TX_STATUS )
+
+#define KS8695_SC_VALID_INT		       0xFFFFFFFF
+#define MAXIRQNUM			       31
+
+/*
+ *  Timer definitions
+ *
+ *  Use timer 1 & 2
+ *  (both run at 25MHz).
+ *
+ */
+#define TICKS_PER_uSEC			25
+#define mSEC_1				1000
+#define mSEC_10				(mSEC_1 * 10)
+
+#endif
+
+/*	END */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h
new file mode 100644
index 000000000..92f6c15f2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LPC32XX_CLK_H
+#define _LPC32XX_CLK_H
+
+#include <asm/types.h>
+
+#define OSC_CLK_FREQUENCY	13000000
+#define RTC_CLK_FREQUENCY	32768
+
+/* Clocking and Power Control Registers */
+struct clk_pm_regs {
+	u32 reserved0[5];
+	u32 boot_map;		/* Boot Map Control Register		*/
+	u32 p0_intr_er;		/* Port 0/1 Start and Interrupt Enable	*/
+	u32 usbdiv_ctrl;	/* USB Clock Pre-Divide Register	*/
+	/* Internal Start Signal Sources Registers	*/
+	u32 start_er_int;	/* Start Enable Register		*/
+	u32 start_rsr_int;	/* Start Raw Status Register		*/
+	u32 start_sr_int;	/* Start Status Register		*/
+	u32 start_apr_int;	/* Start Activation Polarity Register	*/
+	/* Device Pin Start Signal Sources Registers	*/
+	u32 start_er_pin;	/* Start Enable Register		*/
+	u32 start_rsr_pin;	/* Start Raw Status Register		*/
+	u32 start_sr_pin;	/* Start Status Register		*/
+	u32 start_apr_pin;	/* Start Activation Polarity Register	*/
+	/* Clock Control Registers			*/
+	u32 hclkdiv_ctrl;	/* HCLK Divider Control Register	*/
+	u32 pwr_ctrl;		/* Power Control Register		*/
+	u32 pll397_ctrl;	/* PLL397 Control Register		*/
+	u32 osc_ctrl;		/* Main Oscillator Control Register	*/
+	u32 sysclk_ctrl;	/* SYSCLK Control Register		*/
+	u32 lcdclk_ctrl;	/* LCD Clock Control Register		*/
+	u32 hclkpll_ctrl;	/* HCLK PLL Control Register		*/
+	u32 reserved1;
+	u32 adclk_ctrl1;	/* ADC Clock Control1 Register		*/
+	u32 usb_ctrl;		/* USB Control Register			*/
+	u32 sdramclk_ctrl;	/* SDRAM Clock Control Register		*/
+	u32 ddr_lap_nom;	/* DDR Calibration Nominal Value	*/
+	u32 ddr_lap_count;	/* DDR Calibration Measured Value	*/
+	u32 ddr_cal_delay;	/* DDR Calibration Delay Value		*/
+	u32 ssp_ctrl;		/* SSP Control Register			*/
+	u32 i2s_ctrl;		/* I2S Clock Control Register		*/
+	u32 ms_ctrl;		/* Memory Card Control Register		*/
+	u32 reserved2[3];
+	u32 macclk_ctrl;	/* Ethernet MAC Clock Control Register	*/
+	u32 reserved3[4];
+	u32 test_clk;		/* Test Clock Selection Register	*/
+	u32 sw_int;		/* Software Interrupt Register		*/
+	u32 i2cclk_ctrl;	/* I2C Clock Control Register		*/
+	u32 keyclk_ctrl;	/* Keyboard Scan Clock Control Register	*/
+	u32 adclk_ctrl;		/* ADC Clock Control Register		*/
+	u32 pwmclk_ctrl;	/* PWM Clock Control Register		*/
+	u32 timclk_ctrl;	/* Watchdog and Highspeed Timer Control */
+	u32 timclk_ctrl1;	/* Motor and Timer Clock Control	*/
+	u32 spi_ctrl;		/* SPI Control Register			*/
+	u32 flashclk_ctrl;	/* NAND Flash Clock Control Register	*/
+	u32 reserved4;
+	u32 u3clk;		/* UART 3 Clock Control Register	*/
+	u32 u4clk;		/* UART 4 Clock Control Register	*/
+	u32 u5clk;		/* UART 5 Clock Control Register	*/
+	u32 u6clk;		/* UART 6 Clock Control Register	*/
+	u32 irdaclk;		/* IrDA Clock Control Register		*/
+	u32 uartclk_ctrl;	/* UART Clock Control Register		*/
+	u32 dmaclk_ctrl;	/* DMA Clock Control Register		*/
+	u32 autoclk_ctrl;	/* Autoclock Control Register		*/
+};
+
+/* HCLK Divider Control Register bits */
+#define CLK_HCLK_DDRAM_HALF		(0x2 << 7)
+#define CLK_HCLK_DDRAM_NOMINAL		(0x1 << 7)
+#define CLK_HCLK_DDRAM_STOPPED		(0x0 << 7)
+#define CLK_HCLK_PERIPH_DIV_MASK	(0x1F << 2)
+#define CLK_HCLK_PERIPH_DIV(n)		((((n) - 1) & 0x1F) << 2)
+#define CLK_HCLK_ARM_PLL_DIV_MASK	(0x3 << 0)
+#define CLK_HCLK_ARM_PLL_DIV_4		(0x2 << 0)
+#define CLK_HCLK_ARM_PLL_DIV_2		(0x1 << 0)
+#define CLK_HCLK_ARM_PLL_DIV_1		(0x0 << 0)
+
+/* Power Control Register bits */
+#define CLK_PWR_HCLK_RUN_PERIPH		(1 << 10)
+#define CLK_PWR_EMC_SREFREQ		(1 << 9)
+#define CLK_PWR_EMC_SREFREQ_UPDATE	(1 << 8)
+#define CLK_PWR_SDRAM_SREFREQ		(1 << 7)
+#define CLK_PWR_HIGHCORE_LEVEL		(1 << 5)
+#define CLK_PWR_SYSCLKEN_LEVEL		(1 << 4)
+#define CLK_PWR_SYSCLKEN_CTRL		(1 << 3)
+#define CLK_PWR_NORMAL_RUN		(1 << 2)
+#define CLK_PWR_HIGHCORE_CTRL		(1 << 1)
+#define CLK_PWR_STOP_MODE		(1 << 0)
+
+/* SYSCLK Control Register bits */
+#define CLK_SYSCLK_PLL397		(1 << 1)
+#define CLK_SYSCLK_MUX			(1 << 0)
+
+/* HCLK PLL Control Register bits */
+#define CLK_HCLK_PLL_OPERATING		(1 << 16)
+#define CLK_HCLK_PLL_BYPASS		(1 << 15)
+#define CLK_HCLK_PLL_DIRECT		(1 << 14)
+#define CLK_HCLK_PLL_FEEDBACK		(1 << 13)
+#define CLK_HCLK_PLL_POSTDIV_MASK	(0x3 << 11)
+#define CLK_HCLK_PLL_POSTDIV_16		(0x3 << 11)
+#define CLK_HCLK_PLL_POSTDIV_8		(0x2 << 11)
+#define CLK_HCLK_PLL_POSTDIV_4		(0x1 << 11)
+#define CLK_HCLK_PLL_POSTDIV_2		(0x0 << 11)
+#define CLK_HCLK_PLL_PREDIV_MASK	(0x3 << 9)
+#define CLK_HCLK_PLL_PREDIV_4		(0x3 << 9)
+#define CLK_HCLK_PLL_PREDIV_3		(0x2 << 9)
+#define CLK_HCLK_PLL_PREDIV_2		(0x1 << 9)
+#define CLK_HCLK_PLL_PREDIV_1		(0x0 << 9)
+#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK	(0xFF << 1)
+#define CLK_HCLK_PLL_FEEDBACK_DIV(n)	((((n) - 1) & 0xFF) << 1)
+#define CLK_HCLK_PLL_LOCKED		(1 << 0)
+
+/* Ethernet MAC Clock Control Register bits	*/
+#define CLK_MAC_RMII			(0x3 << 3)
+#define CLK_MAC_MII			(0x1 << 3)
+#define CLK_MAC_MASTER			(1 << 2)
+#define CLK_MAC_SLAVE			(1 << 1)
+#define CLK_MAC_REG			(1 << 0)
+
+/* Timer Clock Control1 Register bits */
+#define CLK_TIMCLK_MOTOR		(1 << 6)
+#define CLK_TIMCLK_TIMER3		(1 << 5)
+#define CLK_TIMCLK_TIMER2		(1 << 4)
+#define CLK_TIMCLK_TIMER1		(1 << 3)
+#define CLK_TIMCLK_TIMER0		(1 << 2)
+#define CLK_TIMCLK_TIMER5		(1 << 1)
+#define CLK_TIMCLK_TIMER4		(1 << 0)
+
+/* Timer Clock Control Register bits */
+#define CLK_TIMCLK_HSTIMER		(1 << 1)
+#define CLK_TIMCLK_WATCHDOG		(1 << 0)
+
+/* UART Clock Control Register bits */
+#define CLK_UART(n)			(1 << ((n) - 3))
+
+/* UARTn Clock Select Registers bits */
+#define CLK_UART_HCLK			(1 << 16)
+#define CLK_UART_X_DIV(n)		(((n) & 0xFF) << 8)
+#define CLK_UART_Y_DIV(n)		(((n) & 0xFF) << 0)
+
+/* DMA Clock Control Register bits */
+#define CLK_DMA_ENABLE			(1 << 0)
+
+unsigned int get_sys_clk_rate(void);
+unsigned int get_hclk_pll_rate(void);
+unsigned int get_hclk_clk_div(void);
+unsigned int get_hclk_clk_rate(void);
+unsigned int get_periph_clk_div(void);
+unsigned int get_periph_clk_rate(void);
+
+#endif /* _LPC32XX_CLK_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/config.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/config.h
new file mode 100644
index 000000000..c985401d3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -0,0 +1,60 @@
+/*
+ * Common definitions for LPC32XX board configurations
+ *
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LPC32XX_CONFIG_H
+#define _LPC32XX_CONFIG_H
+
+/* Basic CPU architecture */
+#define CONFIG_ARM926EJS
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+/* UART configuration */
+#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_CONS_INDEX		(CONFIG_SYS_LPC32XX_UART - 2)
+#elif	(CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
+	(CONFIG_SYS_LPC32XX_UART == 7)
+#define CONFIG_LPC32XX_HSUART
+#else
+#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7"
+#endif
+
+#if defined(CONFIG_SYS_NS16550_SERIAL)
+#define CONFIG_SYS_NS16550
+
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#define CONFIG_SYS_NS16550_COM1		UART3_BASE
+#define CONFIG_SYS_NS16550_COM2		UART4_BASE
+#define CONFIG_SYS_NS16550_COM3		UART5_BASE
+#define CONFIG_SYS_NS16550_COM4		UART6_BASE
+#endif
+
+#if defined(CONFIG_LPC32XX_HSUART)
+#if	CONFIG_SYS_LPC32XX_UART == 1
+#define HS_UART_BASE			HS_UART1_BASE
+#elif	CONFIG_SYS_LPC32XX_UART == 2
+#define HS_UART_BASE			HS_UART2_BASE
+#else	/* CONFIG_SYS_LPC32XX_UART == 7 */
+#define HS_UART_BASE			HS_UART7_BASE
+#endif
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+		{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+
+/* NOR Flash */
+#if defined(CONFIG_SYS_FLASH_CFI)
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_PROTECTION
+#endif
+
+#endif /* _LPC32XX_CONFIG_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h
new file mode 100644
index 000000000..199b4a026
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LPC32XX_CPU_H
+#define _LPC32XX_CPU_H
+
+/* LPC32XX Memory map */
+
+/* AHB physical base addresses */
+#define SLC_NAND_BASE	0x20020000	/* SLC NAND Flash registers base    */
+#define SSP0_BASE	0x20084000	/* SSP0 registers base              */
+#define SD_CARD_BASE	0x20098000	/* SD card interface registers base */
+#define MLC_NAND_BASE	0x200A8000	/* MLC NAND Flash registers base    */
+#define DMA_BASE	0x31000000	/* DMA controller registers base    */
+#define USB_BASE	0x31020000	/* USB registers base               */
+#define LCD_BASE	0x31040000	/* LCD registers base               */
+#define ETHERNET_BASE	0x31060000	/* Ethernet registers base          */
+#define EMC_BASE	0x31080000	/* EMC configuration registers base */
+
+/* FAB peripherals base addresses */
+#define CLK_PM_BASE	0x40004000	/* System control registers base    */
+#define HS_UART1_BASE	0x40014000	/* High speed UART 1 registers base */
+#define HS_UART2_BASE	0x40018000	/* High speed UART 2 registers base */
+#define HS_UART7_BASE	0x4001C000	/* High speed UART 7 registers base */
+#define RTC_BASE	0x40024000	/* RTC registers base               */
+#define GPIO_BASE	0x40028000	/* GPIO registers base              */
+#define WDT_BASE	0x4003C000	/* Watchdog timer registers base    */
+#define TIMER0_BASE	0x40044000	/* Timer0 registers base            */
+#define TIMER1_BASE	0x4004C000	/* Timer1 registers base            */
+#define UART_CTRL_BASE	0x40054000	/* UART control regsisters base     */
+
+/* APB peripherals base addresses */
+#define UART3_BASE	0x40080000	/* UART 3 registers base            */
+#define UART4_BASE	0x40088000	/* UART 4 registers base            */
+#define UART5_BASE	0x40090000	/* UART 5 registers base            */
+#define UART6_BASE	0x40098000	/* UART 6 registers base            */
+
+/* External SDRAM Memory Bank base addresses */
+#define EMC_DYCS0_BASE	0x80000000	/* SDRAM DYCS0 base address         */
+#define EMC_DYCS1_BASE	0xA0000000	/* SDRAM DYCS1 base address         */
+
+/* External Static Memory Bank base addresses */
+#define EMC_CS0_BASE	0xE0000000
+#define EMC_CS1_BASE	0xE1000000
+#define EMC_CS2_BASE	0xE2000000
+#define EMC_CS3_BASE	0xE3000000
+
+#endif /* _LPC32XX_CPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h
new file mode 100644
index 000000000..82d9bcce5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/emc.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LPC32XX_EMC_H
+#define _LPC32XX_EMC_H
+
+#include <asm/types.h>
+
+/* EMC Registers */
+struct emc_regs {
+	u32 ctrl;		/* Controls operation of the EMC             */
+	u32 status;		/* Provides EMC status information           */
+	u32 config;		/* Configures operation of the EMC           */
+	u32 reserved0[5];
+	u32 control;		/* Controls dyn memory operation             */
+	u32 refresh;		/* Configures dyn memory refresh operation   */
+	u32 read_config;	/* Configures the dyn memory read strategy   */
+	u32 reserved1;
+	u32 t_rp;		/* Precharge command period                  */
+	u32 t_ras;		/* Active to precharge command period        */
+	u32 t_srex;		/* Self-refresh exit time                    */
+	u32 reserved2[2];
+	u32 t_wr;		/* Write recovery time                       */
+	u32 t_rc;		/* Active to active command period           */
+	u32 t_rfc;		/* Auto-refresh period                       */
+	u32 t_xsr;		/* Exit self-refresh to active command time  */
+	u32 t_rrd;		/* Active bank A to active bank B latency    */
+	u32 t_mrd;		/* Load mode register to active command time */
+	u32 t_cdlr;		/* Last data in to read command time         */
+	u32 reserved3[8];
+	u32 extended_wait;	/* time for static memory rd/wr transfers    */
+	u32 reserved4[31];
+	u32 config0;		/* Configuration information for the SDRAM   */
+	u32 rascas0;		/* RAS and CAS latencies for the SDRAM       */
+	u32 reserved5[6];
+	u32 config1;		/* Configuration information for the SDRAM   */
+	u32 rascas1;		/* RAS and CAS latencies for the SDRAM       */
+	u32 reserved6[54];
+	struct emc_stat_t {
+		u32 config;	/* Static memory configuration               */
+		u32 waitwen;	/* Delay from chip select to write enable    */
+		u32 waitoen;	/* Delay to output enable                    */
+		u32 waitrd;	/* Delay to a read access                    */
+		u32 waitpage;	/* Delay for async page mode read            */
+		u32 waitwr;	/* Delay to a write access                   */
+		u32 waitturn;	/* Number of bus turnaround cycles           */
+		u32 reserved;
+	} stat[4];
+	u32 reserved7[96];
+	struct emc_ahb_t {
+		u32 control;	/* Control register for AHB                  */
+		u32 status;	/* Status register for AHB                   */
+		u32 timeout;	/* Timeout register for AHB                  */
+		u32 reserved[5];
+	} ahb[5];
+};
+
+/* Static Memory Configuration Register bits */
+#define EMC_STAT_CONFIG_WP		(1 << 20)
+#define EMC_STAT_CONFIG_EW		(1 << 8)
+#define EMC_STAT_CONFIG_PB		(1 << 7)
+#define EMC_STAT_CONFIG_PC		(1 << 6)
+#define EMC_STAT_CONFIG_PM		(1 << 3)
+#define EMC_STAT_CONFIG_32BIT		(2 << 0)
+#define EMC_STAT_CONFIG_16BIT		(1 << 0)
+#define EMC_STAT_CONFIG_8BIT		(0 << 0)
+
+/* Static Memory Delay Registers */
+#define EMC_STAT_WAITWEN(n)		(((n) - 1) & 0x0F)
+#define EMC_STAT_WAITOEN(n)		(((n) - 1) & 0x0F)
+#define EMC_STAT_WAITRD(n)		(((n) - 1) & 0x1F)
+#define EMC_STAT_WAITPAGE(n)		(((n) - 1) & 0x1F)
+#define EMC_STAT_WAITWR(n)		(((n) - 2) & 0x1F)
+#define EMC_STAT_WAITTURN(n)		(((n) - 1) & 0x0F)
+
+#endif /* _LPC32XX_EMC_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
new file mode 100644
index 000000000..28812be3c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LPC32XX_SYS_PROTO_H
+#define _LPC32XX_SYS_PROTO_H
+
+void lpc32xx_uart_init(unsigned int uart_id);
+
+#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h
new file mode 100644
index 000000000..bd90144c0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/timer.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LPC32XX_TIMER_H
+#define _LPC32XX_TIMER_H
+
+#include <asm/types.h>
+
+/* Timer/Counter Registers */
+struct timer_regs {
+	u32 ir;			/* Interrupt Register		*/
+	u32 tcr;		/* Timer Control Register	*/
+	u32 tc;			/* Timer Counter		*/
+	u32 pr;			/* Prescale Register		*/
+	u32 pc;			/* Prescale Counter		*/
+	u32 mcr;		/* Match Control Register	*/
+	u32 mr[4];		/* Match Registers		*/
+	u32 ccr;		/* Capture Control Register	*/
+	u32 cr[4];		/* Capture Registers		*/
+	u32 emr;		/* External Match Register	*/
+	u32 reserved[12];
+	u32 ctcr;		/* Count Control Register	*/
+};
+
+/* Timer/Counter Interrupt Register bits */
+#define TIMER_IR_CR(n)			(1 << ((n) + 4))
+#define TIMER_IR_MR(n)			(1 << (n))
+
+/* Timer/Counter Timer Control Register bits */
+#define TIMER_TCR_COUNTER_RESET		(1 << 1)
+#define TIMER_TCR_COUNTER_ENABLE	(1 << 0)
+#define TIMER_TCR_COUNTER_DISABLE	(0 << 0)
+
+/* Timer/Counter Match Control Register bits */
+#define TIMER_MCR_STOP(n)		(1 << (3 * (n) + 2))
+#define TIMER_MCR_RESET(n)		(1 << (3 * (n) + 1))
+#define TIMER_MCR_INTERRUPT(n)		(1 << (3 * (n)))
+
+/* Timer/Counter Capture Control Register bits */
+#define TIMER_CCR_INTERRUPT(n)		(1 << (3 * (n) + 2))
+#define TIMER_CCR_FALLING_EDGE(n)	(1 << (3 * (n) + 1))
+#define TIMER_CCR_RISING_EDGE(n)	(1 << (3 * (n)))
+
+/* Timer/Counter External Match Register bits */
+#define TIMER_EMR_EMC_TOGGLE(n)		(0x3 << (2 * (n) + 4))
+#define TIMER_EMR_EMC_SET(n)		(0x2 << (2 * (n) + 4))
+#define TIMER_EMR_EMC_CLEAR(n)		(0x1 << (2 * (n) + 4))
+#define TIMER_EMR_EMC_NOTHING(n)	(0x0 << (2 * (n) + 4))
+#define TIMER_EMR_EM(n)			(1 << (n))
+
+/* Timer/Counter Count Control Register bits */
+#define TIMER_CTCR_INPUT(n)		((n) << 2)
+#define TIMER_CTCR_MODE_COUNTER_BOTH	(0x3 << 0)
+#define TIMER_CTCR_MODE_COUNTER_FALLING	(0x2 << 0)
+#define TIMER_CTCR_MODE_COUNTER_RISING	(0x1 << 0)
+#define TIMER_CTCR_MODE_TIMER		(0x0 << 0)
+
+#endif /* _LPC32XX_TIMER_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h
new file mode 100644
index 000000000..01dacd61b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/uart.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LPC32XX_UART_H
+#define _LPC32XX_UART_H
+
+#include <asm/types.h>
+
+/* 14-clock UART Registers */
+struct hsuart_regs {
+	union {
+		u32 rx;		/* Receiver FIFO		*/
+		u32 tx;		/* Transmitter FIFO		*/
+	};
+	u32 level;		/* FIFO Level Register		*/
+	u32 iir;		/* Interrupt ID Register	*/
+	u32 ctrl;		/* Control Register		*/
+	u32 rate;		/* Rate Control Register	*/
+};
+
+/* 14-clock UART Receiver FIFO Register bits */
+#define HSUART_RX_BREAK			(1 << 10)
+#define HSUART_RX_ERROR			(1 << 9)
+#define HSUART_RX_EMPTY			(1 << 8)
+#define HSUART_RX_DATA			(0xff << 0)
+
+/* 14-clock UART Level Register bits */
+#define HSUART_LEVEL_TX			(0xff << 8)
+#define HSUART_LEVEL_RX			(0xff << 0)
+
+/* 14-clock UART Interrupt Identification Register bits */
+#define HSUART_IIR_TX_INT_SET		(1 << 6)
+#define HSUART_IIR_RX_OE		(1 << 5)
+#define HSUART_IIR_BRK			(1 << 4)
+#define HSUART_IIR_FE			(1 << 3)
+#define HSUART_IIR_RX_TIMEOUT		(1 << 2)
+#define HSUART_IIR_RX_TRIG		(1 << 1)
+#define HSUART_IIR_TX			(1 << 0)
+
+/* 14-clock UART Control Register bits */
+#define HSUART_CTRL_HRTS_INV		(1 << 21)
+#define HSUART_CTRL_HRTS_TRIG_48	(0x3 << 19)
+#define HSUART_CTRL_HRTS_TRIG_32	(0x2 << 19)
+#define HSUART_CTRL_HRTS_TRIG_16	(0x1 << 19)
+#define HSUART_CTRL_HRTS_TRIG_8		(0x0 << 19)
+#define HSUART_CTRL_HRTS_EN		(1 << 18)
+#define HSUART_CTRL_TMO_16		(0x3 << 16)
+#define HSUART_CTRL_TMO_8		(0x2 << 16)
+#define HSUART_CTRL_TMO_4		(0x1 << 16)
+#define HSUART_CTRL_TMO_DISABLED	(0x0 << 16)
+#define HSUART_CTRL_HCTS_INV		(1 << 15)
+#define HSUART_CTRL_HCTS_EN		(1 << 14)
+#define HSUART_CTRL_HSU_OFFSET(n)	((n) << 9)
+#define HSUART_CTRL_HSU_BREAK		(1 << 8)
+#define HSUART_CTRL_HSU_ERR_INT_EN	(1 << 7)
+#define HSUART_CTRL_HSU_RX_INT_EN	(1 << 6)
+#define HSUART_CTRL_HSU_TX_INT_EN	(1 << 5)
+#define HSUART_CTRL_HSU_RX_TRIG_48	(0x5 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_32	(0x4 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_16	(0x3 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_8	(0x2 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_4	(0x1 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_1	(0x0 << 2)
+#define HSUART_CTRL_HSU_TX_TRIG_16	(0x3 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_8	(0x2 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_4	(0x1 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_0	(0x0 << 0)
+
+/* UART Control Registers */
+struct uart_ctrl_regs {
+	u32 ctrl;		/* Control Register		*/
+	u32 clkmode;		/* Clock Mode Register		*/
+	u32 loop;		/* Loopback Control Register	*/
+};
+
+/* UART Control Register bits */
+#define UART_CTRL_UART3_MD_CTRL		(1 << 11)
+#define UART_CTRL_HDPX_INV		(1 << 10)
+#define UART_CTRL_HDPX_EN		(1 << 9)
+#define UART_CTRL_UART6_IRDA		(1 << 5)
+#define UART_CTRL_IR_TX6_INV		(1 << 4)
+#define UART_CTRL_IR_RX6_INV		(1 << 3)
+#define UART_CTRL_IR_RX_LENGTH		(1 << 2)
+#define UART_CTRL_IR_TX_LENGTH		(1 << 1)
+#define UART_CTRL_UART5_USB_MODE	(1 << 0)
+
+/* UART Clock Mode Register bits */
+#define UART_CLKMODE_STATX(n)		(1 << ((n) + 16))
+#define UART_CLKMODE_STAT		(1 << 14)
+#define UART_CLKMODE_MASK(n)		(0x3 << (2 * (n) - 2))
+#define UART_CLKMODE_AUTO(n)		(0x2 << (2 * (n) - 2))
+#define UART_CLKMODE_ON(n)		(0x1 << (2 * (n) - 2))
+#define UART_CLKMODE_OFF(n)		(0x0 << (2 * (n) - 2))
+
+/* UART Loopback Control Register bits */
+#define UART_LOOPBACK(n)		(1 << ((n) - 1))
+
+#endif /* _LPC32XX_UART_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h
new file mode 100644
index 000000000..d7903c243
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LPC32XX_WDT_H
+#define _LPC32XX_WDT_H
+
+#include <asm/types.h>
+
+/* Watchdog Timer Registers */
+struct wdt_regs {
+	u32 isr;		/* Interrupt Status Register		*/
+	u32 ctrl;		/* Control Register			*/
+	u32 counter;		/* Counter Value Register		*/
+	u32 mctrl;		/* Match Control Register		*/
+	u32 match0;		/* Match 0 Register			*/
+	u32 emr;		/* External Match Control Register	*/
+	u32 pulse;		/* Reset Pulse Length Register		*/
+	u32 res;		/* Reset Source Register		*/
+};
+
+/* Watchdog Timer Control Register bits */
+#define WDTIM_CTRL_PAUSE_EN		(1 << 2)
+#define WDTIM_CTRL_RESET_COUNT		(1 << 1)
+#define WDTIM_CTRL_COUNT_ENAB		(1 << 0)
+
+/* Watchdog Timer Match Control Register bits */
+#define WDTIM_MCTRL_RESFRC2		(1 << 6)
+#define WDTIM_MCTRL_RESFRC1		(1 << 5)
+#define WDTIM_MCTRL_M_RES2		(1 << 4)
+#define WDTIM_MCTRL_M_RES1		(1 << 3)
+#define WDTIM_MCTRL_STOP_COUNT0		(1 << 2)
+#define WDTIM_MCTRL_RESET_COUNT0	(1 << 1)
+#define WDTIM_MCTRL_MR0_INT		(1 << 0)
+
+#endif /* _LPC32XX_WDT_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/hardware.h
new file mode 100644
index 000000000..42a52bc36
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/hardware.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2007
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ *          <cs@mycable.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/sizes.h>
+#include <asm/arch/mb86r0x.h>
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
new file mode 100644
index 000000000..7fec9715b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
@@ -0,0 +1,599 @@
+/*
+ * (C) Copyright 2007
+ *
+ * mb86r0x definitions
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ *          <cs@mycable.de>
+ *
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef MB86R0X_H
+#define MB86R0X_H
+
+#ifndef __ASSEMBLY__
+
+/* GPIO registers */
+struct mb86r0x_gpio {
+	uint32_t gpdr0;
+	uint32_t gpdr1;
+	uint32_t gpdr2;
+	uint32_t res;
+	uint32_t gpddr0;
+	uint32_t gpddr1;
+	uint32_t gpddr2;
+};
+
+/* PWM registers */
+struct mb86r0x_pwm {
+	uint32_t bcr;
+	uint32_t tpr;
+	uint32_t pr;
+	uint32_t dr;
+	uint32_t cr;
+	uint32_t sr;
+	uint32_t ccr;
+	uint32_t ir;
+};
+
+/* The mb86r0x chip control (CCNT) register set. */
+struct mb86r0x_ccnt {
+	uint32_t ccid;
+	uint32_t csrst;
+	uint32_t pad0[2];
+	uint32_t cist;
+	uint32_t cistm;
+	uint32_t cgpio_ist;
+	uint32_t cgpio_istm;
+	uint32_t cgpio_ip;
+	uint32_t cgpio_im;
+	uint32_t caxi_bw;
+	uint32_t caxi_ps;
+	uint32_t cmux_md;
+	uint32_t cex_pin_st;
+	uint32_t cmlb;
+	uint32_t pad1[1];
+	uint32_t cusb;
+	uint32_t pad2[41];
+	uint32_t cbsc;
+	uint32_t cdcrc;
+	uint32_t cmsr0;
+	uint32_t cmsr1;
+	uint32_t pad3[2];
+};
+
+/* The mb86r0x clock reset generator */
+struct mb86r0x_crg {
+	uint32_t crpr;
+	uint32_t pad0;
+	uint32_t crwr;
+	uint32_t crsr;
+	uint32_t crda;
+	uint32_t crdb;
+	uint32_t crha;
+	uint32_t crpa;
+	uint32_t crpb;
+	uint32_t crhb;
+	uint32_t cram;
+};
+
+/* The mb86r0x timer */
+struct mb86r0x_timer {
+	uint32_t load;
+	uint32_t value;
+	uint32_t control;
+	uint32_t intclr;
+	uint32_t ris;
+	uint32_t mis;
+	uint32_t bgload;
+};
+
+/* mb86r0x gdc display controller */
+struct mb86r0x_gdc_dsp {
+	/* Display settings */
+	uint32_t dcm0;
+	uint16_t pad00;
+	uint16_t htp;
+	uint16_t hdp;
+	uint16_t hdb;
+	uint16_t hsp;
+	uint8_t  hsw;
+	uint8_t  vsw;
+	uint16_t pad01;
+	uint16_t vtr;
+	uint16_t vsp;
+	uint16_t vdp;
+	uint16_t wx;
+	uint16_t wy;
+	uint16_t ww;
+	uint16_t wh;
+
+	/* Layer 0 */
+	uint32_t l0m;
+	uint32_t l0oa;
+	uint32_t l0da;
+	uint16_t l0dx;
+	uint16_t l0dy;
+
+	/* Layer 1 */
+	uint32_t l1m;
+	uint32_t cbda0;
+	uint32_t cbda1;
+	uint32_t pad02;
+
+	/* Layer 2 */
+	uint32_t l2m;
+	uint32_t l2oa0;
+	uint32_t l2da0;
+	uint32_t l2oa1;
+	uint32_t l2da1;
+	uint16_t l2dx;
+	uint16_t l2dy;
+
+	/* Layer 3 */
+	uint32_t l3m;
+	uint32_t l3oa0;
+	uint32_t l3da0;
+	uint32_t l3oa1;
+	uint32_t l3da1;
+	uint16_t l3dx;
+	uint16_t l3dy;
+
+	/* Layer 4 */
+	uint32_t l4m;
+	uint32_t l4oa0;
+	uint32_t l4da0;
+	uint32_t l4oa1;
+	uint32_t l4da1;
+	uint16_t l4dx;
+	uint16_t l4dy;
+
+	/* Layer 5 */
+	uint32_t l5m;
+	uint32_t l5oa0;
+	uint32_t l5da0;
+	uint32_t l5oa1;
+	uint32_t l5da1;
+	uint16_t l5dx;
+	uint16_t l5dy;
+
+	/* Cursor */
+	uint16_t cutc;
+	uint8_t  cpm;
+	uint8_t  csize;
+	uint32_t cuoa0;
+	uint16_t cux0;
+	uint16_t cuy0;
+	uint32_t cuoa1;
+	uint16_t cux1;
+	uint16_t cuy1;
+
+	/* Layer blending */
+	uint32_t l0bld;
+	uint32_t pad03;
+	uint32_t l0tc;
+	uint16_t l3tc;
+	uint16_t l2tc;
+	uint32_t pad04[15];
+
+	/* Display settings */
+	uint32_t dcm1;
+	uint32_t dcm2;
+	uint32_t dcm3;
+	uint32_t pad05;
+
+	/* Layer 0 extended */
+	uint32_t l0em;
+	uint16_t l0wx;
+	uint16_t l0wy;
+	uint16_t l0ww;
+	uint16_t l0wh;
+	uint32_t pad06;
+
+	/* Layer 1 extended */
+	uint32_t l1em;
+	uint16_t l1wx;
+	uint16_t l1wy;
+	uint16_t l1ww;
+	uint16_t l1wh;
+	uint32_t pad07;
+
+	/* Layer 2 extended */
+	uint32_t l2em;
+	uint16_t l2wx;
+	uint16_t l2wy;
+	uint16_t l2ww;
+	uint16_t l2wh;
+	uint32_t pad08;
+
+	/* Layer 3 extended */
+	uint32_t l3em;
+	uint16_t l3wx;
+	uint16_t l3wy;
+	uint16_t l3ww;
+	uint16_t l3wh;
+	uint32_t pad09;
+
+	/* Layer 4 extended */
+	uint32_t l4em;
+	uint16_t l4wx;
+	uint16_t l4wy;
+	uint16_t l4ww;
+	uint16_t l4wh;
+	uint32_t pad10;
+
+	/* Layer 5 extended */
+	uint32_t l5em;
+	uint16_t l5wx;
+	uint16_t l5wy;
+	uint16_t l5ww;
+	uint16_t l5wh;
+	uint32_t pad11;
+
+	/* Multi screen control */
+	uint32_t msc;
+	uint32_t pad12[3];
+	uint32_t dls;
+	uint32_t dbgc;
+
+	/* Layer blending */
+	uint32_t l1bld;
+	uint32_t l2bld;
+	uint32_t l3bld;
+	uint32_t l4bld;
+	uint32_t l5bld;
+	uint32_t pad13;
+
+	/* Extended transparency control */
+	uint32_t l0etc;
+	uint32_t l1etc;
+	uint32_t l2etc;
+	uint32_t l3etc;
+	uint32_t l4etc;
+	uint32_t l5etc;
+	uint32_t pad14[10];
+
+	/* YUV coefficients */
+	uint32_t l1ycr0;
+	uint32_t l1ycr1;
+	uint32_t l1ycg0;
+	uint32_t l1ycg1;
+	uint32_t l1ycb0;
+	uint32_t l1ycb1;
+	uint32_t pad15[130];
+
+	/* Layer palletes */
+	uint32_t l0pal[256];
+	uint32_t l1pal[256];
+	uint32_t pad16[256];
+	uint32_t l2pal[256];
+	uint32_t l3pal[256];
+	uint32_t pad17[256];
+
+	/* PWM settings */
+	uint32_t vpwmm;
+	uint16_t vpwms;
+	uint16_t vpwme;
+	uint32_t vpwmc;
+	uint32_t pad18[253];
+};
+
+/* mb86r0x gdc capture controller */
+struct mb86r0x_gdc_cap {
+	uint32_t vcm;
+	uint32_t csc;
+	uint32_t vcs;
+	uint32_t pad01;
+
+	uint32_t cbm;
+	uint32_t cboa;
+	uint32_t cbla;
+	uint16_t cihstr;
+	uint16_t civstr;
+	uint16_t cihend;
+	uint16_t civend;
+	uint32_t pad02;
+
+	uint32_t chp;
+	uint32_t cvp;
+	uint32_t pad03[4];
+
+	uint32_t clpf;
+	uint32_t pad04;
+	uint32_t cmss;
+	uint32_t cmds;
+	uint32_t pad05[12];
+
+	uint32_t rgbhc;
+	uint32_t rgbhen;
+	uint32_t rgbven;
+	uint32_t pad06;
+	uint32_t rgbs;
+	uint32_t pad07[11];
+
+	uint32_t rgbcmy;
+	uint32_t rgbcmcb;
+	uint32_t rgbcmcr;
+	uint32_t rgbcmb;
+	uint32_t pad08[12 + 1984];
+};
+
+/* mb86r0x gdc draw */
+struct mb86r0x_gdc_draw {
+	uint32_t ys;
+	uint32_t xs;
+	uint32_t dxdy;
+	uint32_t xus;
+	uint32_t dxudy;
+	uint32_t xls;
+	uint32_t dxldy;
+	uint32_t usn;
+	uint32_t lsn;
+	uint32_t pad01[7];
+	uint32_t rs;
+	uint32_t drdx;
+	uint32_t drdy;
+	uint32_t gs;
+	uint32_t dgdx;
+	uint32_t dgdy;
+	uint32_t bs;
+	uint32_t dbdx;
+	uint32_t dbdy;
+	uint32_t pad02[7];
+	uint32_t zs;
+	uint32_t dzdx;
+	uint32_t dzdy;
+	uint32_t pad03[13];
+	uint32_t ss;
+	uint32_t dsdx;
+	uint32_t dsdy;
+	uint32_t ts;
+	uint32_t dtdx;
+	uint32_t dtdy;
+	uint32_t qs;
+	uint32_t dqdx;
+	uint32_t dqdy;
+	uint32_t pad04[23];
+	uint32_t lpn;
+	uint32_t lxs;
+	uint32_t lxde;
+	uint32_t lys;
+	uint32_t lyde;
+	uint32_t lzs;
+	uint32_t lzde;
+	uint32_t pad05[13];
+	uint32_t pxdc;
+	uint32_t pydc;
+	uint32_t pzdc;
+	uint32_t pad06[25];
+	uint32_t rxs;
+	uint32_t rys;
+	uint32_t rsizex;
+	uint32_t rsizey;
+	uint32_t pad07[12];
+	uint32_t saddr;
+	uint32_t sstride;
+	uint32_t srx;
+	uint32_t sry;
+	uint32_t daddr;
+	uint32_t dstride;
+	uint32_t drx;
+	uint32_t dry;
+	uint32_t brsizex;
+	uint32_t brsizey;
+	uint32_t tcolor;
+	uint32_t pad08[93];
+	uint32_t blpo;
+	uint32_t pad09[7];
+	uint32_t ctr;
+	uint32_t ifsr;
+	uint32_t ifcnt;
+	uint32_t sst;
+	uint32_t ds;
+	uint32_t pst;
+	uint32_t est;
+	uint32_t pad10;
+	uint32_t mdr0;
+	uint32_t mdr1;
+	uint32_t mdr2;
+	uint32_t mdr3;
+	uint32_t mdr4;
+	uint32_t pad14[2];
+	uint32_t mdr7;
+	uint32_t fbr;
+	uint32_t xres;
+	uint32_t zbr;
+	uint32_t tbr;
+	uint32_t pfbr;
+	uint32_t cxmin;
+	uint32_t cxmax;
+	uint32_t cymin;
+	uint32_t cymax;
+	uint32_t txs;
+	uint32_t tis;
+	uint32_t toa;
+	uint32_t sho;
+	uint32_t abr;
+	uint32_t pad15[2];
+	uint32_t fc;
+	uint32_t bc;
+	uint32_t alf;
+	uint32_t blp;
+	uint32_t pad16;
+	uint32_t tbc;
+	uint32_t pad11[42];
+	uint32_t lx0dc;
+	uint32_t ly0dc;
+	uint32_t lx1dc;
+	uint32_t ly1dc;
+	uint32_t pad12[12];
+	uint32_t x0dc;
+	uint32_t y0dc;
+	uint32_t x1dc;
+	uint32_t y1dc;
+	uint32_t x2dc;
+	uint32_t y2dc;
+	uint32_t pad13[666];
+};
+
+/* mb86r0x gdc geometry engine */
+struct mb86r0x_gdc_geom {
+	uint32_t gctr;
+	uint32_t pad00[15];
+	uint32_t gmdr0;
+	uint32_t gmdr1;
+	uint32_t gmdr2;
+	uint32_t pad01[237];
+	uint32_t dfifog;
+	uint32_t pad02[767];
+};
+
+/* mb86r0x gdc */
+struct mb86r0x_gdc {
+	uint32_t pad00[2];
+	uint32_t lts;
+	uint32_t pad01;
+	uint32_t lsta;
+	uint32_t pad02[3];
+	uint32_t ist;
+	uint32_t imask;
+	uint32_t pad03[6];
+	uint32_t lsa;
+	uint32_t lco;
+	uint32_t lreq;
+
+	uint32_t pad04[16*1024 - 19];
+	struct mb86r0x_gdc_dsp dsp0;
+	struct mb86r0x_gdc_dsp dsp1;
+	uint32_t pad05[4*1024 - 2];
+	uint32_t vccc;
+	uint32_t vcsr;
+	struct mb86r0x_gdc_cap cap0;
+	struct mb86r0x_gdc_cap cap1;
+	uint32_t pad06[4*1024];
+	uint32_t texture_base[16*1024];
+	struct mb86r0x_gdc_draw draw;
+	uint32_t pad07[7*1024];
+	struct mb86r0x_gdc_geom geom;
+	uint32_t pad08[7*1024];
+};
+
+/* mb86r0x ddr2c */
+struct mb86r0x_ddr2c {
+	uint16_t dric;
+	uint16_t dric1;
+	uint16_t dric2;
+	uint16_t drca;
+	uint16_t drcm;
+	uint16_t drcst1;
+	uint16_t drcst2;
+	uint16_t drcr;
+	uint16_t pad00[8];
+	uint16_t drcf;
+	uint16_t pad01[7];
+	uint16_t drasr;
+	uint16_t pad02[15];
+	uint16_t drims;
+	uint16_t pad03[7];
+	uint16_t dros;
+	uint16_t pad04;
+	uint16_t dribsodt1;
+	uint16_t dribsocd;
+	uint16_t dribsocd2;
+	uint16_t pad05[3];
+	uint16_t droaba;
+	uint16_t pad06[9];
+	uint16_t drobs;
+	uint16_t pad07[5];
+	uint16_t drimr1;
+	uint16_t drimr2;
+	uint16_t drimr3;
+	uint16_t drimr4;
+	uint16_t droisr1;
+	uint16_t droisr2;
+};
+
+/* mb86r0x memc */
+struct mb86r0x_memc {
+	uint32_t mcfmode[8];
+	uint32_t mcftim[8];
+	uint32_t mcfarea[8];
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Physical Address Defines
+ */
+#define MB86R0x_DDR2_BASE		0xf3000000
+#define MB86R0x_GDC_BASE		0xf1fc0000
+#define MB86R0x_CCNT_BASE		0xfff42000
+#define MB86R0x_CAN0_BASE		0xfff54000
+#define MB86R0x_CAN1_BASE		0xfff55000
+#define MB86R0x_I2C0_BASE		0xfff56000
+#define MB86R0x_I2C1_BASE		0xfff57000
+#define MB86R0x_EHCI_BASE		0xfff80000
+#define MB86R0x_OHCI_BASE		0xfff81000
+#define MB86R0x_IRC1_BASE		0xfffb0000
+#define MB86R0x_MEMC_BASE		0xfffc0000
+#define MB86R0x_TIMER_BASE		0xfffe0000
+#define MB86R0x_UART0_BASE		0xfffe1000
+#define MB86R0x_UART1_BASE		0xfffe2000
+#define MB86R0x_IRCE_BASE		0xfffe4000
+#define MB86R0x_CRG_BASE		0xfffe7000
+#define MB86R0x_IRC0_BASE		0xfffe8000
+#define MB86R0x_GPIO_BASE		0xfffe9000
+#define MB86R0x_PWM0_BASE		0xfff41000
+#define MB86R0x_PWM1_BASE		0xfff41100
+
+#define MB86R0x_CRSR_SWRSTREQ 		(1 << 1)
+
+/*
+ * Timer register bits
+ */
+#define MB86R0x_TIMER_ENABLE		(1 << 7)
+#define MB86R0x_TIMER_MODE_MSK		(1 << 6)
+#define MB86R0x_TIMER_MODE_FR		(0 << 6)
+#define MB86R0x_TIMER_MODE_PD		(1 << 6)
+
+#define MB86R0x_TIMER_INT_EN		(1 << 5)
+#define MB86R0x_TIMER_PRS_MSK		(3 << 2)
+#define MB86R0x_TIMER_PRS_4S		(1 << 2)
+#define MB86R0x_TIMER_PRS_8S		(1 << 3)
+#define MB86R0x_TIMER_SIZE_32		(1 << 1)
+#define MB86R0x_TIMER_ONE_SHT		(1 << 0)
+
+/*
+ * Clock reset generator bits
+ */
+#define MB86R0x_CRG_CRPR_PLLRDY		(1 << 8)
+#define MB86R0x_CRG_CRPR_PLLMODE	(0x1f << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X49	(0 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X46	(1 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X37	(2 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X20	(3 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X47	(4 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X44	(5 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X36	(6 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X19	(7 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X39	(8 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X38	(9 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X30	(10 << 0)
+#define MB86R0x_CRG_CRPR_PLLMODE_X15	(11 << 0)
+/*
+ * DDR2 controller bits
+ */
+#define MB86R0x_DDR2_DRCI_DRINI		(1 << 15)
+#define MB86R0x_DDR2_DRCI_CKEN		(1 << 14)
+#define MB86R0x_DDR2_DRCI_DRCMD		(1 << 0)
+#define MB86R0x_DDR2_DRCI_CMD		(MB86R0x_DDR2_DRCI_DRINI | \
+					MB86R0x_DDR2_DRCI_CKEN | \
+					MB86R0x_DDR2_DRCI_DRCMD)
+#define MB86R0x_DDR2_DRCI_INIT		(MB86R0x_DDR2_DRCI_DRINI | \
+					MB86R0x_DDR2_DRCI_CKEN)
+#define MB86R0x_DDR2_DRCI_NORMAL	MB86R0x_DDR2_DRCI_CKEN
+#endif /* MB86R0X_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h
new file mode 100644
index 000000000..9fdaa9dc0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/clock.h
@@ -0,0 +1,59 @@
+/*
+ *
+ * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
+ *
+ * Modified for mx25 by John Rigby <jrigby@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+#ifdef CONFIG_MX25_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX25_HCLK_FREQ
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_MX25_CLK32
+#define MXC_CLK32	CONFIG_MX25_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
+enum mxc_clock {
+	/* PER clocks (do not change order) */
+	MXC_CSI_CLK,
+	MXC_EPIT_CLK,
+	MXC_ESAI_CLK,
+	MXC_ESDHC1_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_GPT_CLK,
+	MXC_I2C_CLK,
+	MXC_LCDC_CLK,
+	MXC_NFC_CLK,
+	MXC_OWIRE_CLK,
+	MXC_PWM_CLK,
+	MXC_SIM1_CLK,
+	MXC_SIM2_CLK,
+	MXC_SSI1_CLK,
+	MXC_SSI2_CLK,
+	MXC_UART_CLK,
+	/* Other clocks */
+	MXC_ARM_CLK,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_CSPI_CLK,
+	MXC_FEC_CLK,
+	MXC_CLK_NUM
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#define imx_get_uartclk()	mxc_get_clock(MXC_UART_CLK)
+#define imx_get_fecclk()	mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h
new file mode 100644
index 000000000..81d95ea48
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/gpio.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __ASM_ARCH_MX25_GPIO_H
+#define __ASM_ARCH_MX25_GPIO_H
+
+#include <asm/imx-common/gpio.h>
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h
new file mode 100644
index 000000000..a17f82834
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -0,0 +1,358 @@
+/*
+ * Copyright (C) 2009, DENX Software Engineering
+ * Author: John Rigby <jcrigby@gmail.com
+ *
+ *   Based on arch-mx31/imx-regs.h
+ *	Copyright (C) 2009 Ilya Yanok,
+ *		Emcraft Systems <yanok@emcraft.com>
+ *   and arch-mx27/imx-regs.h
+ *	Copyright (C) 2007 Pengutronix,
+ *		Sascha Hauer <s.hauer@pengutronix.de>
+ *	Copyright (C) 2009 Ilya Yanok,
+ *		Emcraft Systems <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* Clock Control Module (CCM) registers */
+struct ccm_regs {
+	u32 mpctl;	/* Core PLL Control */
+	u32 upctl;	/* USB PLL Control */
+	u32 cctl;	/* Clock Control */
+	u32 cgr0;	/* Clock Gating Control 0 */
+	u32 cgr1;	/* Clock Gating Control 1 */
+	u32 cgr2;	/* Clock Gating Control 2 */
+	u32 pcdr[4];	/* PER Clock Dividers */
+	u32 rcsr;	/* CCM Status */
+	u32 crdr;	/* CCM Reset and Debug */
+	u32 dcvr0;	/* DPTC Comparator Value 0 */
+	u32 dcvr1;	/* DPTC Comparator Value 1 */
+	u32 dcvr2;	/* DPTC Comparator Value 2 */
+	u32 dcvr3;	/* DPTC Comparator Value 3 */
+	u32 ltr0;	/* Load Tracking 0 */
+	u32 ltr1;	/* Load Tracking 1 */
+	u32 ltr2;	/* Load Tracking 2 */
+	u32 ltr3;	/* Load Tracking 3 */
+	u32 ltbr0;	/* Load Tracking Buffer 0 */
+	u32 ltbr1;	/* Load Tracking Buffer 1 */
+	u32 pcmr0;	/* Power Management Control 0 */
+	u32 pcmr1;	/* Power Management Control 1 */
+	u32 pcmr2;	/* Power Management Control 2 */
+	u32 mcr;	/* Miscellaneous Control */
+	u32 lpimr0;	/* Low Power Interrupt Mask 0 */
+	u32 lpimr1;	/* Low Power Interrupt Mask 1 */
+};
+
+/* Enhanced SDRAM Controller (ESDRAMC) registers */
+struct esdramc_regs {
+	u32 ctl0; 	/* control 0 */
+	u32 cfg0; 	/* configuration 0 */
+	u32 ctl1; 	/* control 1 */
+	u32 cfg1; 	/* configuration 1 */
+	u32 misc; 	/* miscellaneous */
+	u32 pad[3];
+	u32 cdly1;	/* Delay Line 1 configuration debug */
+	u32 cdly2;	/* delay line 2 configuration debug */
+	u32 cdly3;	/* delay line 3 configuration debug */
+	u32 cdly4;	/* delay line 4 configuration debug */
+	u32 cdly5;	/* delay line 5 configuration debug */
+	u32 cdlyl;	/* delay line cycle length debug */
+};
+
+/* General Purpose Timer (GPT) registers */
+struct gpt_regs {
+	u32 ctrl;   	/* control */
+	u32 pre;    	/* prescaler */
+	u32 stat;   	/* status */
+	u32 intr;   	/* interrupt */
+	u32 cmp[3]; 	/* output compare 1-3 */
+	u32 capt[2];	/* input capture 1-2 */
+	u32 counter;	/* counter */
+};
+
+/* Watchdog Timer (WDOG) registers */
+struct wdog_regs {
+	u16 wcr;	/* Control */
+	u16 wsr;	/* Service */
+	u16 wrsr;	/* Reset Status */
+	u16 wicr;	/* Interrupt Control */
+	u16 wmcr;	/* Misc Control */
+};
+
+/* IIM control registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prg_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+	u32 res1[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[3];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_7[8];
+	u32 uid[8];
+	u32 fuse16_25[0xa];
+	u32 mac_addr[6];
+};
+
+struct fuse_bank1_regs {
+	u32 fuse0_21[0x16];
+	u32 usr5;
+	u32 fuse23_29[7];
+	u32 usr6[2];
+};
+
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+	u32 mpr0;
+	u32 pad00[3];
+	u32 sgpcr0;
+	u32 pad01[59];
+	u32 mpr1;
+	u32 pad02[3];
+	u32 sgpcr1;
+	u32 pad03[59];
+	u32 mpr2;
+	u32 pad04[3];
+	u32 sgpcr2;
+	u32 pad05[59];
+	u32 mpr3;
+	u32 pad06[3];
+	u32 sgpcr3;
+	u32 pad07[59];
+	u32 mpr4;
+	u32 pad08[3];
+	u32 sgpcr4;
+	u32 pad09[251];
+	u32 mgpcr0;
+	u32 pad10[63];
+	u32 mgpcr1;
+	u32 pad11[63];
+	u32 mgpcr2;
+	u32 pad12[63];
+	u32 mgpcr3;
+	u32 pad13[63];
+	u32 mgpcr4;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+	u32 mpr_0_7;
+	u32 mpr_8_15;
+};
+
+#endif
+
+#define ARCH_MXC
+
+/* AIPS 1 */
+#define IMX_AIPS1_BASE		(0x43F00000)
+#define IMX_MAX_BASE		(0x43F04000)
+#define IMX_CLKCTL_BASE		(0x43F08000)
+#define IMX_ETB_SLOT4_BASE	(0x43F0C000)
+#define IMX_ETB_SLOT5_BASE	(0x43F10000)
+#define IMX_ECT_CTIO_BASE	(0x43F18000)
+#define IMX_I2C_BASE		(0x43F80000)
+#define IMX_I2C3_BASE		(0x43F84000)
+#define IMX_CAN1_BASE		(0x43F88000)
+#define IMX_CAN2_BASE		(0x43F8C000)
+#define UART1_BASE		(0x43F90000)
+#define UART2_BASE		(0x43F94000)
+#define IMX_I2C2_BASE		(0x43F98000)
+#define IMX_OWIRE_BASE		(0x43F9C000)
+#define IMX_CSPI1_BASE		(0x43FA4000)
+#define IMX_KPP_BASE		(0x43FA8000)
+#define IMX_IOPADMUX_BASE	(0x43FAC000)
+#define IOMUXC_BASE_ADDR	IMX_IOPADMUX_BASE
+#define IMX_IOPADCTL_BASE	(0x43FAC22C)
+#define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
+#define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
+#define IMX_AUDMUX_BASE		(0x43FB0000)
+#define IMX_ECT_IP1_BASE	(0x43FB8000)
+#define IMX_ECT_IP2_BASE	(0x43FBC000)
+
+/* SPBA */
+#define IMX_SPBA_BASE		(0x50000000)
+#define IMX_CSPI3_BASE		(0x50004000)
+#define UART4_BASE		(0x50008000)
+#define UART3_BASE		(0x5000C000)
+#define IMX_CSPI2_BASE		(0x50010000)
+#define IMX_SSI2_BASE		(0x50014000)
+#define IMX_ESAI_BASE		(0x50018000)
+#define IMX_ATA_DMA_BASE	(0x50020000)
+#define IMX_SIM1_BASE		(0x50024000)
+#define IMX_SIM2_BASE		(0x50028000)
+#define UART5_BASE		(0x5002C000)
+#define IMX_TSC_BASE		(0x50030000)
+#define IMX_SSI1_BASE		(0x50034000)
+#define IMX_FEC_BASE		(0x50038000)
+#define IMX_SPBA_CTRL_BASE	(0x5003C000)
+
+/* AIPS 2 */
+#define IMX_AIPS2_BASE		(0x53F00000)
+#define IMX_CCM_BASE		(0x53F80000)
+#define IMX_GPT4_BASE		(0x53F84000)
+#define IMX_GPT3_BASE		(0x53F88000)
+#define IMX_GPT2_BASE		(0x53F8C000)
+#define IMX_GPT1_BASE		(0x53F90000)
+#define IMX_EPIT1_BASE		(0x53F94000)
+#define IMX_EPIT2_BASE		(0x53F98000)
+#define IMX_GPIO4_BASE		(0x53F9C000)
+#define IMX_PWM2_BASE		(0x53FA0000)
+#define IMX_GPIO3_BASE		(0x53FA4000)
+#define IMX_PWM3_BASE		(0x53FA8000)
+#define IMX_SCC_BASE		(0x53FAC000)
+#define IMX_SCM_BASE		(0x53FAE000)
+#define IMX_SMN_BASE		(0x53FAF000)
+#define IMX_RNGD_BASE		(0x53FB0000)
+#define IMX_MMC_SDHC1_BASE	(0x53FB4000)
+#define IMX_MMC_SDHC2_BASE	(0x53FB8000)
+#define IMX_LCDC_BASE		(0x53FBC000)
+#define IMX_SLCDC_BASE		(0x53FC0000)
+#define IMX_PWM4_BASE		(0x53FC8000)
+#define IMX_GPIO1_BASE		(0x53FCC000)
+#define IMX_GPIO2_BASE		(0x53FD0000)
+#define IMX_SDMA_BASE		(0x53FD4000)
+#define IMX_WDT_BASE		(0x53FDC000)
+#define IMX_PWM1_BASE		(0x53FE0000)
+#define IMX_RTIC_BASE		(0x53FEC000)
+#define IMX_IIM_BASE		(0x53FF0000)
+#define IIM_BASE_ADDR		IMX_IIM_BASE
+#define IMX_USB_BASE		(0x53FF4000)
+#define IMX_USB_PORT_OFFSET	0x200
+#define IMX_CSI_BASE		(0x53FF8000)
+#define IMX_DRYICE_BASE		(0x53FFC000)
+
+#define IMX_ARM926_ROMPATCH	(0x60000000)
+#define IMX_ARM926_ASIC		(0x68000000)
+
+/* 128K Internal Static RAM */
+#define IMX_RAM_BASE		(0x78000000)
+#define IMX_RAM_SIZE		(128 * 1024)
+
+/* SDRAM BANKS */
+#define IMX_SDRAM_BANK0_BASE	(0x80000000)
+#define IMX_SDRAM_BANK1_BASE	(0x90000000)
+
+#define IMX_WEIM_CS0		(0xA0000000)
+#define IMX_WEIM_CS1		(0xA8000000)
+#define IMX_WEIM_CS2		(0xB0000000)
+#define IMX_WEIM_CS3		(0xB2000000)
+#define IMX_WEIM_CS4		(0xB4000000)
+#define IMX_ESDRAMC_BASE	(0xB8001000)
+#define IMX_WEIM_CTRL_BASE	(0xB8002000)
+#define IMX_M3IF_CTRL_BASE	(0xB8003000)
+#define IMX_EMI_CTRL_BASE	(0xB8004000)
+
+/* NAND Flash Controller */
+#define IMX_NFC_BASE		(0xBB000000)
+#define NFC_BASE_ADDR		IMX_NFC_BASE
+
+/* CCM bitfields */
+#define CCM_PLL_MFI_SHIFT	10
+#define CCM_PLL_MFI_MASK	0xf
+#define CCM_PLL_MFN_SHIFT	0
+#define CCM_PLL_MFN_MASK	0x3ff
+#define CCM_PLL_MFD_SHIFT	16
+#define CCM_PLL_MFD_MASK	0x3ff
+#define CCM_PLL_PD_SHIFT	26
+#define CCM_PLL_PD_MASK		0xf
+#define CCM_CCTL_ARM_DIV_SHIFT	30
+#define CCM_CCTL_ARM_DIV_MASK	3
+#define CCM_CCTL_AHB_DIV_SHIFT	28
+#define CCM_CCTL_AHB_DIV_MASK	3
+#define CCM_CCTL_ARM_SRC	(1 << 14)
+#define CCM_CGR1_GPT1		(1 << 19)
+#define CCM_PERCLK_REG(clk)	(clk / 4)
+#define CCM_PERCLK_SHIFT(clk)	(8 * (clk % 4))
+#define CCM_PERCLK_MASK		0x3f
+#define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
+#define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)
+
+/* ESDRAM Controller register bitfields */
+#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
+#define ESDCTL_BL		(1 << 7)
+#define ESDCTL_FP		(1 << 8)
+#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
+#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
+#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
+#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
+#define ESDCTL_DSIZ_32		(2 << 16)
+#define ESDCTL_COL8		(0 << 20)
+#define ESDCTL_COL9		(1 << 20)
+#define ESDCTL_COL10		(2 << 20)
+#define ESDCTL_ROW11		(0 << 24)
+#define ESDCTL_ROW12		(1 << 24)
+#define ESDCTL_ROW13		(2 << 24)
+#define ESDCTL_ROW14		(3 << 24)
+#define ESDCTL_ROW15		(4 << 24)
+#define ESDCTL_SP		(1 << 27)
+#define ESDCTL_SMODE_NORMAL	(0 << 28)
+#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
+#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
+#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
+#define ESDCTL_SMODE_MAN_REF	(4 << 28)
+#define ESDCTL_SDE		(1 << 31)
+
+#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
+#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
+#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
+#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
+#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
+#define ESDCFG_TWR		(1 << 15)
+#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
+#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
+#define ESDCFG_TWTR		(1 << 20)
+#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
+
+#define ESDMISC_RST		(1 << 1)
+#define ESDMISC_MDDREN		(1 << 2)
+#define ESDMISC_MDDR_DL_RST	(1 << 3)
+#define ESDMISC_MDDR_MDIS	(1 << 4)
+#define ESDMISC_LHD		(1 << 5)
+#define ESDMISC_MA10_SHARE	(1 << 6)
+#define ESDMISC_SDRAM_RDY	(1 << 31)
+
+/* GPT bits */
+#define GPT_CTRL_SWR		(1 << 15)	/* Software reset */
+#define GPT_CTRL_FRR		(1 << 9)	/* Freerun / restart */
+#define GPT_CTRL_CLKSOURCE_32	(4 << 6)	/* Clock source	*/
+#define GPT_CTRL_TEN		1		/* Timer enable	*/
+
+/* WDOG enable */
+#define WCR_WDE 		0x04
+#define WSR_UNLOCK1		0x5555
+#define WSR_UNLOCK2		0xAAAA
+
+/* Names used in GPIO driver */
+#define GPIO1_BASE_ADDR		IMX_GPIO1_BASE
+#define GPIO2_BASE_ADDR		IMX_GPIO2_BASE
+#define GPIO3_BASE_ADDR		IMX_GPIO3_BASE
+#define GPIO4_BASE_ADDR		IMX_GPIO4_BASE
+
+#define CHIP_REV_1_0		0x10
+#define CHIP_REV_1_1		0x11
+#define CHIP_REV_1_2		0x12
+
+#endif				/* _IMX_REGS_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h
new file mode 100644
index 000000000..220cf4ef2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/iomux-mx25.h
@@ -0,0 +1,529 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on mainline Linux i.MX iomux-mx25.h file:
+ * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
+ *
+ * Based on Linux arch/arm/mach-mx25/mx25_pins.h:
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IOMUX_MX25_H__
+#define __IOMUX_MX25_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX25_KPP_ROW_PAD_CTRL	PAD_CTL_PUS_100K_UP
+#define MX25_KPP_COL_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+/*
+ * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*							    PAD    MUX    ALT INPSE PATH PADCTRL */
+enum {
+	MX25_PAD_A10__A10			= IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A10__GPIO_4_0			= IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A13__A13			= IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A13__GPIO_4_1			= IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A14__A14			= IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A14__GPIO_2_0			= IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A15__A15			= IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A15__GPIO_2_1			= IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A16__A16			= IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A16__GPIO_2_2			= IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A17__A17			= IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A17__GPIO_2_3			= IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A18__A18			= IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A18__GPIO_2_4			= IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A18__FEC_COL			= IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A19__A19			= IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A19__FEC_RX_ER			= IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL),
+	MX25_PAD_A19__GPIO_2_5			= IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A20__A20			= IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A20__GPIO_2_6			= IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A20__FEC_RDATA2		= IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A21__A21			= IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A21__GPIO_2_7			= IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A21__FEC_RDATA3		= IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A22__A22			= IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A22__GPIO_2_8			= IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A23__A23			= IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A23__GPIO_2_9			= IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A24__A24			= IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A24__GPIO_2_10			= IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A24__FEC_RX_CLK		= IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A25__A25			= IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A25__GPIO_2_11			= IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A25__FEC_CRS			= IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL),
+
+	MX25_PAD_EB0__EB0			= IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EB0__AUD4_TXD			= IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL),
+	MX25_PAD_EB0__GPIO_2_12			= IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_EB1__EB1			= IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EB1__AUD4_RXD			= IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL),
+	MX25_PAD_EB1__GPIO_2_13			= IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_OE__OE				= IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE__AUD4_TXC			= IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE__GPIO_2_14			= IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS0__CS0			= IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS0__GPIO_4_2			= IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS1__CS1			= IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS1__NF_CE3			= IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS1__GPIO_4_3			= IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS4__CS4			= IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__NF_CE1			= IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__UART5_CTS			= IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__GPIO_3_20			= IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS5__CS5			= IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__NF_CE2			= IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__UART5_RTS			= IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__GPIO_3_21			= IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NF_CE0__NF_CE0			= IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NF_CE0__GPIO_3_22		= IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_ECB__ECB			= IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_ECB__UART5_TXD_MUX		= IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_ECB__GPIO_3_23			= IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LBA__LBA			= IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LBA__UART5_RXD_MUX		= IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL),
+	MX25_PAD_LBA__GPIO_3_24			= IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_BCLK__BCLK			= IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BCLK__GPIO_4_4			= IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_RW__RW				= IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RW__AUD4_TXFS			= IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL),
+	MX25_PAD_RW__GPIO_3_25			= IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFWE_B__NFWE_B			= IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFWE_B__GPIO_3_26		= IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFRE_B__NFRE_B			= IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFRE_B__GPIO_3_27		= IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFALE__NFALE			= IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFALE__GPIO_3_28		= IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFCLE__NFCLE			= IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFCLE__GPIO_3_29		= IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFWP_B__NFWP_B			= IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFWP_B__GPIO_3_30		= IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFRB__NFRB			= IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE),
+	MX25_PAD_NFRB__GPIO_3_31		= IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D15__D15			= IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D15__LD16			= IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_D15__GPIO_4_5			= IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D14__D14			= IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D14__LD17			= IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_D14__GPIO_4_6			= IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D13__D13			= IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D13__LD18			= IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_D13__GPIO_4_7			= IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D12__D12			= IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D12__GPIO_4_8			= IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D11__D11			= IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D11__GPIO_4_9			= IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D10__D10			= IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D10__GPIO_4_10			= IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D10__USBOTG_OC			= IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_D9__D9				= IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D9__GPIO_4_11			= IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D9__USBH2_PWR			= IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
+
+	MX25_PAD_D8__D8				= IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D8__GPIO_4_12			= IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D8__USBH2_OC			= IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_D7__D7				= IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D7__GPIO_4_13			= IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D6__D6				= IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D6__GPIO_4_14			= IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D5__D5				= IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D5__GPIO_4_15			= IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D4__D4				= IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D4__GPIO_4_16			= IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D3__D3				= IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D3__GPIO_4_17			= IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D2__D2				= IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D2__GPIO_4_18			= IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D1__D1				= IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D1__GPIO_4_19			= IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D0__D0				= IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D0__GPIO_4_20			= IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD0__LD0			= IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD0__CSI_D0			= IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL),
+	MX25_PAD_LD0__GPIO_2_15			= IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD1__LD1			= IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD1__CSI_D1			= IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL),
+	MX25_PAD_LD1__GPIO_2_16			= IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD2__LD2			= IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD2__GPIO_2_17			= IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD3__LD3			= IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD3__GPIO_2_18			= IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD4__LD4			= IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD4__GPIO_2_19			= IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD5__LD5			= IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD5__GPIO_1_19			= IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD6__LD6			= IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD6__GPIO_1_20			= IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD7__LD7			= IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD7__GPIO_1_21			= IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD8__LD8			= IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD8__FEC_TX_ERR		= IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD9__LD9			= IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD9__FEC_COL			= IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD10__LD10			= IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD10__FEC_RX_ER		= IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD11__LD11			= IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD11__FEC_RDATA2		= IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD12__LD12			= IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD12__FEC_RDATA3		= IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD13__LD13			= IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD13__FEC_TDATA2		= IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD14__LD14			= IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD14__FEC_TDATA3		= IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD15__LD15			= IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD15__FEC_RX_CLK		= IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL),
+
+	MX25_PAD_HSYNC__HSYNC			= IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_HSYNC__GPIO_1_22		= IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_VSYNC__VSYNC			= IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSYNC__GPIO_1_23		= IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LSCLK__LSCLK			= IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LSCLK__GPIO_1_24		= IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_OE_ACD__OE_ACD			= IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE_ACD__GPIO_1_25		= IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CONTRAST__CONTRAST		= IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CONTRAST__PWM4_PWMO		= IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CONTRAST__FEC_CRS		= IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL),
+
+	MX25_PAD_PWM__PWM			= IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_PWM__GPIO_1_26			= IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_PWM__USBH2_OC			= IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_CSI_D2__CSI_D2			= IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__UART5_RXD_MUX		= IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__GPIO_1_27		= IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__CSPI3_MOSI		= IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D3__CSI_D3			= IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D3__GPIO_1_28		= IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D3__CSPI3_MISO		= IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D4__CSI_D4			= IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__UART5_RTS		= IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__GPIO_1_29		= IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__CSPI3_SCLK		= IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D5__CSI_D5			= IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D5__GPIO_1_30		= IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D5__CSPI3_RDY		= IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D6__CSI_D6			= IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D6__GPIO_1_31		= IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D7__CSI_D7			= IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D7__GPIO_1_6		= IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D8__CSI_D8			= IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D8__GPIO_1_7		= IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D9__CSI_D9			= IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D9__GPIO_4_21		= IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_MCLK__CSI_MCLK		= IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_MCLK__GPIO_1_8		= IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_VSYNC__CSI_VSYNC		= IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_VSYNC__GPIO_1_9		= IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_HSYNC__CSI_HSYNC		= IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_HSYNC__GPIO_1_10		= IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_PIXCLK__CSI_PIXCLK		= IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_PIXCLK__GPIO_1_11		= IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_I2C1_CLK__I2C1_CLK		= IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_I2C1_CLK__GPIO_1_12		= IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_I2C1_DAT__I2C1_DAT		= IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_I2C1_DAT__GPIO_1_13		= IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		= IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MOSI__GPIO_1_14		= IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_MISO__CSPI1_MISO		= IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MISO__GPIO_1_15		= IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_SS0__CSPI1_SS0		= IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS0__GPIO_1_16		= IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_SS1__CSPI1_SS1		= IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS1__I2C3_DAT		= IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS1__GPIO_1_17		= IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_SCLK__CSPI1_SCLK		= IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SCLK__GPIO_1_18		= IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_RDY__CSPI1_RDY		= IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE),
+	MX25_PAD_CSPI1_RDY__GPIO_2_22		= IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_RXD__UART1_RXD		= IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_UART1_RXD__GPIO_4_22		= IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_TXD__UART1_TXD		= IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART1_TXD__GPIO_4_23		= IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_UART1_RTS__CSI_D0		= IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL),
+	MX25_PAD_UART1_RTS__GPIO_4_24		= IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_CTS__UART1_CTS		= IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_UART1_CTS__CSI_D1		= IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL),
+	MX25_PAD_UART1_CTS__GPIO_4_25		= IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_RXD__UART2_RXD		= IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_RXD__GPIO_4_26		= IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_TXD__UART2_TXD		= IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_TXD__GPIO_4_27		= IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_RTS__UART2_RTS		= IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_RTS__FEC_COL		= IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL),
+	MX25_PAD_UART2_RTS__GPIO_4_28		= IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_CTS__FEC_RX_ER		= IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL),
+	MX25_PAD_UART2_CTS__UART2_CTS		= IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_CTS__GPIO_4_29		= IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_CMD__SD1_CMD		= IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_CMD__FEC_RDATA2		= IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_CMD__GPIO_2_23		= IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_CLK__SD1_CLK		= IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_CLK__FEC_RDATA3		= IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_CLK__GPIO_2_24		= IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA0__SD1_DATA0		= IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA0__GPIO_2_25		= IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA1__SD1_DATA1		= IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA1__AUD7_RXD		= IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA1__GPIO_2_26		= IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA2__SD1_DATA2		= IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA2__FEC_RX_CLK		= IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA2__GPIO_2_27		= IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA3__SD1_DATA3		= IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA3__FEC_CRS		= IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA3__GPIO_2_28		= IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW0__KPP_ROW0		= IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW0__GPIO_2_29		= IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW1__KPP_ROW1		= IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW1__GPIO_2_30		= IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW2__KPP_ROW2		= IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__CSI_D0		= IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__GPIO_2_31		= IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW3__KPP_ROW3		= IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW3__CSI_LD1		= IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW3__GPIO_3_0		= IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL0__KPP_COL0		= IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL0__UART4_RXD_MUX	= IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL0__AUD5_TXD		= IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL0__GPIO_3_1		= IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL1__KPP_COL1		= IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL1__UART4_TXD_MUX	= IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL1__AUD5_RXD		= IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL1__GPIO_3_2		= IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL2__KPP_COL2		= IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL2__UART4_RTS		= IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL2__AUD5_TXC		= IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL2__GPIO_3_3		= IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL3__KPP_COL3		= IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL3__UART4_CTS		= IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL3__AUD5_TXFS		= IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL3__GPIO_3_4		= IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_MDC__FEC_MDC		= IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDC__AUD4_TXD		= IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDC__GPIO_3_5		= IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_MDIO__FEC_MDIO		= IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
+	MX25_PAD_FEC_MDIO__AUD4_RXD		= IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDIO__GPIO_3_6		= IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TDATA0__FEC_TDATA0		= IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA0__GPIO_3_7		= IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TDATA1__FEC_TDATA1		= IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA1__AUD4_TXFS		= IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA1__GPIO_3_8		= IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TX_EN__FEC_TX_EN		= IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TX_EN__GPIO_3_9		= IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_RDATA0__FEC_RDATA0		= IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RDATA0__GPIO_3_10		= IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_RDATA1__FEC_RDATA1		= IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RDATA1__GPIO_3_11		= IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_RX_DV__FEC_RX_DV		= IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RX_DV__CAN2_RX		= IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_FEC_RX_DV__GPIO_3_12		= IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		= IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_TX_CLK__GPIO_3_13		= IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_RTCK__RTCK			= IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RTCK__OWIRE			= IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RTCK__GPIO_3_14		= IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_DE_B__DE_B			= IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_DE_B__GPIO_2_20		= IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_TDO__TDO			= IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_GPIO_A__GPIO_A			= IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_A__CAN1_TX		= IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_GPIO_A__USBOTG_PWR		= IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE),
+
+	MX25_PAD_GPIO_B__GPIO_B			= IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_B__CAN1_RX		= IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_GPIO_B__USBOTG_OC		= IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_GPIO_C__GPIO_C			= IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_C__CAN2_TX		= IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
+
+	MX25_PAD_GPIO_D__GPIO_D			= IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_E__LD16			= IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_GPIO_D__CAN2_RX		= IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP),
+
+	MX25_PAD_GPIO_E__GPIO_E			= IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_F__LD17			= IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_GPIO_E__I2C3_CLK		= IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL),
+	MX25_PAD_GPIO_E__AUD7_TXD		= IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_GPIO_F__GPIO_F			= IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_F__AUD7_TXC		= IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_EXT_ARMCLK__EXT_ARMCLK		= IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EXT_ARMCLK__GPIO_3_15		= IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK	= IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UPLL_BYPCLK__GPIO_3_16		= IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_VSTBY_REQ__VSTBY_REQ		= IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_REQ__AUD7_TXFS		= IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_REQ__GPIO_3_17		= IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_ACK__VSTBY_ACK		= IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_ACK__GPIO_3_18		= IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_POWER_FAIL__POWER_FAIL		= IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_POWER_FAIL__AUD7_RXD		= IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL),
+	MX25_PAD_POWER_FAIL__GPIO_3_19		= IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CLKO__CLKO			= IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CLKO__GPIO_2_21		= IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_BOOT_MODE0__BOOT_MODE0		= IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BOOT_MODE0__GPIO_4_30		= IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BOOT_MODE1__BOOT_MODE1		= IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BOOT_MODE1__GPIO_4_31		= IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CTL_GRP_DVS_MISC		= IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_FEC		= IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_JTAG		= IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_NFC		= IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_CSI		= IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_WEIM		= IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_DDR		= IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_CRM		= IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_KPP		= IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_SDHC1		= IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_LCD		= IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_UART		= IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_NFC		= IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_CSI		= IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_CSPI1		= IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DDRTYPE		= IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_SDHC1		= IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_LCD		= IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX25_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h
new file mode 100644
index 000000000..6c41ea038
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx25/macro.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2011
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Common asm macros for imx25
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_MACRO_H__
+#define __ASM_ARM_ARCH_MACRO_H__
+#ifdef __ASSEMBLY__
+
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+#include <asm/macro.h>
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ *
+ * Default argument values:
+ *  - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
+ *    user-mode.
+ */
+.macro init_aips mpr=0x77777777
+	ldr	r0, =IMX_AIPS1_BASE
+	ldr	r1, =\mpr
+	str	r1, [r0, #AIPS_MPR_0_7]
+	str	r1, [r0, #AIPS_MPR_8_15]
+	ldr	r2, =IMX_AIPS2_BASE
+	str	r1, [r2, #AIPS_MPR_0_7]
+	str	r1, [r2, #AIPS_MPR_8_15]
+.endm
+
+/*
+ * MAX (Multi-Layer AHB Crossbar Switch) setup
+ *
+ * Default argument values:
+ *  - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
+ *  - SGPCR: always park on last master
+ *  - MGPCR: restore default values
+ */
+.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
+	ldr	r0, =IMX_MAX_BASE
+	ldr	r1, =\mpr
+	str	r1, [r0, #MAX_MPR0]	/* for S0 */
+	str	r1, [r0, #MAX_MPR1]	/* for S1 */
+	str	r1, [r0, #MAX_MPR2]	/* for S2 */
+	str	r1, [r0, #MAX_MPR3]	/* for S3 */
+	str	r1, [r0, #MAX_MPR4]	/* for S4 */
+	ldr	r1, =\sgpcr
+	str	r1, [r0, #MAX_SGPCR0]	/* for S0 */
+	str	r1, [r0, #MAX_SGPCR1]	/* for S1 */
+	str	r1, [r0, #MAX_SGPCR2]	/* for S2 */
+	str	r1, [r0, #MAX_SGPCR3]	/* for S3 */
+	str	r1, [r0, #MAX_SGPCR4]	/* for S4 */
+	ldr	r1, =\mgpcr
+	str	r1, [r0, #MAX_MGPCR0]	/* for M0 */
+	str	r1, [r0, #MAX_MGPCR1]	/* for M1 */
+	str	r1, [r0, #MAX_MGPCR2]	/* for M2 */
+	str	r1, [r0, #MAX_MGPCR3]	/* for M3 */
+	str	r1, [r0, #MAX_MGPCR4]	/* for M4 */
+.endm
+
+/*
+ * M3IF setup
+ *
+ * Default argument values:
+ *  - CTL:
+ * MRRP[0] = LCDC on priority list (1 << 0)			= 0x00000001
+ * MRRP[1] = MAX1 not on priority list (0 << 1)			= 0x00000000
+ * MRRP[2] = MAX0 not on priority list (0 << 2)			= 0x00000000
+ * MRRP[3] = USBH not on priority list (0 << 3)			= 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 4)			= 0x00000000
+ * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5)	= 0x00000000
+ * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6)	= 0x00000000
+ * MRRP[7] = CSI not on priority list (0 << 7)			= 0x00000000
+ *								------------
+ *								  0x00000001
+ */
+.macro init_m3if ctl=0x00000001
+	/* M3IF Control Register (M3IFCTL) */
+	write32	IMX_M3IF_CTRL_BASE, \ctl
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_ARCH_MACRO_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h
new file mode 100644
index 000000000..c174bd04c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/clock.h
@@ -0,0 +1,23 @@
+/*
+ *
+ * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum mxc_clock {
+	MXC_ARM_CLK,
+	MXC_I2C_CLK,
+	MXC_UART_CLK,
+	MXC_ESDHC_CLK,
+	MXC_FEC_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/gpio.h
new file mode 100644
index 000000000..1e38b9319
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/gpio.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2012
+ * Philippe Reynes <tremyfr@yahoo.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __ASM_ARCH_MX27_GPIO_H
+#define __ASM_ARCH_MX27_GPIO_H
+
+/* GPIO registers */
+struct gpio_regs {
+	u32 gpio_dir; /* DDIR */
+	u32 ocr1;
+	u32 ocr2;
+	u32 iconfa1;
+	u32 iconfa2;
+	u32 iconfb1;
+	u32 iconfb2;
+	u32 gpio_dr; /* DR */
+	u32 gius;
+	u32 gpio_psr; /* SSR */
+	u32 icr1;
+	u32 icr2;
+	u32 imr;
+	u32 isr;
+	u32 gpr;
+	u32 swr;
+	u32 puen;
+	u32 res[0x2f];
+};
+
+/* This structure is used by the function imx_gpio_mode */
+struct gpio_port_regs {
+	struct gpio_regs port[6];
+};
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/imx-regs.h
new file mode 100644
index 000000000..92c847e44
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -0,0 +1,503 @@
+/*
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+
+#include <asm/arch/regs-rtc.h>
+
+#ifndef __ASSEMBLY__
+
+extern void imx_gpio_mode (int gpio_mode);
+
+#ifdef CONFIG_MXC_UART
+extern void mx27_uart1_init_pins(void);
+#endif /* CONFIG_MXC_UART */
+
+#ifdef CONFIG_FEC_MXC
+extern void mx27_fec_init_pins(void);
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_MXC_MMC
+extern void mx27_sd1_init_pins(void);
+extern void mx27_sd2_init_pins(void);
+#endif /* CONFIG_MXC_MMC */
+
+/* AIPI */
+struct aipi_regs {
+	u32 psr0;
+	u32 psr1;
+};
+
+/* System Control */
+struct system_control_regs {
+	u32 res[5];
+	u32 fmcr;
+	u32 gpcr;
+	u32 wbcr;
+	u32 dscr1;
+	u32 dscr2;
+	u32 dscr3;
+	u32 dscr4;
+	u32 dscr5;
+	u32 dscr6;
+	u32 dscr7;
+	u32 dscr8;
+	u32 dscr9;
+	u32 dscr10;
+	u32 dscr11;
+	u32 dscr12;
+	u32 dscr13;
+	u32 pscr;
+	u32 pmcr;
+	u32 res1;
+	u32 dcvr0;
+	u32 dcvr1;
+	u32 dcvr2;
+	u32 dcvr3;
+};
+
+/* Chip Select Registers */
+struct weim_regs {
+	u32 cs0u;	/* Chip Select 0 Upper Register */
+	u32 cs0l;	/* Chip Select 0 Lower Register */
+	u32 cs0a;	/* Chip Select 0 Addition Register */
+	u32 pad0;
+	u32 cs1u;	/* Chip Select 1 Upper Register */
+	u32 cs1l;	/* Chip Select 1 Lower Register */
+	u32 cs1a;	/* Chip Select 1 Addition Register */
+	u32 pad1;
+	u32 cs2u;	/* Chip Select 2 Upper Register */
+	u32 cs2l;	/* Chip Select 2 Lower Register */
+	u32 cs2a;	/* Chip Select 2 Addition Register */
+	u32 pad2;
+	u32 cs3u;	/* Chip Select 3 Upper Register */
+	u32 cs3l;	/* Chip Select 3 Lower Register */
+	u32 cs3a;	/* Chip Select 3 Addition Register */
+	u32 pad3;
+	u32 cs4u;	/* Chip Select 4 Upper Register */
+	u32 cs4l;	/* Chip Select 4 Lower Register */
+	u32 cs4a;	/* Chip Select 4 Addition Register */
+	u32 pad4;
+	u32 cs5u;	/* Chip Select 5 Upper Register */
+	u32 cs5l;	/* Chip Select 5 Lower Register */
+	u32 cs5a;	/* Chip Select 5 Addition Register */
+	u32 pad5;
+	u32 eim;	/* WEIM Configuration Register */
+};
+
+/* SDRAM Controller registers */
+struct esdramc_regs {
+/* Enhanced SDRAM Control Register 0 */
+	u32 esdctl0;
+/* Enhanced SDRAM Configuration Register 0 */
+	u32 esdcfg0;
+/* Enhanced SDRAM Control Register 1 */
+	u32 esdctl1;
+/* Enhanced SDRAM Configuration Register 1 */
+	u32 esdcfg1;
+/* Enhanced SDRAM Miscellanious Register */
+	u32 esdmisc;
+};
+
+/* Watchdog Registers*/
+struct wdog_regs {
+	u32 wcr;
+	u32 wsr;
+	u32 wstr;
+};
+
+/* PLL registers */
+struct pll_regs {
+	u32 cscr;	/* Clock Source Control Register */
+	u32 mpctl0;	/* MCU PLL Control Register 0 */
+	u32 mpctl1;	/* MCU PLL Control Register 1 */
+	u32 spctl0;	/* System PLL Control Register 0 */
+	u32 spctl1;	/* System PLL Control Register 1 */
+	u32 osc26mctl;	/* Oscillator 26M Register */
+	u32 pcdr0;	/* Peripheral Clock Divider Register 0 */
+	u32 pcdr1;	/* Peripheral Clock Divider Register 1 */
+	u32 pccr0;	/* Peripheral Clock Control Register 0 */
+	u32 pccr1;	/* Peripheral Clock Control Register 1 */
+	u32 ccsr;	/* Clock Control Status Register */
+};
+
+/*
+ * Definitions for the clocksource registers
+ */
+struct gpt_regs {
+	u32 gpt_tctl;
+	u32 gpt_tprer;
+	u32 gpt_tcmp;
+	u32 gpt_tcr;
+	u32 gpt_tcn;
+	u32 gpt_tstat;
+};
+
+/*
+ *  GPIO Module and I/O Multiplexer
+ */
+#define PORTA 0
+#define PORTB 1
+#define PORTC 2
+#define PORTD 3
+#define PORTE 4
+#define PORTF 5
+
+/* IIM Control Registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prg_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+	u32 res[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[2];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_3[5];
+	u32 mac_addr[6];
+	u32 fuse10_31[0x16];
+};
+
+#endif
+
+#define ARCH_MXC
+
+#define IMX_IO_BASE		0x10000000
+
+#define IMX_AIPI1_BASE		(0x00000 + IMX_IO_BASE)
+#define IMX_WDT_BASE		(0x02000 + IMX_IO_BASE)
+#define IMX_TIM1_BASE		(0x03000 + IMX_IO_BASE)
+#define IMX_TIM2_BASE		(0x04000 + IMX_IO_BASE)
+#define IMX_TIM3_BASE		(0x05000 + IMX_IO_BASE)
+#define IMX_RTC_BASE		(0x07000 + IMX_IO_BASE)
+#define UART1_BASE		(0x0a000 + IMX_IO_BASE)
+#define UART2_BASE		(0x0b000 + IMX_IO_BASE)
+#define UART3_BASE		(0x0c000 + IMX_IO_BASE)
+#define UART4_BASE		(0x0d000 + IMX_IO_BASE)
+#define IMX_I2C1_BASE		(0x12000 + IMX_IO_BASE)
+#define IMX_GPIO_BASE		(0x15000 + IMX_IO_BASE)
+#define IMX_TIM4_BASE		(0x19000 + IMX_IO_BASE)
+#define IMX_TIM5_BASE		(0x1a000 + IMX_IO_BASE)
+#define IMX_UART5_BASE		(0x1b000 + IMX_IO_BASE)
+#define IMX_UART6_BASE		(0x1c000 + IMX_IO_BASE)
+#define IMX_I2C2_BASE		(0x1D000 + IMX_IO_BASE)
+#define IMX_TIM6_BASE		(0x1f000 + IMX_IO_BASE)
+#define IMX_AIPI2_BASE		(0x20000 + IMX_IO_BASE)
+#define IMX_PLL_BASE		(0x27000 + IMX_IO_BASE)
+#define IMX_SYSTEM_CTL_BASE	(0x27800 + IMX_IO_BASE)
+#define IMX_IIM_BASE		(0x28000 + IMX_IO_BASE)
+#define IIM_BASE_ADDR		IMX_IIM_BASE
+#define IMX_FEC_BASE		(0x2b000 + IMX_IO_BASE)
+
+#define IMX_NFC_BASE		(0xD8000000)
+#define IMX_ESD_BASE		(0xD8001000)
+#define IMX_WEIM_BASE		(0xD8002000)
+
+#define NFC_BASE_ADDR		IMX_NFC_BASE
+
+
+/* FMCR System Control bit definition*/
+#define UART4_RXD_CTL	(1 << 25)
+#define UART4_RTS_CTL	(1 << 24)
+#define KP_COL6_CTL	(1 << 18)
+#define KP_ROW7_CTL	(1 << 17)
+#define KP_ROW6_CTL	(1 << 16)
+#define PC_WAIT_B_CTL	(1 << 14)
+#define PC_READY_CTL	(1 << 13)
+#define PC_VS1_CTL	(1 << 12)
+#define PC_VS2_CTL	(1 << 11)
+#define PC_BVD1_CTL	(1 << 10)
+#define PC_BVD2_CTL	(1 << 9)
+#define IOS16_CTL	(1 << 8)
+#define NF_FMS		(1 << 5)
+#define NF_16BIT_SEL	(1 << 4)
+#define SLCDC_SEL	(1 << 2)
+#define SDCS1_SEL	(1 << 1)
+#define SDCS0_SEL	(1 << 0)
+
+
+/* important definition of some bits of WCR */
+#define WCR_WDE 0x04
+
+#define CSCR_MPEN		(1 << 0)
+#define CSCR_SPEN		(1 << 1)
+#define CSCR_FPM_EN		(1 << 2)
+#define CSCR_OSC26M_DIS		(1 << 3)
+#define CSCR_OSC26M_DIV1P5	(1 << 4)
+#define CSCR_AHB_DIV
+#define CSCR_ARM_DIV
+#define CSCR_ARM_SRC_MPLL	(1 << 15)
+#define CSCR_MCU_SEL		(1 << 16)
+#define CSCR_SP_SEL		(1 << 17)
+#define CSCR_MPLL_RESTART	(1 << 18)
+#define CSCR_SPLL_RESTART	(1 << 19)
+#define CSCR_MSHC_SEL		(1 << 20)
+#define CSCR_H264_SEL		(1 << 21)
+#define CSCR_SSI1_SEL		(1 << 22)
+#define CSCR_SSI2_SEL		(1 << 23)
+#define CSCR_SD_CNT
+#define CSCR_USB_DIV
+#define CSCR_UPDATE_DIS		(1 << 31)
+
+#define MPCTL1_BRMO		(1 << 6)
+#define MPCTL1_LF		(1 << 15)
+
+#define PCCR0_SSI2_EN	(1 << 0)
+#define PCCR0_SSI1_EN	(1 << 1)
+#define PCCR0_SLCDC_EN	(1 << 2)
+#define PCCR0_SDHC3_EN	(1 << 3)
+#define PCCR0_SDHC2_EN	(1 << 4)
+#define PCCR0_SDHC1_EN	(1 << 5)
+#define PCCR0_SDC_EN	(1 << 6)
+#define PCCR0_SAHARA_EN	(1 << 7)
+#define PCCR0_RTIC_EN	(1 << 8)
+#define PCCR0_RTC_EN	(1 << 9)
+#define PCCR0_PWM_EN	(1 << 11)
+#define PCCR0_OWIRE_EN	(1 << 12)
+#define PCCR0_MSHC_EN	(1 << 13)
+#define PCCR0_LCDC_EN	(1 << 14)
+#define PCCR0_KPP_EN	(1 << 15)
+#define PCCR0_IIM_EN	(1 << 16)
+#define PCCR0_I2C2_EN	(1 << 17)
+#define PCCR0_I2C1_EN	(1 << 18)
+#define PCCR0_GPT6_EN	(1 << 19)
+#define PCCR0_GPT5_EN	(1 << 20)
+#define PCCR0_GPT4_EN	(1 << 21)
+#define PCCR0_GPT3_EN	(1 << 22)
+#define PCCR0_GPT2_EN	(1 << 23)
+#define PCCR0_GPT1_EN	(1 << 24)
+#define PCCR0_GPIO_EN	(1 << 25)
+#define PCCR0_FEC_EN	(1 << 26)
+#define PCCR0_EMMA_EN	(1 << 27)
+#define PCCR0_DMA_EN	(1 << 28)
+#define PCCR0_CSPI3_EN	(1 << 29)
+#define PCCR0_CSPI2_EN	(1 << 30)
+#define PCCR0_CSPI1_EN	(1 << 31)
+
+#define PCCR1_MSHC_BAUDEN	(1 << 2)
+#define PCCR1_NFC_BAUDEN	(1 << 3)
+#define PCCR1_SSI2_BAUDEN	(1 << 4)
+#define PCCR1_SSI1_BAUDEN	(1 << 5)
+#define PCCR1_H264_BAUDEN	(1 << 6)
+#define PCCR1_PERCLK4_EN	(1 << 7)
+#define PCCR1_PERCLK3_EN	(1 << 8)
+#define PCCR1_PERCLK2_EN	(1 << 9)
+#define PCCR1_PERCLK1_EN	(1 << 10)
+#define PCCR1_HCLK_USB		(1 << 11)
+#define PCCR1_HCLK_SLCDC	(1 << 12)
+#define PCCR1_HCLK_SAHARA	(1 << 13)
+#define PCCR1_HCLK_RTIC		(1 << 14)
+#define PCCR1_HCLK_LCDC		(1 << 15)
+#define PCCR1_HCLK_H264		(1 << 16)
+#define PCCR1_HCLK_FEC		(1 << 17)
+#define PCCR1_HCLK_EMMA		(1 << 18)
+#define PCCR1_HCLK_EMI		(1 << 19)
+#define PCCR1_HCLK_DMA		(1 << 20)
+#define PCCR1_HCLK_CSI		(1 << 21)
+#define PCCR1_HCLK_BROM		(1 << 22)
+#define PCCR1_HCLK_ATA		(1 << 23)
+#define PCCR1_WDT_EN		(1 << 24)
+#define PCCR1_USB_EN		(1 << 25)
+#define PCCR1_UART6_EN		(1 << 26)
+#define PCCR1_UART5_EN		(1 << 27)
+#define PCCR1_UART4_EN		(1 << 28)
+#define PCCR1_UART3_EN		(1 << 29)
+#define PCCR1_UART2_EN		(1 << 30)
+#define PCCR1_UART1_EN		(1 << 31)
+
+/* SDRAM Controller registers bitfields */
+#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
+#define ESDCTL_BL		(1 << 7)
+#define ESDCTL_FP		(1 << 8)
+#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
+#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
+#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
+#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
+#define ESDCTL_DSIZ_32		(2 << 16)
+#define ESDCTL_COL8		(0 << 20)
+#define ESDCTL_COL9		(1 << 20)
+#define ESDCTL_COL10		(2 << 20)
+#define ESDCTL_ROW11		(0 << 24)
+#define ESDCTL_ROW12		(1 << 24)
+#define ESDCTL_ROW13		(2 << 24)
+#define ESDCTL_ROW14		(3 << 24)
+#define ESDCTL_ROW15		(4 << 24)
+#define ESDCTL_SP		(1 << 27)
+#define ESDCTL_SMODE_NORMAL	(0 << 28)
+#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
+#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
+#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
+#define ESDCTL_SMODE_MAN_REF	(4 << 28)
+#define ESDCTL_SDE		(1 << 31)
+
+#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
+#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
+#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
+#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
+#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
+#define ESDCFG_TWR		(1 << 15)
+#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
+#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
+#define ESDCFG_TWTR		(1 << 20)
+#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
+
+#define ESDMISC_RST		(1 << 1)
+#define ESDMISC_MDDREN		(1 << 2)
+#define ESDMISC_MDDR_DL_RST	(1 << 3)
+#define ESDMISC_MDDR_MDIS	(1 << 4)
+#define ESDMISC_LHD		(1 << 5)
+#define ESDMISC_MA10_SHARE	(1 << 6)
+#define ESDMISC_SDRAM_RDY	(1 << 31)
+
+#define PC5_PF_I2C2_DATA	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
+#define PC6_PF_I2C2_CLK		(GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
+#define PC7_PF_USBOTG_DATA5	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
+#define PC8_PF_USBOTG_DATA6	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
+#define PC9_PF_USBOTG_DATA0	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
+#define PC10_PF_USBOTG_DATA2	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
+#define PC11_PF_USBOTG_DATA1	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
+#define PC12_PF_USBOTG_DATA4	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
+#define PC13_PF_USBOTG_DATA3	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
+
+#define PD0_AIN_FEC_TXD0	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
+#define PD1_AIN_FEC_TXD1	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
+#define PD2_AIN_FEC_TXD2	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
+#define PD3_AIN_FEC_TXD3	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
+#define PD4_AOUT_FEC_RX_ER	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
+#define PD5_AOUT_FEC_RXD1	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
+#define PD6_AOUT_FEC_RXD2	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
+#define PD7_AOUT_FEC_RXD3	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
+#define PD8_AF_FEC_MDIO		(GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
+#define PD9_AIN_FEC_MDC		(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
+#define PD10_AOUT_FEC_CRS	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
+#define PD11_AOUT_FEC_TX_CLK	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
+#define PD12_AOUT_FEC_RXD0	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
+#define PD13_AOUT_FEC_RX_DV	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
+#define PD14_AOUT_FEC_CLR	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
+#define PD15_AOUT_FEC_COL	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
+#define PD16_AIN_FEC_TX_ER	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
+#define PF23_AIN_FEC_TX_EN	(GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
+
+#define PE0_PF_USBOTG_NXT	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
+#define PE1_PF_USBOTG_STP	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
+#define PE2_PF_USBOTG_DIR	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
+#define PE3_PF_UART2_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
+#define PE4_PF_UART2_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
+#define PE6_PF_UART2_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
+#define PE7_PF_UART2_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
+#define PE8_PF_UART3_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
+#define PE9_PF_UART3_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
+#define PE10_PF_UART3_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
+#define PE11_PF_UART3_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
+#define PE12_PF_UART1_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
+#define PE13_PF_UART1_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
+#define PE14_PF_UART1_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
+#define PE15_PF_UART1_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
+#define PE18_PF_SD1_D0		(GPIO_PORTE | GPIO_PF | 18)
+#define PE19_PF_SD1_D1		(GPIO_PORTE | GPIO_PF | 19)
+#define PE20_PF_SD1_D2		(GPIO_PORTE | GPIO_PF | 20)
+#define PE21_PF_SD1_D3		(GPIO_PORTE | GPIO_PF | 21)
+#define PE22_PF_SD1_CMD		(GPIO_PORTE | GPIO_PF | 22)
+#define PE23_PF_SD1_CLK		(GPIO_PORTE | GPIO_PF | 23)
+#define PB4_PF_SD2_D0		(GPIO_PORTB | GPIO_PF | 4)
+#define PB5_PF_SD2_D1		(GPIO_PORTB | GPIO_PF | 5)
+#define PB6_PF_SD2_D2		(GPIO_PORTB | GPIO_PF | 6)
+#define PB7_PF_SD2_D3		(GPIO_PORTB | GPIO_PF | 7)
+#define PB8_PF_SD2_CMD		(GPIO_PORTB | GPIO_PF | 8)
+#define PB9_PF_SD2_CLK		(GPIO_PORTB | GPIO_PF | 9)
+#define PD17_PF_I2C_DATA	(GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_I2C_CLK		(GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PE24_PF_USBOTG_CLK	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
+#define PE25_PF_USBOTG_DATA7	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
+
+/* Clocksource Bitfields */
+#define TCTL_SWR	(1 << 15)	/* Software reset */
+#define TCTL_FRR	(1 << 8)	/* Freerun / restart */
+#define TCTL_CAP	(3 << 6)	/* Capture Edge */
+#define TCTL_OM		(1 << 5)	/* output mode */
+#define TCTL_IRQEN	(1 << 4)	/* interrupt enable */
+#define TCTL_CLKSOURCE	1		/* Clock source bit position */
+#define TCTL_TEN	1		/* Timer enable */
+#define TPRER_PRES	0xff		/* Prescale */
+#define TSTAT_CAPT	(1 << 1)	/* Capture event */
+#define TSTAT_COMP	1		/* Compare event */
+
+#define GPIO1_BASE_ADDR 0x10015000
+#define GPIO2_BASE_ADDR 0x10015100
+#define GPIO3_BASE_ADDR 0x10015200
+#define GPIO4_BASE_ADDR 0x10015300
+#define GPIO5_BASE_ADDR 0x10015400
+#define GPIO6_BASE_ADDR 0x10015500
+
+#define GPIO_PIN_MASK	0x1f
+
+#define GPIO_PORT_SHIFT	5
+#define GPIO_PORT_MASK	(0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA	(PORTA << GPIO_PORT_SHIFT)
+#define GPIO_PORTB	(PORTB << GPIO_PORT_SHIFT)
+#define GPIO_PORTC	(PORTC << GPIO_PORT_SHIFT)
+#define GPIO_PORTD	(PORTD << GPIO_PORT_SHIFT)
+#define GPIO_PORTE	(PORTE << GPIO_PORT_SHIFT)
+#define GPIO_PORTF	(PORTF << GPIO_PORT_SHIFT)
+
+#define GPIO_OUT	(1 << 8)
+#define GPIO_IN		(0 << 8)
+#define GPIO_PUEN	(1 << 9)
+
+#define GPIO_PF		(1 << 10)
+#define GPIO_AF		(1 << 11)
+
+#define GPIO_OCR_SHIFT	12
+#define GPIO_OCR_MASK	(3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN	(0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN	(1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN	(2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO	(3 << GPIO_OCR_SHIFT)
+
+#define GPIO_AOUT_SHIFT	14
+#define GPIO_AOUT_MASK	(3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT	(0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR	(1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0	(2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1	(3 << GPIO_AOUT_SHIFT)
+
+#define GPIO_BOUT_SHIFT	16
+#define GPIO_BOUT_MASK	(3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT	(0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR	(1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0	(2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1	(3 << GPIO_BOUT_SHIFT)
+
+#define IIM_STAT_BUSY	(1 << 7)
+#define IIM_STAT_PRGD	(1 << 1)
+#define IIM_STAT_SNSD	(1 << 0)
+#define IIM_ERR_PRGE	(1 << 7)
+#define IIM_ERR_WPE	(1 << 6)
+#define IIM_ERR_OPE	(1 << 5)
+#define IIM_ERR_RPE	(1 << 4)
+#define IIM_ERR_WLRE	(1 << 3)
+#define IIM_ERR_SNSE	(1 << 2)
+#define IIM_ERR_PARITYE	(1 << 1)
+
+#endif				/* _IMX_REGS_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/mxcmmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/mxcmmc.h
new file mode 100644
index 000000000..116328c8f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/mxcmmc.h
@@ -0,0 +1,12 @@
+/*
+ *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ASM_ARCH_MXCMMC_H
+#define ASM_ARCH_MXCMMC_H
+
+int mxc_mmc_init(bd_t *bis);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/regs-rtc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/regs-rtc.h
new file mode 100644
index 000000000..6b382546e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx27/regs-rtc.h
@@ -0,0 +1,27 @@
+/*
+ * Freescale i.MX27 RTC Register Definitions
+ *
+ * Copyright (C) 2012 Philippe Reynes <tremyfr@yahoo.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX27_REGS_RTC_H__
+#define __MX27_REGS_RTC_H__
+
+#ifndef	__ASSEMBLY__
+struct rtc_regs {
+	u32 hourmin;
+	u32 seconds;
+	u32 alrm_hm;
+	u32 alrm_sec;
+	u32 rtcctl;
+	u32 rtcisr;
+	u32 rtcienr;
+	u32 stpwch;
+	u32 dayr;
+	u32 dayalarm;
+};
+#endif /* __ASSEMBLY__*/
+
+#endif	/* __MX28_REGS_RTC_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/clock.h
new file mode 100644
index 000000000..b955deb29
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/clock.h
@@ -0,0 +1,46 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+#ifdef CONFIG_MX31_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX31_HCLK_FREQ
+#else
+#define MXC_HCLK	26000000
+#endif
+
+#ifdef CONFIG_MX31_CLK32
+#define MXC_CLK32	CONFIG_MX31_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
+enum mxc_clock {
+	MXC_ARM_CLK,
+	MXC_IPG_CLK,
+	MXC_IPG_PERCLK,
+	MXC_CSPI_CLK,
+	MXC_UART_CLK,
+	MXC_IPU_CLK,
+	MXC_ESDHC_CLK,
+	MXC_I2C_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+extern u32 imx_get_uartclk(void);
+extern void mx31_gpio_mux(unsigned long mode);
+extern void mx31_set_pad(enum iomux_pins pin, u32 config);
+extern void mx31_set_gpr(enum iomux_gp_func gp, char en);
+
+void mx31_uart1_hw_init(void);
+void mx31_uart2_hw_init(void);
+void mx31_spi2_hw_init(void);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/gpio.h
new file mode 100644
index 000000000..14e9b85c8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/gpio.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __ASM_ARCH_MX31_GPIO_H
+#define __ASM_ARCH_MX31_GPIO_H
+
+#include <asm/imx-common/gpio.h>
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/imx-regs.h
new file mode 100644
index 000000000..f23350e5c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -0,0 +1,917 @@
+/*
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX31_IMX_REGS_H
+#define __ASM_ARCH_MX31_IMX_REGS_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* Clock control module registers */
+struct clock_control_regs {
+	u32 ccmr;
+	u32 pdr0;
+	u32 pdr1;
+	u32 rcsr;
+	u32 mpctl;
+	u32 upctl;
+	u32 spctl;
+	u32 cosr;
+	u32 cgr0;
+	u32 cgr1;
+	u32 cgr2;
+	u32 wimr0;
+	u32 ldc;
+	u32 dcvr0;
+	u32 dcvr1;
+	u32 dcvr2;
+	u32 dcvr3;
+	u32 ltr0;
+	u32 ltr1;
+	u32 ltr2;
+	u32 ltr3;
+	u32 ltbr0;
+	u32 ltbr1;
+	u32 pmcr0;
+	u32 pmcr1;
+	u32 pdr2;
+};
+
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+	u32 test;
+};
+
+/* IIM control registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prg_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+	u32 res[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[3];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_5[6];
+	u32 usr;
+	u32 fuse7_15[9];
+};
+
+struct fuse_bank2_regs {
+	u32 fuse0;
+	u32 uid[8];
+	u32 fuse9_15[7];
+};
+
+struct iomuxc_regs {
+	u32 unused1;
+	u32 unused2;
+	u32 gpr;
+};
+
+struct mx3_cpu_type {
+	u8 srev;
+	u32 v;
+};
+
+#define IOMUX_PADNUM_MASK	0x1ff
+#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
+
+/*
+ * various IOMUX pad functions
+ */
+enum iomux_pad_config {
+	PAD_CTL_NOLOOPBACK	= 0x0 << 9,
+	PAD_CTL_LOOPBACK	= 0x1 << 9,
+	PAD_CTL_PKE_NONE	= 0x0 << 8,
+	PAD_CTL_PKE_ENABLE	= 0x1 << 8,
+	PAD_CTL_PUE_KEEPER	= 0x0 << 7,
+	PAD_CTL_PUE_PUD		= 0x1 << 7,
+	PAD_CTL_100K_PD		= 0x0 << 5,
+	PAD_CTL_100K_PU		= 0x1 << 5,
+	PAD_CTL_47K_PU		= 0x2 << 5,
+	PAD_CTL_22K_PU		= 0x3 << 5,
+	PAD_CTL_HYS_CMOS	= 0x0 << 4,
+	PAD_CTL_HYS_SCHMITZ	= 0x1 << 4,
+	PAD_CTL_ODE_CMOS	= 0x0 << 3,
+	PAD_CTL_ODE_OpenDrain	= 0x1 << 3,
+	PAD_CTL_DRV_NORMAL	= 0x0 << 1,
+	PAD_CTL_DRV_HIGH	= 0x1 << 1,
+	PAD_CTL_DRV_MAX		= 0x2 << 1,
+	PAD_CTL_SRE_SLOW	= 0x0 << 0,
+	PAD_CTL_SRE_FAST	= 0x1 << 0
+};
+
+/*
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+
+enum iomux_pins {
+	MX31_PIN_TTM_PAD	= IOMUX_PIN(0xff,   0),
+	MX31_PIN_CSPI3_SPI_RDY	= IOMUX_PIN(0xff,   1),
+	MX31_PIN_CSPI3_SCLK	= IOMUX_PIN(0xff,   2),
+	MX31_PIN_CSPI3_MISO	= IOMUX_PIN(0xff,   3),
+	MX31_PIN_CSPI3_MOSI	= IOMUX_PIN(0xff,   4),
+	MX31_PIN_CLKSS		= IOMUX_PIN(0xff,   5),
+	MX31_PIN_CE_CONTROL	= IOMUX_PIN(0xff,   6),
+	MX31_PIN_ATA_RESET_B	= IOMUX_PIN(95,     7),
+	MX31_PIN_ATA_DMACK	= IOMUX_PIN(94,     8),
+	MX31_PIN_ATA_DIOW	= IOMUX_PIN(93,     9),
+	MX31_PIN_ATA_DIOR	= IOMUX_PIN(92,    10),
+	MX31_PIN_ATA_CS1	= IOMUX_PIN(91,    11),
+	MX31_PIN_ATA_CS0	= IOMUX_PIN(90,    12),
+	MX31_PIN_SD1_DATA3	= IOMUX_PIN(63,    13),
+	MX31_PIN_SD1_DATA2	= IOMUX_PIN(62,    14),
+	MX31_PIN_SD1_DATA1	= IOMUX_PIN(61,    15),
+	MX31_PIN_SD1_DATA0	= IOMUX_PIN(60,    16),
+	MX31_PIN_SD1_CLK	= IOMUX_PIN(59,    17),
+	MX31_PIN_SD1_CMD	= IOMUX_PIN(58,    18),
+	MX31_PIN_D3_SPL		= IOMUX_PIN(0xff,  19),
+	MX31_PIN_D3_CLS		= IOMUX_PIN(0xff,  20),
+	MX31_PIN_D3_REV		= IOMUX_PIN(0xff,  21),
+	MX31_PIN_CONTRAST	= IOMUX_PIN(0xff,  22),
+	MX31_PIN_VSYNC3		= IOMUX_PIN(0xff,  23),
+	MX31_PIN_READ		= IOMUX_PIN(0xff,  24),
+	MX31_PIN_WRITE		= IOMUX_PIN(0xff,  25),
+	MX31_PIN_PAR_RS		= IOMUX_PIN(0xff,  26),
+	MX31_PIN_SER_RS		= IOMUX_PIN(89,    27),
+	MX31_PIN_LCS1		= IOMUX_PIN(88,    28),
+	MX31_PIN_LCS0		= IOMUX_PIN(87,    29),
+	MX31_PIN_SD_D_CLK	= IOMUX_PIN(86,    30),
+	MX31_PIN_SD_D_IO	= IOMUX_PIN(85,    31),
+	MX31_PIN_SD_D_I		= IOMUX_PIN(84,    32),
+	MX31_PIN_DRDY0		= IOMUX_PIN(0xff,  33),
+	MX31_PIN_FPSHIFT	= IOMUX_PIN(0xff,  34),
+	MX31_PIN_HSYNC		= IOMUX_PIN(0xff,  35),
+	MX31_PIN_VSYNC0		= IOMUX_PIN(0xff,  36),
+	MX31_PIN_LD17		= IOMUX_PIN(0xff,  37),
+	MX31_PIN_LD16		= IOMUX_PIN(0xff,  38),
+	MX31_PIN_LD15		= IOMUX_PIN(0xff,  39),
+	MX31_PIN_LD14		= IOMUX_PIN(0xff,  40),
+	MX31_PIN_LD13		= IOMUX_PIN(0xff,  41),
+	MX31_PIN_LD12		= IOMUX_PIN(0xff,  42),
+	MX31_PIN_LD11		= IOMUX_PIN(0xff,  43),
+	MX31_PIN_LD10		= IOMUX_PIN(0xff,  44),
+	MX31_PIN_LD9		= IOMUX_PIN(0xff,  45),
+	MX31_PIN_LD8		= IOMUX_PIN(0xff,  46),
+	MX31_PIN_LD7		= IOMUX_PIN(0xff,  47),
+	MX31_PIN_LD6		= IOMUX_PIN(0xff,  48),
+	MX31_PIN_LD5		= IOMUX_PIN(0xff,  49),
+	MX31_PIN_LD4		= IOMUX_PIN(0xff,  50),
+	MX31_PIN_LD3		= IOMUX_PIN(0xff,  51),
+	MX31_PIN_LD2		= IOMUX_PIN(0xff,  52),
+	MX31_PIN_LD1		= IOMUX_PIN(0xff,  53),
+	MX31_PIN_LD0		= IOMUX_PIN(0xff,  54),
+	MX31_PIN_USBH2_DATA1	= IOMUX_PIN(0xff,  55),
+	MX31_PIN_USBH2_DATA0	= IOMUX_PIN(0xff,  56),
+	MX31_PIN_USBH2_NXT	= IOMUX_PIN(0xff,  57),
+	MX31_PIN_USBH2_STP	= IOMUX_PIN(0xff,  58),
+	MX31_PIN_USBH2_DIR	= IOMUX_PIN(0xff,  59),
+	MX31_PIN_USBH2_CLK	= IOMUX_PIN(0xff,  60),
+	MX31_PIN_USBOTG_DATA7	= IOMUX_PIN(0xff,  61),
+	MX31_PIN_USBOTG_DATA6	= IOMUX_PIN(0xff,  62),
+	MX31_PIN_USBOTG_DATA5	= IOMUX_PIN(0xff,  63),
+	MX31_PIN_USBOTG_DATA4	= IOMUX_PIN(0xff,  64),
+	MX31_PIN_USBOTG_DATA3	= IOMUX_PIN(0xff,  65),
+	MX31_PIN_USBOTG_DATA2	= IOMUX_PIN(0xff,  66),
+	MX31_PIN_USBOTG_DATA1	= IOMUX_PIN(0xff,  67),
+	MX31_PIN_USBOTG_DATA0	= IOMUX_PIN(0xff,  68),
+	MX31_PIN_USBOTG_NXT	= IOMUX_PIN(0xff,  69),
+	MX31_PIN_USBOTG_STP	= IOMUX_PIN(0xff,  70),
+	MX31_PIN_USBOTG_DIR	= IOMUX_PIN(0xff,  71),
+	MX31_PIN_USBOTG_CLK	= IOMUX_PIN(0xff,  72),
+	MX31_PIN_USB_BYP	= IOMUX_PIN(31,    73),
+	MX31_PIN_USB_OC		= IOMUX_PIN(30,    74),
+	MX31_PIN_USB_PWR	= IOMUX_PIN(29,    75),
+	MX31_PIN_SJC_MOD	= IOMUX_PIN(0xff,  76),
+	MX31_PIN_DE_B		= IOMUX_PIN(0xff,  77),
+	MX31_PIN_TRSTB		= IOMUX_PIN(0xff,  78),
+	MX31_PIN_TDO		= IOMUX_PIN(0xff,  79),
+	MX31_PIN_TDI		= IOMUX_PIN(0xff,  80),
+	MX31_PIN_TMS		= IOMUX_PIN(0xff,  81),
+	MX31_PIN_TCK		= IOMUX_PIN(0xff,  82),
+	MX31_PIN_RTCK		= IOMUX_PIN(0xff,  83),
+	MX31_PIN_KEY_COL7	= IOMUX_PIN(57,    84),
+	MX31_PIN_KEY_COL6	= IOMUX_PIN(56,    85),
+	MX31_PIN_KEY_COL5	= IOMUX_PIN(55,    86),
+	MX31_PIN_KEY_COL4	= IOMUX_PIN(54,    87),
+	MX31_PIN_KEY_COL3	= IOMUX_PIN(0xff,  88),
+	MX31_PIN_KEY_COL2	= IOMUX_PIN(0xff,  89),
+	MX31_PIN_KEY_COL1	= IOMUX_PIN(0xff,  90),
+	MX31_PIN_KEY_COL0	= IOMUX_PIN(0xff,  91),
+	MX31_PIN_KEY_ROW7	= IOMUX_PIN(53,    92),
+	MX31_PIN_KEY_ROW6	= IOMUX_PIN(52,    93),
+	MX31_PIN_KEY_ROW5	= IOMUX_PIN(51,    94),
+	MX31_PIN_KEY_ROW4	= IOMUX_PIN(50,    95),
+	MX31_PIN_KEY_ROW3	= IOMUX_PIN(0xff,  96),
+	MX31_PIN_KEY_ROW2	= IOMUX_PIN(0xff,  97),
+	MX31_PIN_KEY_ROW1	= IOMUX_PIN(0xff,  98),
+	MX31_PIN_KEY_ROW0	= IOMUX_PIN(0xff,  99),
+	MX31_PIN_BATT_LINE	= IOMUX_PIN(49,   100),
+	MX31_PIN_CTS2		= IOMUX_PIN(0xff, 101),
+	MX31_PIN_RTS2		= IOMUX_PIN(0xff, 102),
+	MX31_PIN_TXD2		= IOMUX_PIN(28,   103),
+	MX31_PIN_RXD2		= IOMUX_PIN(27,   104),
+	MX31_PIN_DTR_DCE2	= IOMUX_PIN(48,   105),
+	MX31_PIN_DCD_DTE1	= IOMUX_PIN(47,   106),
+	MX31_PIN_RI_DTE1	= IOMUX_PIN(46,   107),
+	MX31_PIN_DSR_DTE1	= IOMUX_PIN(45,   108),
+	MX31_PIN_DTR_DTE1	= IOMUX_PIN(44,   109),
+	MX31_PIN_DCD_DCE1	= IOMUX_PIN(43,   110),
+	MX31_PIN_RI_DCE1	= IOMUX_PIN(42,   111),
+	MX31_PIN_DSR_DCE1	= IOMUX_PIN(41,   112),
+	MX31_PIN_DTR_DCE1	= IOMUX_PIN(40,   113),
+	MX31_PIN_CTS1		= IOMUX_PIN(39,   114),
+	MX31_PIN_RTS1		= IOMUX_PIN(38,   115),
+	MX31_PIN_TXD1		= IOMUX_PIN(37,   116),
+	MX31_PIN_RXD1		= IOMUX_PIN(36,   117),
+	MX31_PIN_CSPI2_SPI_RDY	= IOMUX_PIN(0xff, 118),
+	MX31_PIN_CSPI2_SCLK	= IOMUX_PIN(0xff, 119),
+	MX31_PIN_CSPI2_SS2	= IOMUX_PIN(0xff, 120),
+	MX31_PIN_CSPI2_SS1	= IOMUX_PIN(0xff, 121),
+	MX31_PIN_CSPI2_SS0	= IOMUX_PIN(0xff, 122),
+	MX31_PIN_CSPI2_MISO	= IOMUX_PIN(0xff, 123),
+	MX31_PIN_CSPI2_MOSI	= IOMUX_PIN(0xff, 124),
+	MX31_PIN_CSPI1_SPI_RDY	= IOMUX_PIN(0xff, 125),
+	MX31_PIN_CSPI1_SCLK	= IOMUX_PIN(0xff, 126),
+	MX31_PIN_CSPI1_SS2	= IOMUX_PIN(0xff, 127),
+	MX31_PIN_CSPI1_SS1	= IOMUX_PIN(0xff, 128),
+	MX31_PIN_CSPI1_SS0	= IOMUX_PIN(0xff, 129),
+	MX31_PIN_CSPI1_MISO	= IOMUX_PIN(0xff, 130),
+	MX31_PIN_CSPI1_MOSI	= IOMUX_PIN(0xff, 131),
+	MX31_PIN_SFS6		= IOMUX_PIN(26,   132),
+	MX31_PIN_SCK6		= IOMUX_PIN(25,   133),
+	MX31_PIN_SRXD6		= IOMUX_PIN(24,   134),
+	MX31_PIN_STXD6		= IOMUX_PIN(23,   135),
+	MX31_PIN_SFS5		= IOMUX_PIN(0xff, 136),
+	MX31_PIN_SCK5		= IOMUX_PIN(0xff, 137),
+	MX31_PIN_SRXD5		= IOMUX_PIN(22,   138),
+	MX31_PIN_STXD5		= IOMUX_PIN(21,   139),
+	MX31_PIN_SFS4		= IOMUX_PIN(0xff, 140),
+	MX31_PIN_SCK4		= IOMUX_PIN(0xff, 141),
+	MX31_PIN_SRXD4		= IOMUX_PIN(20,   142),
+	MX31_PIN_STXD4		= IOMUX_PIN(19,   143),
+	MX31_PIN_SFS3		= IOMUX_PIN(0xff, 144),
+	MX31_PIN_SCK3		= IOMUX_PIN(0xff, 145),
+	MX31_PIN_SRXD3		= IOMUX_PIN(18,   146),
+	MX31_PIN_STXD3		= IOMUX_PIN(17,   147),
+	MX31_PIN_I2C_DAT	= IOMUX_PIN(0xff, 148),
+	MX31_PIN_I2C_CLK	= IOMUX_PIN(0xff, 149),
+	MX31_PIN_CSI_PIXCLK	= IOMUX_PIN(83,   150),
+	MX31_PIN_CSI_HSYNC	= IOMUX_PIN(82,   151),
+	MX31_PIN_CSI_VSYNC	= IOMUX_PIN(81,   152),
+	MX31_PIN_CSI_MCLK	= IOMUX_PIN(80,   153),
+	MX31_PIN_CSI_D15	= IOMUX_PIN(79,   154),
+	MX31_PIN_CSI_D14	= IOMUX_PIN(78,   155),
+	MX31_PIN_CSI_D13	= IOMUX_PIN(77,   156),
+	MX31_PIN_CSI_D12	= IOMUX_PIN(76,   157),
+	MX31_PIN_CSI_D11	= IOMUX_PIN(75,   158),
+	MX31_PIN_CSI_D10	= IOMUX_PIN(74,   159),
+	MX31_PIN_CSI_D9		= IOMUX_PIN(73,   160),
+	MX31_PIN_CSI_D8		= IOMUX_PIN(72,   161),
+	MX31_PIN_CSI_D7		= IOMUX_PIN(71,   162),
+	MX31_PIN_CSI_D6		= IOMUX_PIN(70,   163),
+	MX31_PIN_CSI_D5		= IOMUX_PIN(69,   164),
+	MX31_PIN_CSI_D4		= IOMUX_PIN(68,   165),
+	MX31_PIN_M_GRANT	= IOMUX_PIN(0xff, 166),
+	MX31_PIN_M_REQUEST	= IOMUX_PIN(0xff, 167),
+	MX31_PIN_PC_POE		= IOMUX_PIN(0xff, 168),
+	MX31_PIN_PC_RW_B	= IOMUX_PIN(0xff, 169),
+	MX31_PIN_IOIS16		= IOMUX_PIN(0xff, 170),
+	MX31_PIN_PC_RST		= IOMUX_PIN(0xff, 171),
+	MX31_PIN_PC_BVD2	= IOMUX_PIN(0xff, 172),
+	MX31_PIN_PC_BVD1	= IOMUX_PIN(0xff, 173),
+	MX31_PIN_PC_VS2		= IOMUX_PIN(0xff, 174),
+	MX31_PIN_PC_VS1		= IOMUX_PIN(0xff, 175),
+	MX31_PIN_PC_PWRON	= IOMUX_PIN(0xff, 176),
+	MX31_PIN_PC_READY	= IOMUX_PIN(0xff, 177),
+	MX31_PIN_PC_WAIT_B	= IOMUX_PIN(0xff, 178),
+	MX31_PIN_PC_CD2_B	= IOMUX_PIN(0xff, 179),
+	MX31_PIN_PC_CD1_B	= IOMUX_PIN(0xff, 180),
+	MX31_PIN_D0		= IOMUX_PIN(0xff, 181),
+	MX31_PIN_D1		= IOMUX_PIN(0xff, 182),
+	MX31_PIN_D2		= IOMUX_PIN(0xff, 183),
+	MX31_PIN_D3		= IOMUX_PIN(0xff, 184),
+	MX31_PIN_D4		= IOMUX_PIN(0xff, 185),
+	MX31_PIN_D5		= IOMUX_PIN(0xff, 186),
+	MX31_PIN_D6		= IOMUX_PIN(0xff, 187),
+	MX31_PIN_D7		= IOMUX_PIN(0xff, 188),
+	MX31_PIN_D8		= IOMUX_PIN(0xff, 189),
+	MX31_PIN_D9		= IOMUX_PIN(0xff, 190),
+	MX31_PIN_D10		= IOMUX_PIN(0xff, 191),
+	MX31_PIN_D11		= IOMUX_PIN(0xff, 192),
+	MX31_PIN_D12		= IOMUX_PIN(0xff, 193),
+	MX31_PIN_D13		= IOMUX_PIN(0xff, 194),
+	MX31_PIN_D14		= IOMUX_PIN(0xff, 195),
+	MX31_PIN_D15		= IOMUX_PIN(0xff, 196),
+	MX31_PIN_NFRB		= IOMUX_PIN(16,   197),
+	MX31_PIN_NFCE_B		= IOMUX_PIN(15,   198),
+	MX31_PIN_NFWP_B		= IOMUX_PIN(14,   199),
+	MX31_PIN_NFCLE		= IOMUX_PIN(13,   200),
+	MX31_PIN_NFALE		= IOMUX_PIN(12,   201),
+	MX31_PIN_NFRE_B		= IOMUX_PIN(11,   202),
+	MX31_PIN_NFWE_B		= IOMUX_PIN(10,   203),
+	MX31_PIN_SDQS3		= IOMUX_PIN(0xff, 204),
+	MX31_PIN_SDQS2		= IOMUX_PIN(0xff, 205),
+	MX31_PIN_SDQS1		= IOMUX_PIN(0xff, 206),
+	MX31_PIN_SDQS0		= IOMUX_PIN(0xff, 207),
+	MX31_PIN_SDCLK_B	= IOMUX_PIN(0xff, 208),
+	MX31_PIN_SDCLK		= IOMUX_PIN(0xff, 209),
+	MX31_PIN_SDCKE1		= IOMUX_PIN(0xff, 210),
+	MX31_PIN_SDCKE0		= IOMUX_PIN(0xff, 211),
+	MX31_PIN_SDWE		= IOMUX_PIN(0xff, 212),
+	MX31_PIN_CAS		= IOMUX_PIN(0xff, 213),
+	MX31_PIN_RAS		= IOMUX_PIN(0xff, 214),
+	MX31_PIN_RW		= IOMUX_PIN(0xff, 215),
+	MX31_PIN_BCLK		= IOMUX_PIN(0xff, 216),
+	MX31_PIN_LBA		= IOMUX_PIN(0xff, 217),
+	MX31_PIN_ECB		= IOMUX_PIN(0xff, 218),
+	MX31_PIN_CS5		= IOMUX_PIN(0xff, 219),
+	MX31_PIN_CS4		= IOMUX_PIN(0xff, 220),
+	MX31_PIN_CS3		= IOMUX_PIN(0xff, 221),
+	MX31_PIN_CS2		= IOMUX_PIN(0xff, 222),
+	MX31_PIN_CS1		= IOMUX_PIN(0xff, 223),
+	MX31_PIN_CS0		= IOMUX_PIN(0xff, 224),
+	MX31_PIN_OE		= IOMUX_PIN(0xff, 225),
+	MX31_PIN_EB1		= IOMUX_PIN(0xff, 226),
+	MX31_PIN_EB0		= IOMUX_PIN(0xff, 227),
+	MX31_PIN_DQM3		= IOMUX_PIN(0xff, 228),
+	MX31_PIN_DQM2		= IOMUX_PIN(0xff, 229),
+	MX31_PIN_DQM1		= IOMUX_PIN(0xff, 230),
+	MX31_PIN_DQM0		= IOMUX_PIN(0xff, 231),
+	MX31_PIN_SD31		= IOMUX_PIN(0xff, 232),
+	MX31_PIN_SD30		= IOMUX_PIN(0xff, 233),
+	MX31_PIN_SD29		= IOMUX_PIN(0xff, 234),
+	MX31_PIN_SD28		= IOMUX_PIN(0xff, 235),
+	MX31_PIN_SD27		= IOMUX_PIN(0xff, 236),
+	MX31_PIN_SD26		= IOMUX_PIN(0xff, 237),
+	MX31_PIN_SD25		= IOMUX_PIN(0xff, 238),
+	MX31_PIN_SD24		= IOMUX_PIN(0xff, 239),
+	MX31_PIN_SD23		= IOMUX_PIN(0xff, 240),
+	MX31_PIN_SD22		= IOMUX_PIN(0xff, 241),
+	MX31_PIN_SD21		= IOMUX_PIN(0xff, 242),
+	MX31_PIN_SD20		= IOMUX_PIN(0xff, 243),
+	MX31_PIN_SD19		= IOMUX_PIN(0xff, 244),
+	MX31_PIN_SD18		= IOMUX_PIN(0xff, 245),
+	MX31_PIN_SD17		= IOMUX_PIN(0xff, 246),
+	MX31_PIN_SD16		= IOMUX_PIN(0xff, 247),
+	MX31_PIN_SD15		= IOMUX_PIN(0xff, 248),
+	MX31_PIN_SD14		= IOMUX_PIN(0xff, 249),
+	MX31_PIN_SD13		= IOMUX_PIN(0xff, 250),
+	MX31_PIN_SD12		= IOMUX_PIN(0xff, 251),
+	MX31_PIN_SD11		= IOMUX_PIN(0xff, 252),
+	MX31_PIN_SD10		= IOMUX_PIN(0xff, 253),
+	MX31_PIN_SD9		= IOMUX_PIN(0xff, 254),
+	MX31_PIN_SD8		= IOMUX_PIN(0xff, 255),
+	MX31_PIN_SD7		= IOMUX_PIN(0xff, 256),
+	MX31_PIN_SD6		= IOMUX_PIN(0xff, 257),
+	MX31_PIN_SD5		= IOMUX_PIN(0xff, 258),
+	MX31_PIN_SD4		= IOMUX_PIN(0xff, 259),
+	MX31_PIN_SD3		= IOMUX_PIN(0xff, 260),
+	MX31_PIN_SD2		= IOMUX_PIN(0xff, 261),
+	MX31_PIN_SD1		= IOMUX_PIN(0xff, 262),
+	MX31_PIN_SD0		= IOMUX_PIN(0xff, 263),
+	MX31_PIN_SDBA0		= IOMUX_PIN(0xff, 264),
+	MX31_PIN_SDBA1		= IOMUX_PIN(0xff, 265),
+	MX31_PIN_A25		= IOMUX_PIN(0xff, 266),
+	MX31_PIN_A24		= IOMUX_PIN(0xff, 267),
+	MX31_PIN_A23		= IOMUX_PIN(0xff, 268),
+	MX31_PIN_A22		= IOMUX_PIN(0xff, 269),
+	MX31_PIN_A21		= IOMUX_PIN(0xff, 270),
+	MX31_PIN_A20		= IOMUX_PIN(0xff, 271),
+	MX31_PIN_A19		= IOMUX_PIN(0xff, 272),
+	MX31_PIN_A18		= IOMUX_PIN(0xff, 273),
+	MX31_PIN_A17		= IOMUX_PIN(0xff, 274),
+	MX31_PIN_A16		= IOMUX_PIN(0xff, 275),
+	MX31_PIN_A14		= IOMUX_PIN(0xff, 276),
+	MX31_PIN_A15		= IOMUX_PIN(0xff, 277),
+	MX31_PIN_A13		= IOMUX_PIN(0xff, 278),
+	MX31_PIN_A12		= IOMUX_PIN(0xff, 279),
+	MX31_PIN_A11		= IOMUX_PIN(0xff, 280),
+	MX31_PIN_MA10		= IOMUX_PIN(0xff, 281),
+	MX31_PIN_A10		= IOMUX_PIN(0xff, 282),
+	MX31_PIN_A9		= IOMUX_PIN(0xff, 283),
+	MX31_PIN_A8		= IOMUX_PIN(0xff, 284),
+	MX31_PIN_A7		= IOMUX_PIN(0xff, 285),
+	MX31_PIN_A6		= IOMUX_PIN(0xff, 286),
+	MX31_PIN_A5		= IOMUX_PIN(0xff, 287),
+	MX31_PIN_A4		= IOMUX_PIN(0xff, 288),
+	MX31_PIN_A3		= IOMUX_PIN(0xff, 289),
+	MX31_PIN_A2		= IOMUX_PIN(0xff, 290),
+	MX31_PIN_A1		= IOMUX_PIN(0xff, 291),
+	MX31_PIN_A0		= IOMUX_PIN(0xff, 292),
+	MX31_PIN_VPG1		= IOMUX_PIN(0xff, 293),
+	MX31_PIN_VPG0		= IOMUX_PIN(0xff, 294),
+	MX31_PIN_DVFS1		= IOMUX_PIN(0xff, 295),
+	MX31_PIN_DVFS0		= IOMUX_PIN(0xff, 296),
+	MX31_PIN_VSTBY		= IOMUX_PIN(0xff, 297),
+	MX31_PIN_POWER_FAIL	= IOMUX_PIN(0xff, 298),
+	MX31_PIN_CKIL		= IOMUX_PIN(0xff, 299),
+	MX31_PIN_BOOT_MODE4	= IOMUX_PIN(0xff, 300),
+	MX31_PIN_BOOT_MODE3	= IOMUX_PIN(0xff, 301),
+	MX31_PIN_BOOT_MODE2	= IOMUX_PIN(0xff, 302),
+	MX31_PIN_BOOT_MODE1	= IOMUX_PIN(0xff, 303),
+	MX31_PIN_BOOT_MODE0	= IOMUX_PIN(0xff, 304),
+	MX31_PIN_CLKO		= IOMUX_PIN(0xff, 305),
+	MX31_PIN_POR_B		= IOMUX_PIN(0xff, 306),
+	MX31_PIN_RESET_IN_B	= IOMUX_PIN(0xff, 307),
+	MX31_PIN_CKIH		= IOMUX_PIN(0xff, 308),
+	MX31_PIN_SIMPD0		= IOMUX_PIN(35,   309),
+	MX31_PIN_SRX0		= IOMUX_PIN(34,   310),
+	MX31_PIN_STX0		= IOMUX_PIN(33,   311),
+	MX31_PIN_SVEN0		= IOMUX_PIN(32,   312),
+	MX31_PIN_SRST0		= IOMUX_PIN(67,   313),
+	MX31_PIN_SCLK0		= IOMUX_PIN(66,   314),
+	MX31_PIN_GPIO3_1	= IOMUX_PIN(65,   315),
+	MX31_PIN_GPIO3_0	= IOMUX_PIN(64,   316),
+	MX31_PIN_GPIO1_6	= IOMUX_PIN(6,    317),
+	MX31_PIN_GPIO1_5	= IOMUX_PIN(5,    318),
+	MX31_PIN_GPIO1_4	= IOMUX_PIN(4,    319),
+	MX31_PIN_GPIO1_3	= IOMUX_PIN(3,    320),
+	MX31_PIN_GPIO1_2	= IOMUX_PIN(2,    321),
+	MX31_PIN_GPIO1_1	= IOMUX_PIN(1,    322),
+	MX31_PIN_GPIO1_0	= IOMUX_PIN(0,    323),
+	MX31_PIN_PWMO		= IOMUX_PIN(9,    324),
+	MX31_PIN_WATCHDOG_RST	= IOMUX_PIN(0xff, 325),
+	MX31_PIN_COMPARE	= IOMUX_PIN(8,    326),
+	MX31_PIN_CAPTURE	= IOMUX_PIN(7,    327),
+};
+
+/*
+ * various IOMUX general purpose functions
+ */
+enum iomux_gp_func {
+	MUX_PGP_FIRI			= 1 << 0,
+	MUX_DDR_MODE			= 1 << 1,
+	MUX_PGP_CSPI_BB			= 1 << 2,
+	MUX_PGP_ATA_1			= 1 << 3,
+	MUX_PGP_ATA_2			= 1 << 4,
+	MUX_PGP_ATA_3			= 1 << 5,
+	MUX_PGP_ATA_4			= 1 << 6,
+	MUX_PGP_ATA_5			= 1 << 7,
+	MUX_PGP_ATA_6			= 1 << 8,
+	MUX_PGP_ATA_7			= 1 << 9,
+	MUX_PGP_ATA_8			= 1 << 10,
+	MUX_PGP_UH2			= 1 << 11,
+	MUX_SDCTL_CSD0_SEL		= 1 << 12,
+	MUX_SDCTL_CSD1_SEL		= 1 << 13,
+	MUX_CSPI1_UART3			= 1 << 14,
+	MUX_EXTDMAREQ2_MBX_SEL		= 1 << 15,
+	MUX_TAMPER_DETECT_EN		= 1 << 16,
+	MUX_PGP_USB_4WIRE		= 1 << 17,
+	MUX_PGP_USB_COMMON		= 1 << 18,
+	MUX_SDHC_MEMSTICK1		= 1 << 19,
+	MUX_SDHC_MEMSTICK2		= 1 << 20,
+	MUX_PGP_SPLL_BYP		= 1 << 21,
+	MUX_PGP_UPLL_BYP		= 1 << 22,
+	MUX_PGP_MSHC1_CLK_SEL		= 1 << 23,
+	MUX_PGP_MSHC2_CLK_SEL		= 1 << 24,
+	MUX_CSPI3_UART5_SEL		= 1 << 25,
+	MUX_PGP_ATA_9			= 1 << 26,
+	MUX_PGP_USB_SUSPEND		= 1 << 27,
+	MUX_PGP_USB_OTG_LOOPBACK	= 1 << 28,
+	MUX_PGP_USB_HS1_LOOPBACK	= 1 << 29,
+	MUX_PGP_USB_HS2_LOOPBACK	= 1 << 30,
+	MUX_CLKO_DDR_MODE		= 1 << 31,
+};
+
+/* Bit definitions for RCSR register in CCM */
+#define CCM_RCSR_NF16B	(1 << 31)
+#define CCM_RCSR_NFMS	(1 << 30)
+
+/* WEIM CS control registers */
+struct mx31_weim_cscr {
+	u32 upper;
+	u32 lower;
+	u32 additional;
+	u32 reserved;
+};
+
+struct mx31_weim {
+	struct mx31_weim_cscr cscr[6];
+};
+
+/* ESD control registers */
+struct esdc_regs {
+	u32 ctl0;
+	u32 cfg0;
+	u32 ctl1;
+	u32 cfg1;
+	u32 misc;
+	u32 dly[5];
+	u32 dlyl;
+};
+
+#endif
+
+#define ARCH_MXC
+
+#define __REG(x)     (*((volatile u32 *)(x)))
+#define __REG16(x)   (*((volatile u16 *)(x)))
+#define __REG8(x)    (*((volatile u8 *)(x)))
+
+#define CCM_BASE	0x53f80000
+#define CCM_CCMR	(CCM_BASE + 0x00)
+#define CCM_PDR0	(CCM_BASE + 0x04)
+#define CCM_PDR1	(CCM_BASE + 0x08)
+#define CCM_RCSR	(CCM_BASE + 0x0c)
+#define CCM_MPCTL	(CCM_BASE + 0x10)
+#define CCM_UPCTL	(CCM_BASE + 0x14)
+#define CCM_SPCTL	(CCM_BASE + 0x18)
+#define CCM_COSR	(CCM_BASE + 0x1C)
+#define CCM_CGR0	(CCM_BASE + 0x20)
+#define CCM_CGR1	(CCM_BASE + 0x24)
+#define CCM_CGR2	(CCM_BASE + 0x28)
+
+#define CCMR_MDS	(1 << 7)
+#define CCMR_SBYCS	(1 << 4)
+#define CCMR_MPE	(1 << 3)
+#define CCMR_PRCS_MASK	(3 << 1)
+#define CCMR_FPM	(1 << 1)
+#define CCMR_CKIH	(2 << 1)
+
+#define MX31_IIM_BASE_ADDR	0x5001C000
+#define IIM_BASE_ADDR		MX31_IIM_BASE_ADDR
+
+#define PDR0_CSI_PODF(x)	(((x) & 0x3f) << 26)
+#define PDR0_CSI_PRDF(x)	(((x) & 0x7) << 23)
+#define PDR0_PER_PODF(x)	(((x) & 0x1f) << 16)
+#define PDR0_HSP_PODF(x)	(((x) & 0x7) << 11)
+#define PDR0_NFC_PODF(x)	(((x) & 0x7) << 8)
+#define PDR0_IPG_PODF(x)	(((x) & 0x3) << 6)
+#define PDR0_MAX_PODF(x)	(((x) & 0x7) << 3)
+#define PDR0_MCU_PODF(x)	((x) & 0x7)
+
+#define PDR1_USB_PRDF(x)	(((x) & 0x3) << 30)
+#define PDR1_USB_PODF(x)	(((x) & 0x7) << 27)
+#define PDR1_FIRI_PRDF(x)	(((x) & 0x7) << 24)
+#define PDR1_FIRI_PODF(x)	(((x) & 0x3f) << 18)
+#define PDR1_SSI2_PRDF(x)	(((x) & 0x7) << 15)
+#define PDR1_SSI2_PODF(x)	(((x) & 0x3f) << 9)
+#define PDR1_SSI1_PRDF(x)	(((x) & 0x7) << 6)
+#define PDR1_SSI1_PODF(x)	((x) & 0x3f)
+
+#define PLL_BRMO(x)		(((x) & 0x1) << 31)
+#define PLL_PD(x)		(((x) & 0xf) << 26)
+#define PLL_MFD(x)		(((x) & 0x3ff) << 16)
+#define PLL_MFI(x)		(((x) & 0xf) << 10)
+#define PLL_MFN(x)		(((x) & 0x3ff) << 0)
+
+#define GET_PDR0_CSI_PODF(x)	(((x) >> 26) & 0x3f)
+#define GET_PDR0_CSI_PRDF(x)	(((x) >> 23) & 0x7)
+#define GET_PDR0_PER_PODF(x)	(((x) >> 16) & 0x1f)
+#define GET_PDR0_HSP_PODF(x)	(((x) >> 11) & 0x7)
+#define GET_PDR0_NFC_PODF(x)	(((x) >> 8) & 0x7)
+#define GET_PDR0_IPG_PODF(x)	(((x) >> 6) & 0x3)
+#define GET_PDR0_MAX_PODF(x)	(((x) >> 3) & 0x7)
+#define GET_PDR0_MCU_PODF(x)	((x) & 0x7)
+
+#define GET_PLL_PD(x)		(((x) >> 26) & 0xf)
+#define GET_PLL_MFD(x)		(((x) >> 16) & 0x3ff)
+#define GET_PLL_MFI(x)		(((x) >> 10) & 0xf)
+#define GET_PLL_MFN(x)		(((x) >> 0) & 0x3ff)
+
+
+#define WEIM_ESDCTL0	0xB8001000
+#define WEIM_ESDCFG0	0xB8001004
+#define WEIM_ESDCTL1	0xB8001008
+#define WEIM_ESDCFG1	0xB800100C
+#define WEIM_ESDMISC	0xB8001010
+
+#define UART1_BASE	0x43F90000
+#define UART2_BASE	0x43F94000
+#define UART3_BASE	0x5000C000
+#define UART4_BASE	0x43FB0000
+#define UART5_BASE	0x43FB4000
+
+#define I2C1_BASE_ADDR          0x43f80000
+#define I2C1_CLK_OFFSET		26
+#define I2C2_BASE_ADDR          0x43F98000
+#define I2C2_CLK_OFFSET		28
+#define I2C3_BASE_ADDR          0x43f84000
+#define I2C3_CLK_OFFSET		30
+
+#define ESDCTL_SDE			(1 << 31)
+#define ESDCTL_CMD_RW			(0 << 28)
+#define ESDCTL_CMD_PRECHARGE		(1 << 28)
+#define ESDCTL_CMD_AUTOREFRESH		(2 << 28)
+#define ESDCTL_CMD_LOADMODEREG		(3 << 28)
+#define ESDCTL_CMD_MANUALREFRESH	(4 << 28)
+#define ESDCTL_ROW_13			(2 << 24)
+#define ESDCTL_ROW(x)			((x) << 24)
+#define ESDCTL_COL_9			(1 << 20)
+#define ESDCTL_COL(x)			((x) << 20)
+#define ESDCTL_DSIZ(x)			((x) << 16)
+#define ESDCTL_SREFR(x)			((x) << 13)
+#define ESDCTL_PWDT(x)			((x) << 10)
+#define ESDCTL_FP(x)			((x) << 8)
+#define ESDCTL_BL(x)			((x) << 7)
+#define ESDCTL_PRCT(x)			((x) << 0)
+
+#define ESDCTL_BASE_ADDR	0xB8001000
+
+/* 13 fields of the upper CS control register */
+#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
+		cnc, wsc, ew, wws, edc) \
+	((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
+	 (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
+	 (wws) << 4 | (edc) << 0)
+/* 12 fields of the lower CS control register */
+#define CSCR_L(oea, oen, ebwa, ebwn, \
+		csa, ebc, dsz, csn, psr, cre, wrap, csen) \
+	((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
+	 (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
+	 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
+/* 14 fields of the additional CS control register */
+#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
+		wwu, age, cnc2, fce) \
+	((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
+	 (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
+	 (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
+	 (age) << 2 | (cnc2) << 1 | (fce) << 0)
+
+#define WEIM_BASE	0xb8002000
+
+#define IOMUXC_BASE	0x43FAC000
+#define IOMUXC_SW_MUX_CTL(x)	(IOMUXC_BASE + 0xc + (x) * 4)
+#define IOMUXC_SW_PAD_CTL(x)	(IOMUXC_BASE + 0x154 + (x) * 4)
+
+#define IPU_BASE		0x53fc0000
+#define IPU_CONF		IPU_BASE
+
+#define IPU_CONF_PXL_ENDIAN	(1<<8)
+#define IPU_CONF_DU_EN		(1<<7)
+#define IPU_CONF_DI_EN		(1<<6)
+#define IPU_CONF_ADC_EN		(1<<5)
+#define IPU_CONF_SDC_EN		(1<<4)
+#define IPU_CONF_PF_EN		(1<<3)
+#define IPU_CONF_ROT_EN		(1<<2)
+#define IPU_CONF_IC_EN		(1<<1)
+#define IPU_CONF_CSI_EN		(1<<0)
+
+#define ARM_PPMRR		0x40000015
+
+#define WDOG1_BASE_ADDR		0x53FDC000
+
+/*
+ * GPIO
+ */
+#define GPIO1_BASE_ADDR	0x53FCC000
+#define GPIO2_BASE_ADDR	0x53FD0000
+#define GPIO3_BASE_ADDR	0x53FA4000
+#define GPIO_DR		0x00000000	/* data register */
+#define GPIO_GDIR	0x00000004	/* direction register */
+#define GPIO_PSR	0x00000008	/* pad status register */
+
+/*
+ * Signal Multiplexing (IOMUX)
+ */
+
+/* bits in the SW_MUX_CTL registers */
+#define MUX_CTL_OUT_GPIO_DR	(0 << 4)
+#define MUX_CTL_OUT_FUNC	(1 << 4)
+#define MUX_CTL_OUT_ALT1	(2 << 4)
+#define MUX_CTL_OUT_ALT2	(3 << 4)
+#define MUX_CTL_OUT_ALT3	(4 << 4)
+#define MUX_CTL_OUT_ALT4	(5 << 4)
+#define MUX_CTL_OUT_ALT5	(6 << 4)
+#define MUX_CTL_OUT_ALT6	(7 << 4)
+#define MUX_CTL_IN_NONE		(0 << 0)
+#define MUX_CTL_IN_GPIO		(1 << 0)
+#define MUX_CTL_IN_FUNC		(2 << 0)
+#define MUX_CTL_IN_ALT1		(4 << 0)
+#define MUX_CTL_IN_ALT2		(8 << 0)
+
+#define MUX_CTL_FUNC		(MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
+#define MUX_CTL_ALT1		(MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
+#define MUX_CTL_ALT2		(MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
+#define MUX_CTL_GPIO		(MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
+
+/* Register offsets based on IOMUXC_BASE */
+/* 0x00 .. 0x7b */
+#define MUX_CTL_CSPI3_MISO		0x0c
+#define MUX_CTL_CSPI3_SCLK		0x0d
+#define MUX_CTL_CSPI3_SPI_RDY	0x0e
+#define MUX_CTL_CSPI3_MOSI		0x13
+
+#define MUX_CTL_SD1_DATA1	0x18
+#define MUX_CTL_SD1_DATA2	0x19
+#define MUX_CTL_SD1_DATA3	0x1a
+#define MUX_CTL_SD1_CMD		0x1d
+#define MUX_CTL_SD1_CLK		0x1e
+#define MUX_CTL_SD1_DATA0	0x1f
+
+#define MUX_CTL_USBH2_DATA1	0x40
+#define MUX_CTL_USBH2_DIR	0x44
+#define MUX_CTL_USBH2_STP	0x45
+#define MUX_CTL_USBH2_NXT	0x46
+#define MUX_CTL_USBH2_DATA0	0x47
+#define MUX_CTL_USBH2_CLK	0x4B
+
+#define MUX_CTL_TXD2		0x70
+#define MUX_CTL_RTS2		0x71
+#define MUX_CTL_CTS2		0x72
+#define MUX_CTL_RXD2		0x77
+
+#define MUX_CTL_RTS1		0x7c
+#define MUX_CTL_CTS1		0x7d
+#define MUX_CTL_DTR_DCE1	0x7e
+#define MUX_CTL_DSR_DCE1	0x7f
+#define MUX_CTL_CSPI2_SCLK	0x80
+#define MUX_CTL_CSPI2_SPI_RDY	0x81
+#define MUX_CTL_RXD1		0x82
+#define MUX_CTL_TXD1		0x83
+#define MUX_CTL_CSPI2_MISO	0x84
+#define MUX_CTL_CSPI2_SS0	0x85
+#define MUX_CTL_CSPI2_SS1	0x86
+#define MUX_CTL_CSPI2_SS2	0x87
+#define MUX_CTL_CSPI1_SS2	0x88
+#define MUX_CTL_CSPI1_SCLK	0x89
+#define MUX_CTL_CSPI1_SPI_RDY	0x8a
+#define MUX_CTL_CSPI2_MOSI	0x8b
+#define MUX_CTL_CSPI1_MOSI	0x8c
+#define MUX_CTL_CSPI1_MISO	0x8d
+#define MUX_CTL_CSPI1_SS0	0x8e
+#define MUX_CTL_CSPI1_SS1	0x8f
+#define MUX_CTL_STXD6		0x90
+#define MUX_CTL_SRXD6		0x91
+#define MUX_CTL_SCK6		0x92
+#define MUX_CTL_SFS6		0x93
+
+#define MUX_CTL_STXD3		0x9C
+#define MUX_CTL_SRXD3		0x9D
+#define MUX_CTL_SCK3		0x9E
+#define MUX_CTL_SFS3		0x9F
+
+#define MUX_CTL_NFC_WP		0xD0
+#define MUX_CTL_NFC_CE		0xD1
+#define MUX_CTL_NFC_RB		0xD2
+#define MUX_CTL_NFC_WE		0xD4
+#define MUX_CTL_NFC_RE		0xD5
+#define MUX_CTL_NFC_ALE		0xD6
+#define MUX_CTL_NFC_CLE		0xD7
+
+
+#define MUX_CTL_CAPTURE		0x150
+#define MUX_CTL_COMPARE		0x151
+
+/*
+ * Helper macros for the MUX_[contact name]__[pin function] macros
+ */
+#define IOMUX_MODE_POS 9
+#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
+
+/*
+ * These macros can be used in mx31_gpio_mux() and have the form
+ * MUX_[contact name]__[pin function]
+ */
+#define MUX_RXD1__UART1_RXD_MUX	IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
+#define MUX_TXD1__UART1_TXD_MUX	IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
+#define MUX_RTS1__UART1_RTS_B	IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
+#define MUX_CTS1__UART1_CTS_B	IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
+
+#define MUX_RXD2__UART2_RXD_MUX	IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
+#define MUX_TXD2__UART2_TXD_MUX	IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
+#define MUX_RTS2__UART2_RTS_B	IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
+#define MUX_CTS2__UART2_CTS_B	IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
+
+#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
+	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
+
+#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
+	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
+
+#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
+#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
+
+/* PAD control registers for SDR/DDR */
+#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B	(IOMUXC_BASE + 0x26C)
+#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0	(IOMUXC_BASE + 0x270)
+#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS		(IOMUXC_BASE + 0x274)
+#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA		(IOMUXC_BASE + 0x278)
+#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4		(IOMUXC_BASE + 0x27C)
+#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1		(IOMUXC_BASE + 0x280)
+#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1		(IOMUXC_BASE + 0x284)
+#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2	(IOMUXC_BASE + 0x288)
+#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31	(IOMUXC_BASE + 0x28C)
+#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28	(IOMUXC_BASE + 0x290)
+#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25	(IOMUXC_BASE + 0x294)
+#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22	(IOMUXC_BASE + 0x298)
+#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19	(IOMUXC_BASE + 0x29C)
+#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16	(IOMUXC_BASE + 0x2A0)
+#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13	(IOMUXC_BASE + 0x2A4)
+#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10		(IOMUXC_BASE + 0x2A8)
+#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7		(IOMUXC_BASE + 0x2AC)
+#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4		(IOMUXC_BASE + 0x2B0)
+#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1		(IOMUXC_BASE + 0x2B4)
+#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1		(IOMUXC_BASE + 0x2B8)
+#define IOMUXC_SW_PAD_CTL_A21_A22_A23		(IOMUXC_BASE + 0x2BC)
+#define IOMUXC_SW_PAD_CTL_A18_A19_A20		(IOMUXC_BASE + 0x2C0)
+#define IOMUXC_SW_PAD_CTL_A15_A16_A17		(IOMUXC_BASE + 0x2C4)
+#define IOMUXC_SW_PAD_CTL_A12_A13_A14		(IOMUXC_BASE + 0x2C8)
+#define IOMUXC_SW_PAD_CTL_A10_MA10_A11		(IOMUXC_BASE + 0x2CC)
+#define IOMUXC_SW_PAD_CTL_A7_A8_A9		(IOMUXC_BASE + 0x2D0)
+#define IOMUXC_SW_PAD_CTL_A4_A5_A6		(IOMUXC_BASE + 0x2D4)
+#define IOMUXC_SW_PAD_CTL_A1_A2_A3		(IOMUXC_BASE + 0x2D8)
+#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0		(IOMUXC_BASE + 0x2DC)
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE	0x70000000
+#define CSD0_BASE	0x80000000
+#define CSD1_BASE	0x90000000
+#define CS0_BASE	0xA0000000
+#define CS1_BASE	0xA8000000
+#define CS2_BASE	0xB0000000
+#define CS3_BASE	0xB2000000
+#define CS4_BASE	0xB4000000
+#define CS4_PSRAM_BASE	0xB5000000
+#define CS5_BASE	0xB6000000
+#define PCMCIA_MEM_BASE	0xC0000000
+
+/*
+ * NAND controller
+ */
+#define NFC_BASE_ADDR	0xB8000000
+
+/* SD card controller */
+#define SDHC1_BASE_ADDR	0x50004000
+#define SDHC2_BASE_ADDR	0x50008000
+
+/*
+ * Internal RAM (16KB)
+ */
+#define	IRAM_BASE_ADDR	0x1FFFC000
+#define IRAM_SIZE	(16 * 1024)
+
+#define MX31_AIPS1_BASE_ADDR	0x43f00000
+#define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_PORT_OFFSET	0x200
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_SMC	(1 << 3)
+#define MXC_CSPICTRL_POL	(1 << 4)
+#define MXC_CSPICTRL_PHA	(1 << 5)
+#define MXC_CSPICTRL_SSCTL	(1 << 6)
+#define MXC_CSPICTRL_SSPOL	(1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC		(1 << 8)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPICTRL_MAXBITS	0x1f
+
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	4
+
+#define MXC_SPI_BASE_ADDRESSES \
+	0x43fa4000, \
+	0x50010000, \
+	0x53f84000,
+
+#endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/sys_proto.h
new file mode 100644
index 000000000..b0dfcba58
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx31/sys_proto.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2011
+ * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+struct mxc_weimcs {
+	u32 upper;
+	u32 lower;
+	u32 additional;
+};
+
+void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs);
+int mxc_mmc_init(bd_t *bis);
+u32 get_cpu_rev(void);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/clock.h
new file mode 100644
index 000000000..bc85aa73b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/clock.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+#ifdef CONFIG_MX35_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX35_HCLK_FREQ
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_MX35_CLK32
+#define MXC_CLK32	CONFIG_MX35_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
+enum mxc_clock {
+	MXC_ARM_CLK,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_IPG_PERCLK,
+	MXC_UART_CLK,
+	MXC_ESDHC1_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_USB_CLK,
+	MXC_CSPI_CLK,
+	MXC_FEC_CLK,
+	MXC_I2C_CLK,
+};
+
+enum mxc_main_clock {
+	CPU_CLK,
+	AHB_CLK,
+	IPG_CLK,
+	IPG_PER_CLK,
+	NFC_CLK,
+	USB_CLK,
+	HSP_CLK,
+};
+
+enum mxc_peri_clock {
+	UART1_BAUD,
+	UART2_BAUD,
+	UART3_BAUD,
+	SSI1_BAUD,
+	SSI2_BAUD,
+	CSI_BAUD,
+	MSHC_CLK,
+	ESDHC1_CLK,
+	ESDHC2_CLK,
+	ESDHC3_CLK,
+	SPDIF_CLK,
+	SPI1_CLK,
+	SPI2_CLK,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h
new file mode 100644
index 000000000..a58ebd523
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/crm_regs.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__
+#define __CPU_ARM1136_MX35_CRM_REGS_H__
+
+/* Register bit definitions */
+#define MXC_CCM_CCMR_WFI                        (1 << 30)
+#define MXC_CCM_CCMR_STBY_EXIT_SRC              (1 << 29)
+#define MXC_CCM_CCMR_VSTBY                      (1 << 28)
+#define MXC_CCM_CCMR_WBEN                       (1 << 27)
+#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET        20
+#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK          (0xF << 20)
+#define MXC_CCM_CCMR_ROMW_OFFSET               18
+#define MXC_CCM_CCMR_ROMW_MASK                 (0x3 << 18)
+#define MXC_CCM_CCMR_RAMW_OFFSET               16
+#define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 16)
+#define MXC_CCM_CCMR_LPM_OFFSET                 14
+#define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
+#define MXC_CCM_CCMR_UPE                        (1 << 9)
+#define MXC_CCM_CCMR_MPE                        (1 << 3)
+
+#define MXC_CCM_PDR0_PER_SEL			(1 << 26)
+#define MXC_CCM_PDR0_IPU_HND_BYP                (1 << 23)
+#define MXC_CCM_PDR0_HSP_PODF_OFFSET            20
+#define MXC_CCM_PDR0_HSP_PODF_MASK              (0x3 << 20)
+#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET		16
+#define MXC_CCM_PDR0_CON_MUX_DIV_MASK           (0xF << 16)
+#define MXC_CCM_PDR0_CKIL_SEL			(1 << 15)
+#define MXC_CCM_PDR0_PER_PODF_OFFSET            12
+#define MXC_CCM_PDR0_PER_PODF_MASK              (0x7 << 12)
+#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET        9
+#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK          (0x7 << 9)
+#define MXC_CCM_PDR0_AUTO_CON	                0x1
+
+#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET           28
+#define MXC_CCM_PDR1_MSHC_PRDF_MASK             (0x7 << 28)
+#define MXC_CCM_PDR1_MSHC_PODF_OFFSET           22
+#define MXC_CCM_PDR1_MSHC_PODF_MASK             (0x3F << 22)
+#define MXC_CCM_PDR1_MSHC_M_U			(1 << 7)
+
+#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET           27
+#define MXC_CCM_PDR2_SSI2_PRDF_MASK             (0x7 << 27)
+#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET           24
+#define MXC_CCM_PDR2_SSI1_PRDF_MASK             (0x7 << 24)
+#define MXC_CCM_PDR2_CSI_PODF_OFFSET            16
+#define MXC_CCM_PDR2_CSI_PODF_MASK              (0x3F << 16)
+#define MXC_CCM_PDR2_SSI2_PODF_OFFSET           8
+#define MXC_CCM_PDR2_SSI2_PODF_MASK             (0x3F << 8)
+#define MXC_CCM_PDR2_CSI_M_U			(1 << 7)
+#define MXC_CCM_PDR2_SSI_M_U			(1 << 6)
+#define MXC_CCM_PDR2_SSI1_PODF_OFFSET           0
+#define MXC_CCM_PDR2_SSI1_PODF_MASK             (0x3F)
+
+#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET          29
+#define MXC_CCM_PDR3_SPDIF_PRDF_MASK            (0x7 << 29)
+#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET          23
+#define MXC_CCM_PDR3_SPDIF_PODF_MASK            (0x3F << 23)
+#define MXC_CCM_PDR3_SPDIF_M_U			(1 << 22)
+#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET         16
+#define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x3F << 16)
+#define MXC_CCM_PDR3_UART_M_U			(1 << 14)
+#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET         8
+#define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x3F << 8)
+#define MXC_CCM_PDR3_ESDHC_M_U			(1 << 6)
+#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET         0
+#define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x3F)
+
+#define MXC_CCM_PDR4_NFC_PODF_OFFSET		28
+#define MXC_CCM_PDR4_NFC_PODF_MASK		(0xF << 28)
+#define MXC_CCM_PDR4_USB_PODF_OFFSET		22
+#define MXC_CCM_PDR4_USB_PODF_MASK		(0x3F << 22)
+#define MXC_CCM_PDR4_PER0_PODF_OFFSET		16
+#define MXC_CCM_PDR4_PER0_PODF_MASK		(0x3F << 16)
+#define MXC_CCM_PDR4_UART_PODF_OFFSET		10
+#define MXC_CCM_PDR4_UART_PODF_MASK		(0x3F << 10)
+#define MXC_CCM_PDR4_USB_M_U			(1 << 9)
+
+/* Bit definitions for RCSR */
+#define MXC_CCM_RCSR_BUS_WIDTH			(1 << 29)
+#define MXC_CCM_RCSR_BUS_16BIT			(1 << 29)
+#define MXC_CCM_RCSR_PAGE_SIZE			(3 << 27)
+#define MXC_CCM_RCSR_PAGE_512			(0 << 27)
+#define MXC_CCM_RCSR_PAGE_2K			(1 << 27)
+#define MXC_CCM_RCSR_PAGE_4K1			(2 << 27)
+#define MXC_CCM_RCSR_PAGE_4K2			(3 << 27)
+#define MXC_CCM_RCSR_SOFT_RESET			(1 << 15)
+#define MXC_CCM_RCSR_NF16B			(1 << 14)
+#define MXC_CCM_RCSR_NFC_4K			(1 << 9)
+#define MXC_CCM_RCSR_NFC_FMS			(1 << 8)
+
+/* Bit definitions for both MCU, PERIPHERAL PLL control registers */
+#define MXC_CCM_PCTL_BRM                        0x80000000
+#define MXC_CCM_PCTL_PD_OFFSET                  26
+#define MXC_CCM_PCTL_PD_MASK                    (0xF << 26)
+#define MXC_CCM_PCTL_MFD_OFFSET                 16
+#define MXC_CCM_PCTL_MFD_MASK                   (0x3FF << 16)
+#define MXC_CCM_PCTL_MFI_OFFSET                 10
+#define MXC_CCM_PCTL_MFI_MASK                   (0xF << 10)
+#define MXC_CCM_PCTL_MFN_OFFSET                 0
+#define MXC_CCM_PCTL_MFN_MASK                   0x3FF
+
+/* Bit definitions for Audio clock mux register*/
+#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET	12
+#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK		(0xF << 12)
+#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET	8
+#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK		(0xF << 8)
+#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET	4
+#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK		(0xF << 4)
+#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET	0
+#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK		(0xF << 0)
+
+/* Bit definitions for Clock gating Register*/
+#define MXC_CCM_CGR_CG_MASK			0x3
+#define MXC_CCM_CGR_CG_OFF			0x0
+#define MXC_CCM_CGR_CG_RUN_ON			0x1
+#define MXC_CCM_CGR_CG_RUN_WAIT_ON		0x2
+#define MXC_CCM_CGR_CG_ON			0x3
+
+#define MXC_CCM_CGR0_ASRC_OFFSET		0
+#define MXC_CCM_CGR0_ASRC_MASK			(0x3 << 0)
+#define MXC_CCM_CGR0_ATA_OFFSET			2
+#define MXC_CCM_CGR0_ATA_MASK			(0x3 << 2)
+#define MXC_CCM_CGR0_CAN1_OFFSET		6
+#define MXC_CCM_CGR0_CAN1_MASK			(0x3 << 6)
+#define MXC_CCM_CGR0_CAN2_OFFSET		8
+#define MXC_CCM_CGR0_CAN2_MASK			(0x3 << 8)
+#define MXC_CCM_CGR0_CSPI1_OFFSET		10
+#define MXC_CCM_CGR0_CSPI1_MASK			(0x3 << 10)
+#define MXC_CCM_CGR0_CSPI2_OFFSET		12
+#define MXC_CCM_CGR0_CSPI2_MASK			(0x3 << 12)
+#define MXC_CCM_CGR0_ECT_OFFSET			14
+#define MXC_CCM_CGR0_ECT_MASK			(0x3 << 14)
+#define MXC_CCM_CGR0_EDIO_OFFSET		16
+#define MXC_CCM_CGR0_EDIO_MASK			(0x3 << 16)
+#define MXC_CCM_CGR0_EMI_OFFSET			18
+#define MXC_CCM_CGR0_EMI_MASK			(0x3 << 18)
+#define MXC_CCM_CGR0_EPIT1_OFFSET		20
+#define MXC_CCM_CGR0_EPIT1_MASK			(0x3 << 20)
+#define MXC_CCM_CGR0_EPIT2_OFFSET		22
+#define MXC_CCM_CGR0_EPIT2_MASK			(0x3 << 22)
+#define MXC_CCM_CGR0_ESAI_OFFSET		24
+#define MXC_CCM_CGR0_ESAI_MASK			(0x3 << 24)
+#define MXC_CCM_CGR0_ESDHC1_OFFSET		26
+#define MXC_CCM_CGR0_ESDHC1_MASK		(0x3 << 26)
+#define MXC_CCM_CGR0_ESDHC2_OFFSET		28
+#define MXC_CCM_CGR0_ESDHC2_MASK		(0x3 << 28)
+#define MXC_CCM_CGR0_ESDHC3_OFFSET		30
+#define MXC_CCM_CGR0_ESDHC3_MASK		(0x3 << 30)
+
+#define MXC_CCM_CGR1_FEC_OFFSET			0
+#define MXC_CCM_CGR1_FEC_MASK			(0x3 << 0)
+#define MXC_CCM_CGR1_GPIO1_OFFSET		2
+#define MXC_CCM_CGR1_GPIO1_MASK			(0x3 << 2)
+#define MXC_CCM_CGR1_GPIO2_OFFSET		4
+#define MXC_CCM_CGR1_GPIO2_MASK			(0x3 << 4)
+#define MXC_CCM_CGR1_GPIO3_OFFSET		6
+#define MXC_CCM_CGR1_GPIO3_MASK			(0x3 << 6)
+#define MXC_CCM_CGR1_GPT_OFFSET			8
+#define MXC_CCM_CGR1_GPT_MASK			(0x3 << 8)
+#define MXC_CCM_CGR1_I2C1_OFFSET		10
+#define MXC_CCM_CGR1_I2C1_MASK			(0x3 << 10)
+#define MXC_CCM_CGR1_I2C2_OFFSET		12
+#define MXC_CCM_CGR1_I2C2_MASK			(0x3 << 12)
+#define MXC_CCM_CGR1_I2C3_OFFSET		14
+#define MXC_CCM_CGR1_I2C3_MASK			(0x3 << 14)
+#define MXC_CCM_CGR1_IOMUXC_OFFSET		16
+#define MXC_CCM_CGR1_IOMUXC_MASK		(0x3 << 16)
+#define MXC_CCM_CGR1_IPU_OFFSET			18
+#define MXC_CCM_CGR1_IPU_MASK			(0x3 << 18)
+#define MXC_CCM_CGR1_KPP_OFFSET			20
+#define MXC_CCM_CGR1_KPP_MASK			(0x3 << 20)
+#define MXC_CCM_CGR1_MLB_OFFSET			22
+#define MXC_CCM_CGR1_MLB_MASK			(0x3 << 22)
+#define MXC_CCM_CGR1_MSHC_OFFSET		24
+#define MXC_CCM_CGR1_MSHC_MASK			(0x3 << 24)
+#define MXC_CCM_CGR1_OWIRE_OFFSET		26
+#define MXC_CCM_CGR1_OWIRE_MASK			(0x3 << 26)
+#define MXC_CCM_CGR1_PWM_OFFSET			28
+#define MXC_CCM_CGR1_PWM_MASK			(0x3 << 28)
+#define MXC_CCM_CGR1_RNGC_OFFSET		30
+#define MXC_CCM_CGR1_RNGC_MASK			(0x3 << 30)
+
+#define MXC_CCM_CGR2_RTC_OFFSET			0
+#define MXC_CCM_CGR2_RTC_MASK			(0x3 << 0)
+#define MXC_CCM_CGR2_RTIC_OFFSET		2
+#define MXC_CCM_CGR2_RTIC_MASK			(0x3 << 2)
+#define MXC_CCM_CGR2_SCC_OFFSET			4
+#define MXC_CCM_CGR2_SCC_MASK			(0x3 << 4)
+#define MXC_CCM_CGR2_SDMA_OFFSET		6
+#define MXC_CCM_CGR2_SDMA_MASK			(0x3 << 6)
+#define MXC_CCM_CGR2_SPBA_OFFSET		8
+#define MXC_CCM_CGR2_SPBA_MASK			(0x3 << 8)
+#define MXC_CCM_CGR2_SPDIF_OFFSET		10
+#define MXC_CCM_CGR2_SPDIF_MASK			(0x3 << 10)
+#define MXC_CCM_CGR2_SSI1_OFFSET		12
+#define MXC_CCM_CGR2_SSI1_MASK			(0x3 << 12)
+#define MXC_CCM_CGR2_SSI2_OFFSET		14
+#define MXC_CCM_CGR2_SSI2_MASK			(0x3 << 14)
+#define MXC_CCM_CGR2_UART1_OFFSET		16
+#define MXC_CCM_CGR2_UART1_MASK			(0x3 << 16)
+#define MXC_CCM_CGR2_UART2_OFFSET		18
+#define MXC_CCM_CGR2_UART2_MASK			(0x3 << 18)
+#define MXC_CCM_CGR2_UART3_OFFSET		20
+#define MXC_CCM_CGR2_UART3_MASK			(0x3 << 20)
+#define MXC_CCM_CGR2_USBOTG_OFFSET		22
+#define MXC_CCM_CGR2_USBOTG_MASK		(0x3 << 22)
+#define MXC_CCM_CGR2_WDOG_OFFSET		24
+#define MXC_CCM_CGR2_WDOG_MASK			(0x3 << 24)
+#define MXC_CCM_CGR2_MAX_OFFSET			26
+#define MXC_CCM_CGR2_MAX_MASK			(0x3 << 26)
+#define MXC_CCM_CGR2_MAX_ENABLE			(0x2 << 26)
+#define MXC_CCM_CGR2_AUDMUX_OFFSET		30
+#define MXC_CCM_CGR2_AUDMUX_MASK		(0x3 << 30)
+
+#define MXC_CCM_CGR3_CSI_OFFSET			0
+#define MXC_CCM_CGR3_CSI_MASK			(0x3 << 0)
+#define MXC_CCM_CGR3_IIM_OFFSET			2
+#define MXC_CCM_CGR3_IIM_MASK			(0x3 << 2)
+#define MXC_CCM_CGR3_GPU2D_OFFSET		4
+#define MXC_CCM_CGR3_GPU2D_MASK			(0x3 << 4)
+
+#define MXC_CCM_COSR_CLKOSEL_MASK		0x1F
+#define MXC_CCM_COSR_CLKOSEL_OFFSET		0
+#define MXC_CCM_COSR_CLKOEN			(1 << 5)
+#define MXC_CCM_COSR_CLKOUTDIV_1		(1 << 6)
+#define MXC_CCM_COSR_CLKOUT_DIV_MASK		(0x3F << 10)
+#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET		10
+#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK	(0x3 << 16)
+#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET	16
+#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK	(0x3 << 18)
+#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET	18
+#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK	(0x3 << 20)
+#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET	20
+#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK	(0x3 << 22)
+#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET	22
+#define MXC_CCM_COSR_ASRC_AUDIO_EN		(1 << 24)
+#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK	(0x3F << 26)
+#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET	26
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/gpio.h
new file mode 100644
index 000000000..f3572a402
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/gpio.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __ASM_ARCH_MX35_GPIO_H
+#define __ASM_ARCH_MX35_GPIO_H
+
+#include <asm/imx-common/gpio.h>
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h
new file mode 100644
index 000000000..b5300291a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -0,0 +1,375 @@
+/*
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX35_H
+#define __ASM_ARCH_MX35_H
+
+#define ARCH_MXC
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR		0x10000000	/* internal ram */
+#define IRAM_SIZE		0x00020000	/* 128 KB */
+
+#define LOW_LEVEL_SRAM_STACK	0x1001E000
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR         0x43F00000
+#define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR           0x43F04000
+#define EVTMON_BASE_ADDR        0x43F08000
+#define CLKCTL_BASE_ADDR        0x43F0C000
+#define I2C1_BASE_ADDR		0x43F80000
+#define I2C3_BASE_ADDR          0x43F84000
+#define ATA_BASE_ADDR           0x43F8C000
+#define UART1_BASE		0x43F90000
+#define UART2_BASE		0x43F94000
+#define I2C2_BASE_ADDR          0x43F98000
+#define CSPI1_BASE_ADDR         0x43FA4000
+#define IOMUXC_BASE_ADDR        0x43FAC000
+
+/*
+ * SPBA
+ */
+#define SPBA_BASE_ADDR          0x50000000
+#define UART3_BASE		0x5000C000
+#define CSPI2_BASE_ADDR         0x50010000
+#define ATA_DMA_BASE_ADDR       0x50020000
+#define FEC_BASE_ADDR           0x50038000
+#define SPBA_CTRL_BASE_ADDR     0x5003C000
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR         0x53F00000
+#define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
+#define CCM_BASE_ADDR           0x53F80000
+#define GPT1_BASE_ADDR          0x53F90000
+#define EPIT1_BASE_ADDR         0x53F94000
+#define EPIT2_BASE_ADDR         0x53F98000
+#define GPIO3_BASE_ADDR         0x53FA4000
+#define MMC_SDHC1_BASE_ADDR	0x53FB4000
+#define MMC_SDHC2_BASE_ADDR	0x53FB8000
+#define MMC_SDHC3_BASE_ADDR	0x53FBC000
+#define IPU_CTRL_BASE_ADDR	0x53FC0000
+#define GPIO1_BASE_ADDR		0x53FCC000
+#define GPIO2_BASE_ADDR		0x53FD0000
+#define SDMA_BASE_ADDR		0x53FD4000
+#define RTC_BASE_ADDR		0x53FD8000
+#define WDOG1_BASE_ADDR		0x53FDC000
+#define PWM_BASE_ADDR		0x53FE0000
+#define RTIC_BASE_ADDR		0x53FEC000
+#define IIM_BASE_ADDR		0x53FF0000
+#define IMX_USB_BASE		0x53FF4000
+#define IMX_USB_PORT_OFFSET	0x400
+
+#define IMX_CCM_BASE		CCM_BASE_ADDR
+
+/*
+ * ROMPATCH and AVIC
+ */
+#define ROMPATCH_BASE_ADDR	0x60000000
+#define AVIC_BASE_ADDR		0x68000000
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define EXT_MEM_CTRL_BASE	0xB8000000
+#define ESDCTL_BASE_ADDR	0xB8001000
+#define WEIM_BASE_ADDR		0xB8002000
+#define WEIM_CTRL_CS0		WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1		(WEIM_BASE_ADDR + 0x10)
+#define WEIM_CTRL_CS2		(WEIM_BASE_ADDR + 0x20)
+#define WEIM_CTRL_CS3		(WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS4		(WEIM_BASE_ADDR + 0x40)
+#define WEIM_CTRL_CS5		(WEIM_BASE_ADDR + 0x50)
+#define M3IF_BASE_ADDR		0xB8003000
+#define EMI_BASE_ADDR		0xB8004000
+
+#define NFC_BASE_ADDR		0xBB000000
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR	0x70000000
+#define CSD0_BASE_ADDR		0x80000000
+#define CSD1_BASE_ADDR		0x90000000
+#define CS0_BASE_ADDR		0xA0000000
+#define CS1_BASE_ADDR		0xA8000000
+#define CS2_BASE_ADDR		0xB0000000
+#define CS3_BASE_ADDR		0xB2000000
+#define CS4_BASE_ADDR		0xB4000000
+#define CS5_BASE_ADDR		0xB6000000
+
+/*
+ * IRQ Controller Register Definitions.
+ */
+#define AVIC_NIMASK		0x04
+#define AVIC_INTTYPEH		0x18
+#define AVIC_INTTYPEL		0x1C
+
+/* L210 */
+#define L2CC_BASE_ADDR		0x30000000
+#define L2_CACHE_LINE_SIZE		32
+#define L2_CACHE_CTL_REG		0x100
+#define L2_CACHE_AUX_CTL_REG		0x104
+#define L2_CACHE_SYNC_REG		0x730
+#define L2_CACHE_INV_LINE_REG		0x770
+#define L2_CACHE_INV_WAY_REG		0x77C
+#define L2_CACHE_CLEAN_LINE_REG		0x7B0
+#define L2_CACHE_CLEAN_INV_LINE_REG	0x7F0
+#define L2_CACHE_DBG_CTL_REG		0xF40
+
+#define CLKMODE_AUTO		0
+#define CLKMODE_CONSUMER	1
+
+#define PLL_PD(x)		(((x) & 0xf) << 26)
+#define PLL_MFD(x)		(((x) & 0x3ff) << 16)
+#define PLL_MFI(x)		(((x) & 0xf) << 10)
+#define PLL_MFN(x)		(((x) & 0x3ff) << 0)
+
+#define _PLL_BRM(x)	((x) << 31)
+#define _PLL_PD(x)	(((x) - 1) << 26)
+#define _PLL_MFD(x)	(((x) - 1) << 16)
+#define _PLL_MFI(x)	((x) << 10)
+#define _PLL_MFN(x)	(x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+	 _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
+#define CSCR_U(x)	(WEIM_CTRL_CS#x + 0)
+#define CSCR_L(x)	(WEIM_CTRL_CS#x + 4)
+#define CSCR_A(x)	(WEIM_CTRL_CS#x + 8)
+
+#define IIM_SREV	0x24
+#define ROMPATCH_REV	0x40
+
+#define IPU_CONF	IPU_CTRL_BASE_ADDR
+
+#define IPU_CONF_PXL_ENDIAN	(1<<8)
+#define IPU_CONF_DU_EN		(1<<7)
+#define IPU_CONF_DI_EN		(1<<6)
+#define IPU_CONF_ADC_EN		(1<<5)
+#define IPU_CONF_SDC_EN		(1<<4)
+#define IPU_CONF_PF_EN		(1<<3)
+#define IPU_CONF_ROT_EN		(1<<2)
+#define IPU_CONF_IC_EN		(1<<1)
+#define IPU_CONF_CSI_EN		(1<<0)
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_SMC	(1 << 3)
+#define MXC_CSPICTRL_POL	(1 << 4)
+#define MXC_CSPICTRL_PHA	(1 << 5)
+#define MXC_CSPICTRL_SSCTL	(1 << 6)
+#define MXC_CSPICTRL_SSPOL	(1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	4
+
+#define MXC_SPI_BASE_ADDRESSES \
+	0x43fa4000, \
+	0x50010000,
+
+#define GPIO_PORT_NUM		3
+#define GPIO_NUM_PIN		32
+
+#define CHIP_REV_1_0		0x10
+#define CHIP_REV_2_0		0x20
+
+#define BOARD_REV_1_0		0x0
+#define BOARD_REV_2_0		0x1
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* Clock Control Module (CCM) registers */
+struct ccm_regs {
+	u32 ccmr;	/* Control */
+	u32 pdr0;	/* Post divider 0 */
+	u32 pdr1;	/* Post divider 1 */
+	u32 pdr2;	/* Post divider 2 */
+	u32 pdr3;	/* Post divider 3 */
+	u32 pdr4;	/* Post divider 4 */
+	u32 rcsr;	/* CCM Status */
+	u32 mpctl;	/* Core PLL Control */
+	u32 ppctl;	/* Peripheral PLL Control */
+	u32 acmr;	/* Audio clock mux */
+	u32 cosr;	/* Clock out source */
+	u32 cgr0;	/* Clock Gating Control 0 */
+	u32 cgr1;	/* Clock Gating Control 1 */
+	u32 cgr2;	/* Clock Gating Control 2 */
+	u32 cgr3;	/* Clock Gating Control 3 */
+	u32 reserved;
+	u32 dcvr0;	/* DPTC Comparator 0 */
+	u32 dcvr1;	/* DPTC Comparator 0 */
+	u32 dcvr2;	/* DPTC Comparator 0 */
+	u32 dcvr3;	/* DPTC Comparator 0 */
+	u32 ltr0;	/* Load Tracking 0 */
+	u32 ltr1;	/* Load Tracking 1 */
+	u32 ltr2;	/* Load Tracking 2 */
+	u32 ltr3;	/* Load Tracking 3 */
+	u32 ltbr0;	/* Load Tracking Buffer 0 */
+};
+
+/* IIM control registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prg_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+	u32 res1[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[3];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_7[8];
+	u32 uid[8];
+	u32 fuse16_31[0x10];
+};
+
+struct fuse_bank1_regs {
+	u32 fuse0_21[0x16];
+	u32 usr;
+	u32 fuse23_31[9];
+};
+
+/* General Purpose Timer (GPT) registers */
+struct gpt_regs {
+	u32 ctrl;	/* control */
+	u32 pre;	/* prescaler */
+	u32 stat;	/* status */
+	u32 intr;	/* interrupt */
+	u32 cmp[3];	/* output compare 1-3 */
+	u32 capt[2];	/* input capture 1-2 */
+	u32 counter;	/* counter */
+};
+
+/* CSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+	u32 test;
+};
+
+struct esdc_regs {
+	u32	esdctl0;
+	u32	esdcfg0;
+	u32	esdctl1;
+	u32	esdcfg1;
+	u32	esdmisc;
+	u32	reserved[4];
+	u32	esdcdly[5];
+	u32	esdcdlyl;
+};
+
+#define ESDC_MISC_RST		(1 << 1)
+#define ESDC_MISC_MDDR_EN	(1 << 2)
+#define ESDC_MISC_MDDR_DL_RST	(1 << 3)
+#define ESDC_MISC_DDR_EN	(1 << 8)
+#define ESDC_MISC_DDR2_EN	(1 << 9)
+
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+	u32 mpr0;
+	u32 pad00[3];
+	u32 sgpcr0;
+	u32 pad01[59];
+	u32 mpr1;
+	u32 pad02[3];
+	u32 sgpcr1;
+	u32 pad03[59];
+	u32 mpr2;
+	u32 pad04[3];
+	u32 sgpcr2;
+	u32 pad05[59];
+	u32 mpr3;
+	u32 pad06[3];
+	u32 sgpcr3;
+	u32 pad07[59];
+	u32 mpr4;
+	u32 pad08[3];
+	u32 sgpcr4;
+	u32 pad09[251];
+	u32 mgpcr0;
+	u32 pad10[63];
+	u32 mgpcr1;
+	u32 pad11[63];
+	u32 mgpcr2;
+	u32 pad12[63];
+	u32 mgpcr3;
+	u32 pad13[63];
+	u32 mgpcr4;
+	u32 pad14[63];
+	u32 mgpcr5;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+	u32 mpr_0_7;
+	u32 mpr_8_15;
+	u32 pad0[6];
+	u32 pacr_0_7;
+	u32 pacr_8_15;
+	u32 pacr_16_23;
+	u32 pacr_24_31;
+	u32 pad1[4];
+	u32 opacr_0_7;
+	u32 opacr_8_15;
+	u32 opacr_16_23;
+	u32 opacr_24_31;
+	u32 opacr_32_39;
+};
+
+/*
+ * NFMS bit in RCSR register for pagesize of nandflash
+ */
+#define NFMS_BIT		8
+#define NFMS_NF_DWIDTH		14
+#define NFMS_NF_PG_SZ		8
+
+#define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
+
+#endif
+#endif /* __ASM_ARCH_MX35_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h
new file mode 100644
index 000000000..5898b46f4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/iomux-mx35.h
@@ -0,0 +1,1260 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on mainline Linux i.MX iomux-mx35.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IOMUX_MX35_H__
+#define __IOMUX_MX35_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/*
+ * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*									    PAD    MUX   ALT INPSE PATH PADCTRL */
+enum {
+	MX35_PAD_CAPTURE__GPT_CAPIN1				= IOMUX_PAD(0x328, 0x004, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__GPT_CMPOUT2				= IOMUX_PAD(0x328, 0x004, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__CSPI2_SS1				= IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__EPIT1_EPITO				= IOMUX_PAD(0x328, 0x004, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__CCM_CLK32K				= IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__GPIO1_4				= IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL),
+
+	MX35_PAD_COMPARE__GPT_CMPOUT1				= IOMUX_PAD(0x32c, 0x008, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__GPT_CAPIN2				= IOMUX_PAD(0x32c, 0x008, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__GPT_CMPOUT3				= IOMUX_PAD(0x32c, 0x008, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__EPIT2_EPITO				= IOMUX_PAD(0x32c, 0x008, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__GPIO1_5				= IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__SDMA_EXTDMA_2				= IOMUX_PAD(0x32c, 0x008, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_WDOG_RST__WDOG_WDOG_B				= IOMUX_PAD(0x330, 0x00c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_WDOG_RST__IPU_FLASH_STROBE			= IOMUX_PAD(0x330, 0x00c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_WDOG_RST__GPIO1_6				= IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO1_0__GPIO1_0				= IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_0__CCM_PMIC_RDY				= IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_0__OWIRE_LINE				= IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_0__SDMA_EXTDMA_0				= IOMUX_PAD(0x334, 0x010, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO1_1__GPIO1_1				= IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__PWM_PWMO				= IOMUX_PAD(0x338, 0x014, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__CSPI1_SS2				= IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT			= IOMUX_PAD(0x338, 0x014, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__SDMA_EXTDMA_1				= IOMUX_PAD(0x338, 0x014, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO2_0__GPIO2_0				= IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK			= IOMUX_PAD(0x33c, 0x018, 1, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO3_0__GPIO3_0				= IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK			= IOMUX_PAD(0x340, 0x01c, 1, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RESET_IN_B__CCM_RESET_IN_B			= IOMUX_PAD(0x344, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_POR_B__CCM_POR_B				= IOMUX_PAD(0x348, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CLKO__CCM_CLKO					= IOMUX_PAD(0x34c, 0x020, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CLKO__GPIO1_8					= IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL),
+
+	MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0			= IOMUX_PAD(0x350, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1			= IOMUX_PAD(0x354, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0			= IOMUX_PAD(0x358, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1			= IOMUX_PAD(0x35c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26		= IOMUX_PAD(0x360, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_VSTBY__CCM_VSTBY				= IOMUX_PAD(0x364, 0x024, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_VSTBY__GPIO1_7					= IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL),
+
+	MX35_PAD_A0__EMI_EIM_DA_L_0				= IOMUX_PAD(0x368, 0x028, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A1__EMI_EIM_DA_L_1				= IOMUX_PAD(0x36c, 0x02c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A2__EMI_EIM_DA_L_2				= IOMUX_PAD(0x370, 0x030, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A3__EMI_EIM_DA_L_3				= IOMUX_PAD(0x374, 0x034, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A4__EMI_EIM_DA_L_4				= IOMUX_PAD(0x378, 0x038, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A5__EMI_EIM_DA_L_5				= IOMUX_PAD(0x37c, 0x03c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A6__EMI_EIM_DA_L_6				= IOMUX_PAD(0x380, 0x040, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A7__EMI_EIM_DA_L_7				= IOMUX_PAD(0x384, 0x044, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A8__EMI_EIM_DA_H_8				= IOMUX_PAD(0x388, 0x048, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A9__EMI_EIM_DA_H_9				= IOMUX_PAD(0x38c, 0x04c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A10__EMI_EIM_DA_H_10				= IOMUX_PAD(0x390, 0x050, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_MA10__EMI_MA10					= IOMUX_PAD(0x394, 0x054, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A11__EMI_EIM_DA_H_11				= IOMUX_PAD(0x398, 0x058, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A12__EMI_EIM_DA_H_12				= IOMUX_PAD(0x39c, 0x05c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A13__EMI_EIM_DA_H_13				= IOMUX_PAD(0x3a0, 0x060, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A14__EMI_EIM_DA_H2_14				= IOMUX_PAD(0x3a4, 0x064, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A15__EMI_EIM_DA_H2_15				= IOMUX_PAD(0x3a8, 0x068, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A16__EMI_EIM_A_16				= IOMUX_PAD(0x3ac, 0x06c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A17__EMI_EIM_A_17				= IOMUX_PAD(0x3b0, 0x070, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A18__EMI_EIM_A_18				= IOMUX_PAD(0x3b4, 0x074, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A19__EMI_EIM_A_19				= IOMUX_PAD(0x3b8, 0x078, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A20__EMI_EIM_A_20				= IOMUX_PAD(0x3bc, 0x07c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A21__EMI_EIM_A_21				= IOMUX_PAD(0x3c0, 0x080, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A22__EMI_EIM_A_22				= IOMUX_PAD(0x3c4, 0x084, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A23__EMI_EIM_A_23				= IOMUX_PAD(0x3c8, 0x088, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A24__EMI_EIM_A_24				= IOMUX_PAD(0x3cc, 0x08c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A25__EMI_EIM_A_25				= IOMUX_PAD(0x3d0, 0x090, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDBA1__EMI_EIM_SDBA1				= IOMUX_PAD(0x3d4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDBA0__EMI_EIM_SDBA0				= IOMUX_PAD(0x3d8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD0__EMI_DRAM_D_0				= IOMUX_PAD(0x3dc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1__EMI_DRAM_D_1				= IOMUX_PAD(0x3e0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD2__EMI_DRAM_D_2				= IOMUX_PAD(0x3e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD3__EMI_DRAM_D_3				= IOMUX_PAD(0x3e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD4__EMI_DRAM_D_4				= IOMUX_PAD(0x3ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD5__EMI_DRAM_D_5				= IOMUX_PAD(0x3f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD6__EMI_DRAM_D_6				= IOMUX_PAD(0x3f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD7__EMI_DRAM_D_7				= IOMUX_PAD(0x3f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD8__EMI_DRAM_D_8				= IOMUX_PAD(0x3fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD9__EMI_DRAM_D_9				= IOMUX_PAD(0x400, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD10__EMI_DRAM_D_10				= IOMUX_PAD(0x404, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD11__EMI_DRAM_D_11				= IOMUX_PAD(0x408, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD12__EMI_DRAM_D_12				= IOMUX_PAD(0x40c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD13__EMI_DRAM_D_13				= IOMUX_PAD(0x410, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD14__EMI_DRAM_D_14				= IOMUX_PAD(0x414, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD15__EMI_DRAM_D_15				= IOMUX_PAD(0x418, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD16__EMI_DRAM_D_16				= IOMUX_PAD(0x41c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD17__EMI_DRAM_D_17				= IOMUX_PAD(0x420, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD18__EMI_DRAM_D_18				= IOMUX_PAD(0x424, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD19__EMI_DRAM_D_19				= IOMUX_PAD(0x428, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD20__EMI_DRAM_D_20				= IOMUX_PAD(0x42c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD21__EMI_DRAM_D_21				= IOMUX_PAD(0x430, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD22__EMI_DRAM_D_22				= IOMUX_PAD(0x434, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD23__EMI_DRAM_D_23				= IOMUX_PAD(0x438, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD24__EMI_DRAM_D_24				= IOMUX_PAD(0x43c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD25__EMI_DRAM_D_25				= IOMUX_PAD(0x440, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD26__EMI_DRAM_D_26				= IOMUX_PAD(0x444, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD27__EMI_DRAM_D_27				= IOMUX_PAD(0x448, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD28__EMI_DRAM_D_28				= IOMUX_PAD(0x44c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD29__EMI_DRAM_D_29				= IOMUX_PAD(0x450, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD30__EMI_DRAM_D_30				= IOMUX_PAD(0x454, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD31__EMI_DRAM_D_31				= IOMUX_PAD(0x458, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM0__EMI_DRAM_DQM_0				= IOMUX_PAD(0x45c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM1__EMI_DRAM_DQM_1				= IOMUX_PAD(0x460, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM2__EMI_DRAM_DQM_2				= IOMUX_PAD(0x464, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM3__EMI_DRAM_DQM_3				= IOMUX_PAD(0x468, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_EB0__EMI_EIM_EB0_B				= IOMUX_PAD(0x46c, 0x094, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_EB1__EMI_EIM_EB1_B				= IOMUX_PAD(0x470, 0x098, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_OE__EMI_EIM_OE					= IOMUX_PAD(0x474, 0x09c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS0__EMI_EIM_CS0				= IOMUX_PAD(0x478, 0x0a0, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS1__EMI_EIM_CS1				= IOMUX_PAD(0x47c, 0x0a4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS1__EMI_NANDF_CE3				= IOMUX_PAD(0x47c, 0x0a4, 3, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS2__EMI_EIM_CS2				= IOMUX_PAD(0x480, 0x0a8, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS3__EMI_EIM_CS3				= IOMUX_PAD(0x484, 0x0ac, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS4__EMI_EIM_CS4				= IOMUX_PAD(0x488, 0x0b0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS4__EMI_DTACK_B				= IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL),
+	MX35_PAD_CS4__EMI_NANDF_CE1				= IOMUX_PAD(0x488, 0x0b0, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS4__GPIO1_20					= IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL),
+
+	MX35_PAD_CS5__EMI_EIM_CS5				= IOMUX_PAD(0x48c, 0x0b4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS5__CSPI2_SS2					= IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL),
+	MX35_PAD_CS5__CSPI1_SS2					= IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL),
+	MX35_PAD_CS5__EMI_NANDF_CE2				= IOMUX_PAD(0x48c, 0x0b4, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS5__GPIO1_21					= IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL),
+
+	MX35_PAD_NF_CE0__EMI_NANDF_CE0				= IOMUX_PAD(0x490, 0x0b8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NF_CE0__GPIO1_22				= IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL),
+
+	MX35_PAD_ECB__EMI_EIM_ECB				= IOMUX_PAD(0x494, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LBA__EMI_EIM_LBA				= IOMUX_PAD(0x498, 0x0bc, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_BCLK__EMI_EIM_BCLK				= IOMUX_PAD(0x49c, 0x0c0, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RW__EMI_EIM_RW					= IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RAS__EMI_DRAM_RAS				= IOMUX_PAD(0x4a4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CAS__EMI_DRAM_CAS				= IOMUX_PAD(0x4a8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDWE__EMI_DRAM_SDWE				= IOMUX_PAD(0x4ac, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0			= IOMUX_PAD(0x4b0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1			= IOMUX_PAD(0x4b4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDCLK__EMI_DRAM_SDCLK				= IOMUX_PAD(0x4b8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS0__EMI_DRAM_SDQS_0				= IOMUX_PAD(0x4bc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS1__EMI_DRAM_SDQS_1				= IOMUX_PAD(0x4c0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS2__EMI_DRAM_SDQS_2				= IOMUX_PAD(0x4c4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS3__EMI_DRAM_SDQS_3				= IOMUX_PAD(0x4c8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFWE_B__EMI_NANDF_WE_B				= IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3			= IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__GPIO2_18				= IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0			= IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFRE_B__EMI_NANDF_RE_B				= IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR			= IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__IPU_DISPB_BCLK				= IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__GPIO2_19				= IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1			= IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFALE__EMI_NANDF_ALE				= IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__USB_TOP_USBH2_STP			= IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__IPU_DISPB_CS0				= IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__GPIO2_20				= IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__ARM11P_TOP_TRACE_2			= IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFCLE__EMI_NANDF_CLE				= IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__USB_TOP_USBH2_NXT			= IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__IPU_DISPB_PAR_RS			= IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__GPIO2_21				= IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3			= IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFWP_B__EMI_NANDF_WP_B				= IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7			= IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__IPU_DISPB_WR				= IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__GPIO2_22				= IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL			= IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFRB__EMI_NANDF_RB				= IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRB__IPU_DISPB_RD				= IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRB__GPIO2_23					= IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL),
+	MX35_PAD_NFRB__ARM11P_TOP_TRCLK				= IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D15__EMI_EIM_D_15				= IOMUX_PAD(0x4e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D14__EMI_EIM_D_14				= IOMUX_PAD(0x4e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D13__EMI_EIM_D_13				= IOMUX_PAD(0x4ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D12__EMI_EIM_D_12				= IOMUX_PAD(0x4f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D11__EMI_EIM_D_11				= IOMUX_PAD(0x4f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D10__EMI_EIM_D_10				= IOMUX_PAD(0x4f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D9__EMI_EIM_D_9				= IOMUX_PAD(0x4fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D8__EMI_EIM_D_8				= IOMUX_PAD(0x500, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D7__EMI_EIM_D_7				= IOMUX_PAD(0x504, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D6__EMI_EIM_D_6				= IOMUX_PAD(0x508, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D5__EMI_EIM_D_5				= IOMUX_PAD(0x50c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D4__EMI_EIM_D_4				= IOMUX_PAD(0x510, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3__EMI_EIM_D_3				= IOMUX_PAD(0x514, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D2__EMI_EIM_D_2				= IOMUX_PAD(0x518, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D1__EMI_EIM_D_1				= IOMUX_PAD(0x51c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D0__EMI_EIM_D_0				= IOMUX_PAD(0x520, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D8__IPU_CSI_D_8				= IOMUX_PAD(0x524, 0x0e0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D8__KPP_COL_0				= IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D8__GPIO1_20				= IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL),
+	MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13			= IOMUX_PAD(0x524, 0x0e0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D9__IPU_CSI_D_9				= IOMUX_PAD(0x528, 0x0e4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D9__KPP_COL_1				= IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D9__GPIO1_21				= IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL),
+	MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14			= IOMUX_PAD(0x528, 0x0e4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D10__IPU_CSI_D_10				= IOMUX_PAD(0x52c, 0x0e8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D10__KPP_COL_2				= IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D10__GPIO1_22				= IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL),
+	MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15			= IOMUX_PAD(0x52c, 0x0e8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D11__IPU_CSI_D_11				= IOMUX_PAD(0x530, 0x0ec, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D11__KPP_COL_3				= IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D11__GPIO1_23				= IOMUX_PAD(0x530, 0x0ec, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D12__IPU_CSI_D_12				= IOMUX_PAD(0x534, 0x0f0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D12__KPP_ROW_0				= IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D12__GPIO1_24				= IOMUX_PAD(0x534, 0x0f0, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D13__IPU_CSI_D_13				= IOMUX_PAD(0x538, 0x0f4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D13__KPP_ROW_1				= IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D13__GPIO1_25				= IOMUX_PAD(0x538, 0x0f4, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D14__IPU_CSI_D_14				= IOMUX_PAD(0x53c, 0x0f8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D14__KPP_ROW_2				= IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D14__GPIO1_26				= IOMUX_PAD(0x53c, 0x0f8, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D15__IPU_CSI_D_15				= IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D15__KPP_ROW_3				= IOMUX_PAD(0x540, 0x0fc, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D15__GPIO1_27				= IOMUX_PAD(0x540, 0x0fc, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_MCLK__IPU_CSI_MCLK				= IOMUX_PAD(0x544, 0x100, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_MCLK__GPIO1_28				= IOMUX_PAD(0x544, 0x100, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC			= IOMUX_PAD(0x548, 0x104, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_VSYNC__GPIO1_29				= IOMUX_PAD(0x548, 0x104, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC			= IOMUX_PAD(0x54c, 0x108, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_HSYNC__GPIO1_30				= IOMUX_PAD(0x54c, 0x108, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK			= IOMUX_PAD(0x550, 0x10c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_PIXCLK__GPIO1_31				= IOMUX_PAD(0x550, 0x10c, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C1_CLK__I2C1_SCL				= IOMUX_PAD(0x554, 0x110, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C1_CLK__GPIO2_24				= IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK			= IOMUX_PAD(0x554, 0x110, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C1_DAT__I2C1_SDA				= IOMUX_PAD(0x558, 0x114, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C1_DAT__GPIO2_25				= IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C2_CLK__I2C2_SCL				= IOMUX_PAD(0x55c, 0x118, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__CAN1_TXCAN				= IOMUX_PAD(0x55c, 0x118, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR			= IOMUX_PAD(0x55c, 0x118, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__GPIO2_26				= IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2		= IOMUX_PAD(0x55c, 0x118, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C2_DAT__I2C2_SDA				= IOMUX_PAD(0x560, 0x11c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__CAN1_RXCAN				= IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC			= IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__GPIO2_27				= IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3		= IOMUX_PAD(0x560, 0x11c, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXD4__AUDMUX_AUD4_TXD				= IOMUX_PAD(0x564, 0x120, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXD4__GPIO2_28				= IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL),
+	MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0		= IOMUX_PAD(0x564, 0x120, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SRXD4__AUDMUX_AUD4_RXD				= IOMUX_PAD(0x568, 0x124, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SRXD4__GPIO2_29				= IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL),
+	MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1		= IOMUX_PAD(0x568, 0x124, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCK4__AUDMUX_AUD4_TXC				= IOMUX_PAD(0x56c, 0x128, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCK4__GPIO2_30					= IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2			= IOMUX_PAD(0x56c, 0x128, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS			= IOMUX_PAD(0x570, 0x12c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXFS4__GPIO2_31				= IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL),
+	MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3		= IOMUX_PAD(0x570, 0x12c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXD5__AUDMUX_AUD5_TXD				= IOMUX_PAD(0x574, 0x130, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXD5__SPDIF_SPDIF_OUT1			= IOMUX_PAD(0x574, 0x130, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXD5__CSPI2_MOSI				= IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL),
+	MX35_PAD_STXD5__GPIO1_0					= IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL),
+	MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4		= IOMUX_PAD(0x574, 0x130, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SRXD5__AUDMUX_AUD5_RXD				= IOMUX_PAD(0x578, 0x134, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__SPDIF_SPDIF_IN1				= IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__CSPI2_MISO				= IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__GPIO1_1					= IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5		= IOMUX_PAD(0x578, 0x134, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCK5__AUDMUX_AUD5_TXC				= IOMUX_PAD(0x57c, 0x138, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__CSPI2_SCLK				= IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__GPIO1_2					= IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6			= IOMUX_PAD(0x57c, 0x138, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS			= IOMUX_PAD(0x580, 0x13c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXFS5__CSPI2_RDY				= IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL),
+	MX35_PAD_STXFS5__GPIO1_3				= IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL),
+	MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7		= IOMUX_PAD(0x580, 0x13c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCKR__ESAI_SCKR				= IOMUX_PAD(0x584, 0x140, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCKR__GPIO1_4					= IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL),
+	MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10			= IOMUX_PAD(0x584, 0x140, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FSR__ESAI_FSR					= IOMUX_PAD(0x588, 0x144, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FSR__GPIO1_5					= IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL),
+	MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11			= IOMUX_PAD(0x588, 0x144, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_HCKR__ESAI_HCKR				= IOMUX_PAD(0x58c, 0x148, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__AUDMUX_AUD5_RXFS				= IOMUX_PAD(0x58c, 0x148, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__CSPI2_SS0				= IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__IPU_FLASH_STROBE				= IOMUX_PAD(0x58c, 0x148, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__GPIO1_6					= IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL),
+	MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12			= IOMUX_PAD(0x58c, 0x148, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCKT__ESAI_SCKT				= IOMUX_PAD(0x590, 0x14c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCKT__GPIO1_7					= IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL),
+	MX35_PAD_SCKT__IPU_CSI_D_0				= IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL),
+	MX35_PAD_SCKT__KPP_ROW_2				= IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL),
+
+	MX35_PAD_FST__ESAI_FST					= IOMUX_PAD(0x594, 0x150, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FST__GPIO1_8					= IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL),
+	MX35_PAD_FST__IPU_CSI_D_1				= IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL),
+	MX35_PAD_FST__KPP_ROW_3					= IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL),
+
+	MX35_PAD_HCKT__ESAI_HCKT				= IOMUX_PAD(0x598, 0x154, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__AUDMUX_AUD5_RXC				= IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__GPIO1_9					= IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__IPU_CSI_D_2				= IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__KPP_COL_3				= IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX5_RX0__ESAI_TX5_RX0				= IOMUX_PAD(0x59c, 0x158, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC			= IOMUX_PAD(0x59c, 0x158, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__CSPI2_SS2				= IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__CAN2_TXCAN				= IOMUX_PAD(0x59c, 0x158, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__UART2_DTR				= IOMUX_PAD(0x59c, 0x158, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__GPIO1_10				= IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0		= IOMUX_PAD(0x59c, 0x158, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TX4_RX1__ESAI_TX4_RX1				= IOMUX_PAD(0x5a0, 0x15c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS			= IOMUX_PAD(0x5a0, 0x15c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__CSPI2_SS3				= IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__CAN2_RXCAN				= IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__UART2_DSR				= IOMUX_PAD(0x5a0, 0x15c, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__GPIO1_11				= IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__IPU_CSI_D_3				= IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__KPP_ROW_0				= IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX3_RX2__ESAI_TX3_RX2				= IOMUX_PAD(0x5a4, 0x160, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__I2C3_SCL				= IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__EMI_NANDF_CE1				= IOMUX_PAD(0x5a4, 0x160, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__GPIO1_12				= IOMUX_PAD(0x5a4, 0x160, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__IPU_CSI_D_4				= IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__KPP_ROW_1				= IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX2_RX3__ESAI_TX2_RX3				= IOMUX_PAD(0x5a8, 0x164, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__I2C3_SDA				= IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__EMI_NANDF_CE2				= IOMUX_PAD(0x5a8, 0x164, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__GPIO1_13				= IOMUX_PAD(0x5a8, 0x164, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__IPU_CSI_D_5				= IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__KPP_COL_0				= IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX1__ESAI_TX1					= IOMUX_PAD(0x5ac, 0x168, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__CCM_PMIC_RDY				= IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL),
+	MX35_PAD_TX1__CSPI1_SS2					= IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL),
+	MX35_PAD_TX1__EMI_NANDF_CE3				= IOMUX_PAD(0x5ac, 0x168, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__UART2_RI					= IOMUX_PAD(0x5ac, 0x168, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__GPIO1_14					= IOMUX_PAD(0x5ac, 0x168, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__IPU_CSI_D_6				= IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL),
+	MX35_PAD_TX1__KPP_COL_1					= IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX0__ESAI_TX0					= IOMUX_PAD(0x5b0, 0x16c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL),
+	MX35_PAD_TX0__CSPI1_SS3					= IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL),
+	MX35_PAD_TX0__EMI_DTACK_B				= IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL),
+	MX35_PAD_TX0__UART2_DCD					= IOMUX_PAD(0x5b0, 0x16c, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX0__GPIO1_15					= IOMUX_PAD(0x5b0, 0x16c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX0__IPU_CSI_D_7				= IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL),
+	MX35_PAD_TX0__KPP_COL_2					= IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_MOSI__CSPI1_MOSI				= IOMUX_PAD(0x5b4, 0x170, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MOSI__GPIO1_16				= IOMUX_PAD(0x5b4, 0x170, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2		= IOMUX_PAD(0x5b4, 0x170, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_MISO__CSPI1_MISO				= IOMUX_PAD(0x5b8, 0x174, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MISO__GPIO1_17				= IOMUX_PAD(0x5b8, 0x174, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3		= IOMUX_PAD(0x5b8, 0x174, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SS0__CSPI1_SS0				= IOMUX_PAD(0x5bc, 0x178, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__OWIRE_LINE				= IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__CSPI2_SS3				= IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__GPIO1_18				= IOMUX_PAD(0x5bc, 0x178, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4			= IOMUX_PAD(0x5bc, 0x178, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SS1__CSPI1_SS1				= IOMUX_PAD(0x5c0, 0x17c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__PWM_PWMO				= IOMUX_PAD(0x5c0, 0x17c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__CCM_CLK32K				= IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__GPIO1_19				= IOMUX_PAD(0x5c0, 0x17c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__IPU_DIAGB_29			= IOMUX_PAD(0x5c0, 0x17c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5			= IOMUX_PAD(0x5c0, 0x17c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SCLK__CSPI1_SCLK				= IOMUX_PAD(0x5c4, 0x180, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SCLK__GPIO3_4				= IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30			= IOMUX_PAD(0x5c4, 0x180, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1		= IOMUX_PAD(0x5c4, 0x180, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY			= IOMUX_PAD(0x5c8, 0x184, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SPI_RDY__GPIO3_5				= IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31			= IOMUX_PAD(0x5c8, 0x184, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2	= IOMUX_PAD(0x5c8, 0x184, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RXD1__UART1_RXD_MUX				= IOMUX_PAD(0x5cc, 0x188, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RXD1__CSPI2_MOSI				= IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL),
+	MX35_PAD_RXD1__KPP_COL_4				= IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL),
+	MX35_PAD_RXD1__GPIO3_6					= IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL),
+	MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16			= IOMUX_PAD(0x5cc, 0x188, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TXD1__UART1_TXD_MUX				= IOMUX_PAD(0x5d0, 0x18c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TXD1__CSPI2_MISO				= IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL),
+	MX35_PAD_TXD1__KPP_COL_5				= IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL),
+	MX35_PAD_TXD1__GPIO3_7					= IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL),
+	MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17			= IOMUX_PAD(0x5d0, 0x18c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RTS1__UART1_RTS				= IOMUX_PAD(0x5d4, 0x190, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__CSPI2_SCLK				= IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS1__I2C3_SCL					= IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS1__IPU_CSI_D_0				= IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS1__KPP_COL_6				= IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__GPIO3_8					= IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__EMI_NANDF_CE1				= IOMUX_PAD(0x5d4, 0x190, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18			= IOMUX_PAD(0x5d4, 0x190, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CTS1__UART1_CTS				= IOMUX_PAD(0x5d8, 0x194, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__CSPI2_RDY				= IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS1__I2C3_SDA					= IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS1__IPU_CSI_D_1				= IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS1__KPP_COL_7				= IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__GPIO3_9					= IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__EMI_NANDF_CE2				= IOMUX_PAD(0x5d8, 0x194, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19			= IOMUX_PAD(0x5d8, 0x194, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RXD2__UART2_RXD_MUX				= IOMUX_PAD(0x5dc, 0x198, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RXD2__KPP_ROW_4				= IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL),
+	MX35_PAD_RXD2__GPIO3_10					= IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL),
+
+	MX35_PAD_TXD2__UART2_TXD_MUX				= IOMUX_PAD(0x5e0, 0x19c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL),
+	MX35_PAD_TXD2__KPP_ROW_5				= IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL),
+	MX35_PAD_TXD2__GPIO3_11					= IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL),
+
+	MX35_PAD_RTS2__UART2_RTS				= IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__SPDIF_SPDIF_IN1				= IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS2__CAN2_RXCAN				= IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS2__IPU_CSI_D_2				= IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS2__KPP_ROW_6				= IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__GPIO3_12					= IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__AUDMUX_AUD5_RXC				= IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__UART3_RXD_MUX				= IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL),
+
+	MX35_PAD_CTS2__UART2_CTS				= IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__SPDIF_SPDIF_OUT1				= IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__CAN2_TXCAN				= IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__IPU_CSI_D_3				= IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS2__KPP_ROW_7				= IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__GPIO3_13					= IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__AUDMUX_AUD5_RXFS				= IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__UART3_TXD_MUX				= IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RTCK__ARM11P_TOP_RTCK				= IOMUX_PAD(0x5ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TCK__SJC_TCK					= IOMUX_PAD(0x5f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TMS__SJC_TMS					= IOMUX_PAD(0x5f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TDI__SJC_TDI					= IOMUX_PAD(0x5f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TDO__SJC_TDO					= IOMUX_PAD(0x5fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TRSTB__SJC_TRSTB				= IOMUX_PAD(0x600, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DE_B__SJC_DE_B					= IOMUX_PAD(0x604, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SJC_MOD__SJC_MOD				= IOMUX_PAD(0x608, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR			= IOMUX_PAD(0x60c, 0x1a8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR			= IOMUX_PAD(0x60c, 0x1a8, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_PWR__GPIO3_14				= IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL),
+
+	MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC			= IOMUX_PAD(0x610, 0x1ac, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC			= IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_OC__GPIO3_15				= IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL),
+
+	MX35_PAD_LD0__IPU_DISPB_DAT_0				= IOMUX_PAD(0x614, 0x1b0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD0__GPIO2_0					= IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL),
+	MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0			= IOMUX_PAD(0x614, 0x1b0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD1__IPU_DISPB_DAT_1				= IOMUX_PAD(0x618, 0x1b4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD1__GPIO2_1					= IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL),
+	MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1			= IOMUX_PAD(0x618, 0x1b4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD2__IPU_DISPB_DAT_2				= IOMUX_PAD(0x61c, 0x1b8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD2__GPIO2_2					= IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2			= IOMUX_PAD(0x61c, 0x1b8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD3__IPU_DISPB_DAT_3				= IOMUX_PAD(0x620, 0x1bc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD3__GPIO2_3					= IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL),
+	MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3			= IOMUX_PAD(0x620, 0x1bc, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD4__IPU_DISPB_DAT_4				= IOMUX_PAD(0x624, 0x1c0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD4__GPIO2_4					= IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4			= IOMUX_PAD(0x624, 0x1c0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD5__IPU_DISPB_DAT_5				= IOMUX_PAD(0x628, 0x1c4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD5__GPIO2_5					= IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL),
+	MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5			= IOMUX_PAD(0x628, 0x1c4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD6__IPU_DISPB_DAT_6				= IOMUX_PAD(0x62c, 0x1c8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD6__GPIO2_6					= IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL),
+	MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6			= IOMUX_PAD(0x62c, 0x1c8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD7__IPU_DISPB_DAT_7				= IOMUX_PAD(0x630, 0x1cc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD7__GPIO2_7					= IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL),
+	MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7			= IOMUX_PAD(0x630, 0x1cc, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD8__IPU_DISPB_DAT_8				= IOMUX_PAD(0x634, 0x1d0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD8__GPIO2_8					= IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8			= IOMUX_PAD(0x634, 0x1d0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD9__IPU_DISPB_DAT_9				= IOMUX_PAD(0x638, 0x1d4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD9__GPIO2_9					= IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL),
+	MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9			= IOMUX_PAD(0x638, 0x1d4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD10__IPU_DISPB_DAT_10				= IOMUX_PAD(0x63c, 0x1d8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD10__GPIO2_10					= IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10			= IOMUX_PAD(0x63c, 0x1d8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD11__IPU_DISPB_DAT_11				= IOMUX_PAD(0x640, 0x1dc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD11__GPIO2_11					= IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL),
+	MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11			= IOMUX_PAD(0x640, 0x1dc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD11__ARM11P_TOP_TRACE_4			= IOMUX_PAD(0x640, 0x1dc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD12__IPU_DISPB_DAT_12				= IOMUX_PAD(0x644, 0x1e0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD12__GPIO2_12					= IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL),
+	MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12			= IOMUX_PAD(0x644, 0x1e0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD12__ARM11P_TOP_TRACE_5			= IOMUX_PAD(0x644, 0x1e0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD13__IPU_DISPB_DAT_13				= IOMUX_PAD(0x648, 0x1e4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD13__GPIO2_13					= IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL),
+	MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13			= IOMUX_PAD(0x648, 0x1e4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD13__ARM11P_TOP_TRACE_6			= IOMUX_PAD(0x648, 0x1e4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD14__IPU_DISPB_DAT_14				= IOMUX_PAD(0x64c, 0x1e8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD14__GPIO2_14					= IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0		= IOMUX_PAD(0x64c, 0x1e8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD14__ARM11P_TOP_TRACE_7			= IOMUX_PAD(0x64c, 0x1e8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD15__IPU_DISPB_DAT_15				= IOMUX_PAD(0x650, 0x1ec, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD15__GPIO2_15					= IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL),
+	MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1		= IOMUX_PAD(0x650, 0x1ec, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD15__ARM11P_TOP_TRACE_8			= IOMUX_PAD(0x650, 0x1ec, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD16__IPU_DISPB_DAT_16				= IOMUX_PAD(0x654, 0x1f0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD16__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL),
+	MX35_PAD_LD16__GPIO2_16					= IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL),
+	MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2		= IOMUX_PAD(0x654, 0x1f0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD16__ARM11P_TOP_TRACE_9			= IOMUX_PAD(0x654, 0x1f0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD17__IPU_DISPB_DAT_17				= IOMUX_PAD(0x658, 0x1f4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD17__IPU_DISPB_CS2				= IOMUX_PAD(0x658, 0x1f4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD17__GPIO2_17					= IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL),
+	MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3		= IOMUX_PAD(0x658, 0x1f4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD17__ARM11P_TOP_TRACE_10			= IOMUX_PAD(0x658, 0x1f4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD18__IPU_DISPB_DAT_18				= IOMUX_PAD(0x65c, 0x1f8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD18__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL),
+	MX35_PAD_LD18__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL),
+	MX35_PAD_LD18__ESDHC3_CMD				= IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL),
+	MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3			= IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD18__GPIO3_24					= IOMUX_PAD(0x65c, 0x1f8, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4		= IOMUX_PAD(0x65c, 0x1f8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD18__ARM11P_TOP_TRACE_11			= IOMUX_PAD(0x65c, 0x1f8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD19__IPU_DISPB_DAT_19				= IOMUX_PAD(0x660, 0x1fc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__IPU_DISPB_BCLK				= IOMUX_PAD(0x660, 0x1fc, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__IPU_DISPB_CS1				= IOMUX_PAD(0x660, 0x1fc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__ESDHC3_CLK				= IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL),
+	MX35_PAD_LD19__USB_TOP_USBOTG_DIR			= IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL),
+	MX35_PAD_LD19__GPIO3_25					= IOMUX_PAD(0x660, 0x1fc, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5		= IOMUX_PAD(0x660, 0x1fc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__ARM11P_TOP_TRACE_12			= IOMUX_PAD(0x660, 0x1fc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD20__IPU_DISPB_DAT_20				= IOMUX_PAD(0x664, 0x200, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__IPU_DISPB_CS0				= IOMUX_PAD(0x664, 0x200, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__IPU_DISPB_SD_CLK				= IOMUX_PAD(0x664, 0x200, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__ESDHC3_DAT0				= IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD20__GPIO3_26					= IOMUX_PAD(0x664, 0x200, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3		= IOMUX_PAD(0x664, 0x200, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__ARM11P_TOP_TRACE_13			= IOMUX_PAD(0x664, 0x200, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD21__IPU_DISPB_DAT_21				= IOMUX_PAD(0x668, 0x204, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__IPU_DISPB_PAR_RS				= IOMUX_PAD(0x668, 0x204, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__IPU_DISPB_SER_RS				= IOMUX_PAD(0x668, 0x204, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__ESDHC3_DAT1				= IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL),
+	MX35_PAD_LD21__USB_TOP_USBOTG_STP			= IOMUX_PAD(0x668, 0x204, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__GPIO3_27					= IOMUX_PAD(0x668, 0x204, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL		= IOMUX_PAD(0x668, 0x204, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__ARM11P_TOP_TRACE_14			= IOMUX_PAD(0x668, 0x204, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD22__IPU_DISPB_DAT_22				= IOMUX_PAD(0x66c, 0x208, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__IPU_DISPB_WR				= IOMUX_PAD(0x66c, 0x208, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__IPU_DISPB_SD_D_I				= IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD22__ESDHC3_DAT2				= IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL),
+	MX35_PAD_LD22__USB_TOP_USBOTG_NXT			= IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL),
+	MX35_PAD_LD22__GPIO3_28					= IOMUX_PAD(0x66c, 0x208, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR			= IOMUX_PAD(0x66c, 0x208, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__ARM11P_TOP_TRCTL				= IOMUX_PAD(0x66c, 0x208, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD23__IPU_DISPB_DAT_23				= IOMUX_PAD(0x670, 0x20c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__IPU_DISPB_RD				= IOMUX_PAD(0x670, 0x20c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL),
+	MX35_PAD_LD23__ESDHC3_DAT3				= IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL),
+	MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7			= IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD23__GPIO3_29					= IOMUX_PAD(0x670, 0x20c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS			= IOMUX_PAD(0x670, 0x20c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__ARM11P_TOP_TRCLK				= IOMUX_PAD(0x670, 0x20c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC			= IOMUX_PAD(0x674, 0x210, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__GPIO3_30				= IOMUX_PAD(0x674, 0x210, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE		= IOMUX_PAD(0x674, 0x210, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15			= IOMUX_PAD(0x674, 0x210, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK			= IOMUX_PAD(0x678, 0x214, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK			= IOMUX_PAD(0x678, 0x214, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__GPIO3_31				= IOMUX_PAD(0x678, 0x214, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0	= IOMUX_PAD(0x678, 0x214, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16		= IOMUX_PAD(0x678, 0x214, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY			= IOMUX_PAD(0x67c, 0x218, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O			= IOMUX_PAD(0x67c, 0x218, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__GPIO1_0				= IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1		= IOMUX_PAD(0x67c, 0x218, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17			= IOMUX_PAD(0x67c, 0x218, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CONTRAST__IPU_DISPB_CONTR			= IOMUX_PAD(0x680, 0x21c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CONTRAST__GPIO1_1				= IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL),
+	MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2	= IOMUX_PAD(0x680, 0x21c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18			= IOMUX_PAD(0x680, 0x21c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC			= IOMUX_PAD(0x684, 0x220, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__IPU_DISPB_CS1			= IOMUX_PAD(0x684, 0x220, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__GPIO1_2				= IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD			= IOMUX_PAD(0x684, 0x220, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19			= IOMUX_PAD(0x684, 0x220, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_REV__IPU_DISPB_D3_REV			= IOMUX_PAD(0x688, 0x224, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__IPU_DISPB_SER_RS			= IOMUX_PAD(0x688, 0x224, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__GPIO1_3				= IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB			= IOMUX_PAD(0x688, 0x224, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20			= IOMUX_PAD(0x688, 0x224, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS			= IOMUX_PAD(0x68c, 0x228, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__IPU_DISPB_CS2				= IOMUX_PAD(0x68c, 0x228, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__GPIO1_4				= IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0		= IOMUX_PAD(0x68c, 0x228, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21			= IOMUX_PAD(0x68c, 0x228, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL			= IOMUX_PAD(0x690, 0x22c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__GPIO1_5				= IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1		= IOMUX_PAD(0x690, 0x22c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22			= IOMUX_PAD(0x690, 0x22c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_CMD__ESDHC1_CMD				= IOMUX_PAD(0x694, 0x230, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__MSHC_SCLK				= IOMUX_PAD(0x694, 0x230, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4			= IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__GPIO1_6				= IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL			= IOMUX_PAD(0x694, 0x230, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_CLK__ESDHC1_CLK				= IOMUX_PAD(0x698, 0x234, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__MSHC_BS				= IOMUX_PAD(0x698, 0x234, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__IPU_DISPB_BCLK			= IOMUX_PAD(0x698, 0x234, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5			= IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__GPIO1_7				= IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK			= IOMUX_PAD(0x698, 0x234, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA0__ESDHC1_DAT0				= IOMUX_PAD(0x69c, 0x238, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__MSHC_DATA_0				= IOMUX_PAD(0x69c, 0x238, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__IPU_DISPB_CS0			= IOMUX_PAD(0x69c, 0x238, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6		= IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__GPIO1_8				= IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23			= IOMUX_PAD(0x69c, 0x238, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA1__ESDHC1_DAT1				= IOMUX_PAD(0x6a0, 0x23c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__MSHC_DATA_1				= IOMUX_PAD(0x6a0, 0x23c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS			= IOMUX_PAD(0x6a0, 0x23c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0		= IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__GPIO1_9				= IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24			= IOMUX_PAD(0x6a0, 0x23c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA2__ESDHC1_DAT2				= IOMUX_PAD(0x6a4, 0x240, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__MSHC_DATA_2				= IOMUX_PAD(0x6a4, 0x240, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__IPU_DISPB_WR			= IOMUX_PAD(0x6a4, 0x240, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1		= IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__GPIO1_10				= IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25			= IOMUX_PAD(0x6a4, 0x240, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA3__ESDHC1_DAT3				= IOMUX_PAD(0x6a8, 0x244, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__MSHC_DATA_3				= IOMUX_PAD(0x6a8, 0x244, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__IPU_DISPB_RD			= IOMUX_PAD(0x6a8, 0x244, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2		= IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__GPIO1_11				= IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26			= IOMUX_PAD(0x6a8, 0x244, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_CMD__ESDHC2_CMD				= IOMUX_PAD(0x6ac, 0x248, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__I2C3_SCL				= IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__ESDHC1_DAT4				= IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__IPU_CSI_D_2				= IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4			= IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__GPIO2_0				= IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1			= IOMUX_PAD(0x6ac, 0x248, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_CLK__ESDHC2_CLK				= IOMUX_PAD(0x6b0, 0x24c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__I2C3_SDA				= IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__ESDHC1_DAT5				= IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__IPU_CSI_D_3				= IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5			= IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__GPIO2_1				= IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1			= IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__IPU_DISPB_CS2				= IOMUX_PAD(0x6b0, 0x24c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA0__ESDHC2_DAT0				= IOMUX_PAD(0x6b4, 0x250, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__UART3_RXD_MUX			= IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__ESDHC1_DAT6				= IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__IPU_CSI_D_4				= IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6		= IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__GPIO2_2				= IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA1__ESDHC2_DAT1				= IOMUX_PAD(0x6b8, 0x254, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__UART3_TXD_MUX			= IOMUX_PAD(0x6b8, 0x254, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__ESDHC1_DAT7				= IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__IPU_CSI_D_5				= IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0		= IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__GPIO2_3				= IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA2__ESDHC2_DAT2				= IOMUX_PAD(0x6bc, 0x258, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__UART3_RTS				= IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__CAN1_RXCAN				= IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__IPU_CSI_D_6				= IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1		= IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__GPIO2_4				= IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA3__ESDHC2_DAT3				= IOMUX_PAD(0x6c0, 0x25c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__UART3_CTS				= IOMUX_PAD(0x6c0, 0x25c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__CAN1_TXCAN				= IOMUX_PAD(0x6c0, 0x25c, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__IPU_CSI_D_7				= IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2		= IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__GPIO2_5				= IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_CS0__ATA_CS0				= IOMUX_PAD(0x6c4, 0x260, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__CSPI1_SS3				= IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__IPU_DISPB_CS1				= IOMUX_PAD(0x6c4, 0x260, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__GPIO2_6				= IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__IPU_DIAGB_0				= IOMUX_PAD(0x6c4, 0x260, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0		= IOMUX_PAD(0x6c4, 0x260, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_CS1__ATA_CS1				= IOMUX_PAD(0x6c8, 0x264, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__IPU_DISPB_CS2				= IOMUX_PAD(0x6c8, 0x264, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__CSPI2_SS0				= IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__GPIO2_7				= IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__IPU_DIAGB_1				= IOMUX_PAD(0x6c8, 0x264, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1		= IOMUX_PAD(0x6c8, 0x264, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DIOR__ATA_DIOR				= IOMUX_PAD(0x6cc, 0x268, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__ESDHC3_DAT0				= IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR			= IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__IPU_DISPB_BE0			= IOMUX_PAD(0x6cc, 0x268, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__CSPI2_SS1				= IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__GPIO2_8				= IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__IPU_DIAGB_2				= IOMUX_PAD(0x6cc, 0x268, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2		= IOMUX_PAD(0x6cc, 0x268, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DIOW__ATA_DIOW				= IOMUX_PAD(0x6d0, 0x26c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__ESDHC3_DAT1				= IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP			= IOMUX_PAD(0x6d0, 0x26c, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__IPU_DISPB_BE1			= IOMUX_PAD(0x6d0, 0x26c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__CSPI2_MOSI				= IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__GPIO2_9				= IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__IPU_DIAGB_3				= IOMUX_PAD(0x6d0, 0x26c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3		= IOMUX_PAD(0x6d0, 0x26c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DMACK__ATA_DMACK				= IOMUX_PAD(0x6d4, 0x270, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__ESDHC3_DAT2				= IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT			= IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__CSPI2_MISO				= IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__GPIO2_10				= IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__IPU_DIAGB_4				= IOMUX_PAD(0x6d4, 0x270, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0		= IOMUX_PAD(0x6d4, 0x270, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_RESET_B__ATA_RESET_B			= IOMUX_PAD(0x6d8, 0x274, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__ESDHC3_DAT3			= IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0		= IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O			= IOMUX_PAD(0x6d8, 0x274, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__CSPI2_RDY				= IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__GPIO2_11				= IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__IPU_DIAGB_5			= IOMUX_PAD(0x6d8, 0x274, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1		= IOMUX_PAD(0x6d8, 0x274, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_IORDY__ATA_IORDY				= IOMUX_PAD(0x6dc, 0x278, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__ESDHC3_DAT4				= IOMUX_PAD(0x6dc, 0x278, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1		= IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__ESDHC2_DAT4				= IOMUX_PAD(0x6dc, 0x278, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__GPIO2_12				= IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__IPU_DIAGB_6				= IOMUX_PAD(0x6dc, 0x278, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2		= IOMUX_PAD(0x6dc, 0x278, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA0__ATA_DATA_0				= IOMUX_PAD(0x6e0, 0x27c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__ESDHC3_DAT5				= IOMUX_PAD(0x6e0, 0x27c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2		= IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__ESDHC2_DAT5				= IOMUX_PAD(0x6e0, 0x27c, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__GPIO2_13				= IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__IPU_DIAGB_7				= IOMUX_PAD(0x6e0, 0x27c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3		= IOMUX_PAD(0x6e0, 0x27c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA1__ATA_DATA_1				= IOMUX_PAD(0x6e4, 0x280, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__ESDHC3_DAT6				= IOMUX_PAD(0x6e4, 0x280, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3		= IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK			= IOMUX_PAD(0x6e4, 0x280, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__ESDHC2_DAT6				= IOMUX_PAD(0x6e4, 0x280, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__GPIO2_14				= IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__IPU_DIAGB_8				= IOMUX_PAD(0x6e4, 0x280, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27			= IOMUX_PAD(0x6e4, 0x280, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA2__ATA_DATA_2				= IOMUX_PAD(0x6e8, 0x284, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__ESDHC3_DAT7				= IOMUX_PAD(0x6e8, 0x284, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4		= IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS			= IOMUX_PAD(0x6e8, 0x284, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__ESDHC2_DAT7				= IOMUX_PAD(0x6e8, 0x284, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__GPIO2_15				= IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__IPU_DIAGB_9				= IOMUX_PAD(0x6e8, 0x284, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28			= IOMUX_PAD(0x6e8, 0x284, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA3__ATA_DATA_3				= IOMUX_PAD(0x6ec, 0x288, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__ESDHC3_CLK				= IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5		= IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__CSPI2_SCLK				= IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__GPIO2_16				= IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__IPU_DIAGB_10			= IOMUX_PAD(0x6ec, 0x288, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29			= IOMUX_PAD(0x6ec, 0x288, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA4__ATA_DATA_4				= IOMUX_PAD(0x6f0, 0x28c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__ESDHC3_CMD				= IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6		= IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__GPIO2_17				= IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__IPU_DIAGB_11			= IOMUX_PAD(0x6f0, 0x28c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30			= IOMUX_PAD(0x6f0, 0x28c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA5__ATA_DATA_5				= IOMUX_PAD(0x6f4, 0x290, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7		= IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__GPIO2_18				= IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__IPU_DIAGB_12			= IOMUX_PAD(0x6f4, 0x290, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31			= IOMUX_PAD(0x6f4, 0x290, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA6__ATA_DATA_6				= IOMUX_PAD(0x6f8, 0x294, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__CAN1_TXCAN				= IOMUX_PAD(0x6f8, 0x294, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__UART1_DTR				= IOMUX_PAD(0x6f8, 0x294, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD			= IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__GPIO2_19				= IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__IPU_DIAGB_13			= IOMUX_PAD(0x6f8, 0x294, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA7__ATA_DATA_7				= IOMUX_PAD(0x6fc, 0x298, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__CAN1_RXCAN				= IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__UART1_DSR				= IOMUX_PAD(0x6fc, 0x298, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD			= IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__GPIO2_20				= IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__IPU_DIAGB_14			= IOMUX_PAD(0x6fc, 0x298, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA8__ATA_DATA_8				= IOMUX_PAD(0x700, 0x29c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__UART3_RTS				= IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__UART1_RI				= IOMUX_PAD(0x700, 0x29c, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC			= IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__GPIO2_21				= IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__IPU_DIAGB_15			= IOMUX_PAD(0x700, 0x29c, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA9__ATA_DATA_9				= IOMUX_PAD(0x704, 0x2a0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__UART3_CTS				= IOMUX_PAD(0x704, 0x2a0, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__UART1_DCD				= IOMUX_PAD(0x704, 0x2a0, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS			= IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__GPIO2_22				= IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__IPU_DIAGB_16			= IOMUX_PAD(0x704, 0x2a0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA10__ATA_DATA_10			= IOMUX_PAD(0x708, 0x2a4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__UART3_RXD_MUX			= IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC			= IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__GPIO2_23				= IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__IPU_DIAGB_17			= IOMUX_PAD(0x708, 0x2a4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA11__ATA_DATA_11			= IOMUX_PAD(0x70c, 0x2a8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__UART3_TXD_MUX			= IOMUX_PAD(0x70c, 0x2a8, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS			= IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__GPIO2_24				= IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__IPU_DIAGB_18			= IOMUX_PAD(0x70c, 0x2a8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA12__ATA_DATA_12			= IOMUX_PAD(0x710, 0x2ac, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA12__I2C3_SCL				= IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA12__GPIO2_25				= IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA12__IPU_DIAGB_19			= IOMUX_PAD(0x710, 0x2ac, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA13__ATA_DATA_13			= IOMUX_PAD(0x714, 0x2b0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA13__I2C3_SDA				= IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA13__GPIO2_26				= IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA13__IPU_DIAGB_20			= IOMUX_PAD(0x714, 0x2b0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA14__ATA_DATA_14			= IOMUX_PAD(0x718, 0x2b4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__IPU_CSI_D_0			= IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__KPP_ROW_0				= IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__GPIO2_27				= IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__IPU_DIAGB_21			= IOMUX_PAD(0x718, 0x2b4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA15__ATA_DATA_15			= IOMUX_PAD(0x71c, 0x2b8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__IPU_CSI_D_1			= IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__KPP_ROW_1				= IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__GPIO2_28				= IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__IPU_DIAGB_22			= IOMUX_PAD(0x71c, 0x2b8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_INTRQ__ATA_INTRQ				= IOMUX_PAD(0x720, 0x2bc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__IPU_CSI_D_2				= IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__KPP_ROW_2				= IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__GPIO2_29				= IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__IPU_DIAGB_23			= IOMUX_PAD(0x720, 0x2bc, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN			= IOMUX_PAD(0x724, 0x2c0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3			= IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__KPP_ROW_3				= IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__GPIO2_30				= IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24			= IOMUX_PAD(0x724, 0x2c0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DMARQ__ATA_DMARQ				= IOMUX_PAD(0x728, 0x2c4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__IPU_CSI_D_4				= IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__KPP_COL_0				= IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__GPIO2_31				= IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__IPU_DIAGB_25			= IOMUX_PAD(0x728, 0x2c4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4			= IOMUX_PAD(0x728, 0x2c4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DA0__ATA_DA_0				= IOMUX_PAD(0x72c, 0x2c8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__IPU_CSI_D_5				= IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__KPP_COL_1				= IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__GPIO3_0				= IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__IPU_DIAGB_26				= IOMUX_PAD(0x72c, 0x2c8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5			= IOMUX_PAD(0x72c, 0x2c8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DA1__ATA_DA_1				= IOMUX_PAD(0x730, 0x2cc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__IPU_CSI_D_6				= IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__KPP_COL_2				= IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__GPIO3_1				= IOMUX_PAD(0x730, 0x2cc, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__IPU_DIAGB_27				= IOMUX_PAD(0x730, 0x2cc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6			= IOMUX_PAD(0x730, 0x2cc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DA2__ATA_DA_2				= IOMUX_PAD(0x734, 0x2d0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__IPU_CSI_D_7				= IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__KPP_COL_3				= IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__GPIO3_2				= IOMUX_PAD(0x734, 0x2d0, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__IPU_DIAGB_28				= IOMUX_PAD(0x734, 0x2d0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7			= IOMUX_PAD(0x734, 0x2d0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_MLB_CLK__MLB_MLBCLK				= IOMUX_PAD(0x738, 0x2d4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_MLB_CLK__GPIO3_3				= IOMUX_PAD(0x738, 0x2d4, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_MLB_DAT__MLB_MLBDAT				= IOMUX_PAD(0x73c, 0x2d8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_MLB_DAT__GPIO3_4				= IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL),
+
+	MX35_PAD_MLB_SIG__MLB_MLBSIG				= IOMUX_PAD(0x740, 0x2dc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_MLB_SIG__GPIO3_5				= IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK				= IOMUX_PAD(0x744, 0x2e0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4			= IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX			= IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR			= IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__CSPI2_MOSI				= IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__GPIO3_6				= IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC		= IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0		= IOMUX_PAD(0x744, 0x2e0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK				= IOMUX_PAD(0x748, 0x2e4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5			= IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX			= IOMUX_PAD(0x748, 0x2e4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP			= IOMUX_PAD(0x748, 0x2e4, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__CSPI2_MISO				= IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__GPIO3_7				= IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I			= IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1		= IOMUX_PAD(0x748, 0x2e4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RX_DV__FEC_RX_DV				= IOMUX_PAD(0x74c, 0x2e8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__ESDHC1_DAT6				= IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__UART3_RTS				= IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT			= IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__CSPI2_SCLK				= IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__GPIO3_8				= IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK			= IOMUX_PAD(0x74c, 0x2e8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2		= IOMUX_PAD(0x74c, 0x2e8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_COL__FEC_COL				= IOMUX_PAD(0x750, 0x2ec, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__ESDHC1_DAT7				= IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__UART3_CTS				= IOMUX_PAD(0x750, 0x2ec, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0			= IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__CSPI2_RDY				= IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__GPIO3_9				= IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__IPU_DISPB_SER_RS			= IOMUX_PAD(0x750, 0x2ec, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3			= IOMUX_PAD(0x750, 0x2ec, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA0__FEC_RDATA_0			= IOMUX_PAD(0x754, 0x2f0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__PWM_PWMO				= IOMUX_PAD(0x754, 0x2f0, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__UART3_DTR				= IOMUX_PAD(0x754, 0x2f0, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1		= IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__CSPI2_SS0				= IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__GPIO3_10				= IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1			= IOMUX_PAD(0x754, 0x2f0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4		= IOMUX_PAD(0x754, 0x2f0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA0__FEC_TDATA_0			= IOMUX_PAD(0x758, 0x2f4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1			= IOMUX_PAD(0x758, 0x2f4, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__UART3_DSR				= IOMUX_PAD(0x758, 0x2f4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2		= IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__CSPI2_SS1				= IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__GPIO3_11				= IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0			= IOMUX_PAD(0x758, 0x2f4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5		= IOMUX_PAD(0x758, 0x2f4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TX_EN__FEC_TX_EN				= IOMUX_PAD(0x75c, 0x2f8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1			= IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__UART3_RI				= IOMUX_PAD(0x75c, 0x2f8, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3		= IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__GPIO3_12				= IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS			= IOMUX_PAD(0x75c, 0x2f8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6		= IOMUX_PAD(0x75c, 0x2f8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_MDC__FEC_MDC				= IOMUX_PAD(0x760, 0x2fc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__CAN2_TXCAN				= IOMUX_PAD(0x760, 0x2fc, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__UART3_DCD				= IOMUX_PAD(0x760, 0x2fc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4			= IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__GPIO3_13				= IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__IPU_DISPB_WR				= IOMUX_PAD(0x760, 0x2fc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7			= IOMUX_PAD(0x760, 0x2fc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_MDIO__FEC_MDIO				= IOMUX_PAD(0x764, 0x300, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__CAN2_RXCAN				= IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5			= IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__GPIO3_14				= IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__IPU_DISPB_RD				= IOMUX_PAD(0x764, 0x300, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8			= IOMUX_PAD(0x764, 0x300, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR				= IOMUX_PAD(0x768, 0x304, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__OWIRE_LINE				= IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6		= IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__GPIO3_15				= IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9		= IOMUX_PAD(0x768, 0x304, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR				= IOMUX_PAD(0x76c, 0x308, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0			= IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7		= IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__KPP_COL_4				= IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__GPIO3_16				= IOMUX_PAD(0x76c, 0x308, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_CRS__FEC_CRS				= IOMUX_PAD(0x770, 0x30c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__IPU_CSI_D_1				= IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR			= IOMUX_PAD(0x770, 0x30c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__KPP_COL_5				= IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__GPIO3_17				= IOMUX_PAD(0x770, 0x30c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__IPU_FLASH_STROBE			= IOMUX_PAD(0x770, 0x30c, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA1__FEC_RDATA_1			= IOMUX_PAD(0x774, 0x310, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__IPU_CSI_D_2			= IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC			= IOMUX_PAD(0x774, 0x310, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC			= IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__KPP_COL_6				= IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__GPIO3_18				= IOMUX_PAD(0x774, 0x310, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0			= IOMUX_PAD(0x774, 0x310, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA1__FEC_TDATA_1			= IOMUX_PAD(0x778, 0x314, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__IPU_CSI_D_3			= IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS			= IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__KPP_COL_7				= IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__GPIO3_19				= IOMUX_PAD(0x778, 0x314, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1			= IOMUX_PAD(0x778, 0x314, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA2__FEC_RDATA_2			= IOMUX_PAD(0x77c, 0x318, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__IPU_CSI_D_4			= IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD			= IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__KPP_ROW_4				= IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__GPIO3_20				= IOMUX_PAD(0x77c, 0x318, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA2__FEC_TDATA_2			= IOMUX_PAD(0x780, 0x31c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__IPU_CSI_D_5			= IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD			= IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__KPP_ROW_5				= IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__GPIO3_21				= IOMUX_PAD(0x780, 0x31c, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA3__FEC_RDATA_3			= IOMUX_PAD(0x784, 0x320, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__IPU_CSI_D_6			= IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC			= IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__KPP_ROW_6				= IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__GPIO3_22				= IOMUX_PAD(0x784, 0x320, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA3__FEC_TDATA_3			= IOMUX_PAD(0x788, 0x324, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__IPU_CSI_D_7			= IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS			= IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__KPP_ROW_7				= IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__GPIO3_23				= IOMUX_PAD(0x788, 0x324, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK			= IOMUX_PAD(0x78c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TEST_MODE__TCU_TEST_MODE			= IOMUX_PAD(0x790, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX35_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S
new file mode 100644
index 000000000..b55d2ef04
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/lowlevel_macro.S
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+#include <asm/macro.h>
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ *
+ * Default argument values:
+ *  - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
+ *    user-mode.
+ *  - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
+ *    SDMA to access them.
+ */
+.macro init_aips mpr=0x77777777, opacr=0x00000000
+	ldr	r0, =AIPS1_BASE_ADDR
+	ldr	r1, =\mpr
+	str	r1, [r0, #AIPS_MPR_0_7]
+	str	r1, [r0, #AIPS_MPR_8_15]
+	ldr	r2, =AIPS2_BASE_ADDR
+	str	r1, [r2, #AIPS_MPR_0_7]
+	str	r1, [r2, #AIPS_MPR_8_15]
+
+	/* Did not change the AIPS control registers access type. */
+	ldr	r1, =\opacr
+	str	r1, [r0, #AIPS_OPACR_0_7]
+	str	r1, [r0, #AIPS_OPACR_8_15]
+	str	r1, [r0, #AIPS_OPACR_16_23]
+	str	r1, [r0, #AIPS_OPACR_24_31]
+	str	r1, [r0, #AIPS_OPACR_32_39]
+	str	r1, [r2, #AIPS_OPACR_0_7]
+	str	r1, [r2, #AIPS_OPACR_8_15]
+	str	r1, [r2, #AIPS_OPACR_16_23]
+	str	r1, [r2, #AIPS_OPACR_24_31]
+	str	r1, [r2, #AIPS_OPACR_32_39]
+.endm
+
+/*
+ * MAX (Multi-Layer AHB Crossbar Switch) setup
+ *
+ * Default argument values:
+ *  - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
+ *  - SGPCR: always park on last master
+ *  - MGPCR: restore default values
+ */
+.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
+	ldr	r0, =MAX_BASE_ADDR
+	ldr	r1, =\mpr
+	str	r1, [r0, #MAX_MPR0]	/* for S0 */
+	str	r1, [r0, #MAX_MPR1]	/* for S1 */
+	str	r1, [r0, #MAX_MPR2]	/* for S2 */
+	str	r1, [r0, #MAX_MPR3]	/* for S3 */
+	str	r1, [r0, #MAX_MPR4]	/* for S4 */
+	ldr	r1, =\sgpcr
+	str	r1, [r0, #MAX_SGPCR0]	/* for S0 */
+	str	r1, [r0, #MAX_SGPCR1]	/* for S1 */
+	str	r1, [r0, #MAX_SGPCR2]	/* for S2 */
+	str	r1, [r0, #MAX_SGPCR3]	/* for S3 */
+	str	r1, [r0, #MAX_SGPCR4]	/* for S4 */
+	ldr	r1, =\mgpcr
+	str	r1, [r0, #MAX_MGPCR0]	/* for M0 */
+	str	r1, [r0, #MAX_MGPCR1]	/* for M1 */
+	str	r1, [r0, #MAX_MGPCR2]	/* for M2 */
+	str	r1, [r0, #MAX_MGPCR3]	/* for M3 */
+	str	r1, [r0, #MAX_MGPCR4]	/* for M4 */
+	str	r1, [r0, #MAX_MGPCR5]	/* for M5 */
+.endm
+
+/*
+ * M3IF setup
+ *
+ * Default argument values:
+ *  - CTL:
+ * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 1)	= 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 2)		= 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 3)		= 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 4)		= 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 5)	= 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6)		= 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 7)		= 0x00000000
+ *							------------
+ *							  0x00000040
+ */
+.macro init_m3if ctl=0x00000040
+	/* M3IF Control Register (M3IFCTL) */
+	write32	M3IF_BASE_ADDR, \ctl
+.endm
+
+.macro core_init
+	mrc	p15, 0, r1, c1, c0, 0
+
+	/* Set branch prediction enable */
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, r0, #7
+	mcr	p15, 0, r0, c1, c0, 1
+	orr	r1, r1, #1 << 11
+
+	/* Set unaligned access enable */
+	orr	r1, r1, #1 << 22
+
+	/* Set low int latency enable */
+	orr	r1, r1, #1 << 21
+
+	mcr	p15, 0, r1, c1, c0, 0
+
+	mov	r0, #0
+
+	mcr	p15, 0, r0, c15, c2, 4
+
+	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I cache and D cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate TLBs */
+	mcr	p15, 0, r0, c7, c10, 4	/* Drain the write buffer */
+
+	/* Setup the Peripheral Port Memory Remap Register */
+	ldr	r0, =0x40000015		/* Start from AIPS 2-GB region */
+	mcr	p15, 0, r0, c15, c2, 4
+.endm
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h
new file mode 100644
index 000000000..775b9552c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/mmc_host_def.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE		512
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/spl.h
new file mode 100644
index 000000000..d0efec21a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/spl.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONENAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+#define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_NOR		8
+#define BOOT_DEVICE_I2C		9
+#define BOOT_DEVICE_SPI		10
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h
new file mode 100644
index 000000000..35c03520a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx35/sys_proto.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_cpu_rev(void);
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+	u32 row, u32 col, u32 dsize, u32 refresh);
+#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h
new file mode 100644
index 000000000..3db4112d1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/clock.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+#ifdef CONFIG_SYS_MX5_HCLK
+#define MXC_HCLK	CONFIG_SYS_MX5_HCLK
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_SYS_MX5_CLK32
+#define MXC_CLK32	CONFIG_SYS_MX5_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_IPG_PERCLK,
+	MXC_UART_CLK,
+	MXC_CSPI_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_ESDHC4_CLK,
+	MXC_FEC_CLK,
+	MXC_SATA_CLK,
+	MXC_DDR_CLK,
+	MXC_NFC_CLK,
+	MXC_PERIPH_CLK,
+	MXC_I2C_CLK,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
+void set_usb_phy_clk(void);
+void enable_usb_phy1_clk(bool enable);
+void enable_usb_phy2_clk(bool enable);
+void set_usboh3_clk(void);
+void enable_usboh3_clk(bool enable);
+void mxc_set_sata_internal_clock(void);
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+void enable_nfc_clk(unsigned char enable);
+void enable_efuse_prog_supply(bool enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/crm_regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/crm_regs.h
new file mode 100644
index 000000000..efe57e07e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -0,0 +1,609 @@
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+#define MXC_CCM_BASE	CCM_BASE_ADDR
+
+/* DPLL register mapping structure */
+struct mxc_pll_reg {
+	u32 ctrl;
+	u32 config;
+	u32 op;
+	u32 mfd;
+	u32 mfn;
+	u32 mfn_minus;
+	u32 mfn_plus;
+	u32 hfs_op;
+	u32 hfs_mfd;
+	u32 hfs_mfn;
+	u32 mfn_togc;
+	u32 destat;
+};
+
+/* Register maping of CCM*/
+struct mxc_ccm_reg {
+	u32 ccr;	/* 0x0000 */
+	u32 ccdr;
+	u32 csr;
+	u32 ccsr;
+	u32 cacrr;	/* 0x0010*/
+	u32 cbcdr;
+	u32 cbcmr;
+	u32 cscmr1;
+	u32 cscmr2;	/* 0x0020 */
+	u32 cscdr1;
+	u32 cs1cdr;
+	u32 cs2cdr;
+	u32 cdcdr;	/* 0x0030 */
+	u32 chscdr;
+	u32 cscdr2;
+	u32 cscdr3;
+	u32 cscdr4;	/* 0x0040 */
+	u32 cwdr;
+	u32 cdhipr;
+	u32 cdcr;
+	u32 ctor;	/* 0x0050 */
+	u32 clpcr;
+	u32 cisr;
+	u32 cimr;
+	u32 ccosr;	/* 0x0060 */
+	u32 cgpr;
+	u32 CCGR0;
+	u32 CCGR1;
+	u32 CCGR2;	/* 0x0070 */
+	u32 CCGR3;
+	u32 CCGR4;
+	u32 CCGR5;
+	u32 CCGR6;	/* 0x0080 */
+#ifdef CONFIG_MX53
+	u32 CCGR7;      /* 0x0084 */
+#endif
+	u32 cmeor;
+};
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN			(0x1 << 12)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_MULT			(0x1 << 11)
+#endif
+#define MXC_CCM_CCR_CAMP2_EN			(0x1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN			(0x1 << 9)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_EN			(0x1 << 8)
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET		0
+#define MXC_CCM_CCR_OSCNT_MASK			0xFF
+#define MXC_CCM_CCR_OSCNT(v)			((v) & 0xFF)
+#define MXC_CCM_CCR_OSCNT_RD(r)			((r) & 0xFF)
+
+/* Define the bits in register CCSR */
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCSR_LP_APM			(0x1 << 9)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCSR_LP_APM			(0x1 << 10)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL		(0x1 << 9)
+#endif
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET		7
+#define MXC_CCM_CCSR_STEP_SEL_MASK		(0x3 << 7)
+#define MXC_CCM_CCSR_STEP_SEL(v)		(((v) & 0x3) << 7)
+#define MXC_CCM_CCSR_STEP_SEL_RD(r)		(((r) >> 7) & 0x3)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET	5
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK		(0x3 << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF(v)		(((v) & 0x3) << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r)	(((r) >> 5) & 0x3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET	3
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK		(0x3 << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF(v)		(((v) & 0x3) << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r)	(((r) >> 3) & 0x3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL		(0x1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL		0x1
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
+#define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
+#define MXC_CCM_CACRR_ARM_PODF(v)		((v) & 0x7)
+#define MXC_CCM_CACRR_ARM_PODF_RD(r)		((r) & 0x7)
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL		(0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_PODF_OFFSET		27
+#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF(v)		(((v) & 0x7) << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_RD(r)		(((r) >> 27) & 0x7)
+#define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
+#define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
+#define MXC_CCM_CBCDR_EMI_PODF(v)		(((v) & 0x7) << 22)
+#define MXC_CCM_CBCDR_EMI_PODF_RD(r)		(((r) >> 22) & 0x7)
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		19
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF(v)		(((v) & 0x7) << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r)		(((r) >> 19) & 0x7)
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		16
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF(v)		(((v) & 0x7) << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r)		(((r) >> 16) & 0x7)
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET		13
+#define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
+#define MXC_CCM_CBCDR_NFC_PODF(v)		(((v) & 0x7) << 13)
+#define MXC_CCM_CBCDR_NFC_PODF_RD(r)		(((r) >> 13) & 0x7)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET		10
+#define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF(v)		(((v) & 0x7) << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_RD(r)		(((r) >> 10) & 0x7)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET		8
+#define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_RD(r)		(((r) >> 8) & 0x3)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	6
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r)	(((r) >> 6) & 0x3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	3
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2(v)		(((v) & 0x7) << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r)	(((r) >> 3) & 0x7)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	0
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK		0x7
+#define MXC_CCM_CBCDR_PERCLK_PODF(v)		((v) & 0x7)
+#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r)		((r) & 0x7)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		30
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v)		(((v) & 0x3) << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r)		(((r) >> 30) & 0x3)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		28
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v)		(((v) & 0x3) << 28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r)		(((r) >> 28) & 0x3)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		24
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r)		(((r) >> 24) & 0x3)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		22
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v)		(((v) & 0x3) << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r)		(((r) >> 22) & 0x3)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	20
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v)		(((v) & 0x3) << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r)	(((r) >> 20) & 0x3)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	16
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v)		(((v) & 0x3) << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r)	(((r) >> 16) & 0x3)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		14
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		8
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		4
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r)		(((r) >> 4) & 0x3)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		2
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r)		(((r) >> 2) & 0x3)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v)			(((v) & 0x7) << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r)		(((r) >> 25) & 0x7)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		19
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v)			(((v) & 0x3F) << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r)		(((r) >> 19) & 0x3F)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		16
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v)			(((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r)		(((r) >> 16) & 0x7)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		9
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v)			(((v) & 0x3F) << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r)		(((r) >> 9) & 0x3F)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		6
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v)		(((v) & 0x7) << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r)		(((r) >> 6) & 0x7)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET		0
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v)		((v) & 0x3F)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r)		((r) & 0x3F)
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v)		(((v) & 0x3) << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		12
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		10
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK			(0x3 << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r)			(((r) >> 10) & 0x3)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET		8
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET		6
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r)		(((r) >> 6) & 0x3)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		4
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK			(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r)			(((r) >> 4) & 0x3)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	22
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v)		(((v) & 0x7) << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r)	(((r) >> 22) & 0x7)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	19
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v)		(((v) & 0x7) << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r)	(((r) >> 19) & 0x7)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	16
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v)		(((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r)	(((r) >> 16) & 0x7)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		14
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r)		(((r) >> 14) & 0x3)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	11
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v)		(((v) & 0x7) << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r)	(((r) >> 11) & 0x7)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v)		(((v) & 0x7) << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r)		(((r) >> 8) & 0x7)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r)		(((r) >> 6) & 0x3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		3
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED(v)			(((v) & 0x7) << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r)		(((r) >> 3) & 0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
+#define MXC_CCM_CSCDR1_UART_CLK_PODF(v)			((v) & 0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r)		((r) & 0x7)
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)
+
+/* Define the bits in register CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(1 << 4)
+
+/* Define the bits in register CCGRx */
+#define MXC_CCM_CCGR_CG_MASK				0x3
+#define MXC_CCM_CCGR_CG_OFF				0x0
+#define MXC_CCM_CCGR_CG_RUN_ON				0x1
+#define MXC_CCM_CCGR_CG_ON				0x3
+
+#define MXC_CCM_CCGR0_ARM_BUS_OFFSET			0
+#define MXC_CCM_CCGR0_ARM_BUS(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR0_ARM_AXI_OFFSET			2
+#define MXC_CCM_CCGR0_ARM_AXI(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET			4
+#define MXC_CCM_CCGR0_ARM_DEBUG(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR0_TZIC_OFFSET			6
+#define MXC_CCM_CCGR0_TZIC(v)				(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR0_DAP_OFFSET			8
+#define MXC_CCM_CCGR0_DAP(v)				(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR0_TPIU_OFFSET			10
+#define MXC_CCM_CCGR0_TPIU(v)				(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR0_CTI2_OFFSET			12
+#define MXC_CCM_CCGR0_CTI2(v)				(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR0_CTI3_OFFSET			14
+#define MXC_CCM_CCGR0_CTI3(v)				(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR0_AHBMUX1_OFFSET			16
+#define MXC_CCM_CCGR0_AHBMUX1(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR0_AHBMUX2_OFFSET			18
+#define MXC_CCM_CCGR0_AHBMUX2(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR0_ROMCP_OFFSET			20
+#define MXC_CCM_CCGR0_ROMCP(v)				(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR0_ROM_OFFSET			22
+#define MXC_CCM_CCGR0_ROM(v)				(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			24
+#define MXC_CCM_CCGR0_AIPS_TZ1(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			26
+#define MXC_CCM_CCGR0_AIPS_TZ2(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR0_AHB_MAX_OFFSET			28
+#define MXC_CCM_CCGR0_AHB_MAX(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR0_IIM_OFFSET			30
+#define MXC_CCM_CCGR0_IIM(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR1_TMAX1_OFFSET			0
+#define MXC_CCM_CCGR1_TMAX1(v)				(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR1_TMAX2_OFFSET			2
+#define MXC_CCM_CCGR1_TMAX2(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR1_TMAX3_OFFSET			4
+#define MXC_CCM_CCGR1_TMAX3(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR1_UART1_IPG_OFFSET			6
+#define MXC_CCM_CCGR1_UART1_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR1_UART1_PER_OFFSET			8
+#define MXC_CCM_CCGR1_UART1_PER(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR1_UART2_IPG_OFFSET			10
+#define MXC_CCM_CCGR1_UART2_IPG(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR1_UART2_PER_OFFSET			12
+#define MXC_CCM_CCGR1_UART2_PER(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR1_UART3_IPG_OFFSET			14
+#define MXC_CCM_CCGR1_UART3_IPG(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR1_UART3_PER_OFFSET			16
+#define MXC_CCM_CCGR1_UART3_PER(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR1_I2C1_OFFSET			18
+#define MXC_CCM_CCGR1_I2C1(v)				(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR1_I2C2_OFFSET			20
+#define MXC_CCM_CCGR1_I2C2(v)				(((v) & 0x3) << 20)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET			22
+#define MXC_CCM_CCGR1_HSI2C_IPG(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET		24
+#define MXC_CCM_CCGR1_HSI2C_SERIAL(v)			(((v) & 0x3) << 24)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR1_I2C3_OFFSET			22
+#define MXC_CCM_CCGR1_I2C3(v)				(((v) & 0x3) << 22)
+#endif
+#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET			26
+#define MXC_CCM_CCGR1_FIRI_IPG(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET		28
+#define MXC_CCM_CCGR1_FIRI_SERIAL(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR1_SCC_OFFSET			30
+#define MXC_CCM_CCGR1_SCC(v)				(((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR2_USB_PHY_OFFSET			0
+#define MXC_CCM_CCGR2_USB_PHY(v)			(((v) & 0x3) << 0)
+#endif
+#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET			2
+#define MXC_CCM_CCGR2_EPIT1_IPG(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET			4
+#define MXC_CCM_CCGR2_EPIT1_HF(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET			6
+#define MXC_CCM_CCGR2_EPIT2_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET			8
+#define MXC_CCM_CCGR2_EPIT2_HF(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET			10
+#define MXC_CCM_CCGR2_PWM1_IPG(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR2_PWM1_HF_OFFSET			12
+#define MXC_CCM_CCGR2_PWM1_HF(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET			14
+#define MXC_CCM_CCGR2_PWM2_IPG(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR2_PWM2_HF_OFFSET			16
+#define MXC_CCM_CCGR2_PWM2_HF(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR2_GPT_IPG_OFFSET			18
+#define MXC_CCM_CCGR2_GPT_IPG(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR2_GPT_HF_OFFSET			20
+#define MXC_CCM_CCGR2_GPT_HF(v)				(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR2_OWIRE_OFFSET			22
+#define MXC_CCM_CCGR2_OWIRE(v)				(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR2_FEC_OFFSET			24
+#define MXC_CCM_CCGR2_FEC(v)				(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET		26
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET			28
+#define MXC_CCM_CCGR2_USBOH3_60M(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR2_TVE_OFFSET			30
+#define MXC_CCM_CCGR2_TVE(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET			0
+#define MXC_CCM_CCGR3_ESDHC1_IPG(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET			2
+#define MXC_CCM_CCGR3_ESDHC1_PER(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET			4
+#define MXC_CCM_CCGR3_ESDHC2_IPG(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET			6
+#define MXC_CCM_CCGR3_ESDHC2_PER(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET			8
+#define MXC_CCM_CCGR3_ESDHC3_IPG(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET			10
+#define MXC_CCM_CCGR3_ESDHC3_PER(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET			12
+#define MXC_CCM_CCGR3_ESDHC4_IPG(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET			14
+#define MXC_CCM_CCGR3_ESDHC4_PER(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET			16
+#define MXC_CCM_CCGR3_SSI1_IPG(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET			18
+#define MXC_CCM_CCGR3_SSI1_SSI(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET			20
+#define MXC_CCM_CCGR3_SSI2_IPG(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET			22
+#define MXC_CCM_CCGR3_SSI2_SSI(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET			24
+#define MXC_CCM_CCGR3_SSI3_IPG(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET			26
+#define MXC_CCM_CCGR3_SSI3_SSI(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET			28
+#define MXC_CCM_CCGR3_SSI_EXT1(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET			30
+#define MXC_CCM_CCGR3_SSI_EXT2(v)			(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR4_PATA_OFFSET			0
+#define MXC_CCM_CCGR4_PATA(v)				(((v) & 0x3) << 0)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR4_SIM_IPG_OFFSET			2
+#define MXC_CCM_CCGR4_SIM_IPG(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET			4
+#define MXC_CCM_CCGR4_SIM_SERIAL(v)			(((v) & 0x3) << 4)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR4_SATA_OFFSET			2
+#define MXC_CCM_CCGR4_SATA(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET			6
+#define MXC_CCM_CCGR4_CAN2_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR4_CAN2_SERIAL(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR4_USB_PHY1_OFFSET			10
+#define MXC_CCM_CCGR4_USB_PHY1(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR4_USB_PHY2_OFFSET			12
+#define MXC_CCM_CCGR4_USB_PHY2(v)			(((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR4_SAHARA_OFFSET			14
+#define MXC_CCM_CCGR4_SAHARA(v)				(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR4_RTIC_OFFSET			16
+#define MXC_CCM_CCGR4_RTIC(v)				(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET			18
+#define MXC_CCM_CCGR4_ECSPI1_IPG(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET			20
+#define MXC_CCM_CCGR4_ECSPI1_PER(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET			22
+#define MXC_CCM_CCGR4_ECSPI2_IPG(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET			24
+#define MXC_CCM_CCGR4_ECSPI2_PER(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET			26
+#define MXC_CCM_CCGR4_CSPI_IPG(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR4_SRTC_OFFSET			28
+#define MXC_CCM_CCGR4_SRTC(v)				(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR4_SDMA_OFFSET			30
+#define MXC_CCM_CCGR4_SDMA(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR5_SPBA_OFFSET			0
+#define MXC_CCM_CCGR5_SPBA(v)				(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR5_GPU_OFFSET			2
+#define MXC_CCM_CCGR5_GPU(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR5_GARB_OFFSET			4
+#define MXC_CCM_CCGR5_GARB(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR5_VPU_OFFSET			6
+#define MXC_CCM_CCGR5_VPU(v)				(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR5_VPU_REF_OFFSET			8
+#define MXC_CCM_CCGR5_VPU_REF(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR5_IPU_OFFSET			10
+#define MXC_CCM_CCGR5_IPU(v)				(((v) & 0x3) << 10)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_IPUMUX12_OFFSET			12
+#define MXC_CCM_CCGR5_IPUMUX12(v)			(((v) & 0x3) << 12)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR5_IPUMUX1_OFFSET			12
+#define MXC_CCM_CCGR5_IPUMUX1(v)			(((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR5_EMI_FAST_OFFSET			14
+#define MXC_CCM_CCGR5_EMI_FAST(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET			16
+#define MXC_CCM_CCGR5_EMI_SLOW(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR5_EMI_INT1_OFFSET			18
+#define MXC_CCM_CCGR5_EMI_INT1(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET			20
+#define MXC_CCM_CCGR5_EMI_ENFC(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET			22
+#define MXC_CCM_CCGR5_EMI_WRCK(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR5_GPC_IPG_OFFSET			24
+#define MXC_CCM_CCGR5_GPC_IPG(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR5_SPDIF0_OFFSET			26
+#define MXC_CCM_CCGR5_SPDIF0(v)				(((v) & 0x3) << 26)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_SPDIF1_OFFSET			28
+#define MXC_CCM_CCGR5_SPDIF1(v)				(((v) & 0x3) << 28)
+#endif
+#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET			30
+#define MXC_CCM_CCGR5_SPDIF_IPG(v)			(((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_IPUMUX2_OFFSET			0
+#define MXC_CCM_CCGR6_IPUMUX2(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR6_OCRAM_OFFSET			2
+#define MXC_CCM_CCGR6_OCRAM(v)				(((v) & 0x3) << 2)
+#endif
+#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET			4
+#define MXC_CCM_CCGR6_CSI_MCLK1(v)			(((v) & 0x3) << 4)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET			6
+#define MXC_CCM_CCGR6_CSI_MCLK2(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR6_EMI_GARB_OFFSET			8
+#define MXC_CCM_CCGR6_EMI_GARB(v)			(((v) & 0x3) << 8)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_EMI_INT2_OFFSET			8
+#define MXC_CCM_CCGR6_EMI_INT2(v)			(((v) & 0x3) << 8)
+#endif
+#define MXC_CCM_CCGR6_IPU_DI0_OFFSET			10
+#define MXC_CCM_CCGR6_IPU_DI0(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR6_IPU_DI1_OFFSET			12
+#define MXC_CCM_CCGR6_IPU_DI1(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR6_GPU2D_OFFSET			14
+#define MXC_CCM_CCGR6_GPU2D(v)				(((v) & 0x3) << 14)
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET			16
+#define MXC_CCM_CCGR6_ESAI_IPG(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET			18
+#define MXC_CCM_CCGR6_ESAI_ROOT(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET			20
+#define MXC_CCM_CCGR6_CAN1_IPG(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET		22
+#define MXC_CCM_CCGR6_CAN1_SERIAL(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR6_PL301_4X1_OFFSET			24
+#define MXC_CCM_CCGR6_PL301_4X1(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR6_PL301_2X2_OFFSET			26
+#define MXC_CCM_CCGR6_PL301_2X2(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR6_LDB_DI0_OFFSET			28
+#define MXC_CCM_CCGR6_LDB_DI0(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR6_LDB_DI1_OFFSET			30
+#define MXC_CCM_CCGR6_LDB_DI1(v)			(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET			0
+#define MXC_CCM_CCGR7_ASRC_IPG(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET			2
+#define MXC_CCM_CCGR7_ASRC_ASRCK(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR7_MLB_OFFSET			4
+#define MXC_CCM_CCGR7_MLB(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR7_IEEE1588_OFFSET			6
+#define MXC_CCM_CCGR7_IEEE1588(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR7_UART4_IPG_OFFSET			8
+#define MXC_CCM_CCGR7_UART4_IPG(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR7_UART4_PER_OFFSET			10
+#define MXC_CCM_CCGR7_UART4_PER(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR7_UART5_IPG_OFFSET			12
+#define MXC_CCM_CCGR7_UART5_IPG(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR7_UART5_PER_OFFSET			14
+#define MXC_CCM_CCGR7_UART5_PER(v)			(((v) & 0x3) << 14)
+#endif
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)
+
+#define	MXC_DPLLC_CTL_HFSM				(1 << 7)
+#define	MXC_DPLLC_CTL_DPDCK0_2_EN			(1 << 12)
+
+#define	MXC_DPLLC_OP_PDF_MASK				0xf
+#define	MXC_DPLLC_OP_MFI_OFFSET				4
+#define	MXC_DPLLC_OP_MFI_MASK				(0xf << 4)
+#define	MXC_DPLLC_OP_MFI(v)				(((v) & 0xf) << 4)
+#define	MXC_DPLLC_OP_MFI_RD(r)				(((r) >> 4) & 0xf)
+
+#define	MXC_DPLLC_MFD_MFD_MASK				0x7ffffff
+
+#define	MXC_DPLLC_MFN_MFN_MASK				0x7ffffff
+
+#endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h
new file mode 100644
index 000000000..e2a5bc97a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/gpio.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __ASM_ARCH_MX5_GPIO_H
+#define __ASM_ARCH_MX5_GPIO_H
+
+#include <asm/imx-common/gpio.h>
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h
new file mode 100644
index 000000000..054c680a5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -0,0 +1,532 @@
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
+#define __ASM_ARCH_MX5_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#if defined(CONFIG_MX51)
+#define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
+#define IPU_SOC_BASE_ADDR	0x40000000
+#define IPU_SOC_OFFSET		0x1E000000
+#define SPBA0_BASE_ADDR         0x70000000
+#define AIPS1_BASE_ADDR         0x73F00000
+#define AIPS2_BASE_ADDR         0x83F00000
+#define CSD0_BASE_ADDR          0x90000000
+#define CSD1_BASE_ADDR          0xA0000000
+#define NFC_BASE_ADDR_AXI       0xCFFF0000
+#define CS1_BASE_ADDR           0xB8000000
+#elif defined(CONFIG_MX53)
+#define IPU_SOC_BASE_ADDR	0x18000000
+#define IPU_SOC_OFFSET		0x06000000
+#define SPBA0_BASE_ADDR         0x50000000
+#define AIPS1_BASE_ADDR         0x53F00000
+#define AIPS2_BASE_ADDR         0x63F00000
+#define CSD0_BASE_ADDR          0x70000000
+#define CSD1_BASE_ADDR          0xB0000000
+#define NFC_BASE_ADDR_AXI       0xF7FF0000
+#define IRAM_BASE_ADDR          0xF8000000
+#define CS1_BASE_ADDR           0xF4000000
+#define SATA_BASE_ADDR		0x10000000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
+#define IRAM_SIZE		0x00020000	/* 128 KB */
+
+/*
+ * SPBA global module enabled #0
+ */
+#define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE		(SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
+#define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
+#define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
+#define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
+#define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
+#define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
+#define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
+#define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 1
+ */
+#define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
+#define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
+#define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
+#define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
+#define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
+#define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
+#define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
+#define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
+#define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
+#define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
+#define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
+#define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
+#define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
+#define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
+#define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
+#define UART1_BASE		(AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE		(AIPS1_BASE_ADDR + 0x000C0000)
+#define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
+#define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
+#define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
+
+#if defined(CONFIG_MX53)
+#define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
+#define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
+#define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
+#define I2C3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000EC000)
+#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000F0000)
+#endif
+/*
+ * AIPS 2
+ */
+#define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
+#define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
+#define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
+#ifdef	CONFIG_MX53
+#define PLL4_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0008c000)
+#endif
+#define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
+#define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
+#define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
+#define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
+#define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
+#define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
+#define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
+#define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
+#define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
+#define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
+#define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
+#define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
+#define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
+#define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
+#define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
+#define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
+#define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
+#define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
+#define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
+#define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
+#define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
+#define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
+#define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
+#define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
+#define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
+#define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
+#define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
+#define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
+#define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
+
+#if defined(CONFIG_MX53)
+#define UART5_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00090000)
+#endif
+
+/*
+ * WEIM CSnGCR1
+ */
+#define CSEN		1
+#define SWR		(1 << 1)
+#define SRD		(1 << 2)
+#define MUM		(1 << 3)
+#define WFL		(1 << 4)
+#define RFL		(1 << 5)
+#define CRE		(1 << 6)
+#define CREP		(1 << 7)
+#define BL(x)		(((x) & 0x7) << 8)
+#define WC		(1 << 11)
+#define BCD(x)		(((x) & 0x3) << 12)
+#define BCS(x)		(((x) & 0x3) << 14)
+#define DSZ(x)		(((x) & 0x7) << 16)
+#define SP		(1 << 19)
+#define CSREC(x)	(((x) & 0x7) << 20)
+#define AUS		(1 << 23)
+#define GBC(x)		(((x) & 0x7) << 24)
+#define WP		(1 << 27)
+#define PSZ(x)		(((x) & 0x0f << 28)
+
+/*
+ * WEIM CSnGCR2
+ */
+#define ADH(x)		(((x) & 0x3))
+#define DAPS(x)		(((x) & 0x0f << 4)
+#define DAE		(1 << 8)
+#define DAP		(1 << 9)
+#define MUX16_BYP	(1 << 12)
+
+/*
+ * WEIM CSnRCR1
+ */
+#define RCSN(x)		(((x) & 0x7))
+#define RCSA(x)		(((x) & 0x7) << 4)
+#define OEN(x)		(((x) & 0x7) << 8)
+#define OEA(x)		(((x) & 0x7) << 12)
+#define RADVN(x)	(((x) & 0x7) << 16)
+#define RAL		(1 << 19)
+#define RADVA(x)	(((x) & 0x7) << 20)
+#define RWSC(x)		(((x) & 0x3f) << 24)
+
+/*
+ * WEIM CSnRCR2
+ */
+#define RBEN(x)		(((x) & 0x7))
+#define RBE		(1 << 3)
+#define RBEA(x)		(((x) & 0x7) << 4)
+#define RL(x)		(((x) & 0x3) << 8)
+#define PAT(x)		(((x) & 0x7) << 12)
+#define APR		(1 << 15)
+
+/*
+ * WEIM CSnWCR1
+ */
+#define WCSN(x)		(((x) & 0x7))
+#define WCSA(x)		(((x) & 0x7) << 3)
+#define WEN(x)		(((x) & 0x7) << 6)
+#define WEA(x)		(((x) & 0x7) << 9)
+#define WBEN(x)		(((x) & 0x7) << 12)
+#define WBEA(x)		(((x) & 0x7) << 15)
+#define WADVN(x)	(((x) & 0x7) << 18)
+#define WADVA(x)	(((x) & 0x7) << 21)
+#define WWSC(x)		(((x) & 0x3f) << 24)
+#define WBED1		(1 << 30)
+#define WAL		(1 << 31)
+
+/*
+ * WEIM CSnWCR2
+ */
+#define WBED		1
+
+#define CS0_128					0
+#define CS0_64M_CS1_64M				1
+#define CS0_64M_CS1_32M_CS2_32M			2
+#define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_MODE_MASK	(0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN	18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
+#define MXC_SPI_BASE_ADDRESSES \
+	CSPI1_BASE_ADDR, \
+	CSPI2_BASE_ADDR, \
+	CSPI3_BASE_ADDR,
+
+/*
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN            32
+
+#define IIM_SREV	0x24
+#define ROM_SI_REV	0x48
+
+#define NFC_BUF_SIZE	0x1000
+
+/* M4IF */
+#define M4IF_FBPM0	0x40
+#define M4IF_FIDBP	0x48
+#define M4IF_GENP_WEIM_MM_MASK		0x00000001
+#define WEIM_GCR2_MUX16_BYP_GRANT_MASK	0x00001000
+
+/* Assuming 24MHz input clock with doubler ON */
+/*                            MFI         PDF */
+#define DP_OP_864	((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_864	(180 - 1) /* PL Dither mode */
+#define DP_MFN_864	180
+#define DP_MFN_800_DIT	60 /* PL Dither mode */
+
+#define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_850	(48 - 1)
+#define DP_MFN_850	41
+
+#define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_800	(3 - 1)
+#define DP_MFN_800	1
+
+#define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_700	(24 - 1)
+#define DP_MFN_700	7
+
+#define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_665	(96 - 1)
+#define DP_MFN_665	89
+
+#define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_532	(24 - 1)
+#define DP_MFN_532	13
+
+#define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_400	(3 - 1)
+#define DP_MFN_400	1
+
+#define DP_OP_455	((9 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_455	(48 - 1)
+#define DP_MFN_455	23
+
+#define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
+#define DP_MFD_216	(4 - 1)
+#define DP_MFN_216	3
+
+#define CHIP_REV_1_0            0x10
+#define CHIP_REV_1_1            0x11
+#define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_5		0x25
+#define CHIP_REV_3_0            0x30
+
+#define BOARD_REV_1_0           0x0
+#define BOARD_REV_2_0           0x1
+
+#define BOARD_VER_OFFSET	0x8
+
+#define IMX_IIM_BASE            (IIM_BASE_ADDR)
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+#define __REG(x)	(*((volatile u32 *)(x)))
+#define __REG16(x)	(*((volatile u16 *)(x)))
+#define __REG8(x)	(*((volatile u8 *)(x)))
+
+struct clkctl {
+	u32	ccr;
+	u32	ccdr;
+	u32	csr;
+	u32	ccsr;
+	u32	cacrr;
+	u32	cbcdr;
+	u32	cbcmr;
+	u32	cscmr1;
+	u32	cscmr2;
+	u32	cscdr1;
+	u32	cs1cdr;
+	u32	cs2cdr;
+	u32	cdcdr;
+	u32	chsccdr;
+	u32	cscdr2;
+	u32	cscdr3;
+	u32	cscdr4;
+	u32	cwdr;
+	u32	cdhipr;
+	u32	cdcr;
+	u32	ctor;
+	u32	clpcr;
+	u32	cisr;
+	u32	cimr;
+	u32	ccosr;
+	u32	cgpr;
+	u32	ccgr0;
+	u32	ccgr1;
+	u32	ccgr2;
+	u32	ccgr3;
+	u32	ccgr4;
+	u32	ccgr5;
+	u32	ccgr6;
+#if defined(CONFIG_MX53)
+	u32	ccgr7;
+#endif
+	u32	cmeor;
+};
+
+/* DPLL registers */
+struct dpll {
+	u32	dp_ctl;
+	u32	dp_config;
+	u32	dp_op;
+	u32	dp_mfd;
+	u32	dp_mfn;
+	u32	dp_mfn_minus;
+	u32	dp_mfn_plus;
+	u32	dp_hfs_op;
+	u32	dp_hfs_mfd;
+	u32	dp_hfs_mfn;
+	u32	dp_mfn_togc;
+	u32	dp_destat;
+};
+/* WEIM registers */
+struct weim {
+	u32	cs0gcr1;
+	u32	cs0gcr2;
+	u32	cs0rcr1;
+	u32	cs0rcr2;
+	u32	cs0wcr1;
+	u32	cs0wcr2;
+	u32	cs1gcr1;
+	u32	cs1gcr2;
+	u32	cs1rcr1;
+	u32	cs1rcr2;
+	u32	cs1wcr1;
+	u32	cs1wcr2;
+	u32	cs2gcr1;
+	u32	cs2gcr2;
+	u32	cs2rcr1;
+	u32	cs2rcr2;
+	u32	cs2wcr1;
+	u32	cs2wcr2;
+	u32	cs3gcr1;
+	u32	cs3gcr2;
+	u32	cs3rcr1;
+	u32	cs3rcr2;
+	u32	cs3wcr1;
+	u32	cs3wcr2;
+	u32	cs4gcr1;
+	u32	cs4gcr2;
+	u32	cs4rcr1;
+	u32	cs4rcr2;
+	u32	cs4wcr1;
+	u32	cs4wcr2;
+	u32	cs5gcr1;
+	u32	cs5gcr2;
+	u32	cs5rcr1;
+	u32	cs5rcr2;
+	u32	cs5wcr1;
+	u32	cs5wcr2;
+	u32	wcr;
+	u32	wiar;
+	u32	ear;
+};
+
+#if defined(CONFIG_MX51)
+struct iomuxc {
+	u32	gpr0;
+	u32	gpr1;
+	u32	omux0;
+	u32	omux1;
+	u32	omux2;
+	u32	omux3;
+	u32	omux4;
+};
+#elif defined(CONFIG_MX53)
+struct iomuxc {
+	u32	gpr0;
+	u32	gpr1;
+	u32	gpr2;
+	u32	omux0;
+	u32	omux1;
+	u32	omux2;
+	u32	omux3;
+	u32	omux4;
+};
+#endif
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32	scr;
+	u32	sbmr;
+	u32	srsr;
+	u32	reserved1[2];
+	u32	sisr;
+	u32	simr;
+};
+
+struct srtc_regs {
+	u32	lpscmr;		/* 0x00 */
+	u32	lpsclr;		/* 0x04 */
+	u32	lpsar;		/* 0x08 */
+	u32	lpsmcr;		/* 0x0c */
+	u32	lpcr;		/* 0x10 */
+	u32	lpsr;		/* 0x14 */
+	u32	lppdr;		/* 0x18 */
+	u32	lpgr;		/* 0x1c */
+	u32	hpcmr;		/* 0x20 */
+	u32	hpclr;		/* 0x24 */
+	u32	hpamr;		/* 0x28 */
+	u32	hpalr;		/* 0x2c */
+	u32	hpcr;		/* 0x30 */
+	u32	hpisr;		/* 0x34 */
+	u32	hpienr;		/* 0x38 */
+};
+
+/* CSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 cfg;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+};
+
+struct iim_regs {
+	u32	stat;
+	u32	statm;
+	u32     err;
+	u32	emask;
+	u32	fctl;
+	u32	ua;
+	u32	la;
+	u32	sdat;
+	u32	prev;
+	u32	srev;
+	u32	prg_p;
+	u32	scs0;
+	u32	scs1;
+	u32	scs2;
+	u32	scs3;
+	u32	res0[0x1f1];
+	struct fuse_bank {
+		u32	fuse_regs[0x20];
+		u32	fuse_rsvd[0xe0];
+#if defined(CONFIG_MX51)
+	} bank[4];
+#elif defined(CONFIG_MX53)
+	} bank[5];
+#endif
+};
+
+struct fuse_bank0_regs {
+	u32	fuse0_7[8];
+	u32	uid[8];
+	u32	fuse16_23[8];
+#if defined(CONFIG_MX51)
+	u32	imei[8];
+#elif defined(CONFIG_MX53)
+	u32	gp[8];
+#endif
+};
+
+struct fuse_bank1_regs {
+	u32	fuse0_8[9];
+	u32	mac_addr[6];
+	u32	fuse15_31[0x11];
+};
+
+#if defined(CONFIG_MX53)
+struct fuse_bank4_regs {
+	u32	fuse0_4[5];
+	u32	gp[3];
+	u32	fuse8_31[0x18];
+};
+#endif
+
+#endif /* __ASSEMBLER__*/
+
+#endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx51.h
new file mode 100644
index 000000000..70aaa37f9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx51.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The vast majority of this file is taken from the Linux kernel at
+ * commit 5d23b39
+ */
+
+#ifndef __IOMUX_MX51_H__
+#define __IOMUX_MX51_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX51_UART_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
+				PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+#define MX51_I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+				PAD_CTL_HYS)
+#define MX51_ESDHC_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+				PAD_CTL_HYS)
+#define MX51_USBH_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+				PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
+#define MX51_ECSPI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_HYS | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+#define MX51_SDHCI_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
+				PAD_CTL_SRE_FAST | PAD_CTL_DVS)
+#define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
+
+#define MX51_PAD_CTRL_2		(PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_4		(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5		(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
+/*
+ * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*							    PAD    MUX   ALT INPSE PATH PADCTRL */
+enum {
+	MX51_PAD_EIM_D16__USBH2_DATA0		= IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D17__GPIO2_1		= IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_D17__USBH2_DATA1		= IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D18__USBH2_DATA2		= IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D19__USBH2_DATA3		= IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D20__USBH2_DATA4		= IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D21__GPIO2_5		= IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_D21__USBH2_DATA5		= IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D22__USBH2_DATA6		= IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D23__USBH2_DATA7		= IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D25__UART3_RXD		= IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_EIM_D26__UART3_TXD		= IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_EIM_D27__GPIO2_9		= IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A16__GPIO2_10		= IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A17__GPIO2_11		= IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A20__GPIO2_14		= IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A22__GPIO2_16		= IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A24__USBH2_CLK		= IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_A25__USBH2_DIR		= IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_A26__GPIO2_20		= IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A26__USBH2_STP		= IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_A27__USBH2_NXT		= IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_EB2__FEC_MDIO		= IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
+	MX51_PAD_EIM_EB3__FEC_RDATA1		= IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_EB3__GPIO2_23		= IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS0__GPIO2_25		= IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS2__FEC_RDATA2		= IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_CS2__GPIO2_27		= IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS3__FEC_RDATA3		= IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_CS3__GPIO2_28		= IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS4__FEC_RX_ER		= IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_EIM_CS4__GPIO2_29		= IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS5__FEC_CRS		= IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_DRAM_RAS__DRAM_RAS		= IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CAS__DRAM_CAS		= IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDWE__DRAM_SDWE		= IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0	= IOMUX_PAD(0x4b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1	= IOMUX_PAD(0x4b4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCLK__DRAM_SDCLK		= IOMUX_PAD(0x4b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS0__DRAM_SDQS0		= IOMUX_PAD(0x4bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS1__DRAM_SDQS1		= IOMUX_PAD(0x4c0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS2__DRAM_SDQS2		= IOMUX_PAD(0x4c4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS3__DRAM_SDQS3		= IOMUX_PAD(0x4c8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CS0__DRAM_CS0		= IOMUX_PAD(0x4cc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CS1__DRAM_CS1		= IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM0__DRAM_DQM0		= IOMUX_PAD(0x4d4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM1__DRAM_DQM1		= IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM2__DRAM_DQM2		= IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM3__DRAM_DQM3		= IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_WE_B__PATA_DIOW		= IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_RE_B__PATA_DIOR		= IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_ALE__PATA_BUFFER_EN	= IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CLE__PATA_RESET_B	= IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_WP_B__PATA_DMACK		= IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_RB0__PATA_DMARQ		= IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_RB1__PATA_IORDY		= IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_RB2__FEC_COL		= IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_NANDF_RB2__GPIO3_10		= IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_RB3__FEC_RX_CLK		= IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_NANDF_RB3__GPIO3_11		= IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO_NAND__PATA_INTRQ		= IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS2__FEC_TX_ER		= IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_CS2__PATA_CS_0		= IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS3__FEC_MDC		= IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_CS3__PATA_CS_1		= IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS4__FEC_TDATA1		= IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_CS4__PATA_DA_0		= IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS5__FEC_TDATA2		= IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_CS5__PATA_DA_1		= IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS6__FEC_TDATA3		= IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_CS6__PATA_DA_2		= IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS7__FEC_TX_EN		= IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	= IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
+	MX51_PAD_NANDF_D15__GPIO3_25		= IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_D15__PATA_DATA15		= IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D14__GPIO3_26		= IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_D14__PATA_DATA14		= IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D13__GPIO3_27		= IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_D13__PATA_DATA13		= IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D12__PATA_DATA12		= IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D11__FEC_RX_DV		= IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D11__PATA_DATA11		= IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D10__GPIO3_30		= IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_D10__PATA_DATA10		= IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D9__FEC_RDATA0		= IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4),
+	MX51_PAD_NANDF_D9__GPIO3_31		= IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_D9__PATA_DATA9		= IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D8__FEC_TDATA0		= IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_D8__PATA_DATA8		= IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D7__PATA_DATA7		= IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D6__PATA_DATA6		= IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D5__PATA_DATA5		= IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D4__PATA_DATA4		= IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D3__PATA_DATA3		= IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D2__PATA_DATA2		= IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D1__PATA_DATA1		= IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D0__PATA_DATA0		= IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_CSI2_D12__GPIO4_9		= IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSI2_D13__GPIO4_10		= IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	= IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_MISO__ECSPI1_MISO	= IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_SS0__ECSPI1_SS0		= IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_SS0__GPIO4_24		= IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_SS1__ECSPI1_SS1		= IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_SS1__GPIO4_25		= IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_RDY__ECSPI1_RDY		= IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_RDY__GPIO4_26		= IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	= IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_UART1_RXD__UART1_RXD		= IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_UART1_TXD__UART1_TXD		= IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_UART1_CTS__UART1_CTS		= IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_USBH1_CLK__USBH1_CLK		= IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DIR__USBH1_DIR		= IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_STP__GPIO1_27		= IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_USBH1_STP__USBH1_STP		= IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_NXT__USBH1_NXT		= IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA0__USBH1_DATA0	= IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA1__USBH1_DATA1	= IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA2__USBH1_DATA2	= IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA3__USBH1_DATA3	= IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA4__USBH1_DATA4	= IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA5__USBH1_DATA5	= IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA6__USBH1_DATA6	= IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA7__USBH1_DATA7	= IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_DI1_PIN11__ECSPI1_SS2		= IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_DI1_PIN12__GPIO3_1		= IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_PIN13__GPIO3_2		= IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_D0_CS__GPIO3_3		= IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_D1_CS__GPIO3_4		= IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DISPB2_SER_DIN__GPIO3_5	= IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DISPB2_SER_DIO__GPIO3_6	= IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_PIN3__DI1_PIN3		= IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI1_PIN2__DI1_PIN2		= IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	= IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI_GP4__DI2_PIN15		= IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_SD1_CMD__SD1_CMD		= IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD1_CLK__SD1_CLK		= IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
+	MX51_PAD_SD1_DATA0__SD1_DATA0		= IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD1_DATA1__SD1_DATA1		= IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD1_DATA2__SD1_DATA2		= IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD1_DATA3__SD1_DATA3		= IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_GPIO1_0__GPIO1_0		= IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_0__SD1_CD		= IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_PAD_GPIO1_1__SD1_WP		= IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_PAD_SD2_CMD__SD2_CMD		= IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD2_CLK__SD2_CLK		= IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
+	MX51_PAD_SD2_DATA0__SD2_DATA0		= IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD2_DATA1__SD2_DATA1		= IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD2_DATA2__SD2_DATA2		= IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD2_DATA3__SD2_DATA3		= IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_GPIO1_2__GPIO1_2		= IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_2__PWM1_PWMO		= IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_GPIO1_3__GPIO1_3		= IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_5__GPIO1_5		= IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_6__GPIO1_6		= IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_7__GPIO1_7		= IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_7__SD2_WP		= IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_PAD_GPIO1_8__SD2_CD		= IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_GRP_DDRPKS				= IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B4			= IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_PKEDDR				= IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_A0				= IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_A1				= IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRAPUS			= IOMUX_PAD(0x84c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR0			= IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR1			= IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR2			= IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR3			= IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B0			= IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRAPKS			= IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B1			= IOMUX_PAD(0x880, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRPUS				= IOMUX_PAD(0x884, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B2			= IOMUX_PAD(0x88c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_PKEADDR			= IOMUX_PAD(0x890, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B4			= IOMUX_PAD(0x89c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_INMODE1			= IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B0			= IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B1			= IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B2			= IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_SR_A1			= IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX51_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx53.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx53.h
new file mode 100644
index 000000000..1b75fd1cf
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/iomux-mx53.h
@@ -0,0 +1,1216 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on Freescale's Linux i.MX iomux-mx53.h file:
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IOMUX_MX53_H__
+#define __IOMUX_MX53_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX53_UART_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX53_SDHC_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+
+/*
+ * The naming convention for the pad modes is MX53_PAD_<padname>__<padmode>
+ * If <padname> refers to a GPIO, it is named GPIO_<unit>
+ * If <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*								    PAD    MUX   ALT INPSE PATH PADCTRL */
+enum {
+	MX53_PAD_GPIO_19__KPP_COL_5			= IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__GPIO4_5			= IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__CCM_CLKO			= IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__SPDIF_OUT1			= IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2		= IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__ECSPI1_RDY			= IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__FEC_TDATA_3			= IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__SRC_INT_BOOT			= IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__KPP_COL_0			= IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__GPIO4_6			= IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC		= IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__UART4_TXD_MUX		= IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL0__ECSPI1_SCLK			= IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__FEC_RDATA_3			= IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__SRC_ANY_PU_RST		= IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__KPP_ROW_0			= IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__GPIO4_7			= IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD		= IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__UART4_RXD_MUX		= IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__ECSPI1_MOSI			= IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__FEC_TX_ER			= IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__KPP_COL_1			= IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__GPIO4_8			= IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS		= IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__UART5_TXD_MUX		= IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL1__ECSPI1_MISO			= IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__FEC_RX_CLK			= IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__USBPHY1_TXREADY		= IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__KPP_ROW_1			= IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__GPIO4_9			= IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD		= IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__UART5_RXD_MUX		= IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__ECSPI1_SS0			= IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__FEC_COL			= IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__USBPHY1_RXVALID		= IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__KPP_COL_2			= IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__GPIO4_10			= IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__CAN1_TXCAN			= IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__FEC_MDIO			= IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__ECSPI1_SS1			= IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__FEC_RDATA_2			= IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE		= IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__KPP_ROW_2			= IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__GPIO4_11			= IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__CAN1_RXCAN			= IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__FEC_MDC			= IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__ECSPI1_SS2			= IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__FEC_TDATA_2			= IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__USBPHY1_RXERROR		= IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__KPP_COL_3			= IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__GPIO4_12			= IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__USBOH3_H2_DP			= IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__SPDIF_IN1			= IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__I2C2_SCL			= IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__ECSPI1_SS3			= IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__FEC_CRS			= IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK		= IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__KPP_ROW_3			= IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__GPIO4_13			= IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__USBOH3_H2_DM			= IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK		= IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__I2C2_SDA			= IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__OSC32K_32K_OUT		= IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__CCM_PLL4_BYP			= IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0		= IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__KPP_COL_4			= IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__GPIO4_14			= IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__CAN2_TXCAN			= IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__IPU_SISG_4			= IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__UART5_RTS			= IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC		= IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1		= IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__KPP_ROW_4			= IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__GPIO4_15			= IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__CAN2_RXCAN			= IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__IPU_SISG_5			= IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__UART5_CTS			= IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR		= IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID		= IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK		= IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__GPIO4_16			= IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR		= IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0	= IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0		= IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID		= IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__IPU_DI0_PIN15		= IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__GPIO4_17			= IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC		= IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1	= IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1		= IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__USBPHY1_BVALID		= IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__IPU_DI0_PIN2			= IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__GPIO4_18			= IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD		= IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2	= IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2		= IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION		= IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__IPU_DI0_PIN3			= IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__GPIO4_19			= IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS		= IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3	= IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3		= IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__USBPHY1_IDDIG		= IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__IPU_DI0_PIN4			= IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__GPIO4_20			= IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD		= IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__ESDHC1_WP			= IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD		= IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4		= IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT	= IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0		= IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__GPIO4_21			= IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__CSPI_SCLK			= IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0	= IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN	= IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5		= IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY		= IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1		= IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__GPIO4_22			= IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__CSPI_MOSI			= IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1	= IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL
+							= IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6		= IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID		= IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2		= IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__GPIO4_23			= IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__CSPI_MISO			= IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2	= IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE		= IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7		= IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE		= IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3		= IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__GPIO4_24			= IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__CSPI_SS0			= IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3	= IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR	= IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8		= IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR		= IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4		= IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__GPIO4_25			= IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__CSPI_SS1			= IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4	= IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB		= IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9		= IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK		= IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5		= IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__GPIO4_26			= IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__CSPI_SS2			= IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5	= IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS	= IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10		= IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0	= IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6		= IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__GPIO4_27			= IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__CSPI_SS3			= IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6	= IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE	= IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11		= IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1	= IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7		= IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__GPIO4_28			= IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__CSPI_RDY			= IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7	= IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0	= IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12		= IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID		= IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8		= IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__GPIO4_29			= IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__PWM1_PWMO			= IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B		= IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1	= IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13		= IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__USBPHY2_AVALID		= IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9		= IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__GPIO4_30			= IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__PWM2_PWMO			= IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B		= IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2	= IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14		= IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0		= IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10		= IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__GPIO4_31			= IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP		= IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3
+							= IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15		= IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1		= IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11		= IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__GPIO5_5			= IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT		= IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4
+							= IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16		= IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2		= IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12		= IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__GPIO5_6			= IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK		= IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5
+							= IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17		= IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3		= IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13		= IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__GPIO5_7			= IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS		= IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0
+							= IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18		= IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4		= IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14		= IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__GPIO5_8			= IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC		= IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1
+							= IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19		= IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5		= IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15		= IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__GPIO5_9			= IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__ECSPI1_SS1		= IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__ECSPI2_SS1		= IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2
+							= IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20		= IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6		= IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16		= IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__GPIO5_10			= IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__ECSPI2_MOSI		= IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC		= IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0		= IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3
+							= IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21		= IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7		= IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17		= IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__GPIO5_11			= IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__ECSPI2_MISO		= IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD		= IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1		= IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4
+							= IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22		= IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18		= IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__GPIO5_12			= IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__ECSPI2_SS0		= IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS		= IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS		= IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5
+							= IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23		= IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2		= IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19		= IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__GPIO5_13			= IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__ECSPI2_SCLK		= IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD		= IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC		= IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6
+							= IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24		= IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3		= IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20		= IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__GPIO5_14			= IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__ECSPI1_SCLK		= IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC		= IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7
+							= IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25		= IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__SATA_PHY_TDI		= IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21		= IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__GPIO5_15			= IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__ECSPI1_MOSI		= IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD		= IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0	= IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26		= IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__SATA_PHY_TDO		= IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22		= IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__GPIO5_16			= IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__ECSPI1_MISO		= IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS		= IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1	= IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27		= IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__SATA_PHY_TCK		= IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23		= IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__GPIO5_17			= IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__ECSPI1_SS0		= IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD		= IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2	= IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28		= IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__SATA_PHY_TMS		= IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK		= IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__GPIO5_18			= IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0		= IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29		= IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC		= IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__GPIO5_19			= IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK		= IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1		= IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30		= IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__TPIU_TRCTL			= IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN		= IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__GPIO5_20			= IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2		= IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31		= IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK		= IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC		= IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__GPIO5_21			= IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3		= IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32		= IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0		= IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4		= IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__GPIO5_22			= IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__KPP_COL_5			= IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__ECSPI1_SCLK			= IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP		= IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC		= IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33		= IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__TPIU_TRACE_1		= IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5		= IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__GPIO5_23			= IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__KPP_ROW_5			= IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__ECSPI1_MOSI			= IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT		= IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD		= IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34		= IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__TPIU_TRACE_2		= IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6		= IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__GPIO5_24			= IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__KPP_COL_6			= IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__ECSPI1_MISO			= IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK		= IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS		= IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35		= IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__TPIU_TRACE_3		= IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7		= IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__GPIO5_25			= IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__KPP_ROW_6			= IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__ECSPI1_SS0			= IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR		= IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD		= IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36		= IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__TPIU_TRACE_4		= IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8		= IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__GPIO5_26			= IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__KPP_COL_7			= IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__ECSPI2_SCLK			= IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC		= IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__I2C1_SDA			= IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37		= IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__TPIU_TRACE_5		= IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9		= IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__GPIO5_27			= IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__KPP_ROW_7			= IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__ECSPI2_MOSI			= IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR		= IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__I2C1_SCL			= IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38		= IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__TPIU_TRACE_6		= IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10		= IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__GPIO5_28			= IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX		= IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__ECSPI2_MISO		= IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC		= IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4		= IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39		= IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__TPIU_TRACE_7		= IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11		= IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__GPIO5_29			= IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX		= IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__ECSPI2_SS0			= IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS		= IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5		= IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40		= IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__TPIU_TRACE_8		= IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12		= IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__GPIO5_30			= IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__UART4_TXD_MUX		= IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0	= IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6		= IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41		= IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__TPIU_TRACE_9		= IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13		= IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__GPIO5_31			= IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__UART4_RXD_MUX		= IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1	= IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7		= IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42		= IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__TPIU_TRACE_10		= IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14		= IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__GPIO6_0			= IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__UART5_TXD_MUX		= IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2	= IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8		= IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43		= IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__TPIU_TRACE_11		= IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15		= IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__GPIO6_1			= IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__UART5_RXD_MUX		= IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3	= IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9		= IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44		= IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__TPIU_TRACE_12		= IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16		= IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__GPIO6_2			= IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__UART4_RTS			= IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4	= IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10		= IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45		= IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__TPIU_TRACE_13		= IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17		= IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__GPIO6_3			= IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__UART4_CTS			= IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5	= IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11		= IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46		= IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__TPIU_TRACE_14		= IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18		= IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__GPIO6_4			= IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__UART5_RTS			= IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6	= IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12		= IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47		= IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__TPIU_TRACE_15		= IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19		= IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__GPIO6_5			= IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__UART5_CTS			= IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7	= IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13		= IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48		= IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK		= IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__EMI_WEIM_A_25			= IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__GPIO5_2			= IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__ECSPI2_RDY			= IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__IPU_DI1_PIN12			= IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__CSPI_SS1			= IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__IPU_DI0_D1_CS			= IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__USBPHY1_BISTOK		= IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__EMI_WEIM_EB_2			= IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__GPIO2_30			= IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK		= IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS		= IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__ECSPI1_SS0			= IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__I2C2_SCL			= IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__EMI_WEIM_D_16			= IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__GPIO3_16			= IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__IPU_DI0_PIN5			= IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK		= IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__ECSPI1_SCLK			= IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__I2C2_SDA			= IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__EMI_WEIM_D_17			= IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__GPIO3_17			= IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__IPU_DI0_PIN6			= IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN		= IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__ECSPI1_MISO			= IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__I2C3_SCL			= IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__EMI_WEIM_D_18			= IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__GPIO3_18			= IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DI0_PIN7			= IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO		= IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__ECSPI1_MOSI			= IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__I2C3_SDA			= IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DI1_D0_CS			= IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__EMI_WEIM_D_19			= IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__GPIO3_19			= IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__IPU_DI0_PIN8			= IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS		= IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__ECSPI1_SS1			= IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__EPIT1_EPITO			= IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__UART1_CTS			= IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D19__USBOH3_USBH2_OC		= IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__EMI_WEIM_D_20			= IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__GPIO3_20			= IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__IPU_DI0_PIN16			= IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__IPU_SER_DISP0_CS		= IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__CSPI_SS0			= IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__EPIT2_EPITO			= IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__UART1_RTS			= IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D20__USBOH3_USBH2_PWR		= IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__EMI_WEIM_D_21			= IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__GPIO3_21			= IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__IPU_DI0_PIN17			= IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK		= IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__CSPI_SCLK			= IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__I2C1_SCL			= IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__USBOH3_USBOTG_OC		= IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__EMI_WEIM_D_22			= IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__GPIO3_22			= IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__IPU_DI0_PIN1			= IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN		= IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__CSPI_MISO			= IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR		= IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__EMI_WEIM_D_23			= IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__GPIO3_23			= IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__UART3_CTS			= IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D23__UART1_DCD			= IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI0_D0_CS			= IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI1_PIN2			= IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN		= IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI1_PIN14			= IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__EMI_WEIM_EB_3			= IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__GPIO2_31			= IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__UART3_RTS			= IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_EB3__UART1_RI			= IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_DI1_PIN3			= IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC		= IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_DI1_PIN16			= IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__EMI_WEIM_D_24			= IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__GPIO3_24			= IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__UART3_TXD_MUX			= IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D24__ECSPI1_SS2			= IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__CSPI_SS2			= IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS		= IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__ECSPI2_SS2			= IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__UART1_DTR			= IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__EMI_WEIM_D_25			= IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__GPIO3_25			= IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__UART3_RXD_MUX			= IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D25__ECSPI1_SS3			= IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__CSPI_SS3			= IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC		= IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__ECSPI2_SS3			= IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__UART1_DSR			= IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__EMI_WEIM_D_26			= IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__GPIO3_26			= IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__UART2_TXD_MUX			= IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D26__FIRI_RXD			= IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_CSI0_D_1			= IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_DI1_PIN11			= IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_SISG_2			= IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_DISP1_DAT_22		= IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__EMI_WEIM_D_27			= IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__GPIO3_27			= IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__UART2_RXD_MUX			= IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D27__FIRI_TXD			= IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_CSI0_D_0			= IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_DI1_PIN13			= IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_SISG_3			= IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_DISP1_DAT_23		= IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__EMI_WEIM_D_28			= IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__GPIO3_28			= IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__UART2_CTS			= IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO		= IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__CSPI_MOSI			= IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__I2C1_SDA			= IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_EXT_TRIG			= IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_DI0_PIN13			= IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__EMI_WEIM_D_29			= IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__GPIO3_29			= IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__UART2_RTS			= IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS		= IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__CSPI_SS0			= IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DI1_PIN15			= IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_CSI1_VSYNC		= IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DI0_PIN14			= IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__EMI_WEIM_D_30			= IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__GPIO3_30			= IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__UART3_CTS			= IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_CSI0_D_3			= IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_DI0_PIN11			= IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_DISP1_DAT_21		= IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__USBOH3_USBH1_OC		= IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__USBOH3_USBH2_OC		= IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__EMI_WEIM_D_31			= IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__GPIO3_31			= IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__UART3_RTS			= IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_CSI0_D_2			= IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_DI0_PIN12			= IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_DISP1_DAT_20		= IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__USBOH3_USBH1_PWR		= IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__USBOH3_USBH2_PWR		= IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__EMI_WEIM_A_24			= IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__GPIO5_4			= IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_DISP1_DAT_19		= IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_CSI1_D_19			= IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_SISG_2			= IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__USBPHY2_BVALID		= IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__EMI_WEIM_A_23			= IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__GPIO6_6			= IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_DISP1_DAT_18		= IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_CSI1_D_18			= IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_SISG_3			= IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__USBPHY2_ENDSESSION		= IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__EMI_WEIM_A_22			= IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__GPIO2_16			= IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__IPU_DISP1_DAT_17		= IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__IPU_CSI1_D_17			= IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__SRC_BT_CFG1_7			= IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__EMI_WEIM_A_21			= IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__GPIO2_17			= IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__IPU_DISP1_DAT_16		= IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__IPU_CSI1_D_16			= IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__SRC_BT_CFG1_6			= IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__EMI_WEIM_A_20			= IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__GPIO2_18			= IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__IPU_DISP1_DAT_15		= IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__IPU_CSI1_D_15			= IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__SRC_BT_CFG1_5			= IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__EMI_WEIM_A_19			= IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__GPIO2_19			= IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__IPU_DISP1_DAT_14		= IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__IPU_CSI1_D_14			= IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__SRC_BT_CFG1_4			= IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__EMI_WEIM_A_18			= IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__GPIO2_20			= IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__IPU_DISP1_DAT_13		= IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__IPU_CSI1_D_13			= IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__SRC_BT_CFG1_3			= IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__EMI_WEIM_A_17			= IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__GPIO2_21			= IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__IPU_DISP1_DAT_12		= IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__IPU_CSI1_D_12			= IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__SRC_BT_CFG1_2			= IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__EMI_WEIM_A_16			= IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__GPIO2_22			= IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK		= IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK		= IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__SRC_BT_CFG1_1			= IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__EMI_WEIM_CS_0			= IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__GPIO2_23			= IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__ECSPI2_SCLK			= IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__IPU_DI1_PIN5			= IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__EMI_WEIM_CS_1			= IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__GPIO2_24			= IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__ECSPI2_MOSI			= IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__IPU_DI1_PIN6			= IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__EMI_WEIM_OE			= IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__GPIO2_25			= IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__ECSPI2_MISO			= IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__IPU_DI1_PIN7			= IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__USBPHY2_IDDIG			= IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__EMI_WEIM_RW			= IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__GPIO2_26			= IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__ECSPI2_SS0			= IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__IPU_DI1_PIN8			= IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT		= IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__EMI_WEIM_LBA			= IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__GPIO2_27			= IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__ECSPI2_SS1			= IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__IPU_DI1_PIN17			= IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__SRC_BT_CFG1_0			= IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__EMI_WEIM_EB_0			= IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__GPIO2_28			= IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11		= IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__IPU_CSI1_D_11			= IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__GPC_PMIC_RDY			= IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__SRC_BT_CFG2_7			= IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__EMI_WEIM_EB_1			= IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__GPIO2_29			= IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10		= IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__IPU_CSI1_D_10			= IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__SRC_BT_CFG2_6			= IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0		= IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__GPIO3_0			= IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9		= IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__IPU_CSI1_D_9			= IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__SRC_BT_CFG2_5			= IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1		= IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__GPIO3_1			= IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8		= IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__IPU_CSI1_D_8			= IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__SRC_BT_CFG2_4			= IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2		= IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__GPIO3_2			= IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7		= IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__IPU_CSI1_D_7			= IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__SRC_BT_CFG2_3			= IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3		= IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__GPIO3_3			= IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6		= IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__IPU_CSI1_D_6			= IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__SRC_BT_CFG2_2			= IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4		= IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__GPIO3_4			= IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5		= IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__IPU_CSI1_D_5			= IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__SRC_BT_CFG3_7			= IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5		= IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__GPIO3_5			= IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4		= IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__IPU_CSI1_D_4			= IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__SRC_BT_CFG3_6			= IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6		= IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__GPIO3_6			= IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3		= IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__IPU_CSI1_D_3			= IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__SRC_BT_CFG3_5			= IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7		= IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__GPIO3_7			= IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2		= IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__IPU_CSI1_D_2			= IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__SRC_BT_CFG3_4			= IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8		= IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__GPIO3_8			= IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1		= IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__IPU_CSI1_D_1			= IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__SRC_BT_CFG3_3			= IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9		= IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__GPIO3_9			= IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0		= IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__IPU_CSI1_D_0			= IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__SRC_BT_CFG3_2			= IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10		= IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__GPIO3_10			= IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__IPU_DI1_PIN15		= IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN		= IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__SRC_BT_CFG3_1		= IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11		= IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__GPIO3_11			= IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__IPU_DI1_PIN2			= IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC		= IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12		= IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__GPIO3_12			= IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__IPU_DI1_PIN3			= IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC		= IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13		= IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__GPIO3_13			= IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__IPU_DI1_D0_CS		= IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK		= IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14		= IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__GPIO3_14			= IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__IPU_DI1_D1_CS		= IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK		= IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15		= IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__GPIO3_15			= IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__IPU_DI1_PIN1			= IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__IPU_DI1_PIN4			= IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B		= IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WE_B__GPIO6_12			= IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B		= IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RE_B__GPIO6_13			= IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT		= IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__GPIO5_0			= IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B		= IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX3_P__GPIO6_22			= IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3		= IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX2_P__GPIO6_24			= IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2		= IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_CLK_P__GPIO6_26			= IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK		= IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX1_P__GPIO6_28			= IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1		= IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX0_P__GPIO6_30			= IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0		= IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX3_P__GPIO7_22			= IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3		= IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_CLK_P__GPIO7_24			= IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK		= IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX2_P__GPIO7_26			= IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2		= IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX1_P__GPIO7_28			= IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1		= IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX0_P__GPIO7_30			= IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0		= IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_10__GPIO4_0			= IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_10__OSC32k_32K_OUT		= IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_11__GPIO4_1			= IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_12__GPIO4_2			= IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_13__GPIO4_3			= IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_14__GPIO4_4			= IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__EMI_NANDF_CLE		= IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__GPIO6_7			= IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0		= IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__EMI_NANDF_ALE		= IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__GPIO6_8			= IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1		= IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B		= IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__GPIO6_9			= IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2		= IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0		= IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__GPIO6_10			= IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3		= IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0		= IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__GPIO6_11			= IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4		= IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1		= IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__GPIO6_14			= IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__MLB_MLBCLK			= IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5		= IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2		= IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__GPIO6_15			= IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__IPU_SISG_0			= IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__ESAI1_TX0			= IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__EMI_WEIM_CRE		= IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK		= IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__MLB_MLBSIG			= IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6		= IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3		= IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__GPIO6_16			= IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__IPU_SISG_1			= IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__ESAI1_TX1			= IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__EMI_WEIM_A_26		= IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__MLB_MLBDAT			= IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7		= IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__FEC_MDIO			= IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__GPIO1_22			= IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__ESAI1_SCKR			= IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__FEC_COL			= IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2		= IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3	= IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49		= IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__FEC_TX_CLK		= IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__GPIO1_23			= IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__ESAI1_FSR			= IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4	= IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50		= IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__FEC_RX_ER			= IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__GPIO1_24			= IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__ESAI1_HCKR			= IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__FEC_RX_CLK			= IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3		= IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__FEC_RX_DV			= IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__GPIO1_25			= IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__ESAI1_SCKT			= IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__FEC_RDATA_1			= IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__GPIO1_26			= IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__ESAI1_FST			= IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__MLB_MLBSIG			= IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1		= IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__FEC_RDATA_0			= IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__GPIO1_27			= IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__ESAI1_HCKT			= IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__OSC32k_32K_OUT		= IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__FEC_TX_EN			= IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__GPIO1_28			= IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2		= IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__FEC_TDATA_1			= IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__GPIO1_29			= IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3		= IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__MLB_MLBCLK			= IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK		= IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__FEC_TDATA_0			= IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__GPIO1_30			= IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1		= IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0		= IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__FEC_MDC			= IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__GPIO1_31			= IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__ESAI1_TX5_RX0			= IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__MLB_MLBDAT			= IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG	= IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1		= IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__PATA_DIOW			= IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__GPIO6_17			= IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__UART1_TXD_MUX		= IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2		= IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__PATA_DMACK			= IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__GPIO6_18			= IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__UART1_RXD_MUX		= IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3		= IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__PATA_DMARQ			= IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__GPIO7_0			= IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__UART2_TXD_MUX		= IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0		= IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4		= IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN		= IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__GPIO7_1		= IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX		= IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1		= IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5	= IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__PATA_INTRQ			= IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__GPIO7_2			= IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__UART2_CTS			= IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__CAN1_TXCAN			= IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2		= IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6		= IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__PATA_DIOR			= IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__GPIO7_3			= IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__UART2_RTS			= IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__CAN1_RXCAN			= IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7		= IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B	= IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__GPIO7_4			= IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__ESDHC3_CMD		= IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__UART1_CTS		= IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__CAN2_TXCAN		= IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0	= IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__PATA_IORDY			= IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__GPIO7_5			= IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__ESDHC3_CLK			= IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__UART1_RTS			= IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__CAN2_RXCAN			= IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1		= IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__PATA_DA_0			= IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__GPIO7_6			= IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__ESDHC3_RST			= IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__OWIRE_LINE			= IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2		= IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__PATA_DA_1			= IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__GPIO7_7			= IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__ESDHC4_CMD			= IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__UART3_CTS			= IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3		= IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__PATA_DA_2			= IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__GPIO7_8			= IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__ESDHC4_CLK			= IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__UART3_RTS			= IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4		= IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__PATA_CS_0			= IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__GPIO7_9			= IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__UART3_TXD_MUX		= IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5		= IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__PATA_CS_1			= IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__GPIO7_10			= IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__UART3_RXD_MUX		= IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6		= IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__PATA_DATA_0		= IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__GPIO2_0			= IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__EMI_NANDF_D_0		= IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__ESDHC3_DAT4		= IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0	= IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0		= IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7		= IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__PATA_DATA_1		= IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__GPIO2_1			= IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__EMI_NANDF_D_1		= IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__ESDHC3_DAT5		= IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1	= IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1		= IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__PATA_DATA_2		= IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__GPIO2_2			= IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__EMI_NANDF_D_2		= IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__ESDHC3_DAT6		= IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2	= IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2		= IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__PATA_DATA_3		= IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__GPIO2_3			= IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__EMI_NANDF_D_3		= IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__ESDHC3_DAT7		= IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3	= IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3		= IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__PATA_DATA_4		= IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__GPIO2_4			= IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__EMI_NANDF_D_4		= IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__ESDHC4_DAT4		= IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4	= IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4		= IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__PATA_DATA_5		= IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__GPIO2_5			= IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__EMI_NANDF_D_5		= IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__ESDHC4_DAT5		= IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5	= IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5		= IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__PATA_DATA_6		= IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__GPIO2_6			= IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__EMI_NANDF_D_6		= IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__ESDHC4_DAT6		= IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6	= IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6		= IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__PATA_DATA_7		= IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__GPIO2_7			= IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__EMI_NANDF_D_7		= IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__ESDHC4_DAT7		= IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7	= IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7		= IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__PATA_DATA_8		= IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__GPIO2_8			= IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__ESDHC1_DAT4		= IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__EMI_NANDF_D_8		= IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__ESDHC3_DAT0		= IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8	= IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8		= IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__PATA_DATA_9		= IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__GPIO2_9			= IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__ESDHC1_DAT5		= IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__EMI_NANDF_D_9		= IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__ESDHC3_DAT1		= IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9	= IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9		= IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__PATA_DATA_10		= IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__GPIO2_10			= IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__ESDHC1_DAT6		= IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__EMI_NANDF_D_10		= IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__ESDHC3_DAT2		= IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10	= IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10		= IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__PATA_DATA_11		= IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__GPIO2_11			= IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__ESDHC1_DAT7		= IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__EMI_NANDF_D_11		= IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__ESDHC3_DAT3		= IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11	= IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11		= IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__PATA_DATA_12		= IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__GPIO2_12			= IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__ESDHC2_DAT4		= IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__EMI_NANDF_D_12		= IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__ESDHC4_DAT0		= IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12	= IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12		= IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__PATA_DATA_13		= IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__GPIO2_13			= IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__ESDHC2_DAT5		= IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__EMI_NANDF_D_13		= IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__ESDHC4_DAT1		= IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13	= IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13		= IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__PATA_DATA_14		= IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__GPIO2_14			= IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__ESDHC2_DAT6		= IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__EMI_NANDF_D_14		= IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__ESDHC4_DAT2		= IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14	= IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14		= IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__PATA_DATA_15		= IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__GPIO2_15			= IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__ESDHC2_DAT7		= IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__EMI_NANDF_D_15		= IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__ESDHC4_DAT3		= IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15	= IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15		= IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__ESDHC1_DAT0			= IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__GPIO1_16			= IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__GPT_CAPIN1			= IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__CSPI_MISO			= IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__CCM_PLL3_BYP		= IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__ESDHC1_DAT1			= IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__GPIO1_17			= IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__GPT_CAPIN2			= IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__CSPI_SS0			= IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__CCM_PLL4_BYP		= IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__ESDHC1_CMD			= IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_CMD__GPIO1_18			= IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__GPT_CMPOUT1			= IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__CSPI_MOSI			= IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__CCM_PLL1_BYP			= IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__ESDHC1_DAT2			= IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__GPIO1_19			= IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__GPT_CMPOUT2			= IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__PWM2_PWMO			= IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__WDOG1_WDOG_B		= IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__CSPI_SS1			= IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB	= IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__CCM_PLL2_BYP		= IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__ESDHC1_CLK			= IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_CLK__GPIO1_20			= IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__OSC32k_32K_OUT		= IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__GPT_CLKIN			= IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__CSPI_SCLK			= IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__SATA_PHY_DTB_0		= IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__ESDHC1_DAT3			= IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__GPIO1_21			= IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__GPT_CMPOUT3			= IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__PWM1_PWMO			= IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__WDOG2_WDOG_B		= IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__CSPI_SS2			= IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB	= IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1		= IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__ESDHC2_CLK			= IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_CLK__GPIO1_10			= IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__KPP_COL_5			= IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS		= IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__CSPI_SCLK			= IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__SCC_RANDOM_V			= IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__ESDHC2_CMD			= IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_CMD__GPIO1_11			= IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__KPP_ROW_5			= IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC		= IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__CSPI_MOSI			= IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__SCC_RANDOM			= IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__ESDHC2_DAT3			= IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__GPIO1_12			= IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__KPP_COL_6			= IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC		= IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__CSPI_SS2			= IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__SJC_DONE			= IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__ESDHC2_DAT2			= IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__GPIO1_13			= IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__KPP_ROW_6			= IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD		= IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__CSPI_SS1			= IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__SJC_FAIL			= IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__ESDHC2_DAT1			= IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__GPIO1_14			= IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__KPP_COL_7			= IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS		= IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__CSPI_SS0			= IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__RTIC_SEC_VIO		= IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__ESDHC2_DAT0			= IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__GPIO1_15			= IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__KPP_ROW_7			= IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD		= IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__CSPI_MISO			= IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__RTIC_DONE_INT		= IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CCM_CLKO			= IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__GPIO1_0			= IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__KPP_COL_5			= IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK		= IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__EPIT1_EPITO			= IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__SRTC_ALARM_DEB			= IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__USBOH3_USBH1_PWR		= IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CSU_TD				= IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__ESAI1_SCKR			= IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__GPIO1_1			= IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__KPP_ROW_5			= IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK		= IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__PWM2_PWMO			= IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__WDOG2_WDOG_B			= IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__ESDHC1_CD			= IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__SRC_TESTER_ACK			= IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__ESAI1_FSR			= IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__GPIO1_9			= IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__KPP_COL_6			= IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__CCM_REF_EN_B			= IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__PWM1_PWMO			= IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__WDOG1_WDOG_B			= IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__ESDHC1_WP			= IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__SCC_FAIL_STATE			= IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__ESAI1_HCKR			= IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__GPIO1_3			= IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__I2C3_SCL			= IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__DPLLIP1_TOG_EN			= IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__CCM_CLKO2			= IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0	= IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__USBOH3_USBH1_OC		= IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__MLB_MLBCLK			= IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__ESAI1_SCKT			= IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__GPIO1_6			= IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__I2C3_SDA			= IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__CCM_CCM_OUT_0			= IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__CSU_CSU_INT_DEB		= IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1	= IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__ESDHC2_LCTL			= IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__MLB_MLBSIG			= IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__ESAI1_FST			= IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__GPIO1_2			= IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__KPP_ROW_6			= IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__CCM_CCM_OUT_1			= IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0		= IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2	= IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__ESDHC2_WP			= IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__MLB_MLBDAT			= IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__ESAI1_HCKT			= IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__GPIO1_4			= IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__KPP_COL_7			= IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__CCM_CCM_OUT_2			= IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1		= IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3	= IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__ESDHC2_CD			= IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__SCC_SEC_STATE			= IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__ESAI1_TX2_RX3			= IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__GPIO1_5			= IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__KPP_ROW_7			= IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CCM_CLKO			= IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2		= IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4	= IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__I2C3_SCL			= IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CCM_PLL1_BYP			= IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__ESAI1_TX4_RX1			= IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__GPIO1_7			= IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__EPIT1_EPITO			= IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__CAN1_TXCAN			= IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__UART2_TXD_MUX			= IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_GPIO_7__FIRI_RXD			= IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__SPDIF_PLOCK			= IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__CCM_PLL2_BYP			= IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__ESAI1_TX5_RX0			= IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__GPIO1_8			= IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__EPIT2_EPITO			= IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__CAN1_RXCAN			= IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__UART2_RXD_MUX			= IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL),
+	MX53_PAD_GPIO_8__FIRI_TXD			= IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__SPDIF_SRCLK			= IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__CCM_PLL3_BYP			= IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__ESAI1_TX3_RX2			= IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__GPIO7_11			= IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT		= IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1		= IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__SPDIF_IN1			= IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__I2C3_SDA			= IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__SJC_DE_B			= IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__ESAI1_TX0			= IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__GPIO7_12			= IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0		= IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__GPC_PMIC_RDY			= IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG		= IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SPDIF_OUT1			= IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__IPU_SNOOP2			= IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SJC_JTAG_ACT			= IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__ESAI1_TX1			= IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__GPIO7_13			= IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1		= IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__OWIRE_LINE			= IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG	= IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK		= IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__ESDHC1_LCTL			= IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__SRC_SYSTEM_RST		= IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX53_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/spl.h
new file mode 100644
index 000000000..20c6cae93
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/spl.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_SPL_H__
+#define __ASM_ARCH_SPL_H__
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_NAND	1
+
+#endif	/* __ASM_ARCH_SPL_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/sys_proto.h
new file mode 100644
index 000000000..ac7705b3b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include "../arch-imx/cpu.h"
+
+#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
+u32 get_cpu_rev(void);
+unsigned imx_ddr_size(void);
+void sdelay(unsigned long);
+void set_chipselect_size(int const);
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+
+int fecmxc_initialize(bd_t *bis);
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
+char *get_reset_cause(void);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h
new file mode 100644
index 000000000..1b4ded7fe
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/clock.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+#ifdef CONFIG_SYS_MX6_HCLK
+#define MXC_HCLK	CONFIG_SYS_MX6_HCLK
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_SYS_MX6_CLK32
+#define MXC_CLK32	CONFIG_SYS_MX6_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_PER_CLK,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_IPG_PERCLK,
+	MXC_UART_CLK,
+	MXC_CSPI_CLK,
+	MXC_AXI_CLK,
+	MXC_EMI_SLOW_CLK,
+	MXC_DDR_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_ESDHC4_CLK,
+	MXC_SATA_CLK,
+	MXC_NFC_CLK,
+	MXC_I2C_CLK,
+};
+
+enum enet_freq {
+	ENET_25MHz,
+	ENET_50MHz,
+	ENET_100MHz,
+	ENET_125MHz,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+void enable_ocotp_clk(unsigned char enable);
+void enable_usboh3_clk(unsigned char enable);
+int enable_sata_clock(void);
+int enable_pcie_clock(void);
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+void enable_ipu_clock(void);
+int enable_fec_anatop_clock(enum enet_freq freq);
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h
new file mode 100644
index 000000000..720207303
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -0,0 +1,893 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+
+#define CCM_CCOSR		0x020c4060
+#define CCM_CCGR0		0x020C4068
+#define CCM_CCGR1		0x020C406c
+#define CCM_CCGR2		0x020C4070
+#define CCM_CCGR3		0x020C4074
+#define CCM_CCGR4		0x020C4078
+#define CCM_CCGR5		0x020C407c
+#define CCM_CCGR6		0x020C4080
+
+#define PMU_MISC2		0x020C8170
+
+#ifndef __ASSEMBLY__
+struct mxc_ccm_reg {
+	u32 ccr;	/* 0x0000 */
+	u32 ccdr;
+	u32 csr;
+	u32 ccsr;
+	u32 cacrr;	/* 0x0010*/
+	u32 cbcdr;
+	u32 cbcmr;
+	u32 cscmr1;
+	u32 cscmr2;	/* 0x0020 */
+	u32 cscdr1;
+	u32 cs1cdr;
+	u32 cs2cdr;
+	u32 cdcdr;	/* 0x0030 */
+	u32 chsccdr;
+	u32 cscdr2;
+	u32 cscdr3;
+	u32 cscdr4;	/* 0x0040 */
+	u32 resv0;
+	u32 cdhipr;
+	u32 cdcr;
+	u32 ctor;	/* 0x0050 */
+	u32 clpcr;
+	u32 cisr;
+	u32 cimr;
+	u32 ccosr;	/* 0x0060 */
+	u32 cgpr;
+	u32 CCGR0;
+	u32 CCGR1;
+	u32 CCGR2;	/* 0x0070 */
+	u32 CCGR3;
+	u32 CCGR4;
+	u32 CCGR5;
+	u32 CCGR6;	/* 0x0080 */
+	u32 CCGR7;
+	u32 cmeor;
+	u32 resv[0xfdd];
+	u32 analog_pll_sys;			/* 0x4000 */
+	u32 analog_pll_sys_set;
+	u32 analog_pll_sys_clr;
+	u32 analog_pll_sys_tog;
+	u32 analog_usb1_pll_480_ctrl;		/* 0x4010 */
+	u32 analog_usb1_pll_480_ctrl_set;
+	u32 analog_usb1_pll_480_ctrl_clr;
+	u32 analog_usb1_pll_480_ctrl_tog;
+	u32 analog_reserved0[4];
+	u32 analog_pll_528;			/* 0x4030 */
+	u32 analog_pll_528_set;
+	u32 analog_pll_528_clr;
+	u32 analog_pll_528_tog;
+	u32 analog_pll_528_ss;			/* 0x4040 */
+	u32 analog_reserved1[3];
+	u32 analog_pll_528_num;			/* 0x4050 */
+	u32 analog_reserved2[3];
+	u32 analog_pll_528_denom;		/* 0x4060 */
+	u32 analog_reserved3[3];
+	u32 analog_pll_audio;			/* 0x4070 */
+	u32 analog_pll_audio_set;
+	u32 analog_pll_audio_clr;
+	u32 analog_pll_audio_tog;
+	u32 analog_pll_audio_num;		/* 0x4080*/
+	u32 analog_reserved4[3];
+	u32 analog_pll_audio_denom;		/* 0x4090 */
+	u32 analog_reserved5[3];
+	u32 analog_pll_video;			/* 0x40a0 */
+	u32 analog_pll_video_set;
+	u32 analog_pll_video_clr;
+	u32 analog_pll_video_tog;
+	u32 analog_pll_video_num;		/* 0x40b0 */
+	u32 analog_reserved6[3];
+	u32 analog_pll_vedio_denon;		/* 0x40c0 */
+	u32 analog_reserved7[7];
+	u32 analog_pll_enet;			/* 0x40e0 */
+	u32 analog_pll_enet_set;
+	u32 analog_pll_enet_clr;
+	u32 analog_pll_enet_tog;
+	u32 analog_pfd_480;			/* 0x40f0 */
+	u32 analog_pfd_480_set;
+	u32 analog_pfd_480_clr;
+	u32 analog_pfd_480_tog;
+	u32 analog_pfd_528;			/* 0x4100 */
+	u32 analog_pfd_528_set;
+	u32 analog_pfd_528_clr;
+	u32 analog_pfd_528_tog;
+};
+#endif
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_RBC_EN				(1 << 27)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK			(0x3F << 21)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET		21
+#define MXC_CCM_CCR_WB_COUNT_MASK			0x7
+#define MXC_CCM_CCR_WB_COUNT_OFFSET			(1 << 16)
+#define MXC_CCM_CCR_COSC_EN				(1 << 12)
+#define MXC_CCM_CCR_OSCNT_MASK				0xFF
+#define MXC_CCM_CCR_OSCNT_OFFSET			0
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK			(1 << 16)
+#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK			(1 << 17)
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSC_READY				(1 << 5)
+#define MXC_CCM_CSR_REF_EN_B				(1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS			(1 << 15)
+#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS			(1 << 14)
+#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS			(1 << 13)
+#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS			(1 << 12)
+#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS			(1 << 11)
+#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS			(1 << 10)
+#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS			(1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL				(1 << 8)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL			(1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL			(1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL			(1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET			0
+#define MXC_CCM_CACRR_ARM_PODF_MASK			0x7
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK		(0x7 << 27)
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET		27
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL			(1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL			(1 << 25)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET		19
+#define MXC_CCM_CBCDR_AXI_PODF_MASK			(0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_PODF_OFFSET			16
+#define MXC_CCM_CBCDR_AHB_PODF_MASK			(0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET			10
+#define MXC_CCM_CBCDR_IPG_PODF_MASK			(0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET			8
+#define MXC_CCM_CBCDR_AXI_ALT_SEL			(1 << 7)
+#define MXC_CCM_CBCDR_AXI_SEL				(1 << 6)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET		3
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK		(0x7 << 0)
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET		0
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK		(0x7 << 29)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET		29
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK		(0x7 << 26)
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET		26
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		23
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	21
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL		(1 << 20)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK		(0x3 << 18)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET		18
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK		(0x3 << 16)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET		16
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET		12
+#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL			(1 << 11)
+#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL			(1 << 10)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	8
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
+#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL			(1 << 1)
+#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL			(1 << 0)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK		(0x3 << 29)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET		29
+#define MXC_CCM_CSCMR1_ACLK_EMI_MASK			(0x3 << 27)
+#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET			27
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET	23
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK		(0x7 << 20)
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET		20
+#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL			(1 << 19)
+#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL			(1 << 18)
+#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL			(1 << 17)
+#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL			(1 << 16)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET		14
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 10)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		10
+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK			0x3F
+
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK		(0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		19
+#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(1 << 11)
+#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3F << 2)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		2
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK		(0x7 << 25)
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET		25
+#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK			(0x7 << 22)
+#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET		22
+#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK			(0x7 << 19)
+#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET		19
+#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK			(0x7 << 16)
+#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET		16
+#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK			(0x7 << 11)
+#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET		11
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#ifdef CONFIG_MX6SL
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x1F
+#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
+#else
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
+#endif
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
+
+/* Define the bits in register CS1CDR */
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK		(0x3F << 25)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET		25
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK		(0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET		16
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK		(0x3 << 9)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET		9
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		6
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		0
+
+/* Define the bits in register CS2CDR */
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK		(0x3F << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET		21
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)			(((v) & 0x3f) << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		18
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)			(((v) & 0x7) << 18)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		12
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET		9
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET		6
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		0
+
+/* Define the bits in register CDCDR */
+#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK			(0x7 << 29)
+#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET		29
+#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL			(1 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET		25
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET		19
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK		(0x3 << 20)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET		20
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK		(0x7 << 12)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET		12
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK		(0x7 << 9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET		9
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK		(0x3 << 7)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET		7
+
+/* Define the bits in register CHSCCDR */
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET	15
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK		(0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET		12
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET		9
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET	6
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET		3
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET		0
+
+#define CHSCCDR_CLK_SEL_LDB_DI0				3
+#define CHSCCDR_PODF_DIVIDE_BY_3			2
+#define CHSCCDR_IPU_PRE_CLK_540M_PFD			5
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	15
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK		(0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET		12
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET		9
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET	6
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET		3
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK		0x7
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET		0
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET		16
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET		14
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK		(0x7 << 11)
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET		11
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK		(0x3 << 9)
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET		9
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
+#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY		(1 << 4)
+#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY		(1 << 3)
+#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY		(1 << 2)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY			(1 << 1)
+#define MXC_CCM_CDHIPR_AXI_PODF_BUSY			1
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_MASK_L2CC_IDLE			(1 << 27)
+#define MXC_CCM_CLPCR_MASK_SCU_IDLE			(1 << 26)
+#define MXC_CCM_CLPCR_MASK_CORE3_WFI			(1 << 25)
+#define MXC_CCM_CLPCR_MASK_CORE2_WFI			(1 << 24)
+#define MXC_CCM_CLPCR_MASK_CORE1_WFI			(1 << 23)
+#define MXC_CCM_CLPCR_MASK_CORE0_WFI			(1 << 22)
+#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS		(1 << 21)
+#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS		(1 << 19)
+#define MXC_CCM_CLPCR_WB_CORE_AT_LPM			(1 << 17)
+#define MXC_CCM_CLPCR_WB_PER_AT_LPM			(1 << 17)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN			(1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK			(0x3 << 9)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET			9
+#define MXC_CCM_CLPCR_VSTBY				(1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC			(1 << 7)
+#define MXC_CCM_CLPCR_SBYOS				(1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM		(1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK			(0x3 << 3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET		3
+#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY		(1 << 2)
+#define MXC_CCM_CLPCR_LPM_MASK				0x3
+#define MXC_CCM_CLPCR_LPM_OFFSET			0
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED			(1 << 26)
+#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED		(1 << 23)
+#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED		(1 << 22)
+#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED		(1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED			(1 << 20)
+#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED		(1 << 19)
+#define MXC_CCM_CISR_AXI_PODF_LOADED			(1 << 17)
+#define MXC_CCM_CISR_COSC_READY				(1 << 6)
+#define MXC_CCM_CISR_LRF_PLL				1
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED		(1 << 26)
+#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED		(1 << 23)
+#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED		(1 << 22)
+#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED		(1 << 21)
+#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED		(1 << 20)
+#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED	(1 << 22)
+#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED		(1 << 17)
+#define MXC_CCM_CIMR_MASK_COSC_READY			(1 << 6)
+#define MXC_CCM_CIMR_MASK_LRF_PLL			1
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET			(1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK			(0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET			21
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET			16
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK			(0x1F << 16)
+#define MXC_CCM_CCOSR_CKOL_EN				(0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK			(0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET			4
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK			0xF
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET			0
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(1 << 4)
+#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS			(1 << 2)
+#define MXC_CCM_CGPR_PMIC_DELAY_SCALER			1
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGR_CG_MASK				3
+
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			0
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			2
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA_OFFSET			4
+#define MXC_CCM_CCGR0_APBHDMA_MASK			(3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
+#define MXC_CCM_CCGR0_ASRC_OFFSET			6
+#define MXC_CCM_CCGR0_ASRC_MASK				(3 << MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET		8
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK		(3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET		10
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK		(3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET		12
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK		(3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_OFFSET			14
+#define MXC_CCM_CCGR0_CAN1_MASK				(3 << MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET		16
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK			(3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_OFFSET			18
+#define MXC_CCM_CCGR0_CAN2_MASK				(3 << MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET		20
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK			(3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET		22
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK		(3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_OFFSET			24
+#define MXC_CCM_CCGR0_DCIC1_MASK			(3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_OFFSET			26
+#define MXC_CCM_CCGR0_DCIC2_MASK			(3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
+#define MXC_CCM_CCGR0_DTCP_OFFSET			28
+#define MXC_CCM_CCGR0_DTCP_MASK				(3 << MXC_CCM_CCGR0_DTCP_OFFSET)
+
+#define MXC_CCM_CCGR1_ECSPI1S_OFFSET			0
+#define MXC_CCM_CCGR1_ECSPI1S_MASK			(3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_OFFSET			2
+#define MXC_CCM_CCGR1_ECSPI2S_MASK			(3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_OFFSET			4
+#define MXC_CCM_CCGR1_ECSPI3S_MASK			(3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_OFFSET			6
+#define MXC_CCM_CCGR1_ECSPI4S_MASK			(3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_OFFSET			8
+#define MXC_CCM_CCGR1_ECSPI5S_MASK			(3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET		10
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK		(3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR1_EPIT1S_OFFSET			12
+#define MXC_CCM_CCGR1_EPIT1S_MASK			(3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_OFFSET			14
+#define MXC_CCM_CCGR1_EPIT2S_MASK			(3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_OFFSET			16
+#define MXC_CCM_CCGR1_ESAIS_MASK			(3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_BUS_OFFSET			20
+#define MXC_CCM_CCGR1_GPT_BUS_MASK			(3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET			22
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK			(3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_GPU2D_OFFSET			24
+#define MXC_CCM_CCGR1_GPU2D_MASK			(3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
+#define MXC_CCM_CCGR1_GPU3D_OFFSET			26
+#define MXC_CCM_CCGR1_GPU3D_MASK			(3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
+
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET		0
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK		(3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET		4
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK		(3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET		6
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET		10
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET			12
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK			(3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET		14
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK		(3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_OFFSET			16
+#define MXC_CCM_CCGR2_IPMUX1_MASK			(3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_OFFSET			18
+#define MXC_CCM_CCGR2_IPMUX2_MASK			(3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_OFFSET			20
+#define MXC_CCM_CCGR2_IPMUX3_MASK			(3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET	22
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET	24
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET	26
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+
+#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET				0
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET			2
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET			4
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET				6
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET			8
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET			10
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_OFFSET				12
+#define MXC_CCM_CCGR3_LDB_DI0_MASK				(3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI1_OFFSET				14
+#define MXC_CCM_CCGR3_LDB_DI1_MASK				(3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET			16
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK			(3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#define MXC_CCM_CCGR3_MLB_OFFSET				18
+#define MXC_CCM_CCGR3_MLB_MASK					(3 << MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET	20
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK		(3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET	22
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK		(3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET		24
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET		26
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_OFFSET				28
+#define MXC_CCM_CCGR3_OCRAM_MASK				(3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
+#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET			30
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK				(3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+
+#define MXC_CCM_CCGR4_PCIE_OFFSET				0
+#define MXC_CCM_CCGR4_PCIE_MASK					(3 << MXC_CCM_CCGR4_PCIE_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET		8
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK			(3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET			12
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK			(3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET	14
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK	(3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_OFFSET				16
+#define MXC_CCM_CCGR4_PWM1_MASK					(3 << MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_OFFSET				18
+#define MXC_CCM_CCGR4_PWM2_MASK					(3 << MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_OFFSET				20
+#define MXC_CCM_CCGR4_PWM3_MASK					(3 << MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_OFFSET				22
+#define MXC_CCM_CCGR4_PWM4_MASK					(3 << MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET		24
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET	26
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET	28
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK	(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET		30
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+
+#define MXC_CCM_CCGR5_ROM_OFFSET			0
+#define MXC_CCM_CCGR5_ROM_MASK				(3 << MXC_CCM_CCGR5_ROM_OFFSET)
+#define MXC_CCM_CCGR5_SATA_OFFSET			4
+#define MXC_CCM_CCGR5_SATA_MASK				(3 << MXC_CCM_CCGR5_SATA_OFFSET)
+#define MXC_CCM_CCGR5_SDMA_OFFSET			6
+#define MXC_CCM_CCGR5_SDMA_MASK				(3 << MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_OFFSET			12
+#define MXC_CCM_CCGR5_SPBA_MASK				(3 << MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_OFFSET			14
+#define MXC_CCM_CCGR5_SPDIF_MASK			(3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_OFFSET			18
+#define MXC_CCM_CCGR5_SSI1_MASK				(3 << MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_OFFSET			20
+#define MXC_CCM_CCGR5_SSI2_MASK				(3 << MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_OFFSET			22
+#define MXC_CCM_CCGR5_SSI3_MASK				(3 << MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_UART_OFFSET			24
+#define MXC_CCM_CCGR5_UART_MASK				(3 << MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET		26
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK			(3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+
+#define MXC_CCM_CCGR6_USBOH3_OFFSET		0
+#define MXC_CCM_CCGR6_USBOH3_MASK		(3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET		2
+#define MXC_CCM_CCGR6_USDHC1_MASK		(3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET		4
+#define MXC_CCM_CCGR6_USDHC2_MASK		(3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_OFFSET		6
+#define MXC_CCM_CCGR6_USDHC3_MASK		(3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET		8
+#define MXC_CCM_CCGR6_USDHC4_MASK		(3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET		10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK		(3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET		12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK		(3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+
+#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
+#define BP_ANADIG_PLL_SYS_RSVD0      20
+#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
+#define BF_ANADIG_PLL_SYS_RSVD0(v)  \
+	(((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
+#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
+#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
+#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
+#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
+#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
+#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_SYS_DIV_SELECT      0
+#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_SYS_DIV_SELECT(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
+
+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
+#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1      17
+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
+#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v)  \
+	(((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC      14
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0      2
+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
+#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)  \
+	(((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT      0
+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
+#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)  \
+	(((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+
+#define BM_ANADIG_PLL_528_LOCK 0x80000000
+#define BP_ANADIG_PLL_528_RSVD1      19
+#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
+#define BF_ANADIG_PLL_528_RSVD1(v)  \
+	(((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
+#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_528_BYPASS 0x00010000
+#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_528_ENABLE 0x00002000
+#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_528_RSVD0      1
+#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
+#define BF_ANADIG_PLL_528_RSVD0(v)  \
+	(((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
+#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
+
+#define BP_ANADIG_PLL_528_SS_STOP      16
+#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
+#define BF_ANADIG_PLL_528_SS_STOP(v) \
+	(((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
+#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
+#define BP_ANADIG_PLL_528_SS_STEP      0
+#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
+#define BF_ANADIG_PLL_528_SS_STEP(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
+
+#define BP_ANADIG_PLL_528_NUM_RSVD0      30
+#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
+#define BP_ANADIG_PLL_528_NUM_A      0
+#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_NUM_A(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
+
+#define BP_ANADIG_PLL_528_DENOM_RSVD0      30
+#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
+#define BP_ANADIG_PLL_528_DENOM_B      0
+#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_DENOM_B(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
+
+#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
+#define BP_ANADIG_PLL_AUDIO_RSVD0      22
+#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
+#define BF_ANADIG_PLL_AUDIO_RSVD0(v)  \
+	(((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT      19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)  \
+	(((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT      0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0      30
+#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
+#define BP_ANADIG_PLL_AUDIO_NUM_A      0
+#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_NUM_A(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
+
+#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0      30
+#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
+#define BP_ANADIG_PLL_AUDIO_DENOM_B      0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
+#define BP_ANADIG_PLL_VIDEO_RSVD0      22
+#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
+#define BF_ANADIG_PLL_VIDEO_RSVD0(v)  \
+	(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT      19
+#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)  \
+	(((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT      0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0      30
+#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
+#define BP_ANADIG_PLL_VIDEO_NUM_A      0
+#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_NUM_A(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
+
+#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0      30
+#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
+#define BP_ANADIG_PLL_VIDEO_DENOM_B      0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
+#define BP_ANADIG_PLL_ENET_RSVD1      21
+#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
+#define BF_ANADIG_PLL_ENET_RSVD1(v)  \
+	(((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
+#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_ENET_RSVD0      2
+#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
+#define BF_ANADIG_PLL_ENET_RSVD0(v)  \
+	(((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT      0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_480_PFD3_FRAC      24
+#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_480_PFD3_FRAC(v)  \
+	(((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
+#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_480_PFD2_FRAC      16
+#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_480_PFD2_FRAC(v)  \
+	(((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
+#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_480_PFD1_FRAC      8
+#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_480_PFD1_FRAC(v)  \
+	(((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
+#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_480_PFD0_FRAC      0
+#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_480_PFD0_FRAC(v)  \
+	(((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
+
+#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_528_PFD3_FRAC      24
+#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_528_PFD3_FRAC(v)  \
+	(((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
+#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_528_PFD2_FRAC      16
+#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_528_PFD2_FRAC(v)  \
+	(((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
+#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_528_PFD1_FRAC      8
+#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_528_PFD1_FRAC(v)  \
+	(((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
+#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_528_PFD0_FRAC      0
+#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
+	(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
+
+#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h
new file mode 100644
index 000000000..e6640f39a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/gpio.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __ASM_ARCH_MX6_GPIO_H
+#define __ASM_ARCH_MX6_GPIO_H
+
+#include <asm/imx-common/gpio.h>
+
+#endif	/* __ASM_ARCH_MX6_GPIO_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/hab.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/hab.h
new file mode 100644
index 000000000..d724f206f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/hab.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+*/
+
+#ifndef __SECURE_MX6Q_H__
+#define __SECURE_MX6Q_H__
+
+#include <linux/types.h>
+
+/* -------- start of HAB API updates ------------*/
+/* The following are taken from HAB4 SIS */
+
+/* Status definitions */
+enum hab_status {
+	HAB_STS_ANY = 0x00,
+	HAB_FAILURE = 0x33,
+	HAB_WARNING = 0x69,
+	HAB_SUCCESS = 0xf0
+};
+
+/* Security Configuration definitions */
+enum hab_config {
+	HAB_CFG_RETURN = 0x33, /**< Field Return IC */
+	HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */
+	HAB_CFG_CLOSED = 0xcc /**< Secure IC */
+};
+
+/* State definitions */
+enum hab_state {
+	HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */
+	HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */
+	HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */
+	HAB_STATE_TRUSTED = 0x99, /**< Trusted state */
+	HAB_STATE_SECURE = 0xaa, /**< Secure state */
+	HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */
+	HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */
+	HAB_STATE_NONE = 0xf0, /**< No security state machine */
+	HAB_STATE_MAX
+};
+
+/*Function prototype description*/
+typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
+		uint8_t* , size_t*);
+typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
+		enum hab_state *);
+typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
+typedef enum hab_status hab_rvt_entry_t(void);
+typedef enum hab_status hab_rvt_exit_t(void);
+typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
+		void **, size_t *, hab_loader_callback_f_t);
+typedef void hapi_clock_init_t(void);
+
+#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
+#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
+#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
+#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
+#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D)
+
+#define HAB_CID_ROM 0 /**< ROM Caller ID */
+#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
+/* ----------- end of HAB API updates ------------*/
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h
new file mode 100644
index 000000000..1f19727b5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -0,0 +1,669 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
+#define __ASM_ARCH_MX6_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define ROMCP_ARB_BASE_ADDR             0x00000000
+#define ROMCP_ARB_END_ADDR              0x000FFFFF
+
+#ifdef CONFIG_MX6SL
+#define GPU_2D_ARB_BASE_ADDR            0x02200000
+#define GPU_2D_ARB_END_ADDR             0x02203FFF
+#define OPENVG_ARB_BASE_ADDR            0x02204000
+#define OPENVG_ARB_END_ADDR             0x02207FFF
+#else
+#define CAAM_ARB_BASE_ADDR              0x00100000
+#define CAAM_ARB_END_ADDR               0x00103FFF
+#define APBH_DMA_ARB_BASE_ADDR          0x00110000
+#define APBH_DMA_ARB_END_ADDR           0x00117FFF
+#define HDMI_ARB_BASE_ADDR              0x00120000
+#define HDMI_ARB_END_ADDR               0x00128FFF
+#define GPU_3D_ARB_BASE_ADDR            0x00130000
+#define GPU_3D_ARB_END_ADDR             0x00133FFF
+#define GPU_2D_ARB_BASE_ADDR            0x00134000
+#define GPU_2D_ARB_END_ADDR             0x00137FFF
+#define DTCP_ARB_BASE_ADDR              0x00138000
+#define DTCP_ARB_END_ADDR               0x0013BFFF
+#endif	/* CONFIG_MX6SL */
+
+#define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
+/* GPV - PL301 configuration ports */
+#ifdef CONFIG_MX6SL
+#define GPV2_BASE_ADDR                  0x00D00000
+#else
+#define GPV2_BASE_ADDR			0x00200000
+#endif
+
+#define GPV3_BASE_ADDR			0x00300000
+#define GPV4_BASE_ADDR			0x00800000
+#define IRAM_BASE_ADDR			0x00900000
+#define SCU_BASE_ADDR                   0x00A00000
+#define IC_INTERFACES_BASE_ADDR         0x00A00100
+#define GLOBAL_TIMER_BASE_ADDR          0x00A00200
+#define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
+#define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
+#define L2_PL310_BASE			0x00A02000
+#define GPV0_BASE_ADDR                  0x00B00000
+#define GPV1_BASE_ADDR                  0x00C00000
+#define PCIE_ARB_BASE_ADDR              0x01000000
+#define PCIE_ARB_END_ADDR               0x01FFFFFF
+
+#define AIPS1_ARB_BASE_ADDR             0x02000000
+#define AIPS1_ARB_END_ADDR              0x020FFFFF
+#define AIPS2_ARB_BASE_ADDR             0x02100000
+#define AIPS2_ARB_END_ADDR              0x021FFFFF
+#define SATA_ARB_BASE_ADDR              0x02200000
+#define SATA_ARB_END_ADDR               0x02203FFF
+#define OPENVG_ARB_BASE_ADDR            0x02204000
+#define OPENVG_ARB_END_ADDR             0x02207FFF
+#define HSI_ARB_BASE_ADDR               0x02208000
+#define HSI_ARB_END_ADDR                0x0220BFFF
+#define IPU1_ARB_BASE_ADDR              0x02400000
+#define IPU1_ARB_END_ADDR               0x027FFFFF
+#define IPU2_ARB_BASE_ADDR              0x02800000
+#define IPU2_ARB_END_ADDR               0x02BFFFFF
+#define WEIM_ARB_BASE_ADDR              0x08000000
+#define WEIM_ARB_END_ADDR               0x0FFFFFFF
+
+#ifdef CONFIG_MX6SL
+#define MMDC0_ARB_BASE_ADDR             0x80000000
+#define MMDC0_ARB_END_ADDR              0xFFFFFFFF
+#define MMDC1_ARB_BASE_ADDR             0xC0000000
+#define MMDC1_ARB_END_ADDR              0xFFFFFFFF
+#else
+#define MMDC0_ARB_BASE_ADDR             0x10000000
+#define MMDC0_ARB_END_ADDR              0x7FFFFFFF
+#define MMDC1_ARB_BASE_ADDR             0x80000000
+#define MMDC1_ARB_END_ADDR              0xFFFFFFFF
+#endif
+
+#define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
+#define IPU_SOC_OFFSET			0x00200000
+
+/* Defines for Blocks connected via AIPS (SkyBlue) */
+#define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
+#define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
+#define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
+#define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
+
+#define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
+#define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
+#define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
+#define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
+#define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
+#ifdef CONFIG_MX6SL
+#define UART5_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x18000)
+#define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
+#define UART2_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x30000)
+#define UART3_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x34000)
+#define UART4_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x38000)
+#else
+#define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
+#define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
+#define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
+#define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
+#endif
+
+#define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
+#define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
+#define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
+
+#define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
+#define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
+#define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
+#define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
+#define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
+#define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
+#define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
+#define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
+#define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
+#define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
+#define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
+#define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
+#define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
+#define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
+#define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
+#define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
+#define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
+#define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
+#define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
+#define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
+#define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
+#define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
+#define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
+#define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
+#define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
+#define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
+#define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
+#ifdef CONFIG_MX6SL
+#define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#else
+#define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#endif
+
+#define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
+#define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
+#define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
+#define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
+#ifdef CONFIG_MX6SL
+#define USBO2H_PL301_IPS_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USBO2H_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
+#else
+#define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
+#endif
+
+#define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
+#ifdef CONFIG_MX6SL
+#define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
+#else
+#define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
+#endif
+
+#define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
+#define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
+#define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
+#define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
+#define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
+#define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
+#define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
+#define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
+#define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
+#ifdef CONFIG_MX6SL
+#define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
+#else
+#define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
+#endif
+
+#define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
+#define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
+#define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
+#define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
+#define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
+#define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
+#define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
+#define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
+#define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
+#define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
+
+#define CHIP_REV_1_0                 0x10
+#define IRAM_SIZE                    0x00040000
+#define FEC_QUIRK_ENET_MAC
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32	scr;
+	u32	sbmr1;
+	u32	srsr;
+	u32	reserved1[2];
+	u32	sisr;
+	u32	simr;
+	u32     sbmr2;
+	u32     gpr1;
+	u32     gpr2;
+	u32     gpr3;
+	u32     gpr4;
+	u32     gpr5;
+	u32     gpr6;
+	u32     gpr7;
+	u32     gpr8;
+	u32     gpr9;
+	u32     gpr10;
+};
+
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET		21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK		(1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+
+/* GPR3 bitfields */
+#define IOMUXC_GPR3_GPU_DBG_OFFSET		29
+#define IOMUXC_GPR3_GPU_DBG_MASK		(3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET	28
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET	27
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET	26
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET	25
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_CTL_OFFSET		21
+#define IOMUXC_GPR3_OCRAM_CTL_MASK		(0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET		17
+#define IOMUXC_GPR3_OCRAM_STATUS_MASK		(0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET	16
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET	15
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET	14
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET	13
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET	12
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET	11
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_IPU_DIAG_OFFSET		10
+#define IOMUXC_GPR3_IPU_DIAG_MASK		(1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
+
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0	0
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1	1
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0	2
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1	3
+
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET	8
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET	6
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET		4
+#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET		2
+#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+
+
+struct iomuxc {
+	u32 gpr[14];
+	u32 omux[5];
+	/* mux and pad registers */
+};
+
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK			(7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
+
+#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET			15
+#define IOMUXC_GPR2_BGREF_RRMODE_MASK			(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES		(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES		(0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH	0
+#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW	1
+
+#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET		10
+#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET		9
+#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_BITMAP_SPWG	0
+#define IOMUXC_GPR2_BITMAP_JEIDA	1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET		8
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18	0
+#define IOMUXC_GPR2_DATA_WIDTH_24	1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET		7
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET		6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET		5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET		4
+#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK			(1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED	0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0	1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1	3
+
+#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET		2
+#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET		0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
+/* ECSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 cfg;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN	18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
+#define MXC_SPI_BASE_ADDRESSES \
+	ECSPI1_BASE_ADDR, \
+	ECSPI2_BASE_ADDR, \
+	ECSPI3_BASE_ADDR, \
+	ECSPI4_BASE_ADDR
+#else
+#define MXC_SPI_BASE_ADDRESSES \
+	ECSPI1_BASE_ADDR, \
+	ECSPI2_BASE_ADDR, \
+	ECSPI3_BASE_ADDR, \
+	ECSPI4_BASE_ADDR, \
+	ECSPI5_BASE_ADDR
+#endif
+
+struct ocotp_regs {
+	u32	ctrl;
+	u32	ctrl_set;
+	u32     ctrl_clr;
+	u32	ctrl_tog;
+	u32	timing;
+	u32     rsvd0[3];
+	u32     data;
+	u32     rsvd1[3];
+	u32     read_ctrl;
+	u32     rsvd2[3];
+	u32	read_fuse_data;
+	u32     rsvd3[3];
+	u32	sw_sticky;
+	u32     rsvd4[3];
+	u32     scs;
+	u32     scs_set;
+	u32     scs_clr;
+	u32     scs_tog;
+	u32     crc_addr;
+	u32     rsvd5[3];
+	u32     crc_value;
+	u32     rsvd6[3];
+	u32     version;
+	u32     rsvd7[0xdb];
+
+	struct fuse_bank {
+		u32	fuse_regs[0x20];
+	} bank[16];
+};
+
+struct fuse_bank0_regs {
+	u32	lock;
+	u32	rsvd0[3];
+	u32	uid_low;
+	u32	rsvd1[3];
+	u32	uid_high;
+	u32	rsvd2[3];
+	u32	rsvd3[4];
+	u32	rsvd4[4];
+	u32	rsvd5[4];
+	u32	cfg5;
+	u32	rsvd6[3];
+	u32	rsvd7[4];
+};
+
+struct fuse_bank4_regs {
+	u32	sjc_resp_low;
+	u32     rsvd0[3];
+	u32     sjc_resp_high;
+	u32     rsvd1[3];
+	u32	mac_addr_low;
+	u32     rsvd2[3];
+	u32     mac_addr_high;
+	u32	rsvd3[0xb];
+	u32	gp1;
+	u32	rsvd4[3];
+	u32	gp2;
+	u32	rsvd5[3];
+};
+
+struct aipstz_regs {
+	u32	mprot0;
+	u32	mprot1;
+	u32	rsvd[0xe];
+	u32	opacr0;
+	u32	opacr1;
+	u32	opacr2;
+	u32	opacr3;
+	u32	opacr4;
+};
+
+struct anatop_regs {
+	u32	pll_sys;		/* 0x000 */
+	u32	pll_sys_set;		/* 0x004 */
+	u32	pll_sys_clr;		/* 0x008 */
+	u32	pll_sys_tog;		/* 0x00c */
+	u32	usb1_pll_480_ctrl;	/* 0x010 */
+	u32	usb1_pll_480_ctrl_set;	/* 0x014 */
+	u32	usb1_pll_480_ctrl_clr;	/* 0x018 */
+	u32	usb1_pll_480_ctrl_tog;	/* 0x01c */
+	u32	usb2_pll_480_ctrl;	/* 0x020 */
+	u32	usb2_pll_480_ctrl_set;	/* 0x024 */
+	u32	usb2_pll_480_ctrl_clr;	/* 0x028 */
+	u32	usb2_pll_480_ctrl_tog;	/* 0x02c */
+	u32	pll_528;		/* 0x030 */
+	u32	pll_528_set;		/* 0x034 */
+	u32	pll_528_clr;		/* 0x038 */
+	u32	pll_528_tog;		/* 0x03c */
+	u32	pll_528_ss;		/* 0x040 */
+	u32	rsvd0[3];
+	u32	pll_528_num;		/* 0x050 */
+	u32	rsvd1[3];
+	u32	pll_528_denom;		/* 0x060 */
+	u32	rsvd2[3];
+	u32	pll_audio;		/* 0x070 */
+	u32	pll_audio_set;		/* 0x074 */
+	u32	pll_audio_clr;		/* 0x078 */
+	u32	pll_audio_tog;		/* 0x07c */
+	u32	pll_audio_num;		/* 0x080 */
+	u32	rsvd3[3];
+	u32	pll_audio_denom;	/* 0x090 */
+	u32	rsvd4[3];
+	u32	pll_video;		/* 0x0a0 */
+	u32	pll_video_set;		/* 0x0a4 */
+	u32	pll_video_clr;		/* 0x0a8 */
+	u32	pll_video_tog;		/* 0x0ac */
+	u32	pll_video_num;		/* 0x0b0 */
+	u32	rsvd5[3];
+	u32	pll_video_denom;	/* 0x0c0 */
+	u32	rsvd6[3];
+	u32	pll_mlb;		/* 0x0d0 */
+	u32	pll_mlb_set;		/* 0x0d4 */
+	u32	pll_mlb_clr;		/* 0x0d8 */
+	u32	pll_mlb_tog;		/* 0x0dc */
+	u32	pll_enet;		/* 0x0e0 */
+	u32	pll_enet_set;		/* 0x0e4 */
+	u32	pll_enet_clr;		/* 0x0e8 */
+	u32	pll_enet_tog;		/* 0x0ec */
+	u32	pfd_480;		/* 0x0f0 */
+	u32	pfd_480_set;		/* 0x0f4 */
+	u32	pfd_480_clr;		/* 0x0f8 */
+	u32	pfd_480_tog;		/* 0x0fc */
+	u32	pfd_528;		/* 0x100 */
+	u32	pfd_528_set;		/* 0x104 */
+	u32	pfd_528_clr;		/* 0x108 */
+	u32	pfd_528_tog;		/* 0x10c */
+	u32	reg_1p1;		/* 0x110 */
+	u32	reg_1p1_set;		/* 0x114 */
+	u32	reg_1p1_clr;		/* 0x118 */
+	u32	reg_1p1_tog;		/* 0x11c */
+	u32	reg_3p0;		/* 0x120 */
+	u32	reg_3p0_set;		/* 0x124 */
+	u32	reg_3p0_clr;		/* 0x128 */
+	u32	reg_3p0_tog;		/* 0x12c */
+	u32	reg_2p5;		/* 0x130 */
+	u32	reg_2p5_set;		/* 0x134 */
+	u32	reg_2p5_clr;		/* 0x138 */
+	u32	reg_2p5_tog;		/* 0x13c */
+	u32	reg_core;		/* 0x140 */
+	u32	reg_core_set;		/* 0x144 */
+	u32	reg_core_clr;		/* 0x148 */
+	u32	reg_core_tog;		/* 0x14c */
+	u32	ana_misc0;		/* 0x150 */
+	u32	ana_misc0_set;		/* 0x154 */
+	u32	ana_misc0_clr;		/* 0x158 */
+	u32	ana_misc0_tog;		/* 0x15c */
+	u32	ana_misc1;		/* 0x160 */
+	u32	ana_misc1_set;		/* 0x164 */
+	u32	ana_misc1_clr;		/* 0x168 */
+	u32	ana_misc1_tog;		/* 0x16c */
+	u32	ana_misc2;		/* 0x170 */
+	u32	ana_misc2_set;		/* 0x174 */
+	u32	ana_misc2_clr;		/* 0x178 */
+	u32	ana_misc2_tog;		/* 0x17c */
+	u32	tempsense0;		/* 0x180 */
+	u32	tempsense0_set;		/* 0x184 */
+	u32	tempsense0_clr;		/* 0x188 */
+	u32	tempsense0_tog;		/* 0x18c */
+	u32	tempsense1;		/* 0x190 */
+	u32	tempsense1_set;		/* 0x194 */
+	u32	tempsense1_clr;		/* 0x198 */
+	u32	tempsense1_tog;		/* 0x19c */
+	u32	usb1_vbus_detect;	/* 0x1a0 */
+	u32	usb1_vbus_detect_set;	/* 0x1a4 */
+	u32	usb1_vbus_detect_clr;	/* 0x1a8 */
+	u32	usb1_vbus_detect_tog;	/* 0x1ac */
+	u32	usb1_chrg_detect;	/* 0x1b0 */
+	u32	usb1_chrg_detect_set;	/* 0x1b4 */
+	u32	usb1_chrg_detect_clr;	/* 0x1b8 */
+	u32	usb1_chrg_detect_tog;	/* 0x1bc */
+	u32	usb1_vbus_det_stat;	/* 0x1c0 */
+	u32	usb1_vbus_det_stat_set;	/* 0x1c4 */
+	u32	usb1_vbus_det_stat_clr;	/* 0x1c8 */
+	u32	usb1_vbus_det_stat_tog;	/* 0x1cc */
+	u32	usb1_chrg_det_stat;	/* 0x1d0 */
+	u32	usb1_chrg_det_stat_set;	/* 0x1d4 */
+	u32	usb1_chrg_det_stat_clr;	/* 0x1d8 */
+	u32	usb1_chrg_det_stat_tog;	/* 0x1dc */
+	u32	usb1_loopback;		/* 0x1e0 */
+	u32	usb1_loopback_set;	/* 0x1e4 */
+	u32	usb1_loopback_clr;	/* 0x1e8 */
+	u32	usb1_loopback_tog;	/* 0x1ec */
+	u32	usb1_misc;		/* 0x1f0 */
+	u32	usb1_misc_set;		/* 0x1f4 */
+	u32	usb1_misc_clr;		/* 0x1f8 */
+	u32	usb1_misc_tog;		/* 0x1fc */
+	u32	usb2_vbus_detect;	/* 0x200 */
+	u32	usb2_vbus_detect_set;	/* 0x204 */
+	u32	usb2_vbus_detect_clr;	/* 0x208 */
+	u32	usb2_vbus_detect_tog;	/* 0x20c */
+	u32	usb2_chrg_detect;	/* 0x210 */
+	u32	usb2_chrg_detect_set;	/* 0x214 */
+	u32	usb2_chrg_detect_clr;	/* 0x218 */
+	u32	usb2_chrg_detect_tog;	/* 0x21c */
+	u32	usb2_vbus_det_stat;	/* 0x220 */
+	u32	usb2_vbus_det_stat_set;	/* 0x224 */
+	u32	usb2_vbus_det_stat_clr;	/* 0x228 */
+	u32	usb2_vbus_det_stat_tog;	/* 0x22c */
+	u32	usb2_chrg_det_stat;	/* 0x230 */
+	u32	usb2_chrg_det_stat_set;	/* 0x234 */
+	u32	usb2_chrg_det_stat_clr;	/* 0x238 */
+	u32	usb2_chrg_det_stat_tog;	/* 0x23c */
+	u32	usb2_loopback;		/* 0x240 */
+	u32	usb2_loopback_set;	/* 0x244 */
+	u32	usb2_loopback_clr;	/* 0x248 */
+	u32	usb2_loopback_tog;	/* 0x24c */
+	u32	usb2_misc;		/* 0x250 */
+	u32	usb2_misc_set;		/* 0x254 */
+	u32	usb2_misc_clr;		/* 0x258 */
+	u32	usb2_misc_tog;		/* 0x25c */
+	u32	digprog;		/* 0x260 */
+	u32	reserved1[7];
+	u32	digprog_sololite;	/* 0x280 */
+};
+
+#define ANATOP_PFD_FRAC_SHIFT(n)	((n)*8)
+#define ANATOP_PFD_FRAC_MASK(n)	(0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
+#define ANATOP_PFD_STABLE_SHIFT(n)	(6+((n)*8))
+#define ANATOP_PFD_STABLE_MASK(n)	(1<<ANATOP_PFD_STABLE_SHIFT(n))
+#define ANATOP_PFD_CLKGATE_SHIFT(n)	(7+((n)*8))
+#define ANATOP_PFD_CLKGATE_MASK(n)	(1<<ANATOP_PFD_CLKGATE_SHIFT(n))
+
+struct iomuxc_base_regs {
+	u32     gpr[14];        /* 0x000 */
+	u32     obsrv[5];       /* 0x038 */
+	u32     swmux_ctl[197]; /* 0x04c */
+	u32     swpad_ctl[250]; /* 0x360 */
+	u32     swgrp[26];      /* 0x748 */
+	u32     daisy[104];     /* 0x7b0..94c */
+};
+
+struct wdog_regs {
+	u16	wcr;	/* Control */
+	u16	wsr;	/* Service */
+	u16	wrsr;	/* Reset Status */
+	u16	wicr;	/* Interrupt Control */
+	u16	wmcr;	/* Miscellaneous Control */
+};
+
+#endif /* __ASSEMBLER__*/
+#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/iomux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/iomux.h
new file mode 100644
index 000000000..f9ee0d983
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/iomux.h
@@ -0,0 +1,160 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IOMUX_H__
+#define __ASM_ARCH_IOMUX_H__
+
+#define MX6_IOMUXC_GPR4		0x020e0010
+#define MX6_IOMUXC_GPR6		0x020e0018
+#define MX6_IOMUXC_GPR7		0x020e001c
+
+/*
+ * IOMUXC_GPR1 bit fields
+ */
+#define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR	(0<<13)
+#define IOMUXC_GPR1_OTG_ID_GPIO1	(1<<13)
+#define IOMUXC_GPR1_OTG_ID_MASK		(1<<13)
+#define IOMUXC_GPR1_REF_SSP_EN			(1 << 16)
+#define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
+
+/*
+ * IOMUXC_GPR8 bit fields
+ */
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK		(0x3f << 0)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET		0
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK	(0x3f << 6)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET	6
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK		(0x3f << 12)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET	12
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK		(0x7f << 18)
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET		18
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK		(0x7f << 25)
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET		25
+
+/*
+ * IOMUXC_GPR12 bit fields
+ */
+#define IOMUXC_GPR12_LOS_LEVEL_9		(0x9 << 4)
+#define IOMUXC_GPR12_LOS_LEVEL_MASK		(0x1f << 4)
+#define IOMUXC_GPR12_APPS_LTSSM_ENABLE		(1 << 10)
+#define IOMUXC_GPR12_DEVICE_TYPE_EP		(0x0 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x2 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_MASK		(0xf << 12)
+
+/*
+ * IOMUXC_GPR13 bit fields
+ */
+#define IOMUXC_GPR13_SDMA_STOP_REQ	(1<<30)
+#define IOMUXC_GPR13_CAN2_STOP_REQ	(1<<29)
+#define IOMUXC_GPR13_CAN1_STOP_REQ	(1<<28)
+#define IOMUXC_GPR13_ENET_STOP_REQ	(1<<27)
+#define IOMUXC_GPR13_SATA_PHY_8_MASK	(7<<24)
+#define IOMUXC_GPR13_SATA_PHY_7_MASK	(0x1f<<19)
+#define IOMUXC_GPR13_SATA_PHY_6_SHIFT	16
+#define IOMUXC_GPR13_SATA_PHY_6_MASK	(7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+#define IOMUXC_GPR13_SATA_SPEED_MASK	(1<<15)
+#define IOMUXC_GPR13_SATA_PHY_5_MASK	(1<<14)
+#define IOMUXC_GPR13_SATA_PHY_4_MASK	(7<<11)
+#define IOMUXC_GPR13_SATA_PHY_3_MASK	(0x1f<<7)
+#define IOMUXC_GPR13_SATA_PHY_2_MASK	(0x1f<<2)
+#define IOMUXC_GPR13_SATA_PHY_1_MASK	(3<<0)
+
+#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
+#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+#define IOMUX_GPR1_FEC_MASK    (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
+				| IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
+
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB	(0<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB	(1<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB	(2<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB	(3<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB	(4<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB	(5<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB	(6<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB	(7<<24)
+
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1I	(0x10<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1M	(0x10<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1X	(0x1A<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2I	(0x12<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2M	(0x12<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2X	(0x1A<<19)
+
+#define IOMUXC_GPR13_SATA_SPEED_1P5G	(0<<15)
+#define IOMUXC_GPR13_SATA_SPEED_3G	(1<<15)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED	(0<<14)
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED		(1<<14)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16	(0<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16	(1<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16	(2<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16	(3<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16		(4<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16		(5<<11)
+
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB	(0<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB	(1<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB	(2<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB	(3<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB	(4<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB	(5<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB	(6<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB	(7<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB	(8<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB	(9<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB	(0xA<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB	(0xB<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB	(0xC<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB	(0xD<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB	(0xE<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB	(0xF<<7)
+
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V	(0<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V	(1<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V	(2<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V	(3<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V	(4<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V	(5<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V	(6<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V	(7<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V	(8<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V	(9<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V	(0xA<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V	(0xB<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V	(0xC<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V	(0xD<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V	(0xE<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V	(0xF<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V	(0x10<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V	(0x11<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V	(0x12<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V	(0x13<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V	(0x14<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V	(0x15<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V	(0x16<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V	(0x17<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V	(0x18<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V	(0x19<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V	(0x1A<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V	(0x1B<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V	(0x1C<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V	(0x1D<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V	(0x1E<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V	(0x1F<<2)
+
+#define IOMUXC_GPR13_SATA_PHY_1_FAST	0
+#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM	1
+#define IOMUXC_GPR13_SATA_PHY_1_SLOW	2
+
+#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
+				|IOMUXC_GPR13_SATA_PHY_7_MASK \
+				|IOMUXC_GPR13_SATA_PHY_6_MASK \
+				|IOMUXC_GPR13_SATA_SPEED_MASK \
+				|IOMUXC_GPR13_SATA_PHY_5_MASK \
+				|IOMUXC_GPR13_SATA_PHY_4_MASK \
+				|IOMUXC_GPR13_SATA_PHY_3_MASK \
+				|IOMUXC_GPR13_SATA_PHY_2_MASK \
+				|IOMUXC_GPR13_SATA_PHY_1_MASK)
+#endif	/* __ASM_ARCH_IOMUX_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-ddr.h
new file mode 100644
index 000000000..43d377af3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARCH_MX6_DDR_H__
+#define __ASM_ARCH_MX6_DDR_H__
+
+#ifdef CONFIG_MX6Q
+#include "mx6q-ddr.h"
+#else
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#include "mx6dl-ddr.h"
+#else
+#error "Please select cpu"
+#endif	/* CONFIG_MX6DL or CONFIG_MX6S */
+#endif	/* CONFIG_MX6Q */
+
+#define MX6_MMDC_P0_MDCTL	0x021b0000
+#define MX6_MMDC_P0_MDPDC	0x021b0004
+#define MX6_MMDC_P0_MDOTC	0x021b0008
+#define MX6_MMDC_P0_MDCFG0	0x021b000c
+#define MX6_MMDC_P0_MDCFG1	0x021b0010
+#define MX6_MMDC_P0_MDCFG2	0x021b0014
+#define MX6_MMDC_P0_MDMISC	0x021b0018
+#define MX6_MMDC_P0_MDSCR	0x021b001c
+#define MX6_MMDC_P0_MDREF	0x021b0020
+#define MX6_MMDC_P0_MDRWD	0x021b002c
+#define MX6_MMDC_P0_MDOR	0x021b0030
+#define MX6_MMDC_P0_MDASP	0x021b0040
+#define MX6_MMDC_P0_MAPSR	0x021b0404
+#define MX6_MMDC_P0_MPZQHWCTRL	0x021b0800
+#define MX6_MMDC_P0_MPWLDECTRL0	0x021b080c
+#define MX6_MMDC_P0_MPWLDECTRL1	0x021b0810
+#define MX6_MMDC_P0_MPODTCTRL	0x021b0818
+#define MX6_MMDC_P0_MPRDDQBY0DL	0x021b081c
+#define MX6_MMDC_P0_MPRDDQBY1DL	0x021b0820
+#define MX6_MMDC_P0_MPRDDQBY2DL	0x021b0824
+#define MX6_MMDC_P0_MPRDDQBY3DL	0x021b0828
+#define MX6_MMDC_P0_MPDGCTRL0	0x021b083c
+#define MX6_MMDC_P0_MPDGCTRL1	0x021b0840
+#define MX6_MMDC_P0_MPRDDLCTL	0x021b0848
+#define MX6_MMDC_P0_MPWRDLCTL	0x021b0850
+#define MX6_MMDC_P0_MPMUR0	0x021b08b8
+
+#define MX6_MMDC_P1_MDCTL	0x021b4000
+#define MX6_MMDC_P1_MDPDC	0x021b4004
+#define MX6_MMDC_P1_MDOTC	0x021b4008
+#define MX6_MMDC_P1_MDCFG0	0x021b400c
+#define MX6_MMDC_P1_MDCFG1	0x021b4010
+#define MX6_MMDC_P1_MDCFG2	0x021b4014
+#define MX6_MMDC_P1_MDMISC	0x021b4018
+#define MX6_MMDC_P1_MDSCR	0x021b401c
+#define MX6_MMDC_P1_MDREF	0x021b4020
+#define MX6_MMDC_P1_MDRWD	0x021b402c
+#define MX6_MMDC_P1_MDOR	0x021b4030
+#define MX6_MMDC_P1_MDASP	0x021b4040
+#define MX6_MMDC_P1_MAPSR	0x021b4404
+#define MX6_MMDC_P1_MPZQHWCTRL	0x021b4800
+#define MX6_MMDC_P1_MPWLDECTRL0	0x021b480c
+#define MX6_MMDC_P1_MPWLDECTRL1	0x021b4810
+#define MX6_MMDC_P1_MPODTCTRL	0x021b4818
+#define MX6_MMDC_P1_MPRDDQBY0DL	0x021b481c
+#define MX6_MMDC_P1_MPRDDQBY1DL	0x021b4820
+#define MX6_MMDC_P1_MPRDDQBY2DL	0x021b4824
+#define MX6_MMDC_P1_MPRDDQBY3DL	0x021b4828
+#define MX6_MMDC_P1_MPDGCTRL0	0x021b483c
+#define MX6_MMDC_P1_MPDGCTRL1	0x021b4840
+#define MX6_MMDC_P1_MPRDDLCTL	0x021b4848
+#define MX6_MMDC_P1_MPWRDLCTL	0x021b4850
+#define MX6_MMDC_P1_MPMUR0	0x021b48b8
+
+#endif	/*__ASM_ARCH_MX6_DDR_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-pins.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-pins.h
new file mode 100644
index 000000000..dcd7f8f32
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARCH_MX6_PINS_H__
+#define __ASM_ARCH_MX6_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
+	prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
+
+#ifdef CONFIG_MX6QDL
+enum {
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),
+#include "mx6q_pins.h"
+#undef MX6_PAD_DECL
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
+#include "mx6dl_pins.h"
+};
+#elif defined(CONFIG_MX6Q)
+enum {
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
+#include "mx6q_pins.h"
+};
+#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+enum {
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
+#include "mx6dl_pins.h"
+};
+#elif defined(CONFIG_MX6SL)
+#include "mx6sl_pins.h"
+#else
+#error "Please select cpu"
+#endif	/* CONFIG_MX6Q */
+
+#endif	/*__ASM_ARCH_MX6_PINS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
new file mode 100644
index 000000000..1eb4b3c8b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARCH_MX6DLS_DDR_H__
+#define __ASM_ARCH_MX6DLS_DDR_H__
+
+#ifndef CONFIG_MX6DL
+#ifndef CONFIG_MX6S
+#error "wrong CPU"
+#endif
+#endif
+
+#define MX6_IOM_DRAM_DQM0	0x020e0470
+#define MX6_IOM_DRAM_DQM1	0x020e0474
+#define MX6_IOM_DRAM_DQM2	0x020e0478
+#define MX6_IOM_DRAM_DQM3	0x020e047c
+#define MX6_IOM_DRAM_DQM4	0x020e0480
+#define MX6_IOM_DRAM_DQM5	0x020e0484
+#define MX6_IOM_DRAM_DQM6	0x020e0488
+#define MX6_IOM_DRAM_DQM7	0x020e048c
+
+#define MX6_IOM_DRAM_CAS	0x020e0464
+#define MX6_IOM_DRAM_RAS	0x020e0490
+#define MX6_IOM_DRAM_RESET	0x020e0494
+#define MX6_IOM_DRAM_SDCLK_0	0x020e04ac
+#define MX6_IOM_DRAM_SDCLK_1	0x020e04b0
+#define MX6_IOM_DRAM_SDBA2	0x020e04a0
+#define MX6_IOM_DRAM_SDCKE0	0x020e04a4
+#define MX6_IOM_DRAM_SDCKE1	0x020e04a8
+#define MX6_IOM_DRAM_SDODT0	0x020e04b4
+#define MX6_IOM_DRAM_SDODT1	0x020e04b8
+
+#define MX6_IOM_DRAM_SDQS0	0x020e04bc
+#define MX6_IOM_DRAM_SDQS1	0x020e04c0
+#define MX6_IOM_DRAM_SDQS2	0x020e04c4
+#define MX6_IOM_DRAM_SDQS3	0x020e04c8
+#define MX6_IOM_DRAM_SDQS4	0x020e04cc
+#define MX6_IOM_DRAM_SDQS5	0x020e04d0
+#define MX6_IOM_DRAM_SDQS6	0x020e04d4
+#define MX6_IOM_DRAM_SDQS7	0x020e04d8
+
+#define MX6_IOM_GRP_B0DS	0x020e0764
+#define MX6_IOM_GRP_B1DS	0x020e0770
+#define MX6_IOM_GRP_B2DS	0x020e0778
+#define MX6_IOM_GRP_B3DS	0x020e077c
+#define MX6_IOM_GRP_B4DS	0x020e0780
+#define MX6_IOM_GRP_B5DS	0x020e0784
+#define MX6_IOM_GRP_B6DS	0x020e078c
+#define MX6_IOM_GRP_B7DS	0x020e0748
+#define MX6_IOM_GRP_ADDDS	0x020e074c
+#define MX6_IOM_DDRMODE_CTL	0x020e0750
+#define MX6_IOM_GRP_DDRPKE	0x020e0754
+#define MX6_IOM_GRP_DDRMODE	0x020e0760
+#define MX6_IOM_GRP_CTLDS	0x020e076c
+#define MX6_IOM_GRP_DDR_TYPE	0x020e0774
+
+#endif	/*__ASM_ARCH_MX6S_DDR_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
new file mode 100644
index 000000000..2e414adf3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -0,0 +1,1080 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__
+#define __ASM_ARCH_MX6_MX6DL_PINS_H__
+
+MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10,	0x0360, 0x004C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC,	0x0360, 0x004C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO,	0x0360, 0x004C, 2, 0x07F8, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA,	0x0360, 0x004C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA,	0x0360, 0x004C, 3, 0x08FC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28,	0x0360, 0x004C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07,	0x0360, 0x004C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11,	0x0364, 0x0050, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS,	0x0364, 0x0050, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0,	0x0364, 0x0050, 2, 0x0800, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA,	0x0364, 0x0050, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA,	0x0364, 0x0050, 3, 0x08FC, 1, 0)
+MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29,	0x0364, 0x0050, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08,	0x0364, 0x0050, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12,	0x0368, 0x0054, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08,	0x0368, 0x0054, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA,	0x0368, 0x0054, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA,	0x0368, 0x0054, 3, 0x0914, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30,	0x0368, 0x0054, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09,	0x0368, 0x0054, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13,	0x036C, 0x0058, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09,	0x036C, 0x0058, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA,	0x036C, 0x0058, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA,	0x036C, 0x0058, 3, 0x0914, 1, 0)
+MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31,	0x036C, 0x0058, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10,	0x036C, 0x0058, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14,	0x0370, 0x005C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10,	0x0370, 0x005C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA,	0x0370, 0x005C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA,	0x0370, 0x005C, 3, 0x091C, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00,	0x0370, 0x005C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11,	0x0370, 0x005C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15,	0x0374, 0x0060, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11,	0x0374, 0x0060, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA,	0x0374, 0x0060, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA,	0x0374, 0x0060, 3, 0x091C, 1, 0)
+MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01,	0x0374, 0x0060, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12,	0x0374, 0x0060, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16,	0x0378, 0x0064, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12,	0x0378, 0x0064, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B,	0x0378, 0x0064, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B,	0x0378, 0x0064, 3, 0x0910, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02,	0x0378, 0x0064, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13,	0x0378, 0x0064, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17,	0x037C, 0x0068, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13,	0x037C, 0x0068, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B,	0x037C, 0x0068, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B,	0x037C, 0x0068, 3, 0x0910, 1, 0)
+MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03,	0x037C, 0x0068, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14,	0x037C, 0x0068, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18,	0x0380, 0x006C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14,	0x0380, 0x006C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B,	0x0380, 0x006C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B,	0x0380, 0x006C, 3, 0x0918, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04,	0x0380, 0x006C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15,	0x0380, 0x006C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19,	0x0384, 0x0070, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15,	0x0384, 0x0070, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B,	0x0384, 0x0070, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B,	0x0384, 0x0070, 3, 0x0918, 1, 0)
+MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05,	0x0384, 0x0070, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04,	0x0388, 0x0074, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02,	0x0388, 0x0074, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK,	0x0388, 0x0074, 2, 0x07D8, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__KEY_COL5,	0x0388, 0x0074, 3, 0x08C0, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC,	0x0388, 0x0074, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22,	0x0388, 0x0074, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01,	0x0388, 0x0074, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05,	0x038C, 0x0078, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03,	0x038C, 0x0078, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI,	0x038C, 0x0078, 2, 0x07E0, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5,	0x038C, 0x0078, 3, 0x08CC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD,	0x038C, 0x0078, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23,	0x038C, 0x0078, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02,	0x038C, 0x0078, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06,	0x0390, 0x007C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04,	0x0390, 0x007C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO,	0x0390, 0x007C, 2, 0x07DC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__KEY_COL6,	0x0390, 0x007C, 3, 0x08C4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS,	0x0390, 0x007C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24,	0x0390, 0x007C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03,	0x0390, 0x007C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07,	0x0394, 0x0080, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05,	0x0394, 0x0080, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0,	0x0394, 0x0080, 2, 0x07E4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6,	0x0394, 0x0080, 3, 0x08D0, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD,	0x0394, 0x0080, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25,	0x0394, 0x0080, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04,	0x0394, 0x0080, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08,	0x0398, 0x0084, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06,	0x0398, 0x0084, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK,	0x0398, 0x0084, 2, 0x07F4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__KEY_COL7,	0x0398, 0x0084, 3, 0x08C8, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA,	0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26,	0x0398, 0x0084, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05,	0x0398, 0x0084, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09,	0x039C, 0x0088, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07,	0x039C, 0x0088, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI,	0x039C, 0x0088, 2, 0x07FC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7,	0x039C, 0x0088, 3, 0x08D4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL,	0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27,	0x039C, 0x0088, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06,	0x039C, 0x0088, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN,	0x03A0, 0x008C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00,	0x03A0, 0x008C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20,	0x03A0, 0x008C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK,	0x03A0, 0x008C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC,	0x03A4, 0x0090, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1,	0x03A4, 0x0090, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19,	0x03A4, 0x0090, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL,	0x03A4, 0x0090, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK,	0x03A8, 0x0094, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18,	0x03A8, 0x0094, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO,	0x03A8, 0x0094, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC,	0x03AC, 0x0098, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01,	0x03AC, 0x0098, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21,	0x03AC, 0x0098, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00,	0x03AC, 0x0098, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_DISP_CLK__LCD_CLK,	0x03B0, 0x009C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16,	0x03B0, 0x009C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__LCD_WR_RWN,	0x03B0, 0x009C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15,	0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN15__LCD_ENABLE,	0x03B4, 0x00A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__AUD6_TXC,	0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17,	0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__LCD_RD_E,	0x03B4, 0x00A0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02,	0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN2__LCD_HSYNC,	0x03B8, 0x00A4, 1, 0x08D8, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__AUD6_TXD,	0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18,	0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__LCD_RS,	0x03B8, 0x00A4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03,	0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN3__LCD_VSYNC,	0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS,	0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19,	0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__LCD_CS,	0x03BC, 0x00A8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04,	0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN4__LCD_BUSY,	0x03C0, 0x00AC, 1, 0x08D8, 1, 0)
+MX6_PAD_DECL(DI0_PIN4__AUD6_RXD,	0x03C0, 0x00AC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__SD1_WP,	0x03C0, 0x00AC, 3, 0x092C, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20,	0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__LCD_RESET,	0x03C0, 0x00AC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00,	0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT0__LCD_DATA00,	0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK,	0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21,	0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01,	0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01,	0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI,	0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22,	0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10,	0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10,	0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31,	0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11,	0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT11__LCD_DATA11,	0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05,	0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12,	0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT12__LCD_DATA12,	0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06,	0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13,	0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT13__LCD_DATA13,	0x03D8, 0x00C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS,	0x03D8, 0x00C4, 3, 0x07BC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07,	0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14,	0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT14__LCD_DATA14,	0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC,	0x03DC, 0x00C8, 3, 0x07B8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08,	0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15,	0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT15__LCD_DATA15,	0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1,	0x03E0, 0x00CC, 2, 0x07E8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1,	0x03E0, 0x00CC, 3, 0x0804, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09,	0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16,	0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT16__LCD_DATA16,	0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI,	0x03E4, 0x00D0, 2, 0x07FC, 1, 0)
+MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC,	0x03E4, 0x00D0, 3, 0x07C0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0,	0x03E4, 0x00D0, 4, 0x08E8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10,	0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17,	0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT17__LCD_DATA17,	0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO,	0x03E8, 0x00D4, 2, 0x07F8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD,	0x03E8, 0x00D4, 3, 0x07B4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1,	0x03E8, 0x00D4, 4, 0x08EC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11,	0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18,	0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT18__LCD_DATA18,	0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0,	0x03EC, 0x00D8, 2, 0x0800, 1, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS,	0x03EC, 0x00D8, 3, 0x07C4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS,	0x03EC, 0x00D8, 4, 0x07A4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12,	0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B,	0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19,	0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT19__LCD_DATA19,	0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK,	0x03F0, 0x00DC, 2, 0x07F4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD,	0x03F0, 0x00DC, 3, 0x07B0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC,	0x03F0, 0x00DC, 4, 0x07A0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13,	0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B,	0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02,	0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02,	0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO,	0x03F4, 0x00E0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23,	0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20,	0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT20__LCD_DATA20,	0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK,	0x03F8, 0x00E4, 2, 0x07D8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC,	0x03F8, 0x00E4, 3, 0x07A8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14,	0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21,	0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT21__LCD_DATA21,	0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI,	0x03FC, 0x00E8, 2, 0x07E0, 1, 0)
+MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD,	0x03FC, 0x00E8, 3, 0x079C, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15,	0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22,	0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT22__LCD_DATA22,	0x0400, 0x00EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO,	0x0400, 0x00EC, 2, 0x07DC, 1, 0)
+MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS,	0x0400, 0x00EC, 3, 0x07AC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16,	0x0400, 0x00EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23,	0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT23__LCD_DATA23,	0x0404, 0x00F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0,	0x0404, 0x00F0, 2, 0x07E4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD,	0x0404, 0x00F0, 3, 0x0798, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17,	0x0404, 0x00F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03,	0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT3__LCD_DATA03,	0x0408, 0x00F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0,	0x0408, 0x00F4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24,	0x0408, 0x00F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04,	0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT4__LCD_DATA04,	0x040C, 0x00F8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1,	0x040C, 0x00F8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25,	0x040C, 0x00F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05,	0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT5__LCD_DATA05,	0x0410, 0x00FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2,	0x0410, 0x00FC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS,	0x0410, 0x00FC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26,	0x0410, 0x00FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06,	0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT6__LCD_DATA06,	0x0414, 0x0100, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3,	0x0414, 0x0100, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC,	0x0414, 0x0100, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27,	0x0414, 0x0100, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07,	0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT7__LCD_DATA07,	0x0418, 0x0104, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY,	0x0418, 0x0104, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28,	0x0418, 0x0104, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08,	0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT8__LCD_DATA08,	0x041C, 0x0108, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT,	0x041C, 0x0108, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__WDOG1_B,	0x041C, 0x0108, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29,	0x041C, 0x0108, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09,	0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT9__LCD_DATA09,	0x0420, 0x010C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT,	0x0420, 0x010C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__WDOG2_B,	0x0420, 0x010C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30,	0x0420, 0x010C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__EIM_ADDR16,	0x04E0, 0x0110, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK,	0x04E0, 0x0110, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU1_CSI1_PIXCLK,	0x04E0, 0x0110, 2, 0x08B8, 0, 0)
+MX6_PAD_DECL(EIM_A16__GPIO2_IO22,	0x04E0, 0x0110, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16,	0x04E0, 0x0110, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__EPDC_DATA00,	0x04E0, 0x0110, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__EIM_ADDR17,	0x04E4, 0x0114, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12,	0x04E4, 0x0114, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU1_CSI1_DATA12,	0x04E4, 0x0114, 2, 0x0890, 0, 0)
+MX6_PAD_DECL(EIM_A17__GPIO2_IO21,	0x04E4, 0x0114, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17,	0x04E4, 0x0114, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__EPDC_PWR_STAT,	0x04E4, 0x0114, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__EIM_ADDR18,	0x04E8, 0x0118, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13,	0x04E8, 0x0118, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU1_CSI1_DATA13,	0x04E8, 0x0118, 2, 0x0894, 0, 0)
+MX6_PAD_DECL(EIM_A18__GPIO2_IO20,	0x04E8, 0x0118, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18,	0x04E8, 0x0118, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__EPDC_PWR_CTRL0,	0x04E8, 0x0118, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__EIM_ADDR19,	0x04EC, 0x011C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14,	0x04EC, 0x011C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU1_CSI1_DATA14,	0x04EC, 0x011C, 2, 0x0898, 0, 0)
+MX6_PAD_DECL(EIM_A19__GPIO2_IO19,	0x04EC, 0x011C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19,	0x04EC, 0x011C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__EPDC_PWR_CTRL1,	0x04EC, 0x011C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__EIM_ADDR20,	0x04F0, 0x0120, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15,	0x04F0, 0x0120, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU1_CSI1_DATA15,	0x04F0, 0x0120, 2, 0x089C, 0, 0)
+MX6_PAD_DECL(EIM_A20__GPIO2_IO18,	0x04F0, 0x0120, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20,	0x04F0, 0x0120, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__EPDC_PWR_CTRL2,	0x04F0, 0x0120, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__EIM_ADDR21,	0x04F4, 0x0124, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16,	0x04F4, 0x0124, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU1_CSI1_DATA16,	0x04F4, 0x0124, 2, 0x08A0, 0, 0)
+MX6_PAD_DECL(EIM_A21__GPIO2_IO17,	0x04F4, 0x0124, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21,	0x04F4, 0x0124, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__EPDC_GDCLK,	0x04F4, 0x0124, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__EIM_ADDR22,	0x04F8, 0x0128, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17,	0x04F8, 0x0128, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU1_CSI1_DATA17,	0x04F8, 0x0128, 2, 0x08A4, 0, 0)
+MX6_PAD_DECL(EIM_A22__GPIO2_IO16,	0x04F8, 0x0128, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22,	0x04F8, 0x0128, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__EPDC_GDSP,	0x04F8, 0x0128, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__EIM_ADDR23,	0x04FC, 0x012C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18,	0x04FC, 0x012C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_CSI1_DATA18,	0x04FC, 0x012C, 2, 0x08A8, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_SISG3,	0x04FC, 0x012C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__GPIO6_IO06,	0x04FC, 0x012C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23,	0x04FC, 0x012C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__EPDC_GDOE,	0x04FC, 0x012C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__EIM_ADDR24,	0x0500, 0x0130, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19,	0x0500, 0x0130, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_CSI1_DATA19,	0x0500, 0x0130, 2, 0x08AC, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_SISG2,	0x0500, 0x0130, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__GPIO5_IO04,	0x0500, 0x0130, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24,	0x0500, 0x0130, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__EPDC_GDRL,	0x0500, 0x0130, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__EIM_ADDR25,	0x0504, 0x0134, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI4_SS1,	0x0504, 0x0134, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI2_RDY,	0x0504, 0x0134, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12,	0x0504, 0x0134, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS,	0x0504, 0x0134, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__GPIO5_IO02,	0x0504, 0x0134, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE,	0x0504, 0x0134, 6, 0x085C, 0, 0)
+MX6_PAD_DECL(EIM_A25__EPDC_DATA15,	0x0504, 0x0134, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__EIM_ACLK_FREERUN,	0x0504, 0x0134, 9, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__EIM_BCLK,	0x0508, 0x0138, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16,	0x0508, 0x0138, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31,	0x0508, 0x0138, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__EPDC_SDCE9,	0x0508, 0x0138, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__EIM_CS0_B,	0x050C, 0x013C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05,	0x050C, 0x013C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK,	0x050C, 0x013C, 2, 0x07F4, 2, 0)
+MX6_PAD_DECL(EIM_CS0__GPIO2_IO23,	0x050C, 0x013C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__EPDC_DATA06,	0x050C, 0x013C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__EIM_CS1_B,	0x0510, 0x0140, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06,	0x0510, 0x0140, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI,	0x0510, 0x0140, 2, 0x07FC, 2, 0)
+MX6_PAD_DECL(EIM_CS1__GPIO2_IO24,	0x0510, 0x0140, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__EPDC_DATA08,	0x0510, 0x0140, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__EIM_DATA16,	0x0514, 0x0144, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK,	0x0514, 0x0144, 1, 0x07D8, 2, 0)
+MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05,	0x0514, 0x0144, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__IPU1_CSI1_DATA18,	0x0514, 0x0144, 3, 0x08A8, 1, 0)
+MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA,	0x0514, 0x0144, 4, 0x0864, 0, 0)
+MX6_PAD_DECL(EIM_D16__GPIO3_IO16,	0x0514, 0x0144, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__I2C2_SDA,	0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0)
+MX6_PAD_DECL(EIM_D16__EPDC_DATA10,	0x0514, 0x0144, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__EIM_DATA17,	0x0518, 0x0148, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__ECSPI1_MISO,	0x0518, 0x0148, 1, 0x07DC, 2, 0)
+MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06,	0x0518, 0x0148, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__IPU1_CSI1_PIXCLK,	0x0518, 0x0148, 3, 0x08B8, 1, 0)
+MX6_PAD_DECL(EIM_D17__DCIC1_OUT,	0x0518, 0x0148, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__GPIO3_IO17,	0x0518, 0x0148, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__I2C3_SCL,	0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0)
+MX6_PAD_DECL(EIM_D17__EPDC_VCOM0,	0x0518, 0x0148, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__EIM_DATA18,	0x051C, 0x014C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI,	0x051C, 0x014C, 1, 0x07E0, 2, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07,	0x051C, 0x014C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_CSI1_DATA17,	0x051C, 0x014C, 3, 0x08A4, 1, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS,	0x051C, 0x014C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__GPIO3_IO18,	0x051C, 0x014C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__I2C3_SDA,	0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0)
+MX6_PAD_DECL(EIM_D18__EPDC_VCOM1,	0x051C, 0x014C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EIM_DATA19,	0x0520, 0x0150, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__ECSPI1_SS1,	0x0520, 0x0150, 1, 0x07E8, 1, 0)
+MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08,	0x0520, 0x0150, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__IPU1_CSI1_DATA16,	0x0520, 0x0150, 3, 0x08A0, 1, 0)
+MX6_PAD_DECL(EIM_D19__UART1_CTS_B,	0x0520, 0x0150, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__UART1_RTS_B,	0x0520, 0x0150, 4, 0x08F8, 0, 0)
+MX6_PAD_DECL(EIM_D19__GPIO3_IO19,	0x0520, 0x0150, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EPIT1_OUT,	0x0520, 0x0150, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EPDC_DATA12,	0x0520, 0x0150, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EIM_DATA20,	0x0524, 0x0154, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__ECSPI4_SS0,	0x0524, 0x0154, 1, 0x0808, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16,	0x0524, 0x0154, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU1_CSI1_DATA15,	0x0524, 0x0154, 3, 0x089C, 1, 0)
+MX6_PAD_DECL(EIM_D20__UART1_CTS_B,	0x0524, 0x0154, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__UART1_RTS_B,	0x0524, 0x0154, 4, 0x08F8, 1, 0)
+MX6_PAD_DECL(EIM_D20__GPIO3_IO20,	0x0524, 0x0154, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EPIT2_OUT,	0x0524, 0x0154, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__EIM_DATA21,	0x0528, 0x0158, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK,	0x0528, 0x0158, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17,	0x0528, 0x0158, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU1_CSI1_DATA11,	0x0528, 0x0158, 3, 0x088C, 0, 0)
+MX6_PAD_DECL(EIM_D21__USB_OTG_OC,	0x0528, 0x0158, 4, 0x0920, 0, 0)
+MX6_PAD_DECL(EIM_D21__GPIO3_IO21,	0x0528, 0x0158, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__I2C1_SCL,	0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0)
+MX6_PAD_DECL(EIM_D21__SPDIF_IN,	0x0528, 0x0158, 7, 0x08F0, 0, 0)
+MX6_PAD_DECL(EIM_D22__EIM_DATA22,	0x052C, 0x015C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__ECSPI4_MISO,	0x052C, 0x015C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01,	0x052C, 0x015C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU1_CSI1_DATA10,	0x052C, 0x015C, 3, 0x0888, 0, 0)
+MX6_PAD_DECL(EIM_D22__USB_OTG_PWR,	0x052C, 0x015C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__GPIO3_IO22,	0x052C, 0x015C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__SPDIF_OUT,	0x052C, 0x015C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__EPDC_SDCE6,	0x052C, 0x015C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__EIM_DATA23,	0x0530, 0x0160, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS,	0x0530, 0x0160, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_CTS_B,	0x0530, 0x0160, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_RTS_B,	0x0530, 0x0160, 2, 0x0908, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART1_DCD_B,	0x0530, 0x0160, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_CSI1_DATA_EN,	0x0530, 0x0160, 4, 0x08B0, 0, 0)
+MX6_PAD_DECL(EIM_D23__GPIO3_IO23,	0x0530, 0x0160, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02,	0x0530, 0x0160, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14,	0x0530, 0x0160, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__EPDC_DATA11,	0x0530, 0x0160, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__EIM_DATA24,	0x0534, 0x0164, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI4_SS2,	0x0534, 0x0164, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_TX_DATA,	0x0534, 0x0164, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_RX_DATA,	0x0534, 0x0164, 2, 0x090C, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI1_SS2,	0x0534, 0x0164, 3, 0x07EC, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI2_SS2,	0x0534, 0x0164, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__GPIO3_IO24,	0x0534, 0x0164, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__AUD5_RXFS,	0x0534, 0x0164, 6, 0x07BC, 1, 0)
+MX6_PAD_DECL(EIM_D24__UART1_DTR_B,	0x0534, 0x0164, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__EPDC_SDCE7,	0x0534, 0x0164, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__EIM_DATA25,	0x0538, 0x0168, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI4_SS3,	0x0538, 0x0168, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_TX_DATA,	0x0538, 0x0168, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_RX_DATA,	0x0538, 0x0168, 2, 0x090C, 1, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI1_SS3,	0x0538, 0x0168, 3, 0x07F0, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI2_SS3,	0x0538, 0x0168, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__GPIO3_IO25,	0x0538, 0x0168, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__AUD5_RXC,	0x0538, 0x0168, 6, 0x07B8, 1, 0)
+MX6_PAD_DECL(EIM_D25__UART1_DSR_B,	0x0538, 0x0168, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__EPDC_SDCE8,	0x0538, 0x0168, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__EIM_DATA26,	0x053C, 0x016C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11,	0x053C, 0x016C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01,	0x053C, 0x016C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_CSI1_DATA14,	0x053C, 0x016C, 3, 0x0898, 1, 0)
+MX6_PAD_DECL(EIM_D26__UART2_TX_DATA,	0x053C, 0x016C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__UART2_RX_DATA,	0x053C, 0x016C, 4, 0x0904, 0, 0)
+MX6_PAD_DECL(EIM_D26__GPIO3_IO26,	0x053C, 0x016C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_SISG2,	0x053C, 0x016C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22,	0x053C, 0x016C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__EPDC_SDOED,	0x053C, 0x016C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__EIM_DATA27,	0x0540, 0x0170, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13,	0x0540, 0x0170, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00,	0x0540, 0x0170, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_CSI1_DATA13,	0x0540, 0x0170, 3, 0x0894, 1, 0)
+MX6_PAD_DECL(EIM_D27__UART2_TX_DATA,	0x0540, 0x0170, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__UART2_RX_DATA,	0x0540, 0x0170, 4, 0x0904, 1, 0)
+MX6_PAD_DECL(EIM_D27__GPIO3_IO27,	0x0540, 0x0170, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_SISG3,	0x0540, 0x0170, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23,	0x0540, 0x0170, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__EPDC_SDOE,	0x0540, 0x0170, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__EIM_DATA28,	0x0544, 0x0174, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__I2C1_SDA,	0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0)
+MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI,	0x0544, 0x0174, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_CSI1_DATA12,	0x0544, 0x0174, 3, 0x0890, 1, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B,	0x0544, 0x0174, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B,	0x0544, 0x0174, 4, 0x0900, 0, 0)
+MX6_PAD_DECL(EIM_D28__GPIO3_IO28,	0x0544, 0x0174, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG,	0x0544, 0x0174, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13,	0x0544, 0x0174, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__EPDC_PWR_CTRL3,	0x0544, 0x0174, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__EIM_DATA29,	0x0548, 0x0178, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15,	0x0548, 0x0178, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__ECSPI4_SS0,	0x0548, 0x0178, 2, 0x0808, 1, 0)
+MX6_PAD_DECL(EIM_D29__UART2_CTS_B,	0x0548, 0x0178, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__UART2_RTS_B,	0x0548, 0x0178, 4, 0x0900, 1, 0)
+MX6_PAD_DECL(EIM_D29__GPIO3_IO29,	0x0548, 0x0178, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_CSI1_VSYNC,	0x0548, 0x0178, 6, 0x08BC, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14,	0x0548, 0x0178, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__EPDC_PWR_WAKE,	0x0548, 0x0178, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__EIM_DATA30,	0x054C, 0x017C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21,	0x054C, 0x017C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11,	0x054C, 0x017C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03,	0x054C, 0x017C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_CTS_B,	0x054C, 0x017C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_RTS_B,	0x054C, 0x017C, 4, 0x0908, 1, 0)
+MX6_PAD_DECL(EIM_D30__GPIO3_IO30,	0x054C, 0x017C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__USB_H1_OC,	0x054C, 0x017C, 6, 0x0924, 0, 0)
+MX6_PAD_DECL(EIM_D30__EPDC_SDOEZ,	0x054C, 0x017C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__EIM_DATA31,	0x0550, 0x0180, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20,	0x0550, 0x0180, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12,	0x0550, 0x0180, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02,	0x0550, 0x0180, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_CTS_B,	0x0550, 0x0180, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_RTS_B,	0x0550, 0x0180, 4, 0x0908, 2, 0)
+MX6_PAD_DECL(EIM_D31__GPIO3_IO31,	0x0550, 0x0180, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__USB_H1_PWR,	0x0550, 0x0180, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__EPDC_SDCLK_P,	0x0550, 0x0180, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__EIM_ACLK_FREERUN,	0x0550, 0x0180, 9, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__EIM_AD00,	0x0554, 0x0184, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09,	0x0554, 0x0184, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU1_CSI1_DATA09,	0x0554, 0x0184, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__GPIO3_IO00,	0x0554, 0x0184, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00,	0x0554, 0x0184, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__EPDC_SDCLK_N,	0x0554, 0x0184, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__EIM_AD01,	0x0558, 0x0188, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08,	0x0558, 0x0188, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU1_CSI1_DATA08,	0x0558, 0x0188, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__GPIO3_IO01,	0x0558, 0x0188, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01,	0x0558, 0x0188, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__EPDC_SDLE,	0x0558, 0x0188, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__EIM_AD10,	0x055C, 0x018C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15,	0x055C, 0x018C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU1_CSI1_DATA_EN,	0x055C, 0x018C, 2, 0x08B0, 1, 0)
+MX6_PAD_DECL(EIM_DA10__GPIO3_IO10,	0x055C, 0x018C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10,	0x055C, 0x018C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__EPDC_DATA01,	0x055C, 0x018C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__EIM_AD11,	0x0560, 0x0190, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02,	0x0560, 0x0190, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU1_CSI1_HSYNC,	0x0560, 0x0190, 2, 0x08B4, 0, 0)
+MX6_PAD_DECL(EIM_DA11__GPIO3_IO11,	0x0560, 0x0190, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11,	0x0560, 0x0190, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__EPDC_DATA03,	0x0560, 0x0190, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__EIM_AD12,	0x0564, 0x0194, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03,	0x0564, 0x0194, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU1_CSI1_VSYNC,	0x0564, 0x0194, 2, 0x08BC, 1, 0)
+MX6_PAD_DECL(EIM_DA12__GPIO3_IO12,	0x0564, 0x0194, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12,	0x0564, 0x0194, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__EPDC_DATA02,	0x0564, 0x0194, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__EIM_AD13,	0x0568, 0x0198, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS,	0x0568, 0x0198, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__GPIO3_IO13,	0x0568, 0x0198, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13,	0x0568, 0x0198, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__EPDC_DATA13,	0x0568, 0x0198, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__EIM_AD14,	0x056C, 0x019C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS,	0x056C, 0x019C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__GPIO3_IO14,	0x056C, 0x019C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14,	0x056C, 0x019C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__EPDC_DATA14,	0x056C, 0x019C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__EIM_AD15,	0x0570, 0x01A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01,	0x0570, 0x01A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04,	0x0570, 0x01A0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__GPIO3_IO15,	0x0570, 0x01A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15,	0x0570, 0x01A0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__EPDC_DATA09,	0x0570, 0x01A0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__EIM_AD02,	0x0574, 0x01A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07,	0x0574, 0x01A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU1_CSI1_DATA07,	0x0574, 0x01A4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__GPIO3_IO02,	0x0574, 0x01A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02,	0x0574, 0x01A4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__EPDC_BDR0,	0x0574, 0x01A4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__EIM_AD03,	0x0578, 0x01A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06,	0x0578, 0x01A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU1_CSI1_DATA06,	0x0578, 0x01A8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__GPIO3_IO03,	0x0578, 0x01A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03,	0x0578, 0x01A8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__EPDC_BDR1,	0x0578, 0x01A8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__EIM_AD04,	0x057C, 0x01AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05,	0x057C, 0x01AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU1_CSI1_DATA05,	0x057C, 0x01AC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__GPIO3_IO04,	0x057C, 0x01AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04,	0x057C, 0x01AC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__EPDC_SDCE0,	0x057C, 0x01AC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__EIM_AD05,	0x0580, 0x01B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04,	0x0580, 0x01B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU1_CSI1_DATA04,	0x0580, 0x01B0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__GPIO3_IO05,	0x0580, 0x01B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05,	0x0580, 0x01B0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__EPDC_SDCE1,	0x0580, 0x01B0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__EIM_AD06,	0x0584, 0x01B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03,	0x0584, 0x01B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU1_CSI1_DATA03,	0x0584, 0x01B4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__GPIO3_IO06,	0x0584, 0x01B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06,	0x0584, 0x01B4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__EPDC_SDCE2,	0x0584, 0x01B4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__EIM_AD07,	0x0588, 0x01B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02,	0x0588, 0x01B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU1_CSI1_DATA02,	0x0588, 0x01B8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__GPIO3_IO07,	0x0588, 0x01B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07,	0x0588, 0x01B8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__EPDC_SDCE3,	0x0588, 0x01B8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__EIM_AD08,	0x058C, 0x01BC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01,	0x058C, 0x01BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU1_CSI1_DATA01,	0x058C, 0x01BC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__GPIO3_IO08,	0x058C, 0x01BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08,	0x058C, 0x01BC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__EPDC_SDCE4,	0x058C, 0x01BC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__EIM_AD09,	0x0590, 0x01C0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00,	0x0590, 0x01C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU1_CSI1_DATA00,	0x0590, 0x01C0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__GPIO3_IO09,	0x0590, 0x01C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09,	0x0590, 0x01C0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__EPDC_SDCE5,	0x0590, 0x01C0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__EIM_EB0_B,	0x0594, 0x01C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11,	0x0594, 0x01C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU1_CSI1_DATA11,	0x0594, 0x01C4, 2, 0x088C, 1, 0)
+MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY,	0x0594, 0x01C4, 4, 0x07D4, 0, 0)
+MX6_PAD_DECL(EIM_EB0__GPIO2_IO28,	0x0594, 0x01C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27,	0x0594, 0x01C4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__EPDC_PWR_COM,	0x0594, 0x01C4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__EIM_EB1_B,	0x0598, 0x01C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10,	0x0598, 0x01C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU1_CSI1_DATA10,	0x0598, 0x01C8, 2, 0x0888, 1, 0)
+MX6_PAD_DECL(EIM_EB1__GPIO2_IO29,	0x0598, 0x01C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28,	0x0598, 0x01C8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__EPDC_SDSHR,	0x0598, 0x01C8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__EIM_EB2_B,	0x059C, 0x01CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0,	0x059C, 0x01CC, 1, 0x07E4, 2, 0)
+MX6_PAD_DECL(EIM_EB2__IPU1_CSI1_DATA19,	0x059C, 0x01CC, 3, 0x08AC, 1, 0)
+MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL,	0x059C, 0x01CC, 4, 0x0860, 0, 0)
+MX6_PAD_DECL(EIM_EB2__GPIO2_IO30,	0x059C, 0x01CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__I2C2_SCL,	0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0)
+MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30,	0x059C, 0x01CC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__EPDC_DATA05,	0x059C, 0x01CC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EIM_EB3_B,	0x05A0, 0x01D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY,	0x05A0, 0x01D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_CTS_B,	0x05A0, 0x01D0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_RTS_B,	0x05A0, 0x01D0, 2, 0x0908, 3, 0)
+MX6_PAD_DECL(EIM_EB3__UART1_RI_B,	0x05A0, 0x01D0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU1_CSI1_HSYNC,	0x05A0, 0x01D0, 4, 0x08B4, 1, 0)
+MX6_PAD_DECL(EIM_EB3__GPIO2_IO31,	0x05A0, 0x01D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03,	0x05A0, 0x01D0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31,	0x05A0, 0x01D0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EPDC_SDCE0,	0x05A0, 0x01D0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EIM_ACLK_FREERUN,	0x05A0, 0x01D0, 9, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__EIM_LBA_B,	0x05A4, 0x01D4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17,	0x05A4, 0x01D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1,	0x05A4, 0x01D4, 2, 0x0804, 1, 0)
+MX6_PAD_DECL(EIM_LBA__GPIO2_IO27,	0x05A4, 0x01D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26,	0x05A4, 0x01D4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__EPDC_DATA04,	0x05A4, 0x01D4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__EIM_OE_B,	0x05A8, 0x01D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07,	0x05A8, 0x01D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__ECSPI2_MISO,	0x05A8, 0x01D8, 2, 0x07F8, 2, 0)
+MX6_PAD_DECL(EIM_OE__GPIO2_IO25,	0x05A8, 0x01D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__EPDC_PWR_IRQ,	0x05A8, 0x01D8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__EIM_RW,	0x05AC, 0x01DC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08,	0x05AC, 0x01DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__ECSPI2_SS0,	0x05AC, 0x01DC, 2, 0x0800, 2, 0)
+MX6_PAD_DECL(EIM_RW__GPIO2_IO26,	0x05AC, 0x01DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29,	0x05AC, 0x01DC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__EPDC_DATA07,	0x05AC, 0x01DC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B,	0x05B0, 0x01E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B,	0x05B0, 0x01E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00,	0x05B0, 0x01E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25,	0x05B0, 0x01E0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN,	0x05B4, 0x01E4, 1, 0x0828, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK,	0x05B4, 0x01E4, 2, 0x0840, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK,	0x05B4, 0x01E4, 3, 0x08F4, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25,	0x05B4, 0x01E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__MLB_DATA,	0x05B8, 0x01E8, 0, 0x08E0, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_MDC,	0x05B8, 0x01E8, 1, 0x0000, 0,  0)
+MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0,	0x05B8, 0x01E8, 2, 0x0858, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN,	0x05B8, 0x01E8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__GPIO1_IO31,	0x05B8, 0x01E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_MDIO,	0x05BC, 0x01EC, 1, 0x0810, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK,	0x05BC, 0x01EC, 2, 0x083C, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT,	0x05BC, 0x01EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22,	0x05BC, 0x01EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK,	0x05BC, 0x01EC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK,	0x05C0, 0x01F0, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS,	0x05C0, 0x01F0, 2, 0x082C, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23,	0x05C0, 0x01F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK,	0x05C0, 0x01F0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID,	0x05C4, 0x01F4, 0, 0x0790, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER,	0x05C4, 0x01F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK,	0x05C4, 0x01F4, 2, 0x0834, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN,	0x05C4, 0x01F4, 3, 0x08F0, 1, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT,	0x05C4, 0x01F4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24,	0x05C4, 0x01F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0,	0x05C8, 0x01F8, 1, 0x0818, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK,	0x05C8, 0x01F8, 2, 0x0838, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT,	0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27,	0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__MLB_SIG,	0x05CC, 0x01FC, 0, 0x08E4, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1,	0x05CC, 0x01FC, 1, 0x081C, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS,	0x05CC, 0x01FC, 2, 0x0830, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT,	0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26,	0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN,	0x05D0, 0x0200, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2,	0x05D0, 0x0200, 2, 0x0850, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28,	0x05D0, 0x0200, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__I2C4_SCL,	0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0,	0x05D4, 0x0204, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1,	0x05D4, 0x0204, 2, 0x0854, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30,	0x05D4, 0x0204, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__MLB_CLK,	0x05D8, 0x0208, 0, 0x08DC, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1,	0x05D8, 0x0208, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3,	0x05D8, 0x0208, 2, 0x084C, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN,	0x05D8, 0x0208, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29,	0x05D8, 0x0208, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__I2C4_SDA,	0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0)
+MX6_PAD_DECL(GPIO_0__CCM_CLKO1,	0x05DC, 0x020C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__KEY_COL5,	0x05DC, 0x020C, 2, 0x08C0, 1, 0)
+MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK,	0x05DC, 0x020C, 3, 0x0794, 0, 0)
+MX6_PAD_DECL(GPIO_0__EPIT1_OUT,	0x05DC, 0x020C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__GPIO1_IO00,	0x05DC, 0x020C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__USB_H1_PWR,	0x05DC, 0x020C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__SNVS_VIO_5,	0x05DC, 0x020C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK,	0x05E0, 0x0210, 0, 0x083C, 1, 0)
+MX6_PAD_DECL(GPIO_1__WDOG2_B,	0x05E0, 0x0210, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__KEY_ROW5,	0x05E0, 0x0210, 2, 0x08CC, 1, 0)
+MX6_PAD_DECL(GPIO_1__USB_OTG_ID,	0x05E0, 0x0210, 3, 0x0790, 1, 0)
+MX6_PAD_DECL(GPIO_1__PWM2_OUT,	0x05E0, 0x0210, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__GPIO1_IO01,	0x05E0, 0x0210, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__SD1_CD_B,	0x05E0, 0x0210, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,	0x05E4, 0x0214, 0, 0x0850, 1, 0)
+MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN,	0x05E4, 0x0214, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,	0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0)
+MX6_PAD_DECL(GPIO_16__SD1_LCTL,	0x05E4, 0x0214, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__SPDIF_IN,	0x05E4, 0x0214, 4, 0x08F0, 2, 0)
+MX6_PAD_DECL(GPIO_16__GPIO7_IO11,	0x05E4, 0x0214, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__I2C3_SDA,	0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0)
+MX6_PAD_DECL(GPIO_16__JTAG_DE_B,	0x05E4, 0x0214, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__ESAI_TX0,	0x05E8, 0x0218, 0, 0x0844, 0, 0)
+MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN,	0x05E8, 0x0218, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY,	0x05E8, 0x0218, 2, 0x07D4, 1, 0)
+MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0,	0x05E8, 0x0218, 3, 0x08E8, 1, 0)
+MX6_PAD_DECL(GPIO_17__SPDIF_OUT,	0x05E8, 0x0218, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__GPIO7_IO12,	0x05E8, 0x0218, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__ESAI_TX1,	0x05EC, 0x021C, 0, 0x0848, 0, 0)
+MX6_PAD_DECL(GPIO_18__ENET_RX_CLK,	0x05EC, 0x021C, 1, 0x0814, 0, 0)
+MX6_PAD_DECL(GPIO_18__SD3_VSELECT,	0x05EC, 0x021C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1,	0x05EC, 0x021C, 3, 0x08EC, 1, 0)
+MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK,	0x05EC, 0x021C, 4, 0x0794, 1, 0)
+MX6_PAD_DECL(GPIO_18__GPIO7_IO13,	0x05EC, 0x021C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL,	0x05EC, 0x021C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__KEY_COL5,	0x05F0, 0x0220, 0, 0x08C0, 2, 0)
+MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT,	0x05F0, 0x0220, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__SPDIF_OUT,	0x05F0, 0x0220, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__CCM_CLKO1,	0x05F0, 0x0220, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ECSPI1_RDY,	0x05F0, 0x0220, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__GPIO4_IO05,	0x05F0, 0x0220, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ENET_TX_ER,	0x05F0, 0x0220, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__ESAI_TX_FS,	0x05F4, 0x0224, 0, 0x0830, 1, 0)
+MX6_PAD_DECL(GPIO_2__KEY_ROW6,	0x05F4, 0x0224, 2, 0x08D0, 1, 0)
+MX6_PAD_DECL(GPIO_2__GPIO1_IO02,	0x05F4, 0x0224, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__SD2_WP,	0x05F4, 0x0224, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__MLB_DATA,	0x05F4, 0x0224, 7, 0x08E0, 1, 0)
+MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK,	0x05F8, 0x0228, 0, 0x0834, 1, 0)
+MX6_PAD_DECL(GPIO_3__I2C3_SCL,	0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0)
+MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M,	0x05F8, 0x0228, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__CCM_CLKO2,	0x05F8, 0x0228, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__GPIO1_IO03,	0x05F8, 0x0228, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__USB_H1_OC,	0x05F8, 0x0228, 6, 0x0924, 1, 0)
+MX6_PAD_DECL(GPIO_3__MLB_CLK,	0x05F8, 0x0228, 7, 0x08DC, 1, 0)
+MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK,	0x05FC, 0x022C, 0, 0x0838, 1, 0)
+MX6_PAD_DECL(GPIO_4__KEY_COL7,	0x05FC, 0x022C, 2, 0x08C8, 1, 0)
+MX6_PAD_DECL(GPIO_4__GPIO1_IO04,	0x05FC, 0x022C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_4__SD2_CD_B,	0x05FC, 0x022C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3,	0x0600, 0x0230, 0, 0x084C, 1, 0)
+MX6_PAD_DECL(GPIO_5__KEY_ROW7,	0x0600, 0x0230, 2, 0x08D4, 1, 0)
+MX6_PAD_DECL(GPIO_5__CCM_CLKO1,	0x0600, 0x0230, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__GPIO1_IO05,	0x0600, 0x0230, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__I2C3_SCL,	0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0)
+MX6_PAD_DECL(GPIO_5__ARM_EVENTI,	0x0600, 0x0230, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK,	0x0604, 0x0234, 0, 0x0840, 1, 0)
+MX6_PAD_DECL(GPIO_6__I2C3_SDA,	0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0)
+MX6_PAD_DECL(GPIO_6__GPIO1_IO06,	0x0604, 0x0234, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__SD2_LCTL,	0x0604, 0x0234, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__MLB_SIG,	0x0604, 0x0234, 7, 0x08E4, 1, 0)
+MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1,	0x0608, 0x0238, 0, 0x0854, 1, 0)
+MX6_PAD_DECL(GPIO_7__EPIT1_OUT,	0x0608, 0x0238, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX,	0x0608, 0x0238, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_TX_DATA,	0x0608, 0x0238, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_RX_DATA,	0x0608, 0x0238, 4, 0x0904, 2, 0)
+MX6_PAD_DECL(GPIO_7__GPIO1_IO07,	0x0608, 0x0238, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__SPDIF_LOCK,	0x0608, 0x0238, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE,	0x0608, 0x0238, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__I2C4_SCL,	0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0)
+MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0,	0x060C, 0x023C, 0, 0x0858, 1, 0)
+MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K,	0x060C, 0x023C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__EPIT2_OUT,	0x060C, 0x023C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX,	0x060C, 0x023C, 3, 0x07C8, 0, 0)
+MX6_PAD_DECL(GPIO_8__UART2_TX_DATA,	0x060C, 0x023C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__UART2_RX_DATA,	0x060C, 0x023C, 4, 0x0904, 3, 0)
+MX6_PAD_DECL(GPIO_8__GPIO1_IO08,	0x060C, 0x023C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK,	0x060C, 0x023C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE,	0x060C, 0x023C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__I2C4_SDA,	0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0)
+MX6_PAD_DECL(GPIO_9__ESAI_RX_FS,	0x0610, 0x0240, 0, 0x082C, 1, 0)
+MX6_PAD_DECL(GPIO_9__WDOG1_B,	0x0610, 0x0240, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__KEY_COL6,	0x0610, 0x0240, 2, 0x08C4, 1, 0)
+MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B,	0x0610, 0x0240, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__PWM1_OUT,	0x0610, 0x0240, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__GPIO1_IO09,	0x0610, 0x0240, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__SD1_WP,	0x0610, 0x0240, 6, 0x092C, 1, 0)
+MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK,	0x062C, 0x0244, 0, 0x07D8, 3, 0)
+MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3,	0x062C, 0x0244, 1, 0x0824, 0, 0)
+MX6_PAD_DECL(KEY_COL0__AUD5_TXC,	0x062C, 0x0244, 2, 0x07C0, 1, 0)
+MX6_PAD_DECL(KEY_COL0__KEY_COL0,	0x062C, 0x0244, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA,	0x062C, 0x0244, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA,	0x062C, 0x0244, 4, 0x0914, 2, 0)
+MX6_PAD_DECL(KEY_COL0__GPIO4_IO06,	0x062C, 0x0244, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__DCIC1_OUT,	0x062C, 0x0244, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO,	0x0630, 0x0248, 0, 0x07DC, 3, 0)
+MX6_PAD_DECL(KEY_COL1__ENET_MDIO,	0x0630, 0x0248, 1, 0x0810, 1, 0)
+MX6_PAD_DECL(KEY_COL1__AUD5_TXFS,	0x0630, 0x0248, 2, 0x07C4, 1, 0)
+MX6_PAD_DECL(KEY_COL1__KEY_COL1,	0x0630, 0x0248, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA,	0x0630, 0x0248, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA,	0x0630, 0x0248, 4, 0x091C, 2, 0)
+MX6_PAD_DECL(KEY_COL1__GPIO4_IO08,	0x0630, 0x0248, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__SD1_VSELECT,	0x0630, 0x0248, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1,	0x0634, 0x024C, 0, 0x07E8, 2, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2,	0x0634, 0x024C, 1, 0x0820, 0, 0)
+MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX,	0x0634, 0x024C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__KEY_COL2,	0x0634, 0x024C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_MDC,	0x0634, 0x024C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__GPIO4_IO10,	0x0634, 0x024C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE,	0x0634, 0x024C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3,	0x0638, 0x0250, 0, 0x07F0, 1, 0)
+MX6_PAD_DECL(KEY_COL3__ENET_CRS,	0x0638, 0x0250, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL,	0x0638, 0x0250, 2, 0x0860, 1, 0)
+MX6_PAD_DECL(KEY_COL3__KEY_COL3,	0x0638, 0x0250, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__I2C2_SCL,	0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0)
+MX6_PAD_DECL(KEY_COL3__GPIO4_IO12,	0x0638, 0x0250, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__SPDIF_IN,	0x0638, 0x0250, 6, 0x08F0, 3, 0)
+MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX,	0x063C, 0x0254, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__IPU1_SISG4,	0x063C, 0x0254, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__USB_OTG_OC,	0x063C, 0x0254, 2, 0x0920, 1, 0)
+MX6_PAD_DECL(KEY_COL4__KEY_COL4,	0x063C, 0x0254, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_CTS_B,	0x063C, 0x0254, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_RTS_B,	0x063C, 0x0254, 4, 0x0918, 2, 0)
+MX6_PAD_DECL(KEY_COL4__GPIO4_IO14,	0x063C, 0x0254, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI,	0x0640, 0x0258, 0, 0x07E0, 3, 0)
+MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3,	0x0640, 0x0258, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__AUD5_TXD,	0x0640, 0x0258, 2, 0x07B4, 1, 0)
+MX6_PAD_DECL(KEY_ROW0__KEY_ROW0,	0x0640, 0x0258, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA,	0x0640, 0x0258, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA,	0x0640, 0x0258, 4, 0x0914, 3, 0)
+MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07,	0x0640, 0x0258, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT,	0x0640, 0x0258, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0,	0x0644, 0x025C, 0, 0x07E4, 3, 0)
+MX6_PAD_DECL(KEY_ROW1__ENET_COL,	0x0644, 0x025C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__AUD5_RXD,	0x0644, 0x025C, 2, 0x07B0, 1, 0)
+MX6_PAD_DECL(KEY_ROW1__KEY_ROW1,	0x0644, 0x025C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA,	0x0644, 0x025C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA,	0x0644, 0x025C, 4, 0x091C, 3, 0)
+MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09,	0x0644, 0x025C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT,	0x0644, 0x025C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2,	0x0648, 0x0260, 0, 0x07EC, 1, 0)
+MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2,	0x0648, 0x0260, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX,	0x0648, 0x0260, 2, 0x07C8, 1, 0)
+MX6_PAD_DECL(KEY_ROW2__KEY_ROW2,	0x0648, 0x0260, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT,	0x0648, 0x0260, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11,	0x0648, 0x0260, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE,	0x0648, 0x0260, 6, 0x085C, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK,	0x064C, 0x0264, 1, 0x0794, 2, 0)
+MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA,	0x064C, 0x0264, 2, 0x0864, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__KEY_ROW3,	0x064C, 0x0264, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__I2C2_SDA,	0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13,	0x064C, 0x0264, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT,	0x064C, 0x0264, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX,	0x0650, 0x0268, 0, 0x07CC, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5,	0x0650, 0x0268, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR,	0x0650, 0x0268, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__KEY_ROW4,	0x0650, 0x0268, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B,	0x0650, 0x0268, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B,	0x0650, 0x0268, 4, 0x0918, 3, 0)
+MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15,	0x0650, 0x0268, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__NAND_ALE,	0x0654, 0x026C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__SD4_RESET,	0x0654, 0x026C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08,	0x0654, 0x026C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__NAND_CLE,	0x0658, 0x0270, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07,	0x0658, 0x0270, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B,	0x065C, 0x0274, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11,	0x065C, 0x0274, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B,	0x0660, 0x0278, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT,	0x0660, 0x0278, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT,	0x0660, 0x0278, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14,	0x0660, 0x0278, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B,	0x0664, 0x027C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0,	0x0664, 0x027C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__ESAI_TX0,	0x0664, 0x027C, 2, 0x0844, 1, 0)
+MX6_PAD_DECL(NANDF_CS2__EIM_CRE,	0x0664, 0x027C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2,	0x0664, 0x027C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15,	0x0664, 0x027C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B,	0x0668, 0x0280, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1,	0x0668, 0x0280, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__ESAI_TX1,	0x0668, 0x0280, 2, 0x0848, 1, 0)
+MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26,	0x0668, 0x0280, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16,	0x0668, 0x0280, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__I2C4_SDA,	0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0)
+MX6_PAD_DECL(NANDF_D0__NAND_DATA00,	0x066C, 0x0284, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__SD1_DATA4,	0x066C, 0x0284, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__GPIO2_IO00,	0x066C, 0x0284, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__NAND_DATA01,	0x0670, 0x0288, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__SD1_DATA5,	0x0670, 0x0288, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__GPIO2_IO01,	0x0670, 0x0288, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__NAND_DATA02,	0x0674, 0x028C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__SD1_DATA6,	0x0674, 0x028C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__GPIO2_IO02,	0x0674, 0x028C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__NAND_DATA03,	0x0678, 0x0290, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__SD1_DATA7,	0x0678, 0x0290, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__GPIO2_IO03,	0x0678, 0x0290, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__NAND_DATA04,	0x067C, 0x0294, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__SD2_DATA4,	0x067C, 0x0294, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__GPIO2_IO04,	0x067C, 0x0294, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__NAND_DATA05,	0x0680, 0x0298, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__SD2_DATA5,	0x0680, 0x0298, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__GPIO2_IO05,	0x0680, 0x0298, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__NAND_DATA06,	0x0684, 0x029C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__SD2_DATA6,	0x0684, 0x029C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__GPIO2_IO06,	0x0684, 0x029C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__NAND_DATA07,	0x0688, 0x02A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__SD2_DATA7,	0x0688, 0x02A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__GPIO2_IO07,	0x0688, 0x02A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__NAND_READY_B,	0x068C, 0x02A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10,	0x068C, 0x02A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B,	0x0690, 0x02A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09,	0x0690, 0x02A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__I2C4_SCL,	0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0)
+MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY,	0x0694, 0x02AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__RGMII_RD0,	0x0694, 0x02AC, 1, 0x0818, 1, 0)
+MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25,	0x0694, 0x02AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG,	0x0698, 0x02B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__RGMII_RD1,	0x0698, 0x02B0, 1, 0x081C, 1, 0)
+MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27,	0x0698, 0x02B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA,	0x069C, 0x02B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__RGMII_RD2,	0x069C, 0x02B4, 1, 0x0820, 1, 0)
+MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28,	0x069C, 0x02B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE,	0x06A0, 0x02B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__RGMII_RD3,	0x06A0, 0x02B8, 1, 0x0824, 1, 0)
+MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29,	0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA,	0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL,	0x06A4, 0x02BC, 1, 0x0828, 1, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24,	0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__USBOH3_H3_STROBE,	0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE,	0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP)
+MX6_PAD_DECL(RGMII_RXC__RGMII_RXC,	0x06A8, 0x02C0, 1, 0x0814, 1, 0)
+MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30,	0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY,	0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__RGMII_TD0,	0x06AC, 0x02C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20,	0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG,	0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__RGMII_TD1,	0x06B0, 0x02C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21,	0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA,	0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__RGMII_TD2,	0x06B4, 0x02CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22,	0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE,	0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__RGMII_TD3,	0x06B8, 0x02D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23,	0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE,	0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE,	0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP)
+MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL,	0x06BC, 0x02D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26,	0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK,	0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0)
+MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA,	0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__RGMII_TXC,	0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK,	0x06C0, 0x02D8, 2, 0x08F4, 1, 0)
+MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19,	0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M,	0x06C0, 0x02D8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__SD1_CLK,	0x06C4, 0x02DC, 0, 0x0928, 1, 0)
+MX6_PAD_DECL(SD1_CLK__GPT_CLKIN,	0x06C4, 0x02DC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__GPIO1_IO20,	0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__SD1_CMD,	0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__PWM4_OUT,	0x06C8, 0x02E0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1,	0x06C8, 0x02E0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPIO1_IO18,	0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__SD1_DATA0,	0x06CC, 0x02E4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1,	0x06CC, 0x02E4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16,	0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__SD1_DATA1,	0x06D0, 0x02E8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__PWM3_OUT,	0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2,	0x06D0, 0x02E8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17,	0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__SD1_DATA2,	0x06D4, 0x02EC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2,	0x06D4, 0x02EC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__PWM2_OUT,	0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_B,	0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19,	0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB,	0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__SD1_DATA3,	0x06D8, 0x02F0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3,	0x06D8, 0x02F0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__PWM1_OUT,	0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_B,	0x06D8, 0x02F0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21,	0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB,	0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CLK__SD2_CLK,	0x06DC, 0x02F4, 0, 0x0930, 1, 0)
+MX6_PAD_DECL(SD2_CLK__KEY_COL5,	0x06DC, 0x02F4, 2, 0x08C0, 3, 0)
+MX6_PAD_DECL(SD2_CLK__AUD4_RXFS,	0x06DC, 0x02F4, 3, 0x07A4, 1, 0)
+MX6_PAD_DECL(SD2_CLK__GPIO1_IO10,	0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__SD2_CMD,	0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__KEY_ROW5,	0x06E0, 0x02F8, 2, 0x08CC, 2, 0)
+MX6_PAD_DECL(SD2_CMD__AUD4_RXC,	0x06E0, 0x02F8, 3, 0x07A0, 1, 0)
+MX6_PAD_DECL(SD2_CMD__GPIO1_IO11,	0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__SD2_DATA0,	0x06E4, 0x02FC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__AUD4_RXD,	0x06E4, 0x02FC, 3, 0x0798, 1, 0)
+MX6_PAD_DECL(SD2_DAT0__KEY_ROW7,	0x06E4, 0x02FC, 4, 0x08D4, 2, 0)
+MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15,	0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT,	0x06E4, 0x02FC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__SD2_DATA1,	0x06E8, 0x0300, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B,	0x06E8, 0x0300, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS,	0x06E8, 0x0300, 3, 0x07AC, 1, 0)
+MX6_PAD_DECL(SD2_DAT1__KEY_COL7,	0x06E8, 0x0300, 4, 0x08C8, 2, 0)
+MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14,	0x06E8, 0x0300, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__SD2_DATA2,	0x06EC, 0x0304, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B,	0x06EC, 0x0304, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__AUD4_TXD,	0x06EC, 0x0304, 3, 0x079C, 1, 0)
+MX6_PAD_DECL(SD2_DAT2__KEY_ROW6,	0x06EC, 0x0304, 4, 0x08D0, 2, 0)
+MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13,	0x06EC, 0x0304, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__SD2_DATA3,	0x06F0, 0x0308, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__KEY_COL6,	0x06F0, 0x0308, 2, 0x08C4, 2, 0)
+MX6_PAD_DECL(SD2_DAT3__AUD4_TXC,	0x06F0, 0x0308, 3, 0x07A8, 1, 0)
+MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12,	0x06F0, 0x0308, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__SD3_CLK,	0x06F4, 0x030C, 0, 0x0934, 1, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_CTS_B,	0x06F4, 0x030C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_RTS_B,	0x06F4, 0x030C, 1, 0x0900, 2, 0)
+MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX,	0x06F4, 0x030C, 2, 0x07C8, 2, 0)
+MX6_PAD_DECL(SD3_CLK__GPIO7_IO03,	0x06F4, 0x030C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__SD3_CMD,	0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_CTS_B,	0x06F8, 0x0310, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_RTS_B,	0x06F8, 0x0310, 1, 0x0900, 3, 0)
+MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX,	0x06F8, 0x0310, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__GPIO7_IO02,	0x06F8, 0x0310, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__SD3_DATA0,	0x06FC, 0x0314, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B,	0x06FC, 0x0314, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B,	0x06FC, 0x0314, 1, 0x08F8, 2, 0)
+MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX,	0x06FC, 0x0314, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04,	0x06FC, 0x0314, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__SD3_DATA1,	0x0700, 0x0318, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B,	0x0700, 0x0318, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B,	0x0700, 0x0318, 1, 0x08F8, 3, 0)
+MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX,	0x0700, 0x0318, 2, 0x07CC, 1, 0)
+MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05,	0x0700, 0x0318, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__SD3_DATA2,	0x0704, 0x031C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06,	0x0704, 0x031C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__SD3_DATA3,	0x0708, 0x0320, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B,	0x0708, 0x0320, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B,	0x0708, 0x0320, 1, 0x0908, 4, 0)
+MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07,	0x0708, 0x0320, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__SD3_DATA4,	0x070C, 0x0324, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA,	0x070C, 0x0324, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA,	0x070C, 0x0324, 1, 0x0904, 4, 0)
+MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01,	0x070C, 0x0324, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__SD3_DATA5,	0x0710, 0x0328, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA,	0x0710, 0x0328, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA,	0x0710, 0x0328, 1, 0x0904, 5, 0)
+MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00,	0x0710, 0x0328, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__SD3_DATA6,	0x0714, 0x032C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA,	0x0714, 0x032C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA,	0x0714, 0x032C, 1, 0x08FC, 2, 0)
+MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18,	0x0714, 0x032C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__SD3_DATA7,	0x0718, 0x0330, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA,	0x0718, 0x0330, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA,	0x0718, 0x0330, 1, 0x08FC, 3, 0)
+MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17,	0x0718, 0x0330, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__SD3_RESET,	0x071C, 0x0334, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_CTS_B,	0x071C, 0x0334, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_RTS_B,	0x071C, 0x0334, 1, 0x0908, 5, 0)
+MX6_PAD_DECL(SD3_RST__GPIO7_IO08,	0x071C, 0x0334, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__SD4_CLK,	0x0720, 0x0338, 0, 0x0938, 1, 0)
+MX6_PAD_DECL(SD4_CLK__NAND_WE_B,	0x0720, 0x0338, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA,	0x0720, 0x0338, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA,	0x0720, 0x0338, 2, 0x090C, 2, 0)
+MX6_PAD_DECL(SD4_CLK__GPIO7_IO10,	0x0720, 0x0338, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__SD4_CMD,	0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__NAND_RE_B,	0x0724, 0x033C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA,	0x0724, 0x033C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA,	0x0724, 0x033C, 2, 0x090C, 3, 0)
+MX6_PAD_DECL(SD4_CMD__GPIO7_IO09,	0x0724, 0x033C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__SD4_DATA0,	0x0728, 0x0340, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__NAND_DQS,	0x0728, 0x0340, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08,	0x0728, 0x0340, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__SD4_DATA1,	0x072C, 0x0344, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__PWM3_OUT,	0x072C, 0x0344, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09,	0x072C, 0x0344, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__SD4_DATA2,	0x0730, 0x0348, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__PWM4_OUT,	0x0730, 0x0348, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10,	0x0730, 0x0348, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__SD4_DATA3,	0x0734, 0x034C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11,	0x0734, 0x034C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__SD4_DATA4,	0x0738, 0x0350, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA,	0x0738, 0x0350, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA,	0x0738, 0x0350, 2, 0x0904, 6, 0)
+MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12,	0x0738, 0x0350, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__SD4_DATA5,	0x073C, 0x0354, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B,	0x073C, 0x0354, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B,	0x073C, 0x0354, 2, 0x0900, 4, 0)
+MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13,	0x073C, 0x0354, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__SD4_DATA6,	0x0740, 0x0358, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B,	0x0740, 0x0358, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B,	0x0740, 0x0358, 2, 0x0900, 5, 0)
+MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14,	0x0740, 0x0358, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__SD4_DATA7,	0x0744, 0x035C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA,	0x0744, 0x035C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA,	0x0744, 0x035C, 2, 0x0904, 7, 0)
+MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15,	0x0744, 0x035C, 5, 0x0000, 0, 0)
+
+#endif	/* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
new file mode 100644
index 000000000..0aa94cffe
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARCH_MX6Q_DDR_H__
+#define __ASM_ARCH_MX6Q_DDR_H__
+
+#ifndef CONFIG_MX6Q
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_DQM0	0x020e05ac
+#define MX6_IOM_DRAM_DQM1	0x020e05b4
+#define MX6_IOM_DRAM_DQM2	0x020e0528
+#define MX6_IOM_DRAM_DQM3	0x020e0520
+#define MX6_IOM_DRAM_DQM4	0x020e0514
+#define MX6_IOM_DRAM_DQM5	0x020e0510
+#define MX6_IOM_DRAM_DQM6	0x020e05bc
+#define MX6_IOM_DRAM_DQM7	0x020e05c4
+
+#define MX6_IOM_DRAM_CAS	0x020e056c
+#define MX6_IOM_DRAM_RAS	0x020e0578
+#define MX6_IOM_DRAM_RESET	0x020e057c
+#define MX6_IOM_DRAM_SDCLK_0	0x020e0588
+#define MX6_IOM_DRAM_SDCLK_1	0x020e0594
+#define MX6_IOM_DRAM_SDBA2	0x020e058c
+#define MX6_IOM_DRAM_SDCKE0	0x020e0590
+#define MX6_IOM_DRAM_SDCKE1	0x020e0598
+#define MX6_IOM_DRAM_SDODT0	0x020e059c
+#define MX6_IOM_DRAM_SDODT1	0x020e05a0
+
+#define MX6_IOM_DRAM_SDQS0	0x020e05a8
+#define MX6_IOM_DRAM_SDQS1	0x020e05b0
+#define MX6_IOM_DRAM_SDQS2	0x020e0524
+#define MX6_IOM_DRAM_SDQS3	0x020e051c
+#define MX6_IOM_DRAM_SDQS4	0x020e0518
+#define MX6_IOM_DRAM_SDQS5	0x020e050c
+#define MX6_IOM_DRAM_SDQS6	0x020e05b8
+#define MX6_IOM_DRAM_SDQS7	0x020e05c0
+
+#define MX6_IOM_GRP_B0DS	0x020e0784
+#define MX6_IOM_GRP_B1DS	0x020e0788
+#define MX6_IOM_GRP_B2DS	0x020e0794
+#define MX6_IOM_GRP_B3DS	0x020e079c
+#define MX6_IOM_GRP_B4DS	0x020e07a0
+#define MX6_IOM_GRP_B5DS	0x020e07a4
+#define MX6_IOM_GRP_B6DS	0x020e07a8
+#define MX6_IOM_GRP_B7DS	0x020e0748
+#define MX6_IOM_GRP_ADDDS	0x020e074c
+#define MX6_IOM_DDRMODE_CTL	0x020e0750
+#define MX6_IOM_GRP_DDRPKE	0x020e0758
+#define MX6_IOM_GRP_DDRMODE	0x020e0774
+#define MX6_IOM_GRP_CTLDS	0x020e078c
+#define MX6_IOM_GRP_DDR_TYPE	0x020e0798
+
+#endif	/*__ASM_ARCH_MX6Q_DDR_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q_pins.h
new file mode 100644
index 000000000..a8456a284
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -0,0 +1,1036 @@
+/*
+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Auto Generate file, please don't edit it
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__
+#define __ASM_ARCH_MX6_MX6Q_PINS_H__
+
+MX6_PAD_DECL(SD2_DAT1__SD2_DATA1,	0x0360, 0x004C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__ECSPI5_SS0,	0x0360, 0x004C, 1, 0x0834, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B,	0x0360, 0x004C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS,	0x0360, 0x004C, 3, 0x07C8, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__KEY_COL7,	0x0360, 0x004C, 4, 0x08F0, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14,	0x0360, 0x004C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__SD2_DATA2,	0x0364, 0x0050, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__ECSPI5_SS1,	0x0364, 0x0050, 1, 0x0838, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B,	0x0364, 0x0050, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__AUD4_TXD,	0x0364, 0x0050, 3, 0x07B8, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__KEY_ROW6,	0x0364, 0x0050, 4, 0x08F8, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13,	0x0364, 0x0050, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__SD2_DATA0,	0x0368, 0x0054, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__ECSPI5_MISO,	0x0368, 0x0054, 1, 0x082C, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__AUD4_RXD,	0x0368, 0x0054, 3, 0x07B4, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__KEY_ROW7,	0x0368, 0x0054, 4, 0x08FC, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15,	0x0368, 0x0054, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT,	0x0368, 0x0054, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA,	0x036C, 0x0058, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__RGMII_TXC,	0x036C, 0x0058, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK,	0x036C, 0x0058, 2, 0x0918, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19,	0x036C, 0x0058, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M,	0x036C, 0x0058, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY,	0x0370, 0x005C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__RGMII_TD0,	0x0370, 0x005C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20,	0x0370, 0x005C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG,	0x0374, 0x0060, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__RGMII_TD1,	0x0374, 0x0060, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21,	0x0374, 0x0060, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA,	0x0378, 0x0064, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__RGMII_TD2,	0x0378, 0x0064, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22,	0x0378, 0x0064, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE,	0x037C, 0x0068, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__RGMII_TD3,	0x037C, 0x0068, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23,	0x037C, 0x0068, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA,	0x0380, 0x006C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL,	0x0380, 0x006C, 1, 0x0858, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24,	0x0380, 0x006C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY,	0x0384, 0x0070, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__RGMII_RD0,	0x0384, 0x0070, 1, 0x0848, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25,	0x0384, 0x0070, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE,	0x0388, 0x0074, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL,	0x0388, 0x0074, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26,	0x0388, 0x0074, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK,	0x0388, 0x0074, 7 | IOMUX_CONFIG_SION, 0x083C, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG,	0x038C, 0x0078, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__RGMII_RD1,	0x038C, 0x0078, 1, 0x084C, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27,	0x038C, 0x0078, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA,	0x0390, 0x007C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__RGMII_RD2,	0x0390, 0x007C, 1, 0x0850, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28,	0x0390, 0x007C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE,	0x0394, 0x0080, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__RGMII_RD3,	0x0394, 0x0080, 1, 0x0854, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29,	0x0394, 0x0080, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE,	0x0398, 0x0084, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__RGMII_RXC,	0x0398, 0x0084, 1, 0x0844, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30,	0x0398, 0x0084, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__EIM_ADDR25,	0x039C, 0x0088, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI4_SS1,	0x039C, 0x0088, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI2_RDY,	0x039C, 0x0088, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12,	0x039C, 0x0088, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS,	0x039C, 0x0088, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__GPIO5_IO02,	0x039C, 0x0088, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE,	0x039C, 0x0088, 6, 0x088C, 0, 0)
+MX6_PAD_DECL(EIM_EB2__EIM_EB2_B,	0x03A0, 0x008C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0,	0x03A0, 0x008C, 1, 0x0800, 0, 0)
+MX6_PAD_DECL(EIM_EB2__IPU2_CSI1_DATA19,	0x03A0, 0x008C, 3, 0x08D4, 0, 0)
+MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL,	0x03A0, 0x008C, 4, 0x0890, 0, 0)
+MX6_PAD_DECL(EIM_EB2__GPIO2_IO30,	0x03A0, 0x008C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__I2C2_SCL,	0x03A0, 0x008C, 22, 0x08A0, 0, 0)
+MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30,	0x03A0, 0x008C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__EIM_DATA16,	0x03A4, 0x0090, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK,	0x03A4, 0x0090, 1, 0x07F4, 0, 0)
+MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05,	0x03A4, 0x0090, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__IPU2_CSI1_DATA18,	0x03A4, 0x0090, 3, 0x08D0, 0, 0)
+MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA,	0x03A4, 0x0090, 4, 0x0894, 0, 0)
+MX6_PAD_DECL(EIM_D16__GPIO3_IO16,	0x03A4, 0x0090, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__I2C2_SDA,	0x03A4, 0x0090, 22, 0x08A4, 0, 0)
+MX6_PAD_DECL(EIM_D17__EIM_DATA17,	0x03A8, 0x0094, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__ECSPI1_MISO,	0x03A8, 0x0094, 1, 0x07F8, 0, 0)
+MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06,	0x03A8, 0x0094, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__IPU2_CSI1_PIXCLK,	0x03A8, 0x0094, 3, 0x08E0, 0, 0)
+MX6_PAD_DECL(EIM_D17__DCIC1_OUT,	0x03A8, 0x0094, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__GPIO3_IO17,	0x03A8, 0x0094, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__I2C3_SCL,	0x03A8, 0x0094, 22, 0x08A8, 0, 0)
+MX6_PAD_DECL(EIM_D18__EIM_DATA18,	0x03AC, 0x0098, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI,	0x03AC, 0x0098, 1, 0x07FC, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07,	0x03AC, 0x0098, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU2_CSI1_DATA17,	0x03AC, 0x0098, 3, 0x08CC, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS,	0x03AC, 0x0098, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__GPIO3_IO18,	0x03AC, 0x0098, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__I2C3_SDA,	0x03AC, 0x0098, 22, 0x08AC, 0, 0)
+MX6_PAD_DECL(EIM_D19__EIM_DATA19,	0x03B0, 0x009C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__ECSPI1_SS1,	0x03B0, 0x009C, 1, 0x0804, 0, 0)
+MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08,	0x03B0, 0x009C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__IPU2_CSI1_DATA16,	0x03B0, 0x009C, 3, 0x08C8, 0, 0)
+MX6_PAD_DECL(EIM_D19__UART1_CTS_B,	0x03B0, 0x009C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__UART1_RTS_B,	0x03B0, 0x009C, 4, 0x091C, 0, 0)
+MX6_PAD_DECL(EIM_D19__GPIO3_IO19,	0x03B0, 0x009C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EPIT1_OUT,	0x03B0, 0x009C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EIM_DATA20,	0x03B4, 0x00A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__ECSPI4_SS0,	0x03B4, 0x00A0, 1, 0x0824, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16,	0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU2_CSI1_DATA15,	0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
+MX6_PAD_DECL(EIM_D20__UART1_CTS_B,	0x03B4, 0x00A0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__UART1_RTS_B,	0x03B4, 0x00A0, 4, 0x091C, 1, 0)
+MX6_PAD_DECL(EIM_D20__GPIO3_IO20,	0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EPIT2_OUT,	0x03B4, 0x00A0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__EIM_DATA21,	0x03B8, 0x00A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK,	0x03B8, 0x00A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17,	0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU2_CSI1_DATA11,	0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
+MX6_PAD_DECL(EIM_D21__USB_OTG_OC,	0x03B8, 0x00A4, 4, 0x0944, 0, 0)
+MX6_PAD_DECL(EIM_D21__GPIO3_IO21,	0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__I2C1_SCL,	0x03B8, 0x00A4, 22, 0x0898, 0, 0)
+MX6_PAD_DECL(EIM_D21__SPDIF_IN,	0x03B8, 0x00A4, 7, 0x0914, 0, 0)
+MX6_PAD_DECL(EIM_D22__EIM_DATA22,	0x03BC, 0x00A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__ECSPI4_MISO,	0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01,	0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU2_CSI1_DATA10,	0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
+MX6_PAD_DECL(EIM_D22__USB_OTG_PWR,	0x03BC, 0x00A8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__GPIO3_IO22,	0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__SPDIF_OUT,	0x03BC, 0x00A8, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__EIM_DATA23,	0x03C0, 0x00AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS,	0x03C0, 0x00AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_CTS_B,	0x03C0, 0x00AC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_RTS_B,	0x03C0, 0x00AC, 2, 0x092C, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART1_DCD_B,	0x03C0, 0x00AC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU2_CSI1_DATA_EN,	0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
+MX6_PAD_DECL(EIM_D23__GPIO3_IO23,	0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02,	0x03C0, 0x00AC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14,	0x03C0, 0x00AC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EIM_EB3_B,	0x03C4, 0x00B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY,	0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_CTS_B,	0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_RTS_B,	0x03C4, 0x00B0, 2, 0x092C, 1, 0)
+MX6_PAD_DECL(EIM_EB3__UART1_RI_B,	0x03C4, 0x00B0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU2_CSI1_HSYNC,	0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
+MX6_PAD_DECL(EIM_EB3__GPIO2_IO31,	0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03,	0x03C4, 0x00B0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31,	0x03C4, 0x00B0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__EIM_DATA24,	0x03C8, 0x00B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI4_SS2,	0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_TX_DATA,	0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_RX_DATA,	0x03C8, 0x00B4, 2, 0x0930, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI1_SS2,	0x03C8, 0x00B4, 3, 0x0808, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI2_SS2,	0x03C8, 0x00B4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__GPIO3_IO24,	0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__AUD5_RXFS,	0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART1_DTR_B,	0x03C8, 0x00B4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__EIM_DATA25,	0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI4_SS3,	0x03CC, 0x00B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_TX_DATA,	0x03CC, 0x00B8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_RX_DATA,	0x03CC, 0x00B8, 2, 0x0930, 1, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI1_SS3,	0x03CC, 0x00B8, 3, 0x080C, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI2_SS3,	0x03CC, 0x00B8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__GPIO3_IO25,	0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__AUD5_RXC,	0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART1_DSR_B,	0x03CC, 0x00B8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__EIM_DATA26,	0x03D0, 0x00BC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11,	0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01,	0x03D0, 0x00BC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU2_CSI1_DATA14,	0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
+MX6_PAD_DECL(EIM_D26__UART2_TX_DATA,	0x03D0, 0x00BC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__UART2_RX_DATA,	0x03D0, 0x00BC, 4, 0x0928, 0, 0)
+MX6_PAD_DECL(EIM_D26__GPIO3_IO26,	0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_SISG2,	0x03D0, 0x00BC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22,	0x03D0, 0x00BC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__EIM_DATA27,	0x03D4, 0x00C0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13,	0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00,	0x03D4, 0x00C0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU2_CSI1_DATA13,	0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
+MX6_PAD_DECL(EIM_D27__UART2_TX_DATA,	0x03D4, 0x00C0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__UART2_RX_DATA,	0x03D4, 0x00C0, 4, 0x0928, 1, 0)
+MX6_PAD_DECL(EIM_D27__GPIO3_IO27,	0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_SISG3,	0x03D4, 0x00C0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23,	0x03D4, 0x00C0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__EIM_DATA28,	0x03D8, 0x00C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__I2C1_SDA,	0x03D8, 0x00C4, 17, 0x089C, 0, 0)
+MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI,	0x03D8, 0x00C4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU2_CSI1_DATA12,	0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B,	0x03D8, 0x00C4, 4, 0x0924, 0, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B,	0x03D8, 0x00C4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__GPIO3_IO28,	0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG,	0x03D8, 0x00C4, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13,	0x03D8, 0x00C4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__EIM_DATA29,	0x03DC, 0x00C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15,	0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__ECSPI4_SS0,	0x03DC, 0x00C8, 2, 0x0824, 1, 0)
+MX6_PAD_DECL(EIM_D29__UART2_CTS_B,	0x03DC, 0x00C8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__UART2_RTS_B,	0x03DC, 0x00C8, 4, 0x0924, 1, 0)
+MX6_PAD_DECL(EIM_D29__GPIO3_IO29,	0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU2_CSI1_VSYNC,	0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14,	0x03DC, 0x00C8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__EIM_DATA30,	0x03E0, 0x00CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21,	0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11,	0x03E0, 0x00CC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03,	0x03E0, 0x00CC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_CTS_B,	0x03E0, 0x00CC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_RTS_B,	0x03E0, 0x00CC, 4, 0x092C, 2, 0)
+MX6_PAD_DECL(EIM_D30__GPIO3_IO30,	0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__USB_H1_OC,	0x03E0, 0x00CC, 6, 0x0948, 0, 0)
+MX6_PAD_DECL(EIM_D31__EIM_DATA31,	0x03E4, 0x00D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20,	0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12,	0x03E4, 0x00D0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02,	0x03E4, 0x00D0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_CTS_B,	0x03E4, 0x00D0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_RTS_B,	0x03E4, 0x00D0, 4, 0x092C, 3, 0)
+MX6_PAD_DECL(EIM_D31__GPIO3_IO31,	0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__USB_H1_PWR,	0x03E4, 0x00D0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__EIM_ADDR24,	0x03E8, 0x00D4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19,	0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU2_CSI1_DATA19,	0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
+MX6_PAD_DECL(EIM_A24__IPU2_SISG2,	0x03E8, 0x00D4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_SISG2,	0x03E8, 0x00D4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__GPIO5_IO04,	0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24,	0x03E8, 0x00D4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__EIM_ADDR23,	0x03EC, 0x00D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18,	0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU2_CSI1_DATA18,	0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
+MX6_PAD_DECL(EIM_A23__IPU2_SISG3,	0x03EC, 0x00D8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_SISG3,	0x03EC, 0x00D8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__GPIO6_IO06,	0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23,	0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__EIM_ADDR22,	0x03F0, 0x00DC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17,	0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU2_CSI1_DATA17,	0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
+MX6_PAD_DECL(EIM_A22__GPIO2_IO16,	0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22,	0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__EIM_ADDR21,	0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16,	0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU2_CSI1_DATA16,	0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
+MX6_PAD_DECL(EIM_A21__GPIO2_IO17,	0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21,	0x03F4, 0x00E0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__EIM_ADDR20,	0x03F8, 0x00E4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15,	0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU2_CSI1_DATA15,	0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
+MX6_PAD_DECL(EIM_A20__GPIO2_IO18,	0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20,	0x03F8, 0x00E4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__EIM_ADDR19,	0x03FC, 0x00E8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14,	0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU2_CSI1_DATA14,	0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
+MX6_PAD_DECL(EIM_A19__GPIO2_IO19,	0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19,	0x03FC, 0x00E8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__EIM_ADDR18,	0x0400, 0x00EC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13,	0x0400, 0x00EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU2_CSI1_DATA13,	0x0400, 0x00EC, 2, 0x08BC, 1, 0)
+MX6_PAD_DECL(EIM_A18__GPIO2_IO20,	0x0400, 0x00EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18,	0x0400, 0x00EC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__EIM_ADDR17,	0x0404, 0x00F0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12,	0x0404, 0x00F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU2_CSI1_DATA12,	0x0404, 0x00F0, 2, 0x08B8, 1, 0)
+MX6_PAD_DECL(EIM_A17__GPIO2_IO21,	0x0404, 0x00F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17,	0x0404, 0x00F0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__EIM_ADDR16,	0x0408, 0x00F4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK,	0x0408, 0x00F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU2_CSI1_PIXCLK,	0x0408, 0x00F4, 2, 0x08E0, 1, 0)
+MX6_PAD_DECL(EIM_A16__GPIO2_IO22,	0x0408, 0x00F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16,	0x0408, 0x00F4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__EIM_CS0_B,	0x040C, 0x00F8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05,	0x040C, 0x00F8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK,	0x040C, 0x00F8, 2, 0x0810, 0, 0)
+MX6_PAD_DECL(EIM_CS0__GPIO2_IO23,	0x040C, 0x00F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__EIM_CS1_B,	0x0410, 0x00FC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06,	0x0410, 0x00FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI,	0x0410, 0x00FC, 2, 0x0818, 0, 0)
+MX6_PAD_DECL(EIM_CS1__GPIO2_IO24,	0x0410, 0x00FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__EIM_OE_B,	0x0414, 0x0100, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07,	0x0414, 0x0100, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__ECSPI2_MISO,	0x0414, 0x0100, 2, 0x0814, 0, 0)
+MX6_PAD_DECL(EIM_OE__GPIO2_IO25,	0x0414, 0x0100, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__EIM_RW,	0x0418, 0x0104, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08,	0x0418, 0x0104, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__ECSPI2_SS0,	0x0418, 0x0104, 2, 0x081C, 0, 0)
+MX6_PAD_DECL(EIM_RW__GPIO2_IO26,	0x0418, 0x0104, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29,	0x0418, 0x0104, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__EIM_LBA_B,	0x041C, 0x0108, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17,	0x041C, 0x0108, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1,	0x041C, 0x0108, 2, 0x0820, 0, 0)
+MX6_PAD_DECL(EIM_LBA__GPIO2_IO27,	0x041C, 0x0108, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26,	0x041C, 0x0108, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__EIM_EB0_B,	0x0420, 0x010C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11,	0x0420, 0x010C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU2_CSI1_DATA11,	0x0420, 0x010C, 2, 0x08B4, 1, 0)
+MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY,	0x0420, 0x010C, 4, 0x07F0, 0, 0)
+MX6_PAD_DECL(EIM_EB0__GPIO2_IO28,	0x0420, 0x010C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27,	0x0420, 0x010C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__EIM_EB1_B,	0x0424, 0x0110, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10,	0x0424, 0x0110, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU2_CSI1_DATA10,	0x0424, 0x0110, 2, 0x08B0, 1, 0)
+MX6_PAD_DECL(EIM_EB1__GPIO2_IO29,	0x0424, 0x0110, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28,	0x0424, 0x0110, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__EIM_AD00,	0x0428, 0x0114, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09,	0x0428, 0x0114, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU2_CSI1_DATA09,	0x0428, 0x0114, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__GPIO3_IO00,	0x0428, 0x0114, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00,	0x0428, 0x0114, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__EIM_AD01,	0x042C, 0x0118, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08,	0x042C, 0x0118, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU2_CSI1_DATA08,	0x042C, 0x0118, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__GPIO3_IO01,	0x042C, 0x0118, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01,	0x042C, 0x0118, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__EIM_AD02,	0x0430, 0x011C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07,	0x0430, 0x011C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU2_CSI1_DATA07,	0x0430, 0x011C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__GPIO3_IO02,	0x0430, 0x011C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02,	0x0430, 0x011C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__EIM_AD03,	0x0434, 0x0120, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06,	0x0434, 0x0120, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU2_CSI1_DATA06,	0x0434, 0x0120, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__GPIO3_IO03,	0x0434, 0x0120, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03,	0x0434, 0x0120, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__EIM_AD04,	0x0438, 0x0124, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05,	0x0438, 0x0124, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU2_CSI1_DATA05,	0x0438, 0x0124, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__GPIO3_IO04,	0x0438, 0x0124, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04,	0x0438, 0x0124, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__EIM_AD05,	0x043C, 0x0128, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04,	0x043C, 0x0128, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU2_CSI1_DATA04,	0x043C, 0x0128, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__GPIO3_IO05,	0x043C, 0x0128, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05,	0x043C, 0x0128, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__EIM_AD06,	0x0440, 0x012C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03,	0x0440, 0x012C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU2_CSI1_DATA03,	0x0440, 0x012C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__GPIO3_IO06,	0x0440, 0x012C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06,	0x0440, 0x012C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__EIM_AD07,	0x0444, 0x0130, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02,	0x0444, 0x0130, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU2_CSI1_DATA02,	0x0444, 0x0130, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__GPIO3_IO07,	0x0444, 0x0130, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07,	0x0444, 0x0130, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__EIM_AD08,	0x0448, 0x0134, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01,	0x0448, 0x0134, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU2_CSI1_DATA01,	0x0448, 0x0134, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__GPIO3_IO08,	0x0448, 0x0134, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08,	0x0448, 0x0134, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__EIM_AD09,	0x044C, 0x0138, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00,	0x044C, 0x0138, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU2_CSI1_DATA00,	0x044C, 0x0138, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__GPIO3_IO09,	0x044C, 0x0138, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09,	0x044C, 0x0138, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__EIM_AD10,	0x0450, 0x013C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15,	0x0450, 0x013C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU2_CSI1_DATA_EN,	0x0450, 0x013C, 2, 0x08D8, 1, 0)
+MX6_PAD_DECL(EIM_DA10__GPIO3_IO10,	0x0450, 0x013C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10,	0x0450, 0x013C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__EIM_AD11,	0x0454, 0x0140, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02,	0x0454, 0x0140, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU2_CSI1_HSYNC,	0x0454, 0x0140, 2, 0x08DC, 1, 0)
+MX6_PAD_DECL(EIM_DA11__GPIO3_IO11,	0x0454, 0x0140, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11,	0x0454, 0x0140, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__EIM_AD12,	0x0458, 0x0144, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03,	0x0458, 0x0144, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU2_CSI1_VSYNC,	0x0458, 0x0144, 2, 0x08E4, 1, 0)
+MX6_PAD_DECL(EIM_DA12__GPIO3_IO12,	0x0458, 0x0144, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12,	0x0458, 0x0144, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__EIM_AD13,	0x045C, 0x0148, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS,	0x045C, 0x0148, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__GPIO3_IO13,	0x045C, 0x0148, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13,	0x045C, 0x0148, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__EIM_AD14,	0x0460, 0x014C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS,	0x0460, 0x014C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__GPIO3_IO14,	0x0460, 0x014C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14,	0x0460, 0x014C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__EIM_AD15,	0x0464, 0x0150, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01,	0x0464, 0x0150, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04,	0x0464, 0x0150, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__GPIO3_IO15,	0x0464, 0x0150, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15,	0x0464, 0x0150, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B,	0x0468, 0x0154, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B,	0x0468, 0x0154, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00,	0x0468, 0x0154, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25,	0x0468, 0x0154, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__EIM_BCLK,	0x046C, 0x0158, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16,	0x046C, 0x0158, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31,	0x046C, 0x0158, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_DISP_CLK__IPU2_DI0_DISP_CLK,	0x0470, 0x015C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16,	0x0470, 0x015C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15,	0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN15__IPU2_DI0_PIN15,	0x0474, 0x0160, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__AUD6_TXC,	0x0474, 0x0160, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17,	0x0474, 0x0160, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02,	0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN2__IPU2_DI0_PIN02,	0x0478, 0x0164, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__AUD6_TXD,	0x0478, 0x0164, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18,	0x0478, 0x0164, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03,	0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN3__IPU2_DI0_PIN03,	0x047C, 0x0168, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS,	0x047C, 0x0168, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19,	0x047C, 0x0168, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04,	0x0480, 0x016C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__IPU2_DI0_PIN04,	0x0480, 0x016C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__AUD6_RXD,	0x0480, 0x016C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__SD1_WP,	0x0480, 0x016C, 3, 0x094C, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20,	0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00,	0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT0__IPU2_DISP0_DATA00,	0x0484, 0x0170, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK,	0x0484, 0x0170, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21,	0x0484, 0x0170, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01,	0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT1__IPU2_DISP0_DATA01,	0x0488, 0x0174, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI,	0x0488, 0x0174, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22,	0x0488, 0x0174, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02,	0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT2__IPU2_DISP0_DATA02,	0x048C, 0x0178, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO,	0x048C, 0x0178, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23,	0x048C, 0x0178, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03,	0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT3__IPU2_DISP0_DATA03,	0x0490, 0x017C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0,	0x0490, 0x017C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24,	0x0490, 0x017C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04,	0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT4__IPU2_DISP0_DATA04,	0x0494, 0x0180, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1,	0x0494, 0x0180, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25,	0x0494, 0x0180, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05,	0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT5__IPU2_DISP0_DATA05,	0x0498, 0x0184, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2,	0x0498, 0x0184, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS,	0x0498, 0x0184, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26,	0x0498, 0x0184, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06,	0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT6__IPU2_DISP0_DATA06,	0x049C, 0x0188, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3,	0x049C, 0x0188, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC,	0x049C, 0x0188, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27,	0x049C, 0x0188, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07,	0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT7__IPU2_DISP0_DATA07,	0x04A0, 0x018C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY,	0x04A0, 0x018C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28,	0x04A0, 0x018C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08,	0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT8__IPU2_DISP0_DATA08,	0x04A4, 0x0190, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT,	0x04A4, 0x0190, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__WDOG1_B,	0x04A4, 0x0190, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29,	0x04A4, 0x0190, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09,	0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT9__IPU2_DISP0_DATA09,	0x04A8, 0x0194, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT,	0x04A8, 0x0194, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__WDOG2_B,	0x04A8, 0x0194, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30,	0x04A8, 0x0194, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10,	0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT10__IPU2_DISP0_DATA10,	0x04AC, 0x0198, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31,	0x04AC, 0x0198, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11,	0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT11__IPU2_DISP0_DATA11,	0x04B0, 0x019C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05,	0x04B0, 0x019C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12,	0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT12__IPU2_DISP0_DATA12,	0x04B4, 0x01A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06,	0x04B4, 0x01A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13,	0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT13__IPU2_DISP0_DATA13,	0x04B8, 0x01A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS,	0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07,	0x04B8, 0x01A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14,	0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT14__IPU2_DISP0_DATA14,	0x04BC, 0x01A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC,	0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08,	0x04BC, 0x01A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15,	0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT15__IPU2_DISP0_DATA15,	0x04C0, 0x01AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1,	0x04C0, 0x01AC, 2, 0x0804, 1, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1,	0x04C0, 0x01AC, 3, 0x0820, 1, 0)
+MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09,	0x04C0, 0x01AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16,	0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT16__IPU2_DISP0_DATA16,	0x04C4, 0x01B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI,	0x04C4, 0x01B0, 2, 0x0818, 1, 0)
+MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC,	0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0,	0x04C4, 0x01B0, 4, 0x090C, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10,	0x04C4, 0x01B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17,	0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT17__IPU2_DISP0_DATA17,	0x04C8, 0x01B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO,	0x04C8, 0x01B4, 2, 0x0814, 1, 0)
+MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD,	0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1,	0x04C8, 0x01B4, 4, 0x0910, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11,	0x04C8, 0x01B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18,	0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT18__IPU2_DISP0_DATA18,	0x04CC, 0x01B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0,	0x04CC, 0x01B8, 2, 0x081C, 1, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS,	0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS,	0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12,	0x04CC, 0x01B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B,	0x04CC, 0x01B8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19,	0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT19__IPU2_DISP0_DATA19,	0x04D0, 0x01BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK,	0x04D0, 0x01BC, 2, 0x0810, 1, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD,	0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC,	0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13,	0x04D0, 0x01BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B,	0x04D0, 0x01BC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20,	0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT20__IPU2_DISP0_DATA20,	0x04D4, 0x01C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK,	0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC,	0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14,	0x04D4, 0x01C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21,	0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT21__IPU2_DISP0_DATA21,	0x04D8, 0x01C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI,	0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
+MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD,	0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15,	0x04D8, 0x01C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22,	0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT22__IPU2_DISP0_DATA22,	0x04DC, 0x01C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO,	0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS,	0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16,	0x04DC, 0x01C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23,	0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT23__IPU2_DISP0_DATA23,	0x04E0, 0x01CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0,	0x04E0, 0x01CC, 2, 0x0800, 1, 0)
+MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD,	0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17,	0x04E0, 0x01CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_MDIO,	0x04E4, 0x01D0, 1, 0x0840, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK,	0x04E4, 0x01D0, 2, 0x086C, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT,	0x04E4, 0x01D0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22,	0x04E4, 0x01D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK,	0x04E4, 0x01D0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK,	0x04E8, 0x01D4, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS,	0x04E8, 0x01D4, 2, 0x085C, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23,	0x04E8, 0x01D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK,	0x04E8, 0x01D4, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID,	0x04EC, 0x01D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER,	0x04EC, 0x01D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK,	0x04EC, 0x01D8, 2, 0x0864, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN,	0x04EC, 0x01D8, 3, 0x0914, 1, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT,	0x04EC, 0x01D8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24,	0x04EC, 0x01D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN,	0x04F0, 0x01DC, 1, 0x0858, 1, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK,	0x04F0, 0x01DC, 2, 0x0870, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK,	0x04F0, 0x01DC, 3, 0x0918, 1, 0)
+MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25,	0x04F0, 0x01DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__MLB_SIG,	0x04F4, 0x01E0, 0, 0x0908, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1,	0x04F4, 0x01E0, 1, 0x084C, 1, 0)
+MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS,	0x04F4, 0x01E0, 2, 0x0860, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT,	0x04F4, 0x01E0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26,	0x04F4, 0x01E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0,	0x04F8, 0x01E4, 1, 0x0848, 1, 0)
+MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK,	0x04F8, 0x01E4, 2, 0x0868, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT,	0x04F8, 0x01E4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27,	0x04F8, 0x01E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN,	0x04FC, 0x01E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2,	0x04FC, 0x01E8, 2, 0x0880, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28,	0x04FC, 0x01E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__MLB_CLK,	0x0500, 0x01EC, 0, 0x0900, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1,	0x0500, 0x01EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3,	0x0500, 0x01EC, 2, 0x087C, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN,	0x0500, 0x01EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29,	0x0500, 0x01EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0,	0x0504, 0x01F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1,	0x0504, 0x01F0, 2, 0x0884, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30,	0x0504, 0x01F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__MLB_DATA,	0x0508, 0x01F4, 0, 0x0904, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_MDC,	0x0508, 0x01F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0,	0x0508, 0x01F4, 2, 0x0888, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN,	0x0508, 0x01F4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__GPIO1_IO31,	0x0508, 0x01F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK,	0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
+MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3,	0x05C8, 0x01F8, 1, 0x0854, 1, 0)
+MX6_PAD_DECL(KEY_COL0__AUD5_TXC,	0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
+MX6_PAD_DECL(KEY_COL0__KEY_COL0,	0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA,	0x05C8, 0x01F8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA,	0x05C8, 0x01F8, 4, 0x0938, 0, 0)
+MX6_PAD_DECL(KEY_COL0__GPIO4_IO06,	0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__DCIC1_OUT,	0x05C8, 0x01F8, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI,	0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
+MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3,	0x05CC, 0x01FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__AUD5_TXD,	0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
+MX6_PAD_DECL(KEY_ROW0__KEY_ROW0,	0x05CC, 0x01FC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA,	0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA,	0x05CC, 0x01FC, 4, 0x0938, 1, 0)
+MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07,	0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT,	0x05CC, 0x01FC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO,	0x05D0, 0x0200, 0, 0x07F8, 2, 0)
+MX6_PAD_DECL(KEY_COL1__ENET_MDIO,	0x05D0, 0x0200, 1, 0x0840, 1, 0)
+MX6_PAD_DECL(KEY_COL1__AUD5_TXFS,	0x05D0, 0x0200, 2, 0x07E0, 1, 0)
+MX6_PAD_DECL(KEY_COL1__KEY_COL1,	0x05D0, 0x0200, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA,	0x05D0, 0x0200, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA,	0x05D0, 0x0200, 4, 0x0940, 0, 0)
+MX6_PAD_DECL(KEY_COL1__GPIO4_IO08,	0x05D0, 0x0200, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__SD1_VSELECT,	0x05D0, 0x0200, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0,	0x05D4, 0x0204, 0, 0x0800, 2, 0)
+MX6_PAD_DECL(KEY_ROW1__ENET_COL,	0x05D4, 0x0204, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__AUD5_RXD,	0x05D4, 0x0204, 2, 0x07CC, 1, 0)
+MX6_PAD_DECL(KEY_ROW1__KEY_ROW1,	0x05D4, 0x0204, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA,	0x05D4, 0x0204, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA,	0x05D4, 0x0204, 4, 0x0940, 1, 0)
+MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09,	0x05D4, 0x0204, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT,	0x05D4, 0x0204, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1,	0x05D8, 0x0208, 0, 0x0804, 2, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2,	0x05D8, 0x0208, 1, 0x0850, 1, 0)
+MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX,	0x05D8, 0x0208, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__KEY_COL2,	0x05D8, 0x0208, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_MDC,	0x05D8, 0x0208, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__GPIO4_IO10,	0x05D8, 0x0208, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE,	0x05D8, 0x0208, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2,	0x05DC, 0x020C, 0, 0x0808, 1, 0)
+MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2,	0x05DC, 0x020C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX,	0x05DC, 0x020C, 2, 0x07E4, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__KEY_ROW2,	0x05DC, 0x020C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT,	0x05DC, 0x020C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11,	0x05DC, 0x020C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE,	0x05DC, 0x020C, 6, 0x088C, 1, 0)
+MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3,	0x05E0, 0x0210, 0, 0x080C, 1, 0)
+MX6_PAD_DECL(KEY_COL3__ENET_CRS,	0x05E0, 0x0210, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL,	0x05E0, 0x0210, 2, 0x0890, 1, 0)
+MX6_PAD_DECL(KEY_COL3__KEY_COL3,	0x05E0, 0x0210, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__I2C2_SCL,	0x05E0, 0x0210, 20, 0x08A0, 1, 0)
+MX6_PAD_DECL(KEY_COL3__GPIO4_IO12,	0x05E0, 0x0210, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__SPDIF_IN,	0x05E0, 0x0210, 6, 0x0914, 2, 0)
+MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK,	0x05E4, 0x0214, 1, 0x07B0, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA,	0x05E4, 0x0214, 2, 0x0894, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__KEY_ROW3,	0x05E4, 0x0214, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__I2C2_SDA,	0x05E4, 0x0214, 20, 0x08A4, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13,	0x05E4, 0x0214, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT,	0x05E4, 0x0214, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX,	0x05E8, 0x0218, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__IPU1_SISG4,	0x05E8, 0x0218, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__USB_OTG_OC,	0x05E8, 0x0218, 2, 0x0944, 1, 0)
+MX6_PAD_DECL(KEY_COL4__KEY_COL4,	0x05E8, 0x0218, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_CTS_B,	0x05E8, 0x0218, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_RTS_B,	0x05E8, 0x0218, 4, 0x093C, 0, 0)
+MX6_PAD_DECL(KEY_COL4__GPIO4_IO14,	0x05E8, 0x0218, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX,	0x05EC, 0x021C, 0, 0x07E8, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5,	0x05EC, 0x021C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR,	0x05EC, 0x021C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__KEY_ROW4,	0x05EC, 0x021C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B,	0x05EC, 0x021C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B,	0x05EC, 0x021C, 4, 0x093C, 1, 0)
+MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15,	0x05EC, 0x021C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__CCM_CLKO1,	0x05F0, 0x0220, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__KEY_COL5,	0x05F0, 0x0220, 2, 0x08E8, 0, 0)
+MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK,	0x05F0, 0x0220, 3, 0x07B0, 1, 0)
+MX6_PAD_DECL(GPIO_0__EPIT1_OUT,	0x05F0, 0x0220, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__GPIO1_IO00,	0x05F0, 0x0220, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__USB_H1_PWR,	0x05F0, 0x0220, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__SNVS_VIO_5,	0x05F0, 0x0220, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK,	0x05F4, 0x0224, 0, 0x086C, 1, 0)
+MX6_PAD_DECL(GPIO_1__WDOG2_B,	0x05F4, 0x0224, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__KEY_ROW5,	0x05F4, 0x0224, 2, 0x08F4, 0, 0)
+MX6_PAD_DECL(GPIO_1__USB_OTG_ID,	0x05F4, 0x0224, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__PWM2_OUT,	0x05F4, 0x0224, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__GPIO1_IO01,	0x05F4, 0x0224, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__SD1_CD_B,	0x05F4, 0x0224, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__ESAI_RX_FS,	0x05F8, 0x0228, 0, 0x085C, 1, 0)
+MX6_PAD_DECL(GPIO_9__WDOG1_B,	0x05F8, 0x0228, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__KEY_COL6,	0x05F8, 0x0228, 2, 0x08EC, 0, 0)
+MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B,	0x05F8, 0x0228, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__PWM1_OUT,	0x05F8, 0x0228, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__GPIO1_IO09,	0x05F8, 0x0228, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__SD1_WP,	0x05F8, 0x0228, 6, 0x094C, 1, 0)
+MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK,	0x05FC, 0x022C, 0, 0x0864, 1, 0)
+MX6_PAD_DECL(GPIO_3__I2C3_SCL,	0x05FC, 0x022C, 18, 0x08A8, 1, 0)
+MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M,	0x05FC, 0x022C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__CCM_CLKO2,	0x05FC, 0x022C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__GPIO1_IO03,	0x05FC, 0x022C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__USB_H1_OC,	0x05FC, 0x022C, 6, 0x0948, 1, 0)
+MX6_PAD_DECL(GPIO_3__MLB_CLK,	0x05FC, 0x022C, 7, 0x0900, 1, 0)
+MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK,	0x0600, 0x0230, 0, 0x0870, 1, 0)
+MX6_PAD_DECL(GPIO_6__I2C3_SDA,	0x0600, 0x0230, 18, 0x08AC, 1, 0)
+MX6_PAD_DECL(GPIO_6__GPIO1_IO06,	0x0600, 0x0230, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__SD2_LCTL,	0x0600, 0x0230, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__MLB_SIG,	0x0600, 0x0230, 7, 0x0908, 1, 0)
+MX6_PAD_DECL(GPIO_2__ESAI_TX_FS,	0x0604, 0x0234, 0, 0x0860, 1, 0)
+MX6_PAD_DECL(GPIO_2__KEY_ROW6,	0x0604, 0x0234, 2, 0x08F8, 1, 0)
+MX6_PAD_DECL(GPIO_2__GPIO1_IO02,	0x0604, 0x0234, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__SD2_WP,	0x0604, 0x0234, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__MLB_DATA,	0x0604, 0x0234, 7, 0x0904, 1, 0)
+MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK,	0x0608, 0x0238, 0, 0x0868, 1, 0)
+MX6_PAD_DECL(GPIO_4__KEY_COL7,	0x0608, 0x0238, 2, 0x08F0, 1, 0)
+MX6_PAD_DECL(GPIO_4__GPIO1_IO04,	0x0608, 0x0238, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_4__SD2_CD_B,	0x0608, 0x0238, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3,	0x060C, 0x023C, 0, 0x087C, 1, 0)
+MX6_PAD_DECL(GPIO_5__KEY_ROW7,	0x060C, 0x023C, 2, 0x08FC, 1, 0)
+MX6_PAD_DECL(GPIO_5__CCM_CLKO1,	0x060C, 0x023C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__GPIO1_IO05,	0x060C, 0x023C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__I2C3_SCL,	0x060C, 0x023C, 22, 0x08A8, 2, 0)
+MX6_PAD_DECL(GPIO_5__ARM_EVENTI,	0x060C, 0x023C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1,	0x0610, 0x0240, 0, 0x0884, 1, 0)
+MX6_PAD_DECL(GPIO_7__ECSPI5_RDY,	0x0610, 0x0240, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__EPIT1_OUT,	0x0610, 0x0240, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX,	0x0610, 0x0240, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_TX_DATA,	0x0610, 0x0240, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_RX_DATA,	0x0610, 0x0240, 4, 0x0928, 2, 0)
+MX6_PAD_DECL(GPIO_7__GPIO1_IO07,	0x0610, 0x0240, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__SPDIF_LOCK,	0x0610, 0x0240, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE,	0x0610, 0x0240, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0,	0x0614, 0x0244, 0, 0x0888, 1, 0)
+MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K,	0x0614, 0x0244, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__EPIT2_OUT,	0x0614, 0x0244, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX,	0x0614, 0x0244, 3, 0x07E4, 1, 0)
+MX6_PAD_DECL(GPIO_8__UART2_TX_DATA,	0x0614, 0x0244, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__UART2_RX_DATA,	0x0614, 0x0244, 4, 0x0928, 3, 0)
+MX6_PAD_DECL(GPIO_8__GPIO1_IO08,	0x0614, 0x0244, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK,	0x0614, 0x0244, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE,	0x0614, 0x0244, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,	0x0618, 0x0248, 0, 0x0880, 1, 0)
+MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN,	0x0618, 0x0248, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,	0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0)
+MX6_PAD_DECL(GPIO_16__SD1_LCTL,	0x0618, 0x0248, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__SPDIF_IN,	0x0618, 0x0248, 4, 0x0914, 3, 0)
+MX6_PAD_DECL(GPIO_16__GPIO7_IO11,	0x0618, 0x0248, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__I2C3_SDA,	0x0618, 0x0248, 22, 0x08AC, 2, 0)
+MX6_PAD_DECL(GPIO_16__JTAG_DE_B,	0x0618, 0x0248, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__ESAI_TX0,	0x061C, 0x024C, 0, 0x0874, 0, 0)
+MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN,	0x061C, 0x024C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY,	0x061C, 0x024C, 2, 0x07F0, 1, 0)
+MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0,	0x061C, 0x024C, 3, 0x090C, 1, 0)
+MX6_PAD_DECL(GPIO_17__SPDIF_OUT,	0x061C, 0x024C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__GPIO7_IO12,	0x061C, 0x024C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__ESAI_TX1,	0x0620, 0x0250, 0, 0x0878, 0, 0)
+MX6_PAD_DECL(GPIO_18__ENET_RX_CLK,	0x0620, 0x0250, 1, 0x0844, 1, 0)
+MX6_PAD_DECL(GPIO_18__SD3_VSELECT,	0x0620, 0x0250, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1,	0x0620, 0x0250, 3, 0x0910, 1, 0)
+MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK,	0x0620, 0x0250, 4, 0x07B0, 2, 0)
+MX6_PAD_DECL(GPIO_18__GPIO7_IO13,	0x0620, 0x0250, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL,	0x0620, 0x0250, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__KEY_COL5,	0x0624, 0x0254, 0, 0x08E8, 1, 0)
+MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT,	0x0624, 0x0254, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__SPDIF_OUT,	0x0624, 0x0254, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__CCM_CLKO1,	0x0624, 0x0254, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ECSPI1_RDY,	0x0624, 0x0254, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__GPIO4_IO05,	0x0624, 0x0254, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ENET_TX_ER,	0x0624, 0x0254, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK,	0x0628, 0x0258, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18,	0x0628, 0x0258, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO,	0x0628, 0x0258, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC,	0x062C, 0x025C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1,	0x062C, 0x025C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19,	0x062C, 0x025C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL,	0x062C, 0x025C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN,	0x0630, 0x0260, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00,	0x0630, 0x0260, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20,	0x0630, 0x0260, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK,	0x0630, 0x0260, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC,	0x0634, 0x0264, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01,	0x0634, 0x0264, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21,	0x0634, 0x0264, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00,	0x0634, 0x0264, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04,	0x0638, 0x0268, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02,	0x0638, 0x0268, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK,	0x0638, 0x0268, 2, 0x07F4, 3, 0)
+MX6_PAD_DECL(CSI0_DAT4__KEY_COL5,	0x0638, 0x0268, 3, 0x08E8, 2, 0)
+MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC,	0x0638, 0x0268, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22,	0x0638, 0x0268, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01,	0x0638, 0x0268, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05,	0x063C, 0x026C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03,	0x063C, 0x026C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI,	0x063C, 0x026C, 2, 0x07FC, 3, 0)
+MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5,	0x063C, 0x026C, 3, 0x08F4, 1, 0)
+MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD,	0x063C, 0x026C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23,	0x063C, 0x026C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02,	0x063C, 0x026C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06,	0x0640, 0x0270, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04,	0x0640, 0x0270, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO,	0x0640, 0x0270, 2, 0x07F8, 3, 0)
+MX6_PAD_DECL(CSI0_DAT6__KEY_COL6,	0x0640, 0x0270, 3, 0x08EC, 1, 0)
+MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS,	0x0640, 0x0270, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24,	0x0640, 0x0270, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03,	0x0640, 0x0270, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07,	0x0644, 0x0274, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05,	0x0644, 0x0274, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0,	0x0644, 0x0274, 2, 0x0800, 3, 0)
+MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6,	0x0644, 0x0274, 3, 0x08F8, 2, 0)
+MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD,	0x0644, 0x0274, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25,	0x0644, 0x0274, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04,	0x0644, 0x0274, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08,	0x0648, 0x0278, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06,	0x0648, 0x0278, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK,	0x0648, 0x0278, 2, 0x0810, 2, 0)
+MX6_PAD_DECL(CSI0_DAT8__KEY_COL7,	0x0648, 0x0278, 3, 0x08F0, 2, 0)
+MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA,	0x0648, 0x0278, 20, 0x089C, 1, 0)
+MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26,	0x0648, 0x0278, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05,	0x0648, 0x0278, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09,	0x064C, 0x027C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07,	0x064C, 0x027C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI,	0x064C, 0x027C, 2, 0x0818, 2, 0)
+MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7,	0x064C, 0x027C, 3, 0x08FC, 2, 0)
+MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL,	0x064C, 0x027C, 20, 0x0898, 1, 0)
+MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27,	0x064C, 0x027C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06,	0x064C, 0x027C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10,	0x0650, 0x0280, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC,	0x0650, 0x0280, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO,	0x0650, 0x0280, 2, 0x0814, 2, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA,	0x0650, 0x0280, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA,	0x0650, 0x0280, 3, 0x0920, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28,	0x0650, 0x0280, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07,	0x0650, 0x0280, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11,	0x0654, 0x0284, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS,	0x0654, 0x0284, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0,	0x0654, 0x0284, 2, 0x081C, 2, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA,	0x0654, 0x0284, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA,	0x0654, 0x0284, 3, 0x0920, 1, 0)
+MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29,	0x0654, 0x0284, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08,	0x0654, 0x0284, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12,	0x0658, 0x0288, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08,	0x0658, 0x0288, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA,	0x0658, 0x0288, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA,	0x0658, 0x0288, 3, 0x0938, 2, 0)
+MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30,	0x0658, 0x0288, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09,	0x0658, 0x0288, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13,	0x065C, 0x028C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09,	0x065C, 0x028C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA,	0x065C, 0x028C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA,	0x065C, 0x028C, 3, 0x0938, 3, 0)
+MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31,	0x065C, 0x028C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10,	0x065C, 0x028C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14,	0x0660, 0x0290, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10,	0x0660, 0x0290, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA,	0x0660, 0x0290, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA,	0x0660, 0x0290, 3, 0x0940, 2, 0)
+MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00,	0x0660, 0x0290, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11,	0x0660, 0x0290, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15,	0x0664, 0x0294, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11,	0x0664, 0x0294, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA,	0x0664, 0x0294, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA,	0x0664, 0x0294, 3, 0x0940, 3, 0)
+MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01,	0x0664, 0x0294, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12,	0x0664, 0x0294, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16,	0x0668, 0x0298, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12,	0x0668, 0x0298, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B,	0x0668, 0x0298, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B,	0x0668, 0x0298, 3, 0x0934, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02,	0x0668, 0x0298, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13,	0x0668, 0x0298, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17,	0x066C, 0x029C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13,	0x066C, 0x029C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B,	0x066C, 0x029C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B,	0x066C, 0x029C, 3, 0x0934, 1, 0)
+MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03,	0x066C, 0x029C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14,	0x066C, 0x029C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18,	0x0670, 0x02A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14,	0x0670, 0x02A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B,	0x0670, 0x02A0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B,	0x0670, 0x02A0, 3, 0x093C, 2, 0)
+MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04,	0x0670, 0x02A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15,	0x0670, 0x02A0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19,	0x0674, 0x02A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15,	0x0674, 0x02A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B,	0x0674, 0x02A4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B,	0x0674, 0x02A4, 3, 0x093C, 3, 0)
+MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05,	0x0674, 0x02A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__SD3_DATA7,	0x0690, 0x02A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA,	0x0690, 0x02A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA,	0x0690, 0x02A8, 1, 0x0920, 2, 0)
+MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17,	0x0690, 0x02A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__SD3_DATA6,	0x0694, 0x02AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA,	0x0694, 0x02AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA,	0x0694, 0x02AC, 1, 0x0920, 3, 0)
+MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18,	0x0694, 0x02AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__SD3_DATA5,	0x0698, 0x02B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA,	0x0698, 0x02B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA,	0x0698, 0x02B0, 1, 0x0928, 4, 0)
+MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00,	0x0698, 0x02B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__SD3_DATA4,	0x069C, 0x02B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA,	0x069C, 0x02B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA,	0x069C, 0x02B4, 1, 0x0928, 5, 0)
+MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01,	0x069C, 0x02B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__SD3_CMD,	0x06A0, 0x02B8, 16, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_CTS_B,	0x06A0, 0x02B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_RTS_B,	0x06A0, 0x02B8, 1, 0x0924, 2, 0)
+MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX,	0x06A0, 0x02B8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__GPIO7_IO02,	0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__SD3_CLK,	0x06A4, 0x02BC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_CTS_B,	0x06A4, 0x02BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_RTS_B,	0x06A4, 0x02BC, 1, 0x0924, 3, 0)
+MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX,	0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
+MX6_PAD_DECL(SD3_CLK__GPIO7_IO03,	0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__SD3_DATA0,	0x06A8, 0x02C0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B,	0x06A8, 0x02C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B,	0x06A8, 0x02C0, 1, 0x091C, 2, 0)
+MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX,	0x06A8, 0x02C0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04,	0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__SD3_DATA1,	0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B,	0x06AC, 0x02C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B,	0x06AC, 0x02C4, 1, 0x091C, 3, 0)
+MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX,	0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
+MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05,	0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__SD3_DATA2,	0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06,	0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__SD3_DATA3,	0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B,	0x06B4, 0x02CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B,	0x06B4, 0x02CC, 1, 0x092C, 4, 0)
+MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07,	0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__SD3_RESET,	0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_CTS_B,	0x06B8, 0x02D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_RTS_B,	0x06B8, 0x02D0, 1, 0x092C, 5, 0)
+MX6_PAD_DECL(SD3_RST__GPIO7_IO08,	0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__NAND_CLE,	0x06BC, 0x02D4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__IPU2_SISG4,	0x06BC, 0x02D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07,	0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__NAND_ALE,	0x06C0, 0x02D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__SD4_RESET,	0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08,	0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B,	0x06C4, 0x02DC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__IPU2_SISG5,	0x06C4, 0x02DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09,	0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__NAND_READY_B,	0x06C8, 0x02E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__IPU2_DI0_PIN01,	0x06C8, 0x02E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10,	0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B,	0x06CC, 0x02E4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11,	0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B,	0x06D0, 0x02E8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT,	0x06D0, 0x02E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT,	0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14,	0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B,	0x06D4, 0x02EC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0,	0x06D4, 0x02EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__ESAI_TX0,	0x06D4, 0x02EC, 2, 0x0874, 1, 0)
+MX6_PAD_DECL(NANDF_CS2__EIM_CRE,	0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2,	0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15,	0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__IPU2_SISG0,	0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B,	0x06D8, 0x02F0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1,	0x06D8, 0x02F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__ESAI_TX1,	0x06D8, 0x02F0, 2, 0x0878, 1, 0)
+MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26,	0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16,	0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1,	0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__SD4_CMD,	0x06DC, 0x02F4, 16, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__NAND_RE_B,	0x06DC, 0x02F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA,	0x06DC, 0x02F4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA,	0x06DC, 0x02F4, 2, 0x0930, 2, 0)
+MX6_PAD_DECL(SD4_CMD__GPIO7_IO09,	0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__SD4_CLK,	0x06E0, 0x02F8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__NAND_WE_B,	0x06E0, 0x02F8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA,	0x06E0, 0x02F8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA,	0x06E0, 0x02F8, 2, 0x0930, 3, 0)
+MX6_PAD_DECL(SD4_CLK__GPIO7_IO10,	0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__NAND_DATA00,	0x06E4, 0x02FC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__SD1_DATA4,	0x06E4, 0x02FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__GPIO2_IO00,	0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__NAND_DATA01,	0x06E8, 0x0300, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__SD1_DATA5,	0x06E8, 0x0300, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__GPIO2_IO01,	0x06E8, 0x0300, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__NAND_DATA02,	0x06EC, 0x0304, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__SD1_DATA6,	0x06EC, 0x0304, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__GPIO2_IO02,	0x06EC, 0x0304, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__NAND_DATA03,	0x06F0, 0x0308, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__SD1_DATA7,	0x06F0, 0x0308, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__GPIO2_IO03,	0x06F0, 0x0308, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__NAND_DATA04,	0x06F4, 0x030C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__SD2_DATA4,	0x06F4, 0x030C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__GPIO2_IO04,	0x06F4, 0x030C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__NAND_DATA05,	0x06F8, 0x0310, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__SD2_DATA5,	0x06F8, 0x0310, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__GPIO2_IO05,	0x06F8, 0x0310, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__NAND_DATA06,	0x06FC, 0x0314, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__SD2_DATA6,	0x06FC, 0x0314, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__GPIO2_IO06,	0x06FC, 0x0314, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__NAND_DATA07,	0x0700, 0x0318, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__SD2_DATA7,	0x0700, 0x0318, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__GPIO2_IO07,	0x0700, 0x0318, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__SD4_DATA0,	0x0704, 0x031C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__NAND_DQS,	0x0704, 0x031C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08,	0x0704, 0x031C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__SD4_DATA1,	0x0708, 0x0320, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__PWM3_OUT,	0x0708, 0x0320, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09,	0x0708, 0x0320, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__SD4_DATA2,	0x070C, 0x0324, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__PWM4_OUT,	0x070C, 0x0324, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10,	0x070C, 0x0324, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__SD4_DATA3,	0x0710, 0x0328, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11,	0x0710, 0x0328, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__SD4_DATA4,	0x0714, 0x032C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA,	0x0714, 0x032C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA,	0x0714, 0x032C, 2, 0x0928, 6, 0)
+MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12,	0x0714, 0x032C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__SD4_DATA5,	0x0718, 0x0330, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B,	0x0718, 0x0330, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B,	0x0718, 0x0330, 2, 0x0924, 4, 0)
+MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13,	0x0718, 0x0330, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__SD4_DATA6,	0x071C, 0x0334, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B,	0x071C, 0x0334, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B,	0x071C, 0x0334, 2, 0x0924, 5, 0)
+MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14,	0x071C, 0x0334, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__SD4_DATA7,	0x0720, 0x0338, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA,	0x0720, 0x0338, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA,	0x0720, 0x0338, 2, 0x0928, 7, 0)
+MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15,	0x0720, 0x0338, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__SD1_DATA1,	0x0724, 0x033C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__ECSPI5_SS0,	0x0724, 0x033C, 1, 0x0834, 1, 0)
+MX6_PAD_DECL(SD1_DAT1__PWM3_OUT,	0x0724, 0x033C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2,	0x0724, 0x033C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17,	0x0724, 0x033C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__SD1_DATA0,	0x0728, 0x0340, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__ECSPI5_MISO,	0x0728, 0x0340, 1, 0x082C, 1, 0)
+MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1,	0x0728, 0x0340, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16,	0x0728, 0x0340, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__SD1_DATA3,	0x072C, 0x0344, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__ECSPI5_SS2,	0x072C, 0x0344, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3,	0x072C, 0x0344, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__PWM1_OUT,	0x072C, 0x0344, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_B,	0x072C, 0x0344, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21,	0x072C, 0x0344, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB,	0x072C, 0x0344, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__SD1_CMD,	0x0730, 0x0348, 16, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI,	0x0730, 0x0348, 1, 0x0830, 0, 0)
+MX6_PAD_DECL(SD1_CMD__PWM4_OUT,	0x0730, 0x0348, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1,	0x0730, 0x0348, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPIO1_IO18,	0x0730, 0x0348, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__SD1_DATA2,	0x0734, 0x034C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__ECSPI5_SS1,	0x0734, 0x034C, 1, 0x0838, 1, 0)
+MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2,	0x0734, 0x034C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__PWM2_OUT,	0x0734, 0x034C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_B,	0x0734, 0x034C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19,	0x0734, 0x034C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB,	0x0734, 0x034C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__SD1_CLK,	0x0738, 0x0350, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__ECSPI5_SCLK,	0x0738, 0x0350, 1, 0x0828, 0, 0)
+MX6_PAD_DECL(SD1_CLK__GPT_CLKIN,	0x0738, 0x0350, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__GPIO1_IO20,	0x0738, 0x0350, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CLK__SD2_CLK,	0x073C, 0x0354, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK,	0x073C, 0x0354, 1, 0x0828, 1, 0)
+MX6_PAD_DECL(SD2_CLK__KEY_COL5,	0x073C, 0x0354, 2, 0x08E8, 3, 0)
+MX6_PAD_DECL(SD2_CLK__AUD4_RXFS,	0x073C, 0x0354, 3, 0x07C0, 1, 0)
+MX6_PAD_DECL(SD2_CLK__GPIO1_IO10,	0x073C, 0x0354, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__SD2_CMD,	0x0740, 0x0358, 16, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI,	0x0740, 0x0358, 1, 0x0830, 1, 0)
+MX6_PAD_DECL(SD2_CMD__KEY_ROW5,	0x0740, 0x0358, 2, 0x08F4, 2, 0)
+MX6_PAD_DECL(SD2_CMD__AUD4_RXC,	0x0740, 0x0358, 3, 0x07BC, 1, 0)
+MX6_PAD_DECL(SD2_CMD__GPIO1_IO11,	0x0740, 0x0358, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__SD2_DATA3,	0x0744, 0x035C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__ECSPI5_SS3,	0x0744, 0x035C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__KEY_COL6,	0x0744, 0x035C, 2, 0x08EC, 2, 0)
+MX6_PAD_DECL(SD2_DAT3__AUD4_TXC,	0x0744, 0x035C, 3, 0x07C4, 1, 0)
+MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12,	0x0744, 0x035C, 5, 0x0000, 0, 0)
+
+#endif	/* __ASM_ARCH_MX6_MX6Q_PINS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
new file mode 100644
index 000000000..5f9c90ad8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__
+#define __ASM_ARCH_MX6_MX6SL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+enum {
+	MX6_PAD_SD2_CLK__USDHC2_CLK				= IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_CMD__USDHC2_CMD				= IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0				= IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1				= IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2				= IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3				= IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+	MX6_PAD_UART1_RXD__UART1_RXD				= IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
+	MX6_PAD_UART1_TXD__UART1_TXD				= IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
+
+	MX6_PAD_FEC_MDC__FEC_MDC				= IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_MDIO__FEC_MDIO				= IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0),
+	MX6_PAD_FEC_CRS_DV__FEC_RX_DV				= IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0),
+	MX6_PAD_FEC_RXD0__FEC_RX_DATA0				= IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0),
+	MX6_PAD_FEC_RXD1__FEC_RX_DATA1				= IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0),
+	MX6_PAD_FEC_TX_EN__FEC_TX_EN				= IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_TXD0__FEC_TX_DATA0				= IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_TXD1__FEC_TX_DATA1				= IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT			= IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
+	MX6_PAD_FEC_RX_ER__GPIO_4_19				= IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
+	MX6_PAD_FEC_TX_CLK__GPIO_4_21				= IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
+};
+#endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
new file mode 100644
index 000000000..e5e3eff59
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
@@ -0,0 +1,1060 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MXC_HDMI_H__
+#define __MXC_HDMI_H__
+
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void);
+void imx_setup_hdmi(void);
+#endif
+
+/*
+ * Hdmi controller registers
+ */
+struct hdmi_regs {
+	/*Identification Registers */
+	u8 design_id;			/* 0x000 */
+	u8 revision_id;			/* 0x001 */
+	u8 product_id0;			/* 0x002 */
+	u8 product_id1;			/* 0x003 */
+	u8 config0_id;			/* 0x004 */
+	u8 config1_id;			/* 0x005 */
+	u8 config2_id;			/* 0x006 */
+	u8 config3_id;			/* 0x007 */
+	u8 reserved1[0xf8];
+	/* Interrupt Registers */
+	u8 ih_fc_stat0;			/* 0x100 */
+	u8 ih_fc_stat1;			/* 0x101 */
+	u8 ih_fc_stat2;			/* 0x102 */
+	u8 ih_as_stat0;			/* 0x103 */
+	u8 ih_phy_stat0;		/* 0x104 */
+	u8 ih_i2cm_stat0;		/* 0x105 */
+	u8 ih_cec_stat0;		/* 0x106 */
+	u8 ih_vp_stat0;			/* 0x107 */
+	u8 ih_i2cmphy_stat0;		/* 0x108 */
+	u8 ih_ahbdmaaud_stat0;		/* 0x109 */
+	u8 reserved2[0x76];
+	u8 ih_mute_fc_stat0;		/* 0x180 */
+	u8 ih_mute_fc_stat1;		/* 0x181 */
+	u8 ih_mute_fc_stat2;		/* 0x182 */
+	u8 ih_mute_as_stat0;		/* 0x183 */
+	u8 ih_mute_phy_stat0;		/* 0x184 */
+	u8 ih_mute_i2cm_stat0;		/* 0x185 */
+	u8 ih_mute_cec_stat0;		/* 0x186 */
+	u8 ih_mute_vp_stat0;		/* 0x187 */
+	u8 ih_mute_i2cmphy_stat0;	/* 0x188 */
+	u8 ih_mute_ahbdmaaud_stat0;	/* 0x189 */
+	u8 reserved3[0x75];
+	u8 ih_mute;			/* 0x1ff */
+	/* Video Sample Registers */
+	u8 tx_invid0;			/* 0x200 */
+	u8 tx_instuffing;		/* 0x201 */
+	u8 tx_gydata0;			/* 0x202 */
+	u8 tx_gydata1;			/* 0x203 */
+	u8 tx_rcrdata0;			/* 0x204 */
+	u8 tx_rcrdata1;			/* 0x205 */
+	u8 tx_bcbdata0;			/* 0x206 */
+	u8 tx_bcbdata1;			/* 0x207 */
+	u8 reserved4[0x5f8];
+	/* Video Packetizer Registers */
+	u8 vp_status;			/* 0x800 */
+	u8 vp_pr_cd;			/* 0x801 */
+	u8 vp_stuff;			/* 0x802 */
+	u8 vp_remap;			/* 0x803 */
+	u8 vp_conf;			/* 0x804 */
+	u8 vp_stat;			/* 0x805 */
+	u8 vp_int;			/* 0x806 */
+	u8 vp_mask;			/* 0x807 */
+	u8 vp_pol;			/* 0x808 */
+	u8 reserved5[0x7f7];
+	/* Frame Composer Registers */
+	u8 fc_invidconf;		/* 0x1000 */
+	u8 fc_inhactv0;			/* 0x1001 */
+	u8 fc_inhactv1;			/* 0x1002 */
+	u8 fc_inhblank0;		/* 0x1003 */
+	u8 fc_inhblank1;		/* 0x1004 */
+	u8 fc_invactv0;			/* 0x1005 */
+	u8 fc_invactv1;			/* 0x1006 */
+	u8 fc_invblank;			/* 0x1007 */
+	u8 fc_hsyncindelay0;		/* 0x1008 */
+	u8 fc_hsyncindelay1;		/* 0x1009 */
+	u8 fc_hsyncinwidth0;		/* 0x100a */
+	u8 fc_hsyncinwidth1;		/* 0x100b */
+	u8 fc_vsyncindelay;		/* 0x100c */
+	u8 fc_vsyncinwidth;		/* 0x100d */
+	u8 fc_infreq0;			/* 0x100e */
+	u8 fc_infreq1;			/* 0x100f */
+	u8 fc_infreq2;			/* 0x1010 */
+	u8 fc_ctrldur;			/* 0x1011 */
+	u8 fc_exctrldur;		/* 0x1012 */
+	u8 fc_exctrlspac;		/* 0x1013 */
+	u8 fc_ch0pream;			/* 0x1014 */
+	u8 fc_ch1pream;			/* 0x1015 */
+	u8 fc_ch2pream;			/* 0x1016 */
+	u8 fc_aviconf3;			/* 0x1017 */
+	u8 fc_gcp;			/* 0x1018 */
+	u8 fc_aviconf0;			/* 0x1019 */
+	u8 fc_aviconf1;			/* 0x101a */
+	u8 fc_aviconf2;			/* 0x101b */
+	u8 fc_avivid;			/* 0x101c */
+	u8 fc_avietb0;			/* 0x101d */
+	u8 fc_avietb1;			/* 0x101e */
+	u8 fc_avisbb0;			/* 0x101f */
+	u8 fc_avisbb1;			/* 0x1020 */
+	u8 fc_avielb0;			/* 0x1021 */
+	u8 fc_avielb1;			/* 0x1022 */
+	u8 fc_avisrb0;			/* 0x1023 */
+	u8 fc_avisrb1;			/* 0x1024 */
+	u8 fc_audiconf0;		/* 0x1025 */
+	u8 fc_audiconf1;		/* 0x1026 */
+	u8 fc_audiconf2;		/* 0x1027 */
+	u8 fc_audiconf3;		/* 0x1028 */
+	u8 fc_vsdieeeid0;		/* 0x1029 */
+	u8 fc_vsdsize;			/* 0x102a */
+	u8 reserved6[5];
+	u8 fc_vsdieeeid1;		/* 0x1030 */
+	u8 fc_vsdieeeid2;		/* 0x1031 */
+	u8 fc_vsdpayload0;		/* 0x1032 */
+	u8 fc_vsdpayload1;		/* 0x1033 */
+	u8 fc_vsdpayload2;		/* 0x1034 */
+	u8 fc_vsdpayload3;		/* 0x1035 */
+	u8 fc_vsdpayload4;		/* 0x1036 */
+	u8 fc_vsdpayload5;		/* 0x1037 */
+	u8 fc_vsdpayload6;		/* 0x1038 */
+	u8 fc_vsdpayload7;		/* 0x1039 */
+	u8 fc_vsdpayload8;		/* 0x103a */
+	u8 fc_vsdpayload9;		/* 0x103b */
+	u8 fc_vsdpayload10;		/* 0x103c */
+	u8 fc_vsdpayload11;		/* 0x103d */
+	u8 fc_vsdpayload12;		/* 0x103e */
+	u8 fc_vsdpayload13;		/* 0x103f */
+	u8 fc_vsdpayload14;		/* 0x1040 */
+	u8 fc_vsdpayload15;		/* 0x1041 */
+	u8 fc_vsdpayload16;		/* 0x1042 */
+	u8 fc_vsdpayload17;		/* 0x1043 */
+	u8 fc_vsdpayload18;		/* 0x1044 */
+	u8 fc_vsdpayload19;		/* 0x1045 */
+	u8 fc_vsdpayload20;		/* 0x1046 */
+	u8 fc_vsdpayload21;		/* 0x1047 */
+	u8 fc_vsdpayload22;		/* 0x1048 */
+	u8 fc_vsdpayload23;		/* 0x1049 */
+	u8 fc_spdvendorname0;		/* 0x104a */
+	u8 fc_spdvendorname1;		/* 0x104b */
+	u8 fc_spdvendorname2;		/* 0x104c */
+	u8 fc_spdvendorname3;		/* 0x104d */
+	u8 fc_spdvendorname4;		/* 0x104e */
+	u8 fc_spdvendorname5;		/* 0x104f */
+	u8 fc_spdvendorname6;		/* 0x1050 */
+	u8 fc_spdvendorname7;		/* 0x1051 */
+	u8 fc_sdpproductname0;		/* 0x1052 */
+	u8 fc_sdpproductname1;		/* 0x1053 */
+	u8 fc_sdpproductname2;		/* 0x1054 */
+	u8 fc_sdpproductname3;		/* 0x1055 */
+	u8 fc_sdpproductname4;		/* 0x1056 */
+	u8 fc_sdpproductname5;		/* 0x1057 */
+	u8 fc_sdpproductname6;		/* 0x1058 */
+	u8 fc_sdpproductname7;		/* 0x1059 */
+	u8 fc_sdpproductname8;		/* 0x105a */
+	u8 fc_sdpproductname9;		/* 0x105b */
+	u8 fc_sdpproductname10;		/* 0x105c */
+	u8 fc_sdpproductname11;		/* 0x105d */
+	u8 fc_sdpproductname12;		/* 0x105e */
+	u8 fc_sdpproductname13;		/* 0x105f */
+	u8 fc_sdpproductname14;		/* 0x1060 */
+	u8 fc_spdproductname15;		/* 0x1061 */
+	u8 fc_spddeviceinf;		/* 0x1062 */
+	u8 fc_audsconf;			/* 0x1063 */
+	u8 fc_audsstat;			/* 0x1064 */
+	u8 reserved7[0xb];
+	u8 fc_datach0fill;		/* 0x1070 */
+	u8 fc_datach1fill;		/* 0x1071 */
+	u8 fc_datach2fill;		/* 0x1072 */
+	u8 fc_ctrlqhigh;		/* 0x1073 */
+	u8 fc_ctrlqlow;			/* 0x1074 */
+	u8 fc_acp0;			/* 0x1075 */
+	u8 fc_acp28;			/* 0x1076 */
+	u8 fc_acp27;			/* 0x1077 */
+	u8 fc_acp26;			/* 0x1078 */
+	u8 fc_acp25;			/* 0x1079 */
+	u8 fc_acp24;			/* 0x107a */
+	u8 fc_acp23;			/* 0x107b */
+	u8 fc_acp22;			/* 0x107c */
+	u8 fc_acp21;			/* 0x107d */
+	u8 fc_acp20;			/* 0x107e */
+	u8 fc_acp19;			/* 0x107f */
+	u8 fc_acp18;			/* 0x1080 */
+	u8 fc_acp17;			/* 0x1081 */
+	u8 fc_acp16;			/* 0x1082 */
+	u8 fc_acp15;			/* 0x1083 */
+	u8 fc_acp14;			/* 0x1084 */
+	u8 fc_acp13;			/* 0x1085 */
+	u8 fc_acp12;			/* 0x1086 */
+	u8 fc_acp11;			/* 0x1087 */
+	u8 fc_acp10;			/* 0x1088 */
+	u8 fc_acp9;			/* 0x1089 */
+	u8 fc_acp8;			/* 0x108a */
+	u8 fc_acp7;			/* 0x108b */
+	u8 fc_acp6;			/* 0x108c */
+	u8 fc_acp5;			/* 0x108d */
+	u8 fc_acp4;			/* 0x108e */
+	u8 fc_acp3;			/* 0x108f */
+	u8 fc_acp2;			/* 0x1090 */
+	u8 fc_acp1;			/* 0x1091 */
+	u8 fc_iscr1_0;			/* 0x1092 */
+	u8 fc_iscr1_16;			/* 0x1093 */
+	u8 fc_iscr1_15;			/* 0x1094 */
+	u8 fc_iscr1_14;			/* 0x1095 */
+	u8 fc_iscr1_13;			/* 0x1096 */
+	u8 fc_iscr1_12;			/* 0x1097 */
+	u8 fc_iscr1_11;			/* 0x1098 */
+	u8 fc_iscr1_10;			/* 0x1099 */
+	u8 fc_iscr1_9;			/* 0x109a */
+	u8 fc_iscr1_8;			/* 0x109b */
+	u8 fc_iscr1_7;			/* 0x109c */
+	u8 fc_iscr1_6;			/* 0x109d */
+	u8 fc_iscr1_5;			/* 0x109e */
+	u8 fc_iscr1_4;			/* 0x109f */
+	u8 fc_iscr1_3;			/* 0x10a0 */
+	u8 fc_iscr1_2;			/* 0x10a1 */
+	u8 fc_iscr1_1;			/* 0x10a2 */
+	u8 fc_iscr2_15;			/* 0x10a3 */
+	u8 fc_iscr2_14;			/* 0x10a4 */
+	u8 fc_iscr2_13;			/* 0x10a5 */
+	u8 fc_iscr2_12;			/* 0x10a6 */
+	u8 fc_iscr2_11;			/* 0x10a7 */
+	u8 fc_iscr2_10;			/* 0x10a8 */
+	u8 fc_iscr2_9;			/* 0x10a9 */
+	u8 fc_iscr2_8;			/* 0x10aa */
+	u8 fc_iscr2_7;			/* 0x10ab */
+	u8 fc_iscr2_6;			/* 0x10ac */
+	u8 fc_iscr2_5;			/* 0x10ad */
+	u8 fc_iscr2_4;			/* 0x10ae */
+	u8 fc_iscr2_3;			/* 0x10af */
+	u8 fc_iscr2_2;			/* 0x10b0 */
+	u8 fc_iscr2_1;			/* 0x10b1 */
+	u8 fc_iscr2_0;			/* 0x10b2 */
+	u8 fc_datauto0;			/* 0x10b3 */
+	u8 fc_datauto1;			/* 0x10b4 */
+	u8 fc_datauto2;			/* 0x10b5 */
+	u8 fc_datman;			/* 0x10b6 */
+	u8 fc_datauto3;			/* 0x10b7 */
+	u8 fc_rdrb0;			/* 0x10b8 */
+	u8 fc_rdrb1;			/* 0x10b9 */
+	u8 fc_rdrb2;			/* 0x10ba */
+	u8 fc_rdrb3;			/* 0x10bb */
+	u8 fc_rdrb4;			/* 0x10bc */
+	u8 fc_rdrb5;			/* 0x10bd */
+	u8 fc_rdrb6;			/* 0x10be */
+	u8 fc_rdrb7;			/* 0x10bf */
+	u8 reserved8[0x10];
+	u8 fc_stat0;			/* 0x10d0 */
+	u8 fc_int0;			/* 0x10d1 */
+	u8 fc_mask0;			/* 0x10d2 */
+	u8 fc_pol0;			/* 0x10d3 */
+	u8 fc_stat1;			/* 0x10d4 */
+	u8 fc_int1;			/* 0x10d5 */
+	u8 fc_mask1;			/* 0x10d6 */
+	u8 fc_pol1;			/* 0x10d7 */
+	u8 fc_stat2;			/* 0x10d8 */
+	u8 fc_int2;			/* 0x10d9 */
+	u8 fc_mask2;			/* 0x10da */
+	u8 fc_pol2;			/* 0x10db */
+	u8 reserved9[0x4];
+	u8 fc_prconf;			/* 0x10e0 */
+	u8 reserved10[0x1f];
+	u8 fc_gmd_stat;			/* 0x1100 */
+	u8 fc_gmd_en;			/* 0x1101 */
+	u8 fc_gmd_up;			/* 0x1102 */
+	u8 fc_gmd_conf;			/* 0x1103 */
+	u8 fc_gmd_hb;			/* 0x1104 */
+	u8 fc_gmd_pb0;			/* 0x1105 */
+	u8 fc_gmd_pb1;			/* 0x1106 */
+	u8 fc_gmd_pb2;			/* 0x1107 */
+	u8 fc_gmd_pb3;			/* 0x1108 */
+	u8 fc_gmd_pb4;			/* 0x1109 */
+	u8 fc_gmd_pb5;			/* 0x110a */
+	u8 fc_gmd_pb6;			/* 0x110b */
+	u8 fc_gmd_pb7;			/* 0x110c */
+	u8 fc_gmd_pb8;			/* 0x110d */
+	u8 fc_gmd_pb9;			/* 0x110e */
+	u8 fc_gmd_pb10;			/* 0x110f */
+	u8 fc_gmd_pb11;			/* 0x1110 */
+	u8 fc_gmd_pb12;			/* 0x1111 */
+	u8 fc_gmd_pb13;			/* 0x1112 */
+	u8 fc_gmd_pb14;			/* 0x1113 */
+	u8 fc_gmd_pb15;			/* 0x1114 */
+	u8 fc_gmd_pb16;			/* 0x1115 */
+	u8 fc_gmd_pb17;			/* 0x1116 */
+	u8 fc_gmd_pb18;			/* 0x1117 */
+	u8 fc_gmd_pb19;			/* 0x1118 */
+	u8 fc_gmd_pb20;			/* 0x1119 */
+	u8 fc_gmd_pb21;			/* 0x111a */
+	u8 fc_gmd_pb22;			/* 0x111b */
+	u8 fc_gmd_pb23;			/* 0x111c */
+	u8 fc_gmd_pb24;			/* 0x111d */
+	u8 fc_gmd_pb25;			/* 0x111e */
+	u8 fc_gmd_pb26;			/* 0x111f */
+	u8 fc_gmd_pb27;			/* 0x1120 */
+	u8 reserved11[0xdf];
+	u8 fc_dbgforce;			/* 0x1200 */
+	u8 fc_dbgaud0ch0;		/* 0x1201 */
+	u8 fc_dbgaud1ch0;		/* 0x1202 */
+	u8 fc_dbgaud2ch0;		/* 0x1203 */
+	u8 fc_dbgaud0ch1;		/* 0x1204 */
+	u8 fc_dbgaud1ch1;		/* 0x1205 */
+	u8 fc_dbgaud2ch1;		/* 0x1206 */
+	u8 fc_dbgaud0ch2;		/* 0x1207 */
+	u8 fc_dbgaud1ch2;		/* 0x1208 */
+	u8 fc_dbgaud2ch2;		/* 0x1209 */
+	u8 fc_dbgaud0ch3;		/* 0x120a */
+	u8 fc_dbgaud1ch3;		/* 0x120b */
+	u8 fc_dbgaud2ch3;		/* 0x120c */
+	u8 fc_dbgaud0ch4;		/* 0x120d */
+	u8 fc_dbgaud1ch4;		/* 0x120e */
+	u8 fc_dbgaud2ch4;		/* 0x120f */
+	u8 fc_dbgaud0ch5;		/* 0x1210 */
+	u8 fc_dbgaud1ch5;		/* 0x1211 */
+	u8 fc_dbgaud2ch5;		/* 0x1212 */
+	u8 fc_dbgaud0ch6;		/* 0x1213 */
+	u8 fc_dbgaud1ch6;		/* 0x1214 */
+	u8 fc_dbgaud2ch6;		/* 0x1215 */
+	u8 fc_dbgaud0ch7;		/* 0x1216 */
+	u8 fc_dbgaud1ch7;		/* 0x1217 */
+	u8 fc_dbgaud2ch7;		/* 0x1218 */
+	u8 fc_dbgtmds0;			/* 0x1219 */
+	u8 fc_dbgtmds1;			/* 0x121a */
+	u8 fc_dbgtmds2;			/* 0x121b */
+	u8 reserved12[0x1de4];
+	/* Hdmi Source Phy Registers */
+	u8 phy_conf0;			/* 0x3000 */
+	u8 phy_tst0;			/* 0x3001 */
+	u8 phy_tst1;			/* 0x3002 */
+	u8 phy_tst2;			/* 0x3003 */
+	u8 phy_stat0;			/* 0x3004 */
+	u8 phy_int0;			/* 0x3005 */
+	u8 phy_mask0;			/* 0x3006 */
+	u8 phy_pol0;			/* 0x3007 */
+	u8 reserved13[0x18];
+	/* Hdmi Master Phy Registers */
+	u8 phy_i2cm_slave_addr;		/* 0x3020 */
+	u8 phy_i2cm_address_addr;	/* 0x3021 */
+	u8 phy_i2cm_datao_1_addr;	/* 0x3022 */
+	u8 phy_i2cm_datao_0_addr;	/* 0x3023 */
+	u8 phy_i2cm_datai_1_addr;	/* 0x3024 */
+	u8 phy_i2cm_datai_0_addr;	/* 0x3025 */
+	u8 phy_i2cm_operation_addr;	/* 0x3026 */
+	u8 phy_i2cm_int_addr;		/* 0x3027 */
+	u8 phy_i2cm_ctlint_addr;	/* 0x3028 */
+	u8 phy_i2cm_div_addr;		/* 0x3029 */
+	u8 phy_i2cm_softrstz_addr;	/* 0x302a */
+	u8 phy_i2cm_ss_scl_hcnt_1_addr;	/* 0x302b */
+	u8 phy_i2cm_ss_scl_hcnt_0_addr;	/* 0x302c */
+	u8 phy_i2cm_ss_scl_lcnt_1_addr;	/* 0x302d */
+	u8 phy_i2cm_ss_scl_lcnt_0_addr;	/* 0x302e */
+	u8 phy_i2cm_fs_scl_hcnt_1_addr;	/* 0x302f */
+	u8 phy_i2cm_fs_scl_hcnt_0_addr;	/* 0x3030 */
+	u8 phy_i2cm_fs_scl_lcnt_1_addr;	/* 0x3031 */
+	u8 phy_i2cm_fs_scl_lcnt_0_addr;	/* 0x3032 */
+	u8 reserved14[0xcd];
+	/* Audio Sampler Registers */
+	u8 aud_conf0;			/* 0x3100 */
+	u8 aud_conf1;			/* 0x3101 */
+	u8 aud_int;			/* 0x3102 */
+	u8 aud_conf2;			/* 0x3103 */
+	u8 reserved15[0xfc];
+	u8 aud_n1;			/* 0x3200 */
+	u8 aud_n2;			/* 0x3201 */
+	u8 aud_n3;			/* 0x3202 */
+	u8 aud_cts1;			/* 0x3203 */
+	u8 aud_cts2;			/* 0x3204 */
+	u8 aud_cts3;			/* 0x3205 */
+	u8 aud_inputclkfs;		/* 0x3206 */
+	u8 reserved16[0xfb];
+	u8 aud_spdifint;		/* 0x3302 */
+	u8 reserved17[0xfd];
+	u8 aud_conf0_hbr;		/* 0x3400 */
+	u8 aud_hbr_status;		/* 0x3401 */
+	u8 aud_hbr_int;			/* 0x3402 */
+	u8 aud_hbr_pol;			/* 0x3403 */
+	u8 aud_hbr_mask;		/* 0x3404 */
+	u8 reserved18[0xfb];
+	/*
+	 * Generic Parallel Audio Interface Registers
+	 * Not used as GPAUD interface is not enabled in hw
+	 */
+	u8 gp_conf0;			/* 0x3500 */
+	u8 gp_conf1;			/* 0x3501 */
+	u8 gp_conf2;			/* 0x3502 */
+	u8 gp_stat;			/* 0x3503 */
+	u8 gp_int;			/* 0x3504 */
+	u8 gp_mask;			/* 0x3505 */
+	u8 gp_pol;			/* 0x3506 */
+	u8 reserved19[0xf9];
+	/* Audio DMA Registers */
+	u8 ahb_dma_conf0;		/* 0x3600 */
+	u8 ahb_dma_start;		/* 0x3601 */
+	u8 ahb_dma_stop;		/* 0x3602 */
+	u8 ahb_dma_thrsld;		/* 0x3603 */
+	u8 ahb_dma_straddr0;		/* 0x3604 */
+	u8 ahb_dma_straddr1;		/* 0x3605 */
+	u8 ahb_dma_straddr2;		/* 0x3606 */
+	u8 ahb_dma_straddr3;		/* 0x3607 */
+	u8 ahb_dma_stpaddr0;		/* 0x3608 */
+	u8 ahb_dma_stpaddr1;		/* 0x3609 */
+	u8 ahb_dma_stpaddr2;		/* 0x360a */
+	u8 ahb_dma_stpaddr3;		/* 0x360b */
+	u8 ahb_dma_bstaddr0;		/* 0x360c */
+	u8 ahb_dma_bstaddr1;		/* 0x360d */
+	u8 ahb_dma_bstaddr2;		/* 0x360e */
+	u8 ahb_dma_bstaddr3;		/* 0x360f */
+	u8 ahb_dma_mblength0;		/* 0x3610 */
+	u8 ahb_dma_mblength1;		/* 0x3611 */
+	u8 ahb_dma_stat;		/* 0x3612 */
+	u8 ahb_dma_int;			/* 0x3613 */
+	u8 ahb_dma_mask;		/* 0x3614 */
+	u8 ahb_dma_pol;			/* 0x3615 */
+	u8 ahb_dma_conf1;		/* 0x3616 */
+	u8 ahb_dma_buffstat;		/* 0x3617 */
+	u8 ahb_dma_buffint;		/* 0x3618 */
+	u8 ahb_dma_buffmask;		/* 0x3619 */
+	u8 ahb_dma_buffpol;		/* 0x361a */
+	u8 reserved20[0x9e5];
+	/* Main Controller Registers */
+	u8 mc_sfrdiv;			/* 0x4000 */
+	u8 mc_clkdis;			/* 0x4001 */
+	u8 mc_swrstz;			/* 0x4002 */
+	u8 mc_opctrl;			/* 0x4003 */
+	u8 mc_flowctrl;			/* 0x4004 */
+	u8 mc_phyrstz;			/* 0x4005 */
+	u8 mc_lockonclock;		/* 0x4006 */
+	u8 mc_heacphy_rst;		/* 0x4007 */
+	u8 reserved21[0xf8];
+	/* Colorspace Converter Registers */
+	u8 csc_cfg;			/* 0x4100 */
+	u8 csc_scale;			/* 0x4101 */
+	u8 csc_coef_a1_msb;		/* 0x4102 */
+	u8 csc_coef_a1_lsb;		/* 0x4103 */
+	u8 csc_coef_a2_msb;		/* 0x4104 */
+	u8 csc_coef_a2_lsb;		/* 0x4105 */
+	u8 csc_coef_a3_msb;		/* 0x4106 */
+	u8 csc_coef_a3_lsb;		/* 0x4107 */
+	u8 csc_coef_a4_msb;		/* 0x4108 */
+	u8 csc_coef_a4_lsb;		/* 0x4109 */
+	u8 csc_coef_b1_msb;		/* 0x410a */
+	u8 csc_coef_b1_lsb;		/* 0x410b */
+	u8 csc_coef_b2_msb;		/* 0x410c */
+	u8 csc_coef_b2_lsb;		/* 0x410d */
+	u8 csc_coef_b3_msb;		/* 0x410e */
+	u8 csc_coef_b3_lsb;		/* 0x410f */
+	u8 csc_coef_b4_msb;		/* 0x4110 */
+	u8 csc_coef_b4_lsb;		/* 0x4111 */
+	u8 csc_coef_c1_msb;		/* 0x4112 */
+	u8 csc_coef_c1_lsb;		/* 0x4113 */
+	u8 csc_coef_c2_msb;		/* 0x4114 */
+	u8 csc_coef_c2_lsb;		/* 0x4115 */
+	u8 csc_coef_c3_msb;		/* 0x4116 */
+	u8 csc_coef_c3_lsb;		/* 0x4117 */
+	u8 csc_coef_c4_msb;		/* 0x4118 */
+	u8 csc_coef_c4_lsb;		/* 0x4119 */
+	u8 reserved22[0xee6];
+	/* HDCP Encryption Engine Registers */
+	u8 a_hdcpcfg0;			/* 0x5000 */
+	u8 a_hdcpcfg1;			/* 0x5001 */
+	u8 a_hdcpobs0;			/* 0x5002 */
+	u8 a_hdcpobs1;			/* 0x5003 */
+	u8 a_hdcpobs2;			/* 0x5004 */
+	u8 a_hdcpobs3;			/* 0x5005 */
+	u8 a_apiintclr;			/* 0x5006 */
+	u8 a_apiintstat;		/* 0x5007 */
+	u8 a_apiintmsk;			/* 0x5008 */
+	u8 a_vidpolcfg;			/* 0x5009 */
+	u8 a_oesswcfg;			/* 0x500a */
+	u8 a_timer1setup0;		/* 0x500b */
+	u8 a_timer1setup1;		/* 0x500c */
+	u8 a_timer2setup0;		/* 0x500d */
+	u8 a_timer2setup1;		/* 0x500e */
+	u8 a_100mscfg;			/* 0x500f */
+	u8 a_2scfg0;			/* 0x5010 */
+	u8 a_2scfg1;			/* 0x5011 */
+	u8 a_5scfg0;			/* 0x5012 */
+	u8 a_5scfg1;			/* 0x5013 */
+	u8 a_srmverlsb;			/* 0x5014 */
+	u8 a_srmvermsb;			/* 0x5015 */
+	u8 a_srmctrl;			/* 0x5016 */
+	u8 a_sfrsetup;			/* 0x5017 */
+	u8 a_i2chsetup;			/* 0x5018 */
+	u8 a_intsetup;			/* 0x5019 */
+	u8 a_presetup;			/* 0x501a */
+	u8 reserved23[0x5];
+	u8 a_srm_base;			/* 0x5020 */
+	u8 reserved24[0x2cdf];
+	/* CEC Engine Registers */
+	u8 cec_ctrl;			/* 0x7d00 */
+	u8 cec_stat;			/* 0x7d01 */
+	u8 cec_mask;			/* 0x7d02 */
+	u8 cec_polarity;		/* 0x7d03 */
+	u8 cec_int;			/* 0x7d04 */
+	u8 cec_addr_l;			/* 0x7d05 */
+	u8 cec_addr_h;			/* 0x7d06 */
+	u8 cec_tx_cnt;			/* 0x7d07 */
+	u8 cec_rx_cnt;			/* 0x7d08 */
+	u8 reserved25[0x7];
+	u8 cec_tx_data0;		/* 0x7d10 */
+	u8 cec_tx_data1;		/* 0x7d11 */
+	u8 cec_tx_data2;		/* 0x7d12 */
+	u8 cec_tx_data3;		/* 0x7d13 */
+	u8 cec_tx_data4;		/* 0x7d14 */
+	u8 cec_tx_data5;		/* 0x7d15 */
+	u8 cec_tx_data6;		/* 0x7d16 */
+	u8 cec_tx_data7;		/* 0x7d17 */
+	u8 cec_tx_data8;		/* 0x7d18 */
+	u8 cec_tx_data9;		/* 0x7d19 */
+	u8 cec_tx_data10;		/* 0x7d1a */
+	u8 cec_tx_data11;		/* 0x7d1b */
+	u8 cec_tx_data12;		/* 0x7d1c */
+	u8 cec_tx_data13;		/* 0x7d1d */
+	u8 cec_tx_data14;		/* 0x7d1e */
+	u8 cec_tx_data15;		/* 0x7d1f */
+	u8 cec_rx_data0;		/* 0x7d20 */
+	u8 cec_rx_data1;		/* 0x7d21 */
+	u8 cec_rx_data2;		/* 0x7d22 */
+	u8 cec_rx_data3;		/* 0x7d23 */
+	u8 cec_rx_data4;		/* 0x7d24 */
+	u8 cec_rx_data5;		/* 0x7d25 */
+	u8 cec_rx_data6;		/* 0x7d26 */
+	u8 cec_rx_data7;		/* 0x7d27 */
+	u8 cec_rx_data8;		/* 0x7d28 */
+	u8 cec_rx_data9;		/* 0x7d29 */
+	u8 cec_rx_data10;		/* 0x7d2a */
+	u8 cec_rx_data11;		/* 0x7d2b */
+	u8 cec_rx_data12;		/* 0x7d2c */
+	u8 cec_rx_data13;		/* 0x7d2d */
+	u8 cec_rx_data14;		/* 0x7d2e */
+	u8 cec_rx_data15;		/* 0x7d2f */
+	u8 cec_lock;			/* 0x7d30 */
+	u8 cec_wkupctrl;		/* 0x7d31 */
+	u8 reserved26[0xce];
+	/* I2C Master Registers (E-DDC) */
+	u8 i2cm_slave;			/* 0x7e00 */
+	u8 i2cmess;			/* 0x7e01 */
+	u8 i2cm_datao;			/* 0x7e02 */
+	u8 i2cm_datai;			/* 0x7e03 */
+	u8 i2cm_operation;		/* 0x7e04 */
+	u8 i2cm_int;			/* 0x7e05 */
+	u8 i2cm_ctlint;			/* 0x7e06 */
+	u8 i2cm_div;			/* 0x7e07 */
+	u8 i2cm_segaddr;		/* 0x7e08 */
+	u8 i2cm_softrstz;		/* 0x7e09 */
+	u8 i2cm_segptr;			/* 0x7e0a */
+	u8 i2cm_ss_scl_hcnt_1_addr;	/* 0x7e0b */
+	u8 i2cm_ss_scl_hcnt_0_addr;	/* 0x7e0c */
+	u8 i2cm_ss_scl_lcnt_1_addr;	/* 0x7e0d */
+	u8 i2cm_ss_scl_lcnt_0_addr;	/* 0x7e0e */
+	u8 i2cm_fs_scl_hcnt_1_addr;	/* 0x7e0f */
+	u8 i2cm_fs_scl_hcnt_0_addr;	/* 0x7e10 */
+	u8 i2cm_fs_scl_lcnt_1_addr;	/* 0x7e11 */
+	u8 i2cm_fs_scl_lcnt_0_addr;	/* 0x7e12 */
+	u8 reserved27[0x1ed];
+	/* Random Number Generator Registers (RNG) */
+	u8 rng_base;			/* 0x8000 */
+};
+
+/*
+ * Register field definitions
+ */
+enum {
+/* IH_FC_INT2 field values */
+	HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
+	HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_FC_STAT2 field values */
+	HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
+	HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_PHY_STAT0 field values */
+	HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
+	HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
+	HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
+	HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
+	HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
+	HDMI_IH_PHY_STAT0_HPD = 0x1,
+
+/* IH_MUTE_I2CMPHY_STAT0 field values */
+	HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
+	HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
+
+/* IH_AHBDMAAUD_STAT0 field values */
+	HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
+	HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
+	HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
+	HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
+	HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
+	HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
+
+/* IH_MUTE_FC_STAT2 field values */
+	HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
+	HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_MUTE_AHBDMAAUD_STAT0 field values */
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
+
+/* IH_MUTE field values */
+	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
+	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
+
+/* TX_INVID0 field values */
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
+	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
+	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
+
+/* TX_INSTUFFING field values */
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
+
+/* VP_PR_CD field values */
+	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
+	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
+
+/* VP_STUFF field values */
+	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
+	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
+	HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
+	HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
+	HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
+	HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
+	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
+	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
+	HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
+	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
+	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
+	HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
+	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
+	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
+	HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
+
+/* VP_CONF field values */
+	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
+	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
+	HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
+	HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
+	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_PR_EN_MASK = 0x10,
+	HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
+	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
+	HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
+	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
+	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
+	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
+	HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
+
+/* VP_REMAP field values */
+	HDMI_VP_REMAP_MASK = 0x3,
+	HDMI_VP_REMAP_YCC422_24bit = 0x2,
+	HDMI_VP_REMAP_YCC422_20bit = 0x1,
+	HDMI_VP_REMAP_YCC422_16bit = 0x0,
+
+/* FC_INVIDCONF field values */
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
+	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
+
+/* FC_AUDICONF0 field values */
+	HDMI_FC_AUDICONF0_CC_OFFSET = 4,
+	HDMI_FC_AUDICONF0_CC_MASK = 0x70,
+	HDMI_FC_AUDICONF0_CT_OFFSET = 0,
+	HDMI_FC_AUDICONF0_CT_MASK = 0xF,
+
+/* FC_AUDICONF1 field values */
+	HDMI_FC_AUDICONF1_SS_OFFSET = 3,
+	HDMI_FC_AUDICONF1_SS_MASK = 0x18,
+	HDMI_FC_AUDICONF1_SF_OFFSET = 0,
+	HDMI_FC_AUDICONF1_SF_MASK = 0x7,
+
+/* FC_AUDICONF3 field values */
+	HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
+	HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
+	HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
+	HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
+	HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
+	HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
+
+/* FC_AUDSCHNLS0 field values */
+	HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
+	HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
+
+/* FC_AUDSCHNLS3-6 field values */
+	HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
+
+	HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
+
+/* HDMI_FC_AUDSCHNLS7 field values */
+	HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
+
+/* HDMI_FC_AUDSCHNLS8 field values */
+	HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
+	HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
+
+/* FC_AUDSCONF field values */
+	HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
+	HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
+
+/* FC_STAT2 field values */
+	HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
+	HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_INT2 field values */
+	HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
+	HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_MASK2 field values */
+	HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
+	HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_PRCONF field values */
+	HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
+	HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
+	HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
+	HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
+
+/* FC_AVICONF0-FC_AVICONF3 field values */
+	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
+	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
+	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
+	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
+	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
+	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
+	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
+	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
+
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
+	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
+	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
+	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
+	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
+
+	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
+	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
+	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
+	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
+	HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
+	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
+	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
+	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
+	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
+	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
+	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
+	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
+
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
+	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
+	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
+	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
+
+/* FC_DBGFORCE field values */
+	HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
+	HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
+
+/* PHY_CONF0 field values */
+	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
+	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
+	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
+	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
+	HDMI_PHY_CONF0_SPARECTRL = 0x20,
+	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
+	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
+	HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
+	HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
+	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
+	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
+	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
+	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
+
+/* PHY_TST0 field values */
+	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
+	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
+	HDMI_PHY_TST0_TSTEN_MASK = 0x10,
+	HDMI_PHY_TST0_TSTEN_OFFSET = 4,
+	HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
+	HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
+
+/* PHY_STAT0 field values */
+	HDMI_PHY_RX_SENSE3 = 0x80,
+	HDMI_PHY_RX_SENSE2 = 0x40,
+	HDMI_PHY_RX_SENSE1 = 0x20,
+	HDMI_PHY_RX_SENSE0 = 0x10,
+	HDMI_PHY_HPD = 0x02,
+	HDMI_PHY_TX_PHY_LOCK = 0x01,
+
+/* Convenience macro RX_SENSE | HPD */
+	HDMI_DVI_STAT = 0xF2,
+
+/* PHY_I2CM_SLAVE_ADDR field values */
+	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
+	HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
+
+/* PHY_I2CM_OPERATION_ADDR field values */
+	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
+	HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
+
+/* HDMI_PHY_I2CM_INT_ADDR */
+	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
+	HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
+
+/* HDMI_PHY_I2CM_CTLINT_ADDR */
+	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
+	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
+	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
+	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
+
+/* AUD_CTS3 field values */
+	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
+	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
+	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
+	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
+	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
+	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
+	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
+	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
+	/* note that the CTS3 MANUAL bit has been removed
+	   from our part. Can't set it, will read as 0. */
+	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
+	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
+
+/* AHB_DMA_CONF0 field values */
+	HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
+	HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
+	HDMI_AHB_DMA_CONF0_HBR = 0x10,
+	HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
+	HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
+	HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
+	HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
+	HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
+	HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
+	HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
+	HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
+
+/* HDMI_AHB_DMA_START field values */
+	HDMI_AHB_DMA_START_START_OFFSET = 0,
+	HDMI_AHB_DMA_START_START_MASK = 0x01,
+
+/* HDMI_AHB_DMA_STOP field values */
+	HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
+	HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
+
+/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
+	HDMI_AHB_DMA_DONE = 0x80,
+	HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
+	HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
+	HDMI_AHB_DMA_ERROR = 0x10,
+	HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
+	HDMI_AHB_DMA_FIFO_FULL = 0x02,
+	HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
+
+/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
+	HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
+	HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
+
+/* MC_CLKDIS field values */
+	HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
+	HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
+	HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
+	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
+	HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
+	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
+	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
+
+/* MC_SWRSTZ field values */
+	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
+
+/* MC_FLOWCTRL field values */
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
+
+/* MC_PHYRSTZ field values */
+	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
+	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
+
+/* MC_HEACPHY_RST field values */
+	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
+	HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
+
+/* CSC_CFG field values */
+	HDMI_CSC_CFG_INTMODE_MASK = 0x30,
+	HDMI_CSC_CFG_INTMODE_OFFSET = 4,
+	HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
+	HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
+	HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
+	HDMI_CSC_CFG_DECMODE_MASK = 0x3,
+	HDMI_CSC_CFG_DECMODE_OFFSET = 0,
+	HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
+
+/* CSC_SCALE field values */
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
+	HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
+
+/* A_HDCPCFG0 field values */
+	HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
+	HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
+	HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
+	HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
+	HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
+	HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
+	HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
+	HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
+	HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
+	HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
+	HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
+	HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
+	HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
+	HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
+	HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
+	HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
+	HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
+	HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
+	HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
+	HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
+
+/* A_HDCPCFG1 field values */
+	HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
+	HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
+	HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
+	HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
+	HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
+	HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
+	HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
+	HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
+	HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
+	HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
+	HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
+
+/* A_VIDPOLCFG field values */
+	HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
+	HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
+	HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
+	HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
+	HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
+	HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
+	HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
+	HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
+	HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
+	HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
+	HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
+};
+
+#endif /* __MXC_HDMI_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/sys_proto.h
new file mode 100644
index 000000000..38851a135
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/imx-common/regs-common.h>
+#include "../arch-imx/cpu.h"
+
+#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
+u32 get_cpu_rev(void);
+
+/* returns MXC_CPU_ value */
+#define cpu_type(rev) (((rev) >> 12)&0xff)
+
+/* use with MXC_CPU_ constants */
+#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
+
+const char *get_imx_type(u32 imxtype);
+unsigned imx_ddr_size(void);
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+
+int fecmxc_initialize(bd_t *bis);
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
+
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg,
+		       uint32_t mask,
+		       unsigned int timeout);
+int mxs_wait_mask_clr(struct mxs_register_32 *reg,
+		       uint32_t mask,
+		       unsigned int timeout);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h
new file mode 100644
index 000000000..fc9d75b50
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/clock.h
@@ -0,0 +1,54 @@
+/*
+ * Freescale i.MX23/i.MX28 Clock
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CLOCK_H__
+#define __CLOCK_H__
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_EMI_CLK,
+	MXC_GPMI_CLK,
+	MXC_IO0_CLK,
+	MXC_IO1_CLK,
+	MXC_XTAL_CLK,
+	MXC_SSP0_CLK,
+#ifdef CONFIG_MX28
+	MXC_SSP1_CLK,
+	MXC_SSP2_CLK,
+	MXC_SSP3_CLK,
+#endif
+};
+
+enum mxs_ioclock {
+	MXC_IOCLK0 = 0,
+	MXC_IOCLK1,
+};
+
+enum mxs_sspclock {
+	MXC_SSPCLK0 = 0,
+#ifdef CONFIG_MX28
+	MXC_SSPCLK1,
+	MXC_SSPCLK2,
+	MXC_SSPCLK3,
+#endif
+};
+
+uint32_t mxc_get_clock(enum mxc_clock clk);
+
+void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
+void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
+void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
+void mxs_set_lcdclk(uint32_t freq);
+
+/* Compatibility with the FEC Ethernet driver */
+#define	imx_get_fecclk()	mxc_get_clock(MXC_AHB_CLK)
+
+#endif	/* __CLOCK_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h
new file mode 100644
index 000000000..3bdf879b1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * Freescale i.MX28 GPIO
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__MX28_GPIO_H__
+#define	__MX28_GPIO_H__
+
+#ifdef	CONFIG_MXS_GPIO
+void mxs_gpio_init(void);
+#else
+inline void mxs_gpio_init(void) {}
+#endif
+
+#endif	/* __MX28_GPIO_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/imx-regs.h
new file mode 100644
index 000000000..86914ef74
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -0,0 +1,39 @@
+/*
+ * Freescale i.MX23/i.MX28 Registers
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX_REGS_H__
+#define __IMX_REGS_H__
+
+#include <asm/imx-common/regs-apbh.h>
+#include <asm/arch/regs-base.h>
+#include <asm/imx-common/regs-bch.h>
+#include <asm/arch/regs-digctl.h>
+#include <asm/imx-common/regs-gpmi.h>
+#include <asm/arch/regs-i2c.h>
+#include <asm/arch/regs-lcdif.h>
+#include <asm/arch/regs-lradc.h>
+#include <asm/arch/regs-ocotp.h>
+#include <asm/arch/regs-pinctrl.h>
+#include <asm/arch/regs-rtc.h>
+#include <asm/arch/regs-ssp.h>
+#include <asm/arch/regs-timrot.h>
+#include <asm/arch/regs-usb.h>
+#include <asm/arch/regs-usbphy.h>
+
+#ifdef CONFIG_MX23
+#include <asm/arch/regs-clkctrl-mx23.h>
+#include <asm/arch/regs-power-mx23.h>
+#endif
+
+#ifdef CONFIG_MX28
+#include <asm/arch/regs-clkctrl-mx28.h>
+#include <asm/arch/regs-power-mx28.h>
+#endif
+
+#endif	/* __IMX_REGS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx23.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx23.h
new file mode 100644
index 000000000..7cb5e7168
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx23.h
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MACH_IOMUX_MX23_H__
+#define __MACH_IOMUX_MX23_H__
+
+#include <asm/arch/iomux.h>
+
+/*
+ * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux.h
+ *
+ *									BANK	PIN	MUX
+ */
+/* MUXSEL_0 */
+#define MX23_PAD_GPMI_D00__GPMI_D00		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D01__GPMI_D01		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D02__GPMI_D02		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D03__GPMI_D03		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D04__GPMI_D04		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D05__GPMI_D05		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D06__GPMI_D06		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D07__GPMI_D07		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D08__GPMI_D08		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D09__GPMI_D09		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D10__GPMI_D10		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D11__GPMI_D11		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D12__GPMI_D12		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D13__GPMI_D13		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D14__GPMI_D14		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D15__GPMI_D15		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CLE__GPMI_CLE		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_ALE__GPMI_ALE		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE2N__GPMI_CE2N		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY0__GPMI_RDY0		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY1__GPMI_RDY1		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY2__GPMI_RDY2		MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY3__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_WPN__GPMI_WPN		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_WRN__GPMI_WRN		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDN__GPMI_RDN		MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_CTS__AUART1_CTS		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_RTS__AUART1_RTS		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_RX__AUART1_RX		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_TX__AUART1_TX		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
+#define MX23_PAD_I2C_SCL__I2C_SCL		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
+#define MX23_PAD_I2C_SDA__I2C_SDA		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
+
+#define MX23_PAD_LCD_D00__LCD_D00		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D01__LCD_D01		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D02__LCD_D02		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D03__LCD_D03		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D04__LCD_D04		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D05__LCD_D05		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D06__LCD_D06		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D07__LCD_D07		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D08__LCD_D08		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D09__LCD_D09		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D10__LCD_D10		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D11__LCD_D11		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D12__LCD_D12		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D13__LCD_D13		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D14__LCD_D14		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D15__LCD_D15		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D16__LCD_D16		MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D17__LCD_D17		MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_RESET__LCD_RESET		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_RS__LCD_RS			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_WR__LCD_WR			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_CS__LCD_CS			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_DOTCK__LCD_DOTCK		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_ENABLE__LCD_ENABLE		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_HSYNC__LCD_HSYNC		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_VSYNC__LCD_VSYNC		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
+#define MX23_PAD_PWM0__PWM0			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
+#define MX23_PAD_PWM1__PWM1			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
+#define MX23_PAD_PWM2__PWM2			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
+#define MX23_PAD_PWM3__PWM3			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
+#define MX23_PAD_PWM4__PWM4			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
+
+#define MX23_PAD_SSP1_CMD__SSP1_CMD		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DETECT__SSP1_DETECT	MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA0__SSP1_DATA0		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA1__SSP1_DATA1		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA2__SSP1_DATA2		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA3__SSP1_DATA3		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_SCK__SSP1_SCK		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
+#define MX23_PAD_ROTARYA__ROTARYA		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
+#define MX23_PAD_ROTARYB__ROTARYB		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A00__EMI_A00		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A01__EMI_A01		MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A02__EMI_A02		MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A03__EMI_A03		MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A04__EMI_A04		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A05__EMI_A05		MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A06__EMI_A06		MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A07__EMI_A07		MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A08__EMI_A08		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A09__EMI_A09		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A10__EMI_A10		MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A11__EMI_A11		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A12__EMI_A12		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_BA0__EMI_BA0		MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_BA1__EMI_BA1		MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CASN__EMI_CASN		MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CE0N__EMI_CE0N		MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CE1N__EMI_CE1N		MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE1N__GPMI_CE1N		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE0N__GPMI_CE0N		MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CKE__EMI_CKE		MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_RASN__EMI_RASN		MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_WEN__EMI_WEN		MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
+
+#define MX23_PAD_EMI_D00__EMI_D00		MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D01__EMI_D01		MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D02__EMI_D02		MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D03__EMI_D03		MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D04__EMI_D04		MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D05__EMI_D05		MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D06__EMI_D06		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D07__EMI_D07		MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D08__EMI_D08		MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D09__EMI_D09		MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D10__EMI_D10		MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D11__EMI_D11		MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D12__EMI_D12		MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D13__EMI_D13		MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D14__EMI_D14		MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D15__EMI_D15		MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQM0__EMI_DQM0		MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQM1__EMI_DQM1		MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQS0__EMI_DQS0		MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQS1__EMI_DQS1		MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CLK__EMI_CLK		MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CLKN__EMI_CLKN		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
+
+/* MUXSEL_1 */
+#define MX23_PAD_GPMI_D00__LCD_D8		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D01__LCD_D9		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D02__LCD_D10		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D03__LCD_D11		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D04__LCD_D12		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D05__LCD_D13		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D06__LCD_D14		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D07__LCD_D15		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D08__LCD_D18		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D09__LCD_D19		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D10__LCD_D20		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D11__LCD_D21		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D12__LCD_D22		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D13__LCD_D23		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D14__AUART2_RX		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D15__AUART2_TX		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_CLE__LCD_D16		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_ALE__LCD_D17		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_CE2N__ATA_A2		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_RTS__IR_CLK		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_RX__IR_RX		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_TX__IR_TX		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
+#define MX23_PAD_I2C_SCL__GPMI_RDY2		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
+#define MX23_PAD_I2C_SDA__GPMI_CE2N		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
+
+#define MX23_PAD_LCD_D00__ETM_DA8		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D01__ETM_DA9		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D02__ETM_DA10		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D03__ETM_DA11		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D04__ETM_DA12		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D05__ETM_DA13		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D06__ETM_DA14		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D07__ETM_DA15		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D08__ETM_DA0		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D09__ETM_DA1		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D10__ETM_DA2		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D11__ETM_DA3		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D12__ETM_DA4		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D13__ETM_DA5		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D14__ETM_DA6		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D15__ETM_DA7		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_RESET__ETM_TCTL		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_RS__ETM_TCLK		MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_DOTCK__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_ENABLE__I2C_SCL		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_HSYNC__I2C_SDA		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_VSYNC__LCD_BUSY		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
+#define MX23_PAD_PWM0__ROTARYA			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
+#define MX23_PAD_PWM1__ROTARYB			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
+#define MX23_PAD_PWM2__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
+#define MX23_PAD_PWM3__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
+#define MX23_PAD_PWM4__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
+
+#define MX23_PAD_SSP1_DETECT__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DATA1__I2C_SCL		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DATA2__I2C_SDA		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
+#define MX23_PAD_ROTARYA__AUART2_RTS		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
+#define MX23_PAD_ROTARYB__AUART2_CTS		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_1)
+
+/* MUXSEL_2 */
+#define MX23_PAD_GPMI_D00__SSP2_DATA0		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D01__SSP2_DATA1		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D02__SSP2_DATA2		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D03__SSP2_DATA3		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D04__SSP2_DATA4		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D05__SSP2_DATA5		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D06__SSP2_DATA6		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D07__SSP2_DATA7		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D08__SSP1_DATA4		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D09__SSP1_DATA5		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D10__SSP1_DATA6		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D11__SSP1_DATA7		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D15__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_RDY0__SSP2_DETECT		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_RDY1__SSP2_CMD		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_WRN__SSP2_SCK		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_CTS__SSP1_DATA4		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_RTS__SSP1_DATA5		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_RX__SSP1_DATA6		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_TX__SSP1_DATA7		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
+#define MX23_PAD_I2C_SCL__AUART1_TX		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
+#define MX23_PAD_I2C_SDA__AUART1_RX		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
+
+#define MX23_PAD_LCD_D08__SAIF2_SDATA0		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D09__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK	MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D11__SAIF_LRCLK		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D12__SAIF2_SDATA1		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D13__SAIF2_SDATA2		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D14__SAIF1_SDATA2		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D15__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK	MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_RESET__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
+#define MX23_PAD_PWM0__DUART_RX			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
+#define MX23_PAD_PWM1__DUART_TX			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
+#define MX23_PAD_PWM3__AUART1_CTS		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
+#define MX23_PAD_PWM4__AUART1_RTS		MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
+
+#define MX23_PAD_SSP1_CMD__JTAG_TDO		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DETECT__USB_OTG_ID	MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA0__JTAG_TDI		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA1__JTAG_TCLK		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA2__JTAG_RTCK		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA3__JTAG_TMS		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_SCK__JTAG_TRST		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_2)
+#define MX23_PAD_ROTARYA__SPDIF			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_2)
+#define MX23_PAD_ROTARYB__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
+
+/* MUXSEL_GPIO */
+#define MX23_PAD_GPMI_D00__GPIO_0_0		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D01__GPIO_0_1		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D02__GPIO_0_2		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D03__GPIO_0_3		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D04__GPIO_0_4		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D05__GPIO_0_5		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D06__GPIO_0_6		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D07__GPIO_0_7		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D08__GPIO_0_8		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D09__GPIO_0_9		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D10__GPIO_0_10		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D11__GPIO_0_11		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D12__GPIO_0_12		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D13__GPIO_0_13		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D14__GPIO_0_14		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D15__GPIO_0_15		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CLE__GPIO_0_16		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_ALE__GPIO_0_17		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE2N__GPIO_0_18		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY0__GPIO_0_19		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY1__GPIO_0_20		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY2__GPIO_0_21		MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY3__GPIO_0_22		MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WPN__GPIO_0_23		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WRN__GPIO_0_24		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDN__GPIO_0_25		MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_CTS__GPIO_0_26		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RTS__GPIO_0_27		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RX__GPIO_0_28		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_TX__GPIO_0_29		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SCL__GPIO_0_30		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SDA__GPIO_0_31		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
+
+#define MX23_PAD_LCD_D00__GPIO_1_0		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D01__GPIO_1_1		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D02__GPIO_1_2		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D03__GPIO_1_3		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D04__GPIO_1_4		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D05__GPIO_1_5		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D06__GPIO_1_6		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D07__GPIO_1_7		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D08__GPIO_1_8		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D09__GPIO_1_9		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D10__GPIO_1_10		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D11__GPIO_1_11		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D12__GPIO_1_12		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D13__GPIO_1_13		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D14__GPIO_1_14		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D15__GPIO_1_15		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D16__GPIO_1_16		MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D17__GPIO_1_17		MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RESET__GPIO_1_18		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RS__GPIO_1_19		MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_WR__GPIO_1_20		MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_CS__GPIO_1_21		MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_DOTCK__GPIO_1_22		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_ENABLE__GPIO_1_23		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_HSYNC__GPIO_1_24		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_VSYNC__GPIO_1_25		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM0__GPIO_1_26		MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM1__GPIO_1_27		MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM2__GPIO_1_28		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM3__GPIO_1_29		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM4__GPIO_1_30		MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+
+#define MX23_PAD_SSP1_CMD__GPIO_2_0		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DETECT__GPIO_2_1		MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA0__GPIO_2_2		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA1__GPIO_2_3		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA2__GPIO_2_4		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA3__GPIO_2_5		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_SCK__GPIO_2_6		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYA__GPIO_2_7		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYB__GPIO_2_8		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A00__GPIO_2_9		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A01__GPIO_2_10		MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A02__GPIO_2_11		MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A03__GPIO_2_12		MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A04__GPIO_2_13		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A05__GPIO_2_14		MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A06__GPIO_2_15		MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A07__GPIO_2_16		MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A08__GPIO_2_17		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A09__GPIO_2_18		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A10__GPIO_2_19		MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A11__GPIO_2_20		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A12__GPIO_2_21		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA0__GPIO_2_22		MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA1__GPIO_2_23		MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CASN__GPIO_2_24		MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE0N__GPIO_2_25		MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE1N__GPIO_2_26		MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE1N__GPIO_2_27		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE0N__GPIO_2_28		MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CKE__GPIO_2_29		MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_RASN__GPIO_2_30		MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_WEN__GPIO_2_31		MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
+
+#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx28.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx28.h
new file mode 100644
index 000000000..b42820de7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux-mx28.h
@@ -0,0 +1,537 @@
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MACH_IOMUX_MX28_H__
+#define __MACH_IOMUX_MX28_H__
+
+#include <asm/arch/iomux.h>
+
+/*
+ * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux.h
+ *
+ *									BANK	PIN	MUX
+ */
+/* MUXSEL_0 */
+#define MX28_PAD_GPMI_D00__GPMI_D0			MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D01__GPMI_D1			MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D02__GPMI_D2			MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D03__GPMI_D3			MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D04__GPMI_D4			MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D05__GPMI_D5			MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D06__GPMI_D6			MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D07__GPMI_D7			MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE0N__GPMI_CE0N			MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE1N__GPMI_CE1N			MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE2N__GPMI_CE2N			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE3N__GPMI_CE3N			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY0__GPMI_READY0			MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY1__GPMI_READY1			MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY2__GPMI_READY2			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY3__GPMI_READY3			MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDN__GPMI_RDN			MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_WRN__GPMI_WRN			MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_ALE__GPMI_ALE			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CLE__GPMI_CLE			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RESETN__GPMI_RESETN		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
+
+#define MX28_PAD_LCD_D00__LCD_D0			MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D01__LCD_D1			MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D02__LCD_D2			MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D03__LCD_D3			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D04__LCD_D4			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D05__LCD_D5			MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D06__LCD_D6			MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D07__LCD_D7			MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D08__LCD_D8			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D09__LCD_D9			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D10__LCD_D10			MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D11__LCD_D11			MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D12__LCD_D12			MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D13__LCD_D13			MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D14__LCD_D14			MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D15__LCD_D15			MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D16__LCD_D16			MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D17__LCD_D17			MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D18__LCD_D18			MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D19__LCD_D19			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D20__LCD_D20			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D21__LCD_D21			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D22__LCD_D22			MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D23__LCD_D23			MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RD_E__LCD_RD_E			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RS__LCD_RS				MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_CS__LCD_CS				MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_VSYNC__LCD_VSYNC			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_HSYNC__LCD_HSYNC			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_ENABLE__LCD_ENABLE			MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
+
+#define MX28_PAD_SSP0_DATA0__SSP0_D0			MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA1__SSP0_D1			MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA2__SSP0_D2			MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA3__SSP0_D3			MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA4__SSP0_D4			MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA5__SSP0_D5			MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA6__SSP0_D6			MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA7__SSP0_D7			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_CMD__SSP0_CMD			MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_SCK__SSP0_SCK			MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_SCK__SSP1_SCK			MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_CMD__SSP1_CMD			MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_DATA0__SSP1_D0			MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_DATA3__SSP1_D3			MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SCK__SSP2_SCK			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_MOSI__SSP2_CMD			MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_MISO__SSP2_D0			MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS0__SSP2_D3			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS1__SSP2_D4			MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS2__SSP2_D5			MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_SCK__SSP3_SCK			MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_MOSI__SSP3_CMD			MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_MISO__SSP3_D0			MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_SS0__SSP3_D3			MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
+
+#define MX28_PAD_AUART0_RX__AUART0_RX			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_TX__AUART0_TX			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_CTS__AUART0_CTS			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_RTS__AUART0_RTS			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_RX__AUART1_RX			MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_TX__AUART1_TX			MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_CTS__AUART1_CTS			MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_RTS__AUART1_RTS			MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_RX__AUART2_RX			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_TX__AUART2_TX			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_CTS__AUART2_CTS			MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_RTS__AUART2_RTS			MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_RX__AUART3_RX			MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_TX__AUART3_TX			MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_CTS__AUART3_CTS			MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_RTS__AUART3_RTS			MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
+#define MX28_PAD_PWM0__PWM_0				MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
+#define MX28_PAD_PWM1__PWM_1				MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
+#define MX28_PAD_PWM2__PWM_2				MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK		MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0		MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
+#define MX28_PAD_I2C0_SCL__I2C0_SCL			MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
+#define MX28_PAD_I2C0_SDA__I2C0_SDA			MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
+#define MX28_PAD_SPDIF__SPDIF_TX			MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
+#define MX28_PAD_PWM3__PWM_3				MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
+#define MX28_PAD_PWM4__PWM_4				MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RESET__LCD_RESET			MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
+
+#define MX28_PAD_ENET0_MDC__ENET0_MDC			MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_MDIO__ENET0_MDIO			MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN		MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD0__ENET0_RXD0			MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD1__ENET0_RXD1			MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK		MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN		MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD0__ENET0_TXD0			MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD1__ENET0_TXD1			MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD2__ENET0_RXD2			MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD3__ENET0_RXD3			MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD2__ENET0_TXD2			MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD3__ENET0_TXD3			MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK		MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_COL__ENET0_COL			MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_CRS__ENET0_CRS			MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
+#define MX28_PAD_ENET_CLK__CLKCTRL_ENET			MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
+#define MX28_PAD_JTAG_RTCK__JTAG_RTCK			MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
+
+#define MX28_PAD_EMI_D00__EMI_DATA0			MXS_IOMUX_PAD_NAKED(5,  0, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D01__EMI_DATA1			MXS_IOMUX_PAD_NAKED(5,  1, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D02__EMI_DATA2			MXS_IOMUX_PAD_NAKED(5,  2, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D03__EMI_DATA3			MXS_IOMUX_PAD_NAKED(5,  3, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D04__EMI_DATA4			MXS_IOMUX_PAD_NAKED(5,  4, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D05__EMI_DATA5			MXS_IOMUX_PAD_NAKED(5,  5, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D06__EMI_DATA6			MXS_IOMUX_PAD_NAKED(5,  6, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D07__EMI_DATA7			MXS_IOMUX_PAD_NAKED(5,  7, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D08__EMI_DATA8			MXS_IOMUX_PAD_NAKED(5,  8, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D09__EMI_DATA9			MXS_IOMUX_PAD_NAKED(5,  9, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D10__EMI_DATA10			MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D11__EMI_DATA11			MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D12__EMI_DATA12			MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D13__EMI_DATA13			MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D14__EMI_DATA14			MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D15__EMI_DATA15			MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_ODT0__EMI_ODT0			MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQM0__EMI_DQM0			MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_ODT1__EMI_ODT1			MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQM1__EMI_DQM1			MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK	MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CLK__EMI_CLK			MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQS0__EMI_DQS0			MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQS1__EMI_DQS1			MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN		MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
+
+#define MX28_PAD_EMI_A00__EMI_ADDR0			MXS_IOMUX_PAD_NAKED(6,  0, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A01__EMI_ADDR1			MXS_IOMUX_PAD_NAKED(6,  1, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A02__EMI_ADDR2			MXS_IOMUX_PAD_NAKED(6,  2, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A03__EMI_ADDR3			MXS_IOMUX_PAD_NAKED(6,  3, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A04__EMI_ADDR4			MXS_IOMUX_PAD_NAKED(6,  4, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A05__EMI_ADDR5			MXS_IOMUX_PAD_NAKED(6,  5, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A06__EMI_ADDR6			MXS_IOMUX_PAD_NAKED(6,  6, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A07__EMI_ADDR7			MXS_IOMUX_PAD_NAKED(6,  7, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A08__EMI_ADDR8			MXS_IOMUX_PAD_NAKED(6,  8, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A09__EMI_ADDR9			MXS_IOMUX_PAD_NAKED(6,  9, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A10__EMI_ADDR10			MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A11__EMI_ADDR11			MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A12__EMI_ADDR12			MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A13__EMI_ADDR13			MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A14__EMI_ADDR14			MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA0__EMI_BA0			MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA1__EMI_BA1			MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA2__EMI_BA2			MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CASN__EMI_CASN			MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_RASN__EMI_RASN			MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_WEN__EMI_WEN			MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CE0N__EMI_CE0N			MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CE1N__EMI_CE1N			MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CKE__EMI_CKE			MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
+
+/* MUXSEL_1 */
+#define MX28_PAD_GPMI_D00__SSP1_D0			MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D01__SSP1_D1			MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D02__SSP1_D2			MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D03__SSP1_D3			MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D04__SSP1_D4			MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D05__SSP1_D5			MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D06__SSP1_D6			MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D07__SSP1_D7			MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE0N__SSP3_D0			MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE1N__SSP3_D3			MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE2N__CAN1_TX			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE3N__CAN1_RX			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY1__SSP1_CMD			MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY2__CAN0_TX			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY3__CAN0_RX			MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDN__SSP3_SCK			MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_WRN__SSP1_SCK			MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_ALE__SSP3_D1			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CLE__SSP3_D2			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RESETN__SSP3_CMD			MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
+
+#define MX28_PAD_LCD_D03__ETM_DA8			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D04__ETM_DA9			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D08__ETM_DA3			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D09__ETM_DA4			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT		MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN		MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RD_E__LCD_VSYNC			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RS__LCD_DOTCLK			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_CS__LCD_ENABLE			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
+
+#define MX28_PAD_SSP0_DATA4__SSP2_D0			MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA5__SSP2_D3			MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA6__SSP2_CMD			MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA7__SSP2_SCK			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_SCK__SSP2_D1			MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_CMD__SSP2_D2			MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_DATA0__SSP2_D6			MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_DATA3__SSP2_D7			MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SCK__AUART2_RX			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_MOSI__AUART2_TX			MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_MISO__AUART3_RX			MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS0__AUART3_TX			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS1__SSP2_D1			MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS2__SSP2_D2			MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_SCK__AUART4_TX			MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_MOSI__AUART4_RX			MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_MISO__AUART4_RTS			MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_SS0__AUART4_CTS			MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
+
+#define MX28_PAD_AUART0_RX__I2C0_SCL			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_TX__I2C0_SDA			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_CTS__AUART4_RX			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_RTS__AUART4_TX			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT		MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT		MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_RTS__USB0_ID			MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_RX__SSP3_D1			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_TX__SSP3_D2			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_CTS__I2C1_SCL			MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_RTS__I2C1_SDA			MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_RX__CAN0_TX			MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_TX__CAN0_RX			MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_CTS__CAN1_TX			MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_RTS__CAN1_RX			MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
+#define MX28_PAD_PWM0__I2C1_SCL				MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
+#define MX28_PAD_PWM1__I2C1_SDA				MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
+#define MX28_PAD_PWM2__USB0_ID				MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_MCLK__PWM_3			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_LRCLK__PWM_4			MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_BITCLK__PWM_5			MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_SDATA0__PWM_6			MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
+#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA		MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
+#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB		MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF1_SDATA0__PWM_7			MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RESET__LCD_VSYNC			MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
+
+#define MX28_PAD_ENET0_MDC__GPMI_CE4N			MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_MDIO__GPMI_CE5N			MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N			MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD0__GPMI_CE7N			MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD1__GPMI_READY4		MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER		MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TX_EN__GPMI_READY5		MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD0__GPMI_READY6		MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD1__GPMI_READY7		MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD2__ENET1_RXD0			MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD3__ENET1_RXD1			MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD2__ENET1_TXD0			MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD3__ENET1_TXD1			MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER		MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_COL__ENET1_TX_EN			MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_CRS__ENET1_RX_EN			MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
+
+/* MUXSEL_2 */
+#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY0__USB0_ID			MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_ALE__SSP3_D4			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_CLE__SSP3_D5			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_LCD_D00__ETM_DA0			MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D01__ETM_DA1			MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D02__ETM_DA2			MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D03__ETM_DA3			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D04__ETM_DA4			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D05__ETM_DA5			MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D06__ETM_DA6			MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D07__ETM_DA7			MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D08__ETM_DA8			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D09__ETM_DA9			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D10__ETM_DA10			MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D11__ETM_DA11			MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D12__ETM_DA12			MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D13__ETM_DA13			MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D14__ETM_DA14			MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D15__ETM_DA15			MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D16__ETM_DA7			MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D17__ETM_DA6			MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D18__ETM_DA5			MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D19__ETM_DA4			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D20__ETM_DA3			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D21__ETM_DA2			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D22__ETM_DA1			MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D23__ETM_DA0			MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_RD_E__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_WR_RWN__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_HSYNC__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_DOTCLK__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
+
+#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT	MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT	MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN	MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT	MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN	MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT	MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_AUART0_RX__DUART_CTS			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_TX__DUART_RTS			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_CTS__DUART_RX			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_RTS__DUART_TX			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_RX__PWM_0			MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_TX__PWM_1			MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB		MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_RX__SSP3_D4			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_TX__SSP3_D5			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK		MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK		MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT	MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN	MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT	MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN	MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
+#define MX28_PAD_PWM0__DUART_RX				MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
+#define MX28_PAD_PWM1__DUART_TX				MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
+#define MX28_PAD_PWM2__USB1_OVERCURRENT			MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_MCLK__AUART4_CTS			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_BITCLK__AUART4_RX		MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_SDATA0__AUART4_TX		MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
+#define MX28_PAD_I2C0_SCL__DUART_RX			MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
+#define MX28_PAD_I2C0_SDA__DUART_TX			MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1		MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
+#define MX28_PAD_SPDIF__ENET1_RX_ER			MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1		MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2		MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2		MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT	MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT	MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN	MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT	MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN	MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN	MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT	MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN	MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
+
+/* MUXSEL_GPIO */
+#define MX28_PAD_GPMI_D00__GPIO_0_0			MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D01__GPIO_0_1			MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D02__GPIO_0_2			MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D03__GPIO_0_3			MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D04__GPIO_0_4			MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D05__GPIO_0_5			MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D06__GPIO_0_6			MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D07__GPIO_0_7			MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE0N__GPIO_0_16			MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE1N__GPIO_0_17			MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE2N__GPIO_0_18			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE3N__GPIO_0_19			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY0__GPIO_0_20			MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY1__GPIO_0_21			MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY2__GPIO_0_22			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY3__GPIO_0_23			MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDN__GPIO_0_24			MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_WRN__GPIO_0_25			MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_ALE__GPIO_0_26			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CLE__GPIO_0_27			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RESETN__GPIO_0_28			MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_LCD_D00__GPIO_1_0			MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D01__GPIO_1_1			MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D02__GPIO_1_2			MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D03__GPIO_1_3			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D04__GPIO_1_4			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D05__GPIO_1_5			MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D06__GPIO_1_6			MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D07__GPIO_1_7			MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D08__GPIO_1_8			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D09__GPIO_1_9			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D10__GPIO_1_10			MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D11__GPIO_1_11			MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D12__GPIO_1_12			MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D13__GPIO_1_13			MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D14__GPIO_1_14			MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D15__GPIO_1_15			MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D16__GPIO_1_16			MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D17__GPIO_1_17			MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D18__GPIO_1_18			MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D19__GPIO_1_19			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D20__GPIO_1_20			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D21__GPIO_1_21			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D22__GPIO_1_22			MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D23__GPIO_1_23			MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RD_E__GPIO_1_24			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_WR_RWN__GPIO_1_25			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RS__GPIO_1_26			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_CS__GPIO_1_27			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_VSYNC__GPIO_1_28			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_HSYNC__GPIO_1_29			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_DOTCLK__GPIO_1_30			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_ENABLE__GPIO_1_31			MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_SSP0_DATA0__GPIO_2_0			MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA1__GPIO_2_1			MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA2__GPIO_2_2			MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA3__GPIO_2_3			MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA4__GPIO_2_4			MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA5__GPIO_2_5			MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA6__GPIO_2_6			MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA7__GPIO_2_7			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_CMD__GPIO_2_8			MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DETECT__GPIO_2_9			MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_SCK__GPIO_2_10			MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_SCK__GPIO_2_12			MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_CMD__GPIO_2_13			MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_DATA0__GPIO_2_14			MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_DATA3__GPIO_2_15			MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SCK__GPIO_2_16			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_MOSI__GPIO_2_17			MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_MISO__GPIO_2_18			MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS0__GPIO_2_19			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS1__GPIO_2_20			MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS2__GPIO_2_21			MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_SCK__GPIO_2_24			MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_MOSI__GPIO_2_25			MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_MISO__GPIO_2_26			MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_SS0__GPIO_2_27			MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_AUART0_RX__GPIO_3_0			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_TX__GPIO_3_1			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_CTS__GPIO_3_2			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_RTS__GPIO_3_3			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_RX__GPIO_3_4			MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_TX__GPIO_3_5			MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_CTS__GPIO_3_6			MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_RTS__GPIO_3_7			MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_RX__GPIO_3_8			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_TX__GPIO_3_9			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_CTS__GPIO_3_10			MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_RTS__GPIO_3_11			MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_RX__GPIO_3_12			MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_TX__GPIO_3_13			MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_CTS__GPIO_3_14			MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_RTS__GPIO_3_15			MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM0__GPIO_3_16			MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM1__GPIO_3_17			MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM2__GPIO_3_18			MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_MCLK__GPIO_3_20			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21			MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22		MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23		MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_I2C0_SCL__GPIO_3_24			MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_I2C0_SDA__GPIO_3_25			MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26		MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SPDIF__GPIO_3_27			MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM3__GPIO_3_28			MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM4__GPIO_3_29			MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RESET__GPIO_3_30			MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_ENET0_MDC__GPIO_4_0			MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_MDIO__GPIO_4_1			MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RX_EN__GPIO_4_2			MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD0__GPIO_4_3			MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD1__GPIO_4_4			MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5			MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TX_EN__GPIO_4_6			MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD0__GPIO_4_7			MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD1__GPIO_4_8			MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD2__GPIO_4_9			MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD3__GPIO_4_10			MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD2__GPIO_4_11			MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD3__GPIO_4_12			MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13		MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_COL__GPIO_4_14			MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_CRS__GPIO_4_15			MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET_CLK__GPIO_4_16			MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_JTAG_RTCK__GPIO_4_20			MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
+
+#endif /* __MACH_IOMUX_MX28_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h
new file mode 100644
index 000000000..3d1149130
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/iomux.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *			<armlinux@phytec.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MACH_MXS_IOMUX_H__
+#define __MACH_MXS_IOMUX_H__
+
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
+/*
+ * IOMUX/PAD Bit field definitions
+ *
+ * PAD_BANK:		 0..2	(3)
+ * PAD_PIN:		 3..7	(5)
+ * PAD_MUXSEL:		 8..9	(2)
+ * PAD_MA:		10..11	(2)
+ * PAD_MA_VALID:	12	(1)
+ * PAD_VOL:		13	(1)
+ * PAD_VOL_VALID:	14	(1)
+ * PAD_PULL:		15	(1)
+ * PAD_PULL_VALID:	16	(1)
+ * RESERVED:		17..31	(15)
+ */
+typedef u32 iomux_cfg_t;
+
+#define MXS_PAD_BANK_SHIFT	0
+#define MXS_PAD_BANK_MASK	((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
+#define MXS_PAD_PIN_SHIFT	3
+#define MXS_PAD_PIN_MASK	((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
+#define MXS_PAD_MUXSEL_SHIFT	8
+#define MXS_PAD_MUXSEL_MASK	((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
+#define MXS_PAD_MA_SHIFT	10
+#define MXS_PAD_MA_MASK		((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
+#define MXS_PAD_MA_VALID_SHIFT	12
+#define MXS_PAD_MA_VALID_MASK	((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
+#define MXS_PAD_VOL_SHIFT	13
+#define MXS_PAD_VOL_MASK	((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
+#define MXS_PAD_VOL_VALID_SHIFT	14
+#define MXS_PAD_VOL_VALID_MASK	((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
+#define MXS_PAD_PULL_SHIFT	15
+#define MXS_PAD_PULL_MASK	((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
+#define MXS_PAD_PULL_VALID_SHIFT 16
+#define MXS_PAD_PULL_VALID_MASK	((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
+
+#define PAD_MUXSEL_0		0
+#define PAD_MUXSEL_1		1
+#define PAD_MUXSEL_2		2
+#define PAD_MUXSEL_GPIO		3
+
+#define PAD_4MA			0
+#define PAD_8MA			1
+#define PAD_12MA		2
+#define PAD_16MA		3
+
+#define PAD_1V8			0
+#if defined(CONFIG_MX28)
+#define PAD_3V3			1
+#else
+#define PAD_3V3			0
+#endif
+
+#define PAD_NOPULL		0
+#define PAD_PULLUP		1
+
+#define MXS_PAD_4MA	((PAD_4MA << MXS_PAD_MA_SHIFT) | \
+					MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_8MA	((PAD_8MA << MXS_PAD_MA_SHIFT) | \
+					MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_12MA	((PAD_12MA << MXS_PAD_MA_SHIFT) | \
+					MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_16MA	((PAD_16MA << MXS_PAD_MA_SHIFT) | \
+					MXS_PAD_MA_VALID_MASK)
+
+#define MXS_PAD_1V8	((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
+					MXS_PAD_VOL_VALID_MASK)
+#define MXS_PAD_3V3	((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
+					MXS_PAD_VOL_VALID_MASK)
+
+#define MXS_PAD_NOPULL	((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
+					MXS_PAD_PULL_VALID_MASK)
+#define MXS_PAD_PULLUP	((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
+					MXS_PAD_PULL_VALID_MASK)
+
+/* generic pad control used in most cases */
+#define MXS_PAD_CTRL	(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
+
+#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull)		\
+		(((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) |		\
+		((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) |		\
+		((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) |	\
+		((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) |		\
+		((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) |		\
+		((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
+
+/*
+ * A pad becomes naked, when none of mA, vol or pull
+ * validity bits is set.
+ */
+#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
+		MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
+
+static inline unsigned int PAD_BANK(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
+}
+
+static inline unsigned int PAD_PIN(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
+}
+
+static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
+}
+
+static inline unsigned int PAD_MA(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
+}
+
+static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
+}
+
+static inline unsigned int PAD_VOL(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
+}
+
+static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
+}
+
+static inline unsigned int PAD_PULL(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
+}
+
+static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
+}
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxs_iomux_setup_pad(iomux_cfg_t pad);
+
+/*
+ * configures multiple pads
+ * convenient way to call the above function with tables
+ */
+int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-base.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-base.h
new file mode 100644
index 000000000..213df514b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-base.h
@@ -0,0 +1,121 @@
+/*
+ * Freescale i.MX23/i.MX28 Peripheral Base Addresses
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2008 Embedded Alley Solutions Inc.
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MXS_REGS_BASE_H__
+#define __MXS_REGS_BASE_H__
+
+/*
+ * Register base addresses for i.MX23
+ */
+#if defined(CONFIG_MX23)
+#define	MXS_ICOLL_BASE		0x80000000
+#define	MXS_APBH_BASE		0x80004000
+#define	MXS_ECC8_BASE		0x80008000
+#define	MXS_BCH_BASE		0x8000A000
+#define	MXS_GPMI_BASE		0x8000C000
+#define	MXS_SSP0_BASE		0x80010000
+#define	MXS_SSP1_BASE		0x80034000
+#define	MXS_ETM_BASE		0x80014000
+#define	MXS_PINCTRL_BASE	0x80018000
+#define	MXS_DIGCTL_BASE		0x8001C000
+#define	MXS_EMI_BASE		0x80020000
+#define	MXS_APBX_BASE		0x80024000
+#define	MXS_DCP_BASE		0x80028000
+#define	MXS_PXP_BASE		0x8002A000
+#define	MXS_OCOTP_BASE		0x8002C000
+#define	MXS_AXI_BASE		0x8002E000
+#define	MXS_LCDIF_BASE		0x80030000
+#define	MXS_SSP1_BASE		0x80034000
+#define	MXS_TVENC_BASE		0x80038000
+#define	MXS_CLKCTRL_BASE	0x80040000
+#define	MXS_SAIF0_BASE		0x80042000
+#define	MXS_POWER_BASE		0x80044000
+#define	MXS_SAIF1_BASE		0x80046000
+#define	MXS_AUDIOOUT_BASE	0x80048000
+#define	MXS_AUDIOIN_BASE	0x8004C000
+#define	MXS_LRADC_BASE		0x80050000
+#define	MXS_SPDIF_BASE		0x80054000
+#define	MXS_I2C0_BASE		0x80058000
+#define	MXS_RTC_BASE		0x8005C000
+#define	MXS_PWM_BASE		0x80064000
+#define	MXS_TIMROT_BASE		0x80068000
+#define	MXS_UARTAPP0_BASE	0x8006C000
+#define	MXS_UARTAPP1_BASE	0x8006E000
+#define	MXS_UARTDBG_BASE	0x80070000
+#define	MXS_USBPHY0_BASE	0x8007C000
+#define	MXS_USBCTRL0_BASE	0x80080000
+#define	MXS_DRAM_BASE		0x800E0000
+
+/*
+ * Register base addresses for i.MX28
+ */
+#elif defined(CONFIG_MX28)
+#define	MXS_ICOL_BASE		0x80000000
+#define	MXS_HSADC_BASE		0x80002000
+#define	MXS_APBH_BASE		0x80004000
+#define	MXS_PERFMON_BASE	0x80006000
+#define	MXS_BCH_BASE		0x8000A000
+#define	MXS_GPMI_BASE		0x8000C000
+#define	MXS_SSP0_BASE		0x80010000
+#define	MXS_SSP1_BASE		0x80012000
+#define	MXS_SSP2_BASE		0x80014000
+#define	MXS_SSP3_BASE		0x80016000
+#define	MXS_PINCTRL_BASE	0x80018000
+#define	MXS_DIGCTL_BASE		0x8001C000
+#define	MXS_ETM_BASE		0x80022000
+#define	MXS_APBX_BASE		0x80024000
+#define	MXS_DCP_BASE		0x80028000
+#define	MXS_PXP_BASE		0x8002A000
+#define	MXS_OCOTP_BASE		0x8002C000
+#define	MXS_AXI_AHB0_BASE	0x8002E000
+#define	MXS_LCDIF_BASE		0x80030000
+#define	MXS_CAN0_BASE		0x80032000
+#define	MXS_CAN1_BASE		0x80034000
+#define	MXS_SIMDBG_BASE		0x8003C000
+#define	MXS_SIMGPMISEL_BASE	0x8003C200
+#define	MXS_SIMSSPSEL_BASE	0x8003C300
+#define	MXS_SIMMEMSEL_BASE	0x8003C400
+#define	MXS_GPIOMON_BASE	0x8003C500
+#define	MXS_SIMENET_BASE	0x8003C700
+#define	MXS_ARMJTAG_BASE	0x8003C800
+#define	MXS_CLKCTRL_BASE	0x80040000
+#define	MXS_SAIF0_BASE		0x80042000
+#define	MXS_POWER_BASE		0x80044000
+#define	MXS_SAIF1_BASE		0x80046000
+#define	MXS_LRADC_BASE		0x80050000
+#define	MXS_SPDIF_BASE		0x80054000
+#define	MXS_RTC_BASE		0x80056000
+#define	MXS_I2C0_BASE		0x80058000
+#define	MXS_I2C1_BASE		0x8005A000
+#define	MXS_PWM_BASE		0x80064000
+#define	MXS_TIMROT_BASE		0x80068000
+#define	MXS_UARTAPP0_BASE	0x8006A000
+#define	MXS_UARTAPP1_BASE	0x8006C000
+#define	MXS_UARTAPP2_BASE	0x8006E000
+#define	MXS_UARTAPP3_BASE	0x80070000
+#define	MXS_UARTAPP4_BASE	0x80072000
+#define	MXS_UARTDBG_BASE	0x80074000
+#define	MXS_USBPHY0_BASE	0x8007C000
+#define	MXS_USBPHY1_BASE	0x8007E000
+#define	MXS_USBCTRL0_BASE	0x80080000
+#define	MXS_USBCTRL1_BASE	0x80090000
+#define	MXS_DFLPT_BASE		0x800C0000
+#define	MXS_DRAM_BASE		0x800E0000
+#define	MXS_ENET0_BASE		0x800F0000
+#define	MXS_ENET1_BASE		0x800F4000
+#else
+#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28
+#endif
+
+#endif /* __MXS_REGS_BASE_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
new file mode 100644
index 000000000..d155e3a5d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
@@ -0,0 +1,208 @@
+/*
+ * Freescale i.MX23 CLKCTRL Register Definitions
+ *
+ * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX23_REGS_CLKCTRL_H__
+#define __MX23_REGS_CLKCTRL_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_clkctrl_regs {
+	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
+	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
+	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
+	mxs_reg_32(hw_clkctrl_cpu)		/* 0x20 */
+	mxs_reg_32(hw_clkctrl_hbus)		/* 0x30 */
+	mxs_reg_32(hw_clkctrl_xbus)		/* 0x40 */
+	mxs_reg_32(hw_clkctrl_xtal)		/* 0x50 */
+	mxs_reg_32(hw_clkctrl_pix)		/* 0x60 */
+	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x70 */
+	mxs_reg_32(hw_clkctrl_gpmi)		/* 0x80 */
+	mxs_reg_32(hw_clkctrl_spdif)		/* 0x90 */
+	mxs_reg_32(hw_clkctrl_emi)		/* 0xa0 */
+
+	uint32_t	reserved1[4];
+
+	mxs_reg_32(hw_clkctrl_saif0)		/* 0xc0 */
+	mxs_reg_32(hw_clkctrl_tv)		/* 0xd0 */
+	mxs_reg_32(hw_clkctrl_etm)		/* 0xe0 */
+	mxs_reg_8(hw_clkctrl_frac0)		/* 0xf0 */
+	mxs_reg_8(hw_clkctrl_frac1)		/* 0x100 */
+	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x110 */
+	mxs_reg_32(hw_clkctrl_reset)		/* 0x120 */
+	mxs_reg_32(hw_clkctrl_status)		/* 0x130 */
+	mxs_reg_32(hw_clkctrl_version)		/* 0x140 */
+};
+#endif
+
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
+#define	CLKCTRL_PLL0CTRL0_POWER			(1 << 16)
+
+#define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
+#define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
+
+#define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
+#define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
+#define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
+#define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
+#define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
+#define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
+#define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
+#define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
+
+#define	CLKCTRL_HBUS_BUSY			(1 << 29)
+#define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 28)
+#define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 27)
+#define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
+#define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
+#define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
+#define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
+#define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
+#define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
+#define	CLKCTRL_HBUS_AUTO_SLOW_MODE		(1 << 20)
+#define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
+#define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
+#define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
+#define	CLKCTRL_HBUS_DIV_MASK			0x1f
+#define	CLKCTRL_HBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XBUS_BUSY			(1 << 31)
+#define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_XBUS_DIV_MASK			0x3ff
+#define	CLKCTRL_XBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
+#define	CLKCTRL_XTAL_FILT_CLK24M_GATE		(1 << 30)
+#define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
+#define	CLKCTRL_XTAL_DRI_CLK24M_GATE		(1 << 28)
+#define	CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE		(1 << 27)
+#define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
+#define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
+#define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
+
+#define	CLKCTRL_PIX_CLKGATE			(1 << 31)
+#define	CLKCTRL_PIX_BUSY			(1 << 29)
+#define	CLKCTRL_PIX_DIV_FRAC_EN			(1 << 12)
+#define	CLKCTRL_PIX_DIV_MASK			0xfff
+#define	CLKCTRL_PIX_DIV_OFFSET			0
+
+#define	CLKCTRL_SSP_CLKGATE			(1 << 31)
+#define	CLKCTRL_SSP_BUSY			(1 << 29)
+#define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
+#define	CLKCTRL_SSP_DIV_MASK			0x1ff
+#define	CLKCTRL_SSP_DIV_OFFSET			0
+
+#define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_GPMI_BUSY			(1 << 29)
+#define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_GPMI_DIV_MASK			0x3ff
+#define	CLKCTRL_GPMI_DIV_OFFSET			0
+
+#define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
+
+#define	CLKCTRL_EMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
+#define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
+#define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
+#define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
+#define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
+#define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
+#define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
+#define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
+#define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
+#define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
+
+#define	CLKCTRL_IR_CLKGATE			(1 << 31)
+#define	CLKCTRL_IR_AUTO_DIV			(1 << 29)
+#define	CLKCTRL_IR_IR_BUSY			(1 << 28)
+#define	CLKCTRL_IR_IROV_BUSY			(1 << 27)
+#define	CLKCTRL_IR_IROV_DIV_MASK		(0x1ff << 16)
+#define	CLKCTRL_IR_IROV_DIV_OFFSET		16
+#define	CLKCTRL_IR_IR_DIV_MASK			0x3ff
+#define	CLKCTRL_IR_IR_DIV_OFFSET		0
+
+#define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
+#define	CLKCTRL_SAIF0_BUSY			(1 << 29)
+#define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
+#define	CLKCTRL_SAIF0_DIV_MASK			0xffff
+#define	CLKCTRL_SAIF0_DIV_OFFSET		0
+
+#define	CLKCTRL_TV_CLK_TV108M_GATE		(1 << 31)
+#define	CLKCTRL_TV_CLK_TV_GATE			(1 << 30)
+
+#define	CLKCTRL_ETM_CLKGATE			(1 << 31)
+#define	CLKCTRL_ETM_BUSY			(1 << 29)
+#define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 6)
+#define	CLKCTRL_ETM_DIV_MASK			0x3f
+#define	CLKCTRL_ETM_DIV_OFFSET			0
+
+#define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
+#define	CLKCTRL_FRAC_STABLE			(1 << 6)
+#define	CLKCTRL_FRAC_FRAC_MASK			0x3f
+#define	CLKCTRL_FRAC_FRAC_OFFSET		0
+#define	CLKCTRL_FRAC0_CPU			0
+#define	CLKCTRL_FRAC0_EMI			1
+#define	CLKCTRL_FRAC0_PIX			2
+#define	CLKCTRL_FRAC0_IO0			3
+#define	CLKCTRL_FRAC1_VID			3
+
+#define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
+#define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 7)
+#define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 6)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP0		(1 << 5)
+#define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 4)
+#define	CLKCTRL_CLKSEQ_BYPASS_IR		(1 << 3)
+#define	CLKCTRL_CLKSEQ_BYPASS_PIX		(1 << 1)
+#define	CLKCTRL_CLKSEQ_BYPASS_SAIF		(1 << 0)
+
+#define	CLKCTRL_RESET_CHIP			(1 << 1)
+#define	CLKCTRL_RESET_DIG			(1 << 0)
+
+#define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
+#define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
+
+#define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
+#define	CLKCTRL_VERSION_MAJOR_OFFSET		24
+#define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
+#define	CLKCTRL_VERSION_MINOR_OFFSET		16
+#define	CLKCTRL_VERSION_STEP_MASK		0xffff
+#define	CLKCTRL_VERSION_STEP_OFFSET		0
+
+#endif /* __MX23_REGS_CLKCTRL_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
new file mode 100644
index 000000000..1490ffd52
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
@@ -0,0 +1,283 @@
+/*
+ * Freescale i.MX28 CLKCTRL Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_CLKCTRL_H__
+#define __MX28_REGS_CLKCTRL_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_clkctrl_regs {
+	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
+	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
+	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
+	mxs_reg_32(hw_clkctrl_pll1ctrl0)	/* 0x20 */
+	uint32_t	hw_clkctrl_pll1ctrl1;	/* 0x30 */
+	uint32_t	reserved_pll1ctrl1[3];	/* 0x34-0x3c */
+	mxs_reg_32(hw_clkctrl_pll2ctrl0)	/* 0x40 */
+	mxs_reg_32(hw_clkctrl_cpu)		/* 0x50 */
+	mxs_reg_32(hw_clkctrl_hbus)		/* 0x60 */
+	mxs_reg_32(hw_clkctrl_xbus)		/* 0x70 */
+	mxs_reg_32(hw_clkctrl_xtal)		/* 0x80 */
+	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x90 */
+	mxs_reg_32(hw_clkctrl_ssp1)		/* 0xa0 */
+	mxs_reg_32(hw_clkctrl_ssp2)		/* 0xb0 */
+	mxs_reg_32(hw_clkctrl_ssp3)		/* 0xc0 */
+	mxs_reg_32(hw_clkctrl_gpmi)		/* 0xd0 */
+	mxs_reg_32(hw_clkctrl_spdif)		/* 0xe0 */
+	mxs_reg_32(hw_clkctrl_emi)		/* 0xf0 */
+	mxs_reg_32(hw_clkctrl_saif0)		/* 0x100 */
+	mxs_reg_32(hw_clkctrl_saif1)		/* 0x110 */
+	mxs_reg_32(hw_clkctrl_lcdif)		/* 0x120 */
+	mxs_reg_32(hw_clkctrl_etm)		/* 0x130 */
+	mxs_reg_32(hw_clkctrl_enet)		/* 0x140 */
+	mxs_reg_32(hw_clkctrl_hsadc)		/* 0x150 */
+	mxs_reg_32(hw_clkctrl_flexcan)		/* 0x160 */
+
+	uint32_t	reserved[16];
+
+	mxs_reg_8(hw_clkctrl_frac0)		/* 0x1b0 */
+	mxs_reg_8(hw_clkctrl_frac1)		/* 0x1c0 */
+	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x1d0 */
+	mxs_reg_32(hw_clkctrl_reset)		/* 0x1e0 */
+	mxs_reg_32(hw_clkctrl_status)		/* 0x1f0 */
+	mxs_reg_32(hw_clkctrl_version)		/* 0x200 */
+};
+#endif
+
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
+#define	CLKCTRL_PLL0CTRL0_POWER			(1 << 17)
+
+#define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
+#define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
+
+#define	CLKCTRL_PLL1CTRL0_CLKGATEEMI		(1 << 31)
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_MASK		(0x3 << 28)
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET	28
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_MASK		(0x3 << 24)
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET		24
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_MASK		(0x3 << 20)
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET	20
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER		(0x1 << 20)
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
+#define	CLKCTRL_PLL1CTRL0_EN_USB_CLKS		(1 << 18)
+#define	CLKCTRL_PLL1CTRL0_POWER			(1 << 17)
+
+#define	CLKCTRL_PLL1CTRL1_LOCK			(1 << 31)
+#define	CLKCTRL_PLL1CTRL1_FORCE_LOCK		(1 << 30)
+#define	CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK	0xffff
+#define	CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET	0
+
+#define	CLKCTRL_PLL2CTRL0_CLKGATE		(1 << 31)
+#define	CLKCTRL_PLL2CTRL0_LFR_SEL_MASK		(0x3 << 28)
+#define	CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET	28
+#define	CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B	(1 << 26)
+#define	CLKCTRL_PLL2CTRL0_CP_SEL_MASK		(0x3 << 24)
+#define	CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET		24
+#define	CLKCTRL_PLL2CTRL0_POWER			(1 << 23)
+
+#define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
+#define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
+#define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
+#define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
+#define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
+#define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
+#define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
+#define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
+
+#define	CLKCTRL_HBUS_ASM_BUSY			(1 << 31)
+#define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 30)
+#define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 29)
+#define	CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE	(1 << 27)
+#define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
+#define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
+#define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
+#define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
+#define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
+#define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
+#define	CLKCTRL_HBUS_ASM_ENABLE			(1 << 20)
+#define	CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE	(1 << 19)
+#define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
+#define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
+#define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
+#define	CLKCTRL_HBUS_DIV_MASK			0x1f
+#define	CLKCTRL_HBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XBUS_BUSY			(1 << 31)
+#define	CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE	(1 << 11)
+#define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_XBUS_DIV_MASK			0x3ff
+#define	CLKCTRL_XBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
+#define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
+#define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
+#define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
+#define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
+
+#define	CLKCTRL_SSP_CLKGATE			(1 << 31)
+#define	CLKCTRL_SSP_BUSY			(1 << 29)
+#define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
+#define	CLKCTRL_SSP_DIV_MASK			0x1ff
+#define	CLKCTRL_SSP_DIV_OFFSET			0
+
+#define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_GPMI_BUSY			(1 << 29)
+#define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_GPMI_DIV_MASK			0x3ff
+#define	CLKCTRL_GPMI_DIV_OFFSET			0
+
+#define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
+
+#define	CLKCTRL_EMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
+#define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
+#define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
+#define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
+#define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
+#define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
+#define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
+#define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
+#define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
+#define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
+
+#define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
+#define	CLKCTRL_SAIF0_BUSY			(1 << 29)
+#define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
+#define	CLKCTRL_SAIF0_DIV_MASK			0xffff
+#define	CLKCTRL_SAIF0_DIV_OFFSET		0
+
+#define	CLKCTRL_SAIF1_CLKGATE			(1 << 31)
+#define	CLKCTRL_SAIF1_BUSY			(1 << 29)
+#define	CLKCTRL_SAIF1_DIV_FRAC_EN		(1 << 16)
+#define	CLKCTRL_SAIF1_DIV_MASK			0xffff
+#define	CLKCTRL_SAIF1_DIV_OFFSET		0
+
+#define	CLKCTRL_DIS_LCDIF_CLKGATE		(1 << 31)
+#define	CLKCTRL_DIS_LCDIF_BUSY			(1 << 29)
+#define	CLKCTRL_DIS_LCDIF_DIV_FRAC_EN		(1 << 13)
+#define	CLKCTRL_DIS_LCDIF_DIV_MASK		0x1fff
+#define	CLKCTRL_DIS_LCDIF_DIV_OFFSET		0
+
+#define	CLKCTRL_ETM_CLKGATE			(1 << 31)
+#define	CLKCTRL_ETM_BUSY			(1 << 29)
+#define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 7)
+#define	CLKCTRL_ETM_DIV_MASK			0x7f
+#define	CLKCTRL_ETM_DIV_OFFSET			0
+
+#define	CLKCTRL_ENET_SLEEP			(1 << 31)
+#define	CLKCTRL_ENET_DISABLE			(1 << 30)
+#define	CLKCTRL_ENET_STATUS			(1 << 29)
+#define	CLKCTRL_ENET_BUSY_TIME			(1 << 27)
+#define	CLKCTRL_ENET_DIV_TIME_MASK		(0x3f << 21)
+#define	CLKCTRL_ENET_DIV_TIME_OFFSET		21
+#define	CLKCTRL_ENET_TIME_SEL_MASK		(0x3 << 19)
+#define	CLKCTRL_ENET_TIME_SEL_OFFSET		19
+#define	CLKCTRL_ENET_TIME_SEL_XTAL		(0x0 << 19)
+#define	CLKCTRL_ENET_TIME_SEL_PLL		(0x1 << 19)
+#define	CLKCTRL_ENET_TIME_SEL_RMII_CLK		(0x2 << 19)
+#define	CLKCTRL_ENET_TIME_SEL_UNDEFINED		(0x3 << 19)
+#define	CLKCTRL_ENET_CLK_OUT_EN			(1 << 18)
+#define	CLKCTRL_ENET_RESET_BY_SW_CHIP		(1 << 17)
+#define	CLKCTRL_ENET_RESET_BY_SW		(1 << 16)
+
+#define	CLKCTRL_HSADC_RESETB			(1 << 30)
+#define	CLKCTRL_HSADC_FREQDIV_MASK		(0x3 << 28)
+#define	CLKCTRL_HSADC_FREQDIV_OFFSET		28
+
+#define	CLKCTRL_FLEXCAN_STOP_CAN0		(1 << 30)
+#define	CLKCTRL_FLEXCAN_CAN0_STATUS		(1 << 29)
+#define	CLKCTRL_FLEXCAN_STOP_CAN1		(1 << 28)
+#define	CLKCTRL_FLEXCAN_CAN1_STATUS		(1 << 27)
+
+#define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
+#define	CLKCTRL_FRAC_STABLE			(1 << 6)
+#define	CLKCTRL_FRAC_FRAC_MASK			0x3f
+#define	CLKCTRL_FRAC_FRAC_OFFSET		0
+#define	CLKCTRL_FRAC0_CPU			0
+#define	CLKCTRL_FRAC0_EMI			1
+#define	CLKCTRL_FRAC0_IO1			2
+#define	CLKCTRL_FRAC0_IO0			3
+#define	CLKCTRL_FRAC1_PIX			0
+#define	CLKCTRL_FRAC1_HSADC			1
+#define	CLKCTRL_FRAC1_GPMI			2
+
+#define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 18)
+#define	CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF		(1 << 14)
+#define	CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS	(0x1 << 14)
+#define	CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD	(0x0 << 14)
+#define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
+#define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 7)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP3		(1 << 6)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP2		(1 << 5)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP1		(1 << 4)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP0		(1 << 3)
+#define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 2)
+#define	CLKCTRL_CLKSEQ_BYPASS_SAIF1		(1 << 1)
+#define	CLKCTRL_CLKSEQ_BYPASS_SAIF0		(1 << 0)
+
+#define	CLKCTRL_RESET_WDOG_POR_DISABLE		(1 << 5)
+#define	CLKCTRL_RESET_EXTERNAL_RESET_ENABLE	(1 << 4)
+#define	CLKCTRL_RESET_THERMAL_RESET_ENABLE	(1 << 3)
+#define	CLKCTRL_RESET_THERMAL_RESET_DEFAULT	(1 << 2)
+#define	CLKCTRL_RESET_CHIP			(1 << 1)
+#define	CLKCTRL_RESET_DIG			(1 << 0)
+
+#define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
+#define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
+
+#define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
+#define	CLKCTRL_VERSION_MAJOR_OFFSET		24
+#define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
+#define	CLKCTRL_VERSION_MINOR_OFFSET		16
+#define	CLKCTRL_VERSION_STEP_MASK		0xffff
+#define	CLKCTRL_VERSION_STEP_OFFSET		0
+
+#endif /* __MX28_REGS_CLKCTRL_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-digctl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-digctl.h
new file mode 100644
index 000000000..860be9e28
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-digctl.h
@@ -0,0 +1,147 @@
+/*
+ * Freescale i.MX28 DIGCTL Register Definitions
+ *
+ * Copyright (C) 2012 Robert Delien <robert@delien.nl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_DIGCTL_H__
+#define __MX28_REGS_DIGCTL_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_digctl_regs {
+	mxs_reg_32(hw_digctl_ctrl)				/* 0x000 */
+	mxs_reg_32(hw_digctl_status)				/* 0x010 */
+	mxs_reg_32(hw_digctl_hclkcount)			/* 0x020 */
+	mxs_reg_32(hw_digctl_ramctrl)				/* 0x030 */
+	mxs_reg_32(hw_digctl_emi_status)			/* 0x040 */
+	mxs_reg_32(hw_digctl_read_margin)			/* 0x050 */
+	uint32_t	hw_digctl_writeonce;			/* 0x060 */
+	uint32_t	reserved_writeonce[3];
+	mxs_reg_32(hw_digctl_bist_ctl)				/* 0x070 */
+	mxs_reg_32(hw_digctl_bist_status)			/* 0x080 */
+	uint32_t	hw_digctl_entropy;			/* 0x090 */
+	uint32_t	reserved_entropy[3];
+	uint32_t	hw_digctl_entropy_latched;		/* 0x0a0 */
+	uint32_t	reserved_entropy_latched[3];
+
+	uint32_t	reserved1[4];
+
+	mxs_reg_32(hw_digctl_microseconds)			/* 0x0c0 */
+	uint32_t	hw_digctl_dbgrd;			/* 0x0d0 */
+	uint32_t	reserved_hw_digctl_dbgrd[3];
+	uint32_t	hw_digctl_dbg;				/* 0x0e0 */
+	uint32_t	reserved_hw_digctl_dbg[3];
+
+	uint32_t	reserved2[4];
+
+	mxs_reg_32(hw_digctl_usb_loopback)			/* 0x100 */
+	mxs_reg_32(hw_digctl_ocram_status0)			/* 0x110 */
+	mxs_reg_32(hw_digctl_ocram_status1)			/* 0x120 */
+	mxs_reg_32(hw_digctl_ocram_status2)			/* 0x130 */
+	mxs_reg_32(hw_digctl_ocram_status3)			/* 0x140 */
+	mxs_reg_32(hw_digctl_ocram_status4)			/* 0x150 */
+	mxs_reg_32(hw_digctl_ocram_status5)			/* 0x160 */
+	mxs_reg_32(hw_digctl_ocram_status6)			/* 0x170 */
+	mxs_reg_32(hw_digctl_ocram_status7)			/* 0x180 */
+	mxs_reg_32(hw_digctl_ocram_status8)			/* 0x190 */
+	mxs_reg_32(hw_digctl_ocram_status9)			/* 0x1a0 */
+	mxs_reg_32(hw_digctl_ocram_status10)			/* 0x1b0 */
+	mxs_reg_32(hw_digctl_ocram_status11)			/* 0x1c0 */
+	mxs_reg_32(hw_digctl_ocram_status12)			/* 0x1d0 */
+	mxs_reg_32(hw_digctl_ocram_status13)			/* 0x1e0 */
+
+	uint32_t	reserved3[36];
+
+	uint32_t	hw_digctl_scratch0;			/* 0x280 */
+	uint32_t	reserved_hw_digctl_scratch0[3];
+	uint32_t	hw_digctl_scratch1;			/* 0x290 */
+	uint32_t	reserved_hw_digctl_scratch1[3];
+	uint32_t	hw_digctl_armcache;			/* 0x2a0 */
+	uint32_t	reserved_hw_digctl_armcache[3];
+	mxs_reg_32(hw_digctl_debug_trap)			/* 0x2b0 */
+	uint32_t	hw_digctl_debug_trap_l0_addr_low;	/* 0x2c0 */
+	uint32_t	reserved_hw_digctl_debug_trap_l0_addr_low[3];
+	uint32_t	hw_digctl_debug_trap_l0_addr_high;	/* 0x2d0 */
+	uint32_t	reserved_hw_digctl_debug_trap_l0_addr_high[3];
+	uint32_t	hw_digctl_debug_trap_l3_addr_low;	/* 0x2e0 */
+	uint32_t	reserved_hw_digctl_debug_trap_l3_addr_low[3];
+	uint32_t	hw_digctl_debug_trap_l3_addr_high;	/* 0x2f0 */
+	uint32_t	reserved_hw_digctl_debug_trap_l3_addr_high[3];
+	uint32_t	hw_digctl_fsl;				/* 0x300 */
+	uint32_t	reserved_hw_digctl_fsl[3];
+	uint32_t	hw_digctl_chipid;			/* 0x310 */
+	uint32_t	reserved_hw_digctl_chipid[3];
+
+	uint32_t	reserved4[4];
+
+	uint32_t	hw_digctl_ahb_stats_select;		/* 0x330 */
+	uint32_t	reserved_hw_digctl_ahb_stats_select[3];
+
+	uint32_t	reserved5[12];
+
+	uint32_t	hw_digctl_l1_ahb_active_cycles;		/* 0x370 */
+	uint32_t	reserved_hw_digctl_l1_ahb_active_cycles[3];
+	uint32_t	hw_digctl_l1_ahb_data_stalled;		/* 0x380 */
+	uint32_t	reserved_hw_digctl_l1_ahb_data_stalled[3];
+	uint32_t	hw_digctl_l1_ahb_data_cycles;		/* 0x390 */
+	uint32_t	reserved_hw_digctl_l1_ahb_data_cycles[3];
+	uint32_t	hw_digctl_l2_ahb_active_cycles;		/* 0x3a0 */
+	uint32_t	reserved_hw_digctl_l2_ahb_active_cycles[3];
+	uint32_t	hw_digctl_l2_ahb_data_stalled;		/* 0x3b0 */
+	uint32_t	reserved_hw_digctl_l2_ahb_data_stalled[3];
+	uint32_t	hw_digctl_l2_ahb_data_cycles;		/* 0x3c0 */
+	uint32_t	reserved_hw_digctl_l2_ahb_data_cycles[3];
+	uint32_t	hw_digctl_l3_ahb_active_cycles;		/* 0x3d0 */
+	uint32_t	reserved_hw_digctl_l3_ahb_active_cycles[3];
+	uint32_t	hw_digctl_l3_ahb_data_stalled;		/* 0x3e0 */
+	uint32_t	reserved_hw_digctl_l3_ahb_data_stalled[3];
+	uint32_t	hw_digctl_l3_ahb_data_cycles;		/* 0x3f0 */
+	uint32_t	reserved_hw_digctl_l3_ahb_data_cycles[3];
+
+	uint32_t	reserved6[64];
+
+	uint32_t	hw_digctl_mpte0_loc;			/* 0x500 */
+	uint32_t	reserved_hw_digctl_mpte0_loc[3];
+	uint32_t	hw_digctl_mpte1_loc;			/* 0x510 */
+	uint32_t	reserved_hw_digctl_mpte1_loc[3];
+	uint32_t	hw_digctl_mpte2_loc;			/* 0x520 */
+	uint32_t	reserved_hw_digctl_mpte2_loc[3];
+	uint32_t	hw_digctl_mpte3_loc;			/* 0x530 */
+	uint32_t	reserved_hw_digctl_mpte3_loc[3];
+	uint32_t	hw_digctl_mpte4_loc;			/* 0x540 */
+	uint32_t	reserved_hw_digctl_mpte4_loc[3];
+	uint32_t	hw_digctl_mpte5_loc;			/* 0x550 */
+	uint32_t	reserved_hw_digctl_mpte5_loc[3];
+	uint32_t	hw_digctl_mpte6_loc;			/* 0x560 */
+	uint32_t	reserved_hw_digctl_mpte6_loc[3];
+	uint32_t	hw_digctl_mpte7_loc;			/* 0x570 */
+	uint32_t	reserved_hw_digctl_mpte7_loc[3];
+	uint32_t	hw_digctl_mpte8_loc;			/* 0x580 */
+	uint32_t	reserved_hw_digctl_mpte8_loc[3];
+	uint32_t	hw_digctl_mpte9_loc;			/* 0x590 */
+	uint32_t	reserved_hw_digctl_mpte9_loc[3];
+	uint32_t	hw_digctl_mpte10_loc;			/* 0x5a0 */
+	uint32_t	reserved_hw_digctl_mpte10_loc[3];
+	uint32_t	hw_digctl_mpte11_loc;			/* 0x5b0 */
+	uint32_t	reserved_hw_digctl_mpte11_loc[3];
+	uint32_t	hw_digctl_mpte12_loc;			/* 0x5c0 */
+	uint32_t	reserved_hw_digctl_mpte12_loc[3];
+	uint32_t	hw_digctl_mpte13_loc;			/* 0x5d0 */
+	uint32_t	reserved_hw_digctl_mpte13_loc[3];
+	uint32_t	hw_digctl_mpte14_loc;			/* 0x5e0 */
+	uint32_t	reserved_hw_digctl_mpte14_loc[3];
+	uint32_t	hw_digctl_mpte15_loc;			/* 0x5f0 */
+	uint32_t	reserved_hw_digctl_mpte15_loc[3];
+};
+#endif
+
+/* Product code identification */
+#define HW_DIGCTL_CHIPID_MASK	(0xffff << 16)
+#define HW_DIGCTL_CHIPID_MX23	(0x3780 << 16)
+#define HW_DIGCTL_CHIPID_MX28	(0x2800 << 16)
+
+#endif /* __MX28_REGS_DIGCTL_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-i2c.h
new file mode 100644
index 000000000..a58303efb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-i2c.h
@@ -0,0 +1,194 @@
+/*
+ * Freescale i.MX28 I2C Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_I2C_H__
+#define __MX28_REGS_I2C_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_i2c_regs {
+	mxs_reg_32(hw_i2c_ctrl0)
+	mxs_reg_32(hw_i2c_timing0)
+	mxs_reg_32(hw_i2c_timing1)
+	mxs_reg_32(hw_i2c_timing2)
+	mxs_reg_32(hw_i2c_ctrl1)
+	mxs_reg_32(hw_i2c_stat)
+	mxs_reg_32(hw_i2c_queuectrl)
+	mxs_reg_32(hw_i2c_queuestat)
+	mxs_reg_32(hw_i2c_queuecmd)
+	mxs_reg_32(hw_i2c_queuedata)
+	mxs_reg_32(hw_i2c_data)
+	mxs_reg_32(hw_i2c_debug0)
+	mxs_reg_32(hw_i2c_debug1)
+	mxs_reg_32(hw_i2c_version)
+};
+#endif
+
+#define	I2C_CTRL_SFTRST				(1 << 31)
+#define	I2C_CTRL_CLKGATE			(1 << 30)
+#define	I2C_CTRL_RUN				(1 << 29)
+#define	I2C_CTRL_PREACK				(1 << 27)
+#define	I2C_CTRL_ACKNOWLEDGE			(1 << 26)
+#define	I2C_CTRL_SEND_NAK_ON_LAST		(1 << 25)
+#define	I2C_CTRL_MULTI_MASTER			(1 << 23)
+#define	I2C_CTRL_CLOCK_HELD			(1 << 22)
+#define	I2C_CTRL_RETAIN_CLOCK			(1 << 21)
+#define	I2C_CTRL_POST_SEND_STOP			(1 << 20)
+#define	I2C_CTRL_PRE_SEND_START			(1 << 19)
+#define	I2C_CTRL_SLAVE_ADDRESS_ENABLE		(1 << 18)
+#define	I2C_CTRL_MASTER_MODE			(1 << 17)
+#define	I2C_CTRL_DIRECTION			(1 << 16)
+#define	I2C_CTRL_XFER_COUNT_MASK		0xffff
+#define	I2C_CTRL_XFER_COUNT_OFFSET		0
+
+#define	I2C_TIMING0_HIGH_COUNT_MASK		(0x3ff << 16)
+#define	I2C_TIMING0_HIGH_COUNT_OFFSET		16
+#define	I2C_TIMING0_RCV_COUNT_MASK		0x3ff
+#define	I2C_TIMING0_RCV_COUNT_OFFSET		0
+
+#define	I2C_TIMING1_LOW_COUNT_MASK		(0x3ff << 16)
+#define	I2C_TIMING1_LOW_COUNT_OFFSET		16
+#define	I2C_TIMING1_XMIT_COUNT_MASK		0x3ff
+#define	I2C_TIMING1_XMIT_COUNT_OFFSET		0
+
+#define	I2C_TIMING2_BUS_FREE_MASK		(0x3ff << 16)
+#define	I2C_TIMING2_BUS_FREE_OFFSET		16
+#define	I2C_TIMING2_LEADIN_COUNT_MASK		0x3ff
+#define	I2C_TIMING2_LEADIN_COUNT_OFFSET		0
+
+#define	I2C_CTRL1_RD_QUEUE_IRQ			(1 << 30)
+#define	I2C_CTRL1_WR_QUEUE_IRQ			(1 << 29)
+#define	I2C_CTRL1_CLR_GOT_A_NAK			(1 << 28)
+#define	I2C_CTRL1_ACK_MODE			(1 << 27)
+#define	I2C_CTRL1_FORCE_DATA_IDLE		(1 << 26)
+#define	I2C_CTRL1_FORCE_CLK_IDLE		(1 << 25)
+#define	I2C_CTRL1_BCAST_SLAVE_EN		(1 << 24)
+#define	I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK	(0xff << 16)
+#define	I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET	16
+#define	I2C_CTRL1_BUS_FREE_IRQ_EN		(1 << 15)
+#define	I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN	(1 << 14)
+#define	I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN		(1 << 13)
+#define	I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN	(1 << 12)
+#define	I2C_CTRL1_EARLY_TERM_IRQ_EN		(1 << 11)
+#define	I2C_CTRL1_MASTER_LOSS_IRQ_EN		(1 << 10)
+#define	I2C_CTRL1_SLAVE_STOP_IRQ_EN		(1 << 9)
+#define	I2C_CTRL1_SLAVE_IRQ_EN			(1 << 8)
+#define	I2C_CTRL1_BUS_FREE_IRQ			(1 << 7)
+#define	I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ		(1 << 6)
+#define	I2C_CTRL1_NO_SLAVE_ACK_IRQ		(1 << 5)
+#define	I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ	(1 << 4)
+#define	I2C_CTRL1_EARLY_TERM_IRQ		(1 << 3)
+#define	I2C_CTRL1_MASTER_LOSS_IRQ		(1 << 2)
+#define	I2C_CTRL1_SLAVE_STOP_IRQ		(1 << 1)
+#define	I2C_CTRL1_SLAVE_IRQ			(1 << 0)
+
+#define	I2C_STAT_MASTER_PRESENT			(1 << 31)
+#define	I2C_STAT_SLAVE_PRESENT			(1 << 30)
+#define	I2C_STAT_ANY_ENABLED_IRQ		(1 << 29)
+#define	I2C_STAT_GOT_A_NAK			(1 << 28)
+#define	I2C_STAT_RCVD_SLAVE_ADDR_MASK		(0xff << 16)
+#define	I2C_STAT_RCVD_SLAVE_ADDR_OFFSET		16
+#define	I2C_STAT_SLAVE_ADDR_EQ_ZERO		(1 << 15)
+#define	I2C_STAT_SLAVE_FOUND			(1 << 14)
+#define	I2C_STAT_SLAVE_SEARCHING		(1 << 13)
+#define	I2C_STAT_DATA_ENGING_DMA_WAIT		(1 << 12)
+#define	I2C_STAT_BUS_BUSY			(1 << 11)
+#define	I2C_STAT_CLK_GEN_BUSY			(1 << 10)
+#define	I2C_STAT_DATA_ENGINE_BUSY		(1 << 9)
+#define	I2C_STAT_SLAVE_BUSY			(1 << 8)
+#define	I2C_STAT_BUS_FREE_IRQ_SUMMARY		(1 << 7)
+#define	I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY	(1 << 6)
+#define	I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY	(1 << 5)
+#define	I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY	(1 << 4)
+#define	I2C_STAT_EARLY_TERM_IRQ_SUMMARY		(1 << 3)
+#define	I2C_STAT_MASTER_LOSS_IRQ_SUMMARY	(1 << 2)
+#define	I2C_STAT_SLAVE_STOP_IRQ_SUMMARY		(1 << 1)
+#define	I2C_STAT_SLAVE_IRQ_SUMMARY		(1 << 0)
+
+#define	I2C_QUEUECTRL_RD_THRESH_MASK		(0x1f << 16)
+#define	I2C_QUEUECTRL_RD_THRESH_OFFSET		16
+#define	I2C_QUEUECTRL_WR_THRESH_MASK		(0x1f << 8)
+#define	I2C_QUEUECTRL_WR_THRESH_OFFSET		8
+#define	I2C_QUEUECTRL_QUEUE_RUN			(1 << 5)
+#define	I2C_QUEUECTRL_RD_CLEAR			(1 << 4)
+#define	I2C_QUEUECTRL_WR_CLEAR			(1 << 3)
+#define	I2C_QUEUECTRL_PIO_QUEUE_MODE		(1 << 2)
+#define	I2C_QUEUECTRL_RD_QUEUE_IRQ_EN		(1 << 1)
+#define	I2C_QUEUECTRL_WR_QUEUE_IRQ_EN		(1 << 0)
+
+#define	I2C_QUEUESTAT_RD_QUEUE_FULL		(1 << 14)
+#define	I2C_QUEUESTAT_RD_QUEUE_EMPTY		(1 << 13)
+#define	I2C_QUEUESTAT_RD_QUEUE_CNT_MASK		(0x1f << 8)
+#define	I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET	8
+#define	I2C_QUEUESTAT_WR_QUEUE_FULL		(1 << 6)
+#define	I2C_QUEUESTAT_WR_QUEUE_EMPTY		(1 << 5)
+#define	I2C_QUEUESTAT_WR_QUEUE_CNT_MASK		0x1f
+#define	I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET	0
+
+#define	I2C_QUEUECMD_PREACK			(1 << 27)
+#define	I2C_QUEUECMD_ACKNOWLEDGE		(1 << 26)
+#define	I2C_QUEUECMD_SEND_NAK_ON_LAST		(1 << 25)
+#define	I2C_QUEUECMD_MULTI_MASTER		(1 << 23)
+#define	I2C_QUEUECMD_CLOCK_HELD			(1 << 22)
+#define	I2C_QUEUECMD_RETAIN_CLOCK		(1 << 21)
+#define	I2C_QUEUECMD_POST_SEND_STOP		(1 << 20)
+#define	I2C_QUEUECMD_PRE_SEND_START		(1 << 19)
+#define	I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE	(1 << 18)
+#define	I2C_QUEUECMD_MASTER_MODE		(1 << 17)
+#define	I2C_QUEUECMD_DIRECTION			(1 << 16)
+#define	I2C_QUEUECMD_XFER_COUNT_MASK		0xffff
+#define	I2C_QUEUECMD_XFER_COUNT_OFFSET		0
+
+#define	I2C_QUEUEDATA_DATA_MASK			0xffffffff
+#define	I2C_QUEUEDATA_DATA_OFFSET		0
+
+#define	I2C_DATA_DATA_MASK			0xffffffff
+#define	I2C_DATA_DATA_OFFSET			0
+
+#define	I2C_DEBUG0_DMAREQ			(1 << 31)
+#define	I2C_DEBUG0_DMAENDCMD			(1 << 30)
+#define	I2C_DEBUG0_DMAKICK			(1 << 29)
+#define	I2C_DEBUG0_DMATERMINATE			(1 << 28)
+#define	I2C_DEBUG0_STATE_VALUE_MASK		(0x3 << 26)
+#define	I2C_DEBUG0_STATE_VALUE_OFFSET		26
+#define	I2C_DEBUG0_DMA_STATE_MASK		(0x3ff << 16)
+#define	I2C_DEBUG0_DMA_STATE_OFFSET		16
+#define	I2C_DEBUG0_START_TOGGLE			(1 << 15)
+#define	I2C_DEBUG0_STOP_TOGGLE			(1 << 14)
+#define	I2C_DEBUG0_GRAB_TOGGLE			(1 << 13)
+#define	I2C_DEBUG0_CHANGE_TOGGLE		(1 << 12)
+#define	I2C_DEBUG0_STATE_LATCH			(1 << 11)
+#define	I2C_DEBUG0_SLAVE_HOLD_CLK		(1 << 10)
+#define	I2C_DEBUG0_STATE_STATE_MASK		0x3ff
+#define	I2C_DEBUG0_STATE_STATE_OFFSET		0
+
+#define	I2C_DEBUG1_I2C_CLK_IN			(1 << 31)
+#define	I2C_DEBUG1_I2C_DATA_IN			(1 << 30)
+#define	I2C_DEBUG1_DMA_BYTE_ENABLES_MASK	(0xf << 24)
+#define	I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET	24
+#define	I2C_DEBUG1_CLK_GEN_STATE_MASK		(0xff << 16)
+#define	I2C_DEBUG1_CLK_GEN_STATE_OFFSET		16
+#define	I2C_DEBUG1_LST_MODE_MASK		(0x3 << 9)
+#define	I2C_DEBUG1_LST_MODE_OFFSET		9
+#define	I2C_DEBUG1_LOCAL_SLAVE_TEST		(1 << 8)
+#define	I2C_DEBUG1_FORCE_CLK_ON			(1 << 4)
+#define	I2C_DEBUG1_FORCE_ABR_LOSS		(1 << 3)
+#define	I2C_DEBUG1_FORCE_RCV_ACK		(1 << 2)
+#define	I2C_DEBUG1_FORCE_I2C_DATA_OE		(1 << 1)
+#define	I2C_DEBUG1_FORCE_I2C_CLK_OE		(1 << 0)
+
+#define	I2C_VERSION_MAJOR_MASK			(0xff << 24)
+#define	I2C_VERSION_MAJOR_OFFSET		24
+#define	I2C_VERSION_MINOR_MASK			(0xff << 16)
+#define	I2C_VERSION_MINOR_OFFSET		16
+#define	I2C_VERSION_STEP_MASK			0xffff
+#define	I2C_VERSION_STEP_OFFSET			0
+
+#endif	/* __MX28_REGS_I2C_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lcdif.h
new file mode 100644
index 000000000..8915d84d0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lcdif.h
@@ -0,0 +1,217 @@
+/*
+ * Freescale i.MX28 LCDIF Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_LCDIF_H__
+#define __MX28_REGS_LCDIF_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_lcdif_regs {
+	mxs_reg_32(hw_lcdif_ctrl)		/* 0x00 */
+	mxs_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
+#if defined(CONFIG_MX28)
+	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
+#endif
+	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
+	mxs_reg_32(hw_lcdif_cur_buf)		/* 0x30/0x40 */
+	mxs_reg_32(hw_lcdif_next_buf)		/* 0x40/0x50 */
+
+#if defined(CONFIG_MX23)
+	uint32_t	reserved1[4];
+#endif
+
+	mxs_reg_32(hw_lcdif_timing)		/* 0x60 */
+	mxs_reg_32(hw_lcdif_vdctrl0)		/* 0x70 */
+	mxs_reg_32(hw_lcdif_vdctrl1)		/* 0x80 */
+	mxs_reg_32(hw_lcdif_vdctrl2)		/* 0x90 */
+	mxs_reg_32(hw_lcdif_vdctrl3)		/* 0xa0 */
+	mxs_reg_32(hw_lcdif_vdctrl4)		/* 0xb0 */
+	mxs_reg_32(hw_lcdif_dvictrl0)		/* 0xc0 */
+	mxs_reg_32(hw_lcdif_dvictrl1)		/* 0xd0 */
+	mxs_reg_32(hw_lcdif_dvictrl2)		/* 0xe0 */
+	mxs_reg_32(hw_lcdif_dvictrl3)		/* 0xf0 */
+	mxs_reg_32(hw_lcdif_dvictrl4)		/* 0x100 */
+	mxs_reg_32(hw_lcdif_csc_coeffctrl0)	/* 0x110 */
+	mxs_reg_32(hw_lcdif_csc_coeffctrl1)	/* 0x120 */
+	mxs_reg_32(hw_lcdif_csc_coeffctrl2)	/* 0x130 */
+	mxs_reg_32(hw_lcdif_csc_coeffctrl3)	/* 0x140 */
+	mxs_reg_32(hw_lcdif_csc_coeffctrl4)	/* 0x150 */
+	mxs_reg_32(hw_lcdif_csc_offset)	/* 0x160 */
+	mxs_reg_32(hw_lcdif_csc_limit)		/* 0x170 */
+
+#if defined(CONFIG_MX23)
+	uint32_t	reserved2[12];
+#endif
+	mxs_reg_32(hw_lcdif_data)		/* 0x1b0/0x180 */
+	mxs_reg_32(hw_lcdif_bm_error_stat)	/* 0x1c0/0x190 */
+#if defined(CONFIG_MX28)
+	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
+#endif
+	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
+	mxs_reg_32(hw_lcdif_version)		/* 0x1e0/0x1c0 */
+	mxs_reg_32(hw_lcdif_debug0)		/* 0x1f0/0x1d0 */
+	mxs_reg_32(hw_lcdif_debug1)		/* 0x200/0x1e0 */
+	mxs_reg_32(hw_lcdif_debug2)		/* 0x1f0 */
+};
+#endif
+
+#define	LCDIF_CTRL_SFTRST					(1 << 31)
+#define	LCDIF_CTRL_CLKGATE					(1 << 30)
+#define	LCDIF_CTRL_YCBCR422_INPUT				(1 << 29)
+#define	LCDIF_CTRL_READ_WRITEB					(1 << 28)
+#define	LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE				(1 << 27)
+#define	LCDIF_CTRL_DATA_SHIFT_DIR				(1 << 26)
+#define	LCDIF_CTRL_SHIFT_NUM_BITS_MASK				(0x1f << 21)
+#define	LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET			21
+#define	LCDIF_CTRL_DVI_MODE					(1 << 20)
+#define	LCDIF_CTRL_BYPASS_COUNT					(1 << 19)
+#define	LCDIF_CTRL_VSYNC_MODE					(1 << 18)
+#define	LCDIF_CTRL_DOTCLK_MODE					(1 << 17)
+#define	LCDIF_CTRL_DATA_SELECT					(1 << 16)
+#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK			(0x3 << 14)
+#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET			14
+#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK			(0x3 << 12)
+#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET			12
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK			(0x3 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET			10
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT			(0 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT			(1 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT			(2 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT			(3 << 10)
+#define	LCDIF_CTRL_WORD_LENGTH_MASK				(0x3 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_OFFSET				8
+#define	LCDIF_CTRL_WORD_LENGTH_16BIT				(0 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_8BIT				(1 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_18BIT				(2 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_24BIT				(3 << 8)
+#define	LCDIF_CTRL_RGB_TO_YCBCR422_CSC				(1 << 7)
+#define	LCDIF_CTRL_LCDIF_MASTER					(1 << 5)
+#define	LCDIF_CTRL_DATA_FORMAT_16_BIT				(1 << 3)
+#define	LCDIF_CTRL_DATA_FORMAT_18_BIT				(1 << 2)
+#define	LCDIF_CTRL_DATA_FORMAT_24_BIT				(1 << 1)
+#define	LCDIF_CTRL_RUN						(1 << 0)
+
+#define	LCDIF_CTRL1_COMBINE_MPU_WR_STRB				(1 << 27)
+#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN				(1 << 26)
+#define	LCDIF_CTRL1_BM_ERROR_IRQ				(1 << 25)
+#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW			(1 << 24)
+#define	LCDIF_CTRL1_INTERLACE_FIELDS				(1 << 23)
+#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD		(1 << 22)
+#define	LCDIF_CTRL1_FIFO_CLEAR					(1 << 21)
+#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS			(1 << 20)
+#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK			(0xf << 16)
+#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET			16
+#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN				(1 << 15)
+#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN				(1 << 14)
+#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN			(1 << 13)
+#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN				(1 << 12)
+#define	LCDIF_CTRL1_OVERFLOW_IRQ				(1 << 11)
+#define	LCDIF_CTRL1_UNDERFLOW_IRQ				(1 << 10)
+#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ				(1 << 9)
+#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ				(1 << 8)
+#define	LCDIF_CTRL1_BUSY_ENABLE					(1 << 2)
+#define	LCDIF_CTRL1_MODE86					(1 << 1)
+#define	LCDIF_CTRL1_RESET					(1 << 0)
+
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_MASK			(0x7 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET			21
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1			(0x0 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2			(0x1 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4			(0x2 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8			(0x3 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16			(0x4 << 21)
+#define	LCDIF_CTRL2_BURST_LEN_8					(1 << 20)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_MASK			(0x7 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET			16
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_RGB			(0x0 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_RBG			(0x1 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_GBR			(0x2 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_GRB			(0x3 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_BRG			(0x4 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_BGR			(0x5 << 16)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK			(0x7 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET			12
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB			(0x0 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG			(0x1 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR			(0x2 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB			(0x3 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG			(0x4 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR			(0x5 << 12)
+#define	LCDIF_CTRL2_READ_PACK_DIR				(1 << 10)
+#define	LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT		(1 << 9)
+#define	LCDIF_CTRL2_READ_MODE_6_BIT_INPUT			(1 << 8)
+#define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK		(0x7 << 4)
+#define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET	4
+#define	LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK			(0x7 << 1)
+#define	LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET			1
+
+#define	LCDIF_TRANSFER_COUNT_V_COUNT_MASK			(0xffff << 16)
+#define	LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET			16
+#define	LCDIF_TRANSFER_COUNT_H_COUNT_MASK			(0xffff << 0)
+#define	LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET			0
+
+#define	LCDIF_CUR_BUF_ADDR_MASK					0xffffffff
+#define	LCDIF_CUR_BUF_ADDR_OFFSET				0
+
+#define	LCDIF_NEXT_BUF_ADDR_MASK				0xffffffff
+#define	LCDIF_NEXT_BUF_ADDR_OFFSET				0
+
+#define	LCDIF_TIMING_CMD_HOLD_MASK				(0xff << 24)
+#define	LCDIF_TIMING_CMD_HOLD_OFFSET				24
+#define	LCDIF_TIMING_CMD_SETUP_MASK				(0xff << 16)
+#define	LCDIF_TIMING_CMD_SETUP_OFFSET				16
+#define	LCDIF_TIMING_DATA_HOLD_MASK				(0xff << 8)
+#define	LCDIF_TIMING_DATA_HOLD_OFFSET				8
+#define	LCDIF_TIMING_DATA_SETUP_MASK				(0xff << 0)
+#define	LCDIF_TIMING_DATA_SETUP_OFFSET				0
+
+#define	LCDIF_VDCTRL0_VSYNC_OEB					(1 << 29)
+#define	LCDIF_VDCTRL0_ENABLE_PRESENT				(1 << 28)
+#define	LCDIF_VDCTRL0_VSYNC_POL					(1 << 27)
+#define	LCDIF_VDCTRL0_HSYNC_POL					(1 << 26)
+#define	LCDIF_VDCTRL0_DOTCLK_POL				(1 << 25)
+#define	LCDIF_VDCTRL0_ENABLE_POL				(1 << 24)
+#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT				(1 << 21)
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT			(1 << 20)
+#define	LCDIF_VDCTRL0_HALF_LINE					(1 << 19)
+#define	LCDIF_VDCTRL0_HALF_LINE_MODE				(1 << 18)
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK			0x3ffff
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET			0
+
+#define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK				0xffffffff
+#define	LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET			0
+
+#if defined(CONFIG_MX23)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0xff << 24)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			24
+#elif defined(CONFIG_MX28)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0x3fff << 18)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			18
+#endif
+#define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK				0x3ffff
+#define	LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET			0
+
+#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS				(1 << 29)
+#define	LCDIF_VDCTRL3_VSYNC_ONLY				(1 << 28)
+#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK			(0xfff << 16)
+#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET		16
+#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK			(0xffff << 0)
+#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET			0
+
+#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK			(0x7 << 29)
+#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET			29
+#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON				(1 << 18)
+#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK		0x3ffff
+#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET		0
+
+#endif /* __MX28_REGS_LCDIF_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lradc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lradc.h
new file mode 100644
index 000000000..74f9f7670
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-lradc.h
@@ -0,0 +1,387 @@
+/*
+ * Freescale i.MX28 LRADC Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_LRADC_H__
+#define __MX28_REGS_LRADC_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_lradc_regs {
+	mxs_reg_32(hw_lradc_ctrl0);
+	mxs_reg_32(hw_lradc_ctrl1);
+	mxs_reg_32(hw_lradc_ctrl2);
+	mxs_reg_32(hw_lradc_ctrl3);
+	mxs_reg_32(hw_lradc_status);
+	mxs_reg_32(hw_lradc_ch0);
+	mxs_reg_32(hw_lradc_ch1);
+	mxs_reg_32(hw_lradc_ch2);
+	mxs_reg_32(hw_lradc_ch3);
+	mxs_reg_32(hw_lradc_ch4);
+	mxs_reg_32(hw_lradc_ch5);
+	mxs_reg_32(hw_lradc_ch6);
+	mxs_reg_32(hw_lradc_ch7);
+	mxs_reg_32(hw_lradc_delay0);
+	mxs_reg_32(hw_lradc_delay1);
+	mxs_reg_32(hw_lradc_delay2);
+	mxs_reg_32(hw_lradc_delay3);
+	mxs_reg_32(hw_lradc_debug0);
+	mxs_reg_32(hw_lradc_debug1);
+	mxs_reg_32(hw_lradc_conversion);
+	mxs_reg_32(hw_lradc_ctrl4);
+	mxs_reg_32(hw_lradc_treshold0);
+	mxs_reg_32(hw_lradc_treshold1);
+	mxs_reg_32(hw_lradc_version);
+};
+#endif
+
+#define	LRADC_CTRL0_SFTRST					(1 << 31)
+#define	LRADC_CTRL0_CLKGATE					(1 << 30)
+#define	LRADC_CTRL0_ONCHIP_GROUNDREF				(1 << 26)
+#define	LRADC_CTRL0_BUTTON1_DETECT_ENABLE			(1 << 25)
+#define	LRADC_CTRL0_BUTTON0_DETECT_ENABLE			(1 << 24)
+#define	LRADC_CTRL0_TOUCH_DETECT_ENABLE				(1 << 23)
+#define	LRADC_CTRL0_TOUCH_SCREEN_TYPE				(1 << 22)
+#define	LRADC_CTRL0_YNLRSW					(1 << 21)
+#define	LRADC_CTRL0_YPLLSW_MASK					(0x3 << 19)
+#define	LRADC_CTRL0_YPLLSW_OFFSET				19
+#define	LRADC_CTRL0_XNURSW_MASK					(0x3 << 17)
+#define	LRADC_CTRL0_XNURSW_OFFSET				17
+#define	LRADC_CTRL0_XPULSW					(1 << 16)
+#define	LRADC_CTRL0_SCHEDULE_MASK				0xff
+#define	LRADC_CTRL0_SCHEDULE_OFFSET				0
+
+#define	LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN			(1 << 28)
+#define	LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN			(1 << 27)
+#define	LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN			(1 << 26)
+#define	LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN			(1 << 25)
+#define	LRADC_CTRL1_TOUCH_DETECT_IRQ_EN				(1 << 24)
+#define	LRADC_CTRL1_LRADC7_IRQ_EN				(1 << 23)
+#define	LRADC_CTRL1_LRADC6_IRQ_EN				(1 << 22)
+#define	LRADC_CTRL1_LRADC5_IRQ_EN				(1 << 21)
+#define	LRADC_CTRL1_LRADC4_IRQ_EN				(1 << 20)
+#define	LRADC_CTRL1_LRADC3_IRQ_EN				(1 << 19)
+#define	LRADC_CTRL1_LRADC2_IRQ_EN				(1 << 18)
+#define	LRADC_CTRL1_LRADC1_IRQ_EN				(1 << 17)
+#define	LRADC_CTRL1_LRADC0_IRQ_EN				(1 << 16)
+#define	LRADC_CTRL1_BUTTON1_DETECT_IRQ				(1 << 12)
+#define	LRADC_CTRL1_BUTTON0_DETECT_IRQ				(1 << 11)
+#define	LRADC_CTRL1_THRESHOLD1_DETECT_IRQ			(1 << 10)
+#define	LRADC_CTRL1_THRESHOLD0_DETECT_IRQ			(1 << 9)
+#define	LRADC_CTRL1_TOUCH_DETECT_IRQ				(1 << 8)
+#define	LRADC_CTRL1_LRADC7_IRQ					(1 << 7)
+#define	LRADC_CTRL1_LRADC6_IRQ					(1 << 6)
+#define	LRADC_CTRL1_LRADC5_IRQ					(1 << 5)
+#define	LRADC_CTRL1_LRADC4_IRQ					(1 << 4)
+#define	LRADC_CTRL1_LRADC3_IRQ					(1 << 3)
+#define	LRADC_CTRL1_LRADC2_IRQ					(1 << 2)
+#define	LRADC_CTRL1_LRADC1_IRQ					(1 << 1)
+#define	LRADC_CTRL1_LRADC0_IRQ					(1 << 0)
+
+#define	LRADC_CTRL2_DIVIDE_BY_TWO_MASK				(0xff << 24)
+#define	LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET			24
+#define	LRADC_CTRL2_TEMPSENSE_PWD				(1 << 15)
+#define	LRADC_CTRL2_VTHSENSE_MASK				(0x3 << 13)
+#define	LRADC_CTRL2_VTHSENSE_OFFSET				13
+#define	LRADC_CTRL2_DISABLE_MUXAMP_BYPASS			(1 << 12)
+#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE1			(1 << 9)
+#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE0			(1 << 8)
+#define	LRADC_CTRL2_TEMP_ISRC1_MASK				(0xf << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_OFFSET				4
+#define	LRADC_CTRL2_TEMP_ISRC1_300				(0xf << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_280				(0xe << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_260				(0xd << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_240				(0xc << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_220				(0xb << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_200				(0xa << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_180				(0x9 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_160				(0x8 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_140				(0x7 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_120				(0x6 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_100				(0x5 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_80				(0x4 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_60				(0x3 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_40				(0x2 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_20				(0x1 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_ZERO				(0x0 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC0_MASK				(0xf << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_OFFSET				0
+#define	LRADC_CTRL2_TEMP_ISRC0_300				(0xf << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_280				(0xe << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_260				(0xd << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_240				(0xc << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_220				(0xb << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_200				(0xa << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_180				(0x9 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_160				(0x8 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_140				(0x7 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_120				(0x6 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_100				(0x5 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_80				(0x4 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_60				(0x3 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_40				(0x2 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_20				(0x1 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_ZERO				(0x0 << 0)
+
+#define	LRADC_CTRL3_DISCARD_MASK				(0x3 << 24)
+#define	LRADC_CTRL3_DISCARD_OFFSET				24
+#define	LRADC_CTRL3_DISCARD_1_SAMPLE				(0x1 << 24)
+#define	LRADC_CTRL3_DISCARD_2_SAMPLES				(0x2 << 24)
+#define	LRADC_CTRL3_DISCARD_3_SAMPLES				(0x3 << 24)
+#define	LRADC_CTRL3_FORCE_ANALOG_PWUP				(1 << 23)
+#define	LRADC_CTRL3_FORCE_ANALOG_PWDN				(1 << 22)
+#define	LRADC_CTRL3_CYCLE_TIME_MASK				(0x3 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_OFFSET				8
+#define	LRADC_CTRL3_CYCLE_TIME_6MHZ				(0x0 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_4MHZ				(0x1 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_3MHZ				(0x2 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_2MHZ				(0x3 << 8)
+#define	LRADC_CTRL3_HIGH_TIME_MASK				(0x3 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_OFFSET				4
+#define	LRADC_CTRL3_HIGH_TIME_42NS				(0x0 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_83NS				(0x1 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_125NS				(0x2 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_250NS				(0x3 << 4)
+#define	LRADC_CTRL3_DELAY_CLOCK					(1 << 1)
+#define	LRADC_CTRL3_INVERT_CLOCK				(1 << 0)
+
+#define	LRADC_STATUS_BUTTON1_PRESENT				(1 << 28)
+#define	LRADC_STATUS_BUTTON0_PRESENT				(1 << 27)
+#define	LRADC_STATUS_TEMP1_PRESENT				(1 << 26)
+#define	LRADC_STATUS_TEMP0_PRESENT				(1 << 25)
+#define	LRADC_STATUS_TOUCH_PANEL_PRESENT			(1 << 24)
+#define	LRADC_STATUS_CHANNEL7_PRESENT				(1 << 23)
+#define	LRADC_STATUS_CHANNEL6_PRESENT				(1 << 22)
+#define	LRADC_STATUS_CHANNEL5_PRESENT				(1 << 21)
+#define	LRADC_STATUS_CHANNEL4_PRESENT				(1 << 20)
+#define	LRADC_STATUS_CHANNEL3_PRESENT				(1 << 19)
+#define	LRADC_STATUS_CHANNEL2_PRESENT				(1 << 18)
+#define	LRADC_STATUS_CHANNEL1_PRESENT				(1 << 17)
+#define	LRADC_STATUS_CHANNEL0_PRESENT				(1 << 16)
+#define	LRADC_STATUS_BUTTON1_DETECT_RAW				(1 << 2)
+#define	LRADC_STATUS_BUTTON0_DETECT_RAW				(1 << 1)
+#define	LRADC_STATUS_TOUCH_DETECT_RAW				(1 << 0)
+
+#define	LRADC_CH_TOGGLE						(1 << 31)
+#define	LRADC_CH7_TESTMODE_TOGGLE				(1 << 30)
+#define	LRADC_CH_ACCUMULATE					(1 << 29)
+#define	LRADC_CH_NUM_SAMPLES_MASK				(0x1f << 24)
+#define	LRADC_CH_NUM_SAMPLES_OFFSET				24
+#define	LRADC_CH_VALUE_MASK					0x3ffff
+#define	LRADC_CH_VALUE_OFFSET					0
+
+#define	LRADC_DELAY_TRIGGER_LRADCS_MASK				(0xff << 24)
+#define	LRADC_DELAY_TRIGGER_LRADCS_OFFSET			24
+#define	LRADC_DELAY_KICK					(1 << 20)
+#define	LRADC_DELAY_TRIGGER_DELAYS_MASK				(0xf << 16)
+#define	LRADC_DELAY_TRIGGER_DELAYS_OFFSET			16
+#define	LRADC_DELAY_LOOP_COUNT_MASK				(0x1f << 11)
+#define	LRADC_DELAY_LOOP_COUNT_OFFSET				11
+#define	LRADC_DELAY_DELAY_MASK					0x7ff
+#define	LRADC_DELAY_DELAY_OFFSET				0
+
+#define	LRADC_DEBUG0_READONLY_MASK				(0xffff << 16)
+#define	LRADC_DEBUG0_READONLY_OFFSET				16
+#define	LRADC_DEBUG0_STATE_MASK					(0xfff << 0)
+#define	LRADC_DEBUG0_STATE_OFFSET				0
+
+#define	LRADC_DEBUG1_REQUEST_MASK				(0xff << 16)
+#define	LRADC_DEBUG1_REQUEST_OFFSET				16
+#define	LRADC_DEBUG1_TESTMODE_COUNT_MASK			(0x1f << 8)
+#define	LRADC_DEBUG1_TESTMODE_COUNT_OFFSET			8
+#define	LRADC_DEBUG1_TESTMODE6					(1 << 2)
+#define	LRADC_DEBUG1_TESTMODE5					(1 << 1)
+#define	LRADC_DEBUG1_TESTMODE					(1 << 0)
+
+#define	LRADC_CONVERSION_AUTOMATIC				(1 << 20)
+#define	LRADC_CONVERSION_SCALE_FACTOR_MASK			(0x3 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_OFFSET			16
+#define	LRADC_CONVERSION_SCALE_FACTOR_NIMH			(0x0 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH			(0x1 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_LI_ION			(0x2 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION		(0x3 << 16)
+#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK		0x3ff
+#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET		0
+
+#define	LRADC_CTRL4_LRADC7SELECT_MASK				(0xf << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_OFFSET				28
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL0			(0x0 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL1			(0x1 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL2			(0x2 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL3			(0x3 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL4			(0x4 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL5			(0x5 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL6			(0x6 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL7			(0x7 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL8			(0x8 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL9			(0x9 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL10			(0xa << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL11			(0xb << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL12			(0xc << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL13			(0xd << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL14			(0xe << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL15			(0xf << 28)
+#define	LRADC_CTRL4_LRADC6SELECT_MASK				(0xf << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_OFFSET				24
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL0			(0x0 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL1			(0x1 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL2			(0x2 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL3			(0x3 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL4			(0x4 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL5			(0x5 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL6			(0x6 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL7			(0x7 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL8			(0x8 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL9			(0x9 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL10			(0xa << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL11			(0xb << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL12			(0xc << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL13			(0xd << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL14			(0xe << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL15			(0xf << 24)
+#define	LRADC_CTRL4_LRADC5SELECT_MASK				(0xf << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_OFFSET				20
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL0			(0x0 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL1			(0x1 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL2			(0x2 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL3			(0x3 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL4			(0x4 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL5			(0x5 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL6			(0x6 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL7			(0x7 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL8			(0x8 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL9			(0x9 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL10			(0xa << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL11			(0xb << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL12			(0xc << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL13			(0xd << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL14			(0xe << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL15			(0xf << 20)
+#define	LRADC_CTRL4_LRADC4SELECT_MASK				(0xf << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_OFFSET				16
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL0			(0x0 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL1			(0x1 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL2			(0x2 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL3			(0x3 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL4			(0x4 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL5			(0x5 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL6			(0x6 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL7			(0x7 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL8			(0x8 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL9			(0x9 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL10			(0xa << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL11			(0xb << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL12			(0xc << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL13			(0xd << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL14			(0xe << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL15			(0xf << 16)
+#define	LRADC_CTRL4_LRADC3SELECT_MASK				(0xf << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_OFFSET				12
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL0			(0x0 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL1			(0x1 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL2			(0x2 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL3			(0x3 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL4			(0x4 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL5			(0x5 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL6			(0x6 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL7			(0x7 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL8			(0x8 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL9			(0x9 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL10			(0xa << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL11			(0xb << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL12			(0xc << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL13			(0xd << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL14			(0xe << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL15			(0xf << 12)
+#define	LRADC_CTRL4_LRADC2SELECT_MASK				(0xf << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_OFFSET				8
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL0			(0x0 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL1			(0x1 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL2			(0x2 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL3			(0x3 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL4			(0x4 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL5			(0x5 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL6			(0x6 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL7			(0x7 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL8			(0x8 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL9			(0x9 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL10			(0xa << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL11			(0xb << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL12			(0xc << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL13			(0xd << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL14			(0xe << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL15			(0xf << 8)
+#define	LRADC_CTRL4_LRADC1SELECT_MASK				(0xf << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_OFFSET				4
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL0			(0x0 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL1			(0x1 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL2			(0x2 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL3			(0x3 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL4			(0x4 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL5			(0x5 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL6			(0x6 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL7			(0x7 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL8			(0x8 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL9			(0x9 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL10			(0xa << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL11			(0xb << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL12			(0xc << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL13			(0xd << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL14			(0xe << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL15			(0xf << 4)
+#define	LRADC_CTRL4_LRADC0SELECT_MASK				0xf
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL0			(0x0 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL1			(0x1 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL2			(0x2 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL3			(0x3 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL4			(0x4 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL5			(0x5 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL6			(0x6 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL7			(0x7 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL8			(0x8 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL9			(0x9 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL10			(0xa << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL11			(0xb << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL12			(0xc << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL13			(0xd << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL14			(0xe << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL15			(0xf << 0)
+
+#define	LRADC_THRESHOLD_ENABLE					(1 << 24)
+#define	LRADC_THRESHOLD_BATTCHRG_DISABLE			(1 << 23)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_MASK			(0x7 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_OFFSET			20
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0			(0x0 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1			(0x1 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2			(0x2 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3			(0x3 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4			(0x4 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5			(0x5 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6			(0x6 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7			(0x7 << 20)
+#define	LRADC_THRESHOLD_SETTING_MASK				(0x3 << 18)
+#define	LRADC_THRESHOLD_SETTING_OFFSET				18
+#define	LRADC_THRESHOLD_SETTING_NO_COMPARE			(0x0 << 18)
+#define	LRADC_THRESHOLD_SETTING_DETECT_LOW			(0x1 << 18)
+#define	LRADC_THRESHOLD_SETTING_DETECT_HIGH			(0x2 << 18)
+#define	LRADC_THRESHOLD_SETTING_RESERVED			(0x3 << 18)
+#define	LRADC_THRESHOLD_VALUE_MASK				0x3ffff
+#define	LRADC_THRESHOLD_VALUE_OFFSET				0
+
+#define	LRADC_VERSION_MAJOR_MASK				(0xff << 24)
+#define	LRADC_VERSION_MAJOR_OFFSET				24
+#define	LRADC_VERSION_MINOR_MASK				(0xff << 16)
+#define	LRADC_VERSION_MINOR_OFFSET				16
+#define	LRADC_VERSION_STEP_MASK					0xffff
+#define	LRADC_VERSION_STEP_OFFSET				0
+
+#endif	/* __MX28_REGS_LRADC_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ocotp.h
new file mode 100644
index 000000000..bd80ac77f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ocotp.h
@@ -0,0 +1,160 @@
+/*
+ * Freescale i.MX28 OCOTP Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_OCOTP_H__
+#define __MX28_REGS_OCOTP_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_ocotp_regs {
+	mxs_reg_32(hw_ocotp_ctrl)	/* 0x0 */
+	mxs_reg_32(hw_ocotp_data)	/* 0x10 */
+	mxs_reg_32(hw_ocotp_cust0)	/* 0x20 */
+	mxs_reg_32(hw_ocotp_cust1)	/* 0x30 */
+	mxs_reg_32(hw_ocotp_cust2)	/* 0x40 */
+	mxs_reg_32(hw_ocotp_cust3)	/* 0x50 */
+	mxs_reg_32(hw_ocotp_crypto0)	/* 0x60 */
+	mxs_reg_32(hw_ocotp_crypto1)	/* 0x70 */
+	mxs_reg_32(hw_ocotp_crypto2)	/* 0x80 */
+	mxs_reg_32(hw_ocotp_crypto3)	/* 0x90 */
+	mxs_reg_32(hw_ocotp_hwcap0)	/* 0xa0 */
+	mxs_reg_32(hw_ocotp_hwcap1)	/* 0xb0 */
+	mxs_reg_32(hw_ocotp_hwcap2)	/* 0xc0 */
+	mxs_reg_32(hw_ocotp_hwcap3)	/* 0xd0 */
+	mxs_reg_32(hw_ocotp_hwcap4)	/* 0xe0 */
+	mxs_reg_32(hw_ocotp_hwcap5)	/* 0xf0 */
+	mxs_reg_32(hw_ocotp_swcap)	/* 0x100 */
+	mxs_reg_32(hw_ocotp_custcap)	/* 0x110 */
+	mxs_reg_32(hw_ocotp_lock)	/* 0x120 */
+	mxs_reg_32(hw_ocotp_ops0)	/* 0x130 */
+	mxs_reg_32(hw_ocotp_ops1)	/* 0x140 */
+	mxs_reg_32(hw_ocotp_ops2)	/* 0x150 */
+	mxs_reg_32(hw_ocotp_ops3)	/* 0x160 */
+	mxs_reg_32(hw_ocotp_un0)	/* 0x170 */
+	mxs_reg_32(hw_ocotp_un1)	/* 0x180 */
+	mxs_reg_32(hw_ocotp_un2)	/* 0x190 */
+	mxs_reg_32(hw_ocotp_rom0)	/* 0x1a0 */
+	mxs_reg_32(hw_ocotp_rom1)	/* 0x1b0 */
+	mxs_reg_32(hw_ocotp_rom2)	/* 0x1c0 */
+	mxs_reg_32(hw_ocotp_rom3)	/* 0x1d0 */
+	mxs_reg_32(hw_ocotp_rom4)	/* 0x1e0 */
+	mxs_reg_32(hw_ocotp_rom5)	/* 0x1f0 */
+	mxs_reg_32(hw_ocotp_rom6)	/* 0x200 */
+	mxs_reg_32(hw_ocotp_rom7)	/* 0x210 */
+	mxs_reg_32(hw_ocotp_srk0)	/* 0x220 */
+	mxs_reg_32(hw_ocotp_srk1)	/* 0x230 */
+	mxs_reg_32(hw_ocotp_srk2)	/* 0x240 */
+	mxs_reg_32(hw_ocotp_srk3)	/* 0x250 */
+	mxs_reg_32(hw_ocotp_srk4)	/* 0x260 */
+	mxs_reg_32(hw_ocotp_srk5)	/* 0x270 */
+	mxs_reg_32(hw_ocotp_srk6)	/* 0x280 */
+	mxs_reg_32(hw_ocotp_srk7)	/* 0x290 */
+	mxs_reg_32(hw_ocotp_version)	/* 0x2a0 */
+};
+#endif
+
+#define	OCOTP_CTRL_WR_UNLOCK_MASK		(0xffff << 16)
+#define	OCOTP_CTRL_WR_UNLOCK_OFFSET		16
+#define	OCOTP_CTRL_WR_UNLOCK_KEY		(0x3e77 << 16)
+#define	OCOTP_CTRL_RELOAD_SHADOWS		(1 << 13)
+#define	OCOTP_CTRL_RD_BANK_OPEN			(1 << 12)
+#define	OCOTP_CTRL_ERROR			(1 << 9)
+#define	OCOTP_CTRL_BUSY				(1 << 8)
+#define	OCOTP_CTRL_ADDR_MASK			0x3f
+#define	OCOTP_CTRL_ADDR_OFFSET			0
+
+#define	OCOTP_DATA_DATA_MASK			0xffffffff
+#define	OCOTP_DATA_DATA_OFFSET			0
+
+#define	OCOTP_CUST_BITS_MASK			0xffffffff
+#define	OCOTP_CUST_BITS_OFFSET			0
+
+#define	OCOTP_CRYPTO_BITS_MASK			0xffffffff
+#define	OCOTP_CRYPTO_BITS_OFFSET		0
+
+#define	OCOTP_HWCAP_BITS_MASK			0xffffffff
+#define	OCOTP_HWCAP_BITS_OFFSET			0
+
+#define	OCOTP_SWCAP_BITS_MASK			0xffffffff
+#define	OCOTP_SWCAP_BITS_OFFSET			0
+
+#define	OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT	(1 << 2)
+#define	OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT	(1 << 1)
+
+#define	OCOTP_LOCK_ROM7				(1 << 31)
+#define	OCOTP_LOCK_ROM6				(1 << 30)
+#define	OCOTP_LOCK_ROM5				(1 << 29)
+#define	OCOTP_LOCK_ROM4				(1 << 28)
+#define	OCOTP_LOCK_ROM3				(1 << 27)
+#define	OCOTP_LOCK_ROM2				(1 << 26)
+#define	OCOTP_LOCK_ROM1				(1 << 25)
+#define	OCOTP_LOCK_ROM0				(1 << 24)
+#define	OCOTP_LOCK_HWSW_SHADOW_ALT		(1 << 23)
+#define	OCOTP_LOCK_CRYPTODCP_ALT		(1 << 22)
+#define	OCOTP_LOCK_CRYPTOKEY_ALT		(1 << 21)
+#define	OCOTP_LOCK_PIN				(1 << 20)
+#define	OCOTP_LOCK_OPS				(1 << 19)
+#define	OCOTP_LOCK_UN2				(1 << 18)
+#define	OCOTP_LOCK_UN1				(1 << 17)
+#define	OCOTP_LOCK_UN0				(1 << 16)
+#define	OCOTP_LOCK_SRK				(1 << 15)
+#define	OCOTP_LOCK_UNALLOCATED_MASK		(0x7 << 12)
+#define	OCOTP_LOCK_UNALLOCATED_OFFSET		12
+#define	OCOTP_LOCK_SRK_SHADOW			(1 << 11)
+#define	OCOTP_LOCK_ROM_SHADOW			(1 << 10)
+#define	OCOTP_LOCK_CUSTCAP			(1 << 9)
+#define	OCOTP_LOCK_HWSW				(1 << 8)
+#define	OCOTP_LOCK_CUSTCAP_SHADOW		(1 << 7)
+#define	OCOTP_LOCK_HWSW_SHADOW			(1 << 6)
+#define	OCOTP_LOCK_CRYPTODCP			(1 << 5)
+#define	OCOTP_LOCK_CRYPTOKEY			(1 << 4)
+#define	OCOTP_LOCK_CUST3			(1 << 3)
+#define	OCOTP_LOCK_CUST2			(1 << 2)
+#define	OCOTP_LOCK_CUST1			(1 << 1)
+#define	OCOTP_LOCK_CUST0			(1 << 0)
+
+#define	OCOTP_OPS_BITS_MASK			0xffffffff
+#define	OCOTP_OPS_BITS_OFFSET			0
+
+#define	OCOTP_UN_BITS_MASK			0xffffffff
+#define	OCOTP_UN_BITS_OFFSET			0
+
+#define	OCOTP_ROM_BOOT_MODE_MASK		(0xff << 24)
+#define	OCOTP_ROM_BOOT_MODE_OFFSET		24
+#define	OCOTP_ROM_SD_MMC_MODE_MASK		(0x3 << 22)
+#define	OCOTP_ROM_SD_MMC_MODE_OFFSET		22
+#define	OCOTP_ROM_SD_POWER_GATE_GPIO_MASK	(0x3 << 20)
+#define	OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET	20
+#define	OCOTP_ROM_SD_POWER_UP_DELAY_MASK	(0x3f << 14)
+#define	OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET	14
+#define	OCOTP_ROM_SD_BUS_WIDTH_MASK		(0x3 << 12)
+#define	OCOTP_ROM_SD_BUS_WIDTH_OFFSET		12
+#define	OCOTP_ROM_SSP_SCK_INDEX_MASK		(0xf << 8)
+#define	OCOTP_ROM_SSP_SCK_INDEX_OFFSET		8
+#define	OCOTP_ROM_EMMC_USE_DDR			(1 << 7)
+#define	OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ	(1 << 6)
+#define	OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM	(1 << 5)
+#define	OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT	(1 << 4)
+#define	OCOTP_ROM_SD_MBR_BOOT			(1 << 3)
+
+#define	OCOTP_SRK_BITS_MASK			0xffffffff
+#define	OCOTP_SRK_BITS_OFFSET			0
+
+#define	OCOTP_VERSION_MAJOR_MASK		(0xff << 24)
+#define	OCOTP_VERSION_MAJOR_OFFSET		24
+#define	OCOTP_VERSION_MINOR_MASK		(0xff << 16)
+#define	OCOTP_VERSION_MINOR_OFFSET		16
+#define	OCOTP_VERSION_STEP_MASK			0xffff
+#define	OCOTP_VERSION_STEP_OFFSET		0
+
+#endif /* __MX28_REGS_OCOTP_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
new file mode 100644
index 000000000..251fe6616
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
@@ -0,0 +1,1271 @@
+/*
+ * Freescale i.MX28 PINCTRL Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_PINCTRL_H__
+#define __MX28_REGS_PINCTRL_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_pinctrl_regs {
+	mxs_reg_32(hw_pinctrl_ctrl)		/* 0x0 */
+
+	uint32_t	reserved1[60];
+
+	mxs_reg_32(hw_pinctrl_muxsel0)		/* 0x100 */
+	mxs_reg_32(hw_pinctrl_muxsel1)		/* 0x110 */
+	mxs_reg_32(hw_pinctrl_muxsel2)		/* 0x120 */
+	mxs_reg_32(hw_pinctrl_muxsel3)		/* 0x130 */
+	mxs_reg_32(hw_pinctrl_muxsel4)		/* 0x140 */
+	mxs_reg_32(hw_pinctrl_muxsel5)		/* 0x150 */
+	mxs_reg_32(hw_pinctrl_muxsel6)		/* 0x160 */
+	mxs_reg_32(hw_pinctrl_muxsel7)		/* 0x170 */
+	mxs_reg_32(hw_pinctrl_muxsel8)		/* 0x180 */
+	mxs_reg_32(hw_pinctrl_muxsel9)		/* 0x190 */
+	mxs_reg_32(hw_pinctrl_muxsel10)	/* 0x1a0 */
+	mxs_reg_32(hw_pinctrl_muxsel11)	/* 0x1b0 */
+	mxs_reg_32(hw_pinctrl_muxsel12)	/* 0x1c0 */
+	mxs_reg_32(hw_pinctrl_muxsel13)	/* 0x1d0 */
+
+	uint32_t	reserved2[72];
+
+	mxs_reg_32(hw_pinctrl_drive0)		/* 0x300 */
+	mxs_reg_32(hw_pinctrl_drive1)		/* 0x310 */
+	mxs_reg_32(hw_pinctrl_drive2)		/* 0x320 */
+	mxs_reg_32(hw_pinctrl_drive3)		/* 0x330 */
+	mxs_reg_32(hw_pinctrl_drive4)		/* 0x340 */
+	mxs_reg_32(hw_pinctrl_drive5)		/* 0x350 */
+	mxs_reg_32(hw_pinctrl_drive6)		/* 0x360 */
+	mxs_reg_32(hw_pinctrl_drive7)		/* 0x370 */
+	mxs_reg_32(hw_pinctrl_drive8)		/* 0x380 */
+	mxs_reg_32(hw_pinctrl_drive9)		/* 0x390 */
+	mxs_reg_32(hw_pinctrl_drive10)		/* 0x3a0 */
+	mxs_reg_32(hw_pinctrl_drive11)		/* 0x3b0 */
+	mxs_reg_32(hw_pinctrl_drive12)		/* 0x3c0 */
+	mxs_reg_32(hw_pinctrl_drive13)		/* 0x3d0 */
+	mxs_reg_32(hw_pinctrl_drive14)		/* 0x3e0 */
+	mxs_reg_32(hw_pinctrl_drive15)		/* 0x3f0 */
+	mxs_reg_32(hw_pinctrl_drive16)		/* 0x400 */
+	mxs_reg_32(hw_pinctrl_drive17)		/* 0x410 */
+	mxs_reg_32(hw_pinctrl_drive18)		/* 0x420 */
+	mxs_reg_32(hw_pinctrl_drive19)		/* 0x430 */
+
+	uint32_t	reserved3[112];
+
+	mxs_reg_32(hw_pinctrl_pull0)		/* 0x600 */
+	mxs_reg_32(hw_pinctrl_pull1)		/* 0x610 */
+	mxs_reg_32(hw_pinctrl_pull2)		/* 0x620 */
+	mxs_reg_32(hw_pinctrl_pull3)		/* 0x630 */
+	mxs_reg_32(hw_pinctrl_pull4)		/* 0x640 */
+	mxs_reg_32(hw_pinctrl_pull5)		/* 0x650 */
+	mxs_reg_32(hw_pinctrl_pull6)		/* 0x660 */
+
+	uint32_t	reserved4[36];
+
+	mxs_reg_32(hw_pinctrl_dout0)		/* 0x700 */
+	mxs_reg_32(hw_pinctrl_dout1)		/* 0x710 */
+	mxs_reg_32(hw_pinctrl_dout2)		/* 0x720 */
+	mxs_reg_32(hw_pinctrl_dout3)		/* 0x730 */
+	mxs_reg_32(hw_pinctrl_dout4)		/* 0x740 */
+
+	uint32_t	reserved5[108];
+
+	mxs_reg_32(hw_pinctrl_din0)		/* 0x900 */
+	mxs_reg_32(hw_pinctrl_din1)		/* 0x910 */
+	mxs_reg_32(hw_pinctrl_din2)		/* 0x920 */
+	mxs_reg_32(hw_pinctrl_din3)		/* 0x930 */
+	mxs_reg_32(hw_pinctrl_din4)		/* 0x940 */
+
+	uint32_t	reserved6[108];
+
+	mxs_reg_32(hw_pinctrl_doe0)		/* 0xb00 */
+	mxs_reg_32(hw_pinctrl_doe1)		/* 0xb10 */
+	mxs_reg_32(hw_pinctrl_doe2)		/* 0xb20 */
+	mxs_reg_32(hw_pinctrl_doe3)		/* 0xb30 */
+	mxs_reg_32(hw_pinctrl_doe4)		/* 0xb40 */
+
+	uint32_t	reserved7[300];
+
+	mxs_reg_32(hw_pinctrl_pin2irq0)	/* 0x1000 */
+	mxs_reg_32(hw_pinctrl_pin2irq1)	/* 0x1010 */
+	mxs_reg_32(hw_pinctrl_pin2irq2)	/* 0x1020 */
+	mxs_reg_32(hw_pinctrl_pin2irq3)	/* 0x1030 */
+	mxs_reg_32(hw_pinctrl_pin2irq4)	/* 0x1040 */
+
+	uint32_t	reserved8[44];
+
+	mxs_reg_32(hw_pinctrl_irqen0)		/* 0x1100 */
+	mxs_reg_32(hw_pinctrl_irqen1)		/* 0x1110 */
+	mxs_reg_32(hw_pinctrl_irqen2)		/* 0x1120 */
+	mxs_reg_32(hw_pinctrl_irqen3)		/* 0x1130 */
+	mxs_reg_32(hw_pinctrl_irqen4)		/* 0x1140 */
+
+	uint32_t	reserved9[44];
+
+	mxs_reg_32(hw_pinctrl_irqlevel0)	/* 0x1200 */
+	mxs_reg_32(hw_pinctrl_irqlevel1)	/* 0x1210 */
+	mxs_reg_32(hw_pinctrl_irqlevel2)	/* 0x1220 */
+	mxs_reg_32(hw_pinctrl_irqlevel3)	/* 0x1230 */
+	mxs_reg_32(hw_pinctrl_irqlevel4)	/* 0x1240 */
+
+	uint32_t	reserved10[44];
+
+	mxs_reg_32(hw_pinctrl_irqpol0)		/* 0x1300 */
+	mxs_reg_32(hw_pinctrl_irqpol1)		/* 0x1310 */
+	mxs_reg_32(hw_pinctrl_irqpol2)		/* 0x1320 */
+	mxs_reg_32(hw_pinctrl_irqpol3)		/* 0x1330 */
+	mxs_reg_32(hw_pinctrl_irqpol4)		/* 0x1340 */
+
+	uint32_t	reserved11[44];
+
+	mxs_reg_32(hw_pinctrl_irqstat0)	/* 0x1400 */
+	mxs_reg_32(hw_pinctrl_irqstat1)	/* 0x1410 */
+	mxs_reg_32(hw_pinctrl_irqstat2)	/* 0x1420 */
+	mxs_reg_32(hw_pinctrl_irqstat3)	/* 0x1430 */
+	mxs_reg_32(hw_pinctrl_irqstat4)	/* 0x1440 */
+
+	uint32_t	reserved12[380];
+
+	mxs_reg_32(hw_pinctrl_emi_odt_ctrl)	/* 0x1a40 */
+
+	uint32_t	reserved13[76];
+
+	mxs_reg_32(hw_pinctrl_emi_ds_ctrl)	/* 0x1b80 */
+};
+#endif
+
+#define	PINCTRL_CTRL_SFTRST				(1 << 31)
+#define	PINCTRL_CTRL_CLKGATE				(1 << 30)
+#define	PINCTRL_CTRL_PRESENT4				(1 << 24)
+#define	PINCTRL_CTRL_PRESENT3				(1 << 23)
+#define	PINCTRL_CTRL_PRESENT2				(1 << 22)
+#define	PINCTRL_CTRL_PRESENT1				(1 << 21)
+#define	PINCTRL_CTRL_PRESENT0				(1 << 20)
+#define	PINCTRL_CTRL_IRQOUT4				(1 << 4)
+#define	PINCTRL_CTRL_IRQOUT3				(1 << 3)
+#define	PINCTRL_CTRL_IRQOUT2				(1 << 2)
+#define	PINCTRL_CTRL_IRQOUT1				(1 << 1)
+#define	PINCTRL_CTRL_IRQOUT0				(1 << 0)
+
+#define	PINCTRL_MUXSEL0_BANK0_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL0_BANK0_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL0_BANK0_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL0_BANK0_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL0_BANK0_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL0_BANK0_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL0_BANK0_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL0_BANK0_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL1_BANK0_PIN28_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET		24
+#define	PINCTRL_MUXSEL1_BANK0_PIN27_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET		22
+#define	PINCTRL_MUXSEL1_BANK0_PIN26_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET		20
+#define	PINCTRL_MUXSEL1_BANK0_PIN25_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET		18
+#define	PINCTRL_MUXSEL1_BANK0_PIN24_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET		16
+#define	PINCTRL_MUXSEL1_BANK0_PIN23_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET		14
+#define	PINCTRL_MUXSEL1_BANK0_PIN22_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET		12
+#define	PINCTRL_MUXSEL1_BANK0_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL1_BANK0_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL1_BANK0_PIN19_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET		6
+#define	PINCTRL_MUXSEL1_BANK0_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL1_BANK0_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL1_BANK0_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL2_BANK1_PIN15_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET		30
+#define	PINCTRL_MUXSEL2_BANK1_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL2_BANK1_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL2_BANK1_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL2_BANK1_PIN11_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET		22
+#define	PINCTRL_MUXSEL2_BANK1_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL2_BANK1_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL2_BANK1_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL2_BANK1_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL2_BANK1_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL2_BANK1_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL2_BANK1_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL2_BANK1_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL2_BANK1_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL2_BANK1_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL2_BANK1_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL3_BANK1_PIN31_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET		30
+#define	PINCTRL_MUXSEL3_BANK1_PIN30_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET		28
+#define	PINCTRL_MUXSEL3_BANK1_PIN29_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET		26
+#define	PINCTRL_MUXSEL3_BANK1_PIN28_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET		24
+#define	PINCTRL_MUXSEL3_BANK1_PIN27_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET		22
+#define	PINCTRL_MUXSEL3_BANK1_PIN26_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET		20
+#define	PINCTRL_MUXSEL3_BANK1_PIN25_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET		18
+#define	PINCTRL_MUXSEL3_BANK1_PIN24_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET		16
+#define	PINCTRL_MUXSEL3_BANK1_PIN23_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET		14
+#define	PINCTRL_MUXSEL3_BANK1_PIN22_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET		12
+#define	PINCTRL_MUXSEL3_BANK1_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL3_BANK1_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL3_BANK1_PIN19_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET		6
+#define	PINCTRL_MUXSEL3_BANK1_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL3_BANK1_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL3_BANK1_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL4_BANK2_PIN15_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET		30
+#define	PINCTRL_MUXSEL4_BANK2_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL4_BANK2_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL4_BANK2_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL4_BANK2_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL4_BANK2_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL4_BANK2_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL4_BANK2_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL4_BANK2_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL4_BANK2_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL4_BANK2_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL4_BANK2_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL4_BANK2_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL4_BANK2_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL4_BANK2_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL5_BANK2_PIN27_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET		22
+#define	PINCTRL_MUXSEL5_BANK2_PIN26_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET		20
+#define	PINCTRL_MUXSEL5_BANK2_PIN25_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET		18
+#define	PINCTRL_MUXSEL5_BANK2_PIN24_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET		16
+#define	PINCTRL_MUXSEL5_BANK2_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL5_BANK2_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL5_BANK2_PIN19_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET		6
+#define	PINCTRL_MUXSEL5_BANK2_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL5_BANK2_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL5_BANK2_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL6_BANK3_PIN15_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET		30
+#define	PINCTRL_MUXSEL6_BANK3_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL6_BANK3_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL6_BANK3_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL6_BANK3_PIN11_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET		22
+#define	PINCTRL_MUXSEL6_BANK3_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL6_BANK3_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL6_BANK3_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL6_BANK3_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL6_BANK3_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL6_BANK3_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL6_BANK3_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL6_BANK3_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL6_BANK3_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL6_BANK3_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL6_BANK3_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL7_BANK3_PIN30_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET		28
+#define	PINCTRL_MUXSEL7_BANK3_PIN29_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET		26
+#define	PINCTRL_MUXSEL7_BANK3_PIN28_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET		24
+#define	PINCTRL_MUXSEL7_BANK3_PIN27_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET		22
+#define	PINCTRL_MUXSEL7_BANK3_PIN26_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET		20
+#define	PINCTRL_MUXSEL7_BANK3_PIN25_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET		18
+#define	PINCTRL_MUXSEL7_BANK3_PIN24_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET		16
+#define	PINCTRL_MUXSEL7_BANK3_PIN23_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET		14
+#define	PINCTRL_MUXSEL7_BANK3_PIN22_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET		12
+#define	PINCTRL_MUXSEL7_BANK3_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL7_BANK3_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL7_BANK3_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL7_BANK3_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL7_BANK3_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL8_BANK4_PIN15_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET		30
+#define	PINCTRL_MUXSEL8_BANK4_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL8_BANK4_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL8_BANK4_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL8_BANK4_PIN11_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET		22
+#define	PINCTRL_MUXSEL8_BANK4_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL8_BANK4_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL8_BANK4_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL8_BANK4_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL8_BANK4_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL8_BANK4_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL8_BANK4_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL8_BANK4_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL8_BANK4_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL8_BANK4_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL8_BANK4_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL9_BANK4_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL9_BANK4_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL10_BANK5_PIN15_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET		30
+#define	PINCTRL_MUXSEL10_BANK5_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL10_BANK5_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL10_BANK5_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL10_BANK5_PIN11_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET		22
+#define	PINCTRL_MUXSEL10_BANK5_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL10_BANK5_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL10_BANK5_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL10_BANK5_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL10_BANK5_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL10_BANK5_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL10_BANK5_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL10_BANK5_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL10_BANK5_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL10_BANK5_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL10_BANK5_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL11_BANK5_PIN26_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET		20
+#define	PINCTRL_MUXSEL11_BANK5_PIN23_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET		14
+#define	PINCTRL_MUXSEL11_BANK5_PIN22_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET		12
+#define	PINCTRL_MUXSEL11_BANK5_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL11_BANK5_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL11_BANK5_PIN19_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET		6
+#define	PINCTRL_MUXSEL11_BANK5_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL11_BANK5_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL11_BANK5_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL12_BANK6_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL12_BANK6_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL12_BANK6_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL12_BANK6_PIN11_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET		22
+#define	PINCTRL_MUXSEL12_BANK6_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL12_BANK6_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL12_BANK6_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL12_BANK6_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL12_BANK6_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL12_BANK6_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL12_BANK6_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL12_BANK6_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL12_BANK6_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL12_BANK6_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL12_BANK6_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL13_BANK6_PIN24_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET		16
+#define	PINCTRL_MUXSEL13_BANK6_PIN23_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET		14
+#define	PINCTRL_MUXSEL13_BANK6_PIN22_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET		12
+#define	PINCTRL_MUXSEL13_BANK6_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL13_BANK6_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL13_BANK6_PIN19_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET		6
+#define	PINCTRL_MUXSEL13_BANK6_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL13_BANK6_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL13_BANK6_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET		0
+
+#define	PINCTRL_DRIVE0_BANK0_PIN07_V			(1 << 30)
+#define	PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET		28
+#define	PINCTRL_DRIVE0_BANK0_PIN06_V			(1 << 26)
+#define	PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET		24
+#define	PINCTRL_DRIVE0_BANK0_PIN05_V			(1 << 22)
+#define	PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET		20
+#define	PINCTRL_DRIVE0_BANK0_PIN04_V			(1 << 18)
+#define	PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET		16
+#define	PINCTRL_DRIVE0_BANK0_PIN03_V			(1 << 14)
+#define	PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET		12
+#define	PINCTRL_DRIVE0_BANK0_PIN02_V			(1 << 10)
+#define	PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET		8
+#define	PINCTRL_DRIVE0_BANK0_PIN01_V			(1 << 6)
+#define	PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET		4
+#define	PINCTRL_DRIVE0_BANK0_PIN00_V			(1 << 2)
+#define	PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE2_BANK0_PIN23_V			(1 << 30)
+#define	PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET		28
+#define	PINCTRL_DRIVE2_BANK0_PIN22_V			(1 << 26)
+#define	PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET		24
+#define	PINCTRL_DRIVE2_BANK0_PIN21_V			(1 << 22)
+#define	PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET		20
+#define	PINCTRL_DRIVE2_BANK0_PIN20_V			(1 << 18)
+#define	PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET		16
+#define	PINCTRL_DRIVE2_BANK0_PIN19_V			(1 << 14)
+#define	PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET		12
+#define	PINCTRL_DRIVE2_BANK0_PIN18_V			(1 << 10)
+#define	PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET		8
+#define	PINCTRL_DRIVE2_BANK0_PIN17_V			(1 << 6)
+#define	PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET		4
+#define	PINCTRL_DRIVE2_BANK0_PIN16_V			(1 << 2)
+#define	PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE3_BANK0_PIN28_V			(1 << 18)
+#define	PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET		16
+#define	PINCTRL_DRIVE3_BANK0_PIN27_V			(1 << 14)
+#define	PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET		12
+#define	PINCTRL_DRIVE3_BANK0_PIN26_V			(1 << 10)
+#define	PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET		8
+#define	PINCTRL_DRIVE3_BANK0_PIN25_V			(1 << 6)
+#define	PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET		4
+#define	PINCTRL_DRIVE3_BANK0_PIN24_V			(1 << 2)
+#define	PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE4_BANK1_PIN07_V			(1 << 30)
+#define	PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET		28
+#define	PINCTRL_DRIVE4_BANK1_PIN06_V			(1 << 26)
+#define	PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET		24
+#define	PINCTRL_DRIVE4_BANK1_PIN05_V			(1 << 22)
+#define	PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET		20
+#define	PINCTRL_DRIVE4_BANK1_PIN04_V			(1 << 18)
+#define	PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET		16
+#define	PINCTRL_DRIVE4_BANK1_PIN03_V			(1 << 14)
+#define	PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET		12
+#define	PINCTRL_DRIVE4_BANK1_PIN02_V			(1 << 10)
+#define	PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET		8
+#define	PINCTRL_DRIVE4_BANK1_PIN01_V			(1 << 6)
+#define	PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET		4
+#define	PINCTRL_DRIVE4_BANK1_PIN00_V			(1 << 2)
+#define	PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE5_BANK1_PIN15_V			(1 << 30)
+#define	PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET		28
+#define	PINCTRL_DRIVE5_BANK1_PIN14_V			(1 << 26)
+#define	PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET		24
+#define	PINCTRL_DRIVE5_BANK1_PIN13_V			(1 << 22)
+#define	PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET		20
+#define	PINCTRL_DRIVE5_BANK1_PIN12_V			(1 << 18)
+#define	PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET		16
+#define	PINCTRL_DRIVE5_BANK1_PIN11_V			(1 << 14)
+#define	PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET		12
+#define	PINCTRL_DRIVE5_BANK1_PIN10_V			(1 << 10)
+#define	PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET		8
+#define	PINCTRL_DRIVE5_BANK1_PIN09_V			(1 << 6)
+#define	PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET		4
+#define	PINCTRL_DRIVE5_BANK1_PIN08_V			(1 << 2)
+#define	PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE6_BANK1_PIN23_V			(1 << 30)
+#define	PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET		28
+#define	PINCTRL_DRIVE6_BANK1_PIN22_V			(1 << 26)
+#define	PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET		24
+#define	PINCTRL_DRIVE6_BANK1_PIN21_V			(1 << 22)
+#define	PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET		20
+#define	PINCTRL_DRIVE6_BANK1_PIN20_V			(1 << 18)
+#define	PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET		16
+#define	PINCTRL_DRIVE6_BANK1_PIN19_V			(1 << 14)
+#define	PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET		12
+#define	PINCTRL_DRIVE6_BANK1_PIN18_V			(1 << 10)
+#define	PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET		8
+#define	PINCTRL_DRIVE6_BANK1_PIN17_V			(1 << 6)
+#define	PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET		4
+#define	PINCTRL_DRIVE6_BANK1_PIN16_V			(1 << 2)
+#define	PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE7_BANK1_PIN31_V			(1 << 30)
+#define	PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET		28
+#define	PINCTRL_DRIVE7_BANK1_PIN30_V			(1 << 26)
+#define	PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET		24
+#define	PINCTRL_DRIVE7_BANK1_PIN29_V			(1 << 22)
+#define	PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET		20
+#define	PINCTRL_DRIVE7_BANK1_PIN28_V			(1 << 18)
+#define	PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET		16
+#define	PINCTRL_DRIVE7_BANK1_PIN27_V			(1 << 14)
+#define	PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET		12
+#define	PINCTRL_DRIVE7_BANK1_PIN26_V			(1 << 10)
+#define	PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET		8
+#define	PINCTRL_DRIVE7_BANK1_PIN25_V			(1 << 6)
+#define	PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET		4
+#define	PINCTRL_DRIVE7_BANK1_PIN24_V			(1 << 2)
+#define	PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE8_BANK2_PIN07_V			(1 << 30)
+#define	PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET		28
+#define	PINCTRL_DRIVE8_BANK2_PIN06_V			(1 << 26)
+#define	PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET		24
+#define	PINCTRL_DRIVE8_BANK2_PIN05_V			(1 << 22)
+#define	PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET		20
+#define	PINCTRL_DRIVE8_BANK2_PIN04_V			(1 << 18)
+#define	PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET		16
+#define	PINCTRL_DRIVE8_BANK2_PIN03_V			(1 << 14)
+#define	PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET		12
+#define	PINCTRL_DRIVE8_BANK2_PIN02_V			(1 << 10)
+#define	PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET		8
+#define	PINCTRL_DRIVE8_BANK2_PIN01_V			(1 << 6)
+#define	PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET		4
+#define	PINCTRL_DRIVE8_BANK2_PIN00_V			(1 << 2)
+#define	PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE9_BANK2_PIN15_V			(1 << 30)
+#define	PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET		28
+#define	PINCTRL_DRIVE9_BANK2_PIN14_V			(1 << 26)
+#define	PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET		24
+#define	PINCTRL_DRIVE9_BANK2_PIN13_V			(1 << 22)
+#define	PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET		20
+#define	PINCTRL_DRIVE9_BANK2_PIN12_V			(1 << 18)
+#define	PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET		16
+#define	PINCTRL_DRIVE9_BANK2_PIN10_V			(1 << 10)
+#define	PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET		8
+#define	PINCTRL_DRIVE9_BANK2_PIN09_V			(1 << 6)
+#define	PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET		4
+#define	PINCTRL_DRIVE9_BANK2_PIN08_V			(1 << 2)
+#define	PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE10_BANK2_PIN21_V			(1 << 22)
+#define	PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET		20
+#define	PINCTRL_DRIVE10_BANK2_PIN20_V			(1 << 18)
+#define	PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET		16
+#define	PINCTRL_DRIVE10_BANK2_PIN19_V			(1 << 14)
+#define	PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET		12
+#define	PINCTRL_DRIVE10_BANK2_PIN18_V			(1 << 10)
+#define	PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET		8
+#define	PINCTRL_DRIVE10_BANK2_PIN17_V			(1 << 6)
+#define	PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET		4
+#define	PINCTRL_DRIVE10_BANK2_PIN16_V			(1 << 2)
+#define	PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE11_BANK2_PIN27_V			(1 << 14)
+#define	PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET		12
+#define	PINCTRL_DRIVE11_BANK2_PIN26_V			(1 << 10)
+#define	PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET		8
+#define	PINCTRL_DRIVE11_BANK2_PIN25_V			(1 << 6)
+#define	PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET		4
+#define	PINCTRL_DRIVE11_BANK2_PIN24_V			(1 << 2)
+#define	PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE12_BANK3_PIN07_V			(1 << 30)
+#define	PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET		28
+#define	PINCTRL_DRIVE12_BANK3_PIN06_V			(1 << 26)
+#define	PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET		24
+#define	PINCTRL_DRIVE12_BANK3_PIN05_V			(1 << 22)
+#define	PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET		20
+#define	PINCTRL_DRIVE12_BANK3_PIN04_V			(1 << 18)
+#define	PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET		16
+#define	PINCTRL_DRIVE12_BANK3_PIN03_V			(1 << 14)
+#define	PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET		12
+#define	PINCTRL_DRIVE12_BANK3_PIN02_V			(1 << 10)
+#define	PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET		8
+#define	PINCTRL_DRIVE12_BANK3_PIN01_V			(1 << 6)
+#define	PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET		4
+#define	PINCTRL_DRIVE12_BANK3_PIN00_V			(1 << 2)
+#define	PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE13_BANK3_PIN15_V			(1 << 30)
+#define	PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET		28
+#define	PINCTRL_DRIVE13_BANK3_PIN14_V			(1 << 26)
+#define	PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET		24
+#define	PINCTRL_DRIVE13_BANK3_PIN13_V			(1 << 22)
+#define	PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET		20
+#define	PINCTRL_DRIVE13_BANK3_PIN12_V			(1 << 18)
+#define	PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET		16
+#define	PINCTRL_DRIVE13_BANK3_PIN11_V			(1 << 14)
+#define	PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET		12
+#define	PINCTRL_DRIVE13_BANK3_PIN10_V			(1 << 10)
+#define	PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET		8
+#define	PINCTRL_DRIVE13_BANK3_PIN09_V			(1 << 6)
+#define	PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET		4
+#define	PINCTRL_DRIVE13_BANK3_PIN08_V			(1 << 2)
+#define	PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE14_BANK3_PIN23_V			(1 << 30)
+#define	PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET		28
+#define	PINCTRL_DRIVE14_BANK3_PIN22_V			(1 << 26)
+#define	PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET		24
+#define	PINCTRL_DRIVE14_BANK3_PIN21_V			(1 << 22)
+#define	PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET		20
+#define	PINCTRL_DRIVE14_BANK3_PIN20_V			(1 << 18)
+#define	PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET		16
+#define	PINCTRL_DRIVE14_BANK3_PIN18_V			(1 << 10)
+#define	PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET		8
+#define	PINCTRL_DRIVE14_BANK3_PIN17_V			(1 << 6)
+#define	PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET		4
+#define	PINCTRL_DRIVE14_BANK3_PIN16_V			(1 << 2)
+#define	PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE15_BANK3_PIN30_V			(1 << 26)
+#define	PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET		24
+#define	PINCTRL_DRIVE15_BANK3_PIN29_V			(1 << 22)
+#define	PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET		20
+#define	PINCTRL_DRIVE15_BANK3_PIN28_V			(1 << 18)
+#define	PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET		16
+#define	PINCTRL_DRIVE15_BANK3_PIN27_V			(1 << 14)
+#define	PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET		12
+#define	PINCTRL_DRIVE15_BANK3_PIN26_V			(1 << 10)
+#define	PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET		8
+#define	PINCTRL_DRIVE15_BANK3_PIN25_V			(1 << 6)
+#define	PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET		4
+#define	PINCTRL_DRIVE15_BANK3_PIN24_V			(1 << 2)
+#define	PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE16_BANK4_PIN07_V			(1 << 30)
+#define	PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET		28
+#define	PINCTRL_DRIVE16_BANK4_PIN06_V			(1 << 26)
+#define	PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET		24
+#define	PINCTRL_DRIVE16_BANK4_PIN05_V			(1 << 22)
+#define	PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET		20
+#define	PINCTRL_DRIVE16_BANK4_PIN04_V			(1 << 18)
+#define	PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET		16
+#define	PINCTRL_DRIVE16_BANK4_PIN03_V			(1 << 14)
+#define	PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET		12
+#define	PINCTRL_DRIVE16_BANK4_PIN02_V			(1 << 10)
+#define	PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET		8
+#define	PINCTRL_DRIVE16_BANK4_PIN01_V			(1 << 6)
+#define	PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET		4
+#define	PINCTRL_DRIVE16_BANK4_PIN00_V			(1 << 2)
+#define	PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE17_BANK4_PIN15_V			(1 << 30)
+#define	PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET		28
+#define	PINCTRL_DRIVE17_BANK4_PIN14_V			(1 << 26)
+#define	PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET		24
+#define	PINCTRL_DRIVE17_BANK4_PIN13_V			(1 << 22)
+#define	PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET		20
+#define	PINCTRL_DRIVE17_BANK4_PIN12_V			(1 << 18)
+#define	PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET		16
+#define	PINCTRL_DRIVE17_BANK4_PIN11_V			(1 << 14)
+#define	PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET		12
+#define	PINCTRL_DRIVE17_BANK4_PIN10_V			(1 << 10)
+#define	PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET		8
+#define	PINCTRL_DRIVE17_BANK4_PIN09_V			(1 << 6)
+#define	PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET		4
+#define	PINCTRL_DRIVE17_BANK4_PIN08_V			(1 << 2)
+#define	PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE18_BANK4_PIN20_V			(1 << 18)
+#define	PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET		16
+#define	PINCTRL_DRIVE18_BANK4_PIN16_V			(1 << 2)
+#define	PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET		0
+
+#define	PINCTRL_PULL0_BANK0_PIN28			(1 << 28)
+#define	PINCTRL_PULL0_BANK0_PIN27			(1 << 27)
+#define	PINCTRL_PULL0_BANK0_PIN26			(1 << 26)
+#define	PINCTRL_PULL0_BANK0_PIN25			(1 << 25)
+#define	PINCTRL_PULL0_BANK0_PIN24			(1 << 24)
+#define	PINCTRL_PULL0_BANK0_PIN23			(1 << 23)
+#define	PINCTRL_PULL0_BANK0_PIN22			(1 << 22)
+#define	PINCTRL_PULL0_BANK0_PIN21			(1 << 21)
+#define	PINCTRL_PULL0_BANK0_PIN20			(1 << 20)
+#define	PINCTRL_PULL0_BANK0_PIN19			(1 << 19)
+#define	PINCTRL_PULL0_BANK0_PIN18			(1 << 18)
+#define	PINCTRL_PULL0_BANK0_PIN17			(1 << 17)
+#define	PINCTRL_PULL0_BANK0_PIN16			(1 << 16)
+#define	PINCTRL_PULL0_BANK0_PIN07			(1 << 7)
+#define	PINCTRL_PULL0_BANK0_PIN06			(1 << 6)
+#define	PINCTRL_PULL0_BANK0_PIN05			(1 << 5)
+#define	PINCTRL_PULL0_BANK0_PIN04			(1 << 4)
+#define	PINCTRL_PULL0_BANK0_PIN03			(1 << 3)
+#define	PINCTRL_PULL0_BANK0_PIN02			(1 << 2)
+#define	PINCTRL_PULL0_BANK0_PIN01			(1 << 1)
+#define	PINCTRL_PULL0_BANK0_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL1_BANK1_PIN31			(1 << 31)
+#define	PINCTRL_PULL1_BANK1_PIN30			(1 << 30)
+#define	PINCTRL_PULL1_BANK1_PIN29			(1 << 29)
+#define	PINCTRL_PULL1_BANK1_PIN28			(1 << 28)
+#define	PINCTRL_PULL1_BANK1_PIN27			(1 << 27)
+#define	PINCTRL_PULL1_BANK1_PIN26			(1 << 26)
+#define	PINCTRL_PULL1_BANK1_PIN25			(1 << 25)
+#define	PINCTRL_PULL1_BANK1_PIN24			(1 << 24)
+#define	PINCTRL_PULL1_BANK1_PIN23			(1 << 23)
+#define	PINCTRL_PULL1_BANK1_PIN22			(1 << 22)
+#define	PINCTRL_PULL1_BANK1_PIN21			(1 << 21)
+#define	PINCTRL_PULL1_BANK1_PIN20			(1 << 20)
+#define	PINCTRL_PULL1_BANK1_PIN19			(1 << 19)
+#define	PINCTRL_PULL1_BANK1_PIN18			(1 << 18)
+#define	PINCTRL_PULL1_BANK1_PIN17			(1 << 17)
+#define	PINCTRL_PULL1_BANK1_PIN16			(1 << 16)
+#define	PINCTRL_PULL1_BANK1_PIN15			(1 << 15)
+#define	PINCTRL_PULL1_BANK1_PIN14			(1 << 14)
+#define	PINCTRL_PULL1_BANK1_PIN13			(1 << 13)
+#define	PINCTRL_PULL1_BANK1_PIN12			(1 << 12)
+#define	PINCTRL_PULL1_BANK1_PIN11			(1 << 11)
+#define	PINCTRL_PULL1_BANK1_PIN10			(1 << 10)
+#define	PINCTRL_PULL1_BANK1_PIN09			(1 << 9)
+#define	PINCTRL_PULL1_BANK1_PIN08			(1 << 8)
+#define	PINCTRL_PULL1_BANK1_PIN07			(1 << 7)
+#define	PINCTRL_PULL1_BANK1_PIN06			(1 << 6)
+#define	PINCTRL_PULL1_BANK1_PIN05			(1 << 5)
+#define	PINCTRL_PULL1_BANK1_PIN04			(1 << 4)
+#define	PINCTRL_PULL1_BANK1_PIN03			(1 << 3)
+#define	PINCTRL_PULL1_BANK1_PIN02			(1 << 2)
+#define	PINCTRL_PULL1_BANK1_PIN01			(1 << 1)
+#define	PINCTRL_PULL1_BANK1_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL2_BANK2_PIN27			(1 << 27)
+#define	PINCTRL_PULL2_BANK2_PIN26			(1 << 26)
+#define	PINCTRL_PULL2_BANK2_PIN25			(1 << 25)
+#define	PINCTRL_PULL2_BANK2_PIN24			(1 << 24)
+#define	PINCTRL_PULL2_BANK2_PIN21			(1 << 21)
+#define	PINCTRL_PULL2_BANK2_PIN20			(1 << 20)
+#define	PINCTRL_PULL2_BANK2_PIN19			(1 << 19)
+#define	PINCTRL_PULL2_BANK2_PIN18			(1 << 18)
+#define	PINCTRL_PULL2_BANK2_PIN17			(1 << 17)
+#define	PINCTRL_PULL2_BANK2_PIN16			(1 << 16)
+#define	PINCTRL_PULL2_BANK2_PIN15			(1 << 15)
+#define	PINCTRL_PULL2_BANK2_PIN14			(1 << 14)
+#define	PINCTRL_PULL2_BANK2_PIN13			(1 << 13)
+#define	PINCTRL_PULL2_BANK2_PIN12			(1 << 12)
+#define	PINCTRL_PULL2_BANK2_PIN10			(1 << 10)
+#define	PINCTRL_PULL2_BANK2_PIN09			(1 << 9)
+#define	PINCTRL_PULL2_BANK2_PIN08			(1 << 8)
+#define	PINCTRL_PULL2_BANK2_PIN07			(1 << 7)
+#define	PINCTRL_PULL2_BANK2_PIN06			(1 << 6)
+#define	PINCTRL_PULL2_BANK2_PIN05			(1 << 5)
+#define	PINCTRL_PULL2_BANK2_PIN04			(1 << 4)
+#define	PINCTRL_PULL2_BANK2_PIN03			(1 << 3)
+#define	PINCTRL_PULL2_BANK2_PIN02			(1 << 2)
+#define	PINCTRL_PULL2_BANK2_PIN01			(1 << 1)
+#define	PINCTRL_PULL2_BANK2_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL3_BANK3_PIN30			(1 << 30)
+#define	PINCTRL_PULL3_BANK3_PIN29			(1 << 29)
+#define	PINCTRL_PULL3_BANK3_PIN28			(1 << 28)
+#define	PINCTRL_PULL3_BANK3_PIN27			(1 << 27)
+#define	PINCTRL_PULL3_BANK3_PIN26			(1 << 26)
+#define	PINCTRL_PULL3_BANK3_PIN25			(1 << 25)
+#define	PINCTRL_PULL3_BANK3_PIN24			(1 << 24)
+#define	PINCTRL_PULL3_BANK3_PIN23			(1 << 23)
+#define	PINCTRL_PULL3_BANK3_PIN22			(1 << 22)
+#define	PINCTRL_PULL3_BANK3_PIN21			(1 << 21)
+#define	PINCTRL_PULL3_BANK3_PIN20			(1 << 20)
+#define	PINCTRL_PULL3_BANK3_PIN18			(1 << 18)
+#define	PINCTRL_PULL3_BANK3_PIN17			(1 << 17)
+#define	PINCTRL_PULL3_BANK3_PIN16			(1 << 16)
+#define	PINCTRL_PULL3_BANK3_PIN15			(1 << 15)
+#define	PINCTRL_PULL3_BANK3_PIN14			(1 << 14)
+#define	PINCTRL_PULL3_BANK3_PIN13			(1 << 13)
+#define	PINCTRL_PULL3_BANK3_PIN12			(1 << 12)
+#define	PINCTRL_PULL3_BANK3_PIN11			(1 << 11)
+#define	PINCTRL_PULL3_BANK3_PIN10			(1 << 10)
+#define	PINCTRL_PULL3_BANK3_PIN09			(1 << 9)
+#define	PINCTRL_PULL3_BANK3_PIN08			(1 << 8)
+#define	PINCTRL_PULL3_BANK3_PIN07			(1 << 7)
+#define	PINCTRL_PULL3_BANK3_PIN06			(1 << 6)
+#define	PINCTRL_PULL3_BANK3_PIN05			(1 << 5)
+#define	PINCTRL_PULL3_BANK3_PIN04			(1 << 4)
+#define	PINCTRL_PULL3_BANK3_PIN03			(1 << 3)
+#define	PINCTRL_PULL3_BANK3_PIN02			(1 << 2)
+#define	PINCTRL_PULL3_BANK3_PIN01			(1 << 1)
+#define	PINCTRL_PULL3_BANK3_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL4_BANK4_PIN20			(1 << 20)
+#define	PINCTRL_PULL4_BANK4_PIN16			(1 << 16)
+#define	PINCTRL_PULL4_BANK4_PIN15			(1 << 15)
+#define	PINCTRL_PULL4_BANK4_PIN14			(1 << 14)
+#define	PINCTRL_PULL4_BANK4_PIN13			(1 << 13)
+#define	PINCTRL_PULL4_BANK4_PIN12			(1 << 12)
+#define	PINCTRL_PULL4_BANK4_PIN11			(1 << 11)
+#define	PINCTRL_PULL4_BANK4_PIN10			(1 << 10)
+#define	PINCTRL_PULL4_BANK4_PIN09			(1 << 9)
+#define	PINCTRL_PULL4_BANK4_PIN08			(1 << 8)
+#define	PINCTRL_PULL4_BANK4_PIN07			(1 << 7)
+#define	PINCTRL_PULL4_BANK4_PIN06			(1 << 6)
+#define	PINCTRL_PULL4_BANK4_PIN05			(1 << 5)
+#define	PINCTRL_PULL4_BANK4_PIN04			(1 << 4)
+#define	PINCTRL_PULL4_BANK4_PIN03			(1 << 3)
+#define	PINCTRL_PULL4_BANK4_PIN02			(1 << 2)
+#define	PINCTRL_PULL4_BANK4_PIN01			(1 << 1)
+#define	PINCTRL_PULL4_BANK4_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL5_BANK5_PIN26			(1 << 26)
+#define	PINCTRL_PULL5_BANK5_PIN23			(1 << 23)
+#define	PINCTRL_PULL5_BANK5_PIN22			(1 << 22)
+#define	PINCTRL_PULL5_BANK5_PIN21			(1 << 21)
+#define	PINCTRL_PULL5_BANK5_PIN20			(1 << 20)
+#define	PINCTRL_PULL5_BANK5_PIN19			(1 << 19)
+#define	PINCTRL_PULL5_BANK5_PIN18			(1 << 18)
+#define	PINCTRL_PULL5_BANK5_PIN17			(1 << 17)
+#define	PINCTRL_PULL5_BANK5_PIN16			(1 << 16)
+#define	PINCTRL_PULL5_BANK5_PIN15			(1 << 15)
+#define	PINCTRL_PULL5_BANK5_PIN14			(1 << 14)
+#define	PINCTRL_PULL5_BANK5_PIN13			(1 << 13)
+#define	PINCTRL_PULL5_BANK5_PIN12			(1 << 12)
+#define	PINCTRL_PULL5_BANK5_PIN11			(1 << 11)
+#define	PINCTRL_PULL5_BANK5_PIN10			(1 << 10)
+#define	PINCTRL_PULL5_BANK5_PIN09			(1 << 9)
+#define	PINCTRL_PULL5_BANK5_PIN08			(1 << 8)
+#define	PINCTRL_PULL5_BANK5_PIN07			(1 << 7)
+#define	PINCTRL_PULL5_BANK5_PIN06			(1 << 6)
+#define	PINCTRL_PULL5_BANK5_PIN05			(1 << 5)
+#define	PINCTRL_PULL5_BANK5_PIN04			(1 << 4)
+#define	PINCTRL_PULL5_BANK5_PIN03			(1 << 3)
+#define	PINCTRL_PULL5_BANK5_PIN02			(1 << 2)
+#define	PINCTRL_PULL5_BANK5_PIN01			(1 << 1)
+#define	PINCTRL_PULL5_BANK5_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL6_BANK6_PIN24			(1 << 24)
+#define	PINCTRL_PULL6_BANK6_PIN23			(1 << 23)
+#define	PINCTRL_PULL6_BANK6_PIN22			(1 << 22)
+#define	PINCTRL_PULL6_BANK6_PIN21			(1 << 21)
+#define	PINCTRL_PULL6_BANK6_PIN20			(1 << 20)
+#define	PINCTRL_PULL6_BANK6_PIN19			(1 << 19)
+#define	PINCTRL_PULL6_BANK6_PIN18			(1 << 18)
+#define	PINCTRL_PULL6_BANK6_PIN17			(1 << 17)
+#define	PINCTRL_PULL6_BANK6_PIN16			(1 << 16)
+#define	PINCTRL_PULL6_BANK6_PIN14			(1 << 14)
+#define	PINCTRL_PULL6_BANK6_PIN13			(1 << 13)
+#define	PINCTRL_PULL6_BANK6_PIN12			(1 << 12)
+#define	PINCTRL_PULL6_BANK6_PIN11			(1 << 11)
+#define	PINCTRL_PULL6_BANK6_PIN10			(1 << 10)
+#define	PINCTRL_PULL6_BANK6_PIN09			(1 << 9)
+#define	PINCTRL_PULL6_BANK6_PIN08			(1 << 8)
+#define	PINCTRL_PULL6_BANK6_PIN07			(1 << 7)
+#define	PINCTRL_PULL6_BANK6_PIN06			(1 << 6)
+#define	PINCTRL_PULL6_BANK6_PIN05			(1 << 5)
+#define	PINCTRL_PULL6_BANK6_PIN04			(1 << 4)
+#define	PINCTRL_PULL6_BANK6_PIN03			(1 << 3)
+#define	PINCTRL_PULL6_BANK6_PIN02			(1 << 2)
+#define	PINCTRL_PULL6_BANK6_PIN01			(1 << 1)
+#define	PINCTRL_PULL6_BANK6_PIN00			(1 << 0)
+
+#define	PINCTRL_DOUT0_DOUT_MASK				0x1fffffff
+#define	PINCTRL_DOUT0_DOUT_OFFSET			0
+
+#define	PINCTRL_DOUT1_DOUT_MASK				0xffffffff
+#define	PINCTRL_DOUT1_DOUT_OFFSET			0
+
+#define	PINCTRL_DOUT2_DOUT_MASK				0xfffffff
+#define	PINCTRL_DOUT2_DOUT_OFFSET			0
+
+#define	PINCTRL_DOUT3_DOUT_MASK				0x7fffffff
+#define	PINCTRL_DOUT3_DOUT_OFFSET			0
+
+#define	PINCTRL_DOUT4_DOUT_MASK				0x1fffff
+#define	PINCTRL_DOUT4_DOUT_OFFSET			0
+
+#define	PINCTRL_DIN0_DIN_MASK				0x1fffffff
+#define	PINCTRL_DIN0_DIN_OFFSET				0
+
+#define	PINCTRL_DIN1_DIN_MASK				0xffffffff
+#define	PINCTRL_DIN1_DIN_OFFSET				0
+
+#define	PINCTRL_DIN2_DIN_MASK				0xfffffff
+#define	PINCTRL_DIN2_DIN_OFFSET				0
+
+#define	PINCTRL_DIN3_DIN_MASK				0x7fffffff
+#define	PINCTRL_DIN3_DIN_OFFSET				0
+
+#define	PINCTRL_DIN4_DIN_MASK				0x1fffff
+#define	PINCTRL_DIN4_DIN_OFFSET				0
+
+#define	PINCTRL_DOE0_DOE_MASK				0x1fffffff
+#define	PINCTRL_DOE0_DOE_OFFSET				0
+
+#define	PINCTRL_DOE1_DOE_MASK				0xffffffff
+#define	PINCTRL_DOE1_DOE_OFFSET				0
+
+#define	PINCTRL_DOE2_DOE_MASK				0xfffffff
+#define	PINCTRL_DOE2_DOE_OFFSET				0
+
+#define	PINCTRL_DOE3_DOE_MASK				0x7fffffff
+#define	PINCTRL_DOE3_DOE_OFFSET				0
+
+#define	PINCTRL_DOE4_DOE_MASK				0x1fffff
+#define	PINCTRL_DOE4_DOE_OFFSET				0
+
+#define	PINCTRL_PIN2IRQ0_PIN2IRQ_MASK			0x1fffffff
+#define	PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET			0
+
+#define	PINCTRL_PIN2IRQ1_PIN2IRQ_MASK			0xffffffff
+#define	PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET			0
+
+#define	PINCTRL_PIN2IRQ2_PIN2IRQ_MASK			0xfffffff
+#define	PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET			0
+
+#define	PINCTRL_PIN2IRQ3_PIN2IRQ_MASK			0x7fffffff
+#define	PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET			0
+
+#define	PINCTRL_PIN2IRQ4_PIN2IRQ_MASK			0x1fffff
+#define	PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET			0
+
+#define	PINCTRL_IRQEN0_IRQEN_MASK			0x1fffffff
+#define	PINCTRL_IRQEN0_IRQEN_OFFSET			0
+
+#define	PINCTRL_IRQEN1_IRQEN_MASK			0xffffffff
+#define	PINCTRL_IRQEN1_IRQEN_OFFSET			0
+
+#define	PINCTRL_IRQEN2_IRQEN_MASK			0xfffffff
+#define	PINCTRL_IRQEN2_IRQEN_OFFSET			0
+
+#define	PINCTRL_IRQEN3_IRQEN_MASK			0x7fffffff
+#define	PINCTRL_IRQEN3_IRQEN_OFFSET			0
+
+#define	PINCTRL_IRQEN4_IRQEN_MASK			0x1fffff
+#define	PINCTRL_IRQEN4_IRQEN_OFFSET			0
+
+#define	PINCTRL_IRQLEVEL0_IRQLEVEL_MASK			0x1fffffff
+#define	PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET		0
+
+#define	PINCTRL_IRQLEVEL1_IRQLEVEL_MASK			0xffffffff
+#define	PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET		0
+
+#define	PINCTRL_IRQLEVEL2_IRQLEVEL_MASK			0xfffffff
+#define	PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET		0
+
+#define	PINCTRL_IRQLEVEL3_IRQLEVEL_MASK			0x7fffffff
+#define	PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET		0
+
+#define	PINCTRL_IRQLEVEL4_IRQLEVEL_MASK			0x1fffff
+#define	PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET		0
+
+#define	PINCTRL_IRQPOL0_IRQPOL_MASK			0x1fffffff
+#define	PINCTRL_IRQPOL0_IRQPOL_OFFSET			0
+
+#define	PINCTRL_IRQPOL1_IRQPOL_MASK			0xffffffff
+#define	PINCTRL_IRQPOL1_IRQPOL_OFFSET			0
+
+#define	PINCTRL_IRQPOL2_IRQPOL_MASK			0xfffffff
+#define	PINCTRL_IRQPOL2_IRQPOL_OFFSET			0
+
+#define	PINCTRL_IRQPOL3_IRQPOL_MASK			0x7fffffff
+#define	PINCTRL_IRQPOL3_IRQPOL_OFFSET			0
+
+#define	PINCTRL_IRQPOL4_IRQPOL_MASK			0x1fffff
+#define	PINCTRL_IRQPOL4_IRQPOL_OFFSET			0
+
+#define	PINCTRL_IRQSTAT0_IRQSTAT_MASK			0x1fffffff
+#define	PINCTRL_IRQSTAT0_IRQSTAT_OFFSET			0
+
+#define	PINCTRL_IRQSTAT1_IRQSTAT_MASK			0xffffffff
+#define	PINCTRL_IRQSTAT1_IRQSTAT_OFFSET			0
+
+#define	PINCTRL_IRQSTAT2_IRQSTAT_MASK			0xfffffff
+#define	PINCTRL_IRQSTAT2_IRQSTAT_OFFSET			0
+
+#define	PINCTRL_IRQSTAT3_IRQSTAT_MASK			0x7fffffff
+#define	PINCTRL_IRQSTAT3_IRQSTAT_OFFSET			0
+
+#define	PINCTRL_IRQSTAT4_IRQSTAT_MASK			0x1fffff
+#define	PINCTRL_IRQSTAT4_IRQSTAT_OFFSET			0
+
+#define	PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK		(0x3 << 26)
+#define	PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET	26
+#define	PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK		(0x3 << 24)
+#define	PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET	24
+#define	PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK		(0x3 << 22)
+#define	PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET	22
+#define	PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK		(0x3 << 20)
+#define	PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET	20
+#define	PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK		(0x3 << 18)
+#define	PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET	18
+#define	PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK		(0x3 << 16)
+#define	PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET	16
+#define	PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK		(0x3 << 14)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET	14
+#define	PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK		(0x3 << 12)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET	12
+#define	PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK		(0x3 << 10)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET	10
+#define	PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK		(0x3 << 8)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET	8
+#define	PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK		(0x3 << 6)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET	6
+#define	PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK		(0x3 << 4)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET	4
+#define	PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK		(0x3 << 2)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET	2
+#define	PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK		(0x3 << 0)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET	0
+
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK		(0x3 << 16)
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET		16
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR		(0x0 << 16)
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO		(0x1 << 16)
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2		(0x2 << 16)
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2		(0x3 << 16)
+#define	PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK		(0x3 << 12)
+#define	PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET		12
+#define	PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK		(0x3 << 10)
+#define	PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET		10
+#define	PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK		(0x3 << 8)
+#define	PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET		8
+#define	PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK		(0x3 << 6)
+#define	PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET		6
+#define	PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK		(0x3 << 4)
+#define	PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET		4
+#define	PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK		(0x3 << 2)
+#define	PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET		2
+#define	PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK		(0x3 << 0)
+#define	PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET		0
+
+#endif /* __MX28_REGS_PINCTRL_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
new file mode 100644
index 000000000..ce2f425c1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
@@ -0,0 +1,345 @@
+/*
+ * Freescale i.MX23 Power Controller Register Definitions
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX23_REGS_POWER_H__
+#define __MX23_REGS_POWER_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_power_regs {
+	mxs_reg_32(hw_power_ctrl)
+	mxs_reg_32(hw_power_5vctrl)
+	mxs_reg_32(hw_power_minpwr)
+	mxs_reg_32(hw_power_charge)
+	uint32_t	hw_power_vdddctrl;
+	uint32_t	reserved_vddd[3];
+	uint32_t	hw_power_vddactrl;
+	uint32_t	reserved_vdda[3];
+	uint32_t	hw_power_vddioctrl;
+	uint32_t	reserved_vddio[3];
+	uint32_t	hw_power_vddmemctrl;
+	uint32_t	reserved_vddmem[3];
+	uint32_t	hw_power_dcdc4p2;
+	uint32_t	reserved_dcdc4p2[3];
+	uint32_t	hw_power_misc;
+	uint32_t	reserved_misc[3];
+	uint32_t	hw_power_dclimits;
+	uint32_t	reserved_dclimits[3];
+	mxs_reg_32(hw_power_loopctrl)
+	uint32_t	hw_power_sts;
+	uint32_t	reserved_sts[3];
+	mxs_reg_32(hw_power_speed)
+	uint32_t	hw_power_battmonitor;
+	uint32_t	reserved_battmonitor[3];
+
+	uint32_t	reserved1[4];
+
+	mxs_reg_32(hw_power_reset)
+
+	uint32_t	reserved2[4];
+
+	mxs_reg_32(hw_power_special)
+	mxs_reg_32(hw_power_version)
+};
+#endif
+
+#define	POWER_CTRL_CLKGATE				(1 << 30)
+#define	POWER_CTRL_PSWITCH_MID_TRAN			(1 << 27)
+#define	POWER_CTRL_DCDC4P2_BO_IRQ			(1 << 24)
+#define	POWER_CTRL_ENIRQ_DCDC4P2_BO			(1 << 23)
+#define	POWER_CTRL_VDD5V_DROOP_IRQ			(1 << 22)
+#define	POWER_CTRL_ENIRQ_VDD5V_DROOP			(1 << 21)
+#define	POWER_CTRL_PSWITCH_IRQ				(1 << 20)
+#define	POWER_CTRL_PSWITCH_IRQ_SRC			(1 << 19)
+#define	POWER_CTRL_POLARITY_PSWITCH			(1 << 18)
+#define	POWER_CTRL_ENIRQ_PSWITCH			(1 << 17)
+#define	POWER_CTRL_POLARITY_DC_OK			(1 << 16)
+#define	POWER_CTRL_DC_OK_IRQ				(1 << 15)
+#define	POWER_CTRL_ENIRQ_DC_OK				(1 << 14)
+#define	POWER_CTRL_BATT_BO_IRQ				(1 << 13)
+#define	POWER_CTRL_ENIRQ_BATT_BO			(1 << 12)
+#define	POWER_CTRL_VDDIO_BO_IRQ				(1 << 11)
+#define	POWER_CTRL_ENIRQ_VDDIO_BO			(1 << 10)
+#define	POWER_CTRL_VDDA_BO_IRQ				(1 << 9)
+#define	POWER_CTRL_ENIRQ_VDDA_BO			(1 << 8)
+#define	POWER_CTRL_VDDD_BO_IRQ				(1 << 7)
+#define	POWER_CTRL_ENIRQ_VDDD_BO			(1 << 6)
+#define	POWER_CTRL_POLARITY_VBUSVALID			(1 << 5)
+#define	POWER_CTRL_VBUS_VALID_IRQ			(1 << 4)
+#define	POWER_CTRL_ENIRQ_VBUS_VALID			(1 << 3)
+#define	POWER_CTRL_POLARITY_VDD5V_GT_VDDIO		(1 << 2)
+#define	POWER_CTRL_VDD5V_GT_VDDIO_IRQ			(1 << 1)
+#define	POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO			(1 << 0)
+
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		28
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V3			(0x0 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V4			(0x1 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V5			(0x2 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V7			(0x3 << 28)
+#define	POWER_5VCTRL_HEADROOM_ADJ_MASK			(0x7 << 24)
+#define	POWER_5VCTRL_HEADROOM_ADJ_OFFSET		24
+#define	POWER_5VCTRL_PWD_CHARGE_4P2_MASK		(0x1 << 20)
+#define	POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET		20
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK		(0x3f << 12)
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET		12
+#define	POWER_5VCTRL_VBUSVALID_TRSH_MASK		(0x7 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_OFFSET		8
+#define	POWER_5VCTRL_VBUSVALID_TRSH_2V9			(0x0 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V0			(0x1 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V1			(0x2 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V2			(0x3 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V3			(0x4 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V4			(0x5 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V5			(0x6 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V6			(0x7 << 8)
+#define	POWER_5VCTRL_PWDN_5VBRNOUT			(1 << 7)
+#define	POWER_5VCTRL_ENABLE_LINREG_ILIMIT		(1 << 6)
+#define	POWER_5VCTRL_DCDC_XFER				(1 << 5)
+#define	POWER_5VCTRL_VBUSVALID_5VDETECT			(1 << 4)
+#define	POWER_5VCTRL_VBUSVALID_TO_B			(1 << 3)
+#define	POWER_5VCTRL_ILIMIT_EQ_ZERO			(1 << 2)
+#define	POWER_5VCTRL_PWRUP_VBUS_CMPS			(1 << 1)
+#define	POWER_5VCTRL_ENABLE_DCDC			(1 << 0)
+
+#define	POWER_MINPWR_LOWPWR_4P2				(1 << 14)
+#define	POWER_MINPWR_VDAC_DUMP_CTRL			(1 << 13)
+#define	POWER_MINPWR_PWD_BO				(1 << 12)
+#define	POWER_MINPWR_USE_VDDXTAL_VBG			(1 << 11)
+#define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
+#define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
+#define	POWER_MINPWR_SELECT_OSC				(1 << 8)
+#define	POWER_MINPWR_VBG_OFF				(1 << 7)
+#define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
+#define	POWER_MINPWR_HALFFETS				(1 << 5)
+#define	POWER_MINPWR_LESSANA_I				(1 << 4)
+#define	POWER_MINPWR_PWD_XTAL24				(1 << 3)
+#define	POWER_MINPWR_DC_STOPCLK				(1 << 2)
+#define	POWER_MINPWR_EN_DC_PFM				(1 << 1)
+#define	POWER_MINPWR_DC_HALFCLK				(1 << 0)
+
+#define	POWER_CHARGE_ADJ_VOLT_MASK			(0x7 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_OFFSET			24
+#define	POWER_CHARGE_ADJ_VOLT_M025P			(0x1 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P050P			(0x2 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M075P			(0x3 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P025P			(0x4 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M050P			(0x5 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P075P			(0x6 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M100P			(0x7 << 24)
+#define	POWER_CHARGE_ENABLE_LOAD			(1 << 22)
+#define	POWER_CHARGE_ENABLE_CHARGER_RESISTORS		(1 << 21)
+#define	POWER_CHARGE_ENABLE_FAULT_DETECT		(1 << 20)
+#define	POWER_CHARGE_CHRG_STS_OFF			(1 << 19)
+#define	POWER_CHARGE_USE_EXTERN_R			(1 << 17)
+#define	POWER_CHARGE_PWD_BATTCHRG			(1 << 16)
+#define	POWER_CHARGE_STOP_ILIMIT_MASK			(0xf << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_OFFSET			8
+#define	POWER_CHARGE_STOP_ILIMIT_10MA			(0x1 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_20MA			(0x2 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_50MA			(0x4 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_100MA			(0x8 << 8)
+#define	POWER_CHARGE_BATTCHRG_I_MASK			0x3f
+#define	POWER_CHARGE_BATTCHRG_I_OFFSET			0
+#define	POWER_CHARGE_BATTCHRG_I_10MA			0x01
+#define	POWER_CHARGE_BATTCHRG_I_20MA			0x02
+#define	POWER_CHARGE_BATTCHRG_I_50MA			0x04
+#define	POWER_CHARGE_BATTCHRG_I_100MA			0x08
+#define	POWER_CHARGE_BATTCHRG_I_200MA			0x10
+#define	POWER_CHARGE_BATTCHRG_I_400MA			0x20
+
+#define	POWER_VDDDCTRL_ADJTN_MASK			(0xf << 28)
+#define	POWER_VDDDCTRL_ADJTN_OFFSET			28
+#define	POWER_VDDDCTRL_PWDN_BRNOUT			(1 << 23)
+#define	POWER_VDDDCTRL_DISABLE_STEPPING			(1 << 22)
+#define	POWER_VDDDCTRL_ENABLE_LINREG			(1 << 21)
+#define	POWER_VDDDCTRL_DISABLE_FET			(1 << 20)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_MASK		(0x3 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_OFFSET		16
+#define	POWER_VDDDCTRL_LINREG_OFFSET_0STEPS		(0x0 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 16)
+#define	POWER_VDDDCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDDCTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDDCTRL_TRG_MASK				0x1f
+#define	POWER_VDDDCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDACTRL_PWDN_BRNOUT			(1 << 19)
+#define	POWER_VDDACTRL_DISABLE_STEPPING			(1 << 18)
+#define	POWER_VDDACTRL_ENABLE_LINREG			(1 << 17)
+#define	POWER_VDDACTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDACTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDACTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDACTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDACTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDACTRL_TRG_MASK				0x1f
+#define	POWER_VDDACTRL_TRG_OFFSET			0
+
+#define	POWER_VDDIOCTRL_ADJTN_MASK			(0xf << 20)
+#define	POWER_VDDIOCTRL_ADJTN_OFFSET			20
+#define	POWER_VDDIOCTRL_PWDN_BRNOUT			(1 << 18)
+#define	POWER_VDDIOCTRL_DISABLE_STEPPING		(1 << 17)
+#define	POWER_VDDIOCTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDIOCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDIOCTRL_BO_OFFSET_OFFSET		8
+#define	POWER_VDDIOCTRL_TRG_MASK			0x1f
+#define	POWER_VDDIOCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDMEMCTRL_PULLDOWN_ACTIVE		(1 << 10)
+#define	POWER_VDDMEMCTRL_ENABLE_ILIMIT			(1 << 9)
+#define	POWER_VDDMEMCTRL_ENABLE_LINREG			(1 << 8)
+#define	POWER_VDDMEMCTRL_TRG_MASK			0x1f
+#define	POWER_VDDMEMCTRL_TRG_OFFSET			0
+
+#define	POWER_DCDC4P2_DROPOUT_CTRL_MASK			(0xf << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_OFFSET		28
+#define	POWER_DCDC4P2_DROPOUT_CTRL_200MV		(0x3 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_100MV		(0x2 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_50MV			(0x1 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_25MV			(0x0 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2		(0x0 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT	(0x1 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL		(0x2 << 28)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_MASK		(0x3 << 24)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_OFFSET		24
+#define	POWER_DCDC4P2_ENABLE_4P2			(1 << 23)
+#define	POWER_DCDC4P2_ENABLE_DCDC			(1 << 22)
+#define	POWER_DCDC4P2_HYST_DIR				(1 << 21)
+#define	POWER_DCDC4P2_HYST_THRESH			(1 << 20)
+#define	POWER_DCDC4P2_TRG_MASK				(0x7 << 16)
+#define	POWER_DCDC4P2_TRG_OFFSET			16
+#define	POWER_DCDC4P2_TRG_4V2				(0x0 << 16)
+#define	POWER_DCDC4P2_TRG_4V1				(0x1 << 16)
+#define	POWER_DCDC4P2_TRG_4V0				(0x2 << 16)
+#define	POWER_DCDC4P2_TRG_3V9				(0x3 << 16)
+#define	POWER_DCDC4P2_TRG_BATT				(0x4 << 16)
+#define	POWER_DCDC4P2_BO_MASK				(0x1f << 8)
+#define	POWER_DCDC4P2_BO_OFFSET				8
+#define	POWER_DCDC4P2_CMPTRIP_MASK			0x1f
+#define	POWER_DCDC4P2_CMPTRIP_OFFSET			0
+
+#define	POWER_MISC_FREQSEL_MASK				(0x7 << 4)
+#define	POWER_MISC_FREQSEL_OFFSET			4
+#define	POWER_MISC_FREQSEL_20MHZ			(0x1 << 4)
+#define	POWER_MISC_FREQSEL_24MHZ			(0x2 << 4)
+#define	POWER_MISC_FREQSEL_19MHZ			(0x3 << 4)
+#define	POWER_MISC_FREQSEL_14MHZ			(0x4 << 4)
+#define	POWER_MISC_FREQSEL_18MHZ			(0x5 << 4)
+#define	POWER_MISC_FREQSEL_21MHZ			(0x6 << 4)
+#define	POWER_MISC_FREQSEL_17MHZ			(0x7 << 4)
+#define	POWER_MISC_DISABLE_FET_BO_LOGIC			(1 << 3)
+#define	POWER_MISC_DELAY_TIMING				(1 << 2)
+#define	POWER_MISC_TEST					(1 << 1)
+#define	POWER_MISC_SEL_PLLCLK				(1 << 0)
+
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
+#define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
+#define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
+
+#define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
+#define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)
+#define	POWER_LOOPCTRL_EN_CM_HYST			(1 << 18)
+#define	POWER_LOOPCTRL_EN_DF_HYST			(1 << 17)
+#define	POWER_LOOPCTRL_CM_HYST_THRESH			(1 << 16)
+#define	POWER_LOOPCTRL_DF_HYST_THRESH			(1 << 15)
+#define	POWER_LOOPCTRL_RCSCALE_THRESH			(1 << 14)
+#define	POWER_LOOPCTRL_EN_RCSCALE_MASK			(0x3 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_OFFSET		12
+#define	POWER_LOOPCTRL_EN_RCSCALE_DIS			(0x0 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_2X			(0x1 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_4X			(0x2 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_8X			(0x3 << 12)
+#define	POWER_LOOPCTRL_DC_FF_MASK			(0x7 << 8)
+#define	POWER_LOOPCTRL_DC_FF_OFFSET			8
+#define	POWER_LOOPCTRL_DC_R_MASK			(0xf << 4)
+#define	POWER_LOOPCTRL_DC_R_OFFSET			4
+#define	POWER_LOOPCTRL_DC_C_MASK			0x3
+#define	POWER_LOOPCTRL_DC_C_OFFSET			0
+#define	POWER_LOOPCTRL_DC_C_MAX				0x0
+#define	POWER_LOOPCTRL_DC_C_2X				0x1
+#define	POWER_LOOPCTRL_DC_C_4X				0x2
+#define	POWER_LOOPCTRL_DC_C_MIN				0x3
+
+#define	POWER_STS_PWRUP_SOURCE_MASK			(0x3f << 24)
+#define	POWER_STS_PWRUP_SOURCE_OFFSET			24
+#define	POWER_STS_PWRUP_SOURCE_5V			(0x20 << 24)
+#define	POWER_STS_PWRUP_SOURCE_RTC			(0x10 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH		(0x02 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_MID		(0x01 << 24)
+#define	POWER_STS_PSWITCH_MASK				(0x3 << 20)
+#define	POWER_STS_PSWITCH_OFFSET			20
+#define	POWER_STS_AVALID0_STATUS			(1 << 17)
+#define	POWER_STS_BVALID0_STATUS			(1 << 16)
+#define	POWER_STS_VBUSVALID0_STATUS			(1 << 15)
+#define	POWER_STS_SESSEND0_STATUS			(1 << 14)
+#define	POWER_STS_BATT_BO				(1 << 13)
+#define	POWER_STS_VDD5V_FAULT				(1 << 12)
+#define	POWER_STS_CHRGSTS				(1 << 11)
+#define	POWER_STS_DCDC_4P2_BO				(1 << 10)
+#define	POWER_STS_DC_OK					(1 << 9)
+#define	POWER_STS_VDDIO_BO				(1 << 8)
+#define	POWER_STS_VDDA_BO				(1 << 7)
+#define	POWER_STS_VDDD_BO				(1 << 6)
+#define	POWER_STS_VDD5V_GT_VDDIO			(1 << 5)
+#define	POWER_STS_VDD5V_DROOP				(1 << 4)
+#define	POWER_STS_AVALID0				(1 << 3)
+#define	POWER_STS_BVALID0				(1 << 2)
+#define	POWER_STS_VBUSVALID0				(1 << 1)
+#define	POWER_STS_SESSEND0				(1 << 0)
+
+#define	POWER_SPEED_STATUS_MASK				(0xff << 16)
+#define	POWER_SPEED_STATUS_OFFSET			16
+#define	POWER_SPEED_CTRL_MASK				0x3
+#define	POWER_SPEED_CTRL_OFFSET				0
+#define	POWER_SPEED_CTRL_SS_OFF				0x0
+#define	POWER_SPEED_CTRL_SS_ON				0x1
+#define	POWER_SPEED_CTRL_SS_ENABLE			0x3
+
+#define	POWER_BATTMONITOR_BATT_VAL_MASK			(0x3ff << 16)
+#define	POWER_BATTMONITOR_BATT_VAL_OFFSET		16
+#define	POWER_BATTMONITOR_EN_BATADJ			(1 << 10)
+#define	POWER_BATTMONITOR_PWDN_BATTBRNOUT		(1 << 9)
+#define	POWER_BATTMONITOR_BRWNOUT_PWD			(1 << 8)
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_MASK		0x1f
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET		0
+
+#define	POWER_RESET_UNLOCK_MASK				(0xffff << 16)
+#define	POWER_RESET_UNLOCK_OFFSET			16
+#define	POWER_RESET_UNLOCK_KEY				(0x3e77 << 16)
+#define	POWER_RESET_PWD_OFF				(1 << 1)
+#define	POWER_RESET_PWD					(1 << 0)
+
+#define	POWER_DEBUG_VBUSVALIDPIOLOCK			(1 << 3)
+#define	POWER_DEBUG_AVALIDPIOLOCK			(1 << 2)
+#define	POWER_DEBUG_BVALIDPIOLOCK			(1 << 1)
+#define	POWER_DEBUG_SESSENDPIOLOCK			(1 << 0)
+
+#define	POWER_SPECIAL_TEST_MASK				0xffffffff
+#define	POWER_SPECIAL_TEST_OFFSET			0
+
+#define	POWER_VERSION_MAJOR_MASK			(0xff << 24)
+#define	POWER_VERSION_MAJOR_OFFSET			24
+#define	POWER_VERSION_MINOR_MASK			(0xff << 16)
+#define	POWER_VERSION_MINOR_OFFSET			16
+#define	POWER_VERSION_STEP_MASK				0xffff
+#define	POWER_VERSION_STEP_OFFSET			0
+
+#endif	/* __MX23_REGS_POWER_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx28.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx28.h
new file mode 100644
index 000000000..9528e3ce9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-power-mx28.h
@@ -0,0 +1,400 @@
+/*
+ * Freescale i.MX28 Power Controller Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_POWER_H__
+#define __MX28_REGS_POWER_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_power_regs {
+	mxs_reg_32(hw_power_ctrl)
+	mxs_reg_32(hw_power_5vctrl)
+	mxs_reg_32(hw_power_minpwr)
+	mxs_reg_32(hw_power_charge)
+	uint32_t	hw_power_vdddctrl;
+	uint32_t	reserved_vddd[3];
+	uint32_t	hw_power_vddactrl;
+	uint32_t	reserved_vdda[3];
+	uint32_t	hw_power_vddioctrl;
+	uint32_t	reserved_vddio[3];
+	uint32_t	hw_power_vddmemctrl;
+	uint32_t	reserved_vddmem[3];
+	uint32_t	hw_power_dcdc4p2;
+	uint32_t	reserved_dcdc4p2[3];
+	uint32_t	hw_power_misc;
+	uint32_t	reserved_misc[3];
+	uint32_t	hw_power_dclimits;
+	uint32_t	reserved_dclimits[3];
+	mxs_reg_32(hw_power_loopctrl)
+	uint32_t	hw_power_sts;
+	uint32_t	reserved_sts[3];
+	mxs_reg_32(hw_power_speed)
+	uint32_t	hw_power_battmonitor;
+	uint32_t	reserved_battmonitor[3];
+
+	uint32_t	reserved[4];
+
+	mxs_reg_32(hw_power_reset)
+	mxs_reg_32(hw_power_debug)
+	mxs_reg_32(hw_power_thermal)
+	mxs_reg_32(hw_power_usb1ctrl)
+	mxs_reg_32(hw_power_special)
+	mxs_reg_32(hw_power_version)
+	mxs_reg_32(hw_power_anaclkctrl)
+	mxs_reg_32(hw_power_refctrl)
+};
+#endif
+
+#define	POWER_CTRL_PSWITCH_MID_TRAN			(1 << 27)
+#define	POWER_CTRL_DCDC4P2_BO_IRQ			(1 << 24)
+#define	POWER_CTRL_ENIRQ_DCDC4P2_BO			(1 << 23)
+#define	POWER_CTRL_VDD5V_DROOP_IRQ			(1 << 22)
+#define	POWER_CTRL_ENIRQ_VDD5V_DROOP			(1 << 21)
+#define	POWER_CTRL_PSWITCH_IRQ				(1 << 20)
+#define	POWER_CTRL_PSWITCH_IRQ_SRC			(1 << 19)
+#define	POWER_CTRL_POLARITY_PSWITCH			(1 << 18)
+#define	POWER_CTRL_ENIRQ_PSWITCH			(1 << 17)
+#define	POWER_CTRL_POLARITY_DC_OK			(1 << 16)
+#define	POWER_CTRL_DC_OK_IRQ				(1 << 15)
+#define	POWER_CTRL_ENIRQ_DC_OK				(1 << 14)
+#define	POWER_CTRL_BATT_BO_IRQ				(1 << 13)
+#define	POWER_CTRL_ENIRQ_BATT_BO			(1 << 12)
+#define	POWER_CTRL_VDDIO_BO_IRQ				(1 << 11)
+#define	POWER_CTRL_ENIRQ_VDDIO_BO			(1 << 10)
+#define	POWER_CTRL_VDDA_BO_IRQ				(1 << 9)
+#define	POWER_CTRL_ENIRQ_VDDA_BO			(1 << 8)
+#define	POWER_CTRL_VDDD_BO_IRQ				(1 << 7)
+#define	POWER_CTRL_ENIRQ_VDDD_BO			(1 << 6)
+#define	POWER_CTRL_POLARITY_VBUSVALID			(1 << 5)
+#define	POWER_CTRL_VBUS_VALID_IRQ			(1 << 4)
+#define	POWER_CTRL_ENIRQ_VBUS_VALID			(1 << 3)
+#define	POWER_CTRL_POLARITY_VDD5V_GT_VDDIO		(1 << 2)
+#define	POWER_CTRL_VDD5V_GT_VDDIO_IRQ			(1 << 1)
+#define	POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO			(1 << 0)
+
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 30)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		30
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V3			(0x0 << 30)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V4			(0x1 << 30)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V5			(0x2 << 30)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V7			(0x3 << 30)
+#define	POWER_5VCTRL_HEADROOM_ADJ_MASK			(0x7 << 24)
+#define	POWER_5VCTRL_HEADROOM_ADJ_OFFSET		24
+#define	POWER_5VCTRL_PWD_CHARGE_4P2_MASK		(0x3 << 20)
+#define	POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET		20
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK		(0x3f << 12)
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET		12
+#define	POWER_5VCTRL_VBUSVALID_TRSH_MASK		(0x7 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_OFFSET		8
+#define	POWER_5VCTRL_VBUSVALID_TRSH_2V9			(0x0 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V0			(0x1 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V1			(0x2 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V2			(0x3 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V3			(0x4 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V4			(0x5 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V5			(0x6 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V6			(0x7 << 8)
+#define	POWER_5VCTRL_PWDN_5VBRNOUT			(1 << 7)
+#define	POWER_5VCTRL_ENABLE_LINREG_ILIMIT		(1 << 6)
+#define	POWER_5VCTRL_DCDC_XFER				(1 << 5)
+#define	POWER_5VCTRL_VBUSVALID_5VDETECT			(1 << 4)
+#define	POWER_5VCTRL_VBUSVALID_TO_B			(1 << 3)
+#define	POWER_5VCTRL_ILIMIT_EQ_ZERO			(1 << 2)
+#define	POWER_5VCTRL_PWRUP_VBUS_CMPS			(1 << 1)
+#define	POWER_5VCTRL_ENABLE_DCDC			(1 << 0)
+
+#define	POWER_MINPWR_LOWPWR_4P2				(1 << 14)
+#define	POWER_MINPWR_PWD_BO				(1 << 12)
+#define	POWER_MINPWR_USE_VDDXTAL_VBG			(1 << 11)
+#define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
+#define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
+#define	POWER_MINPWR_SELECT_OSC				(1 << 8)
+#define	POWER_MINPWR_VBG_OFF				(1 << 7)
+#define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
+#define	POWER_MINPWR_HALFFETS				(1 << 5)
+#define	POWER_MINPWR_LESSANA_I				(1 << 4)
+#define	POWER_MINPWR_PWD_XTAL24				(1 << 3)
+#define	POWER_MINPWR_DC_STOPCLK				(1 << 2)
+#define	POWER_MINPWR_EN_DC_PFM				(1 << 1)
+#define	POWER_MINPWR_DC_HALFCLK				(1 << 0)
+
+#define	POWER_CHARGE_ADJ_VOLT_MASK			(0x7 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_OFFSET			24
+#define	POWER_CHARGE_ADJ_VOLT_M025P			(0x1 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P050P			(0x2 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M075P			(0x3 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P025P			(0x4 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M050P			(0x5 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P075P			(0x6 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M100P			(0x7 << 24)
+#define	POWER_CHARGE_ENABLE_LOAD			(1 << 22)
+#define	POWER_CHARGE_ENABLE_FAULT_DETECT		(1 << 20)
+#define	POWER_CHARGE_CHRG_STS_OFF			(1 << 19)
+#define	POWER_CHARGE_LIION_4P1				(1 << 18)
+#define	POWER_CHARGE_PWD_BATTCHRG			(1 << 16)
+#define	POWER_CHARGE_ENABLE_CHARGER_USB1		(1 << 13)
+#define	POWER_CHARGE_ENABLE_CHARGER_USB0		(1 << 12)
+#define	POWER_CHARGE_STOP_ILIMIT_MASK			(0xf << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_OFFSET			8
+#define	POWER_CHARGE_STOP_ILIMIT_10MA			(0x1 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_20MA			(0x2 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_50MA			(0x4 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_100MA			(0x8 << 8)
+#define	POWER_CHARGE_BATTCHRG_I_MASK			0x3f
+#define	POWER_CHARGE_BATTCHRG_I_OFFSET			0
+#define	POWER_CHARGE_BATTCHRG_I_10MA			0x01
+#define	POWER_CHARGE_BATTCHRG_I_20MA			0x02
+#define	POWER_CHARGE_BATTCHRG_I_50MA			0x04
+#define	POWER_CHARGE_BATTCHRG_I_100MA			0x08
+#define	POWER_CHARGE_BATTCHRG_I_200MA			0x10
+#define	POWER_CHARGE_BATTCHRG_I_400MA			0x20
+
+#define	POWER_VDDDCTRL_ADJTN_MASK			(0xf << 28)
+#define	POWER_VDDDCTRL_ADJTN_OFFSET			28
+#define	POWER_VDDDCTRL_PWDN_BRNOUT			(1 << 23)
+#define	POWER_VDDDCTRL_DISABLE_STEPPING			(1 << 22)
+#define	POWER_VDDDCTRL_ENABLE_LINREG			(1 << 21)
+#define	POWER_VDDDCTRL_DISABLE_FET			(1 << 20)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_MASK		(0x3 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_OFFSET		16
+#define	POWER_VDDDCTRL_LINREG_OFFSET_0STEPS		(0x0 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 16)
+#define	POWER_VDDDCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDDCTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDDCTRL_TRG_MASK				0x1f
+#define	POWER_VDDDCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDACTRL_PWDN_BRNOUT			(1 << 19)
+#define	POWER_VDDACTRL_DISABLE_STEPPING			(1 << 18)
+#define	POWER_VDDACTRL_ENABLE_LINREG			(1 << 17)
+#define	POWER_VDDACTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDACTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDACTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDACTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDACTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDACTRL_TRG_MASK				0x1f
+#define	POWER_VDDACTRL_TRG_OFFSET			0
+
+#define	POWER_VDDIOCTRL_ADJTN_MASK			(0xf << 20)
+#define	POWER_VDDIOCTRL_ADJTN_OFFSET			20
+#define	POWER_VDDIOCTRL_PWDN_BRNOUT			(1 << 18)
+#define	POWER_VDDIOCTRL_DISABLE_STEPPING		(1 << 17)
+#define	POWER_VDDIOCTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDIOCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDIOCTRL_BO_OFFSET_OFFSET		8
+#define	POWER_VDDIOCTRL_TRG_MASK			0x1f
+#define	POWER_VDDIOCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDMEMCTRL_PULLDOWN_ACTIVE		(1 << 10)
+#define	POWER_VDDMEMCTRL_ENABLE_ILIMIT			(1 << 9)
+#define	POWER_VDDMEMCTRL_ENABLE_LINREG			(1 << 8)
+#define	POWER_VDDMEMCTRL_BO_OFFSET_MASK			(0x7 << 5)
+#define	POWER_VDDMEMCTRL_BO_OFFSET_OFFSET		5
+#define	POWER_VDDMEMCTRL_TRG_MASK			0x1f
+#define	POWER_VDDMEMCTRL_TRG_OFFSET			0
+
+#define	POWER_DCDC4P2_DROPOUT_CTRL_MASK			(0xf << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_OFFSET		28
+#define	POWER_DCDC4P2_DROPOUT_CTRL_200MV		(0x3 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_100MV		(0x2 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_50MV			(0x1 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_25MV			(0x0 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2		(0x0 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT	(0x1 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL		(0x2 << 28)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_MASK		(0x3 << 24)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_OFFSET		24
+#define	POWER_DCDC4P2_ENABLE_4P2			(1 << 23)
+#define	POWER_DCDC4P2_ENABLE_DCDC			(1 << 22)
+#define	POWER_DCDC4P2_HYST_DIR				(1 << 21)
+#define	POWER_DCDC4P2_HYST_THRESH			(1 << 20)
+#define	POWER_DCDC4P2_TRG_MASK				(0x7 << 16)
+#define	POWER_DCDC4P2_TRG_OFFSET			16
+#define	POWER_DCDC4P2_TRG_4V2				(0x0 << 16)
+#define	POWER_DCDC4P2_TRG_4V1				(0x1 << 16)
+#define	POWER_DCDC4P2_TRG_4V0				(0x2 << 16)
+#define	POWER_DCDC4P2_TRG_3V9				(0x3 << 16)
+#define	POWER_DCDC4P2_TRG_BATT				(0x4 << 16)
+#define	POWER_DCDC4P2_BO_MASK				(0x1f << 8)
+#define	POWER_DCDC4P2_BO_OFFSET				8
+#define	POWER_DCDC4P2_CMPTRIP_MASK			0x1f
+#define	POWER_DCDC4P2_CMPTRIP_OFFSET			0
+
+#define	POWER_MISC_FREQSEL_MASK				(0x7 << 4)
+#define	POWER_MISC_FREQSEL_OFFSET			4
+#define	POWER_MISC_FREQSEL_20MHZ			(0x1 << 4)
+#define	POWER_MISC_FREQSEL_24MHZ			(0x2 << 4)
+#define	POWER_MISC_FREQSEL_19MHZ			(0x3 << 4)
+#define	POWER_MISC_FREQSEL_14MHZ			(0x4 << 4)
+#define	POWER_MISC_FREQSEL_18MHZ			(0x5 << 4)
+#define	POWER_MISC_FREQSEL_21MHZ			(0x6 << 4)
+#define	POWER_MISC_FREQSEL_17MHZ			(0x7 << 4)
+#define	POWER_MISC_DISABLE_FET_BO_LOGIC			(1 << 3)
+#define	POWER_MISC_DELAY_TIMING				(1 << 2)
+#define	POWER_MISC_TEST					(1 << 1)
+#define	POWER_MISC_SEL_PLLCLK				(1 << 0)
+
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
+#define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
+#define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
+
+#define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
+#define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)
+#define	POWER_LOOPCTRL_EN_CM_HYST			(1 << 18)
+#define	POWER_LOOPCTRL_EN_DF_HYST			(1 << 17)
+#define	POWER_LOOPCTRL_CM_HYST_THRESH			(1 << 16)
+#define	POWER_LOOPCTRL_DF_HYST_THRESH			(1 << 15)
+#define	POWER_LOOPCTRL_RCSCALE_THRESH			(1 << 14)
+#define	POWER_LOOPCTRL_EN_RCSCALE_MASK			(0x3 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_OFFSET		12
+#define	POWER_LOOPCTRL_EN_RCSCALE_DIS			(0x0 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_2X			(0x1 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_4X			(0x2 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_8X			(0x3 << 12)
+#define	POWER_LOOPCTRL_DC_FF_MASK			(0x7 << 8)
+#define	POWER_LOOPCTRL_DC_FF_OFFSET			8
+#define	POWER_LOOPCTRL_DC_R_MASK			(0xf << 4)
+#define	POWER_LOOPCTRL_DC_R_OFFSET			4
+#define	POWER_LOOPCTRL_DC_C_MASK			0x3
+#define	POWER_LOOPCTRL_DC_C_OFFSET			0
+#define	POWER_LOOPCTRL_DC_C_MAX				0x0
+#define	POWER_LOOPCTRL_DC_C_2X				0x1
+#define	POWER_LOOPCTRL_DC_C_4X				0x2
+#define	POWER_LOOPCTRL_DC_C_MIN				0x3
+
+#define	POWER_STS_PWRUP_SOURCE_MASK			(0x3f << 24)
+#define	POWER_STS_PWRUP_SOURCE_OFFSET			24
+#define	POWER_STS_PWRUP_SOURCE_5V			(0x20 << 24)
+#define	POWER_STS_PWRUP_SOURCE_RTC			(0x10 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH		(0x02 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_MID		(0x01 << 24)
+#define	POWER_STS_PSWITCH_MASK				(0x3 << 20)
+#define	POWER_STS_PSWITCH_OFFSET			20
+#define	POWER_STS_THERMAL_WARNING			(1 << 19)
+#define	POWER_STS_VDDMEM_BO				(1 << 18)
+#define	POWER_STS_AVALID0_STATUS			(1 << 17)
+#define	POWER_STS_BVALID0_STATUS			(1 << 16)
+#define	POWER_STS_VBUSVALID0_STATUS			(1 << 15)
+#define	POWER_STS_SESSEND0_STATUS			(1 << 14)
+#define	POWER_STS_BATT_BO				(1 << 13)
+#define	POWER_STS_VDD5V_FAULT				(1 << 12)
+#define	POWER_STS_CHRGSTS				(1 << 11)
+#define	POWER_STS_DCDC_4P2_BO				(1 << 10)
+#define	POWER_STS_DC_OK					(1 << 9)
+#define	POWER_STS_VDDIO_BO				(1 << 8)
+#define	POWER_STS_VDDA_BO				(1 << 7)
+#define	POWER_STS_VDDD_BO				(1 << 6)
+#define	POWER_STS_VDD5V_GT_VDDIO			(1 << 5)
+#define	POWER_STS_VDD5V_DROOP				(1 << 4)
+#define	POWER_STS_AVALID0				(1 << 3)
+#define	POWER_STS_BVALID0				(1 << 2)
+#define	POWER_STS_VBUSVALID0				(1 << 1)
+#define	POWER_STS_SESSEND0				(1 << 0)
+
+#define	POWER_SPEED_STATUS_MASK				(0xffff << 8)
+#define	POWER_SPEED_STATUS_OFFSET			8
+#define	POWER_SPEED_STATUS_SEL_MASK			(0x3 << 6)
+#define	POWER_SPEED_STATUS_SEL_OFFSET			6
+#define	POWER_SPEED_STATUS_SEL_DCDC_STAT		(0x0 << 6)
+#define	POWER_SPEED_STATUS_SEL_CORE_STAT		(0x1 << 6)
+#define	POWER_SPEED_STATUS_SEL_ARM_STAT			(0x2 << 6)
+#define	POWER_SPEED_CTRL_MASK				0x3
+#define	POWER_SPEED_CTRL_OFFSET				0
+#define	POWER_SPEED_CTRL_SS_OFF				0x0
+#define	POWER_SPEED_CTRL_SS_ON				0x1
+#define	POWER_SPEED_CTRL_SS_ENABLE			0x3
+
+#define	POWER_BATTMONITOR_BATT_VAL_MASK			(0x3ff << 16)
+#define	POWER_BATTMONITOR_BATT_VAL_OFFSET		16
+#define	POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN	(1 << 11)
+#define	POWER_BATTMONITOR_EN_BATADJ			(1 << 10)
+#define	POWER_BATTMONITOR_PWDN_BATTBRNOUT		(1 << 9)
+#define	POWER_BATTMONITOR_BRWNOUT_PWD			(1 << 8)
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_MASK		0x1f
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET		0
+
+#define	POWER_RESET_UNLOCK_MASK				(0xffff << 16)
+#define	POWER_RESET_UNLOCK_OFFSET			16
+#define	POWER_RESET_UNLOCK_KEY				(0x3e77 << 16)
+#define	POWER_RESET_FASTFALL_PSWITCH_OFF		(1 << 2)
+#define	POWER_RESET_PWD_OFF				(1 << 1)
+#define	POWER_RESET_PWD					(1 << 0)
+
+#define	POWER_DEBUG_VBUSVALIDPIOLOCK			(1 << 3)
+#define	POWER_DEBUG_AVALIDPIOLOCK			(1 << 2)
+#define	POWER_DEBUG_BVALIDPIOLOCK			(1 << 1)
+#define	POWER_DEBUG_SESSENDPIOLOCK			(1 << 0)
+
+#define	POWER_THERMAL_TEST				(1 << 8)
+#define	POWER_THERMAL_PWD				(1 << 7)
+#define	POWER_THERMAL_LOW_POWER				(1 << 6)
+#define	POWER_THERMAL_OFFSET_ADJ_MASK			(0x3 << 4)
+#define	POWER_THERMAL_OFFSET_ADJ_OFFSET			4
+#define	POWER_THERMAL_OFFSET_ADJ_ENABLE			(1 << 3)
+#define	POWER_THERMAL_TEMP_THRESHOLD_MASK		0x7
+#define	POWER_THERMAL_TEMP_THRESHOLD_OFFSET		0
+
+#define	POWER_USB1CTRL_AVALID1				(1 << 3)
+#define	POWER_USB1CTRL_BVALID1				(1 << 2)
+#define	POWER_USB1CTRL_VBUSVALID1			(1 << 1)
+#define	POWER_USB1CTRL_SESSEND1				(1 << 0)
+
+#define	POWER_SPECIAL_TEST_MASK				0xffffffff
+#define	POWER_SPECIAL_TEST_OFFSET			0
+
+#define	POWER_VERSION_MAJOR_MASK			(0xff << 24)
+#define	POWER_VERSION_MAJOR_OFFSET			24
+#define	POWER_VERSION_MINOR_MASK			(0xff << 16)
+#define	POWER_VERSION_MINOR_OFFSET			16
+#define	POWER_VERSION_STEP_MASK				0xffff
+#define	POWER_VERSION_STEP_OFFSET			0
+
+#define	POWER_ANACLKCTRL_CLKGATE_0			(1 << 31)
+#define	POWER_ANACLKCTRL_OUTDIV_MASK			(0x7 << 28)
+#define	POWER_ANACLKCTRL_OUTDIV_OFFSET			28
+#define	POWER_ANACLKCTRL_INVERT_OUTCLK			(1 << 27)
+#define	POWER_ANACLKCTRL_CLKGATE_I			(1 << 26)
+#define	POWER_ANACLKCTRL_DITHER_OFF			(1 << 10)
+#define	POWER_ANACLKCTRL_SLOW_DITHER			(1 << 9)
+#define	POWER_ANACLKCTRL_INVERT_INCLK			(1 << 8)
+#define	POWER_ANACLKCTRL_INCLK_SHIFT_MASK		(0x3 << 4)
+#define	POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET		4
+#define	POWER_ANACLKCTRL_INDIV_MASK			0x7
+#define	POWER_ANACLKCTRL_INDIV_OFFSET			0
+
+#define	POWER_REFCTRL_FASTSETTLING			(1 << 26)
+#define	POWER_REFCTRL_RAISE_REF				(1 << 25)
+#define	POWER_REFCTRL_XTAL_BGR_BIAS			(1 << 24)
+#define	POWER_REFCTRL_VBG_ADJ_MASK			(0x7 << 20)
+#define	POWER_REFCTRL_VBG_ADJ_OFFSET			20
+#define	POWER_REFCTRL_LOW_PWR				(1 << 19)
+#define	POWER_REFCTRL_BIAS_CTRL_MASK			(0x3 << 16)
+#define	POWER_REFCTRL_BIAS_CTRL_OFFSET			16
+#define	POWER_REFCTRL_VDDXTAL_TO_VDDD			(1 << 14)
+#define	POWER_REFCTRL_ADJ_ANA				(1 << 13)
+#define	POWER_REFCTRL_ADJ_VAG				(1 << 12)
+#define	POWER_REFCTRL_ANA_REFVAL_MASK			(0xf << 8)
+#define	POWER_REFCTRL_ANA_REFVAL_OFFSET			8
+#define	POWER_REFCTRL_VAG_VAL_MASK			(0xf << 4)
+#define	POWER_REFCTRL_VAG_VAL_OFFSET			4
+
+#endif	/* __MX28_REGS_POWER_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-rtc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-rtc.h
new file mode 100644
index 000000000..03e2e5dd6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-rtc.h
@@ -0,0 +1,134 @@
+/*
+ * Freescale i.MX28 RTC Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_RTC_H__
+#define __MX28_REGS_RTC_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_rtc_regs {
+	mxs_reg_32(hw_rtc_ctrl)
+	mxs_reg_32(hw_rtc_stat)
+	mxs_reg_32(hw_rtc_milliseconds)
+	mxs_reg_32(hw_rtc_seconds)
+	mxs_reg_32(hw_rtc_rtc_alarm)
+	mxs_reg_32(hw_rtc_watchdog)
+	mxs_reg_32(hw_rtc_persistent0)
+	mxs_reg_32(hw_rtc_persistent1)
+	mxs_reg_32(hw_rtc_persistent2)
+	mxs_reg_32(hw_rtc_persistent3)
+	mxs_reg_32(hw_rtc_persistent4)
+	mxs_reg_32(hw_rtc_persistent5)
+	mxs_reg_32(hw_rtc_debug)
+	mxs_reg_32(hw_rtc_version)
+};
+#endif
+
+#define	RTC_CTRL_SFTRST				(1 << 31)
+#define	RTC_CTRL_CLKGATE			(1 << 30)
+#define	RTC_CTRL_SUPPRESS_COPY2ANALOG		(1 << 6)
+#define	RTC_CTRL_FORCE_UPDATE			(1 << 5)
+#define	RTC_CTRL_WATCHDOGEN			(1 << 4)
+#define	RTC_CTRL_ONEMSEC_IRQ			(1 << 3)
+#define	RTC_CTRL_ALARM_IRQ			(1 << 2)
+#define	RTC_CTRL_ONEMSEC_IRQ_EN			(1 << 1)
+#define	RTC_CTRL_ALARM_IRQ_EN			(1 << 0)
+
+#define	RTC_STAT_RTC_PRESENT			(1 << 31)
+#define	RTC_STAT_ALARM_PRESENT			(1 << 30)
+#define	RTC_STAT_WATCHDOG_PRESENT		(1 << 29)
+#define	RTC_STAT_XTAL32000_PRESENT		(1 << 28)
+#define	RTC_STAT_XTAL32768_PRESENT		(1 << 27)
+#define	RTC_STAT_STALE_REGS_MASK		(0xff << 16)
+#define	RTC_STAT_STALE_REGS_OFFSET		16
+#define	RTC_STAT_NEW_REGS_MASK			(0xff << 8)
+#define	RTC_STAT_NEW_REGS_OFFSET		8
+
+#define	RTC_MILLISECONDS_COUNT_MASK		0xffffffff
+#define	RTC_MILLISECONDS_COUNT_OFFSET		0
+
+#define	RTC_SECONDS_COUNT_MASK			0xffffffff
+#define	RTC_SECONDS_COUNT_OFFSET		0
+
+#define	RTC_ALARM_VALUE_MASK			0xffffffff
+#define	RTC_ALARM_VALUE_OFFSET			0
+
+#define	RTC_WATCHDOG_COUNT_MASK			0xffffffff
+#define	RTC_WATCHDOG_COUNT_OFFSET		0
+
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK	(0xf << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET	28
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83	(0x0 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78	(0x1 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73	(0x2 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68	(0x3 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62	(0x4 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57	(0x5 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52	(0x6 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48	(0x7 << 28)
+#define	RTC_PERSISTENT0_EXTERNAL_RESET		(1 << 21)
+#define	RTC_PERSISTENT0_THERMAL_RESET		(1 << 20)
+#define	RTC_PERSISTENT0_ENABLE_LRADC_PWRUP	(1 << 18)
+#define	RTC_PERSISTENT0_AUTO_RESTART		(1 << 17)
+#define	RTC_PERSISTENT0_DISABLE_PSWITCH		(1 << 16)
+#define	RTC_PERSISTENT0_LOWERBIAS_MASK		(0xf << 14)
+#define	RTC_PERSISTENT0_LOWERBIAS_OFFSET	14
+#define	RTC_PERSISTENT0_LOWERBIAS_NOMINAL	(0x0 << 14)
+#define	RTC_PERSISTENT0_LOWERBIAS_M25P		(0x1 << 14)
+#define	RTC_PERSISTENT0_LOWERBIAS_M50P		(0x3 << 14)
+#define	RTC_PERSISTENT0_DISABLE_XTALOK		(1 << 13)
+#define	RTC_PERSISTENT0_MSEC_RES_MASK		(0x1f << 8)
+#define	RTC_PERSISTENT0_MSEC_RES_OFFSET		8
+#define	RTC_PERSISTENT0_MSEC_RES_1MS		(0x01 << 8)
+#define	RTC_PERSISTENT0_MSEC_RES_2MS		(0x02 << 8)
+#define	RTC_PERSISTENT0_MSEC_RES_4MS		(0x04 << 8)
+#define	RTC_PERSISTENT0_MSEC_RES_8MS		(0x08 << 8)
+#define	RTC_PERSISTENT0_MSEC_RES_16MS		(0x10 << 8)
+#define	RTC_PERSISTENT0_ALARM_WAKE		(1 << 7)
+#define	RTC_PERSISTENT0_XTAL32_FREQ		(1 << 6)
+#define	RTC_PERSISTENT0_XTAL32KHZ_PWRUP		(1 << 5)
+#define	RTC_PERSISTENT0_XTAL24KHZ_PWRUP		(1 << 4)
+#define	RTC_PERSISTENT0_LCK_SECS		(1 << 3)
+#define	RTC_PERSISTENT0_ALARM_EN		(1 << 2)
+#define	RTC_PERSISTENT0_ALARM_WAKE_EN		(1 << 1)
+#define	RTC_PERSISTENT0_CLOCKSOURCE		(1 << 0)
+
+#define	RTC_PERSISTENT1_GENERAL_MASK		0xffffffff
+#define	RTC_PERSISTENT1_GENERAL_OFFSET		0
+#define	RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE	0x0080
+#define	RTC_PERSISTENT1_GENERAL_OTG_HNP		0x0100
+#define	RTC_PERSISTENT1_GENERAL_USB_LPM		0x0200
+#define	RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK	0x0400
+#define	RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER	0x0800
+#define	RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X	0x1000
+
+#define	RTC_PERSISTENT2_GENERAL_MASK		0xffffffff
+#define	RTC_PERSISTENT2_GENERAL_OFFSET		0
+
+#define	RTC_PERSISTENT3_GENERAL_MASK		0xffffffff
+#define	RTC_PERSISTENT3_GENERAL_OFFSET		0
+
+#define	RTC_PERSISTENT4_GENERAL_MASK		0xffffffff
+#define	RTC_PERSISTENT4_GENERAL_OFFSET		0
+
+#define	RTC_PERSISTENT5_GENERAL_MASK		0xffffffff
+#define	RTC_PERSISTENT5_GENERAL_OFFSET		0
+
+#define	RTC_DEBUG_WATCHDOG_RESET_MASK		(1 << 1)
+#define	RTC_DEBUG_WATCHDOG_RESET		(1 << 0)
+
+#define	RTC_VERSION_MAJOR_MASK			(0xff << 24)
+#define	RTC_VERSION_MAJOR_OFFSET		24
+#define	RTC_VERSION_MINOR_MASK			(0xff << 16)
+#define	RTC_VERSION_MINOR_OFFSET		16
+#define	RTC_VERSION_STEP_MASK			0xffff
+#define	RTC_VERSION_STEP_OFFSET			0
+
+#endif	/* __MX28_REGS_RTC_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ssp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ssp.h
new file mode 100644
index 000000000..e991216d0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-ssp.h
@@ -0,0 +1,416 @@
+/*
+ * Freescale i.MX28 SSP Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_SSP_H__
+#define __MX28_REGS_SSP_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+#if defined(CONFIG_MX23)
+struct mxs_ssp_regs {
+	mxs_reg_32(hw_ssp_ctrl0)
+	mxs_reg_32(hw_ssp_cmd0)
+	mxs_reg_32(hw_ssp_cmd1)
+	mxs_reg_32(hw_ssp_compref)
+	mxs_reg_32(hw_ssp_compmask)
+	mxs_reg_32(hw_ssp_timing)
+	mxs_reg_32(hw_ssp_ctrl1)
+	mxs_reg_32(hw_ssp_data)
+	mxs_reg_32(hw_ssp_sdresp0)
+	mxs_reg_32(hw_ssp_sdresp1)
+	mxs_reg_32(hw_ssp_sdresp2)
+	mxs_reg_32(hw_ssp_sdresp3)
+	mxs_reg_32(hw_ssp_status)
+
+	uint32_t	reserved1[12];
+
+	mxs_reg_32(hw_ssp_debug)
+	mxs_reg_32(hw_ssp_version)
+};
+#elif defined(CONFIG_MX28)
+struct mxs_ssp_regs {
+	mxs_reg_32(hw_ssp_ctrl0)
+	mxs_reg_32(hw_ssp_cmd0)
+	mxs_reg_32(hw_ssp_cmd1)
+	mxs_reg_32(hw_ssp_xfer_size)
+	mxs_reg_32(hw_ssp_block_size)
+	mxs_reg_32(hw_ssp_compref)
+	mxs_reg_32(hw_ssp_compmask)
+	mxs_reg_32(hw_ssp_timing)
+	mxs_reg_32(hw_ssp_ctrl1)
+	mxs_reg_32(hw_ssp_data)
+	mxs_reg_32(hw_ssp_sdresp0)
+	mxs_reg_32(hw_ssp_sdresp1)
+	mxs_reg_32(hw_ssp_sdresp2)
+	mxs_reg_32(hw_ssp_sdresp3)
+	mxs_reg_32(hw_ssp_ddr_ctrl)
+	mxs_reg_32(hw_ssp_dll_ctrl)
+	mxs_reg_32(hw_ssp_status)
+	mxs_reg_32(hw_ssp_dll_sts)
+	mxs_reg_32(hw_ssp_debug)
+	mxs_reg_32(hw_ssp_version)
+};
+#endif
+
+static inline int mxs_ssp_bus_id_valid(int bus)
+{
+#if defined(CONFIG_MX23)
+	const unsigned int mxs_ssp_chan_count = 2;
+#elif defined(CONFIG_MX28)
+	const unsigned int mxs_ssp_chan_count = 4;
+#endif
+
+	if (bus >= mxs_ssp_chan_count)
+		return 0;
+
+	if (bus < 0)
+		return 0;
+
+	return 1;
+}
+
+static inline int mxs_ssp_clock_by_bus(unsigned int clock)
+{
+#if defined(CONFIG_MX23)
+	return 0;
+#elif defined(CONFIG_MX28)
+	return clock;
+#endif
+}
+
+static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
+{
+	switch (port) {
+	case 0:
+		return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
+	case 1:
+		return (struct mxs_ssp_regs *)MXS_SSP1_BASE;
+#ifdef CONFIG_MX28
+	case 2:
+		return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
+	case 3:
+		return (struct mxs_ssp_regs *)MXS_SSP3_BASE;
+#endif
+	default:
+		return NULL;
+	}
+}
+#endif
+
+#define	SSP_CTRL0_SFTRST			(1 << 31)
+#define	SSP_CTRL0_CLKGATE			(1 << 30)
+#define	SSP_CTRL0_RUN				(1 << 29)
+#define	SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)
+#define	SSP_CTRL0_LOCK_CS			(1 << 27)
+#define	SSP_CTRL0_IGNORE_CRC			(1 << 26)
+#define	SSP_CTRL0_READ				(1 << 25)
+#define	SSP_CTRL0_DATA_XFER			(1 << 24)
+#define	SSP_CTRL0_BUS_WIDTH_MASK		(0x3 << 22)
+#define	SSP_CTRL0_BUS_WIDTH_OFFSET		22
+#define	SSP_CTRL0_BUS_WIDTH_ONE_BIT		(0x0 << 22)
+#define	SSP_CTRL0_BUS_WIDTH_FOUR_BIT		(0x1 << 22)
+#define	SSP_CTRL0_BUS_WIDTH_EIGHT_BIT		(0x2 << 22)
+#define	SSP_CTRL0_WAIT_FOR_IRQ			(1 << 21)
+#define	SSP_CTRL0_WAIT_FOR_CMD			(1 << 20)
+#define	SSP_CTRL0_LONG_RESP			(1 << 19)
+#define	SSP_CTRL0_CHECK_RESP			(1 << 18)
+#define	SSP_CTRL0_GET_RESP			(1 << 17)
+#define	SSP_CTRL0_ENABLE			(1 << 16)
+
+#ifdef CONFIG_MX23
+#define	SSP_CTRL0_XFER_COUNT_OFFSET		0
+#define	SSP_CTRL0_XFER_COUNT_MASK		0xffff
+#endif
+
+#define	SSP_CMD0_SOFT_TERMINATE			(1 << 26)
+#define	SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
+#define	SSP_CMD0_PRIM_BOOT_OP_EN		(1 << 24)
+#define	SSP_CMD0_BOOT_ACK_EN			(1 << 23)
+#define	SSP_CMD0_SLOW_CLKING_EN			(1 << 22)
+#define	SSP_CMD0_CONT_CLKING_EN			(1 << 21)
+#define	SSP_CMD0_APPEND_8CYC			(1 << 20)
+#if defined(CONFIG_MX23)
+#define	SSP_CMD0_BLOCK_SIZE_MASK		(0xf << 16)
+#define	SSP_CMD0_BLOCK_SIZE_OFFSET		16
+#define	SSP_CMD0_BLOCK_COUNT_MASK		(0xff << 8)
+#define	SSP_CMD0_BLOCK_COUNT_OFFSET		8
+#endif
+#define	SSP_CMD0_CMD_MASK			0xff
+#define	SSP_CMD0_CMD_OFFSET			0
+#define	SSP_CMD0_CMD_MMC_GO_IDLE_STATE		0x00
+#define	SSP_CMD0_CMD_MMC_SEND_OP_COND		0x01
+#define	SSP_CMD0_CMD_MMC_ALL_SEND_CID		0x02
+#define	SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR	0x03
+#define	SSP_CMD0_CMD_MMC_SET_DSR		0x04
+#define	SSP_CMD0_CMD_MMC_RESERVED_5		0x05
+#define	SSP_CMD0_CMD_MMC_SWITCH			0x06
+#define	SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD	0x07
+#define	SSP_CMD0_CMD_MMC_SEND_EXT_CSD		0x08
+#define	SSP_CMD0_CMD_MMC_SEND_CSD		0x09
+#define	SSP_CMD0_CMD_MMC_SEND_CID		0x0a
+#define	SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP	0x0b
+#define	SSP_CMD0_CMD_MMC_STOP_TRANSMISSION	0x0c
+#define	SSP_CMD0_CMD_MMC_SEND_STATUS		0x0d
+#define	SSP_CMD0_CMD_MMC_BUSTEST_R		0x0e
+#define	SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE	0x0f
+#define	SSP_CMD0_CMD_MMC_SET_BLOCKLEN		0x10
+#define	SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK	0x11
+#define	SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK	0x12
+#define	SSP_CMD0_CMD_MMC_BUSTEST_W		0x13
+#define	SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP	0x14
+#define	SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT	0x17
+#define	SSP_CMD0_CMD_MMC_WRITE_BLOCK		0x18
+#define	SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK	0x19
+#define	SSP_CMD0_CMD_MMC_PROGRAM_CID		0x1a
+#define	SSP_CMD0_CMD_MMC_PROGRAM_CSD		0x1b
+#define	SSP_CMD0_CMD_MMC_SET_WRITE_PROT		0x1c
+#define	SSP_CMD0_CMD_MMC_CLR_WRITE_PROT		0x1d
+#define	SSP_CMD0_CMD_MMC_SEND_WRITE_PROT	0x1e
+#define	SSP_CMD0_CMD_MMC_ERASE_GROUP_START	0x23
+#define	SSP_CMD0_CMD_MMC_ERASE_GROUP_END	0x24
+#define	SSP_CMD0_CMD_MMC_ERASE			0x26
+#define	SSP_CMD0_CMD_MMC_FAST_IO		0x27
+#define	SSP_CMD0_CMD_MMC_GO_IRQ_STATE		0x28
+#define	SSP_CMD0_CMD_MMC_LOCK_UNLOCK		0x2a
+#define	SSP_CMD0_CMD_MMC_APP_CMD		0x37
+#define	SSP_CMD0_CMD_MMC_GEN_CMD		0x38
+#define	SSP_CMD0_CMD_SD_GO_IDLE_STATE		0x00
+#define	SSP_CMD0_CMD_SD_ALL_SEND_CID		0x02
+#define	SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR	0x03
+#define	SSP_CMD0_CMD_SD_SET_DSR			0x04
+#define	SSP_CMD0_CMD_SD_IO_SEND_OP_COND		0x05
+#define	SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD	0x07
+#define	SSP_CMD0_CMD_SD_SEND_CSD		0x09
+#define	SSP_CMD0_CMD_SD_SEND_CID		0x0a
+#define	SSP_CMD0_CMD_SD_STOP_TRANSMISSION	0x0c
+#define	SSP_CMD0_CMD_SD_SEND_STATUS		0x0d
+#define	SSP_CMD0_CMD_SD_GO_INACTIVE_STATE	0x0f
+#define	SSP_CMD0_CMD_SD_SET_BLOCKLEN		0x10
+#define	SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK	0x11
+#define	SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK	0x12
+#define	SSP_CMD0_CMD_SD_WRITE_BLOCK		0x18
+#define	SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK	0x19
+#define	SSP_CMD0_CMD_SD_PROGRAM_CSD		0x1b
+#define	SSP_CMD0_CMD_SD_SET_WRITE_PROT		0x1c
+#define	SSP_CMD0_CMD_SD_CLR_WRITE_PROT		0x1d
+#define	SSP_CMD0_CMD_SD_SEND_WRITE_PROT		0x1e
+#define	SSP_CMD0_CMD_SD_ERASE_WR_BLK_START	0x20
+#define	SSP_CMD0_CMD_SD_ERASE_WR_BLK_END	0x21
+#define	SSP_CMD0_CMD_SD_ERASE_GROUP_START	0x23
+#define	SSP_CMD0_CMD_SD_ERASE_GROUP_END		0x24
+#define	SSP_CMD0_CMD_SD_ERASE			0x26
+#define	SSP_CMD0_CMD_SD_LOCK_UNLOCK		0x2a
+#define	SSP_CMD0_CMD_SD_IO_RW_DIRECT		0x34
+#define	SSP_CMD0_CMD_SD_IO_RW_EXTENDED		0x35
+#define	SSP_CMD0_CMD_SD_APP_CMD			0x37
+#define	SSP_CMD0_CMD_SD_GEN_CMD			0x38
+
+#define	SSP_CMD1_CMD_ARG_MASK			0xffffffff
+#define	SSP_CMD1_CMD_ARG_OFFSET			0
+
+#if defined(CONFIG_MX28)
+#define	SSP_XFER_SIZE_XFER_COUNT_MASK		0xffffffff
+#define	SSP_XFER_SIZE_XFER_COUNT_OFFSET		0
+
+#define	SSP_BLOCK_SIZE_BLOCK_COUNT_MASK		(0xffffff << 4)
+#define	SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET	4
+#define	SSP_BLOCK_SIZE_BLOCK_SIZE_MASK		0xf
+#define	SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET	0
+#endif
+
+#define	SSP_COMPREF_REFERENCE_MASK		0xffffffff
+#define	SSP_COMPREF_REFERENCE_OFFSET		0
+
+#define	SSP_COMPMASK_MASK_MASK			0xffffffff
+#define	SSP_COMPMASK_MASK_OFFSET		0
+
+#define	SSP_TIMING_TIMEOUT_MASK			(0xffff << 16)
+#define	SSP_TIMING_TIMEOUT_OFFSET		16
+#define	SSP_TIMING_CLOCK_DIVIDE_MASK		(0xff << 8)
+#define	SSP_TIMING_CLOCK_DIVIDE_OFFSET		8
+#define	SSP_TIMING_CLOCK_RATE_MASK		0xff
+#define	SSP_TIMING_CLOCK_RATE_OFFSET		0
+
+#define	SSP_CTRL1_SDIO_IRQ			(1 << 31)
+#define	SSP_CTRL1_SDIO_IRQ_EN			(1 << 30)
+#define	SSP_CTRL1_RESP_ERR_IRQ			(1 << 29)
+#define	SSP_CTRL1_RESP_ERR_IRQ_EN		(1 << 28)
+#define	SSP_CTRL1_RESP_TIMEOUT_IRQ		(1 << 27)
+#define	SSP_CTRL1_RESP_TIMEOUT_IRQ_EN		(1 << 26)
+#define	SSP_CTRL1_DATA_TIMEOUT_IRQ		(1 << 25)
+#define	SSP_CTRL1_DATA_TIMEOUT_IRQ_EN		(1 << 24)
+#define	SSP_CTRL1_DATA_CRC_IRQ			(1 << 23)
+#define	SSP_CTRL1_DATA_CRC_IRQ_EN		(1 << 22)
+#define	SSP_CTRL1_FIFO_UNDERRUN_IRQ		(1 << 21)
+#define	SSP_CTRL1_FIFO_UNDERRUN_EN		(1 << 20)
+#define	SSP_CTRL1_CEATA_CCS_ERR_IRQ		(1 << 19)
+#define	SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN		(1 << 18)
+#define	SSP_CTRL1_RECV_TIMEOUT_IRQ		(1 << 17)
+#define	SSP_CTRL1_RECV_TIMEOUT_IRQ_EN		(1 << 16)
+#define	SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)
+#define	SSP_CTRL1_FIFO_OVERRUN_IRQ_EN		(1 << 14)
+#define	SSP_CTRL1_DMA_ENABLE			(1 << 13)
+#define	SSP_CTRL1_CEATA_CCS_ERR_EN		(1 << 12)
+#define	SSP_CTRL1_SLAVE_OUT_DISABLE		(1 << 11)
+#define	SSP_CTRL1_PHASE				(1 << 10)
+#define	SSP_CTRL1_POLARITY			(1 << 9)
+#define	SSP_CTRL1_SLAVE_MODE			(1 << 8)
+#define	SSP_CTRL1_WORD_LENGTH_MASK		(0xf << 4)
+#define	SSP_CTRL1_WORD_LENGTH_OFFSET		4
+#define	SSP_CTRL1_WORD_LENGTH_RESERVED0		(0x0 << 4)
+#define	SSP_CTRL1_WORD_LENGTH_RESERVED1		(0x1 << 4)
+#define	SSP_CTRL1_WORD_LENGTH_RESERVED2		(0x2 << 4)
+#define	SSP_CTRL1_WORD_LENGTH_FOUR_BITS		(0x3 << 4)
+#define	SSP_CTRL1_WORD_LENGTH_EIGHT_BITS	(0x7 << 4)
+#define	SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS	(0xf << 4)
+#define	SSP_CTRL1_SSP_MODE_MASK			0xf
+#define	SSP_CTRL1_SSP_MODE_OFFSET		0
+#define	SSP_CTRL1_SSP_MODE_SPI			0x0
+#define	SSP_CTRL1_SSP_MODE_SSI			0x1
+#define	SSP_CTRL1_SSP_MODE_SD_MMC		0x3
+#define	SSP_CTRL1_SSP_MODE_MS			0x4
+
+#define	SSP_DATA_DATA_MASK			0xffffffff
+#define	SSP_DATA_DATA_OFFSET			0
+
+#define	SSP_SDRESP0_RESP0_MASK			0xffffffff
+#define	SSP_SDRESP0_RESP0_OFFSET		0
+
+#define	SSP_SDRESP1_RESP1_MASK			0xffffffff
+#define	SSP_SDRESP1_RESP1_OFFSET		0
+
+#define	SSP_SDRESP2_RESP2_MASK			0xffffffff
+#define	SSP_SDRESP2_RESP2_OFFSET		0
+
+#define	SSP_SDRESP3_RESP3_MASK			0xffffffff
+#define	SSP_SDRESP3_RESP3_OFFSET		0
+
+#define	SSP_DDR_CTRL_DMA_BURST_TYPE_MASK	(0x3 << 30)
+#define	SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET	30
+#define	SSP_DDR_CTRL_NIBBLE_POS			(1 << 1)
+#define	SSP_DDR_CTRL_TXCLK_DELAY_TYPE		(1 << 0)
+
+#define	SSP_DLL_CTRL_REF_UPDATE_INT_MASK	(0xf << 28)
+#define	SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET	28
+#define	SSP_DLL_CTRL_SLV_UPDATE_INT_MASK	(0xff << 20)
+#define	SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET	20
+#define	SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK	(0x3f << 10)
+#define	SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET	10
+#define	SSP_DLL_CTRL_SLV_OVERRIDE		(1 << 9)
+#define	SSP_DLL_CTRL_GATE_UPDATE		(1 << 7)
+#define	SSP_DLL_CTRL_SLV_DLY_TARGET_MASK	(0xf << 3)
+#define	SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET	3
+#define	SSP_DLL_CTRL_SLV_FORCE_UPD		(1 << 2)
+#define	SSP_DLL_CTRL_RESET			(1 << 1)
+#define	SSP_DLL_CTRL_ENABLE			(1 << 0)
+
+#define	SSP_STATUS_PRESENT			(1 << 31)
+#define	SSP_STATUS_MS_PRESENT			(1 << 30)
+#define	SSP_STATUS_SD_PRESENT			(1 << 29)
+#define	SSP_STATUS_CARD_DETECT			(1 << 28)
+#define	SSP_STATUS_DMABURST			(1 << 22)
+#define	SSP_STATUS_DMASENSE			(1 << 21)
+#define	SSP_STATUS_DMATERM			(1 << 20)
+#define	SSP_STATUS_DMAREQ			(1 << 19)
+#define	SSP_STATUS_DMAEND			(1 << 18)
+#define	SSP_STATUS_SDIO_IRQ			(1 << 17)
+#define	SSP_STATUS_RESP_CRC_ERR			(1 << 16)
+#define	SSP_STATUS_RESP_ERR			(1 << 15)
+#define	SSP_STATUS_RESP_TIMEOUT			(1 << 14)
+#define	SSP_STATUS_DATA_CRC_ERR			(1 << 13)
+#define	SSP_STATUS_TIMEOUT			(1 << 12)
+#define	SSP_STATUS_RECV_TIMEOUT_STAT		(1 << 11)
+#define	SSP_STATUS_CEATA_CCS_ERR		(1 << 10)
+#define	SSP_STATUS_FIFO_OVRFLW			(1 << 9)
+#define	SSP_STATUS_FIFO_FULL			(1 << 8)
+#define	SSP_STATUS_FIFO_EMPTY			(1 << 5)
+#define	SSP_STATUS_FIFO_UNDRFLW			(1 << 4)
+#define	SSP_STATUS_CMD_BUSY			(1 << 3)
+#define	SSP_STATUS_DATA_BUSY			(1 << 2)
+#define	SSP_STATUS_BUSY				(1 << 0)
+
+#define	SSP_DLL_STS_REF_SEL_MASK		(0x3f << 8)
+#define	SSP_DLL_STS_REF_SEL_OFFSET		8
+#define	SSP_DLL_STS_SLV_SEL_MASK		(0x3f << 2)
+#define	SSP_DLL_STS_SLV_SEL_OFFSET		2
+#define	SSP_DLL_STS_REF_LOCK			(1 << 1)
+#define	SSP_DLL_STS_SLV_LOCK			(1 << 0)
+
+#define	SSP_DEBUG_DATACRC_ERR_MASK		(0xf << 28)
+#define	SSP_DEBUG_DATACRC_ERR_OFFSET		28
+#define	SSP_DEBUG_DATA_STALL			(1 << 27)
+#define	SSP_DEBUG_DAT_SM_MASK			(0x7 << 24)
+#define	SSP_DEBUG_DAT_SM_OFFSET			24
+#define	SSP_DEBUG_DAT_SM_DSM_IDLE		(0x0 << 24)
+#define	SSP_DEBUG_DAT_SM_DSM_WORD		(0x2 << 24)
+#define	SSP_DEBUG_DAT_SM_DSM_CRC1		(0x3 << 24)
+#define	SSP_DEBUG_DAT_SM_DSM_CRC2		(0x4 << 24)
+#define	SSP_DEBUG_DAT_SM_DSM_END		(0x5 << 24)
+#define	SSP_DEBUG_MSTK_SM_MASK			(0xf << 20)
+#define	SSP_DEBUG_MSTK_SM_OFFSET		20
+#define	SSP_DEBUG_MSTK_SM_MSTK_IDLE		(0x0 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_CKON		(0x1 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_BS1		(0x2 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_TPC		(0x3 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_BS2		(0x4 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_HDSHK		(0x5 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_BS3		(0x6 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_RW		(0x7 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_CRC1		(0x8 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_CRC2		(0x9 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_BS0		(0xa << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_END1		(0xb << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_END2W		(0xc << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_END2R		(0xd << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_DONE		(0xe << 20)
+#define	SSP_DEBUG_CMD_OE			(1 << 19)
+#define	SSP_DEBUG_DMA_SM_MASK			(0x7 << 16)
+#define	SSP_DEBUG_DMA_SM_OFFSET			16
+#define	SSP_DEBUG_DMA_SM_DMA_IDLE		(0x0 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_DMAREQ		(0x1 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_DMAACK		(0x2 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_STALL		(0x3 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_BUSY		(0x4 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_DONE		(0x5 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_COUNT		(0x6 << 16)
+#define	SSP_DEBUG_MMC_SM_MASK			(0xf << 12)
+#define	SSP_DEBUG_MMC_SM_OFFSET			12
+#define	SSP_DEBUG_MMC_SM_MMC_IDLE		(0x0 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_CMD		(0x1 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_TRC		(0x2 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_RESP		(0x3 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_RPRX		(0x4 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_TX			(0x5 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_CTOK		(0x6 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_RX			(0x7 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_CCS		(0x8 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_PUP		(0x9 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_WAIT		(0xa << 12)
+#define	SSP_DEBUG_CMD_SM_MASK			(0x3 << 10)
+#define	SSP_DEBUG_CMD_SM_OFFSET			10
+#define	SSP_DEBUG_CMD_SM_CSM_IDLE		(0x0 << 10)
+#define	SSP_DEBUG_CMD_SM_CSM_INDEX		(0x1 << 10)
+#define	SSP_DEBUG_CMD_SM_CSM_ARG		(0x2 << 10)
+#define	SSP_DEBUG_CMD_SM_CSM_CRC		(0x3 << 10)
+#define	SSP_DEBUG_SSP_CMD			(1 << 9)
+#define	SSP_DEBUG_SSP_RESP			(1 << 8)
+#define	SSP_DEBUG_SSP_RXD_MASK			0xff
+#define	SSP_DEBUG_SSP_RXD_OFFSET		0
+
+#define	SSP_VERSION_MAJOR_MASK			(0xff << 24)
+#define	SSP_VERSION_MAJOR_OFFSET		24
+#define	SSP_VERSION_MINOR_MASK			(0xff << 16)
+#define	SSP_VERSION_MINOR_OFFSET		16
+#define	SSP_VERSION_STEP_MASK			0xffff
+#define	SSP_VERSION_STEP_OFFSET			0
+
+#endif /* __MX28_REGS_SSP_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-timrot.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-timrot.h
new file mode 100644
index 000000000..713c630dc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-timrot.h
@@ -0,0 +1,259 @@
+/*
+ * Freescale i.MX28 TIMROT Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_TIMROT_H__
+#define __MX28_REGS_TIMROT_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_timrot_regs {
+	mxs_reg_32(hw_timrot_rotctrl)
+	mxs_reg_32(hw_timrot_rotcount)
+#if defined(CONFIG_MX23)
+	mxs_reg_32(hw_timrot_timctrl0)
+	mxs_reg_32(hw_timrot_timcount0)
+	mxs_reg_32(hw_timrot_timctrl1)
+	mxs_reg_32(hw_timrot_timcount1)
+	mxs_reg_32(hw_timrot_timctrl2)
+	mxs_reg_32(hw_timrot_timcount2)
+	mxs_reg_32(hw_timrot_timctrl3)
+	mxs_reg_32(hw_timrot_timcount3)
+#elif defined(CONFIG_MX28)
+	mxs_reg_32(hw_timrot_timctrl0)
+	mxs_reg_32(hw_timrot_running_count0)
+	mxs_reg_32(hw_timrot_fixed_count0)
+	mxs_reg_32(hw_timrot_match_count0)
+	mxs_reg_32(hw_timrot_timctrl1)
+	mxs_reg_32(hw_timrot_running_count1)
+	mxs_reg_32(hw_timrot_fixed_count1)
+	mxs_reg_32(hw_timrot_match_count1)
+	mxs_reg_32(hw_timrot_timctrl2)
+	mxs_reg_32(hw_timrot_running_count2)
+	mxs_reg_32(hw_timrot_fixed_count2)
+	mxs_reg_32(hw_timrot_match_count2)
+	mxs_reg_32(hw_timrot_timctrl3)
+	mxs_reg_32(hw_timrot_running_count3)
+	mxs_reg_32(hw_timrot_fixed_count3)
+	mxs_reg_32(hw_timrot_match_count3)
+#endif
+	mxs_reg_32(hw_timrot_version)
+};
+#endif
+
+#define	TIMROT_ROTCTRL_SFTRST				(1 << 31)
+#define	TIMROT_ROTCTRL_CLKGATE				(1 << 30)
+#define	TIMROT_ROTCTRL_ROTARY_PRESENT			(1 << 29)
+#define	TIMROT_ROTCTRL_TIM3_PRESENT			(1 << 28)
+#define	TIMROT_ROTCTRL_TIM2_PRESENT			(1 << 27)
+#define	TIMROT_ROTCTRL_TIM1_PRESENT			(1 << 26)
+#define	TIMROT_ROTCTRL_TIM0_PRESENT			(1 << 25)
+#define	TIMROT_ROTCTRL_STATE_MASK			(0x7 << 22)
+#define	TIMROT_ROTCTRL_STATE_OFFSET			22
+#define	TIMROT_ROTCTRL_DIVIDER_MASK			(0x3f << 16)
+#define	TIMROT_ROTCTRL_DIVIDER_OFFSET			16
+#define	TIMROT_ROTCTRL_RELATIVE				(1 << 12)
+#define	TIMROT_ROTCTRL_OVERSAMPLE_MASK			(0x3 << 10)
+#define	TIMROT_ROTCTRL_OVERSAMPLE_OFFSET		10
+#define	TIMROT_ROTCTRL_OVERSAMPLE_8X			(0x0 << 10)
+#define	TIMROT_ROTCTRL_OVERSAMPLE_4X			(0x1 << 10)
+#define	TIMROT_ROTCTRL_OVERSAMPLE_2X			(0x2 << 10)
+#define	TIMROT_ROTCTRL_OVERSAMPLE_1X			(0x3 << 10)
+#define	TIMROT_ROTCTRL_POLARITY_B			(1 << 9)
+#define	TIMROT_ROTCTRL_POLARITY_A			(1 << 8)
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_B_MASK			(0x7 << 4)
+#elif defined(CONFIG_MX28)
+#define	TIMROT_ROTCTRL_SELECT_B_MASK			(0xf << 4)
+#endif
+#define	TIMROT_ROTCTRL_SELECT_B_OFFSET			4
+#define	TIMROT_ROTCTRL_SELECT_B_NEVER_TICK		(0x0 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM0			(0x1 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM1			(0x2 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM2			(0x3 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM3			(0x4 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM4			(0x5 << 4)
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_B_ROTARYA		(0x6 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_ROTARYB		(0x7 << 4)
+#elif defined(CONFIG_MX28)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM5			(0x6 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM6			(0x7 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM7			(0x8 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_ROTARYA			(0x9 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_ROTARYB			(0xa << 4)
+#endif
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_A_MASK			0x7
+#elif defined(CONFIG_MX28)
+#define	TIMROT_ROTCTRL_SELECT_A_MASK			0xf
+#endif
+#define	TIMROT_ROTCTRL_SELECT_A_OFFSET			0
+#define	TIMROT_ROTCTRL_SELECT_A_NEVER_TICK		0x0
+#define	TIMROT_ROTCTRL_SELECT_A_PWM0			0x1
+#define	TIMROT_ROTCTRL_SELECT_A_PWM1			0x2
+#define	TIMROT_ROTCTRL_SELECT_A_PWM2			0x3
+#define	TIMROT_ROTCTRL_SELECT_A_PWM3			0x4
+#define	TIMROT_ROTCTRL_SELECT_A_PWM4			0x5
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_A_ROTARYA		0x6
+#define	TIMROT_ROTCTRL_SELECT_A_ROTARYB		0x7
+#elif defined(CONFIG_MX28)
+#define	TIMROT_ROTCTRL_SELECT_A_PWM5			0x6
+#define	TIMROT_ROTCTRL_SELECT_A_PWM6			0x7
+#define	TIMROT_ROTCTRL_SELECT_A_PWM7			0x8
+#define	TIMROT_ROTCTRL_SELECT_A_ROTARYA			0x9
+#define	TIMROT_ROTCTRL_SELECT_A_ROTARYB			0xa
+#endif
+
+#define	TIMROT_ROTCOUNT_UPDOWN_MASK			0xffff
+#define	TIMROT_ROTCOUNT_UPDOWN_OFFSET			0
+
+#define	TIMROT_TIMCTRLn_IRQ				(1 << 15)
+#define	TIMROT_TIMCTRLn_IRQ_EN				(1 << 14)
+#if defined(CONFIG_MX28)
+#define	TIMROT_TIMCTRLn_MATCH_MODE			(1 << 11)
+#endif
+#define	TIMROT_TIMCTRLn_POLARITY			(1 << 8)
+#define	TIMROT_TIMCTRLn_UPDATE				(1 << 7)
+#define	TIMROT_TIMCTRLn_RELOAD				(1 << 6)
+#define	TIMROT_TIMCTRLn_PRESCALE_MASK			(0x3 << 4)
+#define	TIMROT_TIMCTRLn_PRESCALE_OFFSET			4
+#define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1		(0x0 << 4)
+#define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2		(0x1 << 4)
+#define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4		(0x2 << 4)
+#define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8		(0x3 << 4)
+#define	TIMROT_TIMCTRLn_SELECT_MASK			0xf
+#define	TIMROT_TIMCTRLn_SELECT_OFFSET			0
+#define	TIMROT_TIMCTRLn_SELECT_NEVER_TICK		0x0
+#define	TIMROT_TIMCTRLn_SELECT_PWM0			0x1
+#define	TIMROT_TIMCTRLn_SELECT_PWM1			0x2
+#define	TIMROT_TIMCTRLn_SELECT_PWM2			0x3
+#define	TIMROT_TIMCTRLn_SELECT_PWM3			0x4
+#define	TIMROT_TIMCTRLn_SELECT_PWM4			0x5
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRLn_SELECT_ROTARYA		0x6
+#define	TIMROT_TIMCTRLn_SELECT_ROTARYB		0x7
+#define	TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL		0x8
+#define	TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL		0x9
+#define	TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL		0xa
+#define	TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL		0xb
+#define	TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS		0xc
+#elif defined(CONFIG_MX28)
+#define	TIMROT_TIMCTRLn_SELECT_PWM5			0x6
+#define	TIMROT_TIMCTRLn_SELECT_PWM6			0x7
+#define	TIMROT_TIMCTRLn_SELECT_PWM7			0x8
+#define	TIMROT_TIMCTRLn_SELECT_ROTARYA			0x9
+#define	TIMROT_TIMCTRLn_SELECT_ROTARYB			0xa
+#define	TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL		0xb
+#define	TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL		0xc
+#define	TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL		0xd
+#define	TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL		0xe
+#define	TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS		0xf
+#endif
+
+#if defined(CONFIG_MX23)
+#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK	(0xffff << 16)
+#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET	16
+#elif defined(CONFIG_MX28)
+#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK	0xffffffff
+#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET	0
+#endif
+
+#if defined(CONFIG_MX23)
+#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK		0xffff
+#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET		0
+#elif defined(CONFIG_MX28)
+#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK		0xffffffff
+#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET		0
+#endif
+
+#if defined(CONFIG_MX28)
+#define	TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK		0xffffffff
+#define	TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET		0
+#endif
+
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_MASK		(0xf << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET		16
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK		(0x0 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0		(0x1 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1		(0x2 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2		(0x3 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3		(0x4 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4		(0x5 << 16)
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA		(0x6 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB		(0x7 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL		(0x8 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL		(0x9 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL		(0xa << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL		(0xb << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS		(0xc << 16)
+#elif defined(CONFIG_MX28)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5		(0x6 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6		(0x7 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7		(0x8 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA		(0x9 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB		(0xa << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL		(0xb << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL		(0xc << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL		(0xd << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL		(0xe << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS		(0xf << 16)
+#endif
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRL3_IRQ				(1 << 15)
+#define	TIMROT_TIMCTRL3_IRQ_EN				(1 << 14)
+#define	TIMROT_TIMCTRL3_DUTU_VALID			(1 << 10)
+#endif
+#define	TIMROT_TIMCTRL3_DUTY_CYCLE			(1 << 9)
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRL3_POLARITY_MASK			(0x1 << 8)
+#define	TIMROT_TIMCTRL3_POLARITY_OFFSET		8
+#define	TIMROT_TIMCTRL3_POLARITY_POSITIVE		(0x0 << 8)
+#define	TIMROT_TIMCTRL3_POLARITY_NEGATIVE		(0x1 << 8)
+#define	TIMROT_TIMCTRL3_UPDATE				(1 << 7)
+#define	TIMROT_TIMCTRL3_RELOAD				(1 << 6)
+#define	TIMROT_TIMCTRL3_PRESCALE_MASK			(0x3 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_OFFSET		4
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1		(0x0 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2		(0x1 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4		(0x2 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8		(0x3 << 4)
+#define	TIMROT_TIMCTRL3_SELECT_MASK			0xf
+#define	TIMROT_TIMCTRL3_SELECT_OFFSET			0
+#define	TIMROT_TIMCTRL3_SELECT_NEVER_TICK		0x0
+#define	TIMROT_TIMCTRL3_SELECT_PWM0			0x1
+#define	TIMROT_TIMCTRL3_SELECT_PWM1			0x2
+#define	TIMROT_TIMCTRL3_SELECT_PWM2			0x3
+#define	TIMROT_TIMCTRL3_SELECT_PWM3			0x4
+#define	TIMROT_TIMCTRL3_SELECT_PWM4			0x5
+#define	TIMROT_TIMCTRL3_SELECT_ROTARYA		0x6
+#define	TIMROT_TIMCTRL3_SELECT_ROTARYB		0x7
+#define	TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL		0x8
+#define	TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL		0x9
+#define	TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL		0xa
+#define	TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL		0xb
+#define	TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS		0xc
+#define	TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK	(0xffff << 16)
+#define	TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET	16
+#define	TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK	0xffff
+#define	TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET	0
+#endif
+
+#define	TIMROT_VERSION_MAJOR_MASK			(0xff << 24)
+#define	TIMROT_VERSION_MAJOR_OFFSET			24
+#define	TIMROT_VERSION_MINOR_MASK			(0xff << 16)
+#define	TIMROT_VERSION_MINOR_OFFSET			16
+#define	TIMROT_VERSION_STEP_MASK			0xffff
+#define	TIMROT_VERSION_STEP_OFFSET			0
+
+#endif /* __MX28_REGS_TIMROT_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-uartapp.h
new file mode 100644
index 000000000..7ceb810dc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-uartapp.h
@@ -0,0 +1,220 @@
+/*
+ * Freescale MXS UARTAPP Register Definitions
+ *
+ * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM___MXS_UARTAPP_H
+#define __ARCH_ARM___MXS_UARTAPP_H
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mxs_uartapp_regs {
+	mxs_reg_32(hw_uartapp_ctrl0)
+	mxs_reg_32(hw_uartapp_ctrl1)
+	mxs_reg_32(hw_uartapp_ctrl2)
+	mxs_reg_32(hw_uartapp_linectrl)
+	mxs_reg_32(hw_uartapp_linectrl2)
+	mxs_reg_32(hw_uartapp_intr)
+	mxs_reg_32(hw_uartapp_data)
+	mxs_reg_32(hw_uartapp_stat)
+	mxs_reg_32(hw_uartapp_debug)
+	mxs_reg_32(hw_uartapp_version)
+	mxs_reg_32(hw_uartapp_autobaud)
+};
+#endif
+
+#define UARTAPP_CTRL0_SFTRST_MASK				(1 << 31)
+#define UARTAPP_CTRL0_CLKGATE_MASK			(1 << 30)
+#define UARTAPP_CTRL0_RUN_MASK				(1 << 29)
+#define UARTAPP_CTRL0_RX_SOURCE_MASK			(1 << 28)
+#define UARTAPP_CTRL0_RXTO_ENABLE_MASK			(1 << 27)
+#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET			16
+#define UARTAPP_CTRL0_RXTIMEOUT_MASK			(0x7FF << 16)
+#define UARTAPP_CTRL0_XFER_COUNT_OFFSET			0
+#define UARTAPP_CTRL0_XFER_COUNT_MASK			0xFFFF
+
+#define UARTAPP_CTRL1_RUN_MASK				(1 << 28)
+
+#define UARTAPP_CTRL1_XFER_COUNT_OFFSET			0
+#define UARTAPP_CTRL1_XFER_COUNT_MASK			0xFFFF
+
+#define UARTAPP_CTRL2_INVERT_RTS_MASK			(1 << 31)
+#define UARTAPP_CTRL2_INVERT_CTS_MASK			(1 << 30)
+#define UARTAPP_CTRL2_INVERT_TX_MASK			(1 << 29)
+#define UARTAPP_CTRL2_INVERT_RX_MASK			(1 << 28)
+#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK			(1 << 27)
+#define UARTAPP_CTRL2_DMAONERR_MASK			(1 << 26)
+#define UARTAPP_CTRL2_TXDMAE_MASK				(1 << 25)
+#define UARTAPP_CTRL2_RXDMAE_MASK				(1 << 24)
+#define UARTAPP_CTRL2_RXIFLSEL_OFFSET			20
+#define UARTAPP_CTRL2_RXIFLSEL_MASK			(0x7 << 20)
+
+#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY		(0x0 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER		(0x1 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF		(0x2 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS		(0x3 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS		(0x4 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID5		(0x5 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID6		(0x6 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID7		(0x7 << 20)
+#define UARTAPP_CTRL2_TXIFLSEL_OFFSET			16
+#define UARTAPP_CTRL2_TXIFLSEL_MASK			(0x7 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_EMPTY			(0x0 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER		(0x1 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF		(0x2 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS		(0x3 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS		(0x4 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_INVALID5		(0x5 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_INVALID6		(0x6 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_INVALID7		(0x7 << 16)
+#define UARTAPP_CTRL2_CTSEN_MASK				(1 << 15)
+#define UARTAPP_CTRL2_RTSEN_MASK				(1 << 14)
+#define UARTAPP_CTRL2_OUT2_MASK				(1 << 13)
+#define UARTAPP_CTRL2_OUT1_MASK				(1 << 12)
+#define UARTAPP_CTRL2_RTS_MASK				(1 << 11)
+#define UARTAPP_CTRL2_DTR_MASK				(1 << 10)
+#define UARTAPP_CTRL2_RXE_MASK				(1 << 9)
+#define UARTAPP_CTRL2_TXE_MASK				(1 << 8)
+#define UARTAPP_CTRL2_LBE_MASK				(1 << 7)
+#define UARTAPP_CTRL2_USE_LCR2_MASK			(1 << 6)
+
+#define UARTAPP_CTRL2_SIRLP_MASK				(1 << 2)
+#define UARTAPP_CTRL2_SIREN_MASK				(1 << 1)
+#define UARTAPP_CTRL2_UARTEN_MASK				0x01
+
+#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET			16
+#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK			(0xFFFF << 16)
+#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET		6
+
+#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET		8
+#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK		(0x3F << 8)
+#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK	0x3F
+
+#define UARTAPP_LINECTRL_SPS_MASK				(1 << 7)
+#define UARTAPP_LINECTRL_WLEN_OFFSET			5
+#define UARTAPP_LINECTRL_WLEN_MASK			(0x03 << 5)
+#define UARTAPP_LINECTRL_WLEN_5BITS			(0x00 << 5)
+#define UARTAPP_LINECTRL_WLEN_6BITS			(0x01 << 5)
+#define UARTAPP_LINECTRL_WLEN_7BITS			(0x02 << 5)
+#define UARTAPP_LINECTRL_WLEN_8BITS			(0x03 << 5)
+
+#define UARTAPP_LINECTRL_FEN_MASK				(1 << 4)
+#define UARTAPP_LINECTRL_STP2_MASK			(1 << 3)
+#define UARTAPP_LINECTRL_EPS_MASK				(1 << 2)
+#define UARTAPP_LINECTRL_PEN_MASK				(1 << 1)
+#define UARTAPP_LINECTRL_BRK_MASK				1
+
+#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET		16
+#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK		(0xFFFF << 16)
+#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET	6
+
+#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET		8
+#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK		(0x3F << 8)
+#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK	0x3F
+
+#define UARTAPP_LINECTRL2_SPS_MASK			(1 << 7)
+#define UARTAPP_LINECTRL2_WLEN_OFFSET			5
+#define UARTAPP_LINECTRL2_WLEN_MASK			(0x03 << 5)
+#define UARTAPP_LINECTRL2_WLEN_5BITS			(0x00 << 5)
+#define UARTAPP_LINECTRL2_WLEN_6BITS			(0x01 << 5)
+#define UARTAPP_LINECTRL2_WLEN_7BITS			(0x02 << 5)
+#define UARTAPP_LINECTRL2_WLEN_8BITS			(0x03 << 5)
+
+#define UARTAPP_LINECTRL2_FEN_MASK			(1 << 4)
+#define UARTAPP_LINECTRL2_STP2_MASK			(1 << 3)
+#define UARTAPP_LINECTRL2_EPS_MASK			(1 << 2)
+#define UARTAPP_LINECTRL2_PEN_MASK			(1 << 1)
+
+#define UARTAPP_INTR_ABDIEN_MASK				(1 << 27)
+#define UARTAPP_INTR_OEIEN_MASK				(1 << 26)
+#define UARTAPP_INTR_BEIEN_MASK				(1 << 25)
+#define UARTAPP_INTR_PEIEN_MASK				(1 << 24)
+#define UARTAPP_INTR_FEIEN_MASK				(1 << 23)
+#define UARTAPP_INTR_RTIEN_MASK				(1 << 22)
+#define UARTAPP_INTR_TXIEN_MASK				(1 << 21)
+#define UARTAPP_INTR_RXIEN_MASK				(1 << 20)
+#define UARTAPP_INTR_DSRMIEN_MASK				(1 << 19)
+#define UARTAPP_INTR_DCDMIEN_MASK				(1 << 18)
+#define UARTAPP_INTR_CTSMIEN_MASK				(1 << 17)
+#define UARTAPP_INTR_RIMIEN_MASK				(1 << 16)
+
+#define UARTAPP_INTR_ABDIS_MASK				(1 << 11)
+#define UARTAPP_INTR_OEIS_MASK				(1 << 10)
+#define UARTAPP_INTR_BEIS_MASK				(1 << 9)
+#define UARTAPP_INTR_PEIS_MASK				(1 << 8)
+#define UARTAPP_INTR_FEIS_MASK				(1 << 7)
+#define UARTAPP_INTR_RTIS_MASK				(1 << 6)
+#define UARTAPP_INTR_TXIS_MASK				(1 << 5)
+#define UARTAPP_INTR_RXIS_MASK				(1 << 4)
+#define UARTAPP_INTR_DSRMIS_MASK				(1 << 3)
+#define UARTAPP_INTR_DCDMIS_MASK				(1 << 2)
+#define UARTAPP_INTR_CTSMIS_MASK				(1 << 1)
+#define UARTAPP_INTR_RIMIS_MASK				0x1
+
+#define UARTAPP_DATA_DATA_OFFSET				0
+#define UARTAPP_DATA_DATA_MASK				0xFFFFFFFF
+#define UARTAPP_STAT_PRESENT_MASK				(1 << 31)
+#define UARTAPP_STAT_PRESENT_UNAVAILABLE		(0x0 << 31)
+#define UARTAPP_STAT_PRESENT_AVAILABLE			(0x1 << 31)
+
+#define UARTAPP_STAT_HISPEED_MASK				(1 << 30)
+#define UARTAPP_STAT_HISPEED_UNAVAILABLE		(0x0 << 30)
+#define UARTAPP_STAT_HISPEED_AVAILABLE			(0x1 << 30)
+
+#define UARTAPP_STAT_BUSY_MASK				(1 << 29)
+#define UARTAPP_STAT_CTS_MASK				(1 << 28)
+#define UARTAPP_STAT_TXFE_MASK				(1 << 27)
+#define UARTAPP_STAT_RXFF_MASK				(1 << 26)
+#define UARTAPP_STAT_TXFF_MASK				(1 << 25)
+#define UARTAPP_STAT_RXFE_MASK				(1 << 24)
+#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET			20
+#define UARTAPP_STAT_RXBYTE_INVALID_MASK		(0xF << 20)
+
+#define UARTAPP_STAT_OERR_MASK				(1 << 19)
+#define UARTAPP_STAT_BERR_MASK				(1 << 18)
+#define UARTAPP_STAT_PERR_MASK				(1 << 17)
+#define UARTAPP_STAT_FERR_MASK				(1 << 16)
+#define UARTAPP_STAT_RXCOUNT_OFFSET				0
+#define UARTAPP_STAT_RXCOUNT_MASK				0xFFFF
+
+#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET			16
+#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK				(0xFFFF << 16)
+
+#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET			10
+#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK				(0x3F << 10)
+
+#define UARTAPP_DEBUG_TXDMARUN_MASK			(1 << 5)
+#define UARTAPP_DEBUG_RXDMARUN_MASK			(1 << 4)
+#define UARTAPP_DEBUG_TXCMDEND_MASK			(1 << 3)
+#define UARTAPP_DEBUG_RXCMDEND_MASK			(1 << 2)
+#define UARTAPP_DEBUG_TXDMARQ_MASK			(1 << 1)
+#define UARTAPP_DEBUG_RXDMARQ_MASK			0x01
+
+#define UARTAPP_VERSION_MAJOR_OFFSET			24
+#define UARTAPP_VERSION_MAJOR_MASK			(0xFF << 24)
+
+#define UARTAPP_VERSION_MINOR_OFFSET			16
+#define UARTAPP_VERSION_MINOR_MASK			(0xFF << 16)
+
+#define UARTAPP_VERSION_STEP_OFFSET				0
+#define UARTAPP_VERSION_STEP_MASK				0xFFFF
+
+#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET			24
+#define UARTAPP_AUTOBAUD_REFCHAR1_MASK				(0xFF << 24)
+
+#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET			16
+#define UARTAPP_AUTOBAUD_REFCHAR0_MASK				(0xFF << 16)
+
+#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK			(1 << 4)
+#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK		(1 << 3)
+#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK		(1 << 2)
+#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK		(1 << 1)
+#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK		0x01
+#endif /* __ARCH_ARM___UARTAPP_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usb.h
new file mode 100644
index 000000000..8313bec78
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usb.h
@@ -0,0 +1,165 @@
+/*
+ * Freescale i.MX28 USB OTG Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __REGS_USB_H__
+#define __REGS_USB_H__
+
+struct mxs_usb_regs {
+	uint32_t		hw_usbctrl_id;			/* 0x000 */
+	uint32_t		hw_usbctrl_hwgeneral;		/* 0x004 */
+	uint32_t		hw_usbctrl_hwhost;		/* 0x008 */
+	uint32_t		hw_usbctrl_hwdevice;		/* 0x00c */
+	uint32_t		hw_usbctrl_hwtxbuf;		/* 0x010 */
+	uint32_t		hw_usbctrl_hwrxbuf;		/* 0x014 */
+
+	uint32_t		reserved1[26];
+
+	uint32_t		hw_usbctrl_gptimer0ld;		/* 0x080 */
+	uint32_t		hw_usbctrl_gptimer0ctrl;	/* 0x084 */
+	uint32_t		hw_usbctrl_gptimer1ld;		/* 0x088 */
+	uint32_t		hw_usbctrl_gptimer1ctrl;	/* 0x08c */
+	uint32_t		hw_usbctrl_sbuscfg;		/* 0x090 */
+
+	uint32_t		reserved2[27];
+
+	uint32_t		hw_usbctrl_caplength;		/* 0x100 */
+	uint32_t		hw_usbctrl_hcsparams;		/* 0x104 */
+	uint32_t		hw_usbctrl_hccparams;		/* 0x108 */
+
+	uint32_t		reserved3[5];
+
+	uint32_t		hw_usbctrl_dciversion;		/* 0x120 */
+	uint32_t		hw_usbctrl_dccparams;		/* 0x124 */
+
+	uint32_t		reserved4[6];
+
+	uint32_t		hw_usbctrl_usbcmd;		/* 0x140 */
+	uint32_t		hw_usbctrl_usbsts;		/* 0x144 */
+	uint32_t		hw_usbctrl_usbintr;		/* 0x148 */
+	uint32_t		hw_usbctrl_frindex;		/* 0x14c */
+
+	uint32_t		reserved5;
+
+	union {
+		uint32_t	hw_usbctrl_periodiclistbase;	/* 0x154 */
+		uint32_t	hw_usbctrl_deviceaddr;		/* 0x154 */
+	};
+	union {
+		uint32_t	hw_usbctrl_asynclistaddr;	/* 0x158 */
+		uint32_t	hw_usbctrl_endpointlistaddr;	/* 0x158 */
+	};
+
+	uint32_t		hw_usbctrl_ttctrl;		/* 0x15c */
+	uint32_t		hw_usbctrl_burstsize;		/* 0x160 */
+	uint32_t		hw_usbctrl_txfilltuning;	/* 0x164 */
+
+	uint32_t		reserved6;
+
+	uint32_t		hw_usbctrl_ic_usb;		/* 0x16c */
+	uint32_t		hw_usbctrl_ulpi;		/* 0x170 */
+
+	uint32_t		reserved7;
+
+	uint32_t		hw_usbctrl_endptnak;		/* 0x178 */
+	uint32_t		hw_usbctrl_endptnaken;		/* 0x17c */
+
+	uint32_t		reserved8;
+
+	uint32_t		hw_usbctrl_portsc1;		/* 0x184 */
+
+	uint32_t		reserved9[7];
+
+	uint32_t		hw_usbctrl_otgsc;		/* 0x1a4 */
+	uint32_t		hw_usbctrl_usbmode;		/* 0x1a8 */
+	uint32_t		hw_usbctrl_endptsetupstat;	/* 0x1ac */
+	uint32_t		hw_usbctrl_endptprime;		/* 0x1b0 */
+	uint32_t		hw_usbctrl_endptflush;		/* 0x1b4 */
+	uint32_t		hw_usbctrl_endptstat;		/* 0x1b8 */
+	uint32_t		hw_usbctrl_endptcomplete;	/* 0x1bc */
+	uint32_t		hw_usbctrl_endptctrl0;		/* 0x1c0 */
+	uint32_t		hw_usbctrl_endptctrl1;		/* 0x1c4 */
+	uint32_t		hw_usbctrl_endptctrl2;		/* 0x1c8 */
+	uint32_t		hw_usbctrl_endptctrl3;		/* 0x1cc */
+	uint32_t		hw_usbctrl_endptctrl4;		/* 0x1d0 */
+	uint32_t		hw_usbctrl_endptctrl5;		/* 0x1d4 */
+	uint32_t		hw_usbctrl_endptctrl6;		/* 0x1d8 */
+	uint32_t		hw_usbctrl_endptctrl7;		/* 0x1dc */
+};
+
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
+
+#define	HW_USBCTRL_ID_CIVERSION_OFFSET		29
+#define	HW_USBCTRL_ID_CIVERSION_MASK		(0x7 << 29)
+#define	HW_USBCTRL_ID_VERSION_OFFSET		25
+#define	HW_USBCTRL_ID_VERSION_MASK		(0xf << 25)
+#define	HW_USBCTRL_ID_REVISION_OFFSET		21
+#define	HW_USBCTRL_ID_REVISION_MASK		(0xf << 21)
+#define	HW_USBCTRL_ID_TAG_OFFSET		16
+#define	HW_USBCTRL_ID_TAG_MASK			(0x1f << 16)
+#define	HW_USBCTRL_ID_NID_OFFSET		8
+#define	HW_USBCTRL_ID_NID_MASK			(0x3f << 8)
+#define	HW_USBCTRL_ID_ID_OFFSET			0
+#define	HW_USBCTRL_ID_ID_MASK			(0x3f << 0)
+
+#define	HW_USBCTRL_HWGENERAL_SM_OFFSET		9
+#define	HW_USBCTRL_HWGENERAL_SM_MASK		(0x3 << 9)
+#define	HW_USBCTRL_HWGENERAL_PHYM_OFFSET	6
+#define	HW_USBCTRL_HWGENERAL_PHYM_MASK		(0x7 << 6)
+#define	HW_USBCTRL_HWGENERAL_PHYW_OFFSET	4
+#define	HW_USBCTRL_HWGENERAL_PHYW_MASK		(0x3 << 4)
+#define	HW_USBCTRL_HWGENERAL_BWT		(1 << 3)
+#define	HW_USBCTRL_HWGENERAL_CLKC_OFFSET	1
+#define	HW_USBCTRL_HWGENERAL_CLKC_MASK		(0x3 << 1)
+#define	HW_USBCTRL_HWGENERAL_RT			(1 << 0)
+
+#define	HW_USBCTRL_HWHOST_TTPER_OFFSET		24
+#define	HW_USBCTRL_HWHOST_TTPER_MASK		(0xff << 24)
+#define	HW_USBCTRL_HWHOST_TTASY_OFFSET		16
+#define	HW_USBCTRL_HWHOST_TTASY_MASK		(0xff << 19)
+#define	HW_USBCTRL_HWHOST_NPORT_OFFSET		1
+#define	HW_USBCTRL_HWHOST_NPORT_MASK		(0x7 << 1)
+#define	HW_USBCTRL_HWHOST_HC			(1 << 0)
+
+#define	HW_USBCTRL_HWDEVICE_DEVEP_OFFSET	1
+#define	HW_USBCTRL_HWDEVICE_DEVEP_MASK		(0x1f << 1)
+#define	HW_USBCTRL_HWDEVICE_DC			(1 << 0)
+
+#define	HW_USBCTRL_HWTXBUF_TXLCR		(1 << 31)
+#define	HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET	16
+#define	HW_USBCTRL_HWTXBUF_TXCHANADD_MASK	(0xff << 16)
+#define	HW_USBCTRL_HWTXBUF_TXADD_OFFSET		8
+#define	HW_USBCTRL_HWTXBUF_TXADD_MASK		(0xff << 8)
+#define	HW_USBCTRL_HWTXBUF_TXBURST_OFFSET	0
+#define	HW_USBCTRL_HWTXBUF_TXBURST_MASK		0xff
+
+#define	HW_USBCTRL_HWRXBUF_RXADD_OFFSET		8
+#define	HW_USBCTRL_HWRXBUF_RXADD_MASK		(0xff << 8)
+#define	HW_USBCTRL_HWRXBUF_RXBURST_OFFSET	0
+#define	HW_USBCTRL_HWRXBUF_RXBURST_MASK		0xff
+
+#define	HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET	0
+#define	HW_USBCTRL_GPTIMERLD_GPTLD_MASK		0xffffff
+
+#define	HW_USBCTRL_GPTIMERCTRL_GPTRUN		(1 << 31)
+#define	HW_USBCTRL_GPTIMERCTRL_GPTRST		(1 << 30)
+#define	HW_USBCTRL_GPTIMERCTRL_GPTMODE		(1 << 24)
+#define	HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET	0
+#define	HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK	0xffffff
+
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET	0
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_MASK	0x7
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR	0x0
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4	0x1
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8	0x2
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16	0x3
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4	0x5
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8	0x6
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16	0x7
+
+#endif	/* __REGS_USB_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usbphy.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usbphy.h
new file mode 100644
index 000000000..eabefc644
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/regs-usbphy.h
@@ -0,0 +1,138 @@
+/*
+ * Freescale i.MX28 USB PHY Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+struct mxs_usbphy_regs {
+	mxs_reg_32(hw_usbphy_pwd)
+	mxs_reg_32(hw_usbphy_tx)
+	mxs_reg_32(hw_usbphy_rx)
+	mxs_reg_32(hw_usbphy_ctrl)
+	mxs_reg_32(hw_usbphy_status)
+	mxs_reg_32(hw_usbphy_debug)
+	mxs_reg_32(hw_usbphy_debug0_status)
+	mxs_reg_32(hw_usbphy_debug1)
+	mxs_reg_32(hw_usbphy_version)
+	mxs_reg_32(hw_usbphy_ip)
+};
+
+#define	USBPHY_PWD_RXPWDRX				(1 << 20)
+#define	USBPHY_PWD_RXPWDDIFF				(1 << 19)
+#define	USBPHY_PWD_RXPWD1PT1				(1 << 18)
+#define	USBPHY_PWD_RXPWDENV				(1 << 17)
+#define	USBPHY_PWD_TXPWDV2I				(1 << 12)
+#define	USBPHY_PWD_TXPWDIBIAS				(1 << 11)
+#define	USBPHY_PWD_TXPWDFS				(1 << 10)
+
+#define	USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET		26
+#define	USBPHY_TX_USBPHY_TX_EDGECTRL_MASK		(0x7 << 26)
+#define	USBPHY_TX_USBPHY_TX_SYNC_INVERT			(1 << 25)
+#define	USBPHY_TX_USBPHY_TX_SYNC_MUX			(1 << 24)
+#define	USBPHY_TX_TXENCAL45DP				(1 << 21)
+#define	USBPHY_TX_TXCAL45DP_OFFSET			16
+#define	USBPHY_TX_TXCAL45DP_MASK			(0xf << 16)
+#define	USBPHY_TX_TXENCAL45DM				(1 << 13)
+#define	USBPHY_TX_TXCAL45DM_OFFSET			8
+#define	USBPHY_TX_TXCAL45DM_MASK			(0xf << 8)
+#define	USBPHY_TX_D_CAL_OFFSET				0
+#define	USBPHY_TX_D_CAL_MASK				0xf
+
+#define	USBPHY_RX_RXDBYPASS				(1 << 22)
+#define	USBPHY_RX_DISCONADJ_OFFSET			4
+#define	USBPHY_RX_DISCONADJ_MASK			(0x7 << 4)
+#define	USBPHY_RX_ENVADJ_OFFSET				0
+#define	USBPHY_RX_ENVADJ_MASK				0x7
+
+#define	USBPHY_CTRL_SFTRST				(1 << 31)
+#define	USBPHY_CTRL_CLKGATE				(1 << 30)
+#define	USBPHY_CTRL_UTMI_SUSPENDM			(1 << 29)
+#define	USBPHY_CTRL_HOST_FORCE_LS_SE0			(1 << 28)
+#define	USBPHY_CTRL_ENAUTOSET_USBCLKS			(1 << 26)
+#define	USBPHY_CTRL_ENAUTOCLR_USBCLKGATE		(1 << 25)
+#define	USBPHY_CTRL_FSDLL_RST_EN			(1 << 24)
+#define	USBPHY_CTRL_ENVBUSCHG_WKUP			(1 << 23)
+#define	USBPHY_CTRL_ENIDCHG_WKUP			(1 << 22)
+#define	USBPHY_CTRL_ENDPDMCHG_WKUP			(1 << 21)
+#define	USBPHY_CTRL_ENAUTOCLR_PHY_PWD			(1 << 20)
+#define	USBPHY_CTRL_ENAUTOCLR_CLKGATE			(1 << 19)
+#define	USBPHY_CTRL_ENAUTO_PWRON_PLL			(1 << 18)
+#define	USBPHY_CTRL_WAKEUP_IRQ				(1 << 17)
+#define	USBPHY_CTRL_ENIRQWAKEUP				(1 << 16)
+#define	USBPHY_CTRL_ENUTMILEVEL3			(1 << 15)
+#define	USBPHY_CTRL_ENUTMILEVEL2			(1 << 14)
+#define	USBPHY_CTRL_DATA_ON_LRADC			(1 << 13)
+#define	USBPHY_CTRL_DEVPLUGIN_IRQ			(1 << 12)
+#define	USBPHY_CTRL_ENIRQDEVPLUGIN			(1 << 11)
+#define	USBPHY_CTRL_RESUME_IRQ				(1 << 10)
+#define	USBPHY_CTRL_ENIRQRESUMEDETECT			(1 << 9)
+#define	USBPHY_CTRL_RESUMEIRQSTICKY			(1 << 8)
+#define	USBPHY_CTRL_ENOTGIDDETECT			(1 << 7)
+#define	USBPHY_CTRL_DEVPLUGIN_POLARITY			(1 << 5)
+#define	USBPHY_CTRL_ENDEVPLUGINDETECT			(1 << 4)
+#define	USBPHY_CTRL_HOSTDISCONDETECT_IRQ		(1 << 3)
+#define	USBPHY_CTRL_ENIRQHOSTDISCON			(1 << 2)
+#define	USBPHY_CTRL_ENHOSTDISCONDETECT			(1 << 1)
+
+#define	USBPHY_STATUS_RESUME_STATUS			(1 << 10)
+#define	USBPHY_STATUS_OTGID_STATUS			(1 << 8)
+#define	USBPHY_STATUS_DEVPLUGIN_STATUS			(1 << 6)
+#define	USBPHY_STATUS_HOSTDISCONDETECT_STATUS		(1 << 3)
+
+#define	USBPHY_DEBUG_CLKGATE				(1 << 30)
+#define	USBPHY_DEBUG_HOST_RESUME_DEBUG			(1 << 29)
+#define	USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET		25
+#define	USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK		(0xf << 25)
+#define	USBPHY_DEBUG_ENSQUELCHRESET			(1 << 24)
+#define	USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET		16
+#define	USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK		(0x1f << 16)
+#define	USBPHY_DEBUG_ENTX2RXCOUNT			(1 << 12)
+#define	USBPHY_DEBUG_TX2RXCOUNT_OFFSET			8
+#define	USBPHY_DEBUG_TX2RXCOUNT_MASK			(0xf << 8)
+#define	USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET		4
+#define	USBPHY_DEBUG_ENHSTPULLDOWN_MASK			(0x3 << 4)
+#define	USBPHY_DEBUG_HSTPULLDOWN_OFFSET			2
+#define	USBPHY_DEBUG_HSTPULLDOWN_MASK			(0x3 << 2)
+#define	USBPHY_DEBUG_DEBUG_INTERFACE_HOLD		(1 << 1)
+#define	USBPHY_DEBUG_OTGIDPIDLOCK			(1 << 0)
+
+#define	USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET	26
+#define	USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK		(0x3f << 26)
+#define	USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET	16
+#define	USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK		(0x3ff << 16)
+#define	USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET		0
+#define	USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK		0xffff
+
+#define	USBPHY_DEBUG1_ENTAILADJVD_OFFSET		13
+#define	USBPHY_DEBUG1_ENTAILADJVD_MASK			(0x3 << 13)
+#define	USBPHY_DEBUG1_ENTX2TX				(1 << 12)
+#define	USBPHY_DEBUG1_DBG_ADDRESS_OFFSET		0
+#define	USBPHY_DEBUG1_DBG_ADDRESS_MASK			0xf
+
+#define	USBPHY_VERSION_MAJOR_MASK			(0xff << 24)
+#define	USBPHY_VERSION_MAJOR_OFFSET			24
+#define	USBPHY_VERSION_MINOR_MASK			(0xff << 16)
+#define	USBPHY_VERSION_MINOR_OFFSET			16
+#define	USBPHY_VERSION_STEP_MASK			0xffff
+#define	USBPHY_VERSION_STEP_OFFSET			0
+
+#define	USBPHY_IP_DIV_SEL_OFFSET			23
+#define	USBPHY_IP_DIV_SEL_MASK				(0x3 << 23)
+#define	USBPHY_IP_LFR_SEL_OFFSET			21
+#define	USBPHY_IP_LFR_SEL_MASK				(0x3 << 21)
+#define	USBPHY_IP_CP_SEL_OFFSET				19
+#define	USBPHY_IP_CP_SEL_MASK				(0x3 << 19)
+#define	USBPHY_IP_TSTI_TX_DP				(1 << 18)
+#define	USBPHY_IP_TSTI_TX_DM				(1 << 17)
+#define	USBPHY_IP_ANALOG_TESTMODE			(1 << 16)
+#define	USBPHY_IP_EN_USB_CLKS				(1 << 2)
+#define	USBPHY_IP_PLL_LOCKED				(1 << 1)
+#define	USBPHY_IP_PLL_POWER				(1 << 0)
+
+#endif	/* __REGS_USBPHY_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/sys_proto.h
new file mode 100644
index 000000000..09dfc90a9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -0,0 +1,82 @@
+/*
+ * Freescale i.MX23/i.MX28 specific functions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SYS_PROTO_H__
+#define __SYS_PROTO_H__
+
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg,
+		       uint32_t mask,
+		       unsigned int timeout);
+int mxs_wait_mask_clr(struct mxs_register_32 *reg,
+		       uint32_t mask,
+		       unsigned int timeout);
+
+int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
+
+#ifdef CONFIG_SPL_BUILD
+
+#if defined(CONFIG_MX23)
+#include <asm/arch/iomux-mx23.h>
+#elif defined(CONFIG_MX28)
+#include <asm/arch/iomux-mx28.h>
+#endif
+
+void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
+			 const iomux_cfg_t *iomux_setup,
+			 const unsigned int iomux_size);
+#endif
+
+struct mxs_pair {
+	uint8_t	boot_pads;
+	uint8_t boot_mask;
+	const char *mode;
+};
+
+static const struct mxs_pair mxs_boot_modes[] = {
+#if defined(CONFIG_MX23)
+	{ 0x00, 0x0f, "USB" },
+	{ 0x01, 0x1f, "I2C, master" },
+	{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
+	{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
+	{ 0x04, 0x1f, "NAND" },
+	{ 0x06, 0x1f, "JTAG" },
+	{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
+	{ 0x09, 0x1f, "SSP SD/MMC #0" },
+	{ 0x0a, 0x1f, "SSP SD/MMC #1" },
+	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
+#elif defined(CONFIG_MX28)
+	{ 0x00, 0x0f, "USB #0" },
+	{ 0x01, 0x1f, "I2C #0, master, 3V3" },
+	{ 0x11, 0x1f, "I2C #0, master, 1V8" },
+	{ 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
+	{ 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
+	{ 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
+	{ 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
+	{ 0x04, 0x1f, "NAND, 3V3" },
+	{ 0x14, 0x1f, "NAND, 1V8" },
+	{ 0x06, 0x1f, "JTAG" },
+	{ 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
+	{ 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
+	{ 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
+	{ 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
+	{ 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
+	{ 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
+	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
+#endif
+};
+
+struct mxs_spl_data {
+	uint8_t		boot_mode_idx;
+	uint32_t	mem_dram_size;
+};
+
+int mxs_dram_init(void);
+
+#endif	/* __SYS_PROTO_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/gpio.h
new file mode 100644
index 000000000..311758ae1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/gpio.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __NMK_GPIO_H__
+#define __NMK_GPIO_H__
+
+/*
+ * These functions are called from the soft-i2c driver, but
+ * are also used by board files to set output bits.
+ */
+
+enum nmk_af { /* alternate function settings */
+	GPIO_GPIO = 0,
+	GPIO_ALT_A,
+	GPIO_ALT_B,
+	GPIO_ALT_C
+};
+
+extern void nmk_gpio_af(int gpio, int alternate_function);
+extern void nmk_gpio_dir(int gpio, int dir);
+extern void nmk_gpio_set(int gpio, int val);
+extern int nmk_gpio_get(int gpio);
+
+#endif /* __NMK_GPIO_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/mtu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/mtu.h
new file mode 100644
index 000000000..f89f24224
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-nomadik/mtu.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MTU_H
+#define __ASM_ARCH_MTU_H
+
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+
+#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
+#define MTU_RIS		0x04	/* Raw interrupt status */
+#define MTU_MIS		0x08	/* Masked interrupt status */
+#define MTU_ICR		0x0C	/* Interrupt clear register */
+
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
+#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
+#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
+#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */
+
+/* bits for the control register */
+#define MTU_CRn_ENA		0x80
+#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK	0x0c
+#define MTU_CRn_PRESCALE_1		0x00
+#define MTU_CRn_PRESCALE_16		0x04
+#define MTU_CRn_PRESCALE_256		0x08
+#define MTU_CRn_32BITS		0x02
+#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/
+
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR	0xff0
+#define MTU_ITOP	0xff4
+
+#define MTU_PERIPH_ID0	0xfe0
+#define MTU_PERIPH_ID1	0xfe4
+#define MTU_PERIPH_ID2	0xfe8
+#define MTU_PERIPH_ID3	0xfeC
+
+#define MTU_PCELL0	0xff0
+#define MTU_PCELL1	0xff4
+#define MTU_PCELL2	0xff8
+#define MTU_PCELL3	0xffC
+
+#endif /* __ASM_ARCH_MTU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h
new file mode 100644
index 000000000..9d001ff2a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/am35x_def.h
@@ -0,0 +1,70 @@
+/*
+ * am35x_def.h - TI's AM35x specific definitions.
+ *
+ * Based on arch/arm/include/asm/arch-omap3/cpu.h
+ *
+ * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ *
+ * Copyright (c) 2010 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _AM35X_DEF_H_
+#define _AM35X_DEF_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+
+/* LVL_INTR_CLEAR bits */
+#define USBOTGSS_INT_CLR	(1 << 4)
+
+/* IP_SW_RESET bits */
+#define USBOTGSS_SW_RST		(1 << 0)	/* reset USBOTG */
+#define CPGMACSS_SW_RST		(1 << 1)	/* reset CPGMAC */
+
+/* DEVCONF2 bits */
+#define CONF2_PHY_GPIOMODE	(1 << 23)
+#define CONF2_OTGMODE		(3 << 14)
+#define CONF2_NO_OVERRIDE	(0 << 14)
+#define CONF2_FORCE_HOST	(1 << 14)
+#define CONF2_FORCE_DEVICE	(2 << 14)
+#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
+#define CONF2_SESENDEN		(1 << 13)
+#define CONF2_VBDTCTEN		(1 << 12)
+#define CONF2_REFFREQ_24MHZ	(2 << 8)
+#define CONF2_REFFREQ_26MHZ	(7 << 8)
+#define CONF2_REFFREQ_13MHZ	(6 << 8)
+#define CONF2_REFFREQ		(0xf << 8)
+#define CONF2_PHYCLKGD		(1 << 7)
+#define CONF2_VBUSSENSE		(1 << 6)
+#define CONF2_PHY_PLLON		(1 << 5)
+#define CONF2_RESET		(1 << 4)
+#define CONF2_PHYPWRDN		(1 << 3)
+#define CONF2_OTGPWRDN		(1 << 2)
+#define CONF2_DATPOL		(1 << 1)
+
+/* General register mappings of system control module */
+#define AM35X_SCM_GEN_BASE	0x48002270
+struct am35x_scm_general {
+	u32 res1[0xC4];		/* 0x000 - 0x30C */
+	u32 devconf2;		/* 0x310 */
+	u32 devconf3;		/* 0x314 */
+	u32 res2[0x2];		/* 0x318 - 0x31C */
+	u32 cba_priority;	/* 0x320 */
+	u32 lvl_intr_clr;	/* 0x324 */
+	u32 ip_sw_reset;	/* 0x328 */
+	u32 ipss_clk_ctrl;	/* 0x32C */
+};
+#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE)
+
+#define AM35XX_IPSS_USBOTGSS_BASE	0x5C040000
+
+#endif /*__ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#endif /* _AM35X_DEF_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clock.h
new file mode 100644
index 000000000..1912cc9a6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clock.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _CLOCKS_H_
+#define _CLOCKS_H_
+
+#define LDELAY		12000000
+
+#define S12M		12000000
+#define S13M		13000000
+#define S19_2M		19200000
+#define S24M		24000000
+#define S26M		26000000
+#define S38_4M		38400000
+
+#define FCK_IVA2_ON	0x00000001
+#define FCK_CORE1_ON	0x03fffe29
+#define ICK_CORE1_ON	0x3ffffffb
+#define ICK_CORE2_ON	0x0000001f
+#define FCK_WKUP_ON	0x000000e9
+#define ICK_WKUP_ON	0x0000003f
+#define FCK_DSS_ON	0x00000005
+#define ICK_DSS_ON	0x00000001
+#define FCK_CAM_ON	0x00000001
+#define ICK_CAM_ON	0x00000001
+
+/* Used to index into DPLL parameter tables */
+typedef struct {
+	unsigned int m;
+	unsigned int n;
+	unsigned int fsel;
+	unsigned int m2;
+} dpll_param;
+
+struct dpll_per_36x_param {
+	unsigned int sys_clk;
+	unsigned int m;
+	unsigned int n;
+	unsigned int m2;
+	unsigned int m3;
+	unsigned int m4;
+	unsigned int m5;
+	unsigned int m6;
+	unsigned int m2div;
+};
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param *get_mpu_dpll_param(void);
+extern dpll_param *get_iva_dpll_param(void);
+extern dpll_param *get_core_dpll_param(void);
+extern dpll_param *get_per_dpll_param(void);
+extern dpll_param *get_per2_dpll_param(void);
+
+extern dpll_param *get_36x_mpu_dpll_param(void);
+extern dpll_param *get_36x_iva_dpll_param(void);
+extern dpll_param *get_36x_core_dpll_param(void);
+extern dpll_param *get_36x_per_dpll_param(void);
+extern dpll_param *get_36x_per2_dpll_param(void);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h
new file mode 100644
index 000000000..df73c4b2e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/clocks_omap3.h
@@ -0,0 +1,348 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _CLOCKS_OMAP3_H_
+#define _CLOCKS_OMAP3_H_
+
+#define PLL_STOP		1	/* PER & IVA */
+#define PLL_LOW_POWER_BYPASS	5	/* MPU, IVA & CORE */
+#define PLL_FAST_RELOCK_BYPASS	6	/* CORE */
+#define PLL_LOCK		7	/* MPU, IVA, CORE & PER */
+
+/*
+ * The following configurations are OPP and SysClk value independant
+ * and hence are defined here. All the other DPLL related values are
+ * tabulated in lowlevel_init.S.
+ */
+
+/* CORE DPLL */
+#define CORE_M3X2	2	/* 332MHz : CM_CLKSEL1_EMU */
+#define CORE_SSI_DIV	3	/* 221MHz : CM_CLKSEL_CORE */
+#define CORE_FUSB_DIV	2	/* 41.5MHz: */
+#define CORE_L4_DIV	2	/* 83MHz  : L4 */
+#define CORE_L3_DIV	2	/* 166MHz : L3 {DDR} */
+#define GFX_DIV		2	/* 83MHz  : CM_CLKSEL_GFX */
+#define GFX_DIV_36X	5	/* 200MHz : CM_CLKSEL_GFX */
+#define WKUP_RSM	2	/* 41.5MHz: CM_CLKSEL_WKUP */
+
+/* PER DPLL */
+#define PER_M6X2	3	/* 288MHz: CM_CLKSEL1_EMU */
+#define PER_M5X2	4	/* 216MHz: CM_CLKSEL_CAM */
+#define PER_M4X2	2	/* 432MHz: CM_CLKSEL_DSS-dss1 */
+#define PER_M3X2	16	/* 54MHz : CM_CLKSEL_DSS-tv */
+
+#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
+
+/* MPU DPLL */
+
+#define MPU_M_12_ES1		0x0FE
+#define MPU_N_12_ES1		0x07
+#define MPU_FSEL_12_ES1		0x05
+#define MPU_M2_12_ES1		0x01
+
+#define MPU_M_12_ES2		0x0FA
+#define MPU_N_12_ES2		0x05
+#define MPU_FSEL_12_ES2		0x07
+#define MPU_M2_ES2		0x01
+
+#define MPU_M_12		0x085
+#define MPU_N_12		0x05
+#define MPU_FSEL_12		0x07
+#define MPU_M2_12		0x01
+
+#define MPU_M_13_ES1		0x17D
+#define MPU_N_13_ES1		0x0C
+#define MPU_FSEL_13_ES1		0x03
+#define MPU_M2_13_ES1		0x01
+
+#define MPU_M_13_ES2		0x258
+#define MPU_N_13_ES2		0x0C
+#define MPU_FSEL_13_ES2		0x03
+#define MPU_M2_13_ES2		0x01
+
+#define MPU_M_13		0x10A
+#define MPU_N_13		0x0C
+#define MPU_FSEL_13		0x03
+#define MPU_M2_13		0x01
+
+#define MPU_M_19P2_ES1		0x179
+#define MPU_N_19P2_ES1		0x12
+#define MPU_FSEL_19P2_ES1	0x04
+#define MPU_M2_19P2_ES1		0x01
+
+#define MPU_M_19P2_ES2		0x271
+#define MPU_N_19P2_ES2		0x17
+#define MPU_FSEL_19P2_ES2	0x03
+#define MPU_M2_19P2_ES2		0x01
+
+#define MPU_M_19P2		0x14C
+#define MPU_N_19P2		0x17
+#define MPU_FSEL_19P2		0x03
+#define MPU_M2_19P2		0x01
+
+#define MPU_M_26_ES1		0x17D
+#define MPU_N_26_ES1		0x19
+#define MPU_FSEL_26_ES1		0x03
+#define MPU_M2_26_ES1		0x01
+
+#define MPU_M_26_ES2		0x0FA
+#define MPU_N_26_ES2		0x0C
+#define MPU_FSEL_26_ES2		0x07
+#define MPU_M2_26_ES2		0x01
+
+#define MPU_M_26		0x085
+#define MPU_N_26		0x0C
+#define MPU_FSEL_26		0x07
+#define MPU_M2_26		0x01
+
+#define MPU_M_38P4_ES1		0x1FA
+#define MPU_N_38P4_ES1		0x32
+#define MPU_FSEL_38P4_ES1	0x03
+#define MPU_M2_38P4_ES1		0x01
+
+#define MPU_M_38P4_ES2		0x271
+#define MPU_N_38P4_ES2		0x2F
+#define MPU_FSEL_38P4_ES2	0x03
+#define MPU_M2_38P4_ES2		0x01
+
+#define MPU_M_38P4		0x14C
+#define MPU_N_38P4		0x2F
+#define MPU_FSEL_38P4		0x03
+#define MPU_M2_38P4		0x01
+
+/* IVA DPLL */
+
+#define IVA_M_12_ES1		0x07D
+#define IVA_N_12_ES1		0x05
+#define IVA_FSEL_12_ES1		0x07
+#define IVA_M2_12_ES1		0x01
+
+#define IVA_M_12_ES2		0x0B4
+#define IVA_N_12_ES2		0x05
+#define IVA_FSEL_12_ES2		0x07
+#define IVA_M2_12_ES2		0x01
+
+#define IVA_M_12		0x085
+#define IVA_N_12		0x05
+#define IVA_FSEL_12		0x07
+#define IVA_M2_12		0x01
+
+#define IVA_M_13_ES1		0x0FA
+#define IVA_N_13_ES1		0x0C
+#define IVA_FSEL_13_ES1		0x03
+#define IVA_M2_13_ES1		0x01
+
+#define IVA_M_13_ES2		0x168
+#define IVA_N_13_ES2		0x0C
+#define IVA_FSEL_13_ES2		0x03
+#define IVA_M2_13_ES2		0x01
+
+#define IVA_M_13		0x10A
+#define IVA_N_13		0x0C
+#define IVA_FSEL_13		0x03
+#define IVA_M2_13		0x01
+
+#define IVA_M_19P2_ES1		0x082
+#define IVA_N_19P2_ES1		0x09
+#define IVA_FSEL_19P2_ES1	0x07
+#define IVA_M2_19P2_ES1		0x01
+
+#define IVA_M_19P2_ES2		0x0E1
+#define IVA_N_19P2_ES2		0x0B
+#define IVA_FSEL_19P2_ES2	0x06
+#define IVA_M2_19P2_ES2		0x01
+
+#define IVA_M_19P2		0x14C
+#define IVA_N_19P2		0x17
+#define IVA_FSEL_19P2		0x03
+#define IVA_M2_19P2		0x01
+
+#define IVA_M_26_ES1		0x07D
+#define IVA_N_26_ES1		0x0C
+#define IVA_FSEL_26_ES1		0x07
+#define IVA_M2_26_ES1		0x01
+
+#define IVA_M_26_ES2		0x0B4
+#define IVA_N_26_ES2		0x0C
+#define IVA_FSEL_26_ES2		0x07
+#define IVA_M2_26_ES2		0x01
+
+#define IVA_M_26		0x085
+#define IVA_N_26		0x0C
+#define IVA_FSEL_26		0x07
+#define IVA_M2_26		0x01
+
+#define IVA_M_38P4_ES1		0x13F
+#define IVA_N_38P4_ES1		0x30
+#define IVA_FSEL_38P4_ES1	0x03
+#define IVA_M2_38P4_ES1		0x01
+
+#define IVA_M_38P4_ES2		0x0E1
+#define IVA_N_38P4_ES2		0x17
+#define IVA_FSEL_38P4_ES2	0x06
+#define IVA_M2_38P4_ES2		0x01
+
+#define IVA_M_38P4		0x14C
+#define IVA_N_38P4		0x2F
+#define IVA_FSEL_38P4		0x03
+#define IVA_M2_38P4		0x01
+
+/* CORE DPLL */
+
+#define CORE_M_12		0xA6
+#define CORE_N_12		0x05
+#define CORE_FSEL_12		0x07
+#define CORE_M2_12		0x01	/* M3 of 2 */
+
+#define CORE_M_12_ES1		0x19F
+#define CORE_N_12_ES1		0x0E
+#define CORE_FSL_12_ES1		0x03
+#define CORE_M2_12_ES1		0x1	/* M3 of 2 */
+
+#define CORE_M_13		0x14C
+#define CORE_N_13		0x0C
+#define CORE_FSEL_13		0x03
+#define CORE_M2_13		0x01	/* M3 of 2 */
+
+#define CORE_M_13_ES1		0x1B2
+#define CORE_N_13_ES1		0x10
+#define CORE_FSL_13_ES1		0x03
+#define CORE_M2_13_ES1		0x01	/* M3 of 2 */
+
+#define CORE_M_19P2		0x19F
+#define CORE_N_19P2		0x17
+#define CORE_FSEL_19P2		0x03
+#define CORE_M2_19P2		0x01	/* M3 of 2 */
+
+#define CORE_M_19P2_ES1		0x19F
+#define CORE_N_19P2_ES1		0x17
+#define CORE_FSL_19P2_ES1	0x03
+#define CORE_M2_19P2_ES1	0x01	/* M3 of 2 */
+
+#define CORE_M_26		0xA6
+#define CORE_N_26		0x0C
+#define CORE_FSEL_26		0x07
+#define CORE_M2_26		0x01	/* M3 of 2 */
+
+#define CORE_M_26_ES1		0x1B2
+#define CORE_N_26_ES1		0x21
+#define CORE_FSL_26_ES1		0x03
+#define CORE_M2_26_ES1		0x01	/* M3 of 2 */
+
+#define CORE_M_38P4		0x19F
+#define CORE_N_38P4		0x2F
+#define CORE_FSEL_38P4		0x03
+#define CORE_M2_38P4		0x01	/* M3 of 2 */
+
+#define CORE_M_38P4_ES1		0x19F
+#define CORE_N_38P4_ES1		0x2F
+#define CORE_FSL_38P4_ES1	0x03
+#define CORE_M2_38P4_ES1	0x01	/* M3 of 2 */
+
+/* PER DPLL */
+
+#define PER_M_12		0xD8
+#define PER_N_12		0x05
+#define PER_FSEL_12		0x07
+#define PER_M2_12		0x09
+
+#define PER_M_13		0x1B0
+#define PER_N_13		0x0C
+#define PER_FSEL_13		0x03
+#define PER_M2_13		0x09
+
+#define PER_M_19P2		0xE1
+#define PER_N_19P2		0x09
+#define PER_FSEL_19P2		0x07
+#define PER_M2_19P2		0x09
+
+#define PER_M_26		0xD8
+#define PER_N_26		0x0C
+#define PER_FSEL_26		0x07
+#define PER_M2_26		0x09
+
+#define PER_M_38P4		0xE1
+#define PER_N_38P4		0x13
+#define PER_FSEL_38P4		0x07
+#define PER_M2_38P4		0x09
+
+/* PER2 DPLL */
+#define PER2_M_12		0x78
+#define PER2_N_12		0x0B
+#define PER2_FSEL_12		0x03
+#define PER2_M2_12		0x01
+
+#define PER2_M_13		0x78
+#define PER2_N_13		0x0C
+#define PER2_FSEL_13		0x03
+#define PER2_M2_13		0x01
+
+#define PER2_M_19P2		0x2EE
+#define PER2_N_19P2		0x0B
+#define PER2_FSEL_19P2		0x06
+#define PER2_M2_19P2		0x0A
+
+#define PER2_M_26		0x78
+#define PER2_N_26		0x0C
+#define PER2_FSEL_26		0x03
+#define PER2_M2_26		0x01
+
+#define PER2_M_38P4		0x2EE
+#define PER2_N_38P4		0x0B
+#define PER2_FSEL_38P4		0x06
+#define PER2_M2_38P4		0x0A
+
+/* 36XX PER DPLL */
+
+#define PER_36XX_M_12		0x1B0
+#define PER_36XX_N_12		0x05
+#define PER_36XX_FSEL_12	0x07
+#define PER_36XX_M2_12		0x09
+
+#define PER_36XX_M_13		0x360
+#define PER_36XX_N_13		0x0C
+#define PER_36XX_FSEL_13	0x03
+#define PER_36XX_M2_13		0x09
+
+#define PER_36XX_M_19P2		0x1C2
+#define PER_36XX_N_19P2		0x09
+#define PER_36XX_FSEL_19P2	0x07
+#define PER_36XX_M2_19P2	0x09
+
+#define PER_36XX_M_26		0x1B0
+#define PER_36XX_N_26		0x0C
+#define PER_36XX_FSEL_26	0x07
+#define PER_36XX_M2_26		0x09
+
+#define PER_36XX_M_38P4		0x1C2
+#define PER_36XX_N_38P4		0x13
+#define PER_36XX_FSEL_38P4	0x07
+#define PER_36XX_M2_38P4	0x09
+
+/* 36XX PER2 DPLL */
+
+#define PER2_36XX_M_12		0x50
+#define PER2_36XX_N_12		0x00
+#define PER2_36XX_M2_12		0x08
+
+#define PER2_36XX_M_13		0x1BB
+#define PER2_36XX_N_13		0x05
+#define PER2_36XX_M2_13		0x08
+
+#define PER2_36XX_M_19P2		0x32
+#define PER2_36XX_N_19P2		0x00
+#define PER2_36XX_M2_19P2		0x08
+
+#define PER2_36XX_M_26		0x1BB
+#define PER2_36XX_N_26		0x0B
+#define PER2_36XX_M2_26		0x08
+
+#define PER2_36XX_M_38P4		0x19
+#define PER2_36XX_N_38P4		0x00
+#define PER2_36XX_M2_38P4		0x08
+
+#endif	/* endif _CLOCKS_OMAP3_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h
new file mode 100644
index 000000000..4d06ef83f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/cpu.h
@@ -0,0 +1,511 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/* Register offsets of common modules */
+/* Control */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct ctrl {
+	u8 res1[0xC0];
+	u16 gpmc_nadv_ale;	/* 0xC0 */
+	u16 gpmc_noe;		/* 0xC2 */
+	u16 gpmc_nwe;		/* 0xC4 */
+	u8 res2[0x22A];
+	u32 status;		/* 0x2F0 */
+	u32 gpstatus;		/* 0x2F4 */
+	u8 res3[0x08];
+	u32 rpubkey_0;		/* 0x300 */
+	u32 rpubkey_1;		/* 0x304 */
+	u32 rpubkey_2;		/* 0x308 */
+	u32 rpubkey_3;		/* 0x30C */
+	u32 rpubkey_4;		/* 0x310 */
+	u8 res4[0x04];
+	u32 randkey_0;		/* 0x318 */
+	u32 randkey_1;		/* 0x31C */
+	u32 randkey_2;		/* 0x320 */
+	u32 randkey_3;		/* 0x324 */
+	u8 res5[0x124];
+	u32 ctrl_omap_stat;	/* 0x44C */
+};
+#else /* __ASSEMBLY__ */
+#define CONTROL_STATUS		0x2F0
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct ctrl_id {
+	u8 res1[0x4];
+	u32 idcode;		/* 0x04 */
+	u32 prod_id;		/* 0x08 */
+	u32 sku_id;		/* 0x0c */
+	u8 res2[0x08];
+	u32 die_id_0;		/* 0x18 */
+	u32 die_id_1;		/* 0x1C */
+	u32 die_id_2;		/* 0x20 */
+	u32 die_id_3;		/* 0x24 */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* device type */
+#define DEVICE_MASK		(0x7 << 8)
+#define SYSBOOT_MASK		0x1F
+#define TST_DEVICE		0x0
+#define EMU_DEVICE		0x1
+#define HS_DEVICE		0x2
+#define GP_DEVICE		0x3
+
+/* device speed */
+#define SKUID_CLK_MASK		0xf
+#define SKUID_CLK_600MHZ	0x0
+#define SKUID_CLK_720MHZ	0x8
+
+#define GPMC_BASE		(OMAP34XX_GPMC_BASE)
+#define GPMC_CONFIG_CS0		0x60
+#define GPMC_CONFIG_CS0_BASE	(GPMC_BASE + GPMC_CONFIG_CS0)
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifdef __ASSEMBLY__
+#define GPMC_CONFIG1		0x00
+#define GPMC_CONFIG2		0x04
+#define GPMC_CONFIG3		0x08
+#define GPMC_CONFIG4		0x0C
+#define GPMC_CONFIG5		0x10
+#define GPMC_CONFIG6		0x14
+#define GPMC_CONFIG7		0x18
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* GPMC Mapping */
+#define FLASH_BASE		0x10000000	/* NOR flash, */
+						/* aligned to 256 Meg */
+#define FLASH_BASE_SDPV1	0x04000000	/* NOR flash, */
+						/* aligned to 64 Meg */
+#define FLASH_BASE_SDPV2	0x10000000	/* NOR flash, */
+						/* aligned to 256 Meg */
+#define DEBUG_BASE		0x08000000	/* debug board */
+#define NAND_BASE		0x30000000	/* NAND addr */
+						/* (actual size small port) */
+#define PISMO2_BASE		0x18000000	/* PISMO2 CS1/2 */
+#define ONENAND_MAP		0x20000000	/* OneNand addr */
+						/* (actual size small port) */
+/* SMS */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct sms {
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u8 res2[0x34];
+	u32 rg_att0;		/* 0x48 */
+	u8 res3[0x84];
+	u32 class_arb0;		/* 0xD0 */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define BURSTCOMPLETE_GROUP7	(0x1 << 31)
+
+/* SDRC */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct sdrc_cs {
+	u32 mcfg;		/* 0x80 || 0xB0 */
+	u32 mr;			/* 0x84 || 0xB4 */
+	u8 res1[0x4];
+	u32 emr2;		/* 0x8C || 0xBC */
+	u8 res2[0x14];
+	u32 rfr_ctrl;		/* 0x84 || 0xD4 */
+	u32 manual;		/* 0xA8 || 0xD8 */
+	u8 res3[0x4];
+};
+
+struct sdrc_actim {
+	u32 ctrla;		/* 0x9C || 0xC4 */
+	u32 ctrlb;		/* 0xA0 || 0xC8 */
+};
+
+struct sdrc {
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u32 status;		/* 0x14 */
+	u8 res2[0x28];
+	u32 cs_cfg;		/* 0x40 */
+	u32 sharing;		/* 0x44 */
+	u8 res3[0x18];
+	u32 dlla_ctrl;		/* 0x60 */
+	u32 dlla_status;	/* 0x64 */
+	u32 dllb_ctrl;		/* 0x68 */
+	u32 dllb_status;	/* 0x6C */
+	u32 power;		/* 0x70 */
+	u8 res4[0xC];
+	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
+};
+
+/* EMIF4 */
+typedef struct emif4 {
+	unsigned int emif_mod_id_rev;
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+} emif4_t;
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define DLLPHASE_90		(0x1 << 1)
+#define LOADDLL			(0x1 << 2)
+#define ENADLL			(0x1 << 3)
+#define DLL_DELAY_MASK		0xFF00
+#define DLL_NO_FILTER_MASK	((0x1 << 9) | (0x1 << 8))
+
+#define PAGEPOLICY_HIGH		(0x1 << 0)
+#define SRFRONRESET		(0x1 << 7)
+#define PWDNEN			(0x1 << 2)
+#define WAKEUPPROC		(0x1 << 26)
+
+#define DDR_SDRAM		(0x1 << 0)
+#define DEEPPD			(0x1 << 3)
+#define B32NOT16		(0x1 << 4)
+#define BANKALLOCATION		(0x2 << 6)
+#define RAMSIZE_128		(0x40 << 8) /* RAM size in 2MB chunks */
+#define ADDRMUXLEGACY		(0x1 << 19)
+#define CASWIDTH_10BITS		(0x5 << 20)
+#define RASWIDTH_13BITS		(0x2 << 24)
+#define BURSTLENGTH4		(0x2 << 0)
+#define CASL3			(0x3 << 4)
+#define SDRC_ACTIM_CTRL0_BASE	(OMAP34XX_SDRC_BASE + 0x9C)
+#define SDRC_ACTIM_CTRL1_BASE	(OMAP34XX_SDRC_BASE + 0xC4)
+#define ARE_ARCV_1		(0x1 << 0)
+#define ARCV			(0x4e2 << 8) /* Autorefresh count */
+#define OMAP34XX_SDRC_CS0	0x80000000
+#define OMAP34XX_SDRC_CS1	0xA0000000
+#define CMD_NOP			0x0
+#define CMD_PRECHARGE		0x1
+#define CMD_AUTOREFRESH		0x2
+#define CMD_ENTR_PWRDOWN	0x3
+#define CMD_EXIT_PWRDOWN	0x4
+#define CMD_ENTR_SRFRSH		0x5
+#define CMD_CKE_HIGH		0x6
+#define CMD_CKE_LOW		0x7
+#define SOFTRESET		(0x1 << 1)
+#define SMART_IDLE		(0x2 << 3)
+#define REF_ON_IDLE		(0x1 << 6)
+
+/* DMA */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct dma4_chan {
+	u32 ccr;
+	u32 clnk_ctrl;
+	u32 cicr;
+	u32 csr;
+	u32 csdp;
+	u32 cen;
+	u32 cfn;
+	u32 cssa;
+	u32 cdsa;
+	u32 csel;
+	u32 csfl;
+	u32 cdel;
+	u32 cdfl;
+	u32 csac;
+	u32 cdac;
+	u32 ccen;
+	u32 ccfn;
+	u32 color;
+};
+
+struct dma4 {
+	u32 revision;
+	u8 res1[0x4];
+	u32 irqstatus_l[0x4];
+	u32 irqenable_l[0x4];
+	u32 sysstatus;
+	u32 ocp_sysconfig;
+	u8 res2[0x34];
+	u32 caps_0;
+	u8 res3[0x4];
+	u32 caps_2;
+	u32 caps_3;
+	u32 caps_4;
+	u32 gcr;
+	u8 res4[0x4];
+	struct dma4_chan chan[32];
+};
+
+#endif /*__ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* timer regs offsets (32 bit regs) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gptimer {
+	u32 tidr;	/* 0x00 r */
+	u8 res[0xc];
+	u32 tiocp_cfg;	/* 0x10 rw */
+	u32 tistat;	/* 0x14 r */
+	u32 tisr;	/* 0x18 rw */
+	u32 tier;	/* 0x1c rw */
+	u32 twer;	/* 0x20 rw */
+	u32 tclr;	/* 0x24 rw */
+	u32 tcrr;	/* 0x28 rw */
+	u32 tldr;	/* 0x2c rw */
+	u32 ttgr;	/* 0x30 rw */
+	u32 twpc;	/* 0x34 r*/
+	u32 tmar;	/* 0x38 rw*/
+	u32 tcar1;	/* 0x3c r */
+	u32 tcicr;	/* 0x40 rw */
+	u32 tcar2;	/* 0x44 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+	u8 res1[0x34];
+	u32 wwps;	/* 0x34 r */
+	u8 res2[0x10];
+	u32 wspr;	/* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+/* PRCM */
+#define PRCM_BASE		0x48004000
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct prcm {
+	u32 fclken_iva2;	/* 0x00 */
+	u32 clken_pll_iva2;	/* 0x04 */
+	u8 res1[0x1c];
+	u32 idlest_pll_iva2;	/* 0x24 */
+	u8 res2[0x18];
+	u32 clksel1_pll_iva2 ;	/* 0x40 */
+	u32 clksel2_pll_iva2;	/* 0x44 */
+	u8 res3[0x8bc];
+	u32 clken_pll_mpu;	/* 0x904 */
+	u8 res4[0x1c];
+	u32 idlest_pll_mpu;	/* 0x924 */
+	u8 res5[0x18];
+	u32 clksel1_pll_mpu;	/* 0x940 */
+	u32 clksel2_pll_mpu;	/* 0x944 */
+	u8 res6[0xb8];
+	u32 fclken1_core;	/* 0xa00 */
+	u32 res_fclken2_core;
+	u32 fclken3_core;	/* 0xa08 */
+	u8 res7[0x4];
+	u32 iclken1_core;	/* 0xa10 */
+	u32 iclken2_core;	/* 0xa14 */
+	u32 iclken3_core;	/* 0xa18 */
+	u8 res8[0x24];
+	u32 clksel_core;	/* 0xa40 */
+	u8 res9[0xbc];
+	u32 fclken_gfx;		/* 0xb00 */
+	u8 res10[0xc];
+	u32 iclken_gfx;		/* 0xb10 */
+	u8 res11[0x2c];
+	u32 clksel_gfx;		/* 0xb40 */
+	u8 res12[0xbc];
+	u32 fclken_wkup;	/* 0xc00 */
+	u8 res13[0xc];
+	u32 iclken_wkup;	/* 0xc10 */
+	u8 res14[0xc];
+	u32 idlest_wkup;	/* 0xc20 */
+	u8 res15[0x1c];
+	u32 clksel_wkup;	/* 0xc40 */
+	u8 res16[0xbc];
+	u32 clken_pll;		/* 0xd00 */
+	u32 clken2_pll;	        /* 0xd04 */
+	u8 res17[0x18];
+	u32 idlest_ckgen;	/* 0xd20 */
+	u32 idlest2_ckgen;	/* 0xd24 */
+	u8 res18[0x18];
+	u32 clksel1_pll;	/* 0xd40 */
+	u32 clksel2_pll;	/* 0xd44 */
+	u32 clksel3_pll;	/* 0xd48 */
+	u32 clksel4_pll;	/* 0xd4c */
+	u32 clksel5_pll;	/* 0xd50 */
+	u8 res19[0xac];
+	u32 fclken_dss;		/* 0xe00 */
+	u8 res20[0xc];
+	u32 iclken_dss;		/* 0xe10 */
+	u8 res21[0x2c];
+	u32 clksel_dss;		/* 0xe40 */
+	u8 res22[0xbc];
+	u32 fclken_cam;		/* 0xf00 */
+	u8 res23[0xc];
+	u32 iclken_cam;		/* 0xf10 */
+	u8 res24[0x2c];
+	u32 clksel_cam;		/* 0xf40 */
+	u8 res25[0xbc];
+	u32 fclken_per;		/* 0x1000 */
+	u8 res26[0xc];
+	u32 iclken_per;		/* 0x1010 */
+	u8 res27[0x2c];
+	u32 clksel_per;		/* 0x1040 */
+	u8 res28[0xfc];
+	u32 clksel1_emu;	/* 0x1140 */
+	u8 res29[0x2bc];
+	u32 fclken_usbhost;	/* 0x1400 */
+	u8 res30[0xc];
+	u32 iclken_usbhost;	/* 0x1410 */
+};
+#else /* __ASSEMBLY__ */
+#define CM_CLKSEL_CORE		0x48004a40
+#define CM_CLKSEL_GFX		0x48004b40
+#define CM_CLKSEL_WKUP		0x48004c40
+#define CM_CLKEN_PLL		0x48004d00
+#define CM_CLKSEL1_PLL		0x48004d40
+#define CM_CLKSEL1_EMU		0x48005140
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define PRM_BASE		0x48306000
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct prm {
+	u8 res1[0xd40];
+	u32 clksel;		/* 0xd40 */
+	u8 res2[0x50c];
+	u32 rstctrl;		/* 0x1250 */
+	u8 res3[0x1c];
+	u32 clksrc_ctrl;	/* 0x1270 */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define PRM_RSTCTRL		0x48307250
+#define PRM_RSTCTRL_RESET	0x04
+#define PRM_RSTST			0x48307258
+#define PRM_RSTST_WARM_RESET_MASK	0x7D2
+#define SYSCLKDIV_1		(0x1 << 6)
+#define SYSCLKDIV_2		(0x1 << 7)
+
+#define CLKSEL_GPT1		(0x1 << 0)
+
+#define EN_GPT1			(0x1 << 0)
+#define EN_32KSYNC		(0x1 << 2)
+
+#define ST_WDT2			(0x1 << 5)
+
+#define ST_MPU_CLK		(0x1 << 0)
+
+#define ST_CORE_CLK		(0x1 << 0)
+
+#define ST_PERIPH_CLK		(0x1 << 1)
+
+#define ST_IVA2_CLK		(0x1 << 0)
+
+#define RESETDONE		(0x1 << 0)
+
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* SMX-APE */
+#define PM_RT_APE_BASE_ADDR_ARM		(SMX_APE_BASE + 0x10000)
+#define PM_GPMC_BASE_ADDR_ARM		(SMX_APE_BASE + 0x12400)
+#define PM_OCM_RAM_BASE_ADDR_ARM	(SMX_APE_BASE + 0x12800)
+#define PM_IVA2_BASE_ADDR_ARM		(SMX_APE_BASE + 0x14000)
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct pm {
+	u8 res1[0x48];
+	u32 req_info_permission_0;	/* 0x48 */
+	u8 res2[0x4];
+	u32 read_permission_0;		/* 0x50 */
+	u8 res3[0x4];
+	u32 wirte_permission_0;		/* 0x58 */
+	u8 res4[0x4];
+	u32 addr_match_1;		/* 0x58 */
+	u8 res5[0x4];
+	u32 req_info_permission_1;	/* 0x68 */
+	u8 res6[0x14];
+	u32 addr_match_2;		/* 0x80 */
+};
+#endif /*__ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* Permission values for registers -Full fledged permissions to all */
+#define UNLOCK_1			0xFFFFFFFF
+#define UNLOCK_2			0x00000000
+#define UNLOCK_3			0x0000FFFF
+
+#define NOT_EARLY			0
+
+/* I2C base */
+#define I2C_BASE1		(OMAP34XX_CORE_L4_IO_BASE + 0x70000)
+#define I2C_BASE2		(OMAP34XX_CORE_L4_IO_BASE + 0x72000)
+#define I2C_BASE3		(OMAP34XX_CORE_L4_IO_BASE + 0x60000)
+
+/* MUSB base */
+#define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
+
+/* OMAP3 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0014
+#define OMAP_GPIO_IRQSTATUS1		0x0018
+#define OMAP_GPIO_IRQSTATUS2		0x0028
+#define OMAP_GPIO_IRQENABLE2		0x002c
+#define OMAP_GPIO_IRQENABLE1		0x001c
+#define OMAP_GPIO_WAKE_EN		0x0020
+#define OMAP_GPIO_CTRL			0x0030
+#define OMAP_GPIO_OE			0x0034
+#define OMAP_GPIO_DATAIN		0x0038
+#define OMAP_GPIO_DATAOUT		0x003c
+#define OMAP_GPIO_LEVELDETECT0		0x0040
+#define OMAP_GPIO_LEVELDETECT1		0x0044
+#define OMAP_GPIO_RISINGDETECT		0x0048
+#define OMAP_GPIO_FALLINGDETECT		0x004c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0050
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0054
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0060
+#define OMAP_GPIO_SETIRQENABLE1		0x0064
+#define OMAP_GPIO_CLEARWKUENA		0x0080
+#define OMAP_GPIO_SETWKUENA		0x0084
+#define OMAP_GPIO_CLEARDATAOUT		0x0090
+#define OMAP_GPIO_SETDATAOUT		0x0094
+
+#endif /* _CPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h
new file mode 100644
index 000000000..5f0ad35d7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dma.h
@@ -0,0 +1,64 @@
+#ifndef __SDMA_H
+#define __SDMA_H
+
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Functions */
+void omap3_dma_init(void);
+int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
+		uint32_t sze);
+int omap3_dma_start_transfer(uint32_t chan);
+int omap3_dma_wait_for_transfer(uint32_t chan);
+int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
+int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
+
+/* Register settings */
+#define CSDP_DATA_TYPE_8BIT             0x0
+#define CSDP_DATA_TYPE_16BIT            0x1
+#define CSDP_DATA_TYPE_32BIT            0x2
+#define CSDP_SRC_BURST_SINGLE           (0x0 << 7)
+#define CSDP_SRC_BURST_EN_16BYTES       (0x1 << 7)
+#define CSDP_SRC_BURST_EN_32BYTES       (0x2 << 7)
+#define CSDP_SRC_BURST_EN_64BYTES       (0x3 << 7)
+#define CSDP_DST_BURST_SINGLE           (0x0 << 14)
+#define CSDP_DST_BURST_EN_16BYTES       (0x1 << 14)
+#define CSDP_DST_BURST_EN_32BYTES       (0x2 << 14)
+#define CSDP_DST_BURST_EN_64BYTES       (0x3 << 14)
+#define CSDP_DST_ENDIAN_LOCK_ADAPT      (0x0 << 18)
+#define CSDP_DST_ENDIAN_LOCK_LOCK       (0x1 << 18)
+#define CSDP_DST_ENDIAN_LITTLE          (0x0 << 19)
+#define CSDP_DST_ENDIAN_BIG             (0x1 << 19)
+#define CSDP_SRC_ENDIAN_LOCK_ADAPT      (0x0 << 20)
+#define CSDP_SRC_ENDIAN_LOCK_LOCK       (0x1 << 20)
+#define CSDP_SRC_ENDIAN_LITTLE          (0x0 << 21)
+#define CSDP_SRC_ENDIAN_BIG             (0x1 << 21)
+
+#define CCR_READ_PRIORITY_LOW           (0x0 << 6)
+#define CCR_READ_PRIORITY_HIGH          (0x1 << 6)
+#define CCR_ENABLE_DISABLED             (0x0 << 7)
+#define CCR_ENABLE_ENABLE               (0x1 << 7)
+#define CCR_SRC_AMODE_CONSTANT          (0x0 << 12)
+#define CCR_SRC_AMODE_POST_INC          (0x1 << 12)
+#define CCR_SRC_AMODE_SINGLE_IDX        (0x2 << 12)
+#define CCR_SRC_AMODE_DOUBLE_IDX        (0x3 << 12)
+#define CCR_DST_AMODE_CONSTANT          (0x0 << 14)
+#define CCR_DST_AMODE_POST_INC          (0x1 << 14)
+#define CCR_DST_AMODE_SINGLE_IDX        (0x2 << 14)
+#define CCR_DST_AMODE_SOUBLE_IDX        (0x3 << 14)
+
+#define CCR_RD_ACTIVE_MASK              (1 << 9)
+#define CCR_WR_ACTIVE_MASK              (1 << 10)
+
+#define CSR_TRANS_ERR			(1 << 8)
+#define CSR_SUPERVISOR_ERR		(1 << 10)
+#define CSR_MISALIGNED_ADRS_ERR		(1 << 11)
+
+/* others */
+#define CHAN_NR_MIN			0
+#define CHAN_NR_MAX			31
+
+#endif /* __SDMA_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h
new file mode 100644
index 000000000..8bf6b4895
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/dss.h
@@ -0,0 +1,233 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Referred to Linux Kernel DSS driver files for OMAP3 by
+ * Tomi Valkeinen from drivers/video/omap2/dss/
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 and any
+ * later version the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef DSS_H
+#define DSS_H
+
+/* DSS Base Registers */
+#define OMAP3_DSS_BASE		0x48050000
+#define OMAP3_DISPC_BASE	0x48050400
+#define OMAP3_VENC_BASE		0x48050C00
+
+/* DSS Registers */
+struct dss_regs {
+	u32 revision;				/* 0x00 */
+	u8 res1[12];				/* 0x04 */
+	u32 sysconfig;				/* 0x10 */
+	u32 sysstatus;				/* 0x14 */
+	u32 irqstatus;				/* 0x18 */
+	u8 res2[36];				/* 0x1C */
+	u32 control;				/* 0x40 */
+	u32 sdi_control;			/* 0x44 */
+	u32 pll_control;			/* 0x48 */
+};
+
+/* DISPC Registers */
+struct dispc_regs {
+	u32 revision;				/* 0x00 */
+	u8 res1[12];				/* 0x04 */
+	u32 sysconfig;				/* 0x10 */
+	u32 sysstatus;				/* 0x14 */
+	u32 irqstatus;				/* 0x18 */
+	u32 irqenable;				/* 0x1C */
+	u8 res2[32];				/* 0x20 */
+	u32 control;				/* 0x40 */
+	u32 config;				/* 0x44 */
+	u32 reserve_2;				/* 0x48 */
+	u32 default_color0;			/* 0x4C */
+	u32 default_color1;			/* 0x50 */
+	u32 trans_color0;			/* 0x54 */
+	u32 trans_color1;			/* 0x58 */
+	u32 line_status;			/* 0x5C */
+	u32 line_number;			/* 0x60 */
+	u32 timing_h;				/* 0x64 */
+	u32 timing_v;				/* 0x68 */
+	u32 pol_freq;				/* 0x6C */
+	u32 divisor;				/* 0x70 */
+	u32 global_alpha;			/* 0x74 */
+	u32 size_dig;				/* 0x78 */
+	u32 size_lcd;				/* 0x7C */
+	u32 gfx_ba0;				/* 0x80 */
+	u32 gfx_ba1;				/* 0x84 */
+	u32 gfx_position;			/* 0x88 */
+	u32 gfx_size;				/* 0x8C */
+	u8 unused[16];				/* 0x90 */
+	u32 gfx_attributes;			/* 0xA0 */
+	u32 gfx_fifo_threshold;			/* 0xA4 */
+	u32 gfx_fifo_size_status;		/* 0xA8 */
+	u32 gfx_row_inc;			/* 0xAC */
+	u32 gfx_pixel_inc;			/* 0xB0 */
+	u32 gfx_window_skip;			/* 0xB4 */
+	u32 gfx_table_ba;			/* 0xB8 */
+};
+
+/* VENC Registers */
+struct venc_regs {
+	u32 rev_id;				/* 0x00 */
+	u32 status;				/* 0x04 */
+	u32 f_control;				/* 0x08 */
+	u32 reserve_1;				/* 0x0C */
+	u32 vidout_ctrl;			/* 0x10 */
+	u32 sync_ctrl;				/* 0x14 */
+	u32 reserve_2;				/* 0x18 */
+	u32 llen;				/* 0x1C */
+	u32 flens;				/* 0x20 */
+	u32 hfltr_ctrl;				/* 0x24 */
+	u32 cc_carr_wss_carr;			/* 0x28 */
+	u32 c_phase;				/* 0x2C */
+	u32 gain_u;				/* 0x30 */
+	u32 gain_v;				/* 0x34 */
+	u32 gain_y;				/* 0x38 */
+	u32 black_level;			/* 0x3C */
+	u32 blank_level;			/* 0x40 */
+	u32 x_color;				/* 0x44 */
+	u32 m_control;				/* 0x48 */
+	u32 bstamp_wss_data;			/* 0x4C */
+	u32 s_carr;				/* 0x50 */
+	u32 line21;				/* 0x54 */
+	u32 ln_sel;				/* 0x58 */
+	u32 l21__wc_ctl;			/* 0x5C */
+	u32 htrigger_vtrigger;			/* 0x60 */
+	u32 savid__eavid;			/* 0x64 */
+	u32 flen__fal;				/* 0x68 */
+	u32 lal__phase_reset;			/* 0x6C */
+	u32 hs_int_start_stop_x;		/* 0x70 */
+	u32 hs_ext_start_stop_x;		/* 0x74 */
+	u32 vs_int_start_x;			/* 0x78 */
+	u32 vs_int_stop_x__vs_int_start_y;	/* 0x7C */
+	u32 vs_int_stop_y__vs_ext_start_x;	/* 0x80 */
+	u32 vs_ext_stop_x__vs_ext_start_y;	/* 0x84 */
+	u32 vs_ext_stop_y;			/* 0x88 */
+	u32 reserve_3;				/* 0x8C */
+	u32 avid_start_stop_x;			/* 0x90 */
+	u32 avid_start_stop_y;			/* 0x94 */
+	u32 reserve_4;				/* 0x98 */
+	u32 reserve_5;				/* 0x9C */
+	u32 fid_int_start_x__fid_int_start_y;	/* 0xA0 */
+	u32 fid_int_offset_y__fid_ext_start_x;	/* 0xA4 */
+	u32 fid_ext_start_y__fid_ext_offset_y;	/* 0xA8 */
+	u32 reserve_6;				/* 0xAC */
+	u32 tvdetgp_int_start_stop_x;		/* 0xB0 */
+	u32 tvdetgp_int_start_stop_y;		/* 0xB4 */
+	u32 gen_ctrl;				/* 0xB8 */
+	u32 reserve_7;				/* 0xBC */
+	u32 reserve_8;				/* 0xC0 */
+	u32 output_control;			/* 0xC4 */
+	u32 dac_b__dac_c;			/* 0xC8 */
+	u32 height_width;			/* 0xCC */
+};
+
+/* Few Register Offsets */
+#define TFTSTN_SHIFT				3
+#define DATALINES_SHIFT				8
+
+#define GFX_ENABLE				1
+#define GFX_FORMAT_SHIFT			1
+#define LOADMODE_SHIFT				1
+
+#define DSS_SOFTRESET				(1 << 1)
+#define DSS_RESETDONE				1
+
+/* Enabling Display controller */
+#define LCD_ENABLE				1
+#define DIG_ENABLE				(1 << 1)
+#define GO_LCD					(1 << 5)
+#define GO_DIG					(1 << 6)
+#define GP_OUT0					(1 << 15)
+#define GP_OUT1					(1 << 16)
+
+/* Configure VENC DSS Params */
+#define VENC_CLK_ENABLE				(1 << 3)
+#define DAC_DEMEN				(1 << 4)
+#define DAC_POWERDN				(1 << 5)
+#define VENC_OUT_SEL				(1 << 6)
+#define DIG_LPP_SHIFT				16
+
+/* LCD display type */
+#define PASSIVE_DISPLAY			0
+#define ACTIVE_DISPLAY			1
+
+/* TFTDATALINES */
+#define LCD_INTERFACE_12_BIT	0
+#define LCD_INTERFACE_16_BIT	1
+#define LCD_INTERFACE_18_BIT	2
+#define LCD_INTERFACE_24_BIT	3
+
+/* Polarity */
+#define DSS_IVS		(1 << 12)
+#define DSS_IHS		(1 << 13)
+#define DSS_IPC		(1 << 14)
+#define DSS_IEO		(1 << 15)
+#define DSS_ONOFF	(1 << 17)
+
+/* GFX format */
+#define GFXFORMAT_BITMAP1		(0x0 << 1)
+#define GFXFORMAT_BITMAP2		(0x1 << 1)
+#define GFXFORMAT_BITMAP4		(0x2 << 1)
+#define GFXFORMAT_BITMAP8		(0x3 << 1)
+#define GFXFORMAT_RGB12			(0x4 << 1)
+#define GFXFORMAT_ARGB16		(0x5 << 1)
+#define GFXFORMAT_RGB16			(0x6 << 1)
+#define GFXFORMAT_RGB24_UNPACKED	(0x8 << 1)
+#define GFXFORMAT_RGB24_PACKED		(0x9 << 1)
+#define GFXFORMAT_ARGB32		(0xC << 1)
+#define GFXFORMAT_RGBA32		(0xD << 1)
+#define GFXFORMAT_RGBx32		(0xE << 1)
+
+/* Panel Configuration */
+struct panel_config {
+	u32 timing_h;
+	u32 timing_v;
+	u32 pol_freq;
+	u32 divisor;
+	u32 lcd_size;
+	u32 panel_type;
+	u32 data_lines;
+	u32 load_mode;
+	u32 panel_color;
+	u32 gfx_format;
+	void *frame_buffer;
+};
+
+#define DSS_HBP(bp)    (((bp) - 1) << 20)
+#define DSS_HFP(fp)    (((fp) - 1) << 8)
+#define DSS_HSW(sw)    ((sw) - 1)
+#define DSS_VBP(bp)    ((bp) << 20)
+#define DSS_VFP(fp)    ((fp) << 8)
+#define DSS_VSW(sw)    ((sw) - 1)
+
+#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
+#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
+#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
+
+/* Generic DSS Functions */
+void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
+			u32 height, u32 width);
+void omap3_dss_panel_config(const struct panel_config *panel_cfg);
+void omap3_dss_enable(void);
+
+#endif /* DSS_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h
new file mode 100644
index 000000000..d96275578
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/ehci.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2011
+ * Alexander Holler <holler@ahsoftware.de>
+ *
+ * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37
+ *
+ * See there for additional Copyrights.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _OMAP3_EHCI_H_
+#define _OMAP3_EHCI_H_
+
+/* USB/EHCI registers */
+#define OMAP_USBTLL_BASE				0x48062000UL
+#define OMAP_UHH_BASE					0x48064000UL
+#define OMAP_EHCI_BASE					0x48064800UL
+
+/* TLL Register Set */
+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET			(1 << 1)
+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP			(1 << 2)
+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE			(1 << 3)
+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY			(1 << 8)
+#define OMAP_USBTLL_SYSSTATUS_RESETDONE			1
+
+/* UHH Register Set */
+#define OMAP_UHH_SYSCONFIG_SOFTRESET			(1 << 1)
+#define OMAP_UHH_SYSCONFIG_CACTIVITY			(1 << 8)
+#define OMAP_UHH_SYSCONFIG_SIDLEMODE			(1 << 3)
+#define OMAP_UHH_SYSCONFIG_ENAWAKEUP			(1 << 2)
+#define OMAP_UHH_SYSCONFIG_MIDLEMODE			(1 << 12)
+#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE		(1 << 2)
+
+#define OMAP_UHH_SYSCONFIG_VAL		(OMAP_UHH_SYSCONFIG_CACTIVITY | \
+					OMAP_UHH_SYSCONFIG_SIDLEMODE | \
+					OMAP_UHH_SYSCONFIG_ENAWAKEUP | \
+					OMAP_UHH_SYSCONFIG_MIDLEMODE)
+
+#endif /* _OMAP3_EHCI_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h
new file mode 100644
index 000000000..374d82120
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emac_defs.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * dm644x_emac.h
+ *
+ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
+ *
+ * Copyright (C) 2005 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Modifications:
+ * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
+ */
+
+#ifndef _AM3517_EMAC_H_
+#define _AM3517_EMAC_H_
+
+#define EMAC_BASE_ADDR                 0x5C010000
+#define EMAC_WRAPPER_BASE_ADDR         0x5C000000
+#define EMAC_WRAPPER_RAM_ADDR          0x5C020000
+#define EMAC_MDIO_BASE_ADDR            0x5C030000
+#define EMAC_HW_RAM_ADDR               0x01E20000
+
+#define EMAC_MDIO_BUS_FREQ             166000000       /* 166 MHZ check */
+#define EMAC_MDIO_CLOCK_FREQ           1000000         /* 2.0 MHz */
+
+/* SOFTRESET macro definition interferes with emac_regs structure definition */
+#undef SOFTRESET
+
+typedef volatile unsigned int	dv_reg;
+typedef volatile unsigned int	*dv_reg_p;
+
+#define DAVINCI_EMAC_VERSION2
+
+#endif  /* _AM3517_EMAC_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emif4.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emif4.h
new file mode 100644
index 000000000..c8fdf6208
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/emif4.h
@@ -0,0 +1,66 @@
+/*
+ * Auther:
+ *       Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+
+/*
+ * Configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x8 << 12)
+#define EMIF4_TIM1_T_RC		(0xA << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25)
+#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
+#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2)
+
+#define EMIF4_TIM3_T_RFC	(0x25 << 4)
+#define EMIF4_TIM3_T_RAS_MAX	(0x7)
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x50F)
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x0 << 24)
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2)
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+
+#endif /* endif _EMIF_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h
new file mode 100644
index 000000000..f664c1199
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+#ifndef _GPIO_OMAP3_H
+#define _GPIO_OMAP3_H
+
+#include <asm/omap_gpio.h>
+
+#define OMAP_MAX_GPIO			192
+
+#define OMAP34XX_GPIO1_BASE		0x48310000
+#define OMAP34XX_GPIO2_BASE		0x49050000
+#define OMAP34XX_GPIO3_BASE		0x49052000
+#define OMAP34XX_GPIO4_BASE		0x49054000
+#define OMAP34XX_GPIO5_BASE		0x49056000
+#define OMAP34XX_GPIO6_BASE		0x49058000
+
+#endif /* _GPIO_OMAP3_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h
new file mode 100644
index 000000000..b3702909c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/i2c.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _OMAP3_I2C_H_
+#define _OMAP3_I2C_H_
+
+#define I2C_BUS_MAX	3
+#define I2C_DEFAULT_BASE	I2C_BASE1
+
+struct i2c {
+	unsigned short rev;	/* 0x00 */
+	unsigned short res1;
+	unsigned short ie;	/* 0x04 */
+	unsigned short res2;
+	unsigned short stat;	/* 0x08 */
+	unsigned short res3;
+	unsigned short iv;	/* 0x0C */
+	unsigned short res4;
+	unsigned short syss;	/* 0x10 */
+	unsigned short res4a;
+	unsigned short buf;	/* 0x14 */
+	unsigned short res5;
+	unsigned short cnt;	/* 0x18 */
+	unsigned short res6;
+	unsigned short data;	/* 0x1C */
+	unsigned short res7;
+	unsigned short sysc;	/* 0x20 */
+	unsigned short res8;
+	unsigned short con;	/* 0x24 */
+	unsigned short res9;
+	unsigned short oa;	/* 0x28 */
+	unsigned short res10;
+	unsigned short sa;	/* 0x2C */
+	unsigned short res11;
+	unsigned short psc;	/* 0x30 */
+	unsigned short res12;
+	unsigned short scll;	/* 0x34 */
+	unsigned short res13;
+	unsigned short sclh;	/* 0x38 */
+	unsigned short res14;
+	unsigned short systest;	/* 0x3c */
+	unsigned short res15;
+};
+
+#endif /* _OMAP3_I2C_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h
new file mode 100644
index 000000000..18041913c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mem.h
@@ -0,0 +1,466 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+#define CS0		0x0
+#define CS1		0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
+
+#ifndef __ASSEMBLY__
+enum {
+	STACKED = 0,
+	IP_DDR = 1,
+	COMBO_DDR = 2,
+	IP_SDR = 3,
+};
+#endif /* __ASSEMBLY__ */
+
+#define EARLY_INIT	1
+
+/*
+ * For a full explanation of these registers and values please see
+ * the Technical Reference Manual (TRM) for any of the processors in
+ * this family.
+ */
+
+/* Slower full frequency range default timings for x32 operation*/
+#define SDRC_SHARING	0x00000100
+#define SDRC_MR_0_SDR	0x00000031
+
+/*
+ * SDRC autorefresh control values.  This register consists of autorefresh
+ * enable at bits 0:1 and an autorefresh counter value in bits 8:23.  The
+ * counter is a result of ( tREFI / tCK ) - 50.
+ */
+#define SDP_3430_SDRC_RFR_CTRL_100MHz	0x0002da01
+#define SDP_3430_SDRC_RFR_CTRL_133MHz	0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
+#define SDP_3430_SDRC_RFR_CTRL_165MHz	0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+#define SDP_3430_SDRC_RFR_CTRL_200MHz	0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
+
+#define DLL_OFFSET		0
+#define DLL_WRITEDDRCLKX2DIS	1
+#define DLL_ENADLL		1
+#define DLL_LOCKDLL		0
+#define DLL_DLLPHASE_72		0
+#define DLL_DLLPHASE_90		1
+
+/* rkw - need to find of 90/72 degree recommendation for speed like before */
+#define SDP_SDRC_DLLAB_CTRL	((DLL_ENADLL << 3) | \
+				(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
+
+/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
+#define ACTIM_CTRLA_TRFC(v)	(((v) & 0x1F) << 27)	/* 31:27 */
+#define ACTIM_CTRLA_TRC(v)	(((v) & 0x1F) << 22)	/* 26:22 */
+#define ACTIM_CTRLA_TRAS(v)	(((v) & 0x0F) << 18)	/* 21:18 */
+#define ACTIM_CTRLA_TRP(v)	(((v) & 0x07) << 15)	/* 17:15 */
+#define ACTIM_CTRLA_TRCD(v)	(((v) & 0x07) << 12)	/* 14:12 */
+#define ACTIM_CTRLA_TRRD(v)	(((v) & 0x07) << 9)	/* 11:9  */
+#define ACTIM_CTRLA_TDPL(v)	(((v) & 0x07) << 6)	/*  8:6  */
+#define ACTIM_CTRLA_TDAL(v)	(v & 0x1F)		/*  4:0  */
+
+#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal)	\
+		ACTIM_CTRLA_TRFC(trfc)	|	\
+		ACTIM_CTRLA_TRC(trc)	|	\
+		ACTIM_CTRLA_TRAS(tras)	|	\
+		ACTIM_CTRLA_TRP(trp)	|	\
+		ACTIM_CTRLA_TRCD(trcd)	|	\
+		ACTIM_CTRLA_TRRD(trrd)	|	\
+		ACTIM_CTRLA_TDPL(tdpl)	|	\
+		ACTIM_CTRLA_TDAL(tdal)
+
+/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
+#define ACTIM_CTRLB_TWTR(v)	(((v) & 0x03) << 16)	/* 17:16 */
+#define ACTIM_CTRLB_TCKE(v)	(((v) & 0x07) << 12)	/* 14:12 */
+#define ACTIM_CTRLB_TXP(v)	(((v) & 0x07) << 8)	/* 10:8  */
+#define ACTIM_CTRLB_TXSR(v)	(v & 0xFF)		/*  7:0  */
+
+#define ACTIM_CTRLB(twtr, tcke, txp, txsr)		\
+		ACTIM_CTRLB_TWTR(twtr)	|	\
+		ACTIM_CTRLB_TCKE(tcke)	|	\
+		ACTIM_CTRLB_TXP(txp)	|	\
+		ACTIM_CTRLB_TXSR(txsr)
+
+/*
+ * Values used in the MCFG register.  Only values we use today
+ * are defined and the rest can be found in the TRM.  Unless otherwise
+ * noted all fields are one bit.
+ */
+#define V_MCFG_RAMTYPE_DDR		(0x1)
+#define V_MCFG_DEEPPD_EN		(0x1 << 3)
+#define V_MCFG_B32NOT16_32		(0x1 << 4)
+#define V_MCFG_BANKALLOCATION_RBC	(0x2 << 6)		/* 6:7 */
+#define V_MCFG_RAMSIZE(ramsize)		((((ramsize) >> 20)/2) << 8) /* 8:17 */
+#define V_MCFG_ADDRMUXLEGACY_FLEX	(0x1 << 19)
+#define V_MCFG_CASWIDTH(caswidth)	(((caswidth)-5) << 20)	/* 20:22 */
+#define V_MCFG_CASWIDTH_10B		V_MCFG_CASWIDTH(10)
+#define V_MCFG_RASWIDTH(raswidth)	(((raswidth)-11) << 24)	/* 24:26 */
+
+/* Macro to construct MCFG */
+#define MCFG(ramsize, raswidth)						\
+		V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B |	\
+		V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) |	\
+		V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 |	\
+		V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
+
+/* Hynix part of Overo (165MHz optimized) 6.06ns */
+#define HYNIX_TDAL_165   6
+#define HYNIX_TDPL_165   3
+#define HYNIX_TRRD_165   2
+#define HYNIX_TRCD_165   3
+#define HYNIX_TRP_165    3
+#define HYNIX_TRAS_165   7
+#define HYNIX_TRC_165   10
+#define HYNIX_TRFC_165  21
+#define HYNIX_V_ACTIMA_165	\
+		ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165,	\
+				HYNIX_TRAS_165, HYNIX_TRP_165,	\
+				HYNIX_TRCD_165, HYNIX_TRRD_165,	\
+				HYNIX_TDPL_165, HYNIX_TDAL_165)
+
+#define HYNIX_TWTR_165   1
+#define HYNIX_TCKE_165   1
+#define HYNIX_TXP_165    2
+#define HYNIX_XSR_165    24
+#define HYNIX_V_ACTIMB_165	\
+		ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165,	\
+				HYNIX_TXP_165, HYNIX_XSR_165)
+
+#define HYNIX_RASWIDTH_165	13
+#define HYNIX_V_MCFG_165(size)	MCFG((size), HYNIX_RASWIDTH_165)
+
+/* Hynix part of AM/DM37xEVM (200MHz optimized) */
+#define HYNIX_TDAL_200		6
+#define HYNIX_TDPL_200		3
+#define HYNIX_TRRD_200		2
+#define HYNIX_TRCD_200		4
+#define HYNIX_TRP_200		3
+#define HYNIX_TRAS_200		8
+#define HYNIX_TRC_200		11
+#define HYNIX_TRFC_200		18
+#define HYNIX_V_ACTIMA_200	\
+		ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200,	\
+				HYNIX_TRAS_200, HYNIX_TRP_200,	\
+				HYNIX_TRCD_200, HYNIX_TRRD_200,	\
+				HYNIX_TDPL_200, HYNIX_TDAL_200)
+
+#define HYNIX_TWTR_200		2
+#define HYNIX_TCKE_200		1
+#define HYNIX_TXP_200		1
+#define HYNIX_XSR_200		28
+#define HYNIX_V_ACTIMB_200	\
+		ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200,	\
+				HYNIX_TXP_200, HYNIX_XSR_200)
+
+#define HYNIX_RASWIDTH_200	14
+#define HYNIX_V_MCFG_200(size)	MCFG((size), HYNIX_RASWIDTH_200)
+
+/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
+#define INFINEON_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
+					/* 15/6 + 18/6 = 5.5 -> 6	*/
+#define INFINEON_TDPL_165	3	/* 15/6 = 2.5 -> 3 (Twr)	*/
+#define INFINEON_TRRD_165	2	/* 12/6 = 2			*/
+#define INFINEON_TRCD_165	3	/* 18/6 = 3			*/
+#define INFINEON_TRP_165	3	/* 18/6 = 3			*/
+#define INFINEON_TRAS_165	7	/* 42/6 = 7			*/
+#define INFINEON_TRC_165	10	/* 60/6 = 10			*/
+#define INFINEON_TRFC_165	12	/* 72/6 = 12			*/
+
+#define INFINEON_V_ACTIMA_165	\
+		ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165,	\
+				INFINEON_TRAS_165, INFINEON_TRP_165,	\
+				INFINEON_TRCD_165, INFINEON_TRRD_165,	\
+				INFINEON_TDPL_165, INFINEON_TDAL_165)
+
+#define INFINEON_TWTR_165	1
+#define INFINEON_TCKE_165	2
+#define INFINEON_TXP_165	2
+#define INFINEON_XSR_165	20	/* 120/6 = 20	*/
+
+#define INFINEON_V_ACTIMB_165	\
+		ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165,	\
+				INFINEON_TXP_165, INFINEON_XSR_165)
+
+/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
+#define MICRON_TDAL_165		6	/* Twr/Tck + Trp/tck		*/
+					/* 15/6 + 18/6 = 5.5 -> 6	*/
+#define MICRON_TDPL_165		3	/* 15/6 = 2.5 -> 3 (Twr)	*/
+#define MICRON_TRRD_165		2	/* 12/6 = 2			*/
+#define MICRON_TRCD_165		3	/* 18/6 = 3			*/
+#define MICRON_TRP_165		3	/* 18/6 = 3			*/
+#define MICRON_TRAS_165		7	/* 42/6 = 7			*/
+#define MICRON_TRC_165		10	/* 60/6 = 10			*/
+#define MICRON_TRFC_165		21	/* 125/6 = 21			*/
+
+#define MICRON_V_ACTIMA_165	\
+		ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165,		\
+				MICRON_TRAS_165, MICRON_TRP_165,	\
+				MICRON_TRCD_165, MICRON_TRRD_165,	\
+				MICRON_TDPL_165, MICRON_TDAL_165)
+
+#define MICRON_TWTR_165		1
+#define MICRON_TCKE_165		1
+#define MICRON_XSR_165		23	/* 138/6 = 23		*/
+#define MICRON_TXP_165		5	/* 25/6 = 4.1 => ~5	*/
+
+#define MICRON_V_ACTIMB_165	\
+		ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165,	\
+				MICRON_TXP_165,	MICRON_XSR_165)
+
+#define MICRON_RASWIDTH_165	13
+#define MICRON_V_MCFG_165(size)	MCFG((size), MICRON_RASWIDTH_165)
+
+#define MICRON_BL_165			0x2
+#define MICRON_SIL_165			0x0
+#define MICRON_CASL_165			0x3
+#define MICRON_WBST_165			0x0
+#define MICRON_V_MR_165			((MICRON_WBST_165 << 9) | \
+		(MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
+		(MICRON_BL_165))
+
+/* Micron part (200MHz optimized) 5 ns */
+#define MICRON_TDAL_200		6
+#define MICRON_TDPL_200		3
+#define MICRON_TRRD_200		2
+#define MICRON_TRCD_200		3
+#define MICRON_TRP_200		3
+#define MICRON_TRAS_200		8
+#define MICRON_TRC_200		11
+#define MICRON_TRFC_200		15
+#define MICRON_V_ACTIMA_200	\
+		ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200,		\
+				MICRON_TRAS_200, MICRON_TRP_200,	\
+				MICRON_TRCD_200, MICRON_TRRD_200,	\
+				MICRON_TDPL_200, MICRON_TDAL_200)
+
+#define MICRON_TWTR_200		2
+#define MICRON_TCKE_200		4
+#define MICRON_TXP_200		2
+#define MICRON_XSR_200		23
+#define MICRON_V_ACTIMB_200	\
+		ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200,	\
+				MICRON_TXP_200,	MICRON_XSR_200)
+
+#define MICRON_RASWIDTH_200	14
+#define MICRON_V_MCFG_200(size)	MCFG((size), MICRON_RASWIDTH_200)
+
+/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
+#define NUMONYX_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
+					/* 15/6 + 18/6 = 5.5 -> 6	*/
+#define NUMONYX_TDPL_165	3	/* 15/6 = 2.5 -> 3 (Twr)	*/
+#define NUMONYX_TRRD_165	2	/* 12/6 = 2			*/
+#define NUMONYX_TRCD_165	4	/* 22.5/6 = 3.75 -> 4		*/
+#define NUMONYX_TRP_165		3	/* 18/6 = 3			*/
+#define NUMONYX_TRAS_165	7	/* 42/6 = 7			*/
+#define NUMONYX_TRC_165		10	/* 60/6 = 10			*/
+#define NUMONYX_TRFC_165	24	/* 140/6 = 23.3 -> 24		*/
+
+#define NUMONYX_V_ACTIMA_165	\
+		ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165,		\
+				NUMONYX_TRAS_165, NUMONYX_TRP_165,	\
+				NUMONYX_TRCD_165, NUMONYX_TRRD_165,	\
+				NUMONYX_TDPL_165, NUMONYX_TDAL_165)
+
+#define NUMONYX_TWTR_165	2
+#define NUMONYX_TCKE_165	2
+#define NUMONYX_TXP_165		3	/* 200/6 =  33.3 -> 34	*/
+#define NUMONYX_XSR_165		34	/* 1.0 + 1.1 = 2.1 -> 3	*/
+
+#define NUMONYX_V_ACTIMB_165	\
+		ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165,	\
+				NUMONYX_TXP_165, NUMONYX_XSR_165)
+
+#define NUMONYX_RASWIDTH_165		15
+#define NUMONYX_V_MCFG_165(size)	MCFG((size), NUMONYX_RASWIDTH_165)
+
+/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
+#define NUMONYX_TDAL_200	6	/* Twr/Tck + Trp/tck		*/
+					/* 15/5 + 15/5 = 3 + 3 -> 6	*/
+#define NUMONYX_TDPL_200	3	/* 15/5 = 3 -> 3 (Twr)	        */
+#define NUMONYX_TRRD_200	2	/* 10/5 = 2			*/
+#define NUMONYX_TRCD_200	4	/* 16.2/5 = 3.24 -> 4		*/
+#define NUMONYX_TRP_200		3	/* 15/5 = 3			*/
+#define NUMONYX_TRAS_200	8	/* 40/5 = 8			*/
+#define NUMONYX_TRC_200		11	/* 55/5 = 11			*/
+#define NUMONYX_TRFC_200        28      /* 140/5 = 28                   */
+
+#define NUMONYX_V_ACTIMA_200	\
+		ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200,		\
+				NUMONYX_TRAS_200, NUMONYX_TRP_200,	\
+				NUMONYX_TRCD_200, NUMONYX_TRRD_200,	\
+				NUMONYX_TDPL_200, NUMONYX_TDAL_200)
+
+#define NUMONYX_TWTR_200	2
+#define NUMONYX_TCKE_200	2
+#define NUMONYX_TXP_200		3
+#define NUMONYX_XSR_200		40
+
+#define NUMONYX_V_ACTIMB_200	\
+		ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200,	\
+				NUMONYX_TXP_200, NUMONYX_XSR_200)
+
+#define NUMONYX_RASWIDTH_200		15
+#define NUMONYX_V_MCFG_200(size)	MCFG((size), NUMONYX_RASWIDTH_200)
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * STNOR - Intel Strata Flash
+ * SMNAND - Samsung NAND
+ * MPDB - H4 MPDB board
+ * SBNOR - Sibley NOR
+ * MNAND - Micron Large page x16 NAND
+ * ONNAND - Samsung One NAND
+ *
+ * include/configs/file.h contains the defn - for all CS we are interested
+ * #define OMAP34XX_GPMC_CSx PART
+ * #define OMAP34XX_GPMC_CSx_SIZE Size
+ * #define OMAP34XX_GPMC_CSx_MAP Map
+ * Where:
+ * x - CS number
+ * PART - Part Name as defined above
+ * SIZE - how big is the mapping to be
+ *   GPMC_SIZE_128M - 0x8
+ *   GPMC_SIZE_64M  - 0xC
+ *   GPMC_SIZE_32M  - 0xE
+ *   GPMC_SIZE_16M  - 0xF
+ * MAP  - Map this CS to which address(GPMC address space)- Absolute address
+ *   >>24 before being used.
+ */
+#define GPMC_SIZE_128M	0x8
+#define GPMC_SIZE_64M	0xC
+#define GPMC_SIZE_32M	0xE
+#define GPMC_SIZE_16M	0xF
+
+#define GPMC_BASEADDR_MASK	0x3F
+
+#define GPMC_CS_ENABLE		0x1
+
+#define SMNAND_GPMC_CONFIG1	0x00000800
+#define SMNAND_GPMC_CONFIG2	0x00141400
+#define SMNAND_GPMC_CONFIG3	0x00141400
+#define SMNAND_GPMC_CONFIG4	0x0F010F01
+#define SMNAND_GPMC_CONFIG5	0x010C1414
+#define SMNAND_GPMC_CONFIG6	0x1F0F0A80
+#define SMNAND_GPMC_CONFIG7	0x00000C44
+
+#define M_NAND_GPMC_CONFIG1	0x00001800
+#define M_NAND_GPMC_CONFIG2	0x00141400
+#define M_NAND_GPMC_CONFIG3	0x00141400
+#define M_NAND_GPMC_CONFIG4	0x0F010F01
+#define M_NAND_GPMC_CONFIG5	0x010C1414
+#define M_NAND_GPMC_CONFIG6	0x1f0f0A80
+#define M_NAND_GPMC_CONFIG7	0x00000C44
+
+#define STNOR_GPMC_CONFIG1	0x3
+#define STNOR_GPMC_CONFIG2	0x00151501
+#define STNOR_GPMC_CONFIG3	0x00060602
+#define STNOR_GPMC_CONFIG4	0x11091109
+#define STNOR_GPMC_CONFIG5	0x01141F1F
+#define STNOR_GPMC_CONFIG6	0x000004c4
+
+#define SIBNOR_GPMC_CONFIG1	0x1200
+#define SIBNOR_GPMC_CONFIG2	0x001f1f00
+#define SIBNOR_GPMC_CONFIG3	0x00080802
+#define SIBNOR_GPMC_CONFIG4	0x1C091C09
+#define SIBNOR_GPMC_CONFIG5	0x01131F1F
+#define SIBNOR_GPMC_CONFIG6	0x1F0F03C2
+
+#define SDPV2_MPDB_GPMC_CONFIG1	0x00611200
+#define SDPV2_MPDB_GPMC_CONFIG2	0x001F1F01
+#define SDPV2_MPDB_GPMC_CONFIG3	0x00080803
+#define SDPV2_MPDB_GPMC_CONFIG4	0x1D091D09
+#define SDPV2_MPDB_GPMC_CONFIG5	0x041D1F1F
+#define SDPV2_MPDB_GPMC_CONFIG6	0x1D0904C4
+
+#define MPDB_GPMC_CONFIG1	0x00011000
+#define MPDB_GPMC_CONFIG2	0x001f1f01
+#define MPDB_GPMC_CONFIG3	0x00080803
+#define MPDB_GPMC_CONFIG4	0x1c0b1c0a
+#define MPDB_GPMC_CONFIG5	0x041f1F1F
+#define MPDB_GPMC_CONFIG6	0x1F0F04C4
+
+#define P2_GPMC_CONFIG1	0x0
+#define P2_GPMC_CONFIG2	0x0
+#define P2_GPMC_CONFIG3	0x0
+#define P2_GPMC_CONFIG4	0x0
+#define P2_GPMC_CONFIG5	0x0
+#define P2_GPMC_CONFIG6	0x0
+
+#define ONENAND_GPMC_CONFIG1	0x00001200
+#define ONENAND_GPMC_CONFIG2	0x000F0F01
+#define ONENAND_GPMC_CONFIG3	0x00030301
+#define ONENAND_GPMC_CONFIG4	0x0F040F04
+#define ONENAND_GPMC_CONFIG5	0x010F1010
+#define ONENAND_GPMC_CONFIG6	0x1F060000
+
+#define NET_GPMC_CONFIG1	0x00001000
+#define NET_GPMC_CONFIG2	0x001e1e01
+#define NET_GPMC_CONFIG3	0x00080300
+#define NET_GPMC_CONFIG4	0x1c091c09
+#define NET_GPMC_CONFIG5	0x04181f1f
+#define NET_GPMC_CONFIG6	0x00000FCF
+#define NET_GPMC_CONFIG7	0x00000f6c
+
+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1    0x00001000
+#define NET_LAN9221_GPMC_CONFIG2    0x00060700
+#define NET_LAN9221_GPMC_CONFIG3    0x00020201
+#define NET_LAN9221_GPMC_CONFIG4    0x06000700
+#define NET_LAN9221_GPMC_CONFIG5    0x0006090A
+#define NET_LAN9221_GPMC_CONFIG6    0x87030000
+#define NET_LAN9221_GPMC_CONFIG7    0x00000f6c
+
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS	8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG	7
+
+#define PISMO1_NOR	1
+#define PISMO1_NAND	2
+#define PISMO2_CS0	3
+#define PISMO2_CS1	4
+#define PISMO1_ONENAND	5
+#define DBG_MPDB	6
+#define PISMO2_NAND_CS0 7
+#define PISMO2_NAND_CS1 8
+
+/* make it readable for the gpmc_init */
+#define PISMO1_NOR_BASE		FLASH_BASE
+#define PISMO1_NAND_BASE	NAND_BASE
+#define PISMO2_CS0_BASE		PISMO2_MAP1
+#define PISMO1_ONEN_BASE	ONENAND_MAP
+#define DBG_MPDB_BASE		DEBUG_BASE
+
+#ifndef __ASSEMBLY__
+
+/* Function prototypes */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* endif _MEM_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h
new file mode 100644
index 000000000..0ba621a1b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+#include <asm/omap_mmc.h>
+
+/* T2 Register definitions */
+#define T2_BASE			0x48002000
+
+typedef struct t2 {
+	unsigned char res1[0x274];	/* 0x000 */
+	unsigned int devconf0;		/* 0x274 */
+	unsigned char res2[0x060];	/* 0x278 */
+	unsigned int devconf1;		/* 0x2D8 */
+	unsigned char res3[0x16C];	/* 0x2DC */
+	unsigned int ctl_prog_io1;	/* 0x448 */
+	unsigned char res4[0x0D4];	/* 0x44C */
+	unsigned int pbias_lite;	/* 0x520 */
+} t2_t;
+
+#define MMCSDIO1ADPCLKISEL		(1 << 24)
+#define MMCSDIO2ADPCLKISEL		(1 << 6)
+
+#define EN_MMC1				(1 << 24)
+#define EN_MMC2				(1 << 25)
+#define EN_MMC3				(1 << 30)
+
+#define PBIASLITEPWRDNZ0		(1 << 1)
+#define PBIASSPEEDCTRL0			(1 << 2)
+#define PBIASLITEPWRDNZ1		(1 << 9)
+
+#define CTLPROGIO1SPEEDCTRL		(1 << 20)
+
+/*
+ * OMAP HSMMC register definitions
+ */
+#define OMAP_HSMMC1_BASE	0x4809C000
+#define OMAP_HSMMC2_BASE	0x480B4000
+#define OMAP_HSMMC3_BASE	0x480AD000
+
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h
new file mode 100644
index 000000000..cee4ed311
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/musb.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2012
+ * Ilya Yanok, <ilya.yanok@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_OMAP3_MUSB_H
+#define __ASM_ARCH_OMAP3_MUSB_H
+extern void am35x_musb_reset(void);
+extern void am35x_musb_phy_power(u8 on);
+extern void am35x_musb_clear_irq(void);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h
new file mode 100644
index 000000000..2f8320629
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/mux.h
@@ -0,0 +1,451 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _MUX_H_
+#define _MUX_H_
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ */
+
+#define IEN	(1 << 8)
+
+#define IDIS	(0 << 8)
+#define PTU	(1 << 4)
+#define PTD	(0 << 4)
+#define EN	(1 << 3)
+#define DIS	(0 << 3)
+
+#define M0	0
+#define M1	1
+#define M2	2
+#define M3	3
+#define M4	4
+#define M5	5
+#define M6	6
+#define M7	7
+
+/*
+ * To get the actual address the offset has to added
+ * with OMAP34XX_CTRL_BASE to get the actual address
+ */
+
+/*SDRC*/
+#define CONTROL_PADCONF_SDRC_D0		0x0030
+#define CONTROL_PADCONF_SDRC_D1		0x0032
+#define CONTROL_PADCONF_SDRC_D2		0x0034
+#define CONTROL_PADCONF_SDRC_D3		0x0036
+#define CONTROL_PADCONF_SDRC_D4		0x0038
+#define CONTROL_PADCONF_SDRC_D5		0x003A
+#define CONTROL_PADCONF_SDRC_D6		0x003C
+#define CONTROL_PADCONF_SDRC_D7		0x003E
+#define CONTROL_PADCONF_SDRC_D8		0x0040
+#define CONTROL_PADCONF_SDRC_D9		0x0042
+#define CONTROL_PADCONF_SDRC_D10	0x0044
+#define CONTROL_PADCONF_SDRC_D11	0x0046
+#define CONTROL_PADCONF_SDRC_D12	0x0048
+#define CONTROL_PADCONF_SDRC_D13	0x004A
+#define CONTROL_PADCONF_SDRC_D14	0x004C
+#define CONTROL_PADCONF_SDRC_D15	0x004E
+#define CONTROL_PADCONF_SDRC_D16	0x0050
+#define CONTROL_PADCONF_SDRC_D17	0x0052
+#define CONTROL_PADCONF_SDRC_D18	0x0054
+#define CONTROL_PADCONF_SDRC_D19	0x0056
+#define CONTROL_PADCONF_SDRC_D20	0x0058
+#define CONTROL_PADCONF_SDRC_D21	0x005A
+#define CONTROL_PADCONF_SDRC_D22	0x005C
+#define CONTROL_PADCONF_SDRC_D23	0x005E
+#define CONTROL_PADCONF_SDRC_D24	0x0060
+#define CONTROL_PADCONF_SDRC_D25	0x0062
+#define CONTROL_PADCONF_SDRC_D26	0x0064
+#define CONTROL_PADCONF_SDRC_D27	0x0066
+#define CONTROL_PADCONF_SDRC_D28	0x0068
+#define CONTROL_PADCONF_SDRC_D29	0x006A
+#define CONTROL_PADCONF_SDRC_D30	0x006C
+#define CONTROL_PADCONF_SDRC_D31	0x006E
+#define CONTROL_PADCONF_SDRC_CLK	0x0070
+#define CONTROL_PADCONF_SDRC_DQS0	0x0072
+#define CONTROL_PADCONF_SDRC_DQS1	0x0074
+#define CONTROL_PADCONF_SDRC_DQS2	0x0076
+#define CONTROL_PADCONF_SDRC_DQS3	0x0078
+/*GPMC*/
+#define CONTROL_PADCONF_GPMC_A1		0x007A
+#define CONTROL_PADCONF_GPMC_A2		0x007C
+#define CONTROL_PADCONF_GPMC_A3		0x007E
+#define CONTROL_PADCONF_GPMC_A4		0x0080
+#define CONTROL_PADCONF_GPMC_A5		0x0082
+#define CONTROL_PADCONF_GPMC_A6		0x0084
+#define CONTROL_PADCONF_GPMC_A7		0x0086
+#define CONTROL_PADCONF_GPMC_A8		0x0088
+#define CONTROL_PADCONF_GPMC_A9		0x008A
+#define CONTROL_PADCONF_GPMC_A10	0x008C
+#define CONTROL_PADCONF_GPMC_D0		0x008E
+#define CONTROL_PADCONF_GPMC_D1		0x0090
+#define CONTROL_PADCONF_GPMC_D2		0x0092
+#define CONTROL_PADCONF_GPMC_D3		0x0094
+#define CONTROL_PADCONF_GPMC_D4		0x0096
+#define CONTROL_PADCONF_GPMC_D5		0x0098
+#define CONTROL_PADCONF_GPMC_D6		0x009A
+#define CONTROL_PADCONF_GPMC_D7		0x009C
+#define CONTROL_PADCONF_GPMC_D8		0x009E
+#define CONTROL_PADCONF_GPMC_D9		0x00A0
+#define CONTROL_PADCONF_GPMC_D10	0x00A2
+#define CONTROL_PADCONF_GPMC_D11	0x00A4
+#define CONTROL_PADCONF_GPMC_D12	0x00A6
+#define CONTROL_PADCONF_GPMC_D13	0x00A8
+#define CONTROL_PADCONF_GPMC_D14	0x00AA
+#define CONTROL_PADCONF_GPMC_D15	0x00AC
+#define CONTROL_PADCONF_GPMC_NCS0	0x00AE
+#define CONTROL_PADCONF_GPMC_NCS1	0x00B0
+#define CONTROL_PADCONF_GPMC_NCS2	0x00B2
+#define CONTROL_PADCONF_GPMC_NCS3	0x00B4
+#define CONTROL_PADCONF_GPMC_NCS4	0x00B6
+#define CONTROL_PADCONF_GPMC_NCS5	0x00B8
+#define CONTROL_PADCONF_GPMC_NCS6	0x00BA
+#define CONTROL_PADCONF_GPMC_NCS7	0x00BC
+#define CONTROL_PADCONF_GPMC_CLK	0x00BE
+#define CONTROL_PADCONF_GPMC_NADV_ALE	0x00C0
+#define CONTROL_PADCONF_GPMC_NOE	0x00C2
+#define CONTROL_PADCONF_GPMC_NWE	0x00C4
+#define CONTROL_PADCONF_GPMC_NBE0_CLE	0x00C6
+#define CONTROL_PADCONF_GPMC_NBE1	0x00C8
+#define CONTROL_PADCONF_GPMC_NWP	0x00CA
+#define CONTROL_PADCONF_GPMC_WAIT0	0x00CC
+#define CONTROL_PADCONF_GPMC_WAIT1	0x00CE
+#define CONTROL_PADCONF_GPMC_WAIT2	0x00D0
+#define CONTROL_PADCONF_GPMC_WAIT3	0x00D2
+/*DSS*/
+#define CONTROL_PADCONF_DSS_PCLK	0x00D4
+#define CONTROL_PADCONF_DSS_HSYNC	0x00D6
+#define CONTROL_PADCONF_DSS_VSYNC	0x00D8
+#define CONTROL_PADCONF_DSS_ACBIAS	0x00DA
+#define CONTROL_PADCONF_DSS_DATA0	0x00DC
+#define CONTROL_PADCONF_DSS_DATA1	0x00DE
+#define CONTROL_PADCONF_DSS_DATA2	0x00E0
+#define CONTROL_PADCONF_DSS_DATA3	0x00E2
+#define CONTROL_PADCONF_DSS_DATA4	0x00E4
+#define CONTROL_PADCONF_DSS_DATA5	0x00E6
+#define CONTROL_PADCONF_DSS_DATA6	0x00E8
+#define CONTROL_PADCONF_DSS_DATA7	0x00EA
+#define CONTROL_PADCONF_DSS_DATA8	0x00EC
+#define CONTROL_PADCONF_DSS_DATA9	0x00EE
+#define CONTROL_PADCONF_DSS_DATA10	0x00F0
+#define CONTROL_PADCONF_DSS_DATA11	0x00F2
+#define CONTROL_PADCONF_DSS_DATA12	0x00F4
+#define CONTROL_PADCONF_DSS_DATA13	0x00F6
+#define CONTROL_PADCONF_DSS_DATA14	0x00F8
+#define CONTROL_PADCONF_DSS_DATA15	0x00FA
+#define CONTROL_PADCONF_DSS_DATA16	0x00FC
+#define CONTROL_PADCONF_DSS_DATA17	0x00FE
+#define CONTROL_PADCONF_DSS_DATA18	0x0100
+#define CONTROL_PADCONF_DSS_DATA19	0x0102
+#define CONTROL_PADCONF_DSS_DATA20	0x0104
+#define CONTROL_PADCONF_DSS_DATA21	0x0106
+#define CONTROL_PADCONF_DSS_DATA22	0x0108
+#define CONTROL_PADCONF_DSS_DATA23	0x010A
+/*CAMERA*/
+#define CONTROL_PADCONF_CAM_HS		0x010C
+#define CONTROL_PADCONF_CAM_VS		0x010E
+#define CONTROL_PADCONF_CAM_XCLKA	0x0110
+#define CONTROL_PADCONF_CAM_PCLK	0x0112
+#define CONTROL_PADCONF_CAM_FLD		0x0114
+#define CONTROL_PADCONF_CAM_D0		0x0116
+#define CONTROL_PADCONF_CAM_D1		0x0118
+#define CONTROL_PADCONF_CAM_D2		0x011A
+#define CONTROL_PADCONF_CAM_D3		0x011C
+#define CONTROL_PADCONF_CAM_D4		0x011E
+#define CONTROL_PADCONF_CAM_D5		0x0120
+#define CONTROL_PADCONF_CAM_D6		0x0122
+#define CONTROL_PADCONF_CAM_D7		0x0124
+#define CONTROL_PADCONF_CAM_D8		0x0126
+#define CONTROL_PADCONF_CAM_D9		0x0128
+#define CONTROL_PADCONF_CAM_D10		0x012A
+#define CONTROL_PADCONF_CAM_D11		0x012C
+#define CONTROL_PADCONF_CAM_XCLKB	0x012E
+#define CONTROL_PADCONF_CAM_WEN		0x0130
+#define CONTROL_PADCONF_CAM_STROBE	0x0132
+#define CONTROL_PADCONF_CSI2_DX0	0x0134
+#define CONTROL_PADCONF_CSI2_DY0	0x0136
+#define CONTROL_PADCONF_CSI2_DX1	0x0138
+#define CONTROL_PADCONF_CSI2_DY1	0x013A
+/*Audio Interface */
+#define CONTROL_PADCONF_MCBSP2_FSX	0x013C
+#define CONTROL_PADCONF_MCBSP2_CLKX	0x013E
+#define CONTROL_PADCONF_MCBSP2_DR	0x0140
+#define CONTROL_PADCONF_MCBSP2_DX	0x0142
+#define CONTROL_PADCONF_MMC1_CLK	0x0144
+#define CONTROL_PADCONF_MMC1_CMD	0x0146
+#define CONTROL_PADCONF_MMC1_DAT0	0x0148
+#define CONTROL_PADCONF_MMC1_DAT1	0x014A
+#define CONTROL_PADCONF_MMC1_DAT2	0x014C
+#define CONTROL_PADCONF_MMC1_DAT3	0x014E
+#define CONTROL_PADCONF_MMC1_DAT4	0x0150
+#define CONTROL_PADCONF_MMC1_DAT5	0x0152
+#define CONTROL_PADCONF_MMC1_DAT6	0x0154
+#define CONTROL_PADCONF_MMC1_DAT7	0x0156
+/*Wireless LAN */
+#define CONTROL_PADCONF_MMC2_CLK	0x0158
+#define CONTROL_PADCONF_MMC2_CMD	0x015A
+#define CONTROL_PADCONF_MMC2_DAT0	0x015C
+#define CONTROL_PADCONF_MMC2_DAT1	0x015E
+#define CONTROL_PADCONF_MMC2_DAT2	0x0160
+#define CONTROL_PADCONF_MMC2_DAT3	0x0162
+#define CONTROL_PADCONF_MMC2_DAT4	0x0164
+#define CONTROL_PADCONF_MMC2_DAT5	0x0166
+#define CONTROL_PADCONF_MMC2_DAT6	0x0168
+#define CONTROL_PADCONF_MMC2_DAT7	0x016A
+/*Bluetooth*/
+#define CONTROL_PADCONF_MCBSP3_DX	0x016C
+#define CONTROL_PADCONF_MCBSP3_DR	0x016E
+#define CONTROL_PADCONF_MCBSP3_CLKX	0x0170
+#define CONTROL_PADCONF_MCBSP3_FSX	0x0172
+#define CONTROL_PADCONF_UART2_CTS	0x0174
+#define CONTROL_PADCONF_UART2_RTS	0x0176
+#define CONTROL_PADCONF_UART2_TX	0x0178
+#define CONTROL_PADCONF_UART2_RX	0x017A
+/*Modem Interface */
+#define CONTROL_PADCONF_UART1_TX	0x017C
+#define CONTROL_PADCONF_UART1_RTS	0x017E
+#define CONTROL_PADCONF_UART1_CTS	0x0180
+#define CONTROL_PADCONF_UART1_RX	0x0182
+#define CONTROL_PADCONF_MCBSP4_CLKX	0x0184
+#define CONTROL_PADCONF_MCBSP4_DR	0x0186
+#define CONTROL_PADCONF_MCBSP4_DX	0x0188
+#define CONTROL_PADCONF_MCBSP4_FSX	0x018A
+#define CONTROL_PADCONF_MCBSP1_CLKR	0x018C
+#define CONTROL_PADCONF_MCBSP1_FSR	0x018E
+#define CONTROL_PADCONF_MCBSP1_DX	0x0190
+#define CONTROL_PADCONF_MCBSP1_DR	0x0192
+#define CONTROL_PADCONF_MCBSP_CLKS	0x0194
+#define CONTROL_PADCONF_MCBSP1_FSX	0x0196
+#define CONTROL_PADCONF_MCBSP1_CLKX	0x0198
+/*Serial Interface*/
+#define CONTROL_PADCONF_UART3_CTS_RCTX	0x019A
+#define CONTROL_PADCONF_UART3_RTS_SD	0x019C
+#define CONTROL_PADCONF_UART3_RX_IRRX	0x019E
+#define CONTROL_PADCONF_UART3_TX_IRTX	0x01A0
+#define CONTROL_PADCONF_HSUSB0_CLK	0x01A2
+#define CONTROL_PADCONF_HSUSB0_STP	0x01A4
+#define CONTROL_PADCONF_HSUSB0_DIR	0x01A6
+#define CONTROL_PADCONF_HSUSB0_NXT	0x01A8
+#define CONTROL_PADCONF_HSUSB0_DATA0	0x01AA
+#define CONTROL_PADCONF_HSUSB0_DATA1	0x01AC
+#define CONTROL_PADCONF_HSUSB0_DATA2	0x01AE
+#define CONTROL_PADCONF_HSUSB0_DATA3	0x01B0
+#define CONTROL_PADCONF_HSUSB0_DATA4	0x01B2
+#define CONTROL_PADCONF_HSUSB0_DATA5	0x01B4
+#define CONTROL_PADCONF_HSUSB0_DATA6	0x01B6
+#define CONTROL_PADCONF_HSUSB0_DATA7	0x01B8
+#define CONTROL_PADCONF_I2C1_SCL	0x01BA
+#define CONTROL_PADCONF_I2C1_SDA	0x01BC
+#define CONTROL_PADCONF_I2C2_SCL	0x01BE
+#define CONTROL_PADCONF_I2C2_SDA	0x01C0
+#define CONTROL_PADCONF_I2C3_SCL	0x01C2
+#define CONTROL_PADCONF_I2C3_SDA	0x01C4
+#define CONTROL_PADCONF_I2C4_SCL	0x0A00
+#define CONTROL_PADCONF_I2C4_SDA	0x0A02
+#define CONTROL_PADCONF_HDQ_SIO		0x01C6
+#define CONTROL_PADCONF_MCSPI1_CLK	0x01C8
+#define CONTROL_PADCONF_MCSPI1_SIMO	0x01CA
+#define CONTROL_PADCONF_MCSPI1_SOMI	0x01CC
+#define CONTROL_PADCONF_MCSPI1_CS0	0x01CE
+#define CONTROL_PADCONF_MCSPI1_CS1	0x01D0
+#define CONTROL_PADCONF_MCSPI1_CS2	0x01D2
+#define CONTROL_PADCONF_MCSPI1_CS3	0x01D4
+#define CONTROL_PADCONF_MCSPI2_CLK	0x01D6
+#define CONTROL_PADCONF_MCSPI2_SIMO	0x01D8
+#define CONTROL_PADCONF_MCSPI2_SOMI	0x01DA
+#define CONTROL_PADCONF_MCSPI2_CS0	0x01DC
+#define CONTROL_PADCONF_MCSPI2_CS1	0x01DE
+/*Control and debug */
+#define CONTROL_PADCONF_SYS_32K		0x0A04
+#define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
+#define CONTROL_PADCONF_SYS_NIRQ	0x01E0
+#define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
+#define CONTROL_PADCONF_SYS_BOOT1	0x0A0C
+#define CONTROL_PADCONF_SYS_BOOT2	0x0A0E
+#define CONTROL_PADCONF_SYS_BOOT3	0x0A10
+#define CONTROL_PADCONF_SYS_BOOT4	0x0A12
+#define CONTROL_PADCONF_SYS_BOOT5	0x0A14
+#define CONTROL_PADCONF_SYS_BOOT6	0x0A16
+#define CONTROL_PADCONF_SYS_OFF_MODE	0x0A18
+#define CONTROL_PADCONF_SYS_CLKOUT1	0x0A1A
+#define CONTROL_PADCONF_SYS_CLKOUT2	0x01E2
+#define CONTROL_PADCONF_JTAG_nTRST	0x0A1C
+#define CONTROL_PADCONF_JTAG_TCK	0x0A1E
+#define CONTROL_PADCONF_JTAG_TMS	0x0A20
+#define CONTROL_PADCONF_JTAG_TDI	0x0A22
+#define CONTROL_PADCONF_JTAG_EMU0	0x0A24
+#define CONTROL_PADCONF_JTAG_EMU1	0x0A26
+#define CONTROL_PADCONF_ETK_CLK		0x0A28
+#define CONTROL_PADCONF_ETK_CTL		0x0A2A
+#define CONTROL_PADCONF_ETK_D0		0x0A2C
+#define CONTROL_PADCONF_ETK_D1		0x0A2E
+#define CONTROL_PADCONF_ETK_D2		0x0A30
+#define CONTROL_PADCONF_ETK_D3		0x0A32
+#define CONTROL_PADCONF_ETK_D4		0x0A34
+#define CONTROL_PADCONF_ETK_D5		0x0A36
+#define CONTROL_PADCONF_ETK_D6		0x0A38
+#define CONTROL_PADCONF_ETK_D7		0x0A3A
+#define CONTROL_PADCONF_ETK_D8		0x0A3C
+#define CONTROL_PADCONF_ETK_D9		0x0A3E
+#define CONTROL_PADCONF_ETK_D10		0x0A40
+#define CONTROL_PADCONF_ETK_D11		0x0A42
+#define CONTROL_PADCONF_ETK_D12		0x0A44
+#define CONTROL_PADCONF_ETK_D13		0x0A46
+#define CONTROL_PADCONF_ETK_D14		0x0A48
+#define CONTROL_PADCONF_ETK_D15		0x0A4A
+#define CONTROL_PADCONF_ETK_CLK_ES2	0x05D8
+#define CONTROL_PADCONF_ETK_CTL_ES2	0x05DA
+#define CONTROL_PADCONF_ETK_D0_ES2	0x05DC
+#define CONTROL_PADCONF_ETK_D1_ES2	0x05DE
+#define CONTROL_PADCONF_ETK_D2_ES2	0x05E0
+#define CONTROL_PADCONF_ETK_D3_ES2	0x05E2
+#define CONTROL_PADCONF_ETK_D4_ES2	0x05E4
+#define CONTROL_PADCONF_ETK_D5_ES2	0x05E6
+#define CONTROL_PADCONF_ETK_D6_ES2	0x05E8
+#define CONTROL_PADCONF_ETK_D7_ES2	0x05EA
+#define CONTROL_PADCONF_ETK_D8_ES2	0x05EC
+#define CONTROL_PADCONF_ETK_D9_ES2	0x05EE
+#define CONTROL_PADCONF_ETK_D10_ES2	0x05F0
+#define CONTROL_PADCONF_ETK_D11_ES2	0x05F2
+#define CONTROL_PADCONF_ETK_D12_ES2	0x05F4
+#define CONTROL_PADCONF_ETK_D13_ES2	0x05F6
+#define CONTROL_PADCONF_ETK_D14_ES2	0x05F8
+#define CONTROL_PADCONF_ETK_D15_ES2	0x05FA
+/*Die to Die */
+#define CONTROL_PADCONF_D2D_MCAD0	0x01E4
+#define CONTROL_PADCONF_D2D_MCAD1	0x01E6
+#define CONTROL_PADCONF_D2D_MCAD2	0x01E8
+#define CONTROL_PADCONF_D2D_MCAD3	0x01EA
+#define CONTROL_PADCONF_D2D_MCAD4	0x01EC
+#define CONTROL_PADCONF_D2D_MCAD5	0x01EE
+#define CONTROL_PADCONF_D2D_MCAD6	0x01F0
+#define CONTROL_PADCONF_D2D_MCAD7	0x01F2
+#define CONTROL_PADCONF_D2D_MCAD8	0x01F4
+#define CONTROL_PADCONF_D2D_MCAD9	0x01F6
+#define CONTROL_PADCONF_D2D_MCAD10	0x01F8
+#define CONTROL_PADCONF_D2D_MCAD11	0x01FA
+#define CONTROL_PADCONF_D2D_MCAD12	0x01FC
+#define CONTROL_PADCONF_D2D_MCAD13	0x01FE
+#define CONTROL_PADCONF_D2D_MCAD14	0x0200
+#define CONTROL_PADCONF_D2D_MCAD15	0x0202
+#define CONTROL_PADCONF_D2D_MCAD16	0x0204
+#define CONTROL_PADCONF_D2D_MCAD17	0x0206
+#define CONTROL_PADCONF_D2D_MCAD18	0x0208
+#define CONTROL_PADCONF_D2D_MCAD19	0x020A
+#define CONTROL_PADCONF_D2D_MCAD20	0x020C
+#define CONTROL_PADCONF_D2D_MCAD21	0x020E
+#define CONTROL_PADCONF_D2D_MCAD22	0x0210
+#define CONTROL_PADCONF_D2D_MCAD23	0x0212
+#define CONTROL_PADCONF_D2D_MCAD24	0x0214
+#define CONTROL_PADCONF_D2D_MCAD25	0x0216
+#define CONTROL_PADCONF_D2D_MCAD26	0x0218
+#define CONTROL_PADCONF_D2D_MCAD27	0x021A
+#define CONTROL_PADCONF_D2D_MCAD28	0x021C
+#define CONTROL_PADCONF_D2D_MCAD29	0x021E
+#define CONTROL_PADCONF_D2D_MCAD30	0x0220
+#define CONTROL_PADCONF_D2D_MCAD31	0x0222
+#define CONTROL_PADCONF_D2D_MCAD32	0x0224
+#define CONTROL_PADCONF_D2D_MCAD33	0x0226
+#define CONTROL_PADCONF_D2D_MCAD34	0x0228
+#define CONTROL_PADCONF_D2D_MCAD35	0x022A
+#define CONTROL_PADCONF_D2D_MCAD36	0x022C
+#define CONTROL_PADCONF_D2D_CLK26MI	0x022E
+#define CONTROL_PADCONF_D2D_NRESPWRON	0x0230
+#define CONTROL_PADCONF_D2D_NRESWARM	0x0232
+#define CONTROL_PADCONF_D2D_ARM9NIRQ	0x0234
+#define CONTROL_PADCONF_D2D_UMA2P6FIQ	0x0236
+#define CONTROL_PADCONF_D2D_SPINT	0x0238
+#define CONTROL_PADCONF_D2D_FRINT	0x023A
+#define CONTROL_PADCONF_D2D_DMAREQ0	0x023C
+#define CONTROL_PADCONF_D2D_DMAREQ1	0x023E
+#define CONTROL_PADCONF_D2D_DMAREQ2	0x0240
+#define CONTROL_PADCONF_D2D_DMAREQ3	0x0242
+#define CONTROL_PADCONF_D2D_N3GTRST	0x0244
+#define CONTROL_PADCONF_D2D_N3GTDI	0x0246
+#define CONTROL_PADCONF_D2D_N3GTDO	0x0248
+#define CONTROL_PADCONF_D2D_N3GTMS	0x024A
+#define CONTROL_PADCONF_D2D_N3GTCK	0x024C
+#define CONTROL_PADCONF_D2D_N3GRTCK	0x024E
+#define CONTROL_PADCONF_D2D_MSTDBY	0x0250
+#define CONTROL_PADCONF_D2D_SWAKEUP	0x0A4C
+#define CONTROL_PADCONF_D2D_IDLEREQ	0x0252
+#define CONTROL_PADCONF_D2D_IDLEACK	0x0254
+#define CONTROL_PADCONF_D2D_MWRITE	0x0256
+#define CONTROL_PADCONF_D2D_SWRITE	0x0258
+#define CONTROL_PADCONF_D2D_MREAD	0x025A
+#define CONTROL_PADCONF_D2D_SREAD	0x025C
+#define CONTROL_PADCONF_D2D_MBUSFLAG	0x025E
+#define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
+#define CONTROL_PADCONF_SDRC_CKE0	0x0262
+#define CONTROL_PADCONF_SDRC_CKE1	0x0264
+
+/* AM3517 specific mux configuration */
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
+/* CCDC */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
+#define CONTROL_PADCONF_CCDC_HD		0x01E8
+#define CONTROL_PADCONF_CCDC_VD		0x01EA
+#define CONTROL_PADCONF_CCDC_WEN	0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
+/* RMII */
+#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
+#define CONTROL_PADCONF_RMII_RXD0	0x0202
+#define CONTROL_PADCONF_RMII_RXD1	0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
+#define CONTROL_PADCONF_RMII_RXER	0x0208
+#define CONTROL_PADCONF_RMII_TXD0	0x020A
+#define CONTROL_PADCONF_RMII_TXD1	0x020C
+#define CONTROL_PADCONF_RMII_TXEN	0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
+/* CAN */
+#define CONTROL_PADCONF_HECC1_TXD	0x0214
+#define CONTROL_PADCONF_HECC1_RXD	0x0216
+
+#define CONTROL_PADCONF_SYS_BOOT7	0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
+#define CONTROL_PADCONF_SYS_BOOT8	0x0226
+
+/* AM/DM37xx specific */
+#define CONTROL_PADCONF_GPIO127		0x0A54
+#define CONTROL_PADCONF_GPIO126		0x0A56
+#define CONTROL_PADCONF_GPIO128		0x0A58
+#define CONTROL_PADCONF_GPIO129		0x0A5A
+
+/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration
+ * of the extended drain cells */
+#define OMAP34XX_CTRL_WKUP_CTRL		(OMAP34XX_CTRL_BASE + 0x0A5C)
+#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ	(1<<6)
+
+#define MUX_VAL(OFFSET,VALUE)\
+	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+
+#define	CP(x)	(CONTROL_PADCONF_##x)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h
new file mode 100644
index 000000000..002ef7e79
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3-regs.h
@@ -0,0 +1,79 @@
+/*
+ * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _OMAP3_REGS_H
+#define _OMAP3_REGS_H
+
+/*
+ * Register definitions for OMAP3 processors.
+ */
+
+/*
+ * GPMC_CONFIG1 - GPMC_CONFIG7
+ */
+
+/* Values for GPMC_CONFIG1 - signal control parameters */
+#define WRAPBURST                     (1 << 31)
+#define READMULTIPLE                  (1 << 30)
+#define READTYPE                      (1 << 29)
+#define WRITEMULTIPLE                 (1 << 28)
+#define WRITETYPE                     (1 << 27)
+#define CLKACTIVATIONTIME(x)          (((x) & 3) << 25)
+#define ATTACHEDDEVICEPAGELENGTH(x)   (((x) & 3) << 23)
+#define WAITREADMONITORING            (1 << 22)
+#define WAITWRITEMONITORING           (1 << 21)
+#define WAITMONITORINGTIME(x)         (((x) & 3) << 18)
+#define WAITPINSELECT(x)              (((x) & 3) << 16)
+#define DEVICESIZE(x)                 (((x) & 3) << 12)
+#define DEVICESIZE_8BIT               DEVICESIZE(0)
+#define DEVICESIZE_16BIT              DEVICESIZE(1)
+#define DEVICETYPE(x)                 (((x) & 3) << 10)
+#define DEVICETYPE_NOR                DEVICETYPE(0)
+#define DEVICETYPE_NAND               DEVICETYPE(2)
+#define MUXADDDATA                    (1 << 9)
+#define TIMEPARAGRANULARITY           (1 << 4)
+#define GPMCFCLKDIVIDER(x)            (((x) & 3) << 0)
+
+/* Values for GPMC_CONFIG2 - CS timing */
+#define CSWROFFTIME(x)   (((x) & 0x1f) << 16)
+#define CSRDOFFTIME(x)   (((x) & 0x1f) <<  8)
+#define CSEXTRADELAY     (1 << 7)
+#define CSONTIME(x)      (((x) &  0xf) <<  0)
+
+/* Values for GPMC_CONFIG3 - nADV timing */
+#define ADVWROFFTIME(x)  (((x) & 0x1f) << 16)
+#define ADVRDOFFTIME(x)  (((x) & 0x1f) <<  8)
+#define ADVEXTRADELAY    (1 << 7)
+#define ADVONTIME(x)     (((x) &  0xf) <<  0)
+
+/* Values for GPMC_CONFIG4 - nWE and nOE timing */
+#define WEOFFTIME(x)     (((x) & 0x1f) << 24)
+#define WEEXTRADELAY     (1 << 23)
+#define WEONTIME(x)      (((x) &  0xf) << 16)
+#define OEOFFTIME(x)     (((x) & 0x1f) <<  8)
+#define OEEXTRADELAY     (1 << 7)
+#define OEONTIME(x)      (((x) &  0xf) <<  0)
+
+/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */
+#define PAGEBURSTACCESSTIME(x)  (((x) &  0xf) << 24)
+#define RDACCESSTIME(x)         (((x) & 0x1f) << 16)
+#define WRCYCLETIME(x)          (((x) & 0x1f) <<  8)
+#define RDCYCLETIME(x)          (((x) & 0x1f) <<  0)
+
+/* Values for GPMC_CONFIG6 - misc timings */
+#define WRACCESSTIME(x)        (((x) & 0x1f) << 24)
+#define WRDATAONADMUXBUS(x)    (((x) &  0xf) << 16)
+#define CYCLE2CYCLEDELAY(x)    (((x) &  0xf) <<  8)
+#define CYCLE2CYCLESAMECSEN    (1 << 7)
+#define CYCLE2CYCLEDIFFCSEN    (1 << 6)
+#define BUSTURNAROUND(x)       (((x) &  0xf) <<  0)
+
+/* Values for GPMC_CONFIG7 - CS address mapping configuration */
+#define MASKADDRESS(x)         (((x) &  0xf) <<  8)
+#define CSVALID                (1 << 6)
+#define BASEADDRESS(x)         (((x) & 0x3f) <<  0)
+
+#endif /* _OMAP3_REGS_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3.h
new file mode 100644
index 000000000..194b93bf5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/omap3.h
@@ -0,0 +1,248 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _OMAP3_H_
+#define _OMAP3_H_
+
+/* Stuff on L3 Interconnect */
+#define SMX_APE_BASE			0x68000000
+
+/* GPMC */
+#define OMAP34XX_GPMC_BASE		0x6E000000
+
+/* SMS */
+#define OMAP34XX_SMS_BASE		0x6C000000
+
+/* SDRC */
+#define OMAP34XX_SDRC_BASE		0x6D000000
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP34XX_CORE_L4_IO_BASE	0x48000000
+#define OMAP34XX_WAKEUP_L4_IO_BASE	0x48300000
+#define OMAP34XX_ID_L4_IO_BASE		0x4830A200
+#define OMAP34XX_L4_PER			0x49000000
+#define OMAP34XX_L4_IO_BASE		OMAP34XX_CORE_L4_IO_BASE
+
+/* DMA4/SDMA */
+#define OMAP34XX_DMA4_BASE              0x48056000
+
+/* CONTROL */
+#define OMAP34XX_CTRL_BASE		(OMAP34XX_L4_IO_BASE + 0x2000)
+
+#ifndef __ASSEMBLY__
+/* Signal Integrity Parameter Control Registers */
+struct control_prog_io {
+	unsigned char res[0x408];
+	unsigned int io2;		/* 0x408 */
+	unsigned char res2[0x38];
+	unsigned int io0;		/* 0x444 */
+	unsigned int io1;		/* 0x448 */
+};
+#endif /* __ASSEMBLY__ */
+
+/* Bit definition for CONTROL_PROG_IO1 */
+#define PRG_I2C2_PULLUPRESX		0x00000001
+
+/* UART */
+#define OMAP34XX_UART1			(OMAP34XX_L4_IO_BASE + 0x6a000)
+#define OMAP34XX_UART2			(OMAP34XX_L4_IO_BASE + 0x6c000)
+#define OMAP34XX_UART3			(OMAP34XX_L4_PER + 0x20000)
+#define OMAP34XX_UART4			(OMAP34XX_L4_PER + 0x42000)
+
+/* General Purpose Timers */
+#define OMAP34XX_GPT1			0x48318000
+#define OMAP34XX_GPT2			0x49032000
+#define OMAP34XX_GPT3			0x49034000
+#define OMAP34XX_GPT4			0x49036000
+#define OMAP34XX_GPT5			0x49038000
+#define OMAP34XX_GPT6			0x4903A000
+#define OMAP34XX_GPT7			0x4903C000
+#define OMAP34XX_GPT8			0x4903E000
+#define OMAP34XX_GPT9			0x49040000
+#define OMAP34XX_GPT10			0x48086000
+#define OMAP34XX_GPT11			0x48088000
+#define OMAP34XX_GPT12			0x48304000
+
+/* WatchDog Timers (1 secure, 3 GP) */
+#define WD1_BASE			0x4830C000
+#define WD2_BASE			0x48314000
+#define WD3_BASE			0x49030000
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE		0x48320000
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+	unsigned char res[0x10];
+	unsigned int s32k_cr;		/* 0x10 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#ifndef __ASSEMBLY__
+struct gpio {
+	unsigned char res1[0x34];
+	unsigned int oe;		/* 0x34 */
+	unsigned int datain;		/* 0x38 */
+	unsigned char res2[0x54];
+	unsigned int cleardataout;	/* 0x90 */
+	unsigned int setdataout;	/* 0x94 */
+};
+#endif /* __ASSEMBLY__ */
+
+#define GPIO0				(0x1 << 0)
+#define GPIO1				(0x1 << 1)
+#define GPIO2				(0x1 << 2)
+#define GPIO3				(0x1 << 3)
+#define GPIO4				(0x1 << 4)
+#define GPIO5				(0x1 << 5)
+#define GPIO6				(0x1 << 6)
+#define GPIO7				(0x1 << 7)
+#define GPIO8				(0x1 << 8)
+#define GPIO9				(0x1 << 9)
+#define GPIO10				(0x1 << 10)
+#define GPIO11				(0x1 << 11)
+#define GPIO12				(0x1 << 12)
+#define GPIO13				(0x1 << 13)
+#define GPIO14				(0x1 << 14)
+#define GPIO15				(0x1 << 15)
+#define GPIO16				(0x1 << 16)
+#define GPIO17				(0x1 << 17)
+#define GPIO18				(0x1 << 18)
+#define GPIO19				(0x1 << 19)
+#define GPIO20				(0x1 << 20)
+#define GPIO21				(0x1 << 21)
+#define GPIO22				(0x1 << 22)
+#define GPIO23				(0x1 << 23)
+#define GPIO24				(0x1 << 24)
+#define GPIO25				(0x1 << 25)
+#define GPIO26				(0x1 << 26)
+#define GPIO27				(0x1 << 27)
+#define GPIO28				(0x1 << 28)
+#define GPIO29				(0x1 << 29)
+#define GPIO30				(0x1 << 30)
+#define GPIO31				(0x1 << 31)
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0			0x40000000
+#define SRAM_OFFSET1			0x00200000
+#define SRAM_OFFSET2			0x0000F800
+#define SRAM_VECT_CODE			(SRAM_OFFSET0 | SRAM_OFFSET1 | \
+					 SRAM_OFFSET2)
+#define SRAM_CLK_CODE			(SRAM_VECT_CODE + 64)
+
+#define NON_SECURE_SRAM_START		0x40208000 /* Works for GP & EMU */
+#define NON_SECURE_SRAM_END		0x40210000
+
+#define LOW_LEVEL_SRAM_STACK		0x4020FFFC
+
+/* scratch area - accessible on both EMU and GP */
+#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA	NON_SECURE_SRAM_START
+
+#define DEBUG_LED1			149	/* gpio */
+#define DEBUG_LED2			150	/* gpio */
+
+#define XDR_POP		5	/* package on package part */
+#define SDR_DISCRETE	4	/* 128M memory SDR module */
+#define DDR_STACKED	3	/* stacked part on 2422 */
+#define DDR_COMBO	2	/* combo part on cpu daughter card */
+#define DDR_DISCRETE	1	/* 2x16 parts on daughter card */
+
+#define DDR_100		100	/* type found on most mem d-boards */
+#define DDR_111		111	/* some combo parts */
+#define DDR_133		133	/* most combo, some mem d-boards */
+#define DDR_165		165	/* future parts */
+
+#define CPU_3430	0x3430
+
+/*
+ * 343x real hardware:
+ *  ES1     = rev 0
+ *
+ *  ES2 onwards, the value maps to contents of IDCODE register [31:28].
+ *
+ * Note : CPU_3XX_ES20 is used in cache.S.  Please review before changing.
+ */
+#define CPU_3XX_ES10		0
+#define CPU_3XX_ES20		1
+#define CPU_3XX_ES21		2
+#define CPU_3XX_ES30		3
+#define CPU_3XX_ES31		4
+#define CPU_3XX_ES312		7
+#define CPU_3XX_MAX_REV		8
+
+/*
+ * 37xx real hardware:
+ * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
+ */
+
+#define CPU_37XX_ES10		0
+#define CPU_37XX_ES11		1
+#define CPU_37XX_ES12		2
+#define CPU_37XX_MAX_REV	3
+
+#define CPU_3XX_ID_SHIFT	28
+
+#define WIDTH_8BIT		0x0000
+#define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
+
+/*
+ * Hawkeye values
+ */
+#define HAWKEYE_OMAP34XX	0xb7ae
+#define HAWKEYE_AM35XX		0xb868
+#define HAWKEYE_OMAP36XX	0xb891
+
+#define HAWKEYE_SHIFT		12
+
+/*
+ * Define CPU families
+ */
+#define CPU_OMAP34XX		0x3400	/* OMAP34xx/OMAP35 devices */
+#define CPU_AM35XX		0x3500	/* AM35xx devices          */
+#define CPU_OMAP36XX		0x3600	/* OMAP36xx devices        */
+
+/*
+ * Control status register values corresponding to cpu variants
+ */
+#define OMAP3503		0x5c00
+#define OMAP3515		0x1c00
+#define OMAP3525		0x4c00
+#define OMAP3530		0x0c00
+
+#define AM3505			0x5c00
+#define AM3517			0x1c00
+
+#define OMAP3730		0x0c00
+
+/*
+ * ROM code API related flags
+ */
+#define OMAP3_GP_ROMCODE_API_L2_INVAL		1
+#define OMAP3_GP_ROMCODE_API_WRITE_ACR		3
+
+/*
+ * EMU device PPA HAL related flags
+ */
+#define OMAP3_EMU_HAL_API_L2_INVAL		40
+#define OMAP3_EMU_HAL_API_WRITE_ACR		42
+
+#define OMAP3_EMU_HAL_START_HAL_CRITICAL	4
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME		30
+#define OMAP_ABB_CLOCK_CYCLES		8
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK	(0x1 << 26)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h
new file mode 100644
index 000000000..835053278
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/spl.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_NAND	2
+#define BOOT_DEVICE_ONENAND	3
+#define BOOT_DEVICE_MMC2	5 /*emmc*/
+#define BOOT_DEVICE_MMC1	6
+#define BOOT_DEVICE_XIPWAIT	7
+#define BOOT_DEVICE_MMC2_2      0xFF
+
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC2
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC1
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h
new file mode 100644
index 000000000..5866bf23e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+#include <linux/mtd/omap_gpmc.h>
+#include <asm/omap_common.h>
+
+typedef struct {
+	u32 mtype;
+	char *board_string;
+	char *nand_string;
+} omap3_sysinfo;
+
+struct emu_hal_params {
+	u32 num_params;
+	u32 param1;
+};
+
+/* Board SDRC timing values */
+struct board_sdrc_timings {
+	u32 mcfg;
+	u32 ctrla;
+	u32 ctrlb;
+	u32 rfr_ctrl;
+	u32 mr;
+};
+
+void prcm_init(void);
+void per_clocks_enable(void);
+void ehci_clocks_enable(void);
+
+void memif_init(void);
+void sdrc_init(void);
+void do_sdrc_init(u32, u32);
+
+void get_board_mem_timings(struct board_sdrc_timings *timings);
+void identify_nand_chip(int *mfr, int *id);
+void emif4_init(void);
+void gpmc_init(void);
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+			u32 size);
+
+void watchdog_init(void);
+void set_muxconf_regs(void);
+
+u32 get_cpu_family(void);
+u32 get_cpu_rev(void);
+u32 get_sku_id(void);
+u32 get_sysboot_value(void);
+u32 is_gpmc_muxed(void);
+u32 get_gpmc0_type(void);
+u32 get_gpmc0_width(void);
+u32 is_running_in_sdram(void);
+u32 is_running_in_sram(void);
+u32 is_running_in_flash(void);
+u32 get_device_type(void);
+void secureworld_exit(void);
+void try_unlock_memory(void);
+u32 get_boot_type(void);
+void invalidate_dcache(u32);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void make_cs1_contiguous(void);
+void omap_nand_switch_ecc(uint32_t, uint32_t);
+void power_init_r(void);
+void dieid_num_r(void);
+void get_dieid(u32 *id);
+void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
+void omap3_gp_romcode_call(u32 service_id, u32 parameter);
+u32 warm_reset(void);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/clock.h
new file mode 100644
index 000000000..f3a682a19
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/clock.h
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _CLOCKS_OMAP4_H_
+#define _CLOCKS_OMAP4_H_
+#include <common.h>
+#include <asm/omap_common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY		1000000
+
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_OVERRIDE_SHIFT	0
+#define CM_DLL_CTRL_OVERRIDE_MASK	(1 << 0)
+#define CM_DLL_CTRL_NO_OVERRIDE		0
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_FAST_RELOCK_BYPASS	6
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT			22
+#define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT	0
+#define CLKSEL_L3_SHIFT		4
+#define CLKSEL_L4_SHIFT		8
+
+#define CLKSEL_CORE_X2_DIV_1	0
+#define CLKSEL_L3_CORE_DIV_2	1
+#define CLKSEL_L4_L3_DIV_2	1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(1 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	25
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 25)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_IND_38_4_MHZ	6
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
+
+/* PMIC */
+#define SMPS_I2C_SLAVE_ADDR	0x12
+/* TWL6030 SMPS */
+#define SMPS_REG_ADDR_VCORE1	0x55
+#define SMPS_REG_ADDR_VCORE2	0x5B
+#define SMPS_REG_ADDR_VCORE3	0x61
+/* TWL6032 SMPS */
+#define SMPS_REG_ADDR_SMPS1	0x55
+#define SMPS_REG_ADDR_SMPS2	0x5B
+#define SMPS_REG_ADDR_SMPS5	0x49
+
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000
+
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR		0x60
+#define TPS62361_REG_ADDR_SET0		0x0
+#define TPS62361_REG_ADDR_SET1		0x1
+#define TPS62361_REG_ADDR_SET2		0x2
+#define TPS62361_REG_ADDR_SET3		0x3
+#define TPS62361_REG_ADDR_CTRL		0x4
+#define TPS62361_REG_ADDR_TEMP		0x5
+#define TPS62361_REG_ADDR_RMP_CTRL	0x6
+#define TPS62361_REG_ADDR_CHIP_ID	0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2	0x9
+
+#define TPS62361_BASE_VOLT_MV	500
+#define TPS62361_VSEL0_GPIO	7
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK		(1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT		1
+#define AUXCLK_SRCSELECT_MASK		(3 << 1)
+#define AUXCLK_CLKDIV_SHIFT		16
+#define AUXCLK_CLKDIV_MASK		(0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK	0
+#define AUXCLK_SRCSELECT_CORE_DPLL	1
+#define AUXCLK_SRCSELECT_PER_DPLL	2
+#define AUXCLK_SRCSELECT_ALTERNATE	3
+
+#define AUXCLK_CLKDIV_2			1
+#define AUXCLK_CLKDIV_16		0xF
+
+/* ALTCLKSRC */
+#define ALTCLKSRC_MODE_MASK		3
+#define ALTCLKSRC_ENABLE_INT_MASK	4
+#define ALTCLKSRC_ENABLE_EXT_MASK	8
+
+#define ALTCLKSRC_MODE_ACTIVE		1
+
+#define DPLL_NO_LOCK	0
+#define DPLL_LOCK	1
+
+/* Clock Defines */
+#define V_OSCK			38400000	/* Clock output from T2 */
+#define V_SCLK                   V_OSCK
+
+struct omap4_scrm_regs {
+	u32 revision;           /* 0x0000 */
+	u32 pad00[63];
+	u32 clksetuptime;       /* 0x0100 */
+	u32 pmicsetuptime;      /* 0x0104 */
+	u32 pad01[2];
+	u32 altclksrc;          /* 0x0110 */
+	u32 pad02[2];
+	u32 c2cclkm;            /* 0x011c */
+	u32 pad03[56];
+	u32 extclkreq;          /* 0x0200 */
+	u32 accclkreq;          /* 0x0204 */
+	u32 pwrreq;             /* 0x0208 */
+	u32 pad04[1];
+	u32 auxclkreq0;         /* 0x0210 */
+	u32 auxclkreq1;         /* 0x0214 */
+	u32 auxclkreq2;         /* 0x0218 */
+	u32 auxclkreq3;         /* 0x021c */
+	u32 auxclkreq4;         /* 0x0220 */
+	u32 auxclkreq5;         /* 0x0224 */
+	u32 pad05[3];
+	u32 c2cclkreq;          /* 0x0234 */
+	u32 pad06[54];
+	u32 auxclk0;            /* 0x0310 */
+	u32 auxclk1;            /* 0x0314 */
+	u32 auxclk2;            /* 0x0318 */
+	u32 auxclk3;            /* 0x031c */
+	u32 auxclk4;            /* 0x0320 */
+	u32 auxclk5;            /* 0x0324 */
+	u32 pad07[54];
+	u32 rsttime_reg;        /* 0x0400 */
+	u32 pad08[6];
+	u32 c2crstctrl;         /* 0x041c */
+	u32 extpwronrstctrl;    /* 0x0420 */
+	u32 pad09[59];
+	u32 extwarmrstst_reg;   /* 0x0510 */
+	u32 apewarmrstst_reg;   /* 0x0514 */
+	u32 pad10[1];
+	u32 c2cwarmrstst_reg;   /* 0x051C */
+};
+#endif /* _CLOCKS_OMAP4_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/cpu.h
new file mode 100644
index 000000000..c21fb5471
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/cpu.h
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2006-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gptimer {
+	u32 tidr;		/* 0x00 r */
+	u8 res[0xc];
+	u32 tiocp_cfg;		/* 0x10 rw */
+	u32 tistat;		/* 0x14 r */
+	u32 tisr;		/* 0x18 rw */
+	u32 tier;		/* 0x1c rw */
+	u32 twer;		/* 0x20 rw */
+	u32 tclr;		/* 0x24 rw */
+	u32 tcrr;		/* 0x28 rw */
+	u32 tldr;		/* 0x2c rw */
+	u32 ttgr;		/* 0x30 rw */
+	u32 twpc;		/* 0x34 r */
+	u32 tmar;		/* 0x38 rw */
+	u32 tcar1;		/* 0x3c r */
+	u32 tcicr;		/* 0x40 rw */
+	u32 tcar2;		/* 0x44 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+	u8 res1[0x34];
+	u32 wwps;		/* 0x34 r */
+	u8 res2[0x10];
+	u32 wspr;		/* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* GPMC BASE */
+#define GPMC_BASE		(OMAP44XX_GPMC_BASE)
+
+/* I2C base */
+#define I2C_BASE1		(OMAP44XX_L4_PER_BASE + 0x70000)
+#define I2C_BASE2		(OMAP44XX_L4_PER_BASE + 0x72000)
+#define I2C_BASE3		(OMAP44XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4		(OMAP44XX_L4_PER_BASE + 0x350000)
+
+/* MUSB base */
+#define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)
+
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x0118
+#define OMAP_GPIO_IRQSTATUS2		0x0128
+#define OMAP_GPIO_IRQENABLE2		0x012c
+#define OMAP_GPIO_IRQENABLE1		0x011c
+#define OMAP_GPIO_WAKE_EN		0x0120
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0160
+#define OMAP_GPIO_SETIRQENABLE1		0x0164
+#define OMAP_GPIO_CLEARWKUENA		0x0180
+#define OMAP_GPIO_SETWKUENA		0x0184
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE		0x4A306000
+#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL		PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET	0x01
+#define PRM_RSTST		(PRM_DEVICE_BASE + 0x4)
+#define PRM_RSTST_WARM_RESET_MASK	0x07EA
+
+#endif /* _CPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/ehci.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/ehci.h
new file mode 100644
index 000000000..984c8b9f7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/ehci.h
@@ -0,0 +1,49 @@
+/*
+ * OMAP EHCI port support
+ * Based on LINUX KERNEL
+ * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Govindraj R <govindraj.raja@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2  of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _OMAP4_EHCI_H_
+#define _OMAP4_EHCI_H_
+
+#define OMAP_EHCI_BASE				(OMAP44XX_L4_CORE_BASE + 0x64C00)
+#define OMAP_UHH_BASE				(OMAP44XX_L4_CORE_BASE + 0x64000)
+#define OMAP_USBTLL_BASE			(OMAP44XX_L4_CORE_BASE + 0x62000)
+
+/* UHH, TLL and opt clocks */
+#define CM_L3INIT_HSUSBHOST_CLKCTRL		0x4A009358UL
+
+#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK	(1 << 24)
+
+/* TLL Register Set */
+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE		(1 << 3)
+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP		(1 << 2)
+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET		(1 << 1)
+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY		(1 << 8)
+#define OMAP_USBTLL_SYSSTATUS_RESETDONE		1
+
+#define OMAP_UHH_SYSCONFIG_SOFTRESET		1
+#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE	(1 << 2)
+#define OMAP_UHH_SYSCONFIG_NOIDLE		(1 << 2)
+#define OMAP_UHH_SYSCONFIG_NOSTDBY		(1 << 4)
+
+#define OMAP_UHH_SYSCONFIG_VAL	(OMAP_UHH_SYSCONFIG_NOIDLE | \
+					OMAP_UHH_SYSCONFIG_NOSTDBY)
+
+#endif /* _OMAP4_EHCI_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/gpio.h
new file mode 100644
index 000000000..72ba1d71a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+#ifndef _GPIO_OMAP4_H
+#define _GPIO_OMAP4_H
+
+#include <asm/omap_gpio.h>
+
+#define OMAP_MAX_GPIO			192
+
+#define OMAP44XX_GPIO1_BASE		0x4A310000
+#define OMAP44XX_GPIO2_BASE		0x48055000
+#define OMAP44XX_GPIO3_BASE		0x48057000
+#define OMAP44XX_GPIO4_BASE		0x48059000
+#define OMAP44XX_GPIO5_BASE		0x4805B000
+#define OMAP44XX_GPIO6_BASE		0x4805D000
+
+#endif /* _GPIO_OMAP4_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/i2c.h
new file mode 100644
index 000000000..adc8eb23f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/i2c.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _OMAP4_I2C_H_
+#define _OMAP4_I2C_H_
+
+#define I2C_BUS_MAX	4
+#define I2C_DEFAULT_BASE	I2C_BASE1
+
+struct i2c {
+	unsigned short revnb_lo;	/* 0x00 */
+	unsigned short res1;
+	unsigned short revnb_hi;	/* 0x04 */
+	unsigned short res2[13];
+	unsigned short sysc;		/* 0x20 */
+	unsigned short res3;
+	unsigned short irqstatus_raw;	/* 0x24 */
+	unsigned short res4;
+	unsigned short stat;		/* 0x28 */
+	unsigned short res5;
+	unsigned short ie;		/* 0x2C */
+	unsigned short res6;
+	unsigned short irqenable_clr;	/* 0x30 */
+	unsigned short res7;
+	unsigned short iv;		/* 0x34 */
+	unsigned short res8[45];
+	unsigned short syss;		/* 0x90 */
+	unsigned short res9;
+	unsigned short buf;		/* 0x94 */
+	unsigned short res10;
+	unsigned short cnt;		/* 0x98 */
+	unsigned short res11;
+	unsigned short data;		/* 0x9C */
+	unsigned short res13;
+	unsigned short res14;		/* 0xA0 */
+	unsigned short res15;
+	unsigned short con;		/* 0xA4 */
+	unsigned short res16;
+	unsigned short oa;		/* 0xA8 */
+	unsigned short res17;
+	unsigned short sa;		/* 0xAC */
+	unsigned short res18;
+	unsigned short psc;		/* 0xB0 */
+	unsigned short res19;
+	unsigned short scll;		/* 0xB4 */
+	unsigned short res20;
+	unsigned short sclh;		/* 0xB8 */
+	unsigned short res21;
+	unsigned short systest;		/* 0xBC */
+	unsigned short res22;
+	unsigned short bufstat;		/* 0xC0 */
+	unsigned short res23;
+};
+
+#endif /* _OMAP4_I2C_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mmc_host_def.h
new file mode 100644
index 000000000..9c8ccb6c8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+#include <asm/omap_mmc.h>
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE	0x4809C100
+#define OMAP_HSMMC2_BASE	0x480B4100
+#define OMAP_HSMMC3_BASE	0x480AD100
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mux_omap4.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mux_omap4.h
new file mode 100644
index 000000000..b22277813
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/mux_omap4.h
@@ -0,0 +1,329 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff		<r-woodruff2@ti.com>
+ * Aneesh V			<aneesh@ti.com>
+ * Balaji Krishnamoorthy	<balajitk@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _MUX_OMAP4_H_
+#define _MUX_OMAP4_H_
+
+#include <asm/types.h>
+
+struct pad_conf_entry {
+
+	u16 offset;
+
+	u16 val;
+
+};
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_PD          (1 << 12)
+#define OFF_PU          (3 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (2 << 10)
+#define OFF_IN          (1 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (1 << 9)
+#else
+#define OFF_PD          (0 << 12)
+#define OFF_PU          (0 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (0 << 10)
+#define OFF_IN          (0 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (0 << 9)
+#endif
+
+#define IEN             (1 << 8)
+#define IDIS            (0 << 8)
+#define PTU             (3 << 3)
+#define PTD             (1 << 3)
+#define EN              (1 << 3)
+#define DIS             (0 << 3)
+
+#define M0              0
+#define M1              1
+#define M2              2
+#define M3              3
+#define M4              4
+#define M5              5
+#define M6              6
+#define M7              7
+
+#define SAFE_MODE	M7
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
+#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
+#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
+#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
+#else
+#define OFF_IN_PD       0
+#define OFF_IN_PU       0
+#define OFF_OUT_PD      0
+#define OFF_OUT_PU      0
+#endif
+
+#define CORE_REVISION		0x0000
+#define CORE_HWINFO		0x0004
+#define CORE_SYSCONFIG		0x0010
+#define GPMC_AD0		0x0040
+#define GPMC_AD1		0x0042
+#define GPMC_AD2		0x0044
+#define GPMC_AD3		0x0046
+#define GPMC_AD4		0x0048
+#define GPMC_AD5		0x004A
+#define GPMC_AD6		0x004C
+#define GPMC_AD7		0x004E
+#define GPMC_AD8		0x0050
+#define GPMC_AD9		0x0052
+#define GPMC_AD10		0x0054
+#define GPMC_AD11		0x0056
+#define GPMC_AD12		0x0058
+#define GPMC_AD13		0x005A
+#define GPMC_AD14		0x005C
+#define GPMC_AD15		0x005E
+#define GPMC_A16		0x0060
+#define GPMC_A17		0x0062
+#define GPMC_A18		0x0064
+#define GPMC_A19		0x0066
+#define GPMC_A20		0x0068
+#define GPMC_A21		0x006A
+#define GPMC_A22		0x006C
+#define GPMC_A23		0x006E
+#define GPMC_A24		0x0070
+#define GPMC_A25		0x0072
+#define GPMC_NCS0		0x0074
+#define GPMC_NCS1		0x0076
+#define GPMC_NCS2		0x0078
+#define GPMC_NCS3		0x007A
+#define GPMC_NWP		0x007C
+#define GPMC_CLK		0x007E
+#define GPMC_NADV_ALE		0x0080
+#define GPMC_NOE		0x0082
+#define GPMC_NWE		0x0084
+#define GPMC_NBE0_CLE		0x0086
+#define GPMC_NBE1		0x0088
+#define GPMC_WAIT0		0x008A
+#define GPMC_WAIT1		0x008C
+#define C2C_DATA11		0x008E
+#define C2C_DATA12		0x0090
+#define C2C_DATA13		0x0092
+#define C2C_DATA14		0x0094
+#define C2C_DATA15		0x0096
+#define HDMI_HPD		0x0098
+#define HDMI_CEC		0x009A
+#define HDMI_DDC_SCL		0x009C
+#define HDMI_DDC_SDA		0x009E
+#define CSI21_DX0		0x00A0
+#define CSI21_DY0		0x00A2
+#define CSI21_DX1		0x00A4
+#define CSI21_DY1		0x00A6
+#define CSI21_DX2		0x00A8
+#define CSI21_DY2		0x00AA
+#define CSI21_DX3		0x00AC
+#define CSI21_DY3		0x00AE
+#define CSI21_DX4		0x00B0
+#define CSI21_DY4		0x00B2
+#define CSI22_DX0		0x00B4
+#define CSI22_DY0		0x00B6
+#define CSI22_DX1		0x00B8
+#define CSI22_DY1		0x00BA
+#define CAM_SHUTTER		0x00BC
+#define CAM_STROBE		0x00BE
+#define CAM_GLOBALRESET		0x00C0
+#define USBB1_ULPITLL_CLK	0x00C2
+#define USBB1_ULPITLL_STP	0x00C4
+#define USBB1_ULPITLL_DIR	0x00C6
+#define USBB1_ULPITLL_NXT	0x00C8
+#define USBB1_ULPITLL_DAT0	0x00CA
+#define USBB1_ULPITLL_DAT1	0x00CC
+#define USBB1_ULPITLL_DAT2	0x00CE
+#define USBB1_ULPITLL_DAT3	0x00D0
+#define USBB1_ULPITLL_DAT4	0x00D2
+#define USBB1_ULPITLL_DAT5	0x00D4
+#define USBB1_ULPITLL_DAT6	0x00D6
+#define USBB1_ULPITLL_DAT7	0x00D8
+#define USBB1_HSIC_DATA		0x00DA
+#define USBB1_HSIC_STROBE	0x00DC
+#define USBC1_ICUSB_DP		0x00DE
+#define USBC1_ICUSB_DM		0x00E0
+#define SDMMC1_CLK		0x00E2
+#define SDMMC1_CMD		0x00E4
+#define SDMMC1_DAT0		0x00E6
+#define SDMMC1_DAT1		0x00E8
+#define SDMMC1_DAT2		0x00EA
+#define SDMMC1_DAT3		0x00EC
+#define SDMMC1_DAT4		0x00EE
+#define SDMMC1_DAT5		0x00F0
+#define SDMMC1_DAT6		0x00F2
+#define SDMMC1_DAT7		0x00F4
+#define ABE_MCBSP2_CLKX		0x00F6
+#define ABE_MCBSP2_DR		0x00F8
+#define ABE_MCBSP2_DX		0x00FA
+#define ABE_MCBSP2_FSX		0x00FC
+#define ABE_MCBSP1_CLKX		0x00FE
+#define ABE_MCBSP1_DR		0x0100
+#define ABE_MCBSP1_DX		0x0102
+#define ABE_MCBSP1_FSX		0x0104
+#define ABE_PDM_UL_DATA		0x0106
+#define ABE_PDM_DL_DATA		0x0108
+#define ABE_PDM_FRAME		0x010A
+#define ABE_PDM_LB_CLK		0x010C
+#define ABE_CLKS		0x010E
+#define ABE_DMIC_CLK1		0x0110
+#define ABE_DMIC_DIN1		0x0112
+#define ABE_DMIC_DIN2		0x0114
+#define ABE_DMIC_DIN3		0x0116
+#define UART2_CTS		0x0118
+#define UART2_RTS		0x011A
+#define UART2_RX		0x011C
+#define UART2_TX		0x011E
+#define HDQ_SIO			0x0120
+#define I2C1_SCL		0x0122
+#define I2C1_SDA		0x0124
+#define I2C2_SCL		0x0126
+#define I2C2_SDA		0x0128
+#define I2C3_SCL		0x012A
+#define I2C3_SDA		0x012C
+#define I2C4_SCL		0x012E
+#define I2C4_SDA		0x0130
+#define MCSPI1_CLK		0x0132
+#define MCSPI1_SOMI		0x0134
+#define MCSPI1_SIMO		0x0136
+#define MCSPI1_CS0		0x0138
+#define MCSPI1_CS1		0x013A
+#define MCSPI1_CS2		0x013C
+#define MCSPI1_CS3		0x013E
+#define UART3_CTS_RCTX		0x0140
+#define UART3_RTS_SD		0x0142
+#define UART3_RX_IRRX		0x0144
+#define UART3_TX_IRTX		0x0146
+#define SDMMC5_CLK		0x0148
+#define SDMMC5_CMD		0x014A
+#define SDMMC5_DAT0		0x014C
+#define SDMMC5_DAT1		0x014E
+#define SDMMC5_DAT2		0x0150
+#define SDMMC5_DAT3		0x0152
+#define MCSPI4_CLK		0x0154
+#define MCSPI4_SIMO		0x0156
+#define MCSPI4_SOMI		0x0158
+#define MCSPI4_CS0		0x015A
+#define UART4_RX		0x015C
+#define UART4_TX		0x015E
+#define USBB2_ULPITLL_CLK	0x0160
+#define USBB2_ULPITLL_STP	0x0162
+#define USBB2_ULPITLL_DIR	0x0164
+#define USBB2_ULPITLL_NXT	0x0166
+#define USBB2_ULPITLL_DAT0	0x0168
+#define USBB2_ULPITLL_DAT1	0x016A
+#define USBB2_ULPITLL_DAT2	0x016C
+#define USBB2_ULPITLL_DAT3	0x016E
+#define USBB2_ULPITLL_DAT4	0x0170
+#define USBB2_ULPITLL_DAT5	0x0172
+#define USBB2_ULPITLL_DAT6	0x0174
+#define USBB2_ULPITLL_DAT7	0x0176
+#define USBB2_HSIC_DATA		0x0178
+#define USBB2_HSIC_STROBE	0x017A
+#define UNIPRO_TX0		0x017C
+#define UNIPRO_TY0		0x017E
+#define UNIPRO_TX1		0x0180
+#define UNIPRO_TY1		0x0182
+#define UNIPRO_TX2		0x0184
+#define UNIPRO_TY2		0x0186
+#define UNIPRO_RX0		0x0188
+#define UNIPRO_RY0		0x018A
+#define UNIPRO_RX1		0x018C
+#define UNIPRO_RY1		0x018E
+#define UNIPRO_RX2		0x0190
+#define UNIPRO_RY2		0x0192
+#define USBA0_OTG_CE		0x0194
+#define USBA0_OTG_DP		0x0196
+#define USBA0_OTG_DM		0x0198
+#define FREF_CLK1_OUT		0x019A
+#define FREF_CLK2_OUT		0x019C
+#define SYS_NIRQ1		0x019E
+#define SYS_NIRQ2		0x01A0
+#define SYS_BOOT0		0x01A2
+#define SYS_BOOT1		0x01A4
+#define SYS_BOOT2		0x01A6
+#define SYS_BOOT3		0x01A8
+#define SYS_BOOT4		0x01AA
+#define SYS_BOOT5		0x01AC
+#define DPM_EMU0		0x01AE
+#define DPM_EMU1		0x01B0
+#define DPM_EMU2		0x01B2
+#define DPM_EMU3		0x01B4
+#define DPM_EMU4		0x01B6
+#define DPM_EMU5		0x01B8
+#define DPM_EMU6		0x01BA
+#define DPM_EMU7		0x01BC
+#define DPM_EMU8		0x01BE
+#define DPM_EMU9		0x01C0
+#define DPM_EMU10		0x01C2
+#define DPM_EMU11		0x01C4
+#define DPM_EMU12		0x01C6
+#define DPM_EMU13		0x01C8
+#define DPM_EMU14		0x01CA
+#define DPM_EMU15		0x01CC
+#define DPM_EMU16		0x01CE
+#define DPM_EMU17		0x01D0
+#define DPM_EMU18		0x01D2
+#define DPM_EMU19		0x01D4
+#define WAKEUPEVENT_0		0x01D8
+#define WAKEUPEVENT_1		0x01DC
+#define WAKEUPEVENT_2		0x01E0
+#define WAKEUPEVENT_3		0x01E4
+#define WAKEUPEVENT_4		0x01E8
+#define WAKEUPEVENT_5		0x01EC
+#define WAKEUPEVENT_6		0x01F0
+
+#define WKUP_REVISION		0x0000
+#define WKUP_HWINFO		0x0004
+#define WKUP_SYSCONFIG		0x0010
+#define PAD0_SIM_IO		0x0040
+#define PAD1_SIM_CLK		0x0042
+#define PAD0_SIM_RESET		0x0044
+#define PAD1_SIM_CD		0x0046
+#define PAD0_SIM_PWRCTRL		0x0048
+#define PAD1_SR_SCL		0x004A
+#define PAD0_SR_SDA		0x004C
+#define PAD1_FREF_XTAL_IN		0x004E
+#define PAD0_FREF_SLICER_IN	0x0050
+#define PAD1_FREF_CLK_IOREQ	0x0052
+#define PAD0_FREF_CLK0_OUT		0x0054
+#define PAD1_FREF_CLK3_REQ		0x0056
+#define PAD0_FREF_CLK3_OUT		0x0058
+#define PAD1_FREF_CLK4_REQ		0x005A
+#define PAD0_FREF_CLK4_OUT		0x005C
+#define PAD1_SYS_32K		0x005E
+#define PAD0_SYS_NRESPWRON		0x0060
+#define PAD1_SYS_NRESWARM		0x0062
+#define PAD0_SYS_PWR_REQ		0x0064
+#define PAD1_SYS_PWRON_RESET	0x0066
+#define PAD0_SYS_BOOT6		0x0068
+#define PAD1_SYS_BOOT7		0x006A
+#define PAD0_JTAG_NTRST		0x006C
+#define PAD1_JTAG_TCK		0x006D
+#define PAD0_JTAG_RTCK		0x0070
+#define PAD1_JTAG_TMS_TMSC		0x0072
+#define PAD0_JTAG_TDI		0x0074
+#define PAD1_JTAG_TDO		0x0076
+#define PADCONF_WAKEUPEVENT_0	0x007C
+#define CONTROL_SMART1NOPMIO_PADCONF_0		0x05A0
+#define CONTROL_SMART1NOPMIO_PADCONF_1		0x05A4
+#define PADCONF_MODE		0x05A8
+#define CONTROL_XTAL_OSCILLATOR			0x05AC
+#define CONTROL_CONTROL_I2C_2			0x0604
+#define CONTROL_CONTROL_JTAG			0x0608
+#define CONTROL_CONTROL_SYS			0x060C
+#define CONTROL_SPARE_RW		0x0614
+#define CONTROL_SPARE_R		0x0618
+#define CONTROL_SPARE_R_C0		0x061C
+
+#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ	0x4A31E05A
+#endif /* _MUX_OMAP4_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/omap.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/omap.h
new file mode 100644
index 000000000..f66da0d60
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/omap.h
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * Derived from OMAP3 work by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _OMAP4_H_
+#define _OMAP4_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP44XX_L4_CORE_BASE	0x4A000000
+#define OMAP44XX_L4_WKUP_BASE	0x4A300000
+#define OMAP44XX_L4_PER_BASE	0x48000000
+
+#define OMAP44XX_DRAM_ADDR_SPACE_START	0x80000000
+#define OMAP44XX_DRAM_ADDR_SPACE_END	0xD0000000
+#define DRAM_ADDR_SPACE_START	OMAP44XX_DRAM_ADDR_SPACE_START
+#define DRAM_ADDR_SPACE_END	OMAP44XX_DRAM_ADDR_SPACE_END
+
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE		0x4A002204
+#define STD_FUSE_DIE_ID_0	0x4A002200
+#define STD_FUSE_DIE_ID_1	0x4A002208
+#define STD_FUSE_DIE_ID_2	0x4A00220c
+#define STD_FUSE_DIE_ID_3	0x4A002210
+
+#define OMAP4_CONTROL_ID_CODE_ES1_0	0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0	0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3	0x6B95C02F
+#define OMAP4460_CONTROL_ID_CODE_ES1_0	0x0B94E02F
+#define OMAP4460_CONTROL_ID_CODE_ES1_1	0x2B94E02F
+#define OMAP4470_CONTROL_ID_CODE_ES1_0	0x0B97502F
+
+/* UART */
+#define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE		(OMAP44XX_L4_PER_BASE + 0x20000)
+
+/* General Purpose Timers */
+#define GPT1_BASE		(OMAP44XX_L4_WKUP_BASE + 0x18000)
+#define GPT2_BASE		(OMAP44XX_L4_PER_BASE  + 0x32000)
+#define GPT3_BASE		(OMAP44XX_L4_PER_BASE  + 0x34000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define WDT2_BASE		(OMAP44XX_L4_WKUP_BASE + 0x14000)
+
+/* GPMC */
+#define OMAP44XX_GPMC_BASE	0x50000000
+
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+/* GP Timer */
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* Control Module */
+#define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
+#define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
+#define CONTROL_EFUSE_1_OVERRIDE	0x1C4D0110
+#define CONTROL_EFUSE_2_OVERRIDE	0x99084000
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN	0x7C7C7C7C
+#define LPDDR2IO_GR10_WD_MASK				(3 << 17)
+#define CONTROL_LPDDR2IO_3_VAL		0xA0888C0F
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
+#define MMC1_PWRDNZ					(1 << 26)
+#define MMC1_PBIASLITE_PWRDNZ				(1 << 22)
+#define MMC1_PBIASLITE_VMODE				(1 << 21)
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+	unsigned char res[0x10];
+	unsigned int s32k_cr;	/* 0x10 */
+};
+
+#define DEVICE_TYPE_SHIFT (0x8)
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+#define DEVICE_GP 0x3
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Non-secure SRAM Addresses
+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ * at 0x40304000(EMU base) so that our code works for both EMU and GP
+ */
+#define NON_SECURE_SRAM_START	0x40304000
+#define NON_SECURE_SRAM_END	0x4030E000	/* Not inclusive */
+#define SRAM_SCRATCH_SPACE_ADDR	0x4030C000
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE	0x4030D000
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME		50
+#define OMAP_ABB_CLOCK_CYCLES		16
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK	(0x1 << 7)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/spl.h
new file mode 100644
index 000000000..fb842a226
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/spl.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONENAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+#define BOOT_DEVICE_MMC2_2	0xFF
+
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/sys_proto.h
new file mode 100644
index 000000000..80172f379
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/omap_common.h>
+#include <linux/mtd/omap_gpmc.h>
+#include <asm/arch/mux_omap4.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
+extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
+extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
+extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
+struct omap_sysinfo {
+	char *board_string;
+};
+extern const struct omap_sysinfo sysinfo;
+
+void gpmc_init(void);
+void watchdog_init(void);
+u32 get_device_type(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_essential(void);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void set_pl310_ctrl_reg(u32 val);
+void setup_clocks_for_console(void);
+void prcm_init(void);
+void bypass_dpll(u32 const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap4_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
+void sdram_init(void);
+u32 omap_sdram_size(void);
+u32 cortex_rev(void);
+void save_omap_boot_params(void);
+void init_omap_revision(void);
+void do_io_settings(void);
+void sri2c_init(void);
+void gpi2c_init(void);
+int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
+u32 warm_reset(void);
+void force_emif_self_refresh(void);
+void setup_warmreset_time(void);
+
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
+	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+	/*
+	 * u-boot can be running from sdram either because of configuration
+	 * Header or by SPL. If because of CH, then the romcode sets the
+	 * CHSETTINGS executed bit to true in the boot parameter structure that
+	 * it passes to the bootloader.This parameter is stored in the ch_flags
+	 * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
+	 * mandatory section if CH is present.
+	 */
+	if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+		return 0;
+	else
+		return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap_hw_init_context(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	return OMAP_INIT_CONTEXT_SPL;
+#else
+	if (uboot_loaded_by_spl())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
+	else if (running_from_sdram())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
+	else
+		return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
+#endif
+}
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/clock.h
new file mode 100644
index 000000000..2dfe4efb4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/clock.h
@@ -0,0 +1,337 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ *	Aneesh V <aneesh@ti.com>
+ *	Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _CLOCKS_OMAP5_H_
+#define _CLOCKS_OMAP5_H_
+#include <common.h>
+#include <asm/omap_common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY		1000000
+
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_OVERRIDE_SHIFT		0
+#define CM_DLL_CTRL_OVERRIDE_MASK		(1 << 0)
+#define CM_DLL_CTRL_NO_OVERRIDE			0
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_FAST_RELOCK_BYPASS	6
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* SGX */
+#define CLKSEL_GPU_HYD_GCLK_MASK		(1 << 25)
+#define CLKSEL_GPU_CORE_GCLK_MASK		(1 << 24)
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT			22
+#define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT	0
+#define CLKSEL_L3_SHIFT		4
+#define CLKSEL_L4_SHIFT		8
+
+#define CLKSEL_CORE_X2_DIV_1	0
+#define CLKSEL_L3_CORE_DIV_2	1
+#define CLKSEL_L4_L3_DIV_2	1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
+
+/* CM_CLKSEL_ABE_PLL_SYS */
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT	0
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK	1
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1		0
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2		1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(1 << 25)
+
+/* CM_L3INIT_SATA_CLKCTRL */
+#define SATA_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
+
+/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OPTFCLKEN_FUNC48M_CLK			(1 << 15)
+#define OPTFCLKEN_HSIC480M_P2_CLK		(1 << 14)
+#define OPTFCLKEN_HSIC480M_P1_CLK		(1 << 13)
+#define OPTFCLKEN_HSIC60M_P2_CLK		(1 << 12)
+#define OPTFCLKEN_HSIC60M_P1_CLK		(1 << 11)
+#define OPTFCLKEN_UTMI_P3_CLK			(1 << 10)
+#define OPTFCLKEN_UTMI_P2_CLK			(1 << 9)
+#define OPTFCLKEN_UTMI_P1_CLK			(1 << 8)
+#define OPTFCLKEN_HSIC480M_P3_CLK		(1 << 7)
+#define OPTFCLKEN_HSIC60M_P3_CLK		(1 << 6)
+
+/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OPTFCLKEN_USB_CH0_CLK_ENABLE	(1 << 8)
+#define OPTFCLKEN_USB_CH1_CLK_ENABLE	(1 << 9)
+#define OPTFCLKEN_USB_CH2_CLK_ENABLE	(1 << 10)
+
+/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)
+
+/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
+#define OTG_SS_CLKCTRL_MODULEMODE_HW	(1 << 0)
+#define OPTFCLKEN_REFCLK960M			(1 << 8)
+
+/* CM_L3INIT_OCP2SCP1_CLKCTRL */
+#define OCP2SCP1_CLKCTRL_MODULEMODE_HW	(1 << 0)
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(3 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	26
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 26)
+
+/* CM_WKUPAON_SCRM_CLKCTRL */
+#define OPTFCLKEN_SCRM_PER_SHIFT		9
+#define OPTFCLKEN_SCRM_PER_MASK			(1 << 9)
+#define OPTFCLKEN_SCRM_CORE_SHIFT		8
+#define OPTFCLKEN_SCRM_CORE_MASK		(1 << 8)
+
+/* CM_COREAON_IO_SRCOMP_CLKCTRL */
+#define OPTFCLKEN_SRCOMP_FCLK_SHIFT		8
+#define OPTFCLKEN_SRCOMP_FCLK_MASK		(1 << 8)
+
+/* PRM_RSTTIME */
+#define RSTTIME1_SHIFT				0
+#define RSTTIME1_MASK				(0x3ff << 0)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_IND_38_4_MHZ	6
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
+
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET	(1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
+/* SMPS */
+#define SMPS_I2C_SLAVE_ADDR	0x12
+#define SMPS_REG_ADDR_12_MPU	0x23
+#define SMPS_REG_ADDR_45_IVA	0x2B
+#define SMPS_REG_ADDR_8_CORE	0x37
+
+/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
+/* ES1.0 settings */
+#define VDD_MPU		1040
+#define VDD_MM		1040
+#define VDD_CORE	1040
+
+#define VDD_MPU_LOW	890
+#define VDD_MM_LOW	890
+#define VDD_CORE_LOW	890
+
+/* ES2.0 settings */
+#define VDD_MPU_ES2	1060
+#define VDD_MM_ES2	1025
+#define VDD_CORE_ES2	1040
+
+#define VDD_MPU_ES2_HIGH 1250
+#define VDD_MM_ES2_OD  1120
+
+#define VDD_MPU_ES2_LOW 880
+#define VDD_MM_ES2_LOW 880
+
+/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
+#define VDD_MPU_DRA752		1090
+#define VDD_EVE_DRA752		1060
+#define VDD_GPU_DRA752		1060
+#define VDD_CORE_DRA752		1030
+#define VDD_IVA_DRA752		1060
+
+/* Efuse register offsets for DRA7xx platform */
+#define DRA752_EFUSE_BASE	0x4A002000
+#define DRA752_EFUSE_REGBITS	16
+/* STD_FUSE_OPP_VMIN_IVA_2 */
+#define STD_FUSE_OPP_VMIN_IVA_NOM	(DRA752_EFUSE_BASE + 0x05CC)
+/* STD_FUSE_OPP_VMIN_IVA_3 */
+#define STD_FUSE_OPP_VMIN_IVA_OD	(DRA752_EFUSE_BASE + 0x05D0)
+/* STD_FUSE_OPP_VMIN_IVA_4 */
+#define STD_FUSE_OPP_VMIN_IVA_HIGH	(DRA752_EFUSE_BASE + 0x05D4)
+/* STD_FUSE_OPP_VMIN_DSPEVE_2 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_NOM	(DRA752_EFUSE_BASE + 0x05E0)
+/* STD_FUSE_OPP_VMIN_DSPEVE_3 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_OD	(DRA752_EFUSE_BASE + 0x05E4)
+/* STD_FUSE_OPP_VMIN_DSPEVE_4 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH	(DRA752_EFUSE_BASE + 0x05E8)
+/* STD_FUSE_OPP_VMIN_CORE_2 */
+#define STD_FUSE_OPP_VMIN_CORE_NOM	(DRA752_EFUSE_BASE + 0x05F4)
+/* STD_FUSE_OPP_VMIN_GPU_2 */
+#define STD_FUSE_OPP_VMIN_GPU_NOM	(DRA752_EFUSE_BASE + 0x1B08)
+/* STD_FUSE_OPP_VMIN_GPU_3 */
+#define STD_FUSE_OPP_VMIN_GPU_OD	(DRA752_EFUSE_BASE + 0x1B0C)
+/* STD_FUSE_OPP_VMIN_GPU_4 */
+#define STD_FUSE_OPP_VMIN_GPU_HIGH	(DRA752_EFUSE_BASE + 0x1B10)
+/* STD_FUSE_OPP_VMIN_MPU_2 */
+#define STD_FUSE_OPP_VMIN_MPU_NOM	(DRA752_EFUSE_BASE + 0x1B20)
+/* STD_FUSE_OPP_VMIN_MPU_3 */
+#define STD_FUSE_OPP_VMIN_MPU_OD	(DRA752_EFUSE_BASE + 0x1B24)
+/* STD_FUSE_OPP_VMIN_MPU_4 */
+#define STD_FUSE_OPP_VMIN_MPU_HIGH	(DRA752_EFUSE_BASE + 0x1B28)
+
+/* Standard offset is 0.5v expressed in uv */
+#define PALMAS_SMPS_BASE_VOLT_UV 500000
+
+/* TPS659038 */
+#define TPS659038_I2C_SLAVE_ADDR		0x58
+#define TPS659038_REG_ADDR_SMPS12_MPU		0x23
+#define TPS659038_REG_ADDR_SMPS45_EVE		0x2B
+#define TPS659038_REG_ADDR_SMPS6_GPU		0x2F
+#define TPS659038_REG_ADDR_SMPS7_CORE		0x33
+#define TPS659038_REG_ADDR_SMPS8_IVA		0x37
+
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR		0x60
+#define TPS62361_REG_ADDR_SET0		0x0
+#define TPS62361_REG_ADDR_SET1		0x1
+#define TPS62361_REG_ADDR_SET2		0x2
+#define TPS62361_REG_ADDR_SET3		0x3
+#define TPS62361_REG_ADDR_CTRL		0x4
+#define TPS62361_REG_ADDR_TEMP		0x5
+#define TPS62361_REG_ADDR_RMP_CTRL	0x6
+#define TPS62361_REG_ADDR_CHIP_ID	0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2	0x9
+
+#define TPS62361_BASE_VOLT_MV	500
+#define TPS62361_VSEL0_GPIO	7
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
+
+#define DPLL_NO_LOCK	0
+#define DPLL_LOCK	1
+
+/*
+ * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
+ * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
+ * into microsec and passing the value.
+ */
+#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC	31219
+
+#ifdef CONFIG_DRA7XX
+#define V_OSCK			20000000	/* Clock output from T2 */
+#else
+#define V_OSCK			19200000	/* Clock output from T2 */
+#endif
+
+#define V_SCLK	V_OSCK
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK		(1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT		1
+#define AUXCLK_SRCSELECT_MASK		(3 << 1)
+#define AUXCLK_CLKDIV_SHIFT		16
+#define AUXCLK_CLKDIV_MASK		(0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK	0
+#define AUXCLK_SRCSELECT_CORE_DPLL	1
+#define AUXCLK_SRCSELECT_PER_DPLL	2
+#define AUXCLK_SRCSELECT_ALTERNATE	3
+
+#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/cpu.h
new file mode 100644
index 000000000..5f1d7454d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/cpu.h
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2006-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gptimer {
+	u32 tidr;		/* 0x00 r */
+	u8 res1[0xc];
+	u32 tiocp_cfg;		/* 0x10 rw */
+	u8 res2[0x10];
+	u32 tisr_raw;		/* 0x24 r */
+	u32 tisr;		/* 0x28 rw */
+	u32 tier;		/* 0x2c rw */
+	u32 ticr;		/* 0x30 rw */
+	u32 twer;		/* 0x34 rw */
+	u32 tclr;		/* 0x38 rw */
+	u32 tcrr;		/* 0x3c rw */
+	u32 tldr;		/* 0x40 rw */
+	u32 ttgr;		/* 0x44 rw */
+	u32 twpc;		/* 0x48 r */
+	u32 tmar;		/* 0x4c rw */
+	u32 tcar1;		/* 0x50 r */
+	u32 tcicr;		/* 0x54 rw */
+	u32 tcar2;		/* 0x58 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+	u8 res1[0x34];
+	u32 wwps;		/* 0x34 r */
+	u8 res2[0x10];
+	u32 wspr;		/* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define BIT(x)				(1 << (x))
+
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* GPMC BASE */
+#define GPMC_BASE		(OMAP54XX_GPMC_BASE)
+
+/* I2C base */
+#define I2C_BASE1		(OMAP54XX_L4_PER_BASE + 0x70000)
+#define I2C_BASE2		(OMAP54XX_L4_PER_BASE + 0x72000)
+#define I2C_BASE3		(OMAP54XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4		(OMAP54XX_L4_PER_BASE + 0x7A000)
+#define I2C_BASE5		(OMAP54XX_L4_PER_BASE + 0x7C000)
+
+/* MUSB base */
+#define MUSB_BASE		(OMAP54XX_L4_CORE_BASE + 0xAB000)
+
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x0118
+#define OMAP_GPIO_IRQSTATUS2		0x0128
+#define OMAP_GPIO_IRQENABLE2		0x012c
+#define OMAP_GPIO_IRQENABLE1		0x011c
+#define OMAP_GPIO_WAKE_EN		0x0120
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0160
+#define OMAP_GPIO_SETIRQENABLE1		0x0164
+#define OMAP_GPIO_CLEARWKUENA		0x0180
+#define OMAP_GPIO_SETWKUENA		0x0184
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE		0x4AE06000
+#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL		PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET	0x01
+#define PRM_RSTST		(PRM_DEVICE_BASE + 0x4)
+#define PRM_RSTST_WARM_RESET_MASK	0x7FEA
+
+/* DRA7XX CPSW Config space */
+#define CPSW_BASE			0x48484000
+#define CPSW_MDIO_BASE			0x48485000
+
+#endif /* _CPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h
new file mode 100644
index 000000000..63aaa020d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/ehci.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com*
+ * Author: Govindraj R <govindraj.raja@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EHCI_H
+#define _EHCI_H
+
+#define OMAP_EHCI_BASE				(OMAP54XX_L4_CORE_BASE + 0x64C00)
+#define OMAP_UHH_BASE				(OMAP54XX_L4_CORE_BASE + 0x64000)
+#define OMAP_USBTLL_BASE			(OMAP54XX_L4_CORE_BASE + 0x62000)
+
+/* TLL Register Set */
+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE		(1 << 3)
+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP		(1 << 2)
+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET		(1 << 1)
+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY		(1 << 8)
+#define OMAP_USBTLL_SYSSTATUS_RESETDONE		1
+
+#define OMAP_UHH_SYSCONFIG_SOFTRESET		1
+#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE	(1 << 2)
+#define OMAP_UHH_SYSCONFIG_NOIDLE		(1 << 2)
+#define OMAP_UHH_SYSCONFIG_NOSTDBY		(1 << 4)
+
+#define OMAP_UHH_SYSCONFIG_VAL	(OMAP_UHH_SYSCONFIG_NOIDLE | \
+					OMAP_UHH_SYSCONFIG_NOSTDBY)
+
+#endif /* _EHCI_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h
new file mode 100644
index 000000000..9dd03c9fa
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/gpio.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+#ifndef _GPIO_OMAP5_H
+#define _GPIO_OMAP5_H
+
+#include <asm/omap_gpio.h>
+
+#define OMAP_MAX_GPIO			256
+
+#define OMAP54XX_GPIO1_BASE		0x4Ae10000
+#define OMAP54XX_GPIO2_BASE		0x48055000
+#define OMAP54XX_GPIO3_BASE		0x48057000
+#define OMAP54XX_GPIO4_BASE		0x48059000
+#define OMAP54XX_GPIO5_BASE		0x4805B000
+#define OMAP54XX_GPIO6_BASE		0x4805D000
+#define OMAP54XX_GPIO7_BASE		0x48051000
+#define OMAP54XX_GPIO8_BASE		0x48053000
+
+#endif /* _GPIO_OMAP5_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h
new file mode 100644
index 000000000..d875cfe0b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/i2c.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _OMAP5_I2C_H_
+#define _OMAP5_I2C_H_
+
+#define I2C_BUS_MAX	5
+#define I2C_DEFAULT_BASE	I2C_BASE1
+
+struct i2c {
+	unsigned short revnb_lo;	/* 0x00 */
+	unsigned short res1;
+	unsigned short revnb_hi;	/* 0x04 */
+	unsigned short res2[13];
+	unsigned short sysc;		/* 0x20 */
+	unsigned short res3;
+	unsigned short irqstatus_raw;	/* 0x24 */
+	unsigned short res4;
+	unsigned short stat;		/* 0x28 */
+	unsigned short res5;
+	unsigned short ie;		/* 0x2C */
+	unsigned short res6;
+	unsigned short irqenable_clr;	/* 0x30 */
+	unsigned short res7;
+	unsigned short iv;		/* 0x34 */
+	unsigned short res8[45];
+	unsigned short syss;		/* 0x90 */
+	unsigned short res9;
+	unsigned short buf;		/* 0x94 */
+	unsigned short res10;
+	unsigned short cnt;		/* 0x98 */
+	unsigned short res11;
+	unsigned short data;		/* 0x9C */
+	unsigned short res13;
+	unsigned short res14;		/* 0xA0 */
+	unsigned short res15;
+	unsigned short con;		/* 0xA4 */
+	unsigned short res16;
+	unsigned short oa;		/* 0xA8 */
+	unsigned short res17;
+	unsigned short sa;		/* 0xAC */
+	unsigned short res18;
+	unsigned short psc;		/* 0xB0 */
+	unsigned short res19;
+	unsigned short scll;		/* 0xB4 */
+	unsigned short res20;
+	unsigned short sclh;		/* 0xB8 */
+	unsigned short res21;
+	unsigned short systest;		/* 0xBC */
+	unsigned short res22;
+	unsigned short bufstat;		/* 0xC0 */
+	unsigned short res23;
+};
+
+#endif /* _OMAP5_I2C_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mmc_host_def.h
new file mode 100644
index 000000000..9c8ccb6c8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+#include <asm/omap_mmc.h>
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE	0x4809C100
+#define OMAP_HSMMC2_BASE	0x480B4100
+#define OMAP_HSMMC3_BASE	0x480AD100
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
new file mode 100644
index 000000000..e1553879d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
@@ -0,0 +1,331 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated
+ *
+ * Nishant Kamat <nskamat@ti.com>
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _MUX_DRA7XX_H_
+#define _MUX_DRA7XX_H_
+
+#include <asm/types.h>
+
+#define FSC	(1 << 19)
+#define SSC	(0 << 19)
+
+#define IEN	(1 << 18)
+#define IDIS	(0 << 18)
+
+#define PTU	(1 << 17)
+#define PTD	(0 << 17)
+#define PEN	(1 << 16)
+#define PDIS	(0 << 16)
+
+#define WKEN	(1 << 24)
+#define WKDIS	(0 << 24)
+
+#define M0	0
+#define M1	1
+#define M2	2
+#define M3	3
+#define M4	4
+#define M5	5
+#define M6	6
+#define M7	7
+#define M8	8
+#define M9	9
+#define M10	10
+#define M11	11
+#define M12	12
+#define M13	13
+#define M14	14
+#define M15	15
+
+#define SAFE_MODE	M15
+
+#define GPMC_AD0	0x000
+#define GPMC_AD1	0x004
+#define GPMC_AD2	0x008
+#define GPMC_AD3	0x00C
+#define GPMC_AD4	0x010
+#define GPMC_AD5	0x014
+#define GPMC_AD6	0x018
+#define GPMC_AD7	0x01C
+#define GPMC_AD8	0x020
+#define GPMC_AD9	0x024
+#define GPMC_AD10	0x028
+#define GPMC_AD11	0x02C
+#define GPMC_AD12	0x030
+#define GPMC_AD13	0x034
+#define GPMC_AD14	0x038
+#define GPMC_AD15	0x03C
+#define GPMC_A0		0x040
+#define GPMC_A1		0x044
+#define GPMC_A2		0x048
+#define GPMC_A3		0x04C
+#define GPMC_A4		0x050
+#define GPMC_A5		0x054
+#define GPMC_A6		0x058
+#define GPMC_A7		0x05C
+#define GPMC_A8		0x060
+#define GPMC_A9		0x064
+#define GPMC_A10	0x068
+#define GPMC_A11	0x06C
+#define GPMC_A12	0x070
+#define GPMC_A13	0x074
+#define GPMC_A14	0x078
+#define GPMC_A15	0x07C
+#define GPMC_A16	0x080
+#define GPMC_A17	0x084
+#define GPMC_A18	0x088
+#define GPMC_A19	0x08C
+#define GPMC_A20	0x090
+#define GPMC_A21	0x094
+#define GPMC_A22	0x098
+#define GPMC_A23	0x09C
+#define GPMC_A24	0x0A0
+#define GPMC_A25	0x0A4
+#define GPMC_A26	0x0A8
+#define GPMC_A27	0x0AC
+#define GPMC_CS1	0x0B0
+#define GPMC_CS0	0x0B4
+#define GPMC_CS2	0x0B8
+#define GPMC_CS3	0x0BC
+#define GPMC_CLK	0x0C0
+#define GPMC_ADVN_ALE	0x0C4
+#define GPMC_OEN_REN	0x0C8
+#define GPMC_WEN	0x0CC
+#define GPMC_BEN0	0x0D0
+#define GPMC_BEN1	0x0D4
+#define GPMC_WAIT0	0x0D8
+#define VIN1A_CLK0	0x0DC
+#define VIN1B_CLK1	0x0E0
+#define VIN1A_DE0	0x0E4
+#define VIN1A_FLD0	0x0E8
+#define VIN1A_HSYNC0	0x0EC
+#define VIN1A_VSYNC0	0x0F0
+#define VIN1A_D0	0x0F4
+#define VIN1A_D1	0x0F8
+#define VIN1A_D2	0x0FC
+#define VIN1A_D3	0x100
+#define VIN1A_D4	0x104
+#define VIN1A_D5	0x108
+#define VIN1A_D6	0x10C
+#define VIN1A_D7	0x110
+#define VIN1A_D8	0x114
+#define VIN1A_D9	0x118
+#define VIN1A_D10	0x11C
+#define VIN1A_D11	0x120
+#define VIN1A_D12	0x124
+#define VIN1A_D13	0x128
+#define VIN1A_D14	0x12C
+#define VIN1A_D15	0x130
+#define VIN1A_D16	0x134
+#define VIN1A_D17	0x138
+#define VIN1A_D18	0x13C
+#define VIN1A_D19	0x140
+#define VIN1A_D20	0x144
+#define VIN1A_D21	0x148
+#define VIN1A_D22	0x14C
+#define VIN1A_D23	0x150
+#define VIN2A_CLK0	0x154
+#define VIN2A_DE0	0x158
+#define VIN2A_FLD0	0x15C
+#define VIN2A_HSYNC0	0x160
+#define VIN2A_VSYNC0	0x164
+#define VIN2A_D0	0x168
+#define VIN2A_D1	0x16C
+#define VIN2A_D2	0x170
+#define VIN2A_D3	0x174
+#define VIN2A_D4	0x178
+#define VIN2A_D5	0x17C
+#define VIN2A_D6	0x180
+#define VIN2A_D7	0x184
+#define VIN2A_D8	0x188
+#define VIN2A_D9	0x18C
+#define VIN2A_D10	0x190
+#define VIN2A_D11	0x194
+#define VIN2A_D12	0x198
+#define VIN2A_D13	0x19C
+#define VIN2A_D14	0x1A0
+#define VIN2A_D15	0x1A4
+#define VIN2A_D16	0x1A8
+#define VIN2A_D17	0x1AC
+#define VIN2A_D18	0x1B0
+#define VIN2A_D19	0x1B4
+#define VIN2A_D20	0x1B8
+#define VIN2A_D21	0x1BC
+#define VIN2A_D22	0x1C0
+#define VIN2A_D23	0x1C4
+#define VOUT1_CLK	0x1C8
+#define VOUT1_DE	0x1CC
+#define VOUT1_FLD	0x1D0
+#define VOUT1_HSYNC	0x1D4
+#define VOUT1_VSYNC	0x1D8
+#define VOUT1_D0	0x1DC
+#define VOUT1_D1	0x1E0
+#define VOUT1_D2	0x1E4
+#define VOUT1_D3	0x1E8
+#define VOUT1_D4	0x1EC
+#define VOUT1_D5	0x1F0
+#define VOUT1_D6	0x1F4
+#define VOUT1_D7	0x1F8
+#define VOUT1_D8	0x1FC
+#define VOUT1_D9	0x200
+#define VOUT1_D10	0x204
+#define VOUT1_D11	0x208
+#define VOUT1_D12	0x20C
+#define VOUT1_D13	0x210
+#define VOUT1_D14	0x214
+#define VOUT1_D15	0x218
+#define VOUT1_D16	0x21C
+#define VOUT1_D17	0x220
+#define VOUT1_D18	0x224
+#define VOUT1_D19	0x228
+#define VOUT1_D20	0x22C
+#define VOUT1_D21	0x230
+#define VOUT1_D22	0x234
+#define VOUT1_D23	0x238
+#define MDIO_MCLK	0x23C
+#define MDIO_D		0x240
+#define RMII_MHZ_50_CLK	0x244
+#define UART3_RXD	0x248
+#define UART3_TXD	0x24C
+#define RGMII0_TXC	0x250
+#define RGMII0_TXCTL	0x254
+#define RGMII0_TXD3	0x258
+#define RGMII0_TXD2	0x25C
+#define RGMII0_TXD1	0x260
+#define RGMII0_TXD0	0x264
+#define RGMII0_RXC	0x268
+#define RGMII0_RXCTL	0x26C
+#define RGMII0_RXD3	0x270
+#define RGMII0_RXD2	0x274
+#define RGMII0_RXD1	0x278
+#define RGMII0_RXD0	0x27C
+#define USB1_DRVVBUS	0x280
+#define USB2_DRVVBUS	0x284
+#define GPIO6_14	0x288
+#define GPIO6_15	0x28C
+#define GPIO6_16	0x290
+#define XREF_CLK0	0x294
+#define XREF_CLK1	0x298
+#define XREF_CLK2	0x29C
+#define XREF_CLK3	0x2A0
+#define MCASP1_ACLKX	0x2A4
+#define MCASP1_FSX	0x2A8
+#define MCASP1_ACLKR	0x2AC
+#define MCASP1_FSR	0x2B0
+#define MCASP1_AXR0	0x2B4
+#define MCASP1_AXR1	0x2B8
+#define MCASP1_AXR2	0x2BC
+#define MCASP1_AXR3	0x2C0
+#define MCASP1_AXR4	0x2C4
+#define MCASP1_AXR5	0x2C8
+#define MCASP1_AXR6	0x2CC
+#define MCASP1_AXR7	0x2D0
+#define MCASP1_AXR8	0x2D4
+#define MCASP1_AXR9	0x2D8
+#define MCASP1_AXR10	0x2DC
+#define MCASP1_AXR11	0x2E0
+#define MCASP1_AXR12	0x2E4
+#define MCASP1_AXR13	0x2E8
+#define MCASP1_AXR14	0x2EC
+#define MCASP1_AXR15	0x2F0
+#define MCASP2_ACLKX	0x2F4
+#define MCASP2_FSX	0x2F8
+#define MCASP2_ACLKR	0x2FC
+#define MCASP2_FSR	0x300
+#define MCASP2_AXR0	0x304
+#define MCASP2_AXR1	0x308
+#define MCASP2_AXR2	0x30C
+#define MCASP2_AXR3	0x310
+#define MCASP2_AXR4	0x314
+#define MCASP2_AXR5	0x318
+#define MCASP2_AXR6	0x31C
+#define MCASP2_AXR7	0x320
+#define MCASP3_ACLKX	0x324
+#define MCASP3_FSX	0x328
+#define MCASP3_AXR0	0x32C
+#define MCASP3_AXR1	0x330
+#define MCASP4_ACLKX	0x334
+#define MCASP4_FSX	0x338
+#define MCASP4_AXR0	0x33C
+#define MCASP4_AXR1	0x340
+#define MCASP5_ACLKX	0x344
+#define MCASP5_FSX	0x348
+#define MCASP5_AXR0	0x34C
+#define MCASP5_AXR1	0x350
+#define MMC1_CLK	0x354
+#define MMC1_CMD	0x358
+#define MMC1_DAT0	0x35C
+#define MMC1_DAT1	0x360
+#define MMC1_DAT2	0x364
+#define MMC1_DAT3	0x368
+#define MMC1_SDCD	0x36C
+#define MMC1_SDWP	0x370
+#define GPIO6_10	0x374
+#define GPIO6_11	0x378
+#define MMC3_CLK	0x37C
+#define MMC3_CMD	0x380
+#define MMC3_DAT0	0x384
+#define MMC3_DAT1	0x388
+#define MMC3_DAT2	0x38C
+#define MMC3_DAT3	0x390
+#define MMC3_DAT4	0x394
+#define MMC3_DAT5	0x398
+#define MMC3_DAT6	0x39C
+#define MMC3_DAT7	0x3A0
+#define SPI1_SCLK	0x3A4
+#define SPI1_D1		0x3A8
+#define SPI1_D0		0x3AC
+#define SPI1_CS0	0x3B0
+#define SPI1_CS1	0x3B4
+#define SPI1_CS2	0x3B8
+#define SPI1_CS3	0x3BC
+#define SPI2_SCLK	0x3C0
+#define SPI2_D1		0x3C4
+#define SPI2_D0		0x3C8
+#define SPI2_CS0	0x3CC
+#define DCAN1_TX	0x3D0
+#define DCAN1_RX	0x3D4
+#define DCAN2_TX	0x3D8
+#define DCAN2_RX	0x3DC
+#define UART1_RXD	0x3E0
+#define UART1_TXD	0x3E4
+#define UART1_CTSN	0x3E8
+#define UART1_RTSN	0x3EC
+#define UART2_RXD	0x3F0
+#define UART2_TXD	0x3F4
+#define UART2_CTSN	0x3F8
+#define UART2_RTSN	0x3FC
+#define I2C1_SDA	0x400
+#define I2C1_SCL	0x404
+#define I2C2_SDA	0x408
+#define I2C2_SCL	0x40C
+#define I2C3_SDA	0x410
+#define I2C3_SCL	0x414
+#define WAKEUP0		0x418
+#define WAKEUP1		0x41C
+#define WAKEUP2		0x420
+#define WAKEUP3		0x424
+#define ON_OFF		0x428
+#define RTC_PORZ	0x42C
+#define TMS		0x430
+#define TDI		0x434
+#define TDO		0x438
+#define TCLK		0x43C
+#define TRSTN		0x440
+#define RTCK		0x444
+#define EMU0		0x448
+#define EMU1		0x44C
+#define EMU2		0x450
+#define EMU3		0x454
+#define EMU4		0x458
+#define RESETN		0x45C
+#define NMIN		0x460
+#define RSTOUTN		0x464
+
+#endif /* _MUX_DRA7XX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_omap5.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_omap5.h
new file mode 100644
index 000000000..3e93a1512
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/mux_omap5.h
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff		<r-woodruff2@ti.com>
+ * Aneesh V			<aneesh@ti.com>
+ * Balaji Krishnamoorthy	<balajitk@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _MUX_OMAP5_H_
+#define _MUX_OMAP5_H_
+
+#include <asm/types.h>
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_PD          (1 << 12)
+#define OFF_PU          (3 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (2 << 10)
+#define OFF_IN          (1 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (1 << 9)
+#else
+#define OFF_PD          (0 << 12)
+#define OFF_PU          (0 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (0 << 10)
+#define OFF_IN          (0 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (0 << 9)
+#endif
+
+#define IEN             (1 << 8)
+#define IDIS            (0 << 8)
+#define PTU             (3 << 3)
+#define PTD             (1 << 3)
+#define EN              (1 << 3)
+#define DIS             (0 << 3)
+
+#define M0              0
+#define M1              1
+#define M2              2
+#define M3              3
+#define M4              4
+#define M5              5
+#define M6              6
+#define M7              7
+
+#define SAFE_MODE	M7
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
+#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
+#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
+#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
+#else
+#define OFF_IN_PD       0
+#define OFF_IN_PU       0
+#define OFF_OUT_PD      0
+#define OFF_OUT_PU      0
+#endif
+
+#define CORE_REVISION		0x0000
+#define CORE_HWINFO		0x0004
+#define CORE_SYSCONFIG		0x0010
+#define EMMC_CLK		0x0040
+#define EMMC_CMD		0x0042
+#define EMMC_DATA0		0x0044
+#define EMMC_DATA1		0x0046
+#define EMMC_DATA2		0x0048
+#define EMMC_DATA3		0x004a
+#define EMMC_DATA4		0x004c
+#define EMMC_DATA5		0x004e
+#define EMMC_DATA6		0x0050
+#define EMMC_DATA7		0x0052
+#define C2C_CLKOUT0		0x0054
+#define C2C_CLKOUT1		0x0056
+#define C2C_CLKIN0		0x0058
+#define C2C_CLKIN1		0x005a
+#define C2C_DATAIN0		0x005c
+#define C2C_DATAIN1		0x005e
+#define C2C_DATAIN2		0x0060
+#define C2C_DATAIN3		0x0062
+#define C2C_DATAIN4		0x0064
+#define C2C_DATAIN5		0x0066
+#define C2C_DATAIN6		0x0068
+#define C2C_DATAIN7		0x006a
+#define C2C_DATAOUT0		0x006c
+#define C2C_DATAOUT1		0x006e
+#define C2C_DATAOUT2		0x0070
+#define C2C_DATAOUT3		0x0072
+#define C2C_DATAOUT4		0x0074
+#define C2C_DATAOUT5		0x0076
+#define C2C_DATAOUT6		0x0078
+#define C2C_DATAOUT7		0x007a
+#define C2C_DATA8		0x007c
+#define C2C_DATA9		0x007e
+#define C2C_DATA10		0x0080
+#define C2C_DATA11		0x0082
+#define C2C_DATA12		0x0084
+#define C2C_DATA13		0x0086
+#define C2C_DATA14		0x0088
+#define C2C_DATA15		0x008a
+#define LLIA_WAKEREQOUT		0x008c
+#define LLIB_WAKEREQOUT		0x008e
+#define HSI1_ACREADY		0x0090
+#define HSI1_CAREADY		0x0092
+#define HSI1_ACWAKE		0x0094
+#define HSI1_CAWAKE		0x0096
+#define HSI1_ACFLAG		0x0098
+#define HSI1_ACDATA		0x009a
+#define HSI1_CAFLAG		0x009c
+#define HSI1_CADATA		0x009e
+#define UART1_TX		0x00a0
+#define UART1_CTS		0x00a2
+#define UART1_RX		0x00a4
+#define UART1_RTS		0x00a6
+#define HSI2_CAREADY		0x00a8
+#define HSI2_ACREADY		0x00aa
+#define HSI2_CAWAKE		0x00ac
+#define HSI2_ACWAKE		0x00ae
+#define HSI2_CAFLAG		0x00b0
+#define HSI2_CADATA		0x00b2
+#define HSI2_ACFLAG		0x00b4
+#define HSI2_ACDATA		0x00b6
+#define UART2_RTS		0x00b8
+#define UART2_CTS		0x00ba
+#define UART2_RX		0x00bc
+#define UART2_TX		0x00be
+#define USBB1_HSIC_STROBE	0x00c0
+#define USBB1_HSIC_DATA		0x00c2
+#define USBB2_HSIC_STROBE	0x00c4
+#define USBB2_HSIC_DATA		0x00c6
+#define TIMER10_PWM_EVT		0x00c8
+#define DSIPORTA_TE0		0x00ca
+#define DSIPORTA_LANE0X		0x00cc
+#define DSIPORTA_LANE0Y		0x00ce
+#define DSIPORTA_LANE1X		0x00d0
+#define DSIPORTA_LANE1Y		0x00d2
+#define DSIPORTA_LANE2X		0x00d4
+#define DSIPORTA_LANE2Y		0x00d6
+#define DSIPORTA_LANE3X		0x00d8
+#define DSIPORTA_LANE3Y		0x00da
+#define DSIPORTA_LANE4X		0x00dc
+#define DSIPORTA_LANE4Y		0x00de
+#define DSIPORTC_LANE0X		0x00e0
+#define DSIPORTC_LANE0Y		0x00e2
+#define DSIPORTC_LANE1X		0x00e4
+#define DSIPORTC_LANE1Y		0x00e6
+#define DSIPORTC_LANE2X		0x00e8
+#define DSIPORTC_LANE2Y		0x00ea
+#define DSIPORTC_LANE3X		0x00ec
+#define DSIPORTC_LANE3Y		0x00ee
+#define DSIPORTC_LANE4X		0x00f0
+#define DSIPORTC_LANE4Y		0x00f2
+#define DSIPORTC_TE0		0x00f4
+#define TIMER9_PWM_EVT		0x00f6
+#define I2C4_SCL		0x00f8
+#define I2C4_SDA		0x00fa
+#define MCSPI2_CLK		0x00fc
+#define MCSPI2_SIMO		0x00fe
+#define MCSPI2_SOMI		0x0100
+#define MCSPI2_CS0		0x0102
+#define RFBI_DATA15		0x0104
+#define RFBI_DATA14		0x0106
+#define RFBI_DATA13		0x0108
+#define RFBI_DATA12		0x010a
+#define RFBI_DATA11		0x010c
+#define RFBI_DATA10		0x010e
+#define RFBI_DATA9		0x0110
+#define RFBI_DATA8		0x0112
+#define RFBI_DATA7		0x0114
+#define RFBI_DATA6		0x0116
+#define RFBI_DATA5		0x0118
+#define RFBI_DATA4		0x011a
+#define RFBI_DATA3		0x011c
+#define RFBI_DATA2		0x011e
+#define RFBI_DATA1		0x0120
+#define RFBI_DATA0		0x0122
+#define RFBI_WE			0x0124
+#define RFBI_CS0		0x0126
+#define RFBI_A0			0x0128
+#define RFBI_RE			0x012a
+#define RFBI_HSYNC0		0x012c
+#define RFBI_TE_VSYNC0		0x012e
+#define GPIO6_182		0x0130
+#define GPIO6_183		0x0132
+#define GPIO6_184		0x0134
+#define GPIO6_185		0x0136
+#define GPIO6_186		0x0138
+#define GPIO6_187		0x013a
+#define HDMI_CEC		0x013c
+#define HDMI_HPD		0x013e
+#define HDMI_DDC_SCL		0x0140
+#define HDMI_DDC_SDA		0x0142
+#define CSIPORTC_LANE0X		0x0144
+#define CSIPORTC_LANE0Y		0x0146
+#define CSIPORTC_LANE1X		0x0148
+#define CSIPORTC_LANE1Y		0x014a
+#define CSIPORTB_LANE0X		0x014c
+#define CSIPORTB_LANE0Y		0x014e
+#define CSIPORTB_LANE1X		0x0150
+#define CSIPORTB_LANE1Y		0x0152
+#define CSIPORTB_LANE2X		0x0154
+#define CSIPORTB_LANE2Y		0x0156
+#define CSIPORTA_LANE0X		0x0158
+#define CSIPORTA_LANE0Y		0x015a
+#define CSIPORTA_LANE1X		0x015c
+#define CSIPORTA_LANE1Y		0x015e
+#define CSIPORTA_LANE2X		0x0160
+#define CSIPORTA_LANE2Y		0x0162
+#define CSIPORTA_LANE3X		0x0164
+#define CSIPORTA_LANE3Y		0x0166
+#define CSIPORTA_LANE4X		0x0168
+#define CSIPORTA_LANE4Y		0x016a
+#define CAM_SHUTTER		0x016c
+#define CAM_STROBE		0x016e
+#define CAM_GLOBALRESET		0x0170
+#define TIMER11_PWM_EVT		0x0172
+#define TIMER5_PWM_EVT		0x0174
+#define TIMER6_PWM_EVT		0x0176
+#define TIMER8_PWM_EVT		0x0178
+#define I2C3_SCL		0x017a
+#define I2C3_SDA		0x017c
+#define GPIO8_233		0x017e
+#define GPIO8_234		0x0180
+#define ABE_CLKS		0x0182
+#define ABEDMIC_DIN1		0x0184
+#define ABEDMIC_DIN2		0x0186
+#define ABEDMIC_DIN3		0x0188
+#define ABEDMIC_CLK1		0x018a
+#define ABEDMIC_CLK2		0x018c
+#define ABEDMIC_CLK3		0x018e
+#define ABESLIMBUS1_CLOCK	0x0190
+#define ABESLIMBUS1_DATA	0x0192
+#define ABEMCBSP2_DR		0x0194
+#define ABEMCBSP2_DX		0x0196
+#define ABEMCBSP2_FSX		0x0198
+#define ABEMCBSP2_CLKX		0x019a
+#define ABEMCPDM_UL_DATA	0x019c
+#define ABEMCPDM_DL_DATA	0x019e
+#define ABEMCPDM_FRAME		0x01a0
+#define ABEMCPDM_LB_CLK		0x01a2
+#define WLSDIO_CLK		0x01a4
+#define WLSDIO_CMD		0x01a6
+#define WLSDIO_DATA0		0x01a8
+#define WLSDIO_DATA1		0x01aa
+#define WLSDIO_DATA2		0x01ac
+#define WLSDIO_DATA3		0x01ae
+#define UART5_RX		0x01b0
+#define UART5_TX		0x01b2
+#define UART5_CTS		0x01b4
+#define UART5_RTS		0x01b6
+#define I2C2_SCL		0x01b8
+#define I2C2_SDA		0x01ba
+#define MCSPI1_CLK		0x01bc
+#define MCSPI1_SOMI		0x01be
+#define MCSPI1_SIMO		0x01c0
+#define MCSPI1_CS0		0x01c2
+#define MCSPI1_CS1		0x01c4
+#define I2C5_SCL		0x01c6
+#define I2C5_SDA		0x01c8
+#define PERSLIMBUS2_CLOCK	0x01ca
+#define PERSLIMBUS2_DATA	0x01cc
+#define UART6_TX		0x01ce
+#define UART6_RX		0x01d0
+#define UART6_CTS		0x01d2
+#define UART6_RTS		0x01d4
+#define UART3_CTS_RCTX		0x01d6
+#define UART3_RTS_IRSD		0x01d8
+#define UART3_TX_IRTX		0x01da
+#define UART3_RX_IRRX		0x01dc
+#define USBB3_HSIC_STROBE	0x01de
+#define USBB3_HSIC_DATA		0x01e0
+#define SDCARD_CLK		0x01e2
+#define SDCARD_CMD		0x01e4
+#define SDCARD_DATA2		0x01e6
+#define SDCARD_DATA3		0x01e8
+#define SDCARD_DATA0		0x01ea
+#define SDCARD_DATA1		0x01ec
+#define USBD0_HS_DP		0x01ee
+#define USBD0_HS_DM		0x01f0
+#define I2C1_PMIC_SCL		0x01f2
+#define I2C1_PMIC_SDA		0x01f4
+#define USBD0_SS_RX		0x01f6
+
+#define LLIA_WAKEREQIN		0x0040
+#define LLIB_WAKEREQIN		0x0042
+#define DRM_EMU0		0x0044
+#define DRM_EMU1		0x0046
+#define JTAG_NTRST		0x0048
+#define JTAG_TCK		0x004a
+#define JTAG_RTCK		0x004c
+#define JTAG_TMSC		0x004e
+#define JTAG_TDI		0x0050
+#define JTAG_TDO		0x0052
+#define SYS_32K			0x0054
+#define FREF_CLK_IOREQ		0x0056
+#define FREF_CLK0_OUT		0x0058
+#define FREF_CLK1_OUT		0x005a
+#define FREF_CLK2_OUT		0x005c
+#define FREF_CLK2_REQ		0x005e
+#define FREF_CLK1_REQ		0x0060
+#define SYS_NRESPWRON		0x0062
+#define SYS_NRESWARM		0x0064
+#define SYS_PWR_REQ		0x0066
+#define SYS_NIRQ1		0x0068
+#define SYS_NIRQ2		0x006a
+#define SR_PMIC_SCL		0x006c
+#define SR_PMIC_SDA		0x006e
+#define SYS_BOOT0		0x0070
+#define SYS_BOOT1		0x0072
+#define SYS_BOOT2		0x0074
+#define SYS_BOOT3		0x0076
+#define SYS_BOOT4		0x0078
+#define SYS_BOOT5		0x007a
+
+#endif /* _MUX_OMAP5_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h
new file mode 100644
index 000000000..19fdecec0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/omap.h
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ *	Aneesh V <aneesh@ti.com>
+ *	Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _OMAP5_H_
+#define _OMAP5_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP54XX_L4_CORE_BASE	0x4A000000
+#define OMAP54XX_L4_WKUP_BASE	0x4Ae00000
+#define OMAP54XX_L4_PER_BASE	0x48000000
+
+#define OMAP54XX_DRAM_ADDR_SPACE_START	0x80000000
+#define OMAP54XX_DRAM_ADDR_SPACE_END	0xFFFFFFFF
+#define DRAM_ADDR_SPACE_START	OMAP54XX_DRAM_ADDR_SPACE_START
+#define DRAM_ADDR_SPACE_END	OMAP54XX_DRAM_ADDR_SPACE_END
+
+/* CONTROL ID CODE */
+#define CONTROL_CORE_ID_CODE	0x4A002204
+#define CONTROL_WKUP_ID_CODE	0x4AE0C204
+
+#ifdef CONFIG_DRA7XX
+#define CONTROL_ID_CODE		CONTROL_WKUP_ID_CODE
+#else
+#define CONTROL_ID_CODE		CONTROL_CORE_ID_CODE
+#endif
+
+/* To be verified */
+#define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
+#define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
+#define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
+#define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
+#define DRA752_CONTROL_ID_CODE_ES1_0		0x0B99002F
+#define DRA752_CONTROL_ID_CODE_ES1_1		0x1B99002F
+
+/* UART */
+#define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE		(OMAP54XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE		(OMAP54XX_L4_PER_BASE + 0x20000)
+
+/* General Purpose Timers */
+#define GPT1_BASE		(OMAP54XX_L4_WKUP_BASE + 0x18000)
+#define GPT2_BASE		(OMAP54XX_L4_PER_BASE  + 0x32000)
+#define GPT3_BASE		(OMAP54XX_L4_PER_BASE  + 0x34000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define WDT2_BASE		(OMAP54XX_L4_WKUP_BASE + 0x14000)
+
+/* GPMC */
+#define OMAP54XX_GPMC_BASE	0x50000000
+
+/* QSPI */
+#define QSPI_BASE		0x4B300000
+
+/* SATA */
+#define DWC_AHSATA_BASE		0x4A140000
+
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+/* GP Timer */
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* Control Module */
+#define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
+#define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
+#define CONTROL_EFUSE_1_OVERRIDE	0x1C4D0110
+#define CONTROL_EFUSE_2_OVERRIDE	0x00084000
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN	0x7C7C7C7C
+#define LPDDR2IO_GR10_WD_MASK				(3 << 17)
+#define CONTROL_LPDDR2IO_3_VAL		0xA0888C00
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
+#define SDCARD_BIAS_PWRDNZ				(1 << 27)
+#define SDCARD_PWRDNZ					(1 << 26)
+#define SDCARD_BIAS_HIZ_MODE				(1 << 25)
+#define SDCARD_PBIASLITE_VMODE				(1 << 21)
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+	unsigned char res[0x10];
+	unsigned int s32k_cr;	/* 0x10 */
+};
+
+#define DEVICE_TYPE_SHIFT 0x6
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+#define DEVICE_GP 0x3
+
+/* Output impedance control */
+#define ds_120_ohm	0x0
+#define ds_60_ohm	0x1
+#define ds_45_ohm	0x2
+#define ds_30_ohm	0x3
+#define ds_mask		0x3
+
+/* Slew rate control */
+#define sc_slow		0x0
+#define sc_medium	0x1
+#define sc_fast		0x2
+#define sc_na		0x3
+#define sc_mask		0x3
+
+/* Target capacitance control */
+#define lb_5_12_pf	0x0
+#define lb_12_25_pf	0x1
+#define lb_25_50_pf	0x2
+#define lb_50_80_pf	0x3
+#define lb_mask		0x3
+
+#define usb_i_mask	0x7
+
+#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN   0x80828082
+#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
+#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
+#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
+#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
+
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL	0x7C7C7C6C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL	0x64646464
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE				0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE				0xBC6318DC
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE				0x0
+
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
+
+#define EFUSE_1 0x45145100
+#define EFUSE_2 0x45145100
+#define EFUSE_3 0x45145100
+#define EFUSE_4 0x45145100
+#endif /* __ASSEMBLY__ */
+
+/*
+ * In all cases, the TRM defines the RAM Memory Map for the processor
+ * and indicates the area for the downloaded image.  We use all of that
+ * space for download and once up and running may use other parts of the
+ * map for our needs.  We set a scratch space that is at the end of the
+ * OMAP5 download area, but within the DRA7xx download area (as it is
+ * much larger) and do not, at this time, make use of the additional
+ * space.
+ */
+#ifdef CONFIG_DRA7XX
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */
+#else
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
+#endif
+#define SRAM_SCRATCH_SPACE_ADDR	0x4031E000
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE	0x4031F000
+
+/* CONTROL_SRCOMP_XXX_SIDE */
+#define OVERRIDE_XS_SHIFT		30
+#define OVERRIDE_XS_MASK		(1 << 30)
+#define SRCODE_READ_XS_SHIFT		12
+#define SRCODE_READ_XS_MASK		(0xff << 12)
+#define PWRDWN_XS_SHIFT			11
+#define PWRDWN_XS_MASK			(1 << 11)
+#define DIVIDE_FACTOR_XS_SHIFT		4
+#define DIVIDE_FACTOR_XS_MASK		(0x7f << 4)
+#define MULTIPLY_FACTOR_XS_SHIFT	1
+#define MULTIPLY_FACTOR_XS_MASK		(0x7 << 1)
+#define SRCODE_OVERRIDE_SEL_XS_SHIFT	0
+#define SRCODE_OVERRIDE_SEL_XS_MASK	(1 << 0)
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME		50
+#define OMAP_ABB_CLOCK_CYCLES		16
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK		(0x1 << 7)
+
+/* ABB efuse masks */
+#define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)
+#define OMAP5_ABB_FUSE_ENABLE_MASK		(0x1 << 29)
+#define DRA7_ABB_FUSE_VSET_MASK			(0x1F << 20)
+#define DRA7_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
+#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
+#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK	(0x1f << 0)
+
+/* IO Delay module defines */
+#define CFG_IO_DELAY_BASE		0x4844A000
+#define CFG_IO_DELAY_LOCK		(CFG_IO_DELAY_BASE + 0x02C)
+
+/* CPSW IO Delay registers*/
+#define CFG_RGMII0_TXCTL		(CFG_IO_DELAY_BASE + 0x74C)
+#define CFG_RGMII0_TXD0			(CFG_IO_DELAY_BASE + 0x758)
+#define CFG_RGMII0_TXD1			(CFG_IO_DELAY_BASE + 0x764)
+#define CFG_RGMII0_TXD2			(CFG_IO_DELAY_BASE + 0x770)
+#define CFG_RGMII0_TXD3			(CFG_IO_DELAY_BASE + 0x77C)
+#define CFG_VIN2A_D13			(CFG_IO_DELAY_BASE + 0xA7C)
+#define CFG_VIN2A_D17			(CFG_IO_DELAY_BASE + 0xAAC)
+#define CFG_VIN2A_D16			(CFG_IO_DELAY_BASE + 0xAA0)
+#define CFG_VIN2A_D15			(CFG_IO_DELAY_BASE + 0xA94)
+#define CFG_VIN2A_D14			(CFG_IO_DELAY_BASE + 0xA88)
+
+#define CFG_IO_DELAY_UNLOCK_KEY		0x0000AAAA
+#define CFG_IO_DELAY_LOCK_KEY		0x0000AAAB
+#define CFG_IO_DELAY_ACCESS_PATTERN	0x00029000
+#define CFG_IO_DELAY_LOCK_MASK		0x400
+
+#ifndef __ASSEMBLY__
+struct srcomp_params {
+	s8 divide_factor;
+	s8 multiply_factor;
+};
+
+struct ctrl_ioregs {
+	u32 ctrl_ddrch;
+	u32 ctrl_lpddr2ch;
+	u32 ctrl_ddr3ch;
+	u32 ctrl_ddrio_0;
+	u32 ctrl_ddrio_1;
+	u32 ctrl_ddrio_2;
+	u32 ctrl_emif_sdram_config_ext;
+	u32 ctrl_emif_sdram_config_ext_final;
+	u32 ctrl_ddr_ctrl_ext_0;
+};
+
+struct io_delay {
+	u32 addr;
+	u32 dly;
+};
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h
new file mode 100644
index 000000000..b69165b5e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sata.h
@@ -0,0 +1,39 @@
+/*
+ * SATA Wrapper Register map
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TI_SATA_H
+#define _TI_SATA_H
+
+/* SATA Wrapper module */
+#define TI_SATA_WRAPPER_BASE		(OMAP54XX_L4_CORE_BASE + 0x141100)
+/* SATA PHY Module */
+#define TI_SATA_PLLCTRL_BASE		(OMAP54XX_L4_CORE_BASE + 0x96800)
+
+/* SATA Wrapper register offsets */
+#define TI_SATA_SYSCONFIG			0x00
+#define TI_SATA_CDRLOCK				0x04
+
+/* Register Set */
+#define TI_SATA_SYSCONFIG_OVERRIDE0		(1 << 16)
+#define TI_SATA_SYSCONFIG_STANDBY_MASK		(0x3 << 4)
+#define TI_SATA_SYSCONFIG_IDLE_MASK		(0x3 << 2)
+
+/* Standby modes */
+#define TI_SATA_STANDBY_FORCE			0x0
+#define TI_SATA_STANDBY_NO			(0x1 << 4)
+#define TI_SATA_STANDBY_SMART_WAKE		(0x3 << 4)
+#define TI_SATA_STANDBY_SMART			(0x2 << 4)
+
+/* Idle modes */
+#define TI_SATA_IDLE_FORCE			0x0
+#define TI_SATA_IDLE_NO				(0x1 << 2)
+#define TI_SATA_IDLE_SMART_WAKE			(0x3 << 2)
+#define TI_SATA_IDLE_SMART			(0x2 << 2)
+
+#endif /* _TI_SATA_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h
new file mode 100644
index 000000000..f70799860
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/spl.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NONE        0
+#define BOOT_DEVICE_XIP         1
+#define BOOT_DEVICE_XIPWAIT     2
+#define BOOT_DEVICE_NAND        3
+#define BOOT_DEVICE_ONENAND    4
+#define BOOT_DEVICE_MMC1        5
+#define BOOT_DEVICE_MMC2        6
+#define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_SATA	9
+#define BOOT_DEVICE_SPI		10
+#define BOOT_DEVICE_UART	0x43
+
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2_2
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sys_proto.h
new file mode 100644
index 000000000..bf12c7337
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/omap_common.h>
+#include <linux/mtd/omap_gpmc.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pad_conf_entry {
+	u32 offset;
+	u32 val;
+};
+
+struct omap_sysinfo {
+	char *board_string;
+};
+extern const struct omap_sysinfo sysinfo;
+
+void gpmc_init(void);
+void watchdog_init(void);
+u32 get_device_type(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_essential(void);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void setup_clocks_for_console(void);
+void prcm_init(void);
+void bypass_dpll(u32 const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap5_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
+void sdram_init(void);
+u32 omap_sdram_size(void);
+u32 cortex_rev(void);
+void save_omap_boot_params(void);
+void init_omap_revision(void);
+void do_io_settings(void);
+void sri2c_init(void);
+void gpi2c_init(void);
+int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
+u32 warm_reset(void);
+void force_emif_self_refresh(void);
+void get_ioregs(const struct ctrl_ioregs **regs);
+void srcomp_enable(void);
+void setup_warmreset_time(void);
+
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) &&
+	    (pc < OMAP54XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+	/*
+	 * u-boot can be running from sdram either because of configuration
+	 * Header or by SPL. If because of CH, then the romcode sets the
+	 * CHSETTINGS executed bit to true in the boot parameter structure that
+	 * it passes to the bootloader.This parameter is stored in the ch_flags
+	 * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
+	 * mandatory section if CH is present.
+	 */
+	if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+		return 0;
+	else
+		return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap_hw_init_context(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	return OMAP_INIT_CONTEXT_SPL;
+#else
+	if (uboot_loaded_by_spl())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
+	else if (running_from_sdram())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
+	else
+		return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
+#endif
+}
+
+static inline u32 div_round_up(u32 num, u32 den)
+{
+	return (num + den - 1)/den;
+}
+
+static inline u32 usec_to_32k(u32 usec)
+{
+	return div_round_up(32768 * usec, 1000000);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/cpu.h
new file mode 100644
index 000000000..08a450f1f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/cpu.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on original Kirorion5x_ood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ORION5X_CPU_H
+#define _ORION5X_CPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+			| (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
+
+#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
+		((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+	BANK2,
+	BANK3
+};
+
+enum orion5x_cpu_winen {
+	ORION5X_WIN_DISABLE,
+	ORION5X_WIN_ENABLE
+};
+
+enum orion5x_cpu_target {
+	ORION5X_TARGET_DRAM = 0,
+	ORION5X_TARGET_DEVICE = 1,
+	ORION5X_TARGET_PCI = 3,
+	ORION5X_TARGET_PCIE = 4,
+	ORION5X_TARGET_SASRAM = 9
+};
+
+enum orion5x_cpu_attrib {
+	ORION5X_ATTR_DRAM_CS0 = 0x0e,
+	ORION5X_ATTR_DRAM_CS1 = 0x0d,
+	ORION5X_ATTR_DRAM_CS2 = 0x0b,
+	ORION5X_ATTR_DRAM_CS3 = 0x07,
+	ORION5X_ATTR_PCI_MEM = 0x59,
+	ORION5X_ATTR_PCI_IO = 0x51,
+	ORION5X_ATTR_PCIE_MEM = 0x59,
+	ORION5X_ATTR_PCIE_IO = 0x51,
+	ORION5X_ATTR_SASRAM = 0x00,
+	ORION5X_ATTR_DEV_CS0 = 0x1e,
+	ORION5X_ATTR_DEV_CS1 = 0x1d,
+	ORION5X_ATTR_DEV_CS2 = 0x1b,
+	ORION5X_ATTR_BOOTROM = 0x0f
+};
+
+/*
+ * Device Address MAP BAR values
+ *
+ * All addresses and sizes not defined by board code
+ * will be given default values here.
+ */
+
+#if !defined (ORION5X_ADR_PCIE_MEM)
+#define ORION5X_ADR_PCIE_MEM	0x90000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO)
+#define ORION5X_ADR_PCIE_MEM_REMAP_LO	0x90000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI)
+#define ORION5X_ADR_PCIE_MEM_REMAP_HI	0
+#endif
+
+#if !defined (ORION5X_SZ_PCIE_MEM)
+#define ORION5X_SZ_PCIE_MEM	(128*1024*1024)
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_IO)
+#define ORION5X_ADR_PCIE_IO	0xf0000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
+#define ORION5X_ADR_PCIE_IO_REMAP_LO	0x90000000
+#endif
+
+#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
+#define ORION5X_ADR_PCIE_IO_REMAP_HI	0
+#endif
+
+#if !defined (ORION5X_SZ_PCIE_IO)
+#define ORION5X_SZ_PCIE_IO	(64*1024)
+#endif
+
+#if !defined (ORION5X_ADR_PCI_MEM)
+#define ORION5X_ADR_PCI_MEM	0x98000000
+#endif
+
+#if !defined (ORION5X_SZ_PCI_MEM)
+#define ORION5X_SZ_PCI_MEM	(128*1024*1024)
+#endif
+
+#if !defined (ORION5X_ADR_PCI_IO)
+#define ORION5X_ADR_PCI_IO	0xf0100000
+#endif
+
+#if !defined (ORION5X_SZ_PCI_IO)
+#define ORION5X_SZ_PCI_IO	(64*1024)
+#endif
+
+#if !defined (ORION5X_ADR_DEV_CS0)
+#define ORION5X_ADR_DEV_CS0	0xfa000000
+#endif
+
+#if !defined (ORION5X_SZ_DEV_CS0)
+#define ORION5X_SZ_DEV_CS0	(2*1024*1024)
+#endif
+
+#if !defined (ORION5X_ADR_DEV_CS1)
+#define ORION5X_ADR_DEV_CS1	0xf8000000
+#endif
+
+#if !defined (ORION5X_SZ_DEV_CS1)
+#define ORION5X_SZ_DEV_CS1	(32*1024*1024)
+#endif
+
+#if !defined (ORION5X_ADR_DEV_CS2)
+#define ORION5X_ADR_DEV_CS2	0xfa800000
+#endif
+
+#if !defined (ORION5X_SZ_DEV_CS2)
+#define ORION5X_SZ_DEV_CS2	(1*1024*1024)
+#endif
+
+#if !defined (ORION5X_ADR_BOOTROM)
+#define ORION5X_ADR_BOOTROM	0xFFF80000
+#endif
+
+#if !defined (ORION5X_SZ_BOOTROM)
+#define ORION5X_SZ_BOOTROM	(512*1024)
+#endif
+
+/*
+ * PCIE registers are used for SoC device ID and revision
+ */
+#define PCIE_DEV_ID_OFF         (ORION5X_REG_PCIE_BASE + 0x0000)
+#define PCIE_DEV_REV_OFF        (ORION5X_REG_PCIE_BASE + 0x0008)
+
+/*
+ * The following definitions are intended for identifying
+ * the real device and revision on which u-boot is running
+ * even if it was compiled only for a specific one. Thus,
+ * these constants must not be considered chip-specific.
+ */
+
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+#define MV88F5181L_REV_A0       8
+#define MV88F5181L_REV_A1       9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID        0x5182
+#define MV88F5182_REV_A2        2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID        0x5281
+#define MV88F5281_REV_D0        4
+#define MV88F5281_REV_D1        5
+#define MV88F5281_REV_D2        6
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID        0x6183
+#define MV88F6183_REV_B0        3
+
+/*
+ * read feroceon core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+	unsigned int val;
+	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
+			(val) : : "cc");
+	return val;
+}
+
+/*
+ * write feroceon core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
+			(val) : "cc");
+	isb();
+}
+
+/*
+ * AHB to Mbus Bridge Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.4
+ * Note: only windows 0 and 1 have remap capability.
+ */
+struct orion5x_win_registers {
+	u32 ctrl;
+	u32 base;
+	u32 remap_lo;
+	u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.4
+ */
+struct orion5x_cpu_registers {
+	u32 config;	/*0x20100 */
+	u32 ctrl_stat;	/*0x20104 */
+	u32 rstoutn_mask; /* 0x20108 */
+	u32 sys_soft_rst; /* 0x2010C */
+	u32 ahb_mbus_cause_irq; /* 0x20110 */
+	u32 ahb_mbus_mask_irq; /* 0x20114 */
+};
+
+/*
+ * DDR SDRAM Controller Address Decode Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.5.1
+ */
+struct orion5x_ddr_addr_decode_registers {
+	u32 base;
+	u32 size;
+};
+
+/*
+ * functions
+ */
+u32 orion5x_device_id(void);
+u32 orion5x_device_rev(void);
+unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
+void timer_init_r(void);
+#endif /* __ASSEMBLY__ */
+#endif /* _ORION5X_CPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/mv88f5182.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/mv88f5182.h
new file mode 100644
index 000000000..e6c71ae1b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/mv88f5182.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on original Kirkwood 88F6182 support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Feroceon CPU core 88F5182 SOC.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_88F5182_H
+#define _CONFIG_88F5182_H
+
+/* SOC specific definitions */
+#define F88F5182_REGS_PHYS_BASE		0xf1000000
+#define ORION5X_REGS_PHY_BASE		F88F5182_REGS_PHYS_BASE
+
+/* TCLK Core Clock defination */
+#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
+
+#endif /* _CONFIG_88F5182_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/orion5x.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/orion5x.h
new file mode 100644
index 000000000..fbb1de8c0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Marvell's Orion SoC with Feroceon CPU core.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_ORION5X_H
+#define _ASM_ARCH_ORION5X_H
+
+#if defined(CONFIG_FEROCEON)
+
+/* SOC specific definations */
+#define ORION5X_REGISTER(x)			(ORION5X_REGS_PHY_BASE + x)
+
+/* Documented registers */
+#define ORION5X_DRAM_BASE			(ORION5X_REGISTER(0x01500))
+#define ORION5X_TWSI_BASE			(ORION5X_REGISTER(0x11000))
+#define ORION5X_UART0_BASE			(ORION5X_REGISTER(0x12000))
+#define ORION5X_UART1_BASE			(ORION5X_REGISTER(0x12100))
+#define ORION5X_MPP_BASE			(ORION5X_REGISTER(0x10000))
+#define ORION5X_GPIO_BASE			(ORION5X_REGISTER(0x10100))
+#define ORION5X_CPU_WIN_BASE			(ORION5X_REGISTER(0x20000))
+#define ORION5X_CPU_REG_BASE			(ORION5X_REGISTER(0x20100))
+#define ORION5X_TIMER_BASE			(ORION5X_REGISTER(0x20300))
+#define ORION5X_REG_PCI_BASE			(ORION5X_REGISTER(0x30000))
+#define ORION5X_REG_PCIE_BASE			(ORION5X_REGISTER(0x40000))
+#define ORION5X_USB20_PORT0_BASE		(ORION5X_REGISTER(0x50000))
+#define ORION5X_USB20_PORT1_BASE		(ORION5X_REGISTER(0xA0000))
+#define ORION5X_EGIGA_BASE			(ORION5X_REGISTER(0x72000))
+#define ORION5X_SATA_BASE			(ORION5X_REGISTER(0x80000))
+#define ORION5X_SATA_PORT0_OFFSET		0x2000
+#define ORION5X_SATA_PORT1_OFFSET		0x4000
+
+/* Orion5x GbE controller has a single port */
+#define MAX_MVGBE_DEVS	1
+#define MVGBE0_BASE	ORION5X_EGIGA_BASE
+
+/* Orion5x USB Host controller is port 1 */
+#define MVUSB0_BASE			ORION5X_USB20_HOST_PORT_BASE
+#define MVUSB0_CPU_ATTR_DRAM_CS0	ORION5X_ATTR_DRAM_CS0
+#define MVUSB0_CPU_ATTR_DRAM_CS1	ORION5X_ATTR_DRAM_CS1
+#define MVUSB0_CPU_ATTR_DRAM_CS2	ORION5X_ATTR_DRAM_CS2
+#define MVUSB0_CPU_ATTR_DRAM_CS3	ORION5X_ATTR_DRAM_CS3
+
+/* Kirkwood CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA	ORION5X_CPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE	ORION5X_WIN_ENABLE
+#define MVCPU_WIN_DISABLE	ORION5X_WIN_DISABLE
+
+#define CONFIG_MAX_RAM_BANK_SIZE		(64*1024*1024)
+
+/* include here SoC variants. 5181, 5281, 6183 should go here when
+   adding support for them, and this comment should then be updated. */
+#if defined(CONFIG_88F5182)
+#include <asm/arch/mv88f5182.h>
+#else
+#error "SOC Name not defined"
+#endif
+#endif /* CONFIG_FEROCEON */
+#endif /* _ASM_ARCH_ORION5X_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/config.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/config.h
new file mode 100644
index 000000000..fdccd222d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/config.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PANTHEON_CONFIG_H
+#define _PANTHEON_CONFIG_H
+
+#include <asm/arch/pantheon.h>
+
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+/* default Dcache Line length for pantheon */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
+#define MV_MFPR_BASE		PANTHEON_MFPR_BASE
+#define MV_UART_CONSOLE_BASE	PANTHEON_UART1_BASE
+#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
+						represents UART Unit Enable */
+/*
+ * I2C definition
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MV			1
+#define CONFIG_MV_I2C_REG		0xd4011000
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		0
+#define CONFIG_SYS_I2C_SLAVE		0xfe
+#endif
+
+/*
+ * MMC definition
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT			1
+#define CONFIG_MMC			1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_SDHCI			1
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS	1
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	0x1000
+#define CONFIG_MMC_SDMA			1
+#define CONFIG_MV_SDHCI			1
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_EFI_PARTITION		1
+#define CONFIG_SYS_MMC_NUM		2
+#define CONFIG_SYS_MMC_BASE		{0xD4280000, 0xd4281000}
+#endif
+
+#endif /* _PANTHEON_CONFIG_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/cpu.h
new file mode 100644
index 000000000..3ccdf8a35
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/cpu.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PANTHEON_CPU_H
+#define _PANTHEON_CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Register Datasheet 9.1
+ */
+struct panthmpmu_registers {
+	u8 pad0[0x0024];
+	u32 ccgr;	/*0x0024*/
+	u8 pad1[0x0200 - 0x024 - 4];
+	u32 wdtpcr;	/*0x0200*/
+	u8 pad2[0x1020 - 0x200 - 4];
+	u32 aprr;	/*0x1020*/
+	u32 acgr;	/*0x1024*/
+};
+
+/*
+ * Application Power Management (APMU) Registers
+ * Refer Register Datasheet 9.2
+ */
+struct panthapmu_registers {
+	u8 pad0[0x0054];
+	u32 sd1;	/*0x0054*/
+	u8 pad1[0x00e0 - 0x054 - 4];
+	u32 sd3;	/*0x00e0*/
+};
+
+/*
+ * APB Clock Reset/Control Registers
+ * Refer Register Datasheet 6.14
+ */
+struct panthapb_registers {
+	u32 uart0;	/*0x000*/
+	u32 uart1;	/*0x004*/
+	u32 gpio;	/*0x008*/
+	u8 pad0[0x02c - 0x08 - 4];
+	u32 twsi;	/*0x02c*/
+	u8 pad1[0x034 - 0x2c - 4];
+	u32 timers;	/*0x034*/
+};
+
+/*
+ * CPU Interface Registers
+ * Refer Register Datasheet 4.3
+ */
+struct panthcpu_registers {
+	u32 chip_id;		/* Chip Id Reg */
+	u32 pad;
+	u32 cpu_conf;		/* CPU Conf Reg */
+	u32 pad1;
+	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
+	u32 pad2;
+	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
+	u32 mcb_conf;		/* MCB Conf Reg */
+	u32 sys_boot_ctl;	/* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 panth_sdram_base(int);
+u32 panth_sdram_size(int);
+int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
+#endif /* _PANTHEON_CPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/mfp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/mfp.h
new file mode 100644
index 000000000..7909d53d4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/mfp.h
@@ -0,0 +1,39 @@
+/*
+ * Based on arch/arm/include/asm/arch-armada100/mfp.h
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PANTHEON_MFP_H
+#define __PANTHEON_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
+ *
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART2 */
+#define MFP47_UART2_RXD		(MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM)
+#define MFP48_UART2_TXD		(MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
+#define MFP53_CI2C_SCL		(MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP54_CI2C_SDA		(MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+/* More macros can be defined here... */
+#define MFP_MMC1_DAT7		(MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT6		(MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT5		(MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT4		(MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT3		(MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_DAT2		(MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_DAT1		(MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_DAT0		(MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_CMD		(MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_CLK		(MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_CD		(MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_WP		(MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+
+#define MFP_PIN_MAX	117
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/pantheon.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/pantheon.h
new file mode 100644
index 000000000..c3a71bfce
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pantheon/pantheon.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PANTHEON_H
+#define _PANTHEON_H
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
+#define APBC_RST        (1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+/* Common APMU register bit definitions */
+#define APMU_PERI_CLK	(1<<4)	/* Peripheral Clock Enable */
+#define APMU_AXI_CLK	(1<<3)	/* AXI Clock Enable*/
+#define APMU_PERI_RST	(1<<1)	/* Peripheral Reset */
+#define APMU_AXI_RST	(1<<0)	/* AXI Reset */
+
+/* Register Base Addresses */
+#define PANTHEON_DRAM_BASE	0xB0000000
+#define PANTHEON_TIMER_BASE	0xD4014000
+#define PANTHEON_WD_TIMER_BASE	0xD4080000
+#define PANTHEON_APBC_BASE	0xD4015000
+#define PANTHEON_UART1_BASE	0xD4017000
+#define PANTHEON_UART2_BASE	0xD4018000
+#define PANTHEON_GPIO_BASE	0xD4019000
+#define PANTHEON_MFPR_BASE	0xD401E000
+#define PANTHEON_MPMU_BASE	0xD4050000
+#define PANTHEON_APMU_BASE	0xD4282800
+#define PANTHEON_CPU_BASE	0xD4282C00
+
+#endif /* _PANTHEON_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/bitfield.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/bitfield.h
new file mode 100644
index 000000000..104a21c2e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/bitfield.h
@@ -0,0 +1,112 @@
+/*
+ *	FILE		bitfield.h
+ *
+ *	Version		1.1
+ *	Author		Copyright (c) Marc A. Viredaz, 1998
+ *			DEC Western Research Laboratory, Palo Alto, CA
+ *	Date		April 1998 (April 1997)
+ *	System		Advanced RISC Machine (ARM)
+ *	Language	C or ARM Assembly
+ *	Purpose		Definition of macros to operate on bit fields.
+ */
+
+
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
+
+#ifndef __ASSEMBLY__
+#define UData(Data)	((unsigned long) (Data))
+#else
+#define UData(Data)	(Data)
+#endif
+
+
+/*
+ * MACRO: Fld
+ *
+ * Purpose
+ *    The macro "Fld" encodes a bit field, given its size and its shift value
+ *    with respect to bit 0.
+ *
+ * Note
+ *    A more intuitive way to encode bit fields would have been to use their
+ *    mask. However, extracting size and shift value information from a bit
+ *    field's mask is cumbersome and might break the assembler (255-character
+ *    line-size limit).
+ *
+ * Input
+ *    Size		Size of the bit field, in number of bits.
+ *    Shft		Shift value of the bit field with respect to bit 0.
+ *
+ * Output
+ *    Fld		Encoded bit field.
+ */
+
+#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
+
+
+/*
+ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
+ *
+ * Purpose
+ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
+ *    the size, shift value, mask, aligned mask, and first bit of a
+ *    bit field.
+ *
+ * Input
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FSize		Size of the bit field, in number of bits.
+ *    FShft		Shift value of the bit field with respect to bit 0.
+ *    FMsk		Mask for the bit field.
+ *    FAlnMsk		Mask for the bit field, aligned on bit 0.
+ *    F1stBit		First bit of the bit field.
+ */
+
+#define FSize(Field)	((Field) >> 16)
+#define FShft(Field)	((Field) & 0x0000FFFF)
+#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field)	(UData (1) << FShft (Field))
+
+
+/*
+ * MACRO: FInsrt
+ *
+ * Purpose
+ *    The macro "FInsrt" inserts a value into a bit field by shifting the
+ *    former appropriately.
+ *
+ * Input
+ *    Value		Bit-field value.
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FInsrt		Bit-field value positioned appropriately.
+ */
+
+#define FInsrt(Value, Field) \
+			(UData (Value) << FShft (Field))
+
+
+/*
+ * MACRO: FExtr
+ *
+ * Purpose
+ *    The macro "FExtr" extracts the value of a bit field by masking and
+ *    shifting it appropriately.
+ *
+ * Input
+ *    Data		Data containing the bit-field to be extracted.
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FExtr		Bit-field value.
+ */
+
+#define FExtr(Data, Field) \
+			((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+
+#endif /* __BITFIELD_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/hardware.h
new file mode 100644
index 000000000..e671c143a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/hardware.h
@@ -0,0 +1,111 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/hardware.h
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Jun 15, 2001
+ *  Copyright:	MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Note: This file was taken from linux-2.4.19-rmk4-pxa1
+ *
+ * - 2003/01/20 implementation specifics activated
+ *   Robert Schwebel <r.schwebel@pengutronix.de>
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/mach-types.h>
+
+/*
+ * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
+ * PXA300/310/320 all have distinct register mappings in some cases, that's why
+ * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
+ * drivers and compatibility glue with old source then.
+ */
+#ifndef	CONFIG_CPU_MONAHANS
+#if	defined(CONFIG_CPU_PXA300) || \
+	defined(CONFIG_CPU_PXA310) || \
+	defined(CONFIG_CPU_PXA320)
+#define	CONFIG_CPU_MONAHANS
+#endif
+#endif
+
+/*
+ * These are statically mapped PCMCIA IO space for designs using it as a
+ * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
+ * The actual PCMCIA code is mapping required IO region at run time.
+ */
+#define PCMCIA_IO_0_BASE	0xf6000000
+#define PCMCIA_IO_1_BASE	0xf7000000
+
+
+/*
+ * We requires absolute addresses.
+ */
+#define PCIO_BASE		0
+
+/*
+ * Workarounds for at least 2 errata so far require this.
+ * The mapping is set in mach-pxa/generic.c.
+ */
+#define UNCACHED_PHYS_0		0xff000000
+#define UNCACHED_ADDR		UNCACHED_PHYS_0
+
+/*
+ * Intel PXA internal I/O mappings:
+ *
+ * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
+ * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
+ * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
+ */
+
+#include "pxa-regs.h"
+
+#ifndef __ASSEMBLY__
+
+/*
+ * GPIO edge detection for IRQs:
+ * IRQs are generated on Falling-Edge, Rising-Edge, or both.
+ * This must be called *before* the corresponding IRQ is registered.
+ * Use this instead of directly setting GRER/GFER.
+ */
+#define GPIO_FALLING_EDGE	1
+#define GPIO_RISING_EDGE	2
+#define GPIO_BOTH_EDGES		3
+
+#endif
+
+
+/*
+ * Implementation specifics
+ */
+
+#ifdef CONFIG_ARCH_LUBBOCK
+#include "lubbock.h"
+#endif
+
+#ifdef CONFIG_ARCH_PXA_IDP
+#include "idp.h"
+#endif
+
+#ifdef CONFIG_ARCH_PXA_CERF
+#include "cerf.h"
+#endif
+
+#ifdef CONFIG_ARCH_CSB226
+#include "csb226.h"
+#endif
+
+#ifdef CONFIG_ARCH_INNOKOM
+#include "innokom.h"
+#endif
+
+#ifdef CONFIG_ARCH_PLEB
+#include "pleb.h"
+#endif
+
+#endif	/* _ASM_ARCH_HARDWARE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa-regs.h
new file mode 100644
index 000000000..b81b42c07
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -0,0 +1,2635 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/pxa-regs.h
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Jun 15, 2001
+ *  Copyright:	MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
+ *   Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
+ *   Added include for hardware.h (for __REG definition)
+ */
+#ifndef _PXA_REGS_H_
+#define _PXA_REGS_H_
+
+#include "bitfield.h"
+#include "hardware.h"
+
+/* FIXME hack so that SA-1111.h will work [cb] */
+
+#ifndef __ASSEMBLY__
+typedef unsigned short	Word16 ;
+typedef unsigned int	Word32 ;
+typedef Word32		Word ;
+typedef Word		Quad [4] ;
+typedef void		*Address ;
+typedef void		(*ExcpHndlr) (void) ;
+#endif
+
+/*
+ * PXA Chip selects
+ */
+#ifdef CONFIG_CPU_MONAHANS
+#define PXA_CS0_PHYS   0x00000000 /* for both small and large same start */
+#define PXA_CS1_PHYS   0x04000000 /* Small partition start address (64MB) */
+#define PXA_CS1_LPHYS  0x30000000 /* Large partition start address (256MB) */
+#define PXA_CS2_PHYS   0x10000000 /* (64MB) */
+#define PXA_CS3_PHYS   0x14000000 /* (64MB) */
+#define PXA_PCMCIA_PHYS        0x20000000 /* (256MB) */
+#else
+#define PXA_CS0_PHYS	0x00000000
+#define PXA_CS1_PHYS	0x04000000
+#define PXA_CS2_PHYS	0x08000000
+#define PXA_CS3_PHYS	0x0C000000
+#define PXA_CS4_PHYS	0x10000000
+#define PXA_CS5_PHYS	0x14000000
+#endif /* CONFIG_CPU_MONAHANS */
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) sockets
+ */
+#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
+#define PCMCIASp	(4*PCMCIAPrtSp) /* PCMCIA Space [byte]		   */
+#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]	   */
+#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
+#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */
+
+#ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */
+#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]	   */
+#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */
+#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
+#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]	   */
+#endif
+
+#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]	   */
+#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */
+#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
+#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]	   */
+
+#define _PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
+			(0x20000000 + (Nb)*PCMCIASp)
+#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]		   */
+#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]	   */ \
+			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
+#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]		   */ \
+			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
+
+#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0			   */
+#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O			   */
+#define _PCMCIA0Attr	_PCMCIAAttr (0) /* PCMCIA 0 Attribute		   */
+#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory		   */
+
+#ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */
+#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1			   */
+#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O			   */
+#define _PCMCIA1Attr	_PCMCIAAttr (1) /* PCMCIA 1 Attribute		   */
+#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory		   */
+#endif
+
+/*
+ * DMA Controller
+ */
+#define DCSR0		0x40000000  /* DMA Control / Status Register for Channel 0 */
+#define DCSR1		0x40000004  /* DMA Control / Status Register for Channel 1 */
+#define DCSR2		0x40000008  /* DMA Control / Status Register for Channel 2 */
+#define DCSR3		0x4000000c  /* DMA Control / Status Register for Channel 3 */
+#define DCSR4		0x40000010  /* DMA Control / Status Register for Channel 4 */
+#define DCSR5		0x40000014  /* DMA Control / Status Register for Channel 5 */
+#define DCSR6		0x40000018  /* DMA Control / Status Register for Channel 6 */
+#define DCSR7		0x4000001c  /* DMA Control / Status Register for Channel 7 */
+#define DCSR8		0x40000020  /* DMA Control / Status Register for Channel 8 */
+#define DCSR9		0x40000024  /* DMA Control / Status Register for Channel 9 */
+#define DCSR10		0x40000028  /* DMA Control / Status Register for Channel 10 */
+#define DCSR11		0x4000002c  /* DMA Control / Status Register for Channel 11 */
+#define DCSR12		0x40000030  /* DMA Control / Status Register for Channel 12 */
+#define DCSR13		0x40000034  /* DMA Control / Status Register for Channel 13 */
+#define DCSR14		0x40000038  /* DMA Control / Status Register for Channel 14 */
+#define DCSR15		0x4000003c  /* DMA Control / Status Register for Channel 15 */
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define DCSR16		0x40000040  /* DMA Control / Status Register for Channel 16 */
+#define DCSR17		0x40000044  /* DMA Control / Status Register for Channel 17 */
+#define DCSR18		0x40000048  /* DMA Control / Status Register for Channel 18 */
+#define DCSR19		0x4000004c  /* DMA Control / Status Register for Channel 19 */
+#define DCSR20		0x40000050  /* DMA Control / Status Register for Channel 20 */
+#define DCSR21		0x40000054  /* DMA Control / Status Register for Channel 21 */
+#define DCSR22		0x40000058  /* DMA Control / Status Register for Channel 22 */
+#define DCSR23		0x4000005c  /* DMA Control / Status Register for Channel 23 */
+#define DCSR24		0x40000060  /* DMA Control / Status Register for Channel 24 */
+#define DCSR25		0x40000064  /* DMA Control / Status Register for Channel 25 */
+#define DCSR26		0x40000068  /* DMA Control / Status Register for Channel 26 */
+#define DCSR27		0x4000006c  /* DMA Control / Status Register for Channel 27 */
+#define DCSR28		0x40000070  /* DMA Control / Status Register for Channel 28 */
+#define DCSR29		0x40000074  /* DMA Control / Status Register for Channel 29 */
+#define DCSR30		0x40000078  /* DMA Control / Status Register for Channel 30 */
+#define DCSR31		0x4000007c  /* DMA Control / Status Register for Channel 31 */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+#define DCSR(x)		(0x40000000 | ((x) << 2))
+
+#define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
+#define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define DCSR_EORIRQEN	(1 << 28)	/* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN	(1 << 27)	/* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN	(1 << 26)	/* STOP on an EOR */
+#define DCSR_SETCMPST	(1 << 25)	/* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST	(1 << 24)	/* Clear Descriptor Compare Status */
+#define DCSR_CMPST	(1 << 10)	/* The Descriptor Compare Status */
+#define DCSR_ENRINTR	(1 << 9)	/* The end of Receive */
+#endif
+
+#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
+#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
+#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
+#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
+#define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */
+
+#define DINT		0x400000f0  /* DMA Interrupt Register */
+
+#define DRCMR0		0x40000100  /* Request to Channel Map Register for DREQ 0 */
+#define DRCMR1		0x40000104  /* Request to Channel Map Register for DREQ 1 */
+#define DRCMR2		0x40000108  /* Request to Channel Map Register for I2S receive Request */
+#define DRCMR3		0x4000010c  /* Request to Channel Map Register for I2S transmit Request */
+#define DRCMR4		0x40000110  /* Request to Channel Map Register for BTUART receive Request */
+#define DRCMR5		0x40000114  /* Request to Channel Map Register for BTUART transmit Request. */
+#define DRCMR6		0x40000118  /* Request to Channel Map Register for FFUART receive Request */
+#define DRCMR7		0x4000011c  /* Request to Channel Map Register for FFUART transmit Request */
+#define DRCMR8		0x40000120  /* Request to Channel Map Register for AC97 microphone Request */
+#define DRCMR9		0x40000124  /* Request to Channel Map Register for AC97 modem receive Request */
+#define DRCMR10		0x40000128  /* Request to Channel Map Register for AC97 modem transmit Request */
+#define DRCMR11		0x4000012c  /* Request to Channel Map Register for AC97 audio receive Request */
+#define DRCMR12		0x40000130  /* Request to Channel Map Register for AC97 audio transmit Request */
+#define DRCMR13		0x40000134  /* Request to Channel Map Register for SSP receive Request */
+#define DRCMR14		0x40000138  /* Request to Channel Map Register for SSP transmit Request */
+#define DRCMR15		0x4000013c  /* Reserved */
+#define DRCMR16		0x40000140  /* Reserved */
+#define DRCMR17		0x40000144  /* Request to Channel Map Register for ICP receive Request */
+#define DRCMR18		0x40000148  /* Request to Channel Map Register for ICP transmit Request */
+#define DRCMR19		0x4000014c  /* Request to Channel Map Register for STUART receive Request */
+#define DRCMR20		0x40000150  /* Request to Channel Map Register for STUART transmit Request */
+#define DRCMR21		0x40000154  /* Request to Channel Map Register for MMC receive Request */
+#define DRCMR22		0x40000158  /* Request to Channel Map Register for MMC transmit Request */
+#define DRCMR23		0x4000015c  /* Reserved */
+#define DRCMR24		0x40000160  /* Reserved */
+#define DRCMR25		0x40000164  /* Request to Channel Map Register for USB endpoint 1 Request */
+#define DRCMR26		0x40000168  /* Request to Channel Map Register for USB endpoint 2 Request */
+#define DRCMR27		0x4000016C  /* Request to Channel Map Register for USB endpoint 3 Request */
+#define DRCMR28		0x40000170  /* Request to Channel Map Register for USB endpoint 4 Request */
+#define DRCMR29		0x40000174  /* Reserved */
+#define DRCMR30		0x40000178  /* Request to Channel Map Register for USB endpoint 6 Request */
+#define DRCMR31		0x4000017C  /* Request to Channel Map Register for USB endpoint 7 Request */
+#define DRCMR32		0x40000180  /* Request to Channel Map Register for USB endpoint 8 Request */
+#define DRCMR33		0x40000184  /* Request to Channel Map Register for USB endpoint 9 Request */
+#define DRCMR34		0x40000188  /* Reserved */
+#define DRCMR35		0x4000018C  /* Request to Channel Map Register for USB endpoint 11 Request */
+#define DRCMR36		0x40000190  /* Request to Channel Map Register for USB endpoint 12 Request */
+#define DRCMR37		0x40000194  /* Request to Channel Map Register for USB endpoint 13 Request */
+#define DRCMR38		0x40000198  /* Request to Channel Map Register for USB endpoint 14 Request */
+#define DRCMR39		0x4000019C  /* Reserved */
+
+#define DRCMR68		       0x40001110  /* Request to Channel Map Register for Camera FIFO 0 Request */
+#define DRCMR69		       0x40001114  /* Request to Channel Map Register for Camera FIFO 1 Request */
+#define DRCMR70		       0x40001118  /* Request to Channel Map Register for Camera FIFO 2 Request */
+
+#define DRCMRRXSADR	DRCMR2
+#define DRCMRTXSADR	DRCMR3
+#define DRCMRRXBTRBR	DRCMR4
+#define DRCMRTXBTTHR	DRCMR5
+#define DRCMRRXFFRBR	DRCMR6
+#define DRCMRTXFFTHR	DRCMR7
+#define DRCMRRXMCDR	DRCMR8
+#define DRCMRRXMODR	DRCMR9
+#define DRCMRTXMODR	DRCMR10
+#define DRCMRRXPCDR	DRCMR11
+#define DRCMRTXPCDR	DRCMR12
+#define DRCMRRXSSDR	DRCMR13
+#define DRCMRTXSSDR	DRCMR14
+#define DRCMRRXICDR	DRCMR17
+#define DRCMRTXICDR	DRCMR18
+#define DRCMRRXSTRBR	DRCMR19
+#define DRCMRTXSTTHR	DRCMR20
+#define DRCMRRXMMC	DRCMR21
+#define DRCMRTXMMC	DRCMR22
+
+#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
+#define DRCMR_CHLNUM	0x0f		/* mask for Channel Number (read / write) */
+
+#define DDADR0		0x40000200  /* DMA Descriptor Address Register Channel 0 */
+#define DSADR0		0x40000204  /* DMA Source Address Register Channel 0 */
+#define DTADR0		0x40000208  /* DMA Target Address Register Channel 0 */
+#define DCMD0		0x4000020c  /* DMA Command Address Register Channel 0 */
+#define DDADR1		0x40000210  /* DMA Descriptor Address Register Channel 1 */
+#define DSADR1		0x40000214  /* DMA Source Address Register Channel 1 */
+#define DTADR1		0x40000218  /* DMA Target Address Register Channel 1 */
+#define DCMD1		0x4000021c  /* DMA Command Address Register Channel 1 */
+#define DDADR2		0x40000220  /* DMA Descriptor Address Register Channel 2 */
+#define DSADR2		0x40000224  /* DMA Source Address Register Channel 2 */
+#define DTADR2		0x40000228  /* DMA Target Address Register Channel 2 */
+#define DCMD2		0x4000022c  /* DMA Command Address Register Channel 2 */
+#define DDADR3		0x40000230  /* DMA Descriptor Address Register Channel 3 */
+#define DSADR3		0x40000234  /* DMA Source Address Register Channel 3 */
+#define DTADR3		0x40000238  /* DMA Target Address Register Channel 3 */
+#define DCMD3		0x4000023c  /* DMA Command Address Register Channel 3 */
+#define DDADR4		0x40000240  /* DMA Descriptor Address Register Channel 4 */
+#define DSADR4		0x40000244  /* DMA Source Address Register Channel 4 */
+#define DTADR4		0x40000248  /* DMA Target Address Register Channel 4 */
+#define DCMD4		0x4000024c  /* DMA Command Address Register Channel 4 */
+#define DDADR5		0x40000250  /* DMA Descriptor Address Register Channel 5 */
+#define DSADR5		0x40000254  /* DMA Source Address Register Channel 5 */
+#define DTADR5		0x40000258  /* DMA Target Address Register Channel 5 */
+#define DCMD5		0x4000025c  /* DMA Command Address Register Channel 5 */
+#define DDADR6		0x40000260  /* DMA Descriptor Address Register Channel 6 */
+#define DSADR6		0x40000264  /* DMA Source Address Register Channel 6 */
+#define DTADR6		0x40000268  /* DMA Target Address Register Channel 6 */
+#define DCMD6		0x4000026c  /* DMA Command Address Register Channel 6 */
+#define DDADR7		0x40000270  /* DMA Descriptor Address Register Channel 7 */
+#define DSADR7		0x40000274  /* DMA Source Address Register Channel 7 */
+#define DTADR7		0x40000278  /* DMA Target Address Register Channel 7 */
+#define DCMD7		0x4000027c  /* DMA Command Address Register Channel 7 */
+#define DDADR8		0x40000280  /* DMA Descriptor Address Register Channel 8 */
+#define DSADR8		0x40000284  /* DMA Source Address Register Channel 8 */
+#define DTADR8		0x40000288  /* DMA Target Address Register Channel 8 */
+#define DCMD8		0x4000028c  /* DMA Command Address Register Channel 8 */
+#define DDADR9		0x40000290  /* DMA Descriptor Address Register Channel 9 */
+#define DSADR9		0x40000294  /* DMA Source Address Register Channel 9 */
+#define DTADR9		0x40000298  /* DMA Target Address Register Channel 9 */
+#define DCMD9		0x4000029c  /* DMA Command Address Register Channel 9 */
+#define DDADR10		0x400002a0  /* DMA Descriptor Address Register Channel 10 */
+#define DSADR10		0x400002a4  /* DMA Source Address Register Channel 10 */
+#define DTADR10		0x400002a8  /* DMA Target Address Register Channel 10 */
+#define DCMD10		0x400002ac  /* DMA Command Address Register Channel 10 */
+#define DDADR11		0x400002b0  /* DMA Descriptor Address Register Channel 11 */
+#define DSADR11		0x400002b4  /* DMA Source Address Register Channel 11 */
+#define DTADR11		0x400002b8  /* DMA Target Address Register Channel 11 */
+#define DCMD11		0x400002bc  /* DMA Command Address Register Channel 11 */
+#define DDADR12		0x400002c0  /* DMA Descriptor Address Register Channel 12 */
+#define DSADR12		0x400002c4  /* DMA Source Address Register Channel 12 */
+#define DTADR12		0x400002c8  /* DMA Target Address Register Channel 12 */
+#define DCMD12		0x400002cc  /* DMA Command Address Register Channel 12 */
+#define DDADR13		0x400002d0  /* DMA Descriptor Address Register Channel 13 */
+#define DSADR13		0x400002d4  /* DMA Source Address Register Channel 13 */
+#define DTADR13		0x400002d8  /* DMA Target Address Register Channel 13 */
+#define DCMD13		0x400002dc  /* DMA Command Address Register Channel 13 */
+#define DDADR14		0x400002e0  /* DMA Descriptor Address Register Channel 14 */
+#define DSADR14		0x400002e4  /* DMA Source Address Register Channel 14 */
+#define DTADR14		0x400002e8  /* DMA Target Address Register Channel 14 */
+#define DCMD14		0x400002ec  /* DMA Command Address Register Channel 14 */
+#define DDADR15		0x400002f0  /* DMA Descriptor Address Register Channel 15 */
+#define DSADR15		0x400002f4  /* DMA Source Address Register Channel 15 */
+#define DTADR15		0x400002f8  /* DMA Target Address Register Channel 15 */
+#define DCMD15		0x400002fc  /* DMA Command Address Register Channel 15 */
+
+#define DDADR(x)	(0x40000200 | ((x) << 4))
+#define DSADR(x)	(0x40000204 | ((x) << 4))
+#define DTADR(x)	(0x40000208 | ((x) << 4))
+#define DCMD(x)		(0x4000020c | ((x) << 4))
+
+#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
+#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
+
+#define DCMD_INCSRCADDR (1 << 31)	/* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR (1 << 30)	/* Target Address Increment Setting. */
+#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
+#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
+#define DCMD_STARTIRQEN (1 << 22)	/* Start Interrupt Enable */
+#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
+#define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
+#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
+#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
+#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
+#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
+#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
+#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
+
+/* default combinations */
+#define DCMD_RXPCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
+#define DCMD_RXMCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
+#define DCMD_TXPCDR	(DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
+
+/******************************************************************************/
+/*
+ * IrSR (Infrared Selection Register)
+ */
+#define IrSR_OFFSET 0x20
+
+#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
+#define IrSR_RXPL_POS_IS_ZERO 0x0
+#define IrSR_TXPL_NEG_IS_ZERO (1<<3)
+#define IrSR_TXPL_POS_IS_ZERO 0x0
+#define IrSR_XMODE_PULSE_1_6  (1<<2)
+#define IrSR_XMODE_PULSE_3_16 0x0
+#define IrSR_RCVEIR_IR_MODE   (1<<1)
+#define IrSR_RCVEIR_UART_MODE 0x0
+#define IrSR_XMITIR_IR_MODE   (1<<0)
+#define IrSR_XMITIR_UART_MODE 0x0
+
+#define IrSR_IR_RECEIVE_ON (\
+		IrSR_RXPL_NEG_IS_ZERO | \
+		IrSR_TXPL_POS_IS_ZERO | \
+		IrSR_XMODE_PULSE_3_16 | \
+		IrSR_RCVEIR_IR_MODE   | \
+		IrSR_XMITIR_UART_MODE)
+
+#define IrSR_IR_TRANSMIT_ON (\
+		IrSR_RXPL_NEG_IS_ZERO | \
+		IrSR_TXPL_POS_IS_ZERO | \
+		IrSR_XMODE_PULSE_3_16 | \
+		IrSR_RCVEIR_UART_MODE | \
+		IrSR_XMITIR_IR_MODE)
+
+/*
+ * Serial Audio Controller
+ */
+/* FIXME the audio defines collide w/ the SA1111 defines.  I don't like these
+ * short defines because there is too much chance of namespace collision
+ */
+#define SACR0		0x40400000  /*  Global Control Register */
+#define SACR1		0x40400004  /*  Serial Audio I 2 S/MSB-Justified Control Register */
+#define SASR0		0x4040000C  /*  Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+#define SAIMR		0x40400014  /*  Serial Audio Interrupt Mask Register */
+#define SAICR		0x40400018  /*  Serial Audio Interrupt Clear Register */
+#define SADIV		0x40400060  /*  Audio Clock Divider Register. */
+#define SADR		0x40400080  /*  Serial Audio Data Register (TX and RX FIFO access Register). */
+
+/*
+ * AC97 Controller registers
+ */
+#define POCR		0x40500000  /* PCM Out Control Register */
+#define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
+
+#define PICR		0x40500004  /* PCM In Control Register */
+#define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
+
+#define MCCR		0x40500008  /* Mic In Control Register */
+#define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
+
+#define GCR		0x4050000C  /* Global Control Register */
+#define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */
+#define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */
+#define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */
+#define GCR_PRIRDY_IEN	(1 << 8)	/* Primary Ready Interrupt Enable */
+#define GCR_SECRES_IEN	(1 << 5)	/* Secondary Resume Interrupt Enable */
+#define GCR_PRIRES_IEN	(1 << 4)	/* Primary Resume Interrupt Enable */
+#define GCR_ACLINK_OFF	(1 << 3)	/* AC-link Shut Off */
+#define GCR_WARM_RST	(1 << 2)	/* AC97 Warm Reset */
+#define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
+#define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */
+
+#define POSR		0x40500010  /* PCM Out Status Register */
+#define POSR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define PISR		0x40500014  /* PCM In Status Register */
+#define PISR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define MCSR		0x40500018  /* Mic In Status Register */
+#define MCSR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define GSR		0x4050001C  /* Global Status Register */
+#define GSR_CDONE	(1 << 19)	/* Command Done */
+#define GSR_SDONE	(1 << 18)	/* Status Done */
+#define GSR_RDCS	(1 << 15)	/* Read Completion Status */
+#define GSR_BIT3SLT12	(1 << 14)	/* Bit 3 of slot 12 */
+#define GSR_BIT2SLT12	(1 << 13)	/* Bit 2 of slot 12 */
+#define GSR_BIT1SLT12	(1 << 12)	/* Bit 1 of slot 12 */
+#define GSR_SECRES	(1 << 11)	/* Secondary Resume Interrupt */
+#define GSR_PRIRES	(1 << 10)	/* Primary Resume Interrupt */
+#define GSR_SCR		(1 << 9)	/* Secondary Codec Ready */
+#define GSR_PCR		(1 << 8)	/*  Primary Codec Ready */
+#define GSR_MINT	(1 << 7)	/* Mic In Interrupt */
+#define GSR_POINT	(1 << 6)	/* PCM Out Interrupt */
+#define GSR_PIINT	(1 << 5)	/* PCM In Interrupt */
+#define GSR_MOINT	(1 << 2)	/* Modem Out Interrupt */
+#define GSR_MIINT	(1 << 1)	/* Modem In Interrupt */
+#define GSR_GSCI	(1 << 0)	/* Codec GPI Status Change Interrupt */
+
+#define CAR		0x40500020  /* CODEC Access Register */
+#define CAR_CAIP	(1 << 0)	/* Codec Access In Progress */
+
+#define PCDR		0x40500040  /* PCM FIFO Data Register */
+#define MCDR		0x40500060  /* Mic-in FIFO Data Register */
+
+#define MOCR		0x40500100  /* Modem Out Control Register */
+#define MOCR_FEIE	(1 << 3)	/* FIFO Error */
+
+#define MICR		0x40500108  /* Modem In Control Register */
+#define MICR_FEIE	(1 << 3)	/* FIFO Error */
+
+#define MOSR		0x40500110  /* Modem Out Status Register */
+#define MOSR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define MISR		0x40500118  /* Modem In Status Register */
+#define MISR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define MODR		0x40500140  /* Modem FIFO Data Register */
+
+#define PAC_REG_BASE	0x40500200  /* Primary Audio Codec */
+#define SAC_REG_BASE	0x40500300  /* Secondary Audio Codec */
+#define PMC_REG_BASE	0x40500400  /* Primary Modem Codec */
+#define SMC_REG_BASE	0x40500500  /* Secondary Modem Codec */
+
+
+/*
+ * USB Device Controller
+ */
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+
+#define UDCCR		0x40600000	/* UDC Control Register */
+#define UDCCR_UDE	(1 << 0)		/* UDC enable */
+#define UDCCR_UDA	(1 << 1)		/* UDC active */
+#define UDCCR_RSM	(1 << 2)		/* Device resume */
+#define UDCCR_EMCE	(1 << 3)		/* Endpoint Memory Configuration Error */
+#define UDCCR_SMAC	(1 << 4)		/* Switch Endpoint Memory to Active Configuration */
+#define UDCCR_RESIR	(1 << 29)		/* Resume interrupt request */
+#define UDCCR_SUSIR	(1 << 28)		/* Suspend interrupt request */
+#define UDCCR_SM	(1 << 28)		/* Suspend interrupt mask */
+#define UDCCR_RSTIR	(1 << 27)		/* Reset interrupt request */
+#define UDCCR_REM	(1 << 27)		/* Reset interrupt mask */
+#define UDCCR_RM	(1 << 29)		/* resume interrupt mask */
+#define UDCCR_SRM	(UDCCR_SM|UDCCR_RM)
+#define UDCCR_OEN	(1 << 31)		/* On-the-Go Enable */
+#define UDCCR_AALTHNP	(1 << 30)		/* A-device Alternate Host Negotiation Protocol Port Support */
+#define UDCCR_AHNP	(1 << 29)		/* A-device Host Negotiation Protocol Support */
+#define UDCCR_BHNP	(1 << 28)		/* B-device Host Negotiation Protocol Enable */
+#define UDCCR_DWRE	(1 << 16)		/* Device Remote Wake-up Enable */
+#define UDCCR_ACN	(0x03 << 11)		/* Active UDC configuration Number */
+#define UDCCR_ACN_S	11
+#define UDCCR_AIN	(0x07 << 8)		/* Active UDC interface Number */
+#define UDCCR_AIN_S	8
+#define UDCCR_AAISN	(0x07 << 5)		/* Active UDC Alternate Interface  Setting Number */
+#define UDCCR_AAISN_S	5
+
+#define UDCCS0		0x40600100	/* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0_OPR	(1 << 0)		/* OUT packet ready */
+#define UDCCS0_IPR	(1 << 1)		/* IN packet ready */
+#define UDCCS0_FTF	(1 << 2)		/* Flush Tx FIFO */
+#define UDCCS0_DRWF	(1 << 16)		/* Device remote wakeup feature */
+#define UDCCS0_SST	(1 << 4)		/* Sent stall */
+#define UDCCS0_FST	(1 << 5)		/* Force stall */
+#define UDCCS0_RNE	(1 << 6)		/* Receive FIFO no empty */
+#define UDCCS0_SA	(1 << 7)		/* Setup active */
+
+/* Bulk IN - Endpoint 1,6,11 */
+#define UDCCS1		0x40600104  /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6		0x40600028  /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11		0x4060003C  /* UDC Endpoint 11 (IN) Control/Status Register */
+
+#define UDCCS_BI_TFS	(1 << 0)	/* Transmit FIFO service */
+#define UDCCS_BI_TPC	(1 << 1)	/* Transmit packet complete */
+#define UDCCS_BI_FTF	(1 << 8)	/* Flush Tx FIFO */
+#define UDCCS_BI_TUR	(1 << 3)	/* Transmit FIFO underrun */
+#define UDCCS_BI_SST	(1 << 4)	/* Sent stall */
+#define UDCCS_BI_FST	(1 << 5)	/* Force stall */
+#define UDCCS_BI_TSP	(1 << 7)	/* Transmit short packet */
+
+/* Bulk OUT - Endpoint 2,7,12 */
+#define UDCCS2		0x40600108  /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7		0x4060002C  /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12		0x40600040  /* UDC Endpoint 12 (OUT) Control/Status Register */
+
+#define UDCCS_BO_RFS	(1 << 0)	/* Receive FIFO service */
+#define UDCCS_BO_RPC	(1 << 1)	/* Receive packet complete */
+#define UDCCS_BO_DME	(1 << 3)	/* DMA enable */
+#define UDCCS_BO_SST	(1 << 4)	/* Sent stall */
+#define UDCCS_BO_FST	(1 << 5)	/* Force stall */
+#define UDCCS_BO_RNE	(1 << 6)	/* Receive FIFO not empty */
+#define UDCCS_BO_RSP	(1 << 7)	/* Receive short packet */
+
+/* Isochronous IN - Endpoint 3,8,13 */
+#define UDCCS3		0x4060001C  /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8		0x40600030  /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13		0x40600044  /* UDC Endpoint 13 (IN) Control/Status Register */
+
+#define UDCCS_II_TFS	(1 << 0)	/* Transmit FIFO service */
+#define UDCCS_II_TPC	(1 << 1)	/* Transmit packet complete */
+#define UDCCS_II_FTF	(1 << 2)	/* Flush Tx FIFO */
+#define UDCCS_II_TUR	(1 << 3)	/* Transmit FIFO underrun */
+#define UDCCS_II_TSP	(1 << 7)	/* Transmit short packet */
+
+/* Isochronous OUT - Endpoint 4,9,14 */
+#define UDCCS4		0x40600020  /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9		0x40600034  /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14		0x40600048  /* UDC Endpoint 14 (OUT) Control/Status Register */
+
+#define UDCCS_IO_RFS	(1 << 0)	/* Receive FIFO service */
+#define UDCCS_IO_RPC	(1 << 1)	/* Receive packet complete */
+#define UDCCS_IO_ROF	(1 << 3)	/* Receive overflow */
+#define UDCCS_IO_DME	(1 << 3)	/* DMA enable */
+#define UDCCS_IO_RNE	(1 << 6)	/* Receive FIFO not empty */
+#define UDCCS_IO_RSP	(1 << 7)	/* Receive short packet */
+
+/* Interrupt IN - Endpoint 5,10,15 */
+#define UDCCS5		0x40600024  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10		0x40600038  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15		0x4060004C  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+
+#define UDCCS_INT_TFS	(1 << 0)	/* Transmit FIFO service */
+#define UDCCS_INT_TPC	(1 << 1)	/* Transmit packet complete */
+#define UDCCS_INT_FTF	(1 << 2)	/* Flush Tx FIFO */
+#define UDCCS_INT_TUR	(1 << 3)	/* Transmit FIFO underrun */
+#define UDCCS_INT_SST	(1 << 4)	/* Sent stall */
+#define UDCCS_INT_FST	(1 << 5)	/* Force stall */
+#define UDCCS_INT_TSP	(1 << 7)	/* Transmit short packet */
+
+#define UFNRH		0x40600060  /* UDC Frame Number Register High */
+#define UFNRL		0x40600014  /* UDC Frame Number Register Low */
+#define UBCR2		0x40600208  /* UDC Byte Count Reg 2 */
+#define UBCR4		0x4060006c  /* UDC Byte Count Reg 4 */
+#define UBCR7		0x40600070  /* UDC Byte Count Reg 7 */
+#define UBCR9		0x40600074  /* UDC Byte Count Reg 9 */
+#define UBCR12		0x40600078  /* UDC Byte Count Reg 12 */
+#define UBCR14		0x4060007c  /* UDC Byte Count Reg 14 */
+#define UDDR0		0x40600300  /* UDC Endpoint 0 Data Register */
+#define UDDR1		0x40600304  /* UDC Endpoint 1 Data Register */
+#define UDDR2		0x40600308  /* UDC Endpoint 2 Data Register */
+#define UDDR3		0x40600200  /* UDC Endpoint 3 Data Register */
+#define UDDR4		0x40600400  /* UDC Endpoint 4 Data Register */
+#define UDDR5		0x406000A0  /* UDC Endpoint 5 Data Register */
+#define UDDR6		0x40600600  /* UDC Endpoint 6 Data Register */
+#define UDDR7		0x40600680  /* UDC Endpoint 7 Data Register */
+#define UDDR8		0x40600700  /* UDC Endpoint 8 Data Register */
+#define UDDR9		0x40600900  /* UDC Endpoint 9 Data Register */
+#define UDDR10		0x406000C0  /* UDC Endpoint 10 Data Register */
+#define UDDR11		0x40600B00  /* UDC Endpoint 11 Data Register */
+#define UDDR12		0x40600B80  /* UDC Endpoint 12 Data Register */
+#define UDDR13		0x40600C00  /* UDC Endpoint 13 Data Register */
+#define UDDR14		0x40600E00  /* UDC Endpoint 14 Data Register */
+#define UDDR15		0x406000E0  /* UDC Endpoint 15 Data Register */
+
+#define UICR0		0x40600004  /* UDC Interrupt Control Register 0 */
+
+#define UICR0_IM0	(1 << 0)	/* Interrupt mask ep 0 */
+#define UICR0_IM1	(1 << 1)	/* Interrupt mask ep 1 */
+#define UICR0_IM2	(1 << 2)	/* Interrupt mask ep 2 */
+#define UICR0_IM3	(1 << 3)	/* Interrupt mask ep 3 */
+#define UICR0_IM4	(1 << 4)	/* Interrupt mask ep 4 */
+#define UICR0_IM5	(1 << 5)	/* Interrupt mask ep 5 */
+#define UICR0_IM6	(1 << 6)	/* Interrupt mask ep 6 */
+#define UICR0_IM7	(1 << 7)	/* Interrupt mask ep 7 */
+
+#define UICR1		0x40600008  /* UDC Interrupt Control Register 1 */
+
+#define UICR1_IM8	(1 << 0)	/* Interrupt mask ep 8 */
+#define UICR1_IM9	(1 << 1)	/* Interrupt mask ep 9 */
+#define UICR1_IM10	(1 << 2)	/* Interrupt mask ep 10 */
+#define UICR1_IM11	(1 << 3)	/* Interrupt mask ep 11 */
+#define UICR1_IM12	(1 << 4)	/* Interrupt mask ep 12 */
+#define UICR1_IM13	(1 << 5)	/* Interrupt mask ep 13 */
+#define UICR1_IM14	(1 << 6)	/* Interrupt mask ep 14 */
+#define UICR1_IM15	(1 << 7)	/* Interrupt mask ep 15 */
+
+#define USIR0		0x4060000C  /* UDC Status Interrupt Register 0 */
+
+#define USIR0_IR0	(1 << 0)	/* Interrup request ep 0 */
+#define USIR0_IR1	(1 << 2)	/* Interrup request ep 1 */
+#define USIR0_IR2	(1 << 4)	/* Interrup request ep 2 */
+#define USIR0_IR3	(1 << 3)	/* Interrup request ep 3 */
+#define USIR0_IR4	(1 << 4)	/* Interrup request ep 4 */
+#define USIR0_IR5	(1 << 5)	/* Interrup request ep 5 */
+#define USIR0_IR6	(1 << 6)	/* Interrup request ep 6 */
+#define USIR0_IR7	(1 << 7)	/* Interrup request ep 7 */
+
+#define USIR1		0x40600010  /* UDC Status Interrupt Register 1 */
+
+#define USIR1_IR8	(1 << 0)	/* Interrup request ep 8 */
+#define USIR1_IR9	(1 << 1)	/* Interrup request ep 9 */
+#define USIR1_IR10	(1 << 2)	/* Interrup request ep 10 */
+#define USIR1_IR11	(1 << 3)	/* Interrup request ep 11 */
+#define USIR1_IR12	(1 << 4)	/* Interrup request ep 12 */
+#define USIR1_IR13	(1 << 5)	/* Interrup request ep 13 */
+#define USIR1_IR14	(1 << 6)	/* Interrup request ep 14 */
+#define USIR1_IR15	(1 << 7)	/* Interrup request ep 15 */
+
+
+#define UDCICR0         0x40600004	/* UDC Interrupt Control Register0 */
+#define UDCICR1         0x40600008	/* UDC Interrupt Control Register1 */
+#define UDCICR_FIFOERR	(1 << 1)			/* FIFO Error interrupt for EP */
+#define UDCICR_PKTCOMPL (1 << 0)			/* Packet Complete interrupt for EP */
+
+#define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCICR1_IECC	(1 << 31)	/* IntEn - Configuration Change */
+#define UDCICR1_IESOF	(1 << 30)	/* IntEn - Start of Frame */
+#define UDCICR1_IERU	(1 << 29)	/* IntEn - Resume */
+#define UDCICR1_IESU	(1 << 28)	/* IntEn - Suspend */
+#define UDCICR1_IERS	(1 << 27)	/* IntEn - Reset */
+
+#define UDCISR0         0x4060000C /* UDC Interrupt Status Register 0 */
+#define UDCISR1         0x40600010 /* UDC Interrupt Status Register 1 */
+#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCISR1_IRCC	(1 << 31)	/* IntEn - Configuration Change */
+#define UDCISR1_IRSOF	(1 << 30)	/* IntEn - Start of Frame */
+#define UDCISR1_IRRU	(1 << 29)	/* IntEn - Resume */
+#define UDCISR1_IRSU	(1 << 28)	/* IntEn - Suspend */
+#define UDCISR1_IRRS	(1 << 27)	/* IntEn - Reset */
+
+
+#define UDCFNR			0x40600014 /* UDC Frame Number Register */
+#define UDCOTGICR		0x40600018 /* UDC On-The-Go interrupt control */
+#define UDCOTGICR_IESF		(1 << 24)	/* OTG SET_FEATURE command recvd */
+#define UDCOTGICR_IEXR		(1 << 17)	/* Extra Transciever Interrupt Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEXF		(1 << 16)	/* Extra Transciever Interrupt Falling Edge Interrupt Enable */
+#define UDCOTGICR_IEVV40R	(1 << 9)	/* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEVV40F	(1 << 8)	/* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */
+#define UDCOTGICR_IEVV44R	(1 << 7)	/* OTG Vbus Valid 4.4V Rising Edge  Interrupt Enable */
+#define UDCOTGICR_IEVV44F	(1 << 6)	/* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */
+#define UDCOTGICR_IESVR		(1 << 5)	/* OTG Session Valid Rising Edge Interrupt Enable */
+#define UDCOTGICR_IESVF		(1 << 4)	/* OTG Session Valid Falling Edge Interrupt Enable */
+#define UDCOTGICR_IESDR		(1 << 3)	/* OTG A-Device SRP Detect Rising Edge Interrupt Enable */
+#define UDCOTGICR_IESDF		(1 << 2)	/* OTG A-Device SRP Detect Falling  Edge Interrupt Enable */
+#define UDCOTGICR_IEIDR		(1 << 1)	/* OTG ID Change Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEIDF		(1 << 0)	/* OTG ID Change Falling Edge Interrupt Enable */
+
+#define UDCCSN(x)	(0x40600100 + ((x) << 2))
+#define UDCCSR0		0x40600100 /* UDC Control/Status register - Endpoint 0 */
+
+#define UDCCSR0_SA	(1 << 7)	/* Setup Active */
+#define UDCCSR0_RNE	(1 << 6)	/* Receive FIFO Not Empty */
+#define UDCCSR0_FST	(1 << 5)	/* Force Stall */
+#define UDCCSR0_SST	(1 << 4)	/* Sent Stall */
+#define UDCCSR0_DME	(1 << 3)	/* DMA Enable */
+#define UDCCSR0_FTF	(1 << 2)	/* Flush Transmit FIFO */
+#define UDCCSR0_IPR	(1 << 1)	/* IN Packet Ready */
+#define UDCCSR0_OPC	(1 << 0)	/* OUT Packet Complete */
+
+#define UDCCSRA         0x40600104 /* UDC Control/Status register - Endpoint A */
+#define UDCCSRB         0x40600108 /* UDC Control/Status register - Endpoint B */
+#define UDCCSRC         0x4060010C /* UDC Control/Status register - Endpoint C */
+#define UDCCSRD         0x40600110 /* UDC Control/Status register - Endpoint D */
+#define UDCCSRE         0x40600114 /* UDC Control/Status register - Endpoint E */
+#define UDCCSRF         0x40600118 /* UDC Control/Status register - Endpoint F */
+#define UDCCSRG         0x4060011C /* UDC Control/Status register - Endpoint G */
+#define UDCCSRH         0x40600120 /* UDC Control/Status register - Endpoint H */
+#define UDCCSRI         0x40600124 /* UDC Control/Status register - Endpoint I */
+#define UDCCSRJ         0x40600128 /* UDC Control/Status register - Endpoint J */
+#define UDCCSRK         0x4060012C /* UDC Control/Status register - Endpoint K */
+#define UDCCSRL         0x40600130 /* UDC Control/Status register - Endpoint L */
+#define UDCCSRM         0x40600134 /* UDC Control/Status register - Endpoint M */
+#define UDCCSRN         0x40600138 /* UDC Control/Status register - Endpoint N */
+#define UDCCSRP         0x4060013C /* UDC Control/Status register - Endpoint P */
+#define UDCCSRQ         0x40600140 /* UDC Control/Status register - Endpoint Q */
+#define UDCCSRR         0x40600144 /* UDC Control/Status register - Endpoint R */
+#define UDCCSRS         0x40600148 /* UDC Control/Status register - Endpoint S */
+#define UDCCSRT         0x4060014C /* UDC Control/Status register - Endpoint T */
+#define UDCCSRU         0x40600150 /* UDC Control/Status register - Endpoint U */
+#define UDCCSRV         0x40600154 /* UDC Control/Status register - Endpoint V */
+#define UDCCSRW         0x40600158 /* UDC Control/Status register - Endpoint W */
+#define UDCCSRX         0x4060015C /* UDC Control/Status register - Endpoint X */
+
+#define UDCCSR_DPE	(1 << 9)	/* Data Packet Error */
+#define UDCCSR_FEF	(1 << 8)	/* Flush Endpoint FIFO */
+#define UDCCSR_SP	(1 << 7)	/* Short Packet Control/Status */
+#define UDCCSR_BNE	(1 << 6)	/* Buffer Not Empty (IN endpoints) */
+#define UDCCSR_BNF	(1 << 6)	/* Buffer Not Full (OUT endpoints) */
+#define UDCCSR_FST	(1 << 5)	/* Force STALL */
+#define UDCCSR_SST	(1 << 4)	/* Sent STALL */
+#define UDCCSR_DME	(1 << 3)	/* DMA Enable */
+#define UDCCSR_TRN	(1 << 2)	/* Tx/Rx NAK */
+#define UDCCSR_PC	(1 << 1)	/* Packet Complete */
+#define UDCCSR_FS	(1 << 0)	/* FIFO needs service */
+
+#define UDCBCN(x)	(0x40600200 + ((x) << 2))
+#define UDCBCR0         0x40600200 /* Byte Count Register - EP0 */
+#define UDCBCRA         0x40600204 /* Byte Count Register - EPA */
+#define UDCBCRB         0x40600208 /* Byte Count Register - EPB */
+#define UDCBCRC         0x4060020C /* Byte Count Register - EPC */
+#define UDCBCRD         0x40600210 /* Byte Count Register - EPD */
+#define UDCBCRE         0x40600214 /* Byte Count Register - EPE */
+#define UDCBCRF         0x40600218 /* Byte Count Register - EPF */
+#define UDCBCRG         0x4060021C /* Byte Count Register - EPG */
+#define UDCBCRH         0x40600220 /* Byte Count Register - EPH */
+#define UDCBCRI         0x40600224 /* Byte Count Register - EPI */
+#define UDCBCRJ         0x40600228 /* Byte Count Register - EPJ */
+#define UDCBCRK         0x4060022C /* Byte Count Register - EPK */
+#define UDCBCRL         0x40600230 /* Byte Count Register - EPL */
+#define UDCBCRM         0x40600234 /* Byte Count Register - EPM */
+#define UDCBCRN         0x40600238 /* Byte Count Register - EPN */
+#define UDCBCRP         0x4060023C /* Byte Count Register - EPP */
+#define UDCBCRQ         0x40600240 /* Byte Count Register - EPQ */
+#define UDCBCRR         0x40600244 /* Byte Count Register - EPR */
+#define UDCBCRS         0x40600248 /* Byte Count Register - EPS */
+#define UDCBCRT         0x4060024C /* Byte Count Register - EPT */
+#define UDCBCRU         0x40600250 /* Byte Count Register - EPU */
+#define UDCBCRV         0x40600254 /* Byte Count Register - EPV */
+#define UDCBCRW         0x40600258 /* Byte Count Register - EPW */
+#define UDCBCRX         0x4060025C /* Byte Count Register - EPX */
+
+#define UDCDN(x)	(0x40600300 + ((x) << 2))
+#define UDCDR0          0x40600300 /* Data Register - EP0 */
+#define UDCDRA          0x40600304 /* Data Register - EPA */
+#define UDCDRB          0x40600308 /* Data Register - EPB */
+#define UDCDRC          0x4060030C /* Data Register - EPC */
+#define UDCDRD          0x40600310 /* Data Register - EPD */
+#define UDCDRE          0x40600314 /* Data Register - EPE */
+#define UDCDRF          0x40600318 /* Data Register - EPF */
+#define UDCDRG          0x4060031C /* Data Register - EPG */
+#define UDCDRH          0x40600320 /* Data Register - EPH */
+#define UDCDRI          0x40600324 /* Data Register - EPI */
+#define UDCDRJ          0x40600328 /* Data Register - EPJ */
+#define UDCDRK          0x4060032C /* Data Register - EPK */
+#define UDCDRL          0x40600330 /* Data Register - EPL */
+#define UDCDRM          0x40600334 /* Data Register - EPM */
+#define UDCDRN          0x40600338 /* Data Register - EPN */
+#define UDCDRP          0x4060033C /* Data Register - EPP */
+#define UDCDRQ          0x40600340 /* Data Register - EPQ */
+#define UDCDRR          0x40600344 /* Data Register - EPR */
+#define UDCDRS          0x40600348 /* Data Register - EPS */
+#define UDCDRT          0x4060034C /* Data Register - EPT */
+#define UDCDRU          0x40600350 /* Data Register - EPU */
+#define UDCDRV          0x40600354 /* Data Register - EPV */
+#define UDCDRW          0x40600358 /* Data Register - EPW */
+#define UDCDRX          0x4060035C /* Data Register - EPX */
+
+#define UDCCN(x)	(0x40600400 + ((x) << 2))
+#define UDCCRA          0x40600404 /* Configuration register EPA */
+#define UDCCRB          0x40600408 /* Configuration register EPB */
+#define UDCCRC          0x4060040C /* Configuration register EPC */
+#define UDCCRD          0x40600410 /* Configuration register EPD */
+#define UDCCRE          0x40600414 /* Configuration register EPE */
+#define UDCCRF          0x40600418 /* Configuration register EPF */
+#define UDCCRG          0x4060041C /* Configuration register EPG */
+#define UDCCRH          0x40600420 /* Configuration register EPH */
+#define UDCCRI          0x40600424 /* Configuration register EPI */
+#define UDCCRJ          0x40600428 /* Configuration register EPJ */
+#define UDCCRK          0x4060042C /* Configuration register EPK */
+#define UDCCRL          0x40600430 /* Configuration register EPL */
+#define UDCCRM          0x40600434 /* Configuration register EPM */
+#define UDCCRN          0x40600438 /* Configuration register EPN */
+#define UDCCRP          0x4060043C /* Configuration register EPP */
+#define UDCCRQ          0x40600440 /* Configuration register EPQ */
+#define UDCCRR          0x40600444 /* Configuration register EPR */
+#define UDCCRS          0x40600448 /* Configuration register EPS */
+#define UDCCRT          0x4060044C /* Configuration register EPT */
+#define UDCCRU          0x40600450 /* Configuration register EPU */
+#define UDCCRV          0x40600454 /* Configuration register EPV */
+#define UDCCRW          0x40600458 /* Configuration register EPW */
+#define UDCCRX          0x4060045C /* Configuration register EPX */
+
+#define UDCCONR_CN	(0x03 << 25)	/* Configuration Number */
+#define UDCCONR_CN_S	(25)
+#define UDCCONR_IN	(0x07 << 22)	/* Interface Number */
+#define UDCCONR_IN_S	(22)
+#define UDCCONR_AISN	(0x07 << 19)	/* Alternate Interface Number */
+#define UDCCONR_AISN_S	(19)
+#define UDCCONR_EN	(0x0f << 15)	/* Endpoint Number */
+#define UDCCONR_EN_S	(15)
+#define UDCCONR_ET	(0x03 << 13)	/* Endpoint Type: */
+#define UDCCONR_ET_S	(13)
+#define UDCCONR_ET_INT	(0x03 << 13)	/* Interrupt */
+#define UDCCONR_ET_BULK	(0x02 << 13)	/* Bulk */
+#define UDCCONR_ET_ISO	(0x01 << 13)	/* Isochronous */
+#define UDCCONR_ET_NU	(0x00 << 13)	/* Not used */
+#define UDCCONR_ED	(1 << 12)	/* Endpoint Direction */
+#define UDCCONR_MPS	(0x3ff << 2)	/* Maximum Packet Size */
+#define UDCCONR_MPS_S	(2)
+#define UDCCONR_DE	(1 << 1)	/* Double Buffering Enable */
+#define UDCCONR_EE	(1 << 0)	/* Endpoint Enable */
+
+
+#define UDC_INT_FIFOERROR	(0x2)
+#define UDC_INT_PACKETCMP	(0x1)
+#define UDC_FNR_MASK		(0x7ff)
+#define UDCCSR_WR_MASK		(UDCCSR_DME|UDCCSR_FST)
+#define UDC_BCR_MASK		(0x3ff)
+
+#endif /* CONFIG_CPU_PXA27X */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+
+/******************************************************************************/
+/*
+ * USB Host Controller
+ */
+#define OHCI_REGS_BASE	0x4C000000	/* required for ohci driver */
+#define UHCREV		0x4C000000
+#define UHCHCON		0x4C000004
+#define UHCCOMS		0x4C000008
+#define UHCINTS		0x4C00000C
+#define UHCINTE		0x4C000010
+#define UHCINTD		0x4C000014
+#define UHCHCCA		0x4C000018
+#define UHCPCED		0x4C00001C
+#define UHCCHED		0x4C000020
+#define UHCCCED		0x4C000024
+#define UHCBHED		0x4C000028
+#define UHCBCED		0x4C00002C
+#define UHCDHEAD	0x4C000030
+#define UHCFMI		0x4C000034
+#define UHCFMR		0x4C000038
+#define UHCFMN		0x4C00003C
+#define UHCPERS		0x4C000040
+#define UHCLST		0x4C000044
+#define UHCRHDA		0x4C000048
+#define UHCRHDB		0x4C00004C
+#define UHCRHS		0x4C000050
+#define UHCRHPS1	0x4C000054
+#define UHCRHPS2	0x4C000058
+#define UHCRHPS3	0x4C00005C
+#define UHCSTAT		0x4C000060
+#define UHCHR		0x4C000064
+#define UHCHIE		0x4C000068
+#define UHCHIT		0x4C00006C
+
+#define UHCCOMS_HCR	(1<<0)
+
+#define UHCHR_FSBIR	(1<<0)
+#define UHCHR_FHR	(1<<1)
+#define UHCHR_CGR	(1<<2)
+#define UHCHR_SSDC	(1<<3)
+#define UHCHR_UIT	(1<<4)
+#define UHCHR_SSE	(1<<5)
+#define UHCHR_PSPL	(1<<6)
+#define UHCHR_PCPL	(1<<7)
+#define UHCHR_SSEP0	(1<<9)
+#define UHCHR_SSEP1	(1<<10)
+#define UHCHR_SSEP2	(1<<11)
+
+#define UHCHIE_UPRIE	(1<<13)
+#define UHCHIE_UPS2IE	(1<<12)
+#define UHCHIE_UPS1IE	(1<<11)
+#define UHCHIE_TAIE	(1<<10)
+#define UHCHIE_HBAIE	(1<<8)
+#define UHCHIE_RWIE	(1<<7)
+
+#define UP2OCR		0x40600020
+
+#define UP2OCR_HXOE	(1<<17)
+#define UP2OCR_HXS	(1<<16)
+#define UP2OCR_IDON	(1<<10)
+#define UP2OCR_EXSUS	(1<<9)
+#define UP2OCR_EXSP	(1<<8)
+#define UP2OCR_DMSTATE	(1<<7)
+#define UP2OCR_VPM	(1<<6)
+#define UP2OCR_DPSTATE	(1<<5)
+#define UP2OCR_DPPUE	(1<<4)
+#define UP2OCR_DMPDE	(1<<3)
+#define UP2OCR_DPPDE	(1<<2)
+#define UP2OCR_CPVPE	(1<<1)
+#define UP2OCR_CPVEN	(1<<0)
+
+#endif	/* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+/******************************************************************************/
+/*
+ * Fast Infrared Communication Port
+ */
+#define ICCR0		0x40800000  /* ICP Control Register 0 */
+#define ICCR1		0x40800004  /* ICP Control Register 1 */
+#define ICCR2		0x40800008  /* ICP Control Register 2 */
+#define ICDR		0x4080000c  /* ICP Data Register */
+#define ICSR0		0x40800014  /* ICP Status Register 0 */
+#define ICSR1		0x40800018  /* ICP Status Register 1 */
+
+/*
+ * Real Time Clock
+ */
+#define RCNR		0x40900000  /* RTC Count Register */
+#define RTAR		0x40900004  /* RTC Alarm Register */
+#define RTSR		0x40900008  /* RTC Status Register */
+#define RTTR		0x4090000C  /* RTC Timer Trim Register */
+#define RDAR1		0x40900018  /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2		0x40900020  /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1		0x4090001C  /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2		0x40900024  /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1		0x4090002C  /* Stopwatch Alarm Register 1 */
+#define SWAR2		0x40900030  /* Stopwatch Alarm Register 2 */
+#define PIAR		0x40900038  /* Periodic Interrupt Alarm Register */
+#define RDCR		0x40900010  /* RTC Day Count Register. */
+#define RYCR		0x40900014  /* RTC Year Count Register. */
+#define SWCR		0x40900028  /* Stopwatch Count Register */
+#define RTCPICR		0x40900034  /* Periodic Interrupt Counter Register */
+
+#define RTSR_PICE	(1 << 15)	/* Peridoc interrupt count enable */
+#define RTSR_PIALE	(1 << 14)	/* Peridoc interrupt Alarm enable */
+#define RTSR_PIAL	(1 << 13)	/* Peridoc  interrupt Alarm status */
+#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
+#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
+#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
+#define RTSR_AL		(1 << 0)	/* RTC alarm detected */
+
+/******************************************************************************/
+/*
+ * OS Timer & Match Registers
+ */
+#define OSMR0		0x40A00000  /* OS Timer Match Register 0 */
+#define OSMR1		0x40A00004  /* OS Timer Match Register 1 */
+#define OSMR2		0x40A00008  /* OS Timer Match Register 2 */
+#define OSMR3		0x40A0000C  /* OS Timer Match Register 3 */
+#define OSCR		0x40A00010  /* OS Timer Counter Register */
+#define OSSR		0x40A00014  /* OS Timer Status Register */
+#define OWER		0x40A00018  /* OS Timer Watchdog Enable Register */
+#define OIER		0x40A0001C  /* OS Timer Interrupt Enable Register */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define OSCR4		0x40A00040  /* OS Timer Counter Register 4 */
+#define OSCR5		0x40A00044  /* OS Timer Counter Register 5 */
+#define OSCR6		0x40A00048  /* OS Timer Counter Register 6 */
+#define OSCR7		0x40A0004C  /* OS Timer Counter Register 7 */
+#define OSCR8		0x40A00050  /* OS Timer Counter Register 8 */
+#define OSCR9		0x40A00054  /* OS Timer Counter Register 9 */
+#define OSCR10		0x40A00058  /* OS Timer Counter Register 10 */
+#define OSCR11		0x40A0005C  /* OS Timer Counter Register 11 */
+
+#define OSMR4		0x40A00080  /* OS Timer Match Register 4 */
+#define OSMR5		0x40A00084  /* OS Timer Match Register 5 */
+#define OSMR6		0x40A00088  /* OS Timer Match Register 6 */
+#define OSMR7		0x40A0008C  /* OS Timer Match Register 7 */
+#define OSMR8		0x40A00090  /* OS Timer Match Register 8 */
+#define OSMR9		0x40A00094  /* OS Timer Match Register 9 */
+#define OSMR10		0x40A00098  /* OS Timer Match Register 10 */
+#define OSMR11		0x40A0009C  /* OS Timer Match Register 11 */
+
+#define OMCR4		0x40A000C0  /* OS Match Control Register 4 */
+#define OMCR5		0x40A000C4  /* OS Match Control Register 5 */
+#define OMCR6		0x40A000C8  /* OS Match Control Register 6 */
+#define OMCR7		0x40A000CC  /* OS Match Control Register 7 */
+#define OMCR8		0x40A000D0  /* OS Match Control Register 8 */
+#define OMCR9		0x40A000D4  /* OS Match Control Register 9 */
+#define OMCR10		0x40A000D8  /* OS Match Control Register 10 */
+#define OMCR11		0x40A000DC  /* OS Match Control Register 11 */
+
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+#define OSSR_M4		(1 << 4)	/* Match status channel 4 */
+#define OSSR_M3		(1 << 3)	/* Match status channel 3 */
+#define OSSR_M2		(1 << 2)	/* Match status channel 2 */
+#define OSSR_M1		(1 << 1)	/* Match status channel 1 */
+#define OSSR_M0		(1 << 0)	/* Match status channel 0 */
+
+#define OWER_WME	(1 << 0)	/* Watchdog Match Enable */
+
+#define OIER_E4		(1 << 4)	/* Interrupt enable channel 4 */
+#define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
+#define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
+#define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
+#define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */
+
+#define	OSCR_CLK_FREQ	3250
+
+/******************************************************************************/
+/*
+ * Core Clock
+ */
+
+#if defined(CONFIG_CPU_MONAHANS)
+#define ACCR		0x41340000  /* Application Subsystem Clock Configuration Register */
+#define ACSR		0x41340004  /* Application Subsystem Clock Status Register */
+#define AICSR		0x41340008  /* Application Subsystem Interrupt Control/Status Register */
+#define CKENA		0x4134000C  /* A Clock Enable Register */
+#define CKENB		0x41340010  /* B Clock Enable Register */
+#define AC97_DIV	0x41340014  /* AC97 clock divisor value register */
+
+#define ACCR_SMC_MASK	0x03800000	/* Static Memory Controller Frequency Select */
+#define ACCR_SRAM_MASK	0x000c0000	/* SRAM Controller Frequency Select */
+#define ACCR_FC_MASK	0x00030000	/* Frequency Change Frequency Select */
+#define ACCR_HSIO_MASK	0x0000c000	/* High Speed IO Frequency Select */
+#define ACCR_DDR_MASK	0x00003000	/* DDR Memory Controller Frequency Select */
+#define ACCR_XN_MASK	0x00000700	/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define ACCR_XL_MASK	0x0000001f	/* Crystal Frequency to Memory Frequency Multiplier */
+#define ACCR_XPDIS	(1 << 31)
+#define ACCR_SPDIS	(1 << 30)
+#define ACCR_13MEND1	(1 << 27)
+#define ACCR_D0CS	(1 << 26)
+#define ACCR_13MEND2	(1 << 21)
+#define ACCR_PCCE	(1 << 11)
+
+#define CKENA_30_MSL0	(1 << 30)	/* MSL0 Interface Unit Clock Enable */
+#define CKENA_29_SSP4	(1 << 29)	/* SSP3 Unit Clock Enable */
+#define CKENA_28_SSP3	(1 << 28)	/* SSP2 Unit Clock Enable */
+#define CKENA_27_SSP2	(1 << 27)	/* SSP1 Unit Clock Enable */
+#define CKENA_26_SSP1	(1 << 26)	/* SSP0 Unit Clock Enable */
+#define CKENA_25_TSI	(1 << 25)	/* TSI Clock Enable */
+#define CKENA_24_AC97	(1 << 24)	/* AC97 Unit Clock Enable */
+#define CKENA_23_STUART	(1 << 23)	/* STUART Unit Clock Enable */
+#define CKENA_22_FFUART	(1 << 22)	/* FFUART Unit Clock Enable */
+#define CKENA_21_BTUART	(1 << 21)	/* BTUART Unit Clock Enable */
+#define CKENA_20_UDC	(1 << 20)	/* UDC Clock Enable */
+#define CKENA_19_TPM	(1 << 19)	/* TPM Unit Clock Enable */
+#define CKENA_18_USIM1	(1 << 18)	/* USIM1 Unit Clock Enable */
+#define CKENA_17_USIM0	(1 << 17)	/* USIM0 Unit Clock Enable */
+#define CKENA_15_CIR	(1 << 15)	/* Consumer IR Clock Enable */
+#define CKENA_14_KEY	(1 << 14)	/* Keypad Controller Clock Enable */
+#define CKENA_13_MMC1	(1 << 13)	/* MMC1 Clock Enable */
+#define CKENA_12_MMC0	(1 << 12)	/* MMC0 Clock Enable */
+#define CKENA_11_FLASH	(1 << 11)	/* Boot ROM Clock Enable */
+#define CKENA_10_SRAM	(1 << 10)	/* SRAM Controller Clock Enable */
+#define CKENA_9_SMC	(1 << 9)	/* Static Memory Controller */
+#define CKENA_8_DMC	(1 << 8)	/* Dynamic Memory Controller */
+#define CKENA_7_GRAPHICS (1 << 7)	/* 2D Graphics Clock Enable */
+#define CKENA_6_USBCLI	(1 << 6)	/* USB Client Unit Clock Enable */
+#define CKENA_4_NAND	(1 << 4)	/* NAND Flash Controller Clock Enable */
+#define CKENA_3_CAMERA	(1 << 3)	/* Camera Interface Clock Enable */
+#define CKENA_2_USBHOST	(1 << 2)	/* USB Host Unit Clock Enable */
+#define CKENA_1_LCD	(1 << 1)	/* LCD Unit Clock Enable */
+
+#define CKENB_9_SYSBUS2	(1 << 9)	/* System bus 2 */
+#define CKENB_8_1WIRE	(1 << 8)	/* One Wire Interface Unit Clock Enable */
+#define CKENB_7_GPIO	(1 << 7)	/* GPIO Clock Enable */
+#define CKENB_6_IRQ	(1 << 6)	/* Interrupt Controller Clock Enable */
+#define CKENB_4_I2C	(1 << 4)	/* I2C Unit Clock Enable */
+#define CKENB_1_PWM1	(1 << 1)	/* PWM2 & PWM3 Clock Enable */
+#define CKENB_0_PWM0	(1 << 0)	/* PWM0 & PWM1 Clock Enable */
+
+#else /* if defined CONFIG_CPU_MONAHANS */
+
+#define CCCR		0x41300000  /* Core Clock Configuration Register */
+#define CKEN		0x41300004  /* Clock Enable Register */
+#define OSCC		0x41300008  /* Oscillator Configuration Register */
+#define CCSR		0x4130000C /* Core Clock Status Register */
+
+#define CKEN23_SSP1	(1 << 23) /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC	(1 << 22) /* Memory Controler */
+#define CKEN21_MSHC	(1 << 21) /* Memery Stick Host Controller */
+#define CKEN20_IM	(1 << 20) /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD	(1 << 19) /* Keypad Interface Clock Enable */
+#define CKEN18_USIM	(1 << 18) /* USIM Unit Clock Enable */
+#define CKEN17_MSL	(1 << 17) /* MSL Interface Unit Clock Enable */
+#define CKEN15_PWR_I2C	(1 << 15) /* PWR_I2C Unit Clock Enable */
+#define CKEN9_OST	(1 << 9)  /* OS Timer Unit Clock Enable */
+#define CKEN4_SSP3	(1 << 4)  /* SSP3 Unit Clock Enable */
+
+#define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#if !defined(CONFIG_CPU_PXA27X)
+#define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
+#endif
+#define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN24_CAMERA	(1 << 24)	/* Camera Interface Clock Enable */
+#define CKEN23_SSP1	(1 << 23)	/* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC	(1 << 22)	/* Memory Controller Clock Enable */
+#define CKEN21_MEMSTK	(1 << 21)	/* Memory Stick Host Controller */
+#define CKEN20_IM	(1 << 20)	/* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD	(1 << 19)	/* Keypad Interface Clock Enable */
+#define CKEN18_USIM	(1 << 18)	/* USIM Unit Clock Enable */
+#define CKEN17_MSL	(1 << 17)	/* MSL Unit Clock Enable */
+#define CKEN16_LCD	(1 << 16)	/* LCD Unit Clock Enable */
+#define CKEN15_PWRI2C	(1 << 15)	/* PWR I2C Unit Clock Enable */
+#define CKEN14_I2C	(1 << 14)	/* I2C Unit Clock Enable */
+#define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */
+#define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */
+#define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */
+#if defined(CONFIG_CPU_PXA27X)
+#define CKEN10_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
+#define CKEN24_CAMERA	(1 << 24)	/* Camera Unit Clock Enable */
+#endif
+#define CKEN8_I2S	(1 << 8)	/* I2S Unit Clock Enable */
+#define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */
+#define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */
+#define CKEN5_STUART	(1 << 5)	/* STUART Unit Clock Enable */
+#define CKEN3_SSP	(1 << 3)	/* SSP Unit Clock Enable */
+#define CKEN2_AC97	(1 << 2)	/* AC97 Unit Clock Enable */
+#define CKEN1_PWM1	(1 << 1)	/* PWM1 Clock Enable */
+#define CKEN0_PWM0	(1 << 0)	/* PWM0 Clock Enable */
+
+#define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
+
+#if !defined(CONFIG_CPU_PXA27X)
+#define	 CCCR_L09      (0x1F)
+#define	 CCCR_L27      (0x1)
+#define	 CCCR_L32      (0x2)
+#define	 CCCR_L36      (0x3)
+#define	 CCCR_L40      (0x4)
+#define	 CCCR_L45      (0x5)
+
+#define	 CCCR_M1       (0x1 << 5)
+#define	 CCCR_M2       (0x2 << 5)
+#define	 CCCR_M4       (0x3 << 5)
+
+#define	 CCCR_N10      (0x2 << 7)
+#define	 CCCR_N15      (0x3 << 7)
+#define	 CCCR_N20      (0x4 << 7)
+#define	 CCCR_N25      (0x5 << 7)
+#define	 CCCR_N30      (0x6 << 7)
+#endif
+
+#endif /* CONFIG_CPU_MONAHANS */
+
+/******************************************************************************/
+/*
+ * Pulse Width Modulator
+ */
+#define PWM_CTRL0	0x40B00000  /* PWM 0 Control Register */
+#define PWM_PWDUTY0	0x40B00004  /* PWM 0 Duty Cycle Register */
+#define PWM_PERVAL0	0x40B00008  /* PWM 0 Period Control Register */
+
+#define PWM_CTRL1	0x40C00000  /* PWM 1 Control Register */
+#define PWM_PWDUTY1	0x40C00004  /* PWM 1 Duty Cycle Register */
+#define PWM_PERVAL1	0x40C00008  /* PWM 1 Period Control Register */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define PWM_CTRL2	0x40B00010  /* PWM 2 Control Register */
+#define PWM_PWDUTY2	0x40B00014  /* PWM 2 Duty Cycle Register */
+#define PWM_PERVAL2	0x40B00018  /* PWM 2 Period Control Register */
+
+#define PWM_CTRL3	0x40C00010  /* PWM 3 Control Register */
+#define PWM_PWDUTY3	0x40C00014  /* PWM 3 Duty Cycle Register */
+#define PWM_PERVAL3	0x40C00018  /* PWM 3 Period Control Register */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+/*
+ * Interrupt Controller
+ */
+#define ICIP		0x40D00000  /* Interrupt Controller IRQ Pending Register */
+#define ICMR		0x40D00004  /* Interrupt Controller Mask Register */
+#define ICLR		0x40D00008  /* Interrupt Controller Level Register */
+#define ICFP		0x40D0000C  /* Interrupt Controller FIQ Pending Register */
+#define ICPR		0x40D00010  /* Interrupt Controller Pending Register */
+#define ICCR		0x40D00014  /* Interrupt Controller Control Register */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define ICHP		0x40D00018  /* Interrupt Controller Highest Priority Register */
+#define ICIP2		0x40D0009C  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2		0x40D000A0  /* Interrupt Controller Mask Register 2 */
+#define ICLR2		0x40D000A4  /* Interrupt Controller Level Register 2 */
+#define ICFP2		0x40D000A8  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2		0x40D000AC  /* Interrupt Controller Pending Register 2 */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+/******************************************************************************/
+/*
+ * General Purpose I/O
+ */
+#define GPLR0		0x40E00000  /* GPIO Pin-Level Register GPIO<31:0> */
+#define GPLR1		0x40E00004  /* GPIO Pin-Level Register GPIO<63:32> */
+#define GPLR2		0x40E00008  /* GPIO Pin-Level Register GPIO<80:64> */
+
+#define GPDR0		0x40E0000C  /* GPIO Pin Direction Register GPIO<31:0> */
+#define GPDR1		0x40E00010  /* GPIO Pin Direction Register GPIO<63:32> */
+#define GPDR2		0x40E00014  /* GPIO Pin Direction Register GPIO<80:64> */
+
+#define GPSR0		0x40E00018  /* GPIO Pin Output Set Register GPIO<31:0> */
+#define GPSR1		0x40E0001C  /* GPIO Pin Output Set Register GPIO<63:32> */
+#define GPSR2		0x40E00020  /* GPIO Pin Output Set Register GPIO<80:64> */
+
+#define GPCR0		0x40E00024  /* GPIO Pin Output Clear Register GPIO<31:0> */
+#define GPCR1		0x40E00028  /* GPIO Pin Output Clear Register GPIO <63:32> */
+#define GPCR2		0x40E0002C  /* GPIO Pin Output Clear Register GPIO <80:64> */
+
+#define GRER0		0x40E00030  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
+#define GRER1		0x40E00034  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
+#define GRER2		0x40E00038  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
+
+#define GFER0		0x40E0003C  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GFER1		0x40E00040  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
+#define GFER2		0x40E00044  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
+
+#define GEDR0		0x40E00048  /* GPIO Edge Detect Status Register GPIO<31:0> */
+#define GEDR1		0x40E0004C  /* GPIO Edge Detect Status Register GPIO<63:32> */
+#define GEDR2		0x40E00050  /* GPIO Edge Detect Status Register GPIO<80:64> */
+
+#define GAFR0_L		0x40E00054  /* GPIO Alternate Function Select Register GPIO<15:0> */
+#define GAFR0_U		0x40E00058  /* GPIO Alternate Function Select Register GPIO<31:16> */
+#define GAFR1_L		0x40E0005C  /* GPIO Alternate Function Select Register GPIO<47:32> */
+#define GAFR1_U		0x40E00060  /* GPIO Alternate Function Select Register GPIO<63:48> */
+#define GAFR2_L		0x40E00064  /* GPIO Alternate Function Select Register GPIO<79:64> */
+#define GAFR2_U		0x40E00068  /* GPIO Alternate Function Select Register GPIO 80 */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define GPLR3		0x40E00100  /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3		0x40E0010C  /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3		0x40E00118  /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3		0x40E00124  /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3		0x40E00130  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3		0x40E0013C  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3		0x40E00148  /* GPIO Edge Detect Status Register GPIO<127:96> */
+#define GAFR3_L		0x40E0006C  /* GPIO Alternate Function Select Register GPIO<111:96> */
+#define GAFR3_U		0x40E00070  /* GPIO Alternate Function Select Register GPIO<127:112> */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+#ifdef CONFIG_CPU_MONAHANS
+#define GSDR0		0x40E00400 /* Bit-wise Set of GPDR[31:0] */
+#define GSDR1		0x40E00404 /* Bit-wise Set of GPDR[63:32] */
+#define GSDR2		0x40E00408 /* Bit-wise Set of GPDR[95:64] */
+#define GSDR3		0x40E0040C /* Bit-wise Set of GPDR[127:96] */
+
+#define GCDR0		0x40E00420 /* Bit-wise Clear of GPDR[31:0] */
+#define GCDR1		0x40E00424 /* Bit-wise Clear of GPDR[63:32] */
+#define GCDR2		0x40E00428 /* Bit-wise Clear of GPDR[95:64] */
+#define GCDR3		0x40E0042C /* Bit-wise Clear of GPDR[127:96] */
+
+#define GSRER0		0x40E00440 /* Set Rising Edge Det. Enable [31:0] */
+#define GSRER1		0x40E00444 /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER2		0x40E00448 /* Set Rising Edge Det. Enable [95:64] */
+#define GSRER3		0x40E0044C /* Set Rising Edge Det. Enable [127:96] */
+
+#define GCRER0		0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */
+#define GCRER1		0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER2		0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */
+#define GCRER3		0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */
+
+#define GSFER0		0x40E00480 /* Set Falling Edge Det. Enable [31:0] */
+#define GSFER1		0x40E00484 /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER2		0x40E00488 /* Set Falling Edge Det. Enable [95:64] */
+#define GSFER3		0x40E0048C /* Set Falling Edge Det. Enable[127:96] */
+
+#define GCFER0		0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */
+#define GCFER1		0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER2		0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */
+#define GCFER3		0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */
+
+#define GSDR(x)		(0x40E00400 | ((x) & 0x60) >> 3)
+#define GCDR(x)		(0x40E00420 | ((x) & 0x60) >> 3)
+#endif
+
+#define _GPLR(x)	(0x40E00000 + (((x) & 0x60) >> 3))
+#define _GPDR(x)	(0x40E0000C + (((x) & 0x60) >> 3))
+#define _GPSR(x)	(0x40E00018 + (((x) & 0x60) >> 3))
+#define _GPCR(x)	(0x40E00024 + (((x) & 0x60) >> 3))
+#define _GRER(x)	(0x40E00030 + (((x) & 0x60) >> 3))
+#define _GFER(x)	(0x40E0003C + (((x) & 0x60) >> 3))
+#define _GEDR(x)	(0x40E00048 + (((x) & 0x60) >> 3))
+#define _GAFR(x)	(0x40E00054 + (((x) & 0x70) >> 2))
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define GPLR(x)		(((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
+#define GPDR(x)		(((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
+#define GPSR(x)		(((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
+#define GPCR(x)		(((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3))
+#define GRER(x)		(((((x) & 0x7f) < 96) ? _GRER(x) : GRER3))
+#define GFER(x)		(((((x) & 0x7f) < 96) ? _GFER(x) : GFER3))
+#define GEDR(x)		(((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3))
+#define GAFR(x)		(((((x) & 0x7f) < 96) ? _GAFR(x) : \
+			((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)))
+#else
+#define GPLR(x)		_GPLR(x)
+#define GPDR(x)		_GPDR(x)
+#define GPSR(x)		_GPSR(x)
+#define GPCR(x)		_GPCR(x)
+#define GRER(x)		_GRER(x)
+#define GFER(x)		_GFER(x)
+#define GEDR(x)		_GEDR(x)
+#define GAFR(x)		_GAFR(x)
+#endif
+
+#define GPIO_bit(x)	(1 << ((x) & 0x1f))
+
+/******************************************************************************/
+/*
+ * Multi-function Pin Registers:
+ */
+/* PXA320 */
+#if defined(CONFIG_CPU_PXA320)
+#define	DF_IO0		0x40e1024c
+#define	DF_IO1		0x40e10254
+#define	DF_IO2		0x40e1025c
+#define	DF_IO3		0x40e10264
+#define	DF_IO4		0x40e1026c
+#define	DF_IO5		0x40e10274
+#define	DF_IO6		0x40e1027c
+#define	DF_IO7		0x40e10284
+#define	DF_IO8		0x40e10250
+#define	DF_IO9		0x40e10258
+#define	DF_IO10		0x40e10260
+#define	DF_IO11		0x40e10268
+#define	DF_IO12		0x40e10270
+#define	DF_IO13		0x40e10278
+#define	DF_IO14		0x40e10280
+#define	DF_IO15		0x40e10288
+#define	DF_CLE_nOE	0x40e10204
+#define	DF_ALE_nWE1	0x40e10208
+#define	DF_ALE_nWE2	0x40e1021c
+#define	DF_SCLK_E	0x40e10210
+#define	DF_nCS0		0x40e10224
+#define	DF_nCS1		0x40e10228
+#define	nBE0		0x40e10214
+#define	nBE1		0x40e10218
+#define	nLUA		0x40e10234
+#define	nLLA		0x40e10238
+#define	DF_ADDR0	0x40e1023c
+#define	DF_ADDR1	0x40e10240
+#define	DF_ADDR2	0x40e10244
+#define	DF_ADDR3	0x40e10248
+#define	DF_INT_RnB	0x40e10220
+#define	DF_nCS0		0x40e10224
+#define	DF_nCS1		0x40e10228
+#define	DF_nWE		0x40e1022c
+#define	DF_nRE		0x40e10230
+
+#define	nXCVREN		0x40e10138
+
+#define	GPIO0		0x40e10124
+#define	GPIO1		0x40e10128
+#define	GPIO2		0x40e1012c
+#define	GPIO3		0x40e10130
+#define	GPIO4		0x40e10134
+#define	GPIO5		0x40e1028c
+#define	GPIO6		0x40e10290
+#define	GPIO7		0x40e10294
+#define	GPIO8		0x40e10298
+#define	GPIO9		0x40e1029c
+#define	GPIO10		0x40e10458
+#define	GPIO11		0x40e102a0
+#define	GPIO12		0x40e102a4
+#define	GPIO13		0x40e102a8
+#define	GPIO14		0x40e102ac
+#define	GPIO15		0x40e102b0
+#define	GPIO16		0x40e102b4
+#define	GPIO17		0x40e102b8
+#define	GPIO18		0x40e102bc
+#define	GPIO19		0x40e102c0
+#define	GPIO20		0x40e102c4
+#define	GPIO21		0x40e102c8
+#define	GPIO22		0x40e102cc
+#define	GPIO23		0x40e102d0
+#define	GPIO24		0x40e102d4
+#define	GPIO25		0x40e102d8
+#define	GPIO26		0x40e102dc
+
+#define	GPIO27		0x40e10400
+#define	GPIO28		0x40e10404
+#define	GPIO29		0x40e10408
+#define	GPIO30		0x40e1040c
+#define	GPIO31		0x40e10410
+#define	GPIO32		0x40e10414
+#define	GPIO33		0x40e10418
+#define	GPIO34		0x40e1041c
+#define	GPIO35		0x40e10420
+#define	GPIO36		0x40e10424
+#define	GPIO37		0x40e10428
+#define	GPIO38		0x40e1042c
+#define	GPIO39		0x40e10430
+#define	GPIO40		0x40e10434
+#define	GPIO41		0x40e10438
+#define	GPIO42		0x40e1043c
+#define	GPIO43		0x40e10440
+#define	GPIO44		0x40e10444
+#define	GPIO45		0x40e10448
+#define	GPIO46		0x40e1044c
+#define	GPIO47		0x40e10450
+#define	GPIO48		0x40e10454
+#define	GPIO49		0x40e1045c
+#define	GPIO50		0x40e10460
+#define	GPIO51		0x40e10464
+#define	GPIO52		0x40e10468
+#define	GPIO53		0x40e1046c
+#define	GPIO54		0x40e10470
+#define	GPIO55		0x40e10474
+#define	GPIO56		0x40e10478
+#define	GPIO57		0x40e1047c
+#define	GPIO58		0x40e10480
+#define	GPIO59		0x40e10484
+#define	GPIO60		0x40e10488
+#define	GPIO61		0x40e1048c
+#define	GPIO62		0x40e10490
+
+#define	GPIO6_2		0x40e10494
+#define	GPIO7_2		0x40e10498
+#define	GPIO8_2		0x40e1049c
+#define	GPIO9_2		0x40e104a0
+#define	GPIO10_2	0x40e104a4
+#define	GPIO11_2	0x40e104a8
+#define	GPIO12_2	0x40e104ac
+#define	GPIO13_2	0x40e104b0
+
+#define	GPIO63		0x40e104b4
+#define	GPIO64		0x40e104b8
+#define	GPIO65		0x40e104bc
+#define	GPIO66		0x40e104c0
+#define	GPIO67		0x40e104c4
+#define	GPIO68		0x40e104c8
+#define	GPIO69		0x40e104cc
+#define	GPIO70		0x40e104d0
+#define	GPIO71		0x40e104d4
+#define	GPIO72		0x40e104d8
+#define	GPIO73		0x40e104dc
+
+#define	GPIO14_2	0x40e104e0
+#define	GPIO15_2	0x40e104e4
+#define	GPIO16_2	0x40e104e8
+#define	GPIO17_2	0x40e104ec
+
+#define	GPIO74		0x40e104f0
+#define	GPIO75		0x40e104f4
+#define	GPIO76		0x40e104f8
+#define	GPIO77		0x40e104fc
+#define	GPIO78		0x40e10500
+#define	GPIO79		0x40e10504
+#define	GPIO80		0x40e10508
+#define	GPIO81		0x40e1050c
+#define	GPIO82		0x40e10510
+#define	GPIO83		0x40e10514
+#define	GPIO84		0x40e10518
+#define	GPIO85		0x40e1051c
+#define	GPIO86		0x40e10520
+#define	GPIO87		0x40e10524
+#define	GPIO88		0x40e10528
+#define	GPIO89		0x40e1052c
+#define	GPIO90		0x40e10530
+#define	GPIO91		0x40e10534
+#define	GPIO92		0x40e10538
+#define	GPIO93		0x40e1053c
+#define	GPIO94		0x40e10540
+#define	GPIO95		0x40e10544
+#define	GPIO96		0x40e10548
+#define	GPIO97		0x40e1054c
+#define	GPIO98		0x40e10550
+
+#define	GPIO99		0x40e10600
+#define	GPIO100		0x40e10604
+#define	GPIO101		0x40e10608
+#define	GPIO102		0x40e1060c
+#define	GPIO103		0x40e10610
+#define	GPIO104		0x40e10614
+#define	GPIO105		0x40e10618
+#define	GPIO106		0x40e1061c
+#define	GPIO107		0x40e10620
+#define	GPIO108		0x40e10624
+#define	GPIO109		0x40e10628
+#define	GPIO110		0x40e1062c
+#define	GPIO111		0x40e10630
+#define	GPIO112		0x40e10634
+
+#define	GPIO113		0x40e10638
+#define	GPIO114		0x40e1063c
+#define	GPIO115		0x40e10640
+#define	GPIO116		0x40e10644
+#define	GPIO117		0x40e10648
+#define	GPIO118		0x40e1064c
+#define	GPIO119		0x40e10650
+#define	GPIO120		0x40e10654
+#define	GPIO121		0x40e10658
+#define	GPIO122		0x40e1065c
+#define	GPIO123		0x40e10660
+#define	GPIO124		0x40e10664
+#define	GPIO125		0x40e10668
+#define	GPIO126		0x40e1066c
+#define	GPIO127		0x40e10670
+
+#define	GPIO0_2		0x40e10674
+#define	GPIO1_2		0x40e10678
+#define	GPIO2_2		0x40e1067c
+#define	GPIO3_2		0x40e10680
+#define	GPIO4_2		0x40e10684
+#define	GPIO5_2		0x40e10688
+
+/* PXA300 and PXA310 */
+#elif	defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310)
+#define	DF_IO0		0x40e10220
+#define	DF_IO1		0x40e10228
+#define	DF_IO2		0x40e10230
+#define	DF_IO3		0x40e10238
+#define	DF_IO4		0x40e10258
+#define	DF_IO5		0x40e10260
+#define	DF_IO7		0x40e10270
+#define	DF_IO6		0x40e10268
+#define	DF_IO8		0x40e10224
+#define	DF_IO9		0x40e1022c
+#define	DF_IO10		0x40e10234
+#define	DF_IO11		0x40e1023c
+#define	DF_IO12		0x40e1025c
+#define	DF_IO13		0x40e10264
+#define	DF_IO14		0x40e1026c
+#define	DF_IO15		0x40e10274
+#define	DF_CLE_NOE	0x40e10240
+#define	DF_ALE_nWE	0x40e1020c
+#define	DF_SCLK_E	0x40e10250
+#define	nCS0		0x40e100c4
+#define	nCS1		0x40e100c0
+#define	nBE0		0x40e10204
+#define	nBE1		0x40e10208
+#define	nLUA		0x40e10244
+#define	nLLA		0x40e10254
+#define	DF_ADDR0	0x40e10210
+#define	DF_ADDR1	0x40e10214
+#define	DF_ADDR2	0x40e10218
+#define	DF_ADDR3	0x40e1021c
+#define	DF_INT_RnB	0x40e100c8
+#define	DF_nCS0		0x40e10248
+#define	DF_nCS1		0x40e10278
+#define	DF_nWE		0x40e100cc
+#define	DF_nRE		0x40e10200
+
+#define	GPIO0		0x40e100b4
+#define	GPIO1		0x40e100b8
+#define	GPIO2		0x40e100bc
+#define	GPIO3		0x40e1027c
+#define	GPIO4		0x40e10280
+
+#define	GPIO5		0x40e10284
+#define	GPIO6		0x40e10288
+#define	GPIO7		0x40e1028c
+#define	GPIO8		0x40e10290
+#define	GPIO9		0x40e10294
+#define	GPIO10		0x40e10298
+#define	GPIO11		0x40e1029c
+#define	GPIO12		0x40e102a0
+#define	GPIO13		0x40e102a4
+#define	GPIO14		0x40e102a8
+#define	GPIO15		0x40e102ac
+#define	GPIO16		0x40e102b0
+#define	GPIO17		0x40e102b4
+#define	GPIO18		0x40e102b8
+#define	GPIO19		0x40e102bc
+#define	GPIO20		0x40e102c0
+#define	GPIO21		0x40e102c4
+#define	GPIO22		0x40e102c8
+#define	GPIO23		0x40e102cc
+#define	GPIO24		0x40e102d0
+#define	GPIO25		0x40e102d4
+#define	GPIO26		0x40e102d8
+
+#define	GPIO27		0x40e10400
+#define	GPIO28		0x40e10404
+#define	GPIO29		0x40e10408
+#define	ULPI_STP	0x40e1040c
+#define	ULPI_NXT	0x40e10410
+#define	ULPI_DIR	0x40e10414
+#define	GPIO30		0x40e10418
+#define	GPIO31		0x40e1041c
+#define	GPIO32		0x40e10420
+#define	GPIO33		0x40e10424
+#define	GPIO34		0x40e10428
+#define	GPIO35		0x40e1042c
+#define	GPIO36		0x40e10430
+#define	GPIO37		0x40e10434
+#define	GPIO38		0x40e10438
+#define	GPIO39		0x40e1043c
+#define	GPIO40		0x40e10440
+#define	GPIO41		0x40e10444
+#define	GPIO42		0x40e10448
+#define	GPIO43		0x40e1044c
+#define	GPIO44		0x40e10450
+#define	GPIO45		0x40e10454
+#define	GPIO46		0x40e10458
+#define	GPIO47		0x40e1045c
+#define	GPIO48		0x40e10460
+
+#define	GPIO49		0x40e10464
+#define	GPIO50		0x40e10468
+#define	GPIO51		0x40e1046c
+#define	GPIO52		0x40e10470
+#define	GPIO53		0x40e10474
+#define	GPIO54		0x40e10478
+#define	GPIO55		0x40e1047c
+#define	GPIO56		0x40e10480
+#define	GPIO57		0x40e10484
+#define	GPIO58		0x40e10488
+#define	GPIO59		0x40e1048c
+#define	GPIO60		0x40e10490
+#define	GPIO61		0x40e10494
+#define	GPIO62		0x40e10498
+#define	GPIO63		0x40e1049c
+#define	GPIO64		0x40e104a0
+#define	GPIO65		0x40e104a4
+#define	GPIO66		0x40e104a8
+#define	GPIO67		0x40e104ac
+#define	GPIO68		0x40e104b0
+#define	GPIO69		0x40e104b4
+#define	GPIO70		0x40e104b8
+#define	GPIO71		0x40e104bc
+#define	GPIO72		0x40e104c0
+#define	GPIO73		0x40e104c4
+#define	GPIO74		0x40e104c8
+#define	GPIO75		0x40e104cc
+#define	GPIO76		0x40e104d0
+#define	GPIO77		0x40e104d4
+#define	GPIO78		0x40e104d8
+#define	GPIO79		0x40e104dc
+#define	GPIO80		0x40e104e0
+#define	GPIO81		0x40e104e4
+#define	GPIO82		0x40e104e8
+#define	GPIO83		0x40e104ec
+#define	GPIO84		0x40e104f0
+#define	GPIO85		0x40e104f4
+#define	GPIO86		0x40e104f8
+#define	GPIO87		0x40e104fc
+#define	GPIO88		0x40e10500
+#define	GPIO89		0x40e10504
+#define	GPIO90		0x40e10508
+#define	GPIO91		0x40e1050c
+#define	GPIO92		0x40e10510
+#define	GPIO93		0x40e10514
+#define	GPIO94		0x40e10518
+#define	GPIO95		0x40e1051c
+#define	GPIO96		0x40e10520
+#define	GPIO97		0x40e10524
+#define	GPIO98		0x40e10528
+
+#define	GPIO99		0x40e10600
+#define	GPIO100		0x40e10604
+#define	GPIO101		0x40e10608
+#define	GPIO102		0x40e1060c
+#define	GPIO103		0x40e10610
+#define	GPIO104		0x40e10614
+#define	GPIO105		0x40e10618
+#define	GPIO106		0x40e1061c
+#define	GPIO107		0x40e10620
+#define	GPIO108		0x40e10624
+#define	GPIO109		0x40e10628
+#define	GPIO110		0x40e1062c
+#define	GPIO111		0x40e10630
+#define	GPIO112		0x40e10634
+
+#define	GPIO113		0x40e10638
+#define	GPIO114		0x40e1063c
+#define	GPIO115		0x40e10640
+#define	GPIO116		0x40e10644
+#define	GPIO117		0x40e10648
+#define	GPIO118		0x40e1064c
+#define	GPIO119		0x40e10650
+#define	GPIO120		0x40e10654
+#define	GPIO121		0x40e10658
+#define	GPIO122		0x40e1065c
+#define	GPIO123		0x40e10660
+#define	GPIO124		0x40e10664
+#define	GPIO125		0x40e10668
+#define	GPIO126		0x40e1066c
+#define	GPIO127		0x40e10670
+
+#define	GPIO0_2		0x40e10674
+#define	GPIO1_2		0x40e10678
+#define	GPIO2_2		0x40e102dc
+#define	GPIO3_2		0x40e102e0
+#define	GPIO4_2		0x40e102e4
+#define	GPIO5_2		0x40e102e8
+#define	GPIO6_2		0x40e102ec
+
+#ifndef	CONFIG_CPU_PXA300	/* PXA310 only */
+#define	GPIO7_2		0x40e1052c
+#define	GPIO8_2		0x40e10530
+#define	GPIO9_2		0x40e10534
+#define	GPIO10_2	0x40e10538
+#endif
+#endif
+
+#ifdef CONFIG_CPU_MONAHANS
+/* MFPR Bit Definitions, see 4-10, Vol. 1 */
+#define PULL_SEL	0x8000
+#define PULLUP_EN	0x4000
+#define PULLDOWN_EN	0x2000
+
+#define DRIVE_FAST_1mA	0x0
+#define DRIVE_FAST_2mA	0x400
+#define DRIVE_FAST_3mA	0x800
+#define DRIVE_FAST_4mA	0xC00
+#define DRIVE_SLOW_6mA	0x1000
+#define DRIVE_FAST_6mA	0x1400
+#define DRIVE_SLOW_10mA	0x1800
+#define DRIVE_FAST_10mA	0x1C00
+
+#define SLEEP_SEL	0x200
+#define SLEEP_DATA	0x100
+#define SLEEP_OE_N	0x80
+#define EDGE_CLEAR	0x40
+#define EDGE_FALL_EN	0x20
+#define EDGE_RISE_EN	0x10
+
+#define AF_SEL_0	0x0	/* Alternate function 0 (reset state) */
+#define AF_SEL_1	0x1	/* Alternate function 1 */
+#define AF_SEL_2	0x2	/* Alternate function 2 */
+#define AF_SEL_3	0x3	/* Alternate function 3 */
+#define AF_SEL_4	0x4	/* Alternate function 4 */
+#define AF_SEL_5	0x5	/* Alternate function 5 */
+#define AF_SEL_6	0x6	/* Alternate function 6 */
+#define AF_SEL_7	0x7	/* Alternate function 7 */
+
+#endif /* CONFIG_CPU_MONAHANS */
+
+/* GPIO alternate function assignments */
+
+#define GPIO1_RST		1	/* reset */
+#define GPIO6_MMCCLK		6	/* MMC Clock */
+#define GPIO8_48MHz		7	/* 48 MHz clock output */
+#define GPIO8_MMCCS0		8	/* MMC Chip Select 0 */
+#define GPIO9_MMCCS1		9	/* MMC Chip Select 1 */
+#define GPIO10_RTCCLK		10	/* real time clock (1 Hz) */
+#define GPIO11_3_6MHz		11	/* 3.6 MHz oscillator out */
+#define GPIO12_32KHz		12	/* 32 kHz out */
+#define GPIO13_MBGNT		13	/* memory controller grant */
+#define GPIO14_MBREQ		14	/* alternate bus master request */
+#define GPIO15_nCS_1		15	/* chip select 1 */
+#define GPIO16_PWM0		16	/* PWM0 output */
+#define GPIO17_PWM1		17	/* PWM1 output */
+#define GPIO18_RDY		18	/* Ext. Bus Ready */
+#define GPIO19_DREQ1		19	/* External DMA Request */
+#define GPIO20_DREQ0		20	/* External DMA Request */
+#define GPIO23_SCLK		23	/* SSP clock */
+#define GPIO24_SFRM		24	/* SSP Frame */
+#define GPIO25_STXD		25	/* SSP transmit */
+#define GPIO26_SRXD		26	/* SSP receive */
+#define GPIO27_SEXTCLK		27	/* SSP ext_clk */
+#define GPIO28_BITCLK		28	/* AC97/I2S bit_clk */
+#define GPIO29_SDATA_IN		29	/* AC97 Sdata_in0 / I2S Sdata_in */
+#define GPIO30_SDATA_OUT	30	/* AC97/I2S Sdata_out */
+#define GPIO31_SYNC		31	/* AC97/I2S sync */
+#define GPIO32_SDATA_IN1	32	/* AC97 Sdata_in1 */
+#define GPIO33_nCS_5		33	/* chip select 5 */
+#define GPIO34_FFRXD		34	/* FFUART receive */
+#define GPIO34_MMCCS0		34	/* MMC Chip Select 0 */
+#define GPIO35_FFCTS		35	/* FFUART Clear to send */
+#define GPIO36_FFDCD		36	/* FFUART Data carrier detect */
+#define GPIO37_FFDSR		37	/* FFUART data set ready */
+#define GPIO38_FFRI		38	/* FFUART Ring Indicator */
+#define GPIO39_MMCCS1		39	/* MMC Chip Select 1 */
+#define GPIO39_FFTXD		39	/* FFUART transmit data */
+#define GPIO40_FFDTR		40	/* FFUART data terminal Ready */
+#define GPIO41_FFRTS		41	/* FFUART request to send */
+#define GPIO42_BTRXD		42	/* BTUART receive data */
+#define GPIO43_BTTXD		43	/* BTUART transmit data */
+#define GPIO44_BTCTS		44	/* BTUART clear to send */
+#define GPIO45_BTRTS		45	/* BTUART request to send */
+#define GPIO46_ICPRXD		46	/* ICP receive data */
+#define GPIO46_STRXD		46	/* STD_UART receive data */
+#define GPIO47_ICPTXD		47	/* ICP transmit data */
+#define GPIO47_STTXD		47	/* STD_UART transmit data */
+#define GPIO48_nPOE		48	/* Output Enable for Card Space */
+#define GPIO49_nPWE		49	/* Write Enable for Card Space */
+#define GPIO50_nPIOR		50	/* I/O Read for Card Space */
+#define GPIO51_nPIOW		51	/* I/O Write for Card Space */
+#define GPIO52_nPCE_1		52	/* Card Enable for Card Space */
+#define GPIO53_nPCE_2		53	/* Card Enable for Card Space */
+#define GPIO53_MMCCLK		53	/* MMC Clock */
+#define GPIO54_MMCCLK		54	/* MMC Clock */
+#define GPIO54_pSKTSEL		54	/* Socket Select for Card Space */
+#define GPIO55_nPREG		55	/* Card Address bit 26 */
+#define GPIO56_nPWAIT		56	/* Wait signal for Card Space */
+#define GPIO57_nIOIS16		57	/* Bus Width select for I/O Card Space */
+#define GPIO58_LDD_0		58	/* LCD data pin 0 */
+#define GPIO59_LDD_1		59	/* LCD data pin 1 */
+#define GPIO60_LDD_2		60	/* LCD data pin 2 */
+#define GPIO61_LDD_3		61	/* LCD data pin 3 */
+#define GPIO62_LDD_4		62	/* LCD data pin 4 */
+#define GPIO63_LDD_5		63	/* LCD data pin 5 */
+#define GPIO64_LDD_6		64	/* LCD data pin 6 */
+#define GPIO65_LDD_7		65	/* LCD data pin 7 */
+#define GPIO66_LDD_8		66	/* LCD data pin 8 */
+#define GPIO66_MBREQ		66	/* alternate bus master req */
+#define GPIO67_LDD_9		67	/* LCD data pin 9 */
+#define GPIO67_MMCCS0		67	/* MMC Chip Select 0 */
+#define GPIO68_LDD_10		68	/* LCD data pin 10 */
+#define GPIO68_MMCCS1		68	/* MMC Chip Select 1 */
+#define GPIO69_LDD_11		69	/* LCD data pin 11 */
+#define GPIO69_MMCCLK		69	/* MMC_CLK */
+#define GPIO70_LDD_12		70	/* LCD data pin 12 */
+#define GPIO70_RTCCLK		70	/* Real Time clock (1 Hz) */
+#define GPIO71_LDD_13		71	/* LCD data pin 13 */
+#define GPIO71_3_6MHz		71	/* 3.6 MHz Oscillator clock */
+#define GPIO72_LDD_14		72	/* LCD data pin 14 */
+#define GPIO72_32kHz		72	/* 32 kHz clock */
+#define GPIO73_LDD_15		73	/* LCD data pin 15 */
+#define GPIO73_MBGNT		73	/* Memory controller grant */
+#define GPIO74_LCD_FCLK		74	/* LCD Frame clock */
+#define GPIO75_LCD_LCLK		75	/* LCD line clock */
+#define GPIO76_LCD_PCLK		76	/* LCD Pixel clock */
+#define GPIO77_LCD_ACBIAS	77	/* LCD AC Bias */
+#define GPIO78_nCS_2		78	/* chip select 2 */
+#define GPIO79_nCS_3		79	/* chip select 3 */
+#define GPIO80_nCS_4		80	/* chip select 4 */
+
+/* GPIO alternate function mode & direction */
+
+#define GPIO_IN			0x000
+#define GPIO_OUT		0x080
+#define GPIO_ALT_FN_1_IN	0x100
+#define GPIO_ALT_FN_1_OUT	0x180
+#define GPIO_ALT_FN_2_IN	0x200
+#define GPIO_ALT_FN_2_OUT	0x280
+#define GPIO_ALT_FN_3_IN	0x300
+#define GPIO_ALT_FN_3_OUT	0x380
+#define GPIO_MD_MASK_NR		0x07f
+#define GPIO_MD_MASK_DIR	0x080
+#define GPIO_MD_MASK_FN		0x300
+
+#define GPIO1_RTS_MD		( 1 | GPIO_ALT_FN_1_IN)
+#define GPIO6_MMCCLK_MD		( 6 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_48MHz_MD		( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_MMCCS0_MD		( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO9_MMCCS1_MD		( 9 | GPIO_ALT_FN_1_OUT)
+#define GPIO10_RTCCLK_MD	(10 | GPIO_ALT_FN_1_OUT)
+#define GPIO11_3_6MHz_MD	(11 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_32KHz_MD		(12 | GPIO_ALT_FN_1_OUT)
+#define GPIO13_MBGNT_MD		(13 | GPIO_ALT_FN_2_OUT)
+#define GPIO14_MBREQ_MD		(14 | GPIO_ALT_FN_1_IN)
+#define GPIO15_nCS_1_MD		(15 | GPIO_ALT_FN_2_OUT)
+#define GPIO16_PWM0_MD		(16 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_PWM1_MD		(17 | GPIO_ALT_FN_2_OUT)
+#define GPIO18_RDY_MD		(18 | GPIO_ALT_FN_1_IN)
+#define GPIO19_DREQ1_MD		(19 | GPIO_ALT_FN_1_IN)
+#define GPIO20_DREQ0_MD		(20 | GPIO_ALT_FN_1_IN)
+#define GPIO23_SCLK_md		(23 | GPIO_ALT_FN_2_OUT)
+#define GPIO24_SFRM_MD		(24 | GPIO_ALT_FN_2_OUT)
+#define GPIO25_STXD_MD		(25 | GPIO_ALT_FN_2_OUT)
+#define GPIO26_SRXD_MD		(26 | GPIO_ALT_FN_1_IN)
+#define GPIO27_SEXTCLK_MD	(27 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_AC97_MD	(28 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_I2S_MD	(28 | GPIO_ALT_FN_2_IN)
+#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
+#define GPIO29_SDATA_IN_I2S_MD	(29 | GPIO_ALT_FN_2_IN)
+#define GPIO30_SDATA_OUT_AC97_MD	(30 | GPIO_ALT_FN_2_OUT)
+#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_AC97_MD	(31 | GPIO_ALT_FN_2_OUT)
+#define GPIO31_SYNC_I2S_MD	(31 | GPIO_ALT_FN_1_OUT)
+#define GPIO32_SDATA_IN1_AC97_MD	(32 | GPIO_ALT_FN_1_IN)
+#define GPIO33_nCS_5_MD		(33 | GPIO_ALT_FN_2_OUT)
+#define GPIO34_FFRXD_MD		(34 | GPIO_ALT_FN_1_IN)
+#define GPIO34_MMCCS0_MD	(34 | GPIO_ALT_FN_2_OUT)
+#define GPIO35_FFCTS_MD		(35 | GPIO_ALT_FN_1_IN)
+#define GPIO36_FFDCD_MD		(36 | GPIO_ALT_FN_1_IN)
+#define GPIO37_FFDSR_MD		(37 | GPIO_ALT_FN_1_IN)
+#define GPIO38_FFRI_MD		(38 | GPIO_ALT_FN_1_IN)
+#define GPIO39_MMCCS1_MD	(39 | GPIO_ALT_FN_1_OUT)
+#define GPIO39_FFTXD_MD		(39 | GPIO_ALT_FN_2_OUT)
+#define GPIO40_FFDTR_MD		(40 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_FFRTS_MD		(41 | GPIO_ALT_FN_2_OUT)
+#define GPIO42_BTRXD_MD		(42 | GPIO_ALT_FN_1_IN)
+#define GPIO43_BTTXD_MD		(43 | GPIO_ALT_FN_2_OUT)
+#define GPIO44_BTCTS_MD		(44 | GPIO_ALT_FN_1_IN)
+#define GPIO45_BTRTS_MD		(45 | GPIO_ALT_FN_2_OUT)
+#define GPIO46_ICPRXD_MD	(46 | GPIO_ALT_FN_1_IN)
+#define GPIO46_STRXD_MD		(46 | GPIO_ALT_FN_2_IN)
+#define GPIO47_ICPTXD_MD	(47 | GPIO_ALT_FN_2_OUT)
+#define GPIO47_STTXD_MD		(47 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD		(48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_nPWE_MD		(49 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_nPIOR_MD		(50 | GPIO_ALT_FN_2_OUT)
+#define GPIO51_nPIOW_MD		(51 | GPIO_ALT_FN_2_OUT)
+#define GPIO52_nPCE_1_MD	(52 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_nPCE_2_MD	(53 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_MMCCLK_MD	(53 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_MMCCLK_MD	(54 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_pSKTSEL_MD	(54 | GPIO_ALT_FN_2_OUT)
+#define GPIO55_nPREG_MD		(55 | GPIO_ALT_FN_2_OUT)
+#define GPIO56_nPWAIT_MD	(56 | GPIO_ALT_FN_1_IN)
+#define GPIO57_nIOIS16_MD	(57 | GPIO_ALT_FN_1_IN)
+#define GPIO58_LDD_0_MD		(58 | GPIO_ALT_FN_2_OUT)
+#define GPIO59_LDD_1_MD		(59 | GPIO_ALT_FN_2_OUT)
+#define GPIO60_LDD_2_MD		(60 | GPIO_ALT_FN_2_OUT)
+#define GPIO61_LDD_3_MD		(61 | GPIO_ALT_FN_2_OUT)
+#define GPIO62_LDD_4_MD		(62 | GPIO_ALT_FN_2_OUT)
+#define GPIO63_LDD_5_MD		(63 | GPIO_ALT_FN_2_OUT)
+#define GPIO64_LDD_6_MD		(64 | GPIO_ALT_FN_2_OUT)
+#define GPIO65_LDD_7_MD		(65 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_LDD_8_MD		(66 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_MBREQ_MD		(66 | GPIO_ALT_FN_1_IN)
+#define GPIO67_LDD_9_MD		(67 | GPIO_ALT_FN_2_OUT)
+#define GPIO67_MMCCS0_MD	(67 | GPIO_ALT_FN_1_OUT)
+#define GPIO68_LDD_10_MD	(68 | GPIO_ALT_FN_2_OUT)
+#define GPIO68_MMCCS1_MD	(68 | GPIO_ALT_FN_1_OUT)
+#define GPIO69_LDD_11_MD	(69 | GPIO_ALT_FN_2_OUT)
+#define GPIO69_MMCCLK_MD	(69 | GPIO_ALT_FN_1_OUT)
+#define GPIO70_LDD_12_MD	(70 | GPIO_ALT_FN_2_OUT)
+#define GPIO70_RTCCLK_MD	(70 | GPIO_ALT_FN_1_OUT)
+#define GPIO71_LDD_13_MD	(71 | GPIO_ALT_FN_2_OUT)
+#define GPIO71_3_6MHz_MD	(71 | GPIO_ALT_FN_1_OUT)
+#define GPIO72_LDD_14_MD	(72 | GPIO_ALT_FN_2_OUT)
+#define GPIO72_32kHz_MD		(72 | GPIO_ALT_FN_1_OUT)
+#define GPIO73_LDD_15_MD	(73 | GPIO_ALT_FN_2_OUT)
+#define GPIO73_MBGNT_MD		(73 | GPIO_ALT_FN_1_OUT)
+#define GPIO74_LCD_FCLK_MD	(74 | GPIO_ALT_FN_2_OUT)
+#define GPIO75_LCD_LCLK_MD	(75 | GPIO_ALT_FN_2_OUT)
+#define GPIO76_LCD_PCLK_MD	(76 | GPIO_ALT_FN_2_OUT)
+#define GPIO77_LCD_ACBIAS_MD	(77 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nCS_2_MD		(78 | GPIO_ALT_FN_2_OUT)
+#define GPIO79_nCS_3_MD		(79 | GPIO_ALT_FN_2_OUT)
+#define GPIO80_nCS_4_MD		(80 | GPIO_ALT_FN_2_OUT)
+
+#define GPIO117_SCL		(117 | GPIO_ALT_FN_1_OUT)
+#define GPIO118_SDA		(118 | GPIO_ALT_FN_1_OUT)
+
+/*
+ * Power Manager
+ */
+#ifdef CONFIG_CPU_MONAHANS
+
+#define ASCR		0x40F40000  /* Application Subsystem Power Status/Control Register */
+#define ARSR		0x40F40004  /* Application Subsystem Reset Status Register */
+#define AD3ER		0x40F40008  /* Application Subsystem D3 state Wakeup Enable Register */
+#define AD3SR		0x40F4000C  /* Application Subsystem D3 state Wakeup Status Register */
+#define AD2D0ER		0x40F40010  /* Application Subsystem D2 to D0 state Wakeup Enable Register */
+#define AD2D0SR		0x40F40014  /* Application Subsystem D2 to D0 state Wakeup Status Register */
+#define AD2D1ER		0x40F40018  /* Application Subsystem D2 to D1 state Wakeup Enable Register */
+#define AD2D1SR		0x40F4001C  /* Application Subsystem D2 to D1 state Wakeup Status Register */
+#define AD1D0ER		0x40F40020  /* Application Subsystem D1 to D0 state Wakeup Enable Register */
+#define AD1D0SR		0x40F40024  /* Application Subsystem D1 to D0 state Wakeup Status Register */
+#define ASDCNT		0x40F40028  /* Application Subsystem SRAM Drowsy Count Register */
+#define AD3R		0x40F40030  /* Application Subsystem D3 State Configuration Register */
+#define AD2R		0x40F40034  /* Application Subsystem D2 State Configuration Register */
+#define AD1R		0x40F40038  /* Application Subsystem D1 State Configuration Register */
+
+#define PMCR		0x40F50000  /* Power Manager Control Register */
+#define PSR		0x40F50004  /* Power Manager S2 Status Register */
+#define PSPR		0x40F50008  /* Power Manager Scratch Pad Register */
+#define PCFR		0x40F5000C  /* Power Manager General Configuration Register */
+#define PWER		0x40F50010  /* Power Manager Wake-up Enable Register */
+#define PWSR		0x40F50014  /* Power Manager Wake-up Status Register */
+#define PECR		0x40F50018  /* Power Manager EXT_WAKEUP[1:0] Control Register */
+#define DCDCSR		0x40F50080  /* DC-DC Controller Status Register */
+#define PVCR		0x40F50100  /* Power Manager Voltage Change Control Register */
+#define    PCMD(x) (0x40F50110 + x*4)
+#define    PCMD0   (0x40F50110 + 0 * 4)
+#define    PCMD1   (0x40F50110 + 1 * 4)
+#define    PCMD2   (0x40F50110 + 2 * 4)
+#define    PCMD3   (0x40F50110 + 3 * 4)
+#define    PCMD4   (0x40F50110 + 4 * 4)
+#define    PCMD5   (0x40F50110 + 5 * 4)
+#define    PCMD6   (0x40F50110 + 6 * 4)
+#define    PCMD7   (0x40F50110 + 7 * 4)
+#define    PCMD8   (0x40F50110 + 8 * 4)
+#define    PCMD9   (0x40F50110 + 9 * 4)
+#define    PCMD10  (0x40F50110 + 10 * 4)
+#define    PCMD11  (0x40F50110 + 11 * 4)
+#define    PCMD12  (0x40F50110 + 12 * 4)
+#define    PCMD13  (0x40F50110 + 13 * 4)
+#define    PCMD14  (0x40F50110 + 14 * 4)
+#define    PCMD15  (0x40F50110 + 15 * 4)
+#define    PCMD16  (0x40F50110 + 16 * 4)
+#define    PCMD17  (0x40F50110 + 17 * 4)
+#define    PCMD18  (0x40F50110 + 18 * 4)
+#define    PCMD19  (0x40F50110 + 19 * 4)
+#define    PCMD20  (0x40F50110 + 20 * 4)
+#define    PCMD21  (0x40F50110 + 21 * 4)
+#define    PCMD22  (0x40F50110 + 22 * 4)
+#define    PCMD23  (0x40F50110 + 23 * 4)
+#define    PCMD24  (0x40F50110 + 24 * 4)
+#define    PCMD25  (0x40F50110 + 25 * 4)
+#define    PCMD26  (0x40F50110 + 26 * 4)
+#define    PCMD27  (0x40F50110 + 27 * 4)
+#define    PCMD28  (0x40F50110 + 28 * 4)
+#define    PCMD29  (0x40F50110 + 29 * 4)
+#define    PCMD30  (0x40F50110 + 30 * 4)
+#define    PCMD31  (0x40F50110 + 31 * 4)
+
+#define    PCMD_MBC    (1<<12)
+#define    PCMD_DCE    (1<<11)
+#define    PCMD_LC     (1<<10)
+#define    PCMD_SQC    (3<<8)  /* only 00 and 01 are valid */
+
+#define PVCR_FVC                   (0x1 << 28)
+#define PVCR_VCSA                  (0x1<<14)
+#define PVCR_CommandDelay          (0xf80)
+#define PVCR_ReadPointer           0x01f00000
+#define PVCR_SlaveAddress          (0x7f)
+
+#else /* ifdef CONFIG_CPU_MONAHANS */
+
+#define PMCR		0x40F00000  /* Power Manager Control Register */
+#define PSSR		0x40F00004  /* Power Manager Sleep Status Register */
+#define PSPR		0x40F00008  /* Power Manager Scratch Pad Register */
+#define PWER		0x40F0000C  /* Power Manager Wake-up Enable Register */
+#define PRER		0x40F00010  /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER		0x40F00014  /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR		0x40F00018  /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR		0x40F0001C  /* Power Manager General Configuration Register */
+#define PGSR0		0x40F00020  /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1		0x40F00024  /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2		0x40F00028  /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3		0x40F0002C  /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR		0x40F00030  /* Reset Controller Status Register */
+
+#define	   PSLR	   0x40F00034	/* Power Manager Sleep Config Register */
+#define	   PSTR	   0x40F00038	/* Power Manager Standby Config Register */
+#define	   PSNR	   0x40F0003C	/* Power Manager Sense Config Register */
+#define	   PVCR	   0x40F00040	/* Power Manager VoltageControl Register */
+#define	   PKWR	   0x40F00050	/* Power Manager KB Wake-up Enable Reg */
+#define	   PKSR	   0x40F00054	/* Power Manager KB Level-Detect Register */
+#define	   PCMD(x) (0x40F00080 + x*4)
+#define	   PCMD0   (0x40F00080 + 0 * 4)
+#define	   PCMD1   (0x40F00080 + 1 * 4)
+#define	   PCMD2   (0x40F00080 + 2 * 4)
+#define	   PCMD3   (0x40F00080 + 3 * 4)
+#define	   PCMD4   (0x40F00080 + 4 * 4)
+#define	   PCMD5   (0x40F00080 + 5 * 4)
+#define	   PCMD6   (0x40F00080 + 6 * 4)
+#define	   PCMD7   (0x40F00080 + 7 * 4)
+#define	   PCMD8   (0x40F00080 + 8 * 4)
+#define	   PCMD9   (0x40F00080 + 9 * 4)
+#define	   PCMD10  (0x40F00080 + 10 * 4)
+#define	   PCMD11  (0x40F00080 + 11 * 4)
+#define	   PCMD12  (0x40F00080 + 12 * 4)
+#define	   PCMD13  (0x40F00080 + 13 * 4)
+#define	   PCMD14  (0x40F00080 + 14 * 4)
+#define	   PCMD15  (0x40F00080 + 15 * 4)
+#define	   PCMD16  (0x40F00080 + 16 * 4)
+#define	   PCMD17  (0x40F00080 + 17 * 4)
+#define	   PCMD18  (0x40F00080 + 18 * 4)
+#define	   PCMD19  (0x40F00080 + 19 * 4)
+#define	   PCMD20  (0x40F00080 + 20 * 4)
+#define	   PCMD21  (0x40F00080 + 21 * 4)
+#define	   PCMD22  (0x40F00080 + 22 * 4)
+#define	   PCMD23  (0x40F00080 + 23 * 4)
+#define	   PCMD24  (0x40F00080 + 24 * 4)
+#define	   PCMD25  (0x40F00080 + 25 * 4)
+#define	   PCMD26  (0x40F00080 + 26 * 4)
+#define	   PCMD27  (0x40F00080 + 27 * 4)
+#define	   PCMD28  (0x40F00080 + 28 * 4)
+#define	   PCMD29  (0x40F00080 + 29 * 4)
+#define	   PCMD30  (0x40F00080 + 30 * 4)
+#define	   PCMD31  (0x40F00080 + 31 * 4)
+
+#define	   PCMD_MBC    (1<<12)
+#define	   PCMD_DCE    (1<<11)
+#define	   PCMD_LC     (1<<10)
+/* FIXME:  PCMD_SQC need be checked.   */
+#define	   PCMD_SQC    (3<<8)  /* currently only bit 8 is changerable, */
+				/* bit 9 should be 0 all day. */
+#define PVCR_VCSA		   (0x1<<14)
+#define PVCR_CommandDelay	   (0xf80)
+/* define MACRO for Power Manager General Configuration Register (PCFR) */
+#define PCFR_FVC		   (0x1 << 10)
+#define PCFR_PI2C_EN		   (0x1 << 6)
+
+#define PSSR_OTGPH	(1 << 6)	/* OTG Peripheral control Hold */
+#define PSSR_RDH	(1 << 5)	/* Read Disable Hold */
+#define PSSR_PH		(1 << 4)	/* Peripheral Control Hold */
+#define PSSR_VFS	(1 << 2)	/* VDD Fault Status */
+#define PSSR_BFS	(1 << 1)	/* Battery Fault Status */
+#define PSSR_SSS	(1 << 0)	/* Software Sleep Status */
+
+#define PCFR_DS		(1 << 3)	/* Deep Sleep Mode */
+#define PCFR_FS		(1 << 2)	/* Float Static Chip Selects */
+#define PCFR_FP		(1 << 1)	/* Float PCMCIA controls */
+#define PCFR_OPDE	(1 << 0)	/* 3.6864 MHz oscillator power-down enable */
+
+#define RCSR_GPR	(1 << 3)	/* GPIO Reset */
+#define RCSR_SMR	(1 << 2)	/* Sleep Mode */
+#define RCSR_WDR	(1 << 1)	/* Watchdog Reset */
+#define RCSR_HWR	(1 << 0)	/* Hardware Reset */
+
+#endif /* CONFIG_CPU_MONAHANS */
+
+/*
+ * SSP Serial Port Registers
+ */
+#define SSCR0		0x41000000  /* SSP Control Register 0 */
+#define SSCR1		0x41000004  /* SSP Control Register 1 */
+#define SSSR		0x41000008  /* SSP Status Register */
+#define SSITR		0x4100000C  /* SSP Interrupt Test Register */
+#define SSDR		0x41000010  /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
+
+/*
+ * MultiMediaCard (MMC) controller
+ */
+#define MMC_STRPCL	0x41100000  /* Control to start and stop MMC clock */
+#define MMC_STAT	0x41100004  /* MMC Status Register (read only) */
+#define MMC_CLKRT	0x41100008  /* MMC clock rate */
+#define MMC_SPI		0x4110000c  /* SPI mode control bits */
+#define MMC_CMDAT	0x41100010  /* Command/response/data sequence control */
+#define MMC_RESTO	0x41100014  /* Expected response time out */
+#define MMC_RDTO	0x41100018  /* Expected data read time out */
+#define MMC_BLKLEN	0x4110001c  /* Block length of data transaction */
+#define MMC_NOB		0x41100020  /* Number of blocks, for block mode */
+#define MMC_PRTBUF	0x41100024  /* Partial MMC_TXFIFO FIFO written */
+#define MMC_I_MASK	0x41100028  /* Interrupt Mask */
+#define MMC_I_REG	0x4110002c  /* Interrupt Register (read only) */
+#define MMC_CMD		0x41100030  /* Index of current command */
+#define MMC_ARGH	0x41100034  /* MSW part of the current command argument */
+#define MMC_ARGL	0x41100038  /* LSW part of the current command argument */
+#define MMC_RES		0x4110003c  /* Response FIFO (read only) */
+#define MMC_RXFIFO	0x41100040  /* Receive FIFO (read only) */
+#define MMC_TXFIFO	0x41100044  /* Transmit FIFO (write only) */
+
+
+/*
+ * LCD
+ */
+#define LCCR0		0x44000000  /* LCD Controller Control Register 0 */
+#define LCCR1		0x44000004  /* LCD Controller Control Register 1 */
+#define LCCR2		0x44000008  /* LCD Controller Control Register 2 */
+#define LCCR3		0x4400000C  /* LCD Controller Control Register 3 */
+#define DFBR0		0x44000020  /* DMA Channel 0 Frame Branch Register */
+#define DFBR1		0x44000024  /* DMA Channel 1 Frame Branch Register */
+#define LCSR0		0x44000038  /* LCD Controller Status Register */
+#define LCSR1		0x44000034  /* LCD Controller Status Register */
+#define LIIDR		0x4400003C  /* LCD Controller Interrupt ID Register */
+#define TMEDRGBR	0x44000040  /* TMED RGB Seed Register */
+#define TMEDCR		0x44000044  /* TMED Control Register */
+
+#define FDADR0		0x44000200  /* DMA Channel 0 Frame Descriptor Address Register */
+#define FSADR0		0x44000204  /* DMA Channel 0 Frame Source Address Register */
+#define FIDR0		0x44000208  /* DMA Channel 0 Frame ID Register */
+#define LDCMD0		0x4400020C  /* DMA Channel 0 Command Register */
+#define FDADR1		0x44000210  /* DMA Channel 1 Frame Descriptor Address Register */
+#define FSADR1		0x44000214  /* DMA Channel 1 Frame Source Address Register */
+#define FIDR1		0x44000218  /* DMA Channel 1 Frame ID Register */
+#define LDCMD1		0x4400021C  /* DMA Channel 1 Command Register */
+
+#define LCCR0_ENB	(1 << 0)	/* LCD Controller enable */
+#define LCCR0_CMS	(1 << 1)	/* Color = 0, Monochrome = 1 */
+#define LCCR0_SDS	(1 << 2)	/* Single Panel = 0, Dual Panel = 1 */
+#define LCCR0_LDM	(1 << 3)	/* LCD Disable Done Mask */
+#define LCCR0_SFM	(1 << 4)	/* Start of frame mask */
+#define LCCR0_IUM	(1 << 5)	/* Input FIFO underrun mask */
+#define LCCR0_EFM	(1 << 6)	/* End of Frame mask */
+#define LCCR0_PAS	(1 << 7)	/* Passive = 0, Active = 1 */
+#define LCCR0_BLE	(1 << 8)	/* Little Endian = 0, Big Endian = 1 */
+#define LCCR0_DPD	(1 << 9)	/* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
+#define LCCR0_DIS	(1 << 10)	/* LCD Disable */
+#define LCCR0_QDM	(1 << 11)	/* LCD Quick Disable mask */
+#define LCCR0_PDD	(0xff << 12)	/* Palette DMA request delay */
+#define LCCR0_PDD_S	12
+#define LCCR0_BM	(1 << 20)	/* Branch mask */
+#define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
+#if defined(CONFIG_CPU_PXA27X)
+#define LCCR0_LCDT	(1 << 22)	/* LCD Panel Type */
+#define LCCR0_RDSTM	(1 << 23)	/* Read Status Interrupt Mask */
+#define LCCR0_CMDIM	(1 << 24)	/* Command Interrupt Mask */
+#endif
+
+#define LCCR1_PPL	Fld (10, 0)	 /* Pixels Per Line - 1 */
+#define LCCR1_DisWdth(Pixel)		/* Display Width [1..800 pix.]	*/ \
+			(((Pixel) - 1) << FShft (LCCR1_PPL))
+
+#define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization	  */
+#define LCCR1_HorSnchWdth(Tpix)		/* Horizontal Synchronization	  */ \
+					/* pulse Width [1..64 Tpix]	  */ \
+			(((Tpix) - 1) << FShft (LCCR1_HSW))
+
+#define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait	   */
+					/* count - 1 [Tpix]		   */
+#define LCCR1_EndLnDel(Tpix)		/*  End-of-Line Delay		   */ \
+					/*  [1..256 Tpix]		   */ \
+			(((Tpix) - 1) << FShft (LCCR1_ELW))
+
+#define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
+					/* Wait count - 1 [Tpix]	   */
+#define LCCR1_BegLnDel(Tpix)		/*  Beginning-of-Line Delay	   */ \
+					/*  [1..256 Tpix]		   */ \
+			(((Tpix) - 1) << FShft (LCCR1_BLW))
+
+
+#define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1		   */
+#define LCCR2_DisHght(Line)		/*  Display Height [1..1024 lines] */ \
+			(((Line) - 1) << FShft (LCCR2_LPP))
+
+#define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
+					/* Width - 1 [Tln] (L_FCLK)	   */
+#define LCCR2_VrtSnchWdth(Tln)		/*  Vertical Synchronization pulse */ \
+					/*  Width [1..64 Tln]		   */ \
+			(((Tln) - 1) << FShft (LCCR2_VSW))
+
+#define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait	   */
+					/* count [Tln]			   */
+#define LCCR2_EndFrmDel(Tln)		/*  End-of-Frame Delay		   */ \
+					/*  [0..255 Tln]		   */ \
+			((Tln) << FShft (LCCR2_EFW))
+
+#define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
+					/* Wait count [Tln]		   */
+#define LCCR2_BegFrmDel(Tln)		/*  Beginning-of-Frame Delay	   */ \
+					/*  [0..255 Tln]		   */ \
+			((Tln) << FShft (LCCR2_BFW))
+
+#define LCCR3_API	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
+#define LCCR3_API_S	16
+#define LCCR3_VSP	(1 << 20)	/* vertical sync polarity */
+#define LCCR3_HSP	(1 << 21)	/* horizontal sync polarity */
+#define LCCR3_PCP	(1 << 22)	/* pixel clock polarity */
+#define LCCR3_OEP	(1 << 23)	/* output enable polarity */
+#define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
+
+#define LCCR3_PDFOR_0	 (0 << 30)
+#define LCCR3_PDFOR_1	 (1 << 30)
+#define LCCR3_PDFOR_2	 (2 << 30)
+#define LCCR3_PDFOR_3	 (3 << 30)
+
+
+#define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor */
+#define LCCR3_PixClkDiv(Div)		/* Pixel Clock Divisor */ \
+			(((Div) << FShft (LCCR3_PCD)))
+
+
+#define LCCR3_BPP	Fld (3, 24)	/* Bit Per Pixel */
+#define LCCR3_Bpp(Bpp)			/* Bit Per Pixel */ \
+			((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26)))
+
+#define LCCR3_ACB	Fld (8, 8)	/* AC Bias */
+#define LCCR3_Acb(Acb)			/* BAC Bias */ \
+			(((Acb) << FShft (LCCR3_ACB)))
+
+#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization	   */
+					/*  pulse active High		   */
+#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization	   */
+
+#define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
+					/*  active High			   */
+#define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
+					/*  active Low			   */
+
+#define LCSR0_LDD	(1 << 0)	/* LCD Disable Done */
+#define LCSR0_SOF	(1 << 1)	/* Start of frame */
+#define LCSR0_BER	(1 << 2)	/* Bus error */
+#define LCSR0_ABC	(1 << 3)	/* AC Bias count */
+#define LCSR0_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
+#define LCSR0_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
+#define LCSR0_OU	(1 << 6)	/* output FIFO underrun */
+#define LCSR0_QD	(1 << 7)	/* quick disable */
+#define LCSR0_EOF0	(1 << 8)	/* end of frame */
+#define LCSR0_BS	(1 << 9)	/* branch status */
+#define LCSR0_SINT	(1 << 10)	/* subsequent interrupt */
+
+#define LCSR1_SOF1	(1 << 0)
+#define LCSR1_SOF2	(1 << 1)
+#define LCSR1_SOF3	(1 << 2)
+#define LCSR1_SOF4	(1 << 3)
+#define LCSR1_SOF5	(1 << 4)
+#define LCSR1_SOF6	(1 << 5)
+
+#define LCSR1_EOF1	(1 << 8)
+#define LCSR1_EOF2	(1 << 9)
+#define LCSR1_EOF3	(1 << 10)
+#define LCSR1_EOF4	(1 << 11)
+#define LCSR1_EOF5	(1 << 12)
+#define LCSR1_EOF6	(1 << 13)
+
+#define LCSR1_BS1	(1 << 16)
+#define LCSR1_BS2	(1 << 17)
+#define LCSR1_BS3	(1 << 18)
+#define LCSR1_BS4	(1 << 19)
+#define LCSR1_BS5	(1 << 20)
+#define LCSR1_BS6	(1 << 21)
+
+#define LCSR1_IU2	(1 << 25)
+#define LCSR1_IU3	(1 << 26)
+#define LCSR1_IU4	(1 << 27)
+#define LCSR1_IU5	(1 << 28)
+#define LCSR1_IU6	(1 << 29)
+
+#define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
+#if defined(CONFIG_CPU_PXA27X)
+#define LDCMD_SOFINT	(1 << 22)
+#define LDCMD_EOFINT	(1 << 21)
+#endif
+
+/*
+ * Memory controller
+ */
+
+#ifdef CONFIG_CPU_MONAHANS
+
+/* PXA3xx */
+
+/* Static Memory Controller Registers */
+#define	MSC0		0x4A000008 /* Static Memory Control Register 0 */
+#define	MSC1		0x4A00000C /* Static Memory Control Register 1 */
+#define	MECR		0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define	SXCNFG		0x4A00001C /* Synchronous Static Memory Control Register */
+#define	MCMEM0		0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */
+#define	MCATT0		0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define	MCIO0		0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */
+#define	MEMCLKCFG	0x4A000068 /* SCLK speed configuration */
+#define	CSADRCFG0	0x4A000080 /* Address Configuration for chip select 0 */
+#define	CSADRCFG1	0x4A000084 /* Address Configuration for chip select 1 */
+#define	CSADRCFG2	0x4A000088 /* Address Configuration for chip select 2 */
+#define	CSADRCFG3	0x4A00008C /* Address Configuration for chip select 3 */
+#define	CSADRCFG_P	0x4A000090 /* Address Configuration for pcmcia card interface */
+#define	CSMSADRCFG	0x4A0000A0 /* Master Address Configuration Register */
+#define	CLK_RET_DEL	0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */
+#define	ADV_RET_DEL	0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */
+
+/* Dynamic Memory Controller Registers */
+#define	MDCNFG		0x48100000 /* SDRAM Configuration Register 0 */
+#define	MDREFR		0x48100004 /* SDRAM Refresh Control Register */
+#define	FLYCNFG		0x48100020 /* Fly-by DMA DVAL[1:0] polarities */
+#define	MDMRS		0x48100040 /* MRS value to be written to SDRAM */
+#define	DDR_SCAL	0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */
+#define	DDR_HCAL	0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
+#define	DDR_WCAL	0x48100068 /* DDR Write Strobe Calibration Register */
+#define	DMCIER		0x48100070 /* Dynamic MC Interrupt Enable Register. */
+#define	DMCISR		0x48100078 /* Dynamic MC Interrupt Status Register. */
+#define	DDR_DLS		0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */
+#define	EMPI		0x48100090 /* EMPI Control Register */
+#define	RCOMP		0x48100100
+#define	PAD_MA		0x48100110
+#define	PAD_MDMSB	0x48100114
+#define	PAD_MDLSB	0x48100118
+#define	PAD_DMEM	0x4810011c
+#define	PAD_SDCLK	0x48100120
+#define	PAD_SDCS	0x48100124
+#define	PAD_SMEM	0x48100128
+#define	PAD_SCLK	0x4810012C
+#define	TAI		0x48100F00 /* TAI Tavor Address Isolation Register */
+
+/* Some frequently used bits */
+#define MDCNFG_DMAP	0x80000000	/* SDRAM 1GB Memory Map Enable */
+#define MDCNFG_DMCEN	0x40000000	/* Enable Dynamic Memory Controller */
+#define MDCNFG_HWFREQ	0x20000000	/* Hardware Frequency Change Calibration */
+#define MDCNFG_DTYPE	0x400		/* SDRAM Type: 1=DDR SDRAM */
+
+#define MDCNFG_DTC_0	0x0		/* Timing Category of SDRAM */
+#define MDCNFG_DTC_1	0x100
+#define MDCNFG_DTC_2	0x200
+#define MDCNFG_DTC_3	0x300
+
+#define MDCNFG_DRAC_12	0x0		/* Number of Row Access Bits */
+#define MDCNFG_DRAC_13	0x20
+#define MDCNFG_DRAC_14	0x40
+
+#define MDCNFG_DCAC_9	0x0		/* Number of Column Acess Bits */
+#define MDCNFG_DCAC_10	0x08
+#define MDCNFG_DCAC_11	0x10
+
+#define MDCNFG_DBW_16	0x4		/* SDRAM Data Bus width 16bit */
+#define MDCNFG_DCSE1	0x2		/* SDRAM CS 1 Enable */
+#define MDCNFG_DCSE0	0x1		/* SDRAM CS 0 Enable */
+
+
+/* Data Flash Controller Registers */
+
+#define NDCR		0x43100000  /* Data Flash Control register */
+#define NDTR0CS0	0x43100004  /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
+/* #define NDTR0CS1	0x43100008  /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
+#define NDTR1CS0	0x4310000C  /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
+/* #define NDTR1CS1	0x43100010  /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
+#define NDSR		0x43100014  /* Data Controller Status Register */
+#define NDPCR		0x43100018  /* Data Controller Page Count Register */
+#define NDBDR0		0x4310001C  /* Data Controller Bad Block Register 0 */
+#define NDBDR1		0x43100020  /* Data Controller Bad Block Register 1 */
+#define NDDB		0x43100040  /* Data Controller Data Buffer */
+#define NDCB0		0x43100048  /* Data Controller Command Buffer0 */
+#define NDCB1		0x4310004C  /* Data Controller Command Buffer1 */
+#define NDCB2		0x43100050  /* Data Controller Command Buffer2 */
+
+#define NDCR_SPARE_EN	(0x1<<31)
+#define NDCR_ECC_EN	(0x1<<30)
+#define NDCR_DMA_EN	(0x1<<29)
+#define NDCR_ND_RUN	(0x1<<28)
+#define NDCR_DWIDTH_C	(0x1<<27)
+#define NDCR_DWIDTH_M	(0x1<<26)
+#define NDCR_PAGE_SZ	(0x3<<24)
+#define NDCR_NCSX	(0x1<<23)
+#define NDCR_ND_STOP	(0x1<<22)
+/* reserved:
+ * #define NDCR_ND_MODE	(0x3<<21)
+ * #define NDCR_NAND_MODE   0x0 */
+#define NDCR_CLR_PG_CNT	(0x1<<20)
+#define NDCR_CLR_ECC	(0x1<<19)
+#define NDCR_RD_ID_CNT	(0x7<<16)
+#define NDCR_RA_START	(0x1<<15)
+#define NDCR_PG_PER_BLK	(0x1<<14)
+#define NDCR_ND_ARB_EN	(0x1<<12)
+#define NDCR_RDYM	(0x1<<11)
+#define NDCR_CS0_PAGEDM	(0x1<<10)
+#define NDCR_CS1_PAGEDM	(0x1<<9)
+#define NDCR_CS0_CMDDM	(0x1<<8)
+#define NDCR_CS1_CMDDM	(0x1<<7)
+#define NDCR_CS0_BBDM	(0x1<<6)
+#define NDCR_CS1_BBDM	(0x1<<5)
+#define NDCR_DBERRM	(0x1<<4)
+#define NDCR_SBERRM	(0x1<<3)
+#define NDCR_WRDREQM	(0x1<<2)
+#define NDCR_RDDREQM	(0x1<<1)
+#define NDCR_WRCMDREQM	(0x1)
+
+#define NDSR_RDY	(0x1<<11)
+#define NDSR_CS0_PAGED	(0x1<<10)
+#define NDSR_CS1_PAGED	(0x1<<9)
+#define NDSR_CS0_CMDD	(0x1<<8)
+#define NDSR_CS1_CMDD	(0x1<<7)
+#define NDSR_CS0_BBD	(0x1<<6)
+#define NDSR_CS1_BBD	(0x1<<5)
+#define NDSR_DBERR	(0x1<<4)
+#define NDSR_SBERR	(0x1<<3)
+#define NDSR_WRDREQ	(0x1<<2)
+#define NDSR_RDDREQ	(0x1<<1)
+#define NDSR_WRCMDREQ	(0x1)
+
+#define NDCB0_AUTO_RS	(0x1<<25)
+#define NDCB0_CSEL	(0x1<<24)
+#define NDCB0_CMD_TYPE	(0x7<<21)
+#define NDCB0_NC	(0x1<<20)
+#define NDCB0_DBC	(0x1<<19)
+#define NDCB0_ADDR_CYC	(0x7<<16)
+#define NDCB0_CMD2	(0xff<<8)
+#define NDCB0_CMD1	(0xff)
+#define MCMEM(s) MCMEM0
+#define MCATT(s) MCATT0
+#define MCIO(s) MCIO0
+#define MECR_CIT	(1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
+
+/* Maximum values for NAND Interface Timing Registers in DFC clock
+ * periods */
+#define DFC_MAX_tCH	7
+#define DFC_MAX_tCS	7
+#define DFC_MAX_tWH	7
+#define DFC_MAX_tWP	7
+#define DFC_MAX_tRH	7
+#define DFC_MAX_tRP	15
+#define DFC_MAX_tR	65535
+#define DFC_MAX_tWHR	15
+#define DFC_MAX_tAR	15
+
+#define DFC_CLOCK	104		/* DFC Clock is 104 MHz */
+#define DFC_CLK_PER_US	DFC_CLOCK/1000	/* clock period in ns */
+
+#else /* CONFIG_CPU_MONAHANS */
+
+/* PXA2xx */
+
+#define MEMC_BASE	0x48000000  /* Base of Memory Controller */
+#define MDCNFG_OFFSET	0x0
+#define MDREFR_OFFSET	0x4
+#define MSC0_OFFSET	0x8
+#define MSC1_OFFSET	0xC
+#define MSC2_OFFSET	0x10
+#define MECR_OFFSET	0x14
+#define SXLCR_OFFSET	0x18
+#define SXCNFG_OFFSET	0x1C
+#define FLYCNFG_OFFSET	0x20
+#define SXMRS_OFFSET	0x24
+#define MCMEM0_OFFSET	0x28
+#define MCMEM1_OFFSET	0x2C
+#define MCATT0_OFFSET	0x30
+#define MCATT1_OFFSET	0x34
+#define MCIO0_OFFSET	0x38
+#define MCIO1_OFFSET	0x3C
+#define MDMRS_OFFSET	0x40
+
+#define MDCNFG		0x48000000  /* SDRAM Configuration Register 0 */
+#define MDCNFG_DE0	0x00000001
+#define MDCNFG_DE1	0x00000002
+#define MDCNFG_DE2	0x00010000
+#define MDCNFG_DE3	0x00020000
+#define MDCNFG_DWID0	0x00000004
+
+#define MDREFR		0x48000004  /* SDRAM Refresh Control Register */
+#define MSC0		0x48000008  /* Static Memory Control Register 0 */
+#define MSC1		0x4800000C  /* Static Memory Control Register 1 */
+#define MSC2		0x48000010  /* Static Memory Control Register 2 */
+#define MECR		0x48000014  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR		0x48000018  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG		0x4800001C  /* Synchronous Static Memory Control Register */
+#define FLYCNFG		0x48000020
+#define SXMRS		0x48000024  /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0		0x48000028  /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1		0x4800002C  /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0		0x48000030  /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1		0x48000034  /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0		0x48000038  /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1		0x4800003C  /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS		0x48000040  /* MRS value to be written to SDRAM */
+#define BOOT_DEF	0x48000044  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+
+#define MDREFR_ALTREFA	(1 << 31)	/* Exiting Alternate Bus Master Mode Refresh Control */
+#define MDREFR_ALTREFB	(1 << 30)	/* Entering Alternate Bus Master Mode Refresh Control */
+#define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
+#define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
+#define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
+#define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
+
+#if defined(CONFIG_CPU_PXA27X)
+
+#define ARB_CNTRL	0x48000048  /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK	(1<<31)	   /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK		(1<<30)	   /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK		(1<<29)	   /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK	(1<<28)	   /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK		(1<<27)	   /* Be parked with USB when idle */
+#define ARB_LCD_PARK		(1<<26)	   /* Be parked with LCD when idle */
+#define ARB_DMA_PARK		(1<<25)	   /* Be parked with DMA when idle */
+#define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
+#define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
+
+#endif /* CONFIG_CPU_PXA27X */
+
+/* LCD registers */
+#define LCCR4		0x44000010  /* LCD Controller Control Register 4 */
+#define LCCR5		0x44000014  /* LCD Controller Control Register 5 */
+#define FBR0		0x44000020  /* DMA Channel 0 Frame Branch Register */
+#define FBR1		0x44000024  /* DMA Channel 1 Frame Branch Register */
+#define FBR2		0x44000028  /* DMA Channel 2 Frame Branch Register */
+#define FBR3		0x4400002C  /* DMA Channel 3 Frame Branch Register */
+#define FBR4		0x44000030  /* DMA Channel 4 Frame Branch Register */
+#define FDADR2		0x44000220  /* DMA Channel 2 Frame Descriptor Address Register */
+#define FSADR2		0x44000224  /* DMA Channel 2 Frame Source Address Register */
+#define FIDR2		0x44000228  /* DMA Channel 2 Frame ID Register */
+#define LDCMD2		0x4400022C  /* DMA Channel 2 Command Register */
+#define FDADR3		0x44000230  /* DMA Channel 3 Frame Descriptor Address Register */
+#define FSADR3		0x44000234  /* DMA Channel 3 Frame Source Address Register */
+#define FIDR3		0x44000238  /* DMA Channel 3 Frame ID Register */
+#define LDCMD3		0x4400023C  /* DMA Channel 3 Command Register */
+#define FDADR4		0x44000240  /* DMA Channel 4 Frame Descriptor Address Register */
+#define FSADR4		0x44000244  /* DMA Channel 4 Frame Source Address Register */
+#define FIDR4		0x44000248  /* DMA Channel 4 Frame ID Register */
+#define LDCMD4		0x4400024C  /* DMA Channel 4 Command Register */
+#define FDADR5		0x44000250  /* DMA Channel 5 Frame Descriptor Address Register */
+#define FSADR5		0x44000254  /* DMA Channel 5 Frame Source Address Register */
+#define FIDR5		0x44000258  /* DMA Channel 5 Frame ID Register */
+#define LDCMD5		0x4400025C  /* DMA Channel 5 Command Register */
+
+#define OVL1C1		0x44000050  /* Overlay 1 Control Register 1 */
+#define OVL1C2		0x44000060  /* Overlay 1 Control Register 2 */
+#define OVL2C1		0x44000070  /* Overlay 2 Control Register 1 */
+#define OVL2C2		0x44000080  /* Overlay 2 Control Register 2 */
+#define CCR		0x44000090  /* Cursor Control Register */
+
+#define FBR5		0x44000110  /* DMA Channel 5 Frame Branch Register */
+#define FBR6		0x44000114  /* DMA Channel 6 Frame Branch Register */
+
+#define LCCR0_LDDALT	(1<<26)		/* LDD Alternate mapping bit when base pixel is RGBT16 */
+#define LCCR0_OUC	(1<<25)		/* Overlay Underlay Control Bit */
+
+#define LCCR5_SOFM1	(1<<0)		/* Start Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_SOFM2	(1<<1)		/* Start Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_SOFM3	(1<<2)		/* Start Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_SOFM4	(1<<3)		/* Start Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_SOFM5	(1<<4)		/* Start Of Frame Mask for cursor (channel 5) */
+#define LCCR5_SOFM6	(1<<5)		/* Start Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_EOFM1	(1<<8)		/* End Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_EOFM2	(1<<9)		/* End Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_EOFM3	(1<<10)		/* End Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_EOFM4	(1<<11)		/* End Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_EOFM5	(1<<12)		/* End Of Frame Mask for cursor (channel 5) */
+#define LCCR5_EOFM6	(1<<13)		/* End Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_BSM1	(1<<16)		/* Branch mask for Overlay 1 (channel 1) */
+#define LCCR5_BSM2	(1<<17)		/* Branch mask for Overlay 2 (channel 2) */
+#define LCCR5_BSM3	(1<<18)		/* Branch mask for Overlay 2 (channel 3) */
+#define LCCR5_BSM4	(1<<19)		/* Branch mask for Overlay 2 (channel 4) */
+#define LCCR5_BSM5	(1<<20)		/* Branch mask for cursor (channel 5) */
+#define LCCR5_BSM6	(1<<21)		/* Branch mask for data command	 (channel 6) */
+
+#define LCCR5_IUM1	(1<<24)		/* Input FIFO Underrun Mask for Overlay 1  */
+#define LCCR5_IUM2	(1<<25)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM3	(1<<26)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM4	(1<<27)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM5	(1<<28)		/* Input FIFO Underrun Mask for cursor */
+#define LCCR5_IUM6	(1<<29)		/* Input FIFO Underrun Mask for data command */
+
+#define OVL1C1_O1EN	(1<<31)		/* Enable bit for Overlay 1 */
+#define OVL2C1_O2EN	(1<<31)		/* Enable bit for Overlay 2 */
+#define CCR_CEN		(1<<31)		/* Enable bit for Cursor */
+
+/* Keypad controller */
+
+#define KPC		0x41500000 /* Keypad Interface Control register */
+#define KPDK		0x41500008 /* Keypad Interface Direct Key register */
+#define KPREC		0x41500010 /* Keypad Intefcace Rotary Encoder register */
+#define KPMK		0x41500018 /* Keypad Intefcace Matrix Key register */
+#define KPAS		0x41500020 /* Keypad Interface Automatic Scan register */
+#define KPASMKP0	0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
+#define KPASMKP1	0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
+#define KPASMKP2	0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
+#define KPASMKP3	0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
+#define KPKDI		0x41500048 /* Keypad Interface Key Debounce Interval register */
+
+#define KPC_AS		(0x1 << 30)  /* Automatic Scan bit */
+#define KPC_ASACT	(0x1 << 29)  /* Automatic Scan on Activity */
+#define KPC_MI		(0x1 << 22)  /* Matrix interrupt bit */
+#define KPC_IMKP	(0x1 << 21)  /* Ignore Multiple Key Press */
+#define KPC_MS7		(0x1 << 20)  /* Matrix scan line 7 */
+#define KPC_MS6		(0x1 << 19)  /* Matrix scan line 6 */
+#define KPC_MS5		(0x1 << 18)  /* Matrix scan line 5 */
+#define KPC_MS4		(0x1 << 17)  /* Matrix scan line 4 */
+#define KPC_MS3		(0x1 << 16)  /* Matrix scan line 3 */
+#define KPC_MS2		(0x1 << 15)  /* Matrix scan line 2 */
+#define KPC_MS1		(0x1 << 14)  /* Matrix scan line 1 */
+#define KPC_MS0		(0x1 << 13)  /* Matrix scan line 0 */
+#define KPC_ME		(0x1 << 12)  /* Matrix Keypad Enable */
+#define KPC_MIE		(0x1 << 11)  /* Matrix Interrupt Enable */
+#define KPC_DK_DEB_SEL	(0x1 <<	 9)  /* Direct Key Debounce select */
+#define KPC_DI		(0x1 <<	 5)  /* Direct key interrupt bit */
+#define KPC_DEE0	(0x1 <<	 2)  /* Rotary Encoder 0 Enable */
+#define KPC_DE		(0x1 <<	 1)  /* Direct Keypad Enable */
+#define KPC_DIE		(0x1 <<	 0)  /* Direct Keypad interrupt Enable */
+
+#define KPDK_DKP	(0x1 << 31)
+#define KPDK_DK7	(0x1 <<	 7)
+#define KPDK_DK6	(0x1 <<	 6)
+#define KPDK_DK5	(0x1 <<	 5)
+#define KPDK_DK4	(0x1 <<	 4)
+#define KPDK_DK3	(0x1 <<	 3)
+#define KPDK_DK2	(0x1 <<	 2)
+#define KPDK_DK1	(0x1 <<	 1)
+#define KPDK_DK0	(0x1 <<	 0)
+
+#define KPREC_OF1	(0x1 << 31)
+#define kPREC_UF1	(0x1 << 30)
+#define KPREC_OF0	(0x1 << 15)
+#define KPREC_UF0	(0x1 << 14)
+
+#define KPMK_MKP	(0x1 << 31)
+#define KPAS_SO		(0x1 << 31)
+#define KPASMKPx_SO	(0x1 << 31)
+
+#define GPIO113_BIT	(1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
+#define PSLR		0x40F00034
+#define PSTR		0x40F00038  /* Power Manager Standby Configuration Reg */
+#define PSNR		0x40F0003C  /* Power Manager Sense Configuration Reg */
+#define PVCR		0x40F00040  /* Power Manager Voltage Change Control Reg */
+#define PKWR		0x40F00050  /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR		0x40F00054  /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4		0x40A00080  /* */
+#define OSCR4		0x40A00040  /* OS Timer Counter Register */
+#define OMCR4		0x40A000C0  /* */
+
+#endif	/* CONFIG_CPU_PXA27X */
+
+#endif	/* _PXA_REGS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h
new file mode 100644
index 000000000..d759aea60
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/pxa.h
@@ -0,0 +1,29 @@
+/*
+ * PXA common functions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__PXA_H__
+#define	__PXA_H__
+
+#define PXA255_A0	0x00000106
+#define PXA250_C0	0x00000105
+#define PXA250_B2	0x00000104
+#define PXA250_B1	0x00000103
+#define PXA250_B0	0x00000102
+#define PXA250_A1	0x00000101
+#define PXA250_A0	0x00000100
+#define PXA210_C0	0x00000125
+#define PXA210_B2	0x00000124
+#define PXA210_B1	0x00000123
+#define PXA210_B0	0x00000122
+
+int cpu_is_pxa25x(void);
+int cpu_is_pxa27x(void);
+uint32_t pxa_get_cpu_revision(void);
+void pxa2xx_dram_init(void);
+
+#endif	/* __PXA_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-mmc.h
new file mode 100644
index 000000000..1b18eea0c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-mmc.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __REGS_MMC_H__
+#define __REGS_MMC_H__
+
+#define MMC0_BASE	0x41100000
+#define MMC1_BASE	0x42000000
+
+int pxa_mmc_register(int card_index);
+
+struct pxa_mmc_regs {
+	uint32_t	strpcl;
+	uint32_t	stat;
+	uint32_t	clkrt;
+	uint32_t	spi;
+	uint32_t	cmdat;
+	uint32_t	resto;
+	uint32_t	rdto;
+	uint32_t	blklen;
+	uint32_t	nob;
+	uint32_t	prtbuf;
+	uint32_t	i_mask;
+	uint32_t	i_reg;
+	uint32_t	cmd;
+	uint32_t	argh;
+	uint32_t	argl;
+	uint32_t	res;
+	uint32_t	rxfifo;
+	uint32_t	txfifo;
+};
+
+/* MMC_STRPCL */
+#define MMC_STRPCL_STOP_CLK		(1 << 0)
+#define MMC_STRPCL_START_CLK		(1 << 1)
+
+/* MMC_STAT */
+#define MMC_STAT_END_CMD_RES		(1 << 13)
+#define MMC_STAT_PRG_DONE		(1 << 12)
+#define MMC_STAT_DATA_TRAN_DONE		(1 << 11)
+#define MMC_STAT_CLK_EN			(1 << 8)
+#define MMC_STAT_RECV_FIFO_FULL		(1 << 7)
+#define MMC_STAT_XMIT_FIFO_EMPTY	(1 << 6)
+#define MMC_STAT_RES_CRC_ERROR		(1 << 5)
+#define MMC_STAT_SPI_READ_ERROR_TOKEN	(1 << 4)
+#define MMC_STAT_CRC_READ_ERROR		(1 << 3)
+#define MMC_STAT_CRC_WRITE_ERROR	(1 << 2)
+#define MMC_STAT_TIME_OUT_RESPONSE	(1 << 1)
+#define MMC_STAT_READ_TIME_OUT		(1 << 0)
+
+/* MMC_CLKRT */
+#define MMC_CLKRT_20MHZ			0
+#define MMC_CLKRT_10MHZ			1
+#define MMC_CLKRT_5MHZ			2
+#define MMC_CLKRT_2_5MHZ		3
+#define MMC_CLKRT_1_25MHZ		4
+#define MMC_CLKRT_0_625MHZ		5
+#define MMC_CLKRT_0_3125MHZ		6
+
+/* MMC_SPI */
+#define MMC_SPI_EN			(1 << 0)
+#define MMC_SPI_CS_EN			(1 << 2)
+#define MMC_SPI_CS_ADDRESS		(1 << 3)
+#define MMC_SPI_CRC_ON			(1 << 1)
+
+/* MMC_CMDAT */
+#define MMC_CMDAT_SD_4DAT		(1 << 8)
+#define MMC_CMDAT_MMC_DMA_EN		(1 << 7)
+#define MMC_CMDAT_INIT			(1 << 6)
+#define MMC_CMDAT_BUSY			(1 << 5)
+#define MMC_CMDAT_BCR			(MMC_CMDAT_BUSY | MMC_CMDAT_INIT)
+#define MMC_CMDAT_STREAM		(1 << 4)
+#define MMC_CMDAT_WRITE			(1 << 3)
+#define MMC_CMDAT_DATA_EN		(1 << 2)
+#define MMC_CMDAT_R0			0
+#define MMC_CMDAT_R1			1
+#define MMC_CMDAT_R2			2
+#define MMC_CMDAT_R3			3
+
+/* MMC_RESTO */
+#define MMC_RES_TO_MAX_MASK		0x7f
+
+/* MMC_RDTO */
+#define MMC_READ_TO_MAX_MASK		0xffff
+
+/* MMC_BLKLEN */
+#define MMC_BLK_LEN_MAX_MASK		0x3ff
+
+/* MMC_PRTBUF */
+#define MMC_PRTBUF_BUF_PART_FULL	(1 << 0)
+
+/* MMC_I_MASK */
+#define MMC_I_MASK_TXFIFO_WR_REQ	(1 << 6)
+#define MMC_I_MASK_RXFIFO_RD_REQ	(1 << 5)
+#define MMC_I_MASK_CLK_IS_OFF		(1 << 4)
+#define MMC_I_MASK_STOP_CMD		(1 << 3)
+#define MMC_I_MASK_END_CMD_RES		(1 << 2)
+#define MMC_I_MASK_PRG_DONE		(1 << 1)
+#define MMC_I_MASK_DATA_TRAN_DONE	(1 << 0)
+#define MMC_I_MASK_ALL			0x7f
+
+
+/* MMC_I_REG */
+#define MMC_I_REG_TXFIFO_WR_REQ		(1 << 6)
+#define MMC_I_REG_RXFIFO_RD_REQ		(1 << 5)
+#define MMC_I_REG_CLK_IS_OFF		(1 << 4)
+#define MMC_I_REG_STOP_CMD		(1 << 3)
+#define MMC_I_REG_END_CMD_RES		(1 << 2)
+#define MMC_I_REG_PRG_DONE		(1 << 1)
+#define MMC_I_REG_DATA_TRAN_DONE	(1 << 0)
+
+/* MMC_CMD */
+#define MMC_CMD_INDEX_MAX		0x6f
+
+#define MMC_R1_IDLE_STATE		0x01
+#define MMC_R1_ERASE_STATE		0x02
+#define MMC_R1_ILLEGAL_CMD		0x04
+#define MMC_R1_COM_CRC_ERR		0x08
+#define MMC_R1_ERASE_SEQ_ERR		0x01
+#define MMC_R1_ADDR_ERR			0x02
+#define MMC_R1_PARAM_ERR		0x04
+
+#define MMC_R1B_WP_ERASE_SKIP		0x0002
+#define MMC_R1B_ERR			0x0004
+#define MMC_R1B_CC_ERR			0x0008
+#define MMC_R1B_CARD_ECC_ERR		0x0010
+#define MMC_R1B_WP_VIOLATION		0x0020
+#define MMC_R1B_ERASE_PARAM		0x0040
+#define MMC_R1B_OOR			0x0080
+#define MMC_R1B_IDLE_STATE		0x0100
+#define MMC_R1B_ERASE_RESET		0x0200
+#define MMC_R1B_ILLEGAL_CMD		0x0400
+#define MMC_R1B_COM_CRC_ERR		0x0800
+#define MMC_R1B_ERASE_SEQ_ERR		0x1000
+#define MMC_R1B_ADDR_ERR		0x2000
+#define MMC_R1B_PARAM_ERR		0x4000
+
+#endif	/* __REGS_MMC_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-uart.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-uart.h
new file mode 100644
index 000000000..313a6919c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-uart.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__REGS_UART_H__
+#define	__REGS_UART_H__
+
+#define	FFUART_BASE		0x40100000
+#define	BTUART_BASE		0x40200000
+#define	STUART_BASE		0x40700000
+#define	HWUART_BASE		0x41600000
+
+struct pxa_uart_regs {
+	union {
+		uint32_t	thr;
+		uint32_t	rbr;
+		uint32_t	dll;
+	};
+	union {
+		uint32_t	ier;
+		uint32_t	dlh;
+	};
+	union {
+		uint32_t	fcr;
+		uint32_t	iir;
+	};
+	uint32_t	lcr;
+	uint32_t	mcr;
+	uint32_t	lsr;
+	uint32_t	msr;
+	uint32_t	spr;
+	uint32_t	isr;
+};
+
+#define	IER_DMAE	(1 << 7)
+#define	IER_UUE		(1 << 6)
+#define	IER_NRZE	(1 << 5)
+#define	IER_RTIOE	(1 << 4)
+#define	IER_MIE		(1 << 3)
+#define	IER_RLSE	(1 << 2)
+#define	IER_TIE		(1 << 1)
+#define	IER_RAVIE	(1 << 0)
+
+#define	IIR_FIFOES1	(1 << 7)
+#define	IIR_FIFOES0	(1 << 6)
+#define	IIR_TOD		(1 << 3)
+#define	IIR_IID2	(1 << 2)
+#define	IIR_IID1	(1 << 1)
+#define	IIR_IP		(1 << 0)
+
+#define	FCR_ITL2	(1 << 7)
+#define	FCR_ITL1	(1 << 6)
+#define	FCR_RESETTF	(1 << 2)
+#define	FCR_RESETRF	(1 << 1)
+#define	FCR_TRFIFOE	(1 << 0)
+#define	FCR_ITL_1	0
+#define	FCR_ITL_8	(FCR_ITL1)
+#define	FCR_ITL_16	(FCR_ITL2)
+#define	FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
+
+#define	LCR_DLAB	(1 << 7)
+#define	LCR_SB		(1 << 6)
+#define	LCR_STKYP	(1 << 5)
+#define	LCR_EPS		(1 << 4)
+#define	LCR_PEN		(1 << 3)
+#define	LCR_STB		(1 << 2)
+#define	LCR_WLS1	(1 << 1)
+#define	LCR_WLS0	(1 << 0)
+
+#define	LSR_FIFOE	(1 << 7)
+#define	LSR_TEMT	(1 << 6)
+#define	LSR_TDRQ	(1 << 5)
+#define	LSR_BI		(1 << 4)
+#define	LSR_FE		(1 << 3)
+#define	LSR_PE		(1 << 2)
+#define	LSR_OE		(1 << 1)
+#define	LSR_DR		(1 << 0)
+
+#define	MCR_LOOP	(1 << 4)
+#define	MCR_OUT2	(1 << 3)
+#define	MCR_OUT1	(1 << 2)
+#define	MCR_RTS		(1 << 1)
+#define	MCR_DTR		(1 << 0)
+
+#define	MSR_DCD		(1 << 7)
+#define	MSR_RI		(1 << 6)
+#define	MSR_DSR		(1 << 5)
+#define	MSR_CTS		(1 << 4)
+#define	MSR_DDCD	(1 << 3)
+#define	MSR_TERI	(1 << 2)
+#define	MSR_DDSR	(1 << 1)
+#define	MSR_DCTS	(1 << 0)
+
+#endif	/* __REGS_UART_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-usb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-usb.h
new file mode 100644
index 000000000..90ffbf470
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-pxa/regs-usb.h
@@ -0,0 +1,147 @@
+/*
+ * PXA25x UDC definitions
+ *
+ * Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __REGS_USB_H__
+#define __REGS_USB_H__
+
+struct pxa25x_udc_regs {
+	/* UDC Control Register */
+	uint32_t	udccr; /* 0x000 */
+	uint32_t	reserved1;
+
+	/* UDC Control Function Register */
+	uint32_t	udccfr; /* 0x008 */
+	uint32_t	reserved2;
+
+	/* UDC Endpoint Control/Status Registers */
+	uint32_t	udccs[16]; /* 0x010 - 0x04c */
+
+	/* UDC Interrupt Control/Status Registers */
+	uint32_t	uicr0; /* 0x050 */
+	uint32_t	uicr1; /* 0x054 */
+	uint32_t	usir0; /* 0x058 */
+	uint32_t	usir1; /* 0x05c */
+
+	/* UDC Frame Number/Byte Count Registers */
+	uint32_t	ufnrh;  /* 0x060 */
+	uint32_t	ufnrl;  /* 0x064 */
+	uint32_t	ubcr2;  /* 0x068 */
+	uint32_t	ubcr4;  /* 0x06c */
+	uint32_t	ubcr7;  /* 0x070 */
+	uint32_t	ubcr9;  /* 0x074 */
+	uint32_t	ubcr12; /* 0x078 */
+	uint32_t	ubcr14; /* 0x07c */
+
+	/* UDC Endpoint Data Registers */
+	uint32_t	uddr0;  /* 0x080 */
+	uint32_t	reserved3[7];
+	uint32_t	uddr5;  /* 0x0a0 */
+	uint32_t	reserved4[7];
+	uint32_t	uddr10; /* 0x0c0 */
+	uint32_t	reserved5[7];
+	uint32_t	uddr15; /* 0x0e0 */
+	uint32_t	reserved6[7];
+	uint32_t	uddr1;  /* 0x100 */
+	uint32_t	reserved7[31];
+	uint32_t	uddr2;  /* 0x180 */
+	uint32_t	reserved8[31];
+	uint32_t	uddr3;  /* 0x200 */
+	uint32_t	reserved9[127];
+	uint32_t	uddr4;  /* 0x400 */
+	uint32_t	reserved10[127];
+	uint32_t	uddr6;  /* 0x600 */
+	uint32_t	reserved11[31];
+	uint32_t	uddr7;  /* 0x680 */
+	uint32_t	reserved12[31];
+	uint32_t	uddr8;  /* 0x700 */
+	uint32_t	reserved13[127];
+	uint32_t	uddr9;  /* 0x900 */
+	uint32_t	reserved14[127];
+	uint32_t	uddr11; /* 0xb00 */
+	uint32_t	reserved15[31];
+	uint32_t	uddr12; /* 0xb80 */
+	uint32_t	reserved16[31];
+	uint32_t	uddr13; /* 0xc00 */
+	uint32_t	reserved17[127];
+	uint32_t	uddr14; /* 0xe00 */
+
+};
+
+#define PXA25X_UDC_BASE		0x40600000
+
+#define UDCCR_UDE		(1 << 0)
+#define UDCCR_UDA		(1 << 1)
+#define UDCCR_RSM		(1 << 2)
+#define UDCCR_RESIR		(1 << 3)
+#define UDCCR_SUSIR		(1 << 4)
+#define UDCCR_SRM		(1 << 5)
+#define UDCCR_RSTIR		(1 << 6)
+#define UDCCR_REM		(1 << 7)
+
+/* Bulk IN endpoint 1/6/11 */
+#define UDCCS_BI_TSP		(1 << 7)
+#define UDCCS_BI_FST		(1 << 5)
+#define UDCCS_BI_SST		(1 << 4)
+#define UDCCS_BI_TUR		(1 << 3)
+#define UDCCS_BI_FTF		(1 << 2)
+#define UDCCS_BI_TPC		(1 << 1)
+#define UDCCS_BI_TFS		(1 << 0)
+
+/* Bulk OUT endpoint 2/7/12 */
+#define UDCCS_BO_RSP		(1 << 7)
+#define UDCCS_BO_RNE		(1 << 6)
+#define UDCCS_BO_FST		(1 << 5)
+#define UDCCS_BO_SST		(1 << 4)
+#define UDCCS_BO_DME		(1 << 3)
+#define UDCCS_BO_RPC		(1 << 1)
+#define UDCCS_BO_RFS		(1 << 0)
+
+/* Isochronous OUT endpoint 4/9/14 */
+#define UDCCS_IO_RSP		(1 << 7)
+#define UDCCS_IO_RNE		(1 << 6)
+#define UDCCS_IO_DME		(1 << 3)
+#define UDCCS_IO_ROF		(1 << 2)
+#define UDCCS_IO_RPC		(1 << 1)
+#define UDCCS_IO_RFS		(1 << 0)
+
+/* Control endpoint 0 */
+#define UDCCS0_OPR		(1 << 0)
+#define UDCCS0_IPR		(1 << 1)
+#define UDCCS0_FTF		(1 << 2)
+#define UDCCS0_DRWF		(1 << 3)
+#define UDCCS0_SST		(1 << 4)
+#define UDCCS0_FST		(1 << 5)
+#define UDCCS0_RNE		(1 << 6)
+#define UDCCS0_SA		(1 << 7)
+
+#define UICR0_IM0		(1 << 0)
+
+#define USIR0_IR0		(1 << 0)
+#define USIR0_IR1		(1 << 1)
+#define USIR0_IR2		(1 << 2)
+#define USIR0_IR3		(1 << 3)
+#define USIR0_IR4		(1 << 4)
+#define USIR0_IR5		(1 << 5)
+#define USIR0_IR6		(1 << 6)
+#define USIR0_IR7		(1 << 7)
+
+#define UDCCFR_AREN		(1 << 7) /* ACK response enable (now) */
+#define UDCCFR_ACM		(1 << 2) /* ACK control mode (wait for AREN) */
+/*
+ * Intel(R) PXA255 Processor Specification, September 2003 (page 31)
+ * define new "must be one" bits in UDCCFR (see Table 12-13.)
+ */
+#define UDCCFR_MB1		(0xff & ~(UDCCFR_AREN | UDCCFR_ACM))
+
+#define UFNRH_SIR		(1 << 7)	/* SOF interrupt request */
+#define UFNRH_SIM		(1 << 6)	/* SOF interrupt mask */
+#define UFNRH_IPE14		(1 << 5)	/* ISO packet error, ep14 */
+#define UFNRH_IPE9		(1 << 4)	/* ISO packet error, ep9 */
+#define UFNRH_IPE4		(1 << 3)	/* ISO packet error, ep4 */
+
+#endif /* __REGS_USB_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h
new file mode 100644
index 000000000..463654efd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h
@@ -0,0 +1,147 @@
+/*
+ *  Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *  Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ *  SPDX-License-Identifier:     GPL-2.0
+ */
+
+#ifndef __EHCI_RMOBILE_H__
+#define __EHCI_RMOBILE_H__
+
+/* Register offset */
+#define OHCI_OFFSET	0x00
+#define OHCI_SIZE	0x1000
+#define EHCI_OFFSET	0x1000
+#define EHCI_SIZE	0x1000
+
+#define EHCI_USBCMD	(EHCI_OFFSET + 0x0020)
+
+/* USBCTR */
+#define DIRPD		(1 << 8)
+#define PLL_RST		(1 << 2)
+#define PCICLK_MASK	(1 << 1)
+#define USBH_RST	(1 << 0)
+
+/* CMND_STS */
+#define SERREN		(1 << 8)
+#define PERREN		(1 << 6)
+#define MASTEREN	(1 << 2)
+#define MEMEN		(1 << 1)
+
+/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */
+#define PCIAHB_WIN_PREFETCH	((1 << 1)|(1 << 0))
+
+/* AHBPCI_WIN1_CTR */
+#define PCIWIN1_PCICMD		((1 << 3)|(1 << 1))
+#define AHB_CFG_AHBPCI		0x40000000
+#define AHB_CFG_HOST		0x80000000
+
+/* AHBPCI_WIN2_CTR */
+#define PCIWIN2_PCICMD		((1 << 2)|(1 << 1))
+
+/* PCI_INT_ENABLE */
+#define USBH_PMEEN		(1 << 19)
+#define USBH_INTBEN		(1 << 17)
+#define USBH_INTAEN		(1 << 16)
+
+/* AHB_BUS_CTR */
+#define SMODE_READY_CTR		(1 << 17)
+#define SMODE_READ_BURST	(1 << 16)
+#define MMODE_HBUSREQ		(1 << 7)
+#define MMODE_BOUNDARY		((1 << 6)|(1 << 5))
+#define MMODE_BURST_WIDTH	((1 << 4)|(1 << 3))
+#define MMODE_SINGLE_MODE	((1 << 4)|(1 << 3))
+#define MMODE_WR_INCR		(1 << 2)
+#define MMODE_BYTE_BURST	(1 << 1)
+#define MMODE_HTRANS		(1 << 0)
+
+/* PCI_ARBITER_CTR */
+#define PCIBUS_PARK_TIMER       0x00FF0000
+#define PCIBUS_PARK_TIMER_SET   0x00070000
+#define PCIBP_MODE		(1 << 12)
+#define PCIREQ7                 (1 << 7)
+#define PCIREQ6                 (1 << 6)
+#define PCIREQ5                 (1 << 5)
+#define PCIREQ4                 (1 << 4)
+#define PCIREQ3                 (1 << 3)
+#define PCIREQ2                 (1 << 2)
+#define PCIREQ1                 (1 << 1)
+#define PCIREQ0                 (1 << 0)
+
+#define SMSTPCR7        0xE615014C
+#define SMSTPCR703      (1 << 3)
+
+/* Init AHB master and slave functions of the host logic */
+#define AHB_BUS_CTR_INIT \
+	(SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \
+	 MMODE_BYTE_BURST | MMODE_HTRANS)
+
+#define USBCTR_WIN_SIZE_1GB	0x800
+
+/* PCI Configuration Registers */
+#define PCI_CONF_OHCI_OFFSET	0x10000
+#define PCI_CONF_EHCI_OFFSET	0x10100
+struct ahb_pciconf {
+	u32 vid_did;
+	u32 cmnd_sts;
+	u32 rev;
+	u32 cache_line;
+	u32 basead;
+};
+
+/* PCI Configuration Registers for AHB-PCI Bridge Registers */
+#define PCI_CONF_AHBPCI_OFFSET	0x10000
+struct ahbconf_pci_bridge {
+	u32 vid_did;		/* 0x00 */
+	u32 cmnd_sts;
+	u32 revid_cc;
+	u32 cls_lt_ht_bist;
+	u32 basead;		/* 0x10 */
+	u32 win1_basead;
+	u32 win2_basead;
+	u32 dummy0[5];
+	u32 ssvdi_ssid;		/* 0x2C */
+	u32 dummy1[4];
+	u32 intr_line_pin;
+};
+
+/* AHB-PCI Bridge PCI Communication Registers */
+#define AHBPCI_OFFSET	0x10800
+struct ahbcom_pci_bridge {
+	u32 pciahb_win1_ctr;	/* 0x00 */
+	u32 pciahb_win2_ctr;
+	u32 pciahb_dct_ctr;
+	u32 dummy0;
+	u32 ahbpci_win1_ctr;	/* 0x10 */
+	u32 ahbpci_win2_ctr;
+	u32 dummy1;
+	u32 ahbpci_dct_ctr;
+	u32 pci_int_enable;	/* 0x20 */
+	u32 pci_int_status;
+	u32 dummy2[2];
+	u32 ahb_bus_ctr;	/* 0x30 */
+	u32 usbctr;
+	u32 dummy3[2];
+	u32 pci_arbiter_ctr;	/* 0x40 */
+	u32 dummy4;
+	u32 pci_unit_rev;	/* 0x48 */
+};
+
+struct rmobile_ehci_reg {
+	u32 hciversion;		/* hciversion/caplength */
+	u32 hcsparams;		/* hcsparams */
+	u32 hccparams;		/* hccparams */
+	u32 hcsp_portroute;	/* hcsp_portroute */
+	u32 usbcmd;		/* usbcmd */
+	u32 usbsts;		/* usbsts */
+	u32 usbintr;		/* usbintr */
+	u32 frindex;		/* frindex */
+	u32 ctrldssegment;	/* ctrldssegment */
+	u32 periodiclistbase;	/* periodiclistbase */
+	u32 asynclistaddr;	/* asynclistaddr */
+	u32 dummy[9];
+	u32 configflag;		/* configflag */
+	u32 portsc;		/* portsc */
+};
+
+#endif /* __EHCI_RMOBILE_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/gpio.h
new file mode 100644
index 000000000..560e9f42d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/gpio.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#if defined(CONFIG_SH73A0)
+#include "sh73a0-gpio.h"
+void sh73a0_pinmux_init(void);
+#elif defined(CONFIG_R8A7740)
+#include "r8a7740-gpio.h"
+void r8a7740_pinmux_init(void);
+#elif defined(CONFIG_R8A7790)
+#include "r8a7790-gpio.h"
+void r8a7790_pinmux_init(void);
+#elif defined(CONFIG_R8A7791)
+#include "r8a7791-gpio.h"
+void r8a7791_pinmux_init(void);
+#endif
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/irqs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/irqs.h
new file mode 100644
index 000000000..dcb714f4d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/irqs.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+#define NR_IRQS         1024
+
+/* GIC */
+#define gic_spi(nr)		((nr) + 32)
+
+/* INTCA */
+#define evt2irq(evt)		(((evt) >> 5) - 16)
+#define irq2evt(irq)		(((irq) + 16) << 5)
+
+/* INTCS */
+#define INTCS_VECT_BASE		0x2200
+#define INTCS_VECT(n, vect)	INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt)	evt2irq(INTCS_VECT_BASE + (evt))
+
+#endif /* __ASM_MACH_IRQS_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h
new file mode 100644
index 000000000..9d447abb9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h
@@ -0,0 +1,584 @@
+/*
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __ASM_R8A7740_H__
+#define __ASM_R8A7740_H__
+
+/*
+ * MD_CKx pin
+ */
+#define MD_CK2	(1 << 2)
+#define MD_CK1	(1 << 1)
+#define MD_CK0	(1 << 0)
+
+/*
+ * Pin Function Controller:
+ *	GPIO_FN_xx - GPIO used to select pin function
+ *	GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	/* PORT */
+	GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+	GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+	GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+	GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+	GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+	GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+	GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+	GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+	GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+	GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+	GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+	GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+	GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+	GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+	GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+	GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+	GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+	GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+	GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+	GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+	GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+	GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+	GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+	GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
+
+	GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
+	GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
+
+	GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+	GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+	GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+	GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+	GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+	GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+	GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+	GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
+
+	GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
+	GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
+
+	GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
+	GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
+
+	GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+	GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+	GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+	GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+	GPIO_PORT210, GPIO_PORT211,
+
+	/* IRQ */
+	GPIO_FN_IRQ0_PORT2,	GPIO_FN_IRQ0_PORT13,
+	GPIO_FN_IRQ1,
+	GPIO_FN_IRQ2_PORT11,	GPIO_FN_IRQ2_PORT12,
+	GPIO_FN_IRQ3_PORT10,	GPIO_FN_IRQ3_PORT14,
+	GPIO_FN_IRQ4_PORT15,	GPIO_FN_IRQ4_PORT172,
+	GPIO_FN_IRQ5_PORT0,	GPIO_FN_IRQ5_PORT1,
+	GPIO_FN_IRQ6_PORT121,	GPIO_FN_IRQ6_PORT173,
+	GPIO_FN_IRQ7_PORT120,	GPIO_FN_IRQ7_PORT209,
+	GPIO_FN_IRQ8,
+	GPIO_FN_IRQ9_PORT118,	GPIO_FN_IRQ9_PORT210,
+	GPIO_FN_IRQ10,
+	GPIO_FN_IRQ11,
+	GPIO_FN_IRQ12_PORT42,	GPIO_FN_IRQ12_PORT97,
+	GPIO_FN_IRQ13_PORT64,	GPIO_FN_IRQ13_PORT98,
+	GPIO_FN_IRQ14_PORT63,	GPIO_FN_IRQ14_PORT99,
+	GPIO_FN_IRQ15_PORT62,	GPIO_FN_IRQ15_PORT100,
+	GPIO_FN_IRQ16_PORT68,	GPIO_FN_IRQ16_PORT211,
+	GPIO_FN_IRQ17,
+	GPIO_FN_IRQ18,
+	GPIO_FN_IRQ19,
+	GPIO_FN_IRQ20,
+	GPIO_FN_IRQ21,
+	GPIO_FN_IRQ22,
+	GPIO_FN_IRQ23,
+	GPIO_FN_IRQ24,
+	GPIO_FN_IRQ25,
+	GPIO_FN_IRQ26_PORT58,	GPIO_FN_IRQ26_PORT81,
+	GPIO_FN_IRQ27_PORT57,	GPIO_FN_IRQ27_PORT168,
+	GPIO_FN_IRQ28_PORT56,	GPIO_FN_IRQ28_PORT169,
+	GPIO_FN_IRQ29_PORT50,	GPIO_FN_IRQ29_PORT170,
+	GPIO_FN_IRQ30_PORT49,	GPIO_FN_IRQ30_PORT171,
+	GPIO_FN_IRQ31_PORT41,	GPIO_FN_IRQ31_PORT167,
+
+	/* Function */
+
+	/* DBGT */
+	GPIO_FN_DBGMDT2,	GPIO_FN_DBGMDT1,	GPIO_FN_DBGMDT0,
+	GPIO_FN_DBGMD10,	GPIO_FN_DBGMD11,	GPIO_FN_DBGMD20,
+	GPIO_FN_DBGMD21,
+
+	/* FSI */
+	GPIO_FN_FSIAISLD_PORT0,		/* FSIAISLD Port 0/5 */
+	GPIO_FN_FSIAISLD_PORT5,
+	GPIO_FN_FSIASPDIF_PORT9,	/* FSIASPDIF Port 9/18 */
+	GPIO_FN_FSIASPDIF_PORT18,
+	GPIO_FN_FSIAOSLD1,	GPIO_FN_FSIAOSLD2,
+	GPIO_FN_FSIAOLR,	GPIO_FN_FSIAOBT,
+	GPIO_FN_FSIAOSLD,	GPIO_FN_FSIAOMC,
+	GPIO_FN_FSIACK,		GPIO_FN_FSIAILR,
+	GPIO_FN_FSIAIBT,
+
+	/* FMSI */
+	GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
+	GPIO_FN_FMSISLD_PORT6,
+	GPIO_FN_FMSIILR,	GPIO_FN_FMSIIBT,
+	GPIO_FN_FMSIOLR,	GPIO_FN_FMSIOBT,
+	GPIO_FN_FMSICK,		GPIO_FN_FMSOILR,
+	GPIO_FN_FMSOIBT,	GPIO_FN_FMSOOLR,
+	GPIO_FN_FMSOOBT,	GPIO_FN_FMSOSLD,
+	GPIO_FN_FMSOCK,
+
+	/* SCIFA0 */
+	GPIO_FN_SCIFA0_SCK,	GPIO_FN_SCIFA0_CTS,
+	GPIO_FN_SCIFA0_RTS,	GPIO_FN_SCIFA0_RXD,
+	GPIO_FN_SCIFA0_TXD,
+
+	/* SCIFA1 */
+	GPIO_FN_SCIFA1_CTS,	GPIO_FN_SCIFA1_SCK,
+	GPIO_FN_SCIFA1_RXD,	GPIO_FN_SCIFA1_TXD,
+	GPIO_FN_SCIFA1_RTS,
+
+	/* SCIFA2 */
+	GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
+	GPIO_FN_SCIFA2_SCK_PORT199,
+	GPIO_FN_SCIFA2_RXD,	GPIO_FN_SCIFA2_TXD,
+	GPIO_FN_SCIFA2_CTS,	GPIO_FN_SCIFA2_RTS,
+
+	/* SCIFA3 */
+	GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
+	GPIO_FN_SCIFA3_SCK_PORT116,
+	GPIO_FN_SCIFA3_CTS_PORT117,
+	GPIO_FN_SCIFA3_RXD_PORT174,
+	GPIO_FN_SCIFA3_TXD_PORT175,
+
+	GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
+	GPIO_FN_SCIFA3_SCK_PORT158,
+	GPIO_FN_SCIFA3_CTS_PORT162,
+	GPIO_FN_SCIFA3_RXD_PORT159,
+	GPIO_FN_SCIFA3_TXD_PORT160,
+
+	/* SCIFA4 */
+	GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
+	GPIO_FN_SCIFA4_TXD_PORT13,
+
+	GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
+	GPIO_FN_SCIFA4_TXD_PORT203,
+
+	GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
+	GPIO_FN_SCIFA4_TXD_PORT93,
+
+	GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
+	GPIO_FN_SCIFA4_SCK_PORT205,
+
+	/* SCIFA5 */
+	GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
+	GPIO_FN_SCIFA5_RXD_PORT10,
+
+	GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
+	GPIO_FN_SCIFA5_TXD_PORT208,
+
+	GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
+	GPIO_FN_SCIFA5_RXD_PORT92,
+
+	GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
+	GPIO_FN_SCIFA5_SCK_PORT206,
+
+	/* SCIFA6 */
+	GPIO_FN_SCIFA6_SCK,	GPIO_FN_SCIFA6_RXD,	GPIO_FN_SCIFA6_TXD,
+
+	/* SCIFA7 */
+	GPIO_FN_SCIFA7_TXD,	GPIO_FN_SCIFA7_RXD,
+
+	/* SCIFAB */
+	GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
+	GPIO_FN_SCIFB_RXD_PORT191,
+	GPIO_FN_SCIFB_TXD_PORT192,
+	GPIO_FN_SCIFB_RTS_PORT186,
+	GPIO_FN_SCIFB_CTS_PORT187,
+
+	GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
+	GPIO_FN_SCIFB_RXD_PORT3,
+	GPIO_FN_SCIFB_TXD_PORT4,
+	GPIO_FN_SCIFB_RTS_PORT172,
+	GPIO_FN_SCIFB_CTS_PORT173,
+
+	/* LCD0 */
+	GPIO_FN_LCDC0_SELECT,
+	GPIO_FN_LCD0_D0,	GPIO_FN_LCD0_D1,	GPIO_FN_LCD0_D2,
+	GPIO_FN_LCD0_D3,	GPIO_FN_LCD0_D4,	GPIO_FN_LCD0_D5,
+	GPIO_FN_LCD0_D6,	GPIO_FN_LCD0_D7,	GPIO_FN_LCD0_D8,
+	GPIO_FN_LCD0_D9,	GPIO_FN_LCD0_D10,	GPIO_FN_LCD0_D11,
+	GPIO_FN_LCD0_D12,	GPIO_FN_LCD0_D13,	GPIO_FN_LCD0_D14,
+	GPIO_FN_LCD0_D15,	GPIO_FN_LCD0_D16,	GPIO_FN_LCD0_D17,
+	GPIO_FN_LCD0_DON,	GPIO_FN_LCD0_VCPWC,	GPIO_FN_LCD0_VEPWC,
+
+	GPIO_FN_LCD0_DCK,	GPIO_FN_LCD0_VSYN, /* for RGB */
+	GPIO_FN_LCD0_HSYN,	GPIO_FN_LCD0_DISP, /* for RGB */
+
+	GPIO_FN_LCD0_WR,	GPIO_FN_LCD0_RD, /* for SYS */
+	GPIO_FN_LCD0_CS,	GPIO_FN_LCD0_RS, /* for SYS */
+
+	GPIO_FN_LCD0_D18_PORT163,	GPIO_FN_LCD0_D19_PORT162,
+	GPIO_FN_LCD0_D20_PORT161,	GPIO_FN_LCD0_D21_PORT158,
+	GPIO_FN_LCD0_D22_PORT160,	GPIO_FN_LCD0_D23_PORT159,
+	GPIO_FN_LCD0_LCLK_PORT165,	 /* MSEL5CR_6_1 */
+
+	GPIO_FN_LCD0_D18_PORT40,	GPIO_FN_LCD0_D19_PORT4,
+	GPIO_FN_LCD0_D20_PORT3,		GPIO_FN_LCD0_D21_PORT2,
+	GPIO_FN_LCD0_D22_PORT0,		GPIO_FN_LCD0_D23_PORT1,
+	GPIO_FN_LCD0_LCLK_PORT102,	/* MSEL5CR_6_0 */
+
+	/* LCD1 */
+	GPIO_FN_LCDC1_SELECT,
+	GPIO_FN_LCD1_D0,	GPIO_FN_LCD1_D1,	GPIO_FN_LCD1_D2,
+	GPIO_FN_LCD1_D3,	GPIO_FN_LCD1_D4,	GPIO_FN_LCD1_D5,
+	GPIO_FN_LCD1_D6,	GPIO_FN_LCD1_D7,	GPIO_FN_LCD1_D8,
+	GPIO_FN_LCD1_D9,	GPIO_FN_LCD1_D10,	GPIO_FN_LCD1_D11,
+	GPIO_FN_LCD1_D12,	GPIO_FN_LCD1_D13,	GPIO_FN_LCD1_D14,
+	GPIO_FN_LCD1_D15,	GPIO_FN_LCD1_D16,	GPIO_FN_LCD1_D17,
+	GPIO_FN_LCD1_D18,	GPIO_FN_LCD1_D19,	GPIO_FN_LCD1_D20,
+	GPIO_FN_LCD1_D21,	GPIO_FN_LCD1_D22,	GPIO_FN_LCD1_D23,
+	GPIO_FN_LCD1_DON,	GPIO_FN_LCD1_VCPWC,
+	GPIO_FN_LCD1_LCLK,	GPIO_FN_LCD1_VEPWC,
+
+	GPIO_FN_LCD1_DCK,	GPIO_FN_LCD1_VSYN, /* for RGB */
+	GPIO_FN_LCD1_HSYN,	GPIO_FN_LCD1_DISP, /* for RGB */
+
+	GPIO_FN_LCD1_WR,	GPIO_FN_LCD1_RD, /* for SYS */
+	GPIO_FN_LCD1_CS,	GPIO_FN_LCD1_RS, /* for SYS */
+
+	/* RSPI */
+	GPIO_FN_RSPI_SSL0_A,	GPIO_FN_RSPI_SSL1_A,
+	GPIO_FN_RSPI_SSL2_A,	GPIO_FN_RSPI_SSL3_A,
+	GPIO_FN_RSPI_MOSI_A,	GPIO_FN_RSPI_MISO_A,
+	GPIO_FN_RSPI_CK_A,
+
+	/* VIO CKO */
+	GPIO_FN_VIO_CKO1,
+	GPIO_FN_VIO_CKO2,
+	GPIO_FN_VIO_CKO_1,
+	GPIO_FN_VIO_CKO,
+
+	/* VIO0 */
+	GPIO_FN_VIO0_D0,	GPIO_FN_VIO0_D1,	GPIO_FN_VIO0_D2,
+	GPIO_FN_VIO0_D3,	GPIO_FN_VIO0_D4,	GPIO_FN_VIO0_D5,
+	GPIO_FN_VIO0_D6,	GPIO_FN_VIO0_D7,	GPIO_FN_VIO0_D8,
+	GPIO_FN_VIO0_D9,	GPIO_FN_VIO0_D10,	GPIO_FN_VIO0_D11,
+	GPIO_FN_VIO0_D12,	GPIO_FN_VIO0_VD,	GPIO_FN_VIO0_HD,
+	GPIO_FN_VIO0_CLK,	GPIO_FN_VIO0_FIELD,
+
+	GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
+	GPIO_FN_VIO0_D14_PORT25,
+	GPIO_FN_VIO0_D15_PORT24,
+
+	GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
+	GPIO_FN_VIO0_D14_PORT95,
+	GPIO_FN_VIO0_D15_PORT96,
+
+	/* VIO1 */
+	GPIO_FN_VIO1_D0,	GPIO_FN_VIO1_D1,	GPIO_FN_VIO1_D2,
+	GPIO_FN_VIO1_D3,	GPIO_FN_VIO1_D4,	GPIO_FN_VIO1_D5,
+	GPIO_FN_VIO1_D6,	GPIO_FN_VIO1_D7,	GPIO_FN_VIO1_VD,
+	GPIO_FN_VIO1_HD,	GPIO_FN_VIO1_CLK,	GPIO_FN_VIO1_FIELD,
+
+	/* TPU0 */
+	GPIO_FN_TPU0TO0,	GPIO_FN_TPU0TO1,
+	GPIO_FN_TPU0TO3,
+	GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
+	GPIO_FN_TPU0TO2_PORT202,
+
+	/* SSP1 0 */
+	GPIO_FN_STP0_IPD0,	GPIO_FN_STP0_IPD1,	GPIO_FN_STP0_IPD2,
+	GPIO_FN_STP0_IPD3,	GPIO_FN_STP0_IPD4,	GPIO_FN_STP0_IPD5,
+	GPIO_FN_STP0_IPD6,	GPIO_FN_STP0_IPD7,	GPIO_FN_STP0_IPEN,
+	GPIO_FN_STP0_IPCLK,	GPIO_FN_STP0_IPSYNC,
+
+	/* SSP1 1 */
+	GPIO_FN_STP1_IPD1,	GPIO_FN_STP1_IPD2,	GPIO_FN_STP1_IPD3,
+	GPIO_FN_STP1_IPD4,	GPIO_FN_STP1_IPD5,	GPIO_FN_STP1_IPD6,
+	GPIO_FN_STP1_IPD7,	GPIO_FN_STP1_IPCLK,	GPIO_FN_STP1_IPSYNC,
+
+	GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
+	GPIO_FN_STP1_IPEN_PORT187,
+
+	GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
+	GPIO_FN_STP1_IPEN_PORT193,
+
+	/* SIM */
+	GPIO_FN_SIM_RST,	GPIO_FN_SIM_CLK,
+	GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
+	GPIO_FN_SIM_D_PORT199,
+
+	/* SDHI0 */
+	GPIO_FN_SDHI0_D0,	GPIO_FN_SDHI0_D1,	GPIO_FN_SDHI0_D2,
+	GPIO_FN_SDHI0_D3,	GPIO_FN_SDHI0_CD,	GPIO_FN_SDHI0_WP,
+	GPIO_FN_SDHI0_CMD,	GPIO_FN_SDHI0_CLK,
+
+	/* SDHI1 */
+	GPIO_FN_SDHI1_D0,	GPIO_FN_SDHI1_D1,	GPIO_FN_SDHI1_D2,
+	GPIO_FN_SDHI1_D3,	GPIO_FN_SDHI1_CD,	GPIO_FN_SDHI1_WP,
+	GPIO_FN_SDHI1_CMD,	GPIO_FN_SDHI1_CLK,
+
+	/* SDHI2 */
+	GPIO_FN_SDHI2_D0,	GPIO_FN_SDHI2_D1,	GPIO_FN_SDHI2_D2,
+	GPIO_FN_SDHI2_D3,	GPIO_FN_SDHI2_CLK,	GPIO_FN_SDHI2_CMD,
+
+	GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
+	GPIO_FN_SDHI2_WP_PORT25,
+
+	GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
+	GPIO_FN_SDHI2_CD_PORT202,
+
+	/* MSIOF2 */
+	GPIO_FN_MSIOF2_TXD,	GPIO_FN_MSIOF2_RXD,	GPIO_FN_MSIOF2_TSCK,
+	GPIO_FN_MSIOF2_SS2,	GPIO_FN_MSIOF2_TSYNC,	GPIO_FN_MSIOF2_SS1,
+	GPIO_FN_MSIOF2_MCK1,	GPIO_FN_MSIOF2_MCK0,	GPIO_FN_MSIOF2_RSYNC,
+	GPIO_FN_MSIOF2_RSCK,
+
+	/* KEYSC */
+	GPIO_FN_KEYIN4,		GPIO_FN_KEYIN5,
+	GPIO_FN_KEYIN6,		GPIO_FN_KEYIN7,
+	GPIO_FN_KEYOUT0,	GPIO_FN_KEYOUT1,	GPIO_FN_KEYOUT2,
+	GPIO_FN_KEYOUT3,	GPIO_FN_KEYOUT4,	GPIO_FN_KEYOUT5,
+	GPIO_FN_KEYOUT6,	GPIO_FN_KEYOUT7,
+
+	GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
+	GPIO_FN_KEYIN1_PORT44,
+	GPIO_FN_KEYIN2_PORT45,
+	GPIO_FN_KEYIN3_PORT46,
+
+	GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
+	GPIO_FN_KEYIN1_PORT57,
+	GPIO_FN_KEYIN2_PORT56,
+	GPIO_FN_KEYIN3_PORT55,
+
+	/* VOU */
+	GPIO_FN_DV_D0,	GPIO_FN_DV_D1,	GPIO_FN_DV_D2,	GPIO_FN_DV_D3,
+	GPIO_FN_DV_D4,	GPIO_FN_DV_D5,	GPIO_FN_DV_D6,	GPIO_FN_DV_D7,
+	GPIO_FN_DV_D8,	GPIO_FN_DV_D9,	GPIO_FN_DV_D10,	GPIO_FN_DV_D11,
+	GPIO_FN_DV_D12,	GPIO_FN_DV_D13,	GPIO_FN_DV_D14,	GPIO_FN_DV_D15,
+	GPIO_FN_DV_CLK,
+	GPIO_FN_DV_VSYNC,
+	GPIO_FN_DV_HSYNC,
+
+	/* MEMC */
+	GPIO_FN_MEMC_AD0,	GPIO_FN_MEMC_AD1,	GPIO_FN_MEMC_AD2,
+	GPIO_FN_MEMC_AD3,	GPIO_FN_MEMC_AD4,	GPIO_FN_MEMC_AD5,
+	GPIO_FN_MEMC_AD6,	GPIO_FN_MEMC_AD7,	GPIO_FN_MEMC_AD8,
+	GPIO_FN_MEMC_AD9,	GPIO_FN_MEMC_AD10,	GPIO_FN_MEMC_AD11,
+	GPIO_FN_MEMC_AD12,	GPIO_FN_MEMC_AD13,	GPIO_FN_MEMC_AD14,
+	GPIO_FN_MEMC_AD15,	GPIO_FN_MEMC_CS0,	GPIO_FN_MEMC_INT,
+	GPIO_FN_MEMC_NWE,	GPIO_FN_MEMC_NOE,
+
+	GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
+	GPIO_FN_MEMC_ADV,
+	GPIO_FN_MEMC_WAIT,
+	GPIO_FN_MEMC_BUSCLK,
+
+	GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
+	GPIO_FN_MEMC_DREQ0,
+	GPIO_FN_MEMC_DREQ1,
+	GPIO_FN_MEMC_A0,
+
+	/* MMC */
+	GPIO_FN_MMC0_D0_PORT68,		GPIO_FN_MMC0_D1_PORT69,
+	GPIO_FN_MMC0_D2_PORT70,		GPIO_FN_MMC0_D3_PORT71,
+	GPIO_FN_MMC0_D4_PORT72,		GPIO_FN_MMC0_D5_PORT73,
+	GPIO_FN_MMC0_D6_PORT74,		GPIO_FN_MMC0_D7_PORT75,
+	GPIO_FN_MMC0_CLK_PORT66,
+	GPIO_FN_MMC0_CMD_PORT67,	/* MSEL4CR_15_0 */
+
+	GPIO_FN_MMC1_D0_PORT149,	GPIO_FN_MMC1_D1_PORT148,
+	GPIO_FN_MMC1_D2_PORT147,	GPIO_FN_MMC1_D3_PORT146,
+	GPIO_FN_MMC1_D4_PORT145,	GPIO_FN_MMC1_D5_PORT144,
+	GPIO_FN_MMC1_D6_PORT143,	GPIO_FN_MMC1_D7_PORT142,
+	GPIO_FN_MMC1_CLK_PORT103,
+	GPIO_FN_MMC1_CMD_PORT104,	/* MSEL4CR_15_1 */
+
+	/* MSIOF0 */
+	GPIO_FN_MSIOF0_SS1,	GPIO_FN_MSIOF0_SS2,
+	GPIO_FN_MSIOF0_RXD,	GPIO_FN_MSIOF0_TXD,
+	GPIO_FN_MSIOF0_MCK0,	GPIO_FN_MSIOF0_MCK1,
+	GPIO_FN_MSIOF0_RSYNC,	GPIO_FN_MSIOF0_RSCK,
+	GPIO_FN_MSIOF0_TSCK,	GPIO_FN_MSIOF0_TSYNC,
+
+	/* MSIOF1 */
+	GPIO_FN_MSIOF1_RSCK,	GPIO_FN_MSIOF1_RSYNC,
+	GPIO_FN_MSIOF1_MCK0,	GPIO_FN_MSIOF1_MCK1,
+
+	GPIO_FN_MSIOF1_SS2_PORT116,	GPIO_FN_MSIOF1_SS1_PORT117,
+	GPIO_FN_MSIOF1_RXD_PORT118,	GPIO_FN_MSIOF1_TXD_PORT119,
+	GPIO_FN_MSIOF1_TSYNC_PORT120,
+	GPIO_FN_MSIOF1_TSCK_PORT121,	/* MSEL4CR_10_0 */
+
+	GPIO_FN_MSIOF1_SS1_PORT67,	GPIO_FN_MSIOF1_TSCK_PORT72,
+	GPIO_FN_MSIOF1_TSYNC_PORT73,	GPIO_FN_MSIOF1_TXD_PORT74,
+	GPIO_FN_MSIOF1_RXD_PORT75,
+	GPIO_FN_MSIOF1_SS2_PORT202,	/* MSEL4CR_10_1 */
+
+	/* GPIO */
+	GPIO_FN_GPO0,	GPIO_FN_GPI0,
+	GPIO_FN_GPO1,	GPIO_FN_GPI1,
+
+	/* USB0 */
+	GPIO_FN_USB0_OCI,	GPIO_FN_USB0_PPON,	GPIO_FN_VBUS,
+
+	/* USB1 */
+	GPIO_FN_USB1_OCI,	GPIO_FN_USB1_PPON,
+
+	/* BBIF1 */
+	GPIO_FN_BBIF1_RXD,	GPIO_FN_BBIF1_TXD,	GPIO_FN_BBIF1_TSYNC,
+	GPIO_FN_BBIF1_TSCK,	GPIO_FN_BBIF1_RSCK,	GPIO_FN_BBIF1_RSYNC,
+	GPIO_FN_BBIF1_FLOW,	GPIO_FN_BBIF1_RX_FLOW_N,
+
+	/* BBIF2 */
+	GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
+	GPIO_FN_BBIF2_RXD2_PORT60,
+	GPIO_FN_BBIF2_TSYNC2_PORT6,
+	GPIO_FN_BBIF2_TSCK2_PORT59,
+
+	GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
+	GPIO_FN_BBIF2_TXD2_PORT183,
+	GPIO_FN_BBIF2_TSCK2_PORT89,
+	GPIO_FN_BBIF2_TSYNC2_PORT184,
+
+	/* BSC / FLCTL / PCMCIA */
+	GPIO_FN_CS0,	GPIO_FN_CS2,	GPIO_FN_CS4,
+	GPIO_FN_CS5B,	GPIO_FN_CS6A,
+	GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
+	GPIO_FN_CS5A_PORT19,
+	GPIO_FN_IOIS16, /* ? */
+
+	GPIO_FN_A0,	GPIO_FN_A1,	GPIO_FN_A2,	GPIO_FN_A3,
+	GPIO_FN_A4_FOE,		/* share with FLCTL */
+	GPIO_FN_A5_FCDE,	/* share with FLCTL */
+	GPIO_FN_A6,	GPIO_FN_A7,	GPIO_FN_A8,	GPIO_FN_A9,
+	GPIO_FN_A10,	GPIO_FN_A11,	GPIO_FN_A12,	GPIO_FN_A13,
+	GPIO_FN_A14,	GPIO_FN_A15,	GPIO_FN_A16,	GPIO_FN_A17,
+	GPIO_FN_A18,	GPIO_FN_A19,	GPIO_FN_A20,	GPIO_FN_A21,
+	GPIO_FN_A22,	GPIO_FN_A23,	GPIO_FN_A24,	GPIO_FN_A25,
+	GPIO_FN_A26,
+
+	GPIO_FN_D0_NAF0,	GPIO_FN_D1_NAF1,	/* share with FLCTL */
+	GPIO_FN_D2_NAF2,	GPIO_FN_D3_NAF3,	/* share with FLCTL */
+	GPIO_FN_D4_NAF4,	GPIO_FN_D5_NAF5,	/* share with FLCTL */
+	GPIO_FN_D6_NAF6,	GPIO_FN_D7_NAF7,	/* share with FLCTL */
+	GPIO_FN_D8_NAF8,	GPIO_FN_D9_NAF9,	/* share with FLCTL */
+	GPIO_FN_D10_NAF10,	GPIO_FN_D11_NAF11,	/* share with FLCTL */
+	GPIO_FN_D12_NAF12,	GPIO_FN_D13_NAF13,	/* share with FLCTL */
+	GPIO_FN_D14_NAF14,	GPIO_FN_D15_NAF15,	/* share with FLCTL */
+
+	GPIO_FN_D16,	GPIO_FN_D17,	GPIO_FN_D18,	GPIO_FN_D19,
+	GPIO_FN_D20,	GPIO_FN_D21,	GPIO_FN_D22,	GPIO_FN_D23,
+	GPIO_FN_D24,	GPIO_FN_D25,	GPIO_FN_D26,	GPIO_FN_D27,
+	GPIO_FN_D28,	GPIO_FN_D29,	GPIO_FN_D30,	GPIO_FN_D31,
+
+	GPIO_FN_WE0_FWE,	/* share with FLCTL */
+	GPIO_FN_WE1,
+	GPIO_FN_WE2_ICIORD,	/* share with PCMCIA */
+	GPIO_FN_WE3_ICIOWR,	/* share with PCMCIA */
+	GPIO_FN_CKO,	GPIO_FN_BS,	GPIO_FN_RDWR,
+	GPIO_FN_RD_FSC,		/* share with FLCTL */
+	GPIO_FN_WAIT_PORT177,	/* WAIT Port 90/177 */
+	GPIO_FN_WAIT_PORT90,
+
+	GPIO_FN_FCE0,	GPIO_FN_FCE1,	GPIO_FN_FRB, /* FLCTL */
+
+	/* IRDA */
+	GPIO_FN_IRDA_FIRSEL,	GPIO_FN_IRDA_IN,	GPIO_FN_IRDA_OUT,
+
+	/* ATAPI */
+	GPIO_FN_IDE_D0,		GPIO_FN_IDE_D1,		GPIO_FN_IDE_D2,
+	GPIO_FN_IDE_D3,		GPIO_FN_IDE_D4,		GPIO_FN_IDE_D5,
+	GPIO_FN_IDE_D6,		GPIO_FN_IDE_D7,		GPIO_FN_IDE_D8,
+	GPIO_FN_IDE_D9,		GPIO_FN_IDE_D10,	GPIO_FN_IDE_D11,
+	GPIO_FN_IDE_D12,	GPIO_FN_IDE_D13,	GPIO_FN_IDE_D14,
+	GPIO_FN_IDE_D15,	GPIO_FN_IDE_A0,		GPIO_FN_IDE_A1,
+	GPIO_FN_IDE_A2,		GPIO_FN_IDE_CS0,	GPIO_FN_IDE_CS1,
+	GPIO_FN_IDE_IOWR,	GPIO_FN_IDE_IORD,	GPIO_FN_IDE_IORDY,
+	GPIO_FN_IDE_INT,	GPIO_FN_IDE_RST,	GPIO_FN_IDE_DIRECTION,
+	GPIO_FN_IDE_EXBUF_ENB,	GPIO_FN_IDE_IODACK,	GPIO_FN_IDE_IODREQ,
+
+	/* RMII */
+	GPIO_FN_RMII_CRS_DV,	GPIO_FN_RMII_RX_ER,	GPIO_FN_RMII_RXD0,
+	GPIO_FN_RMII_RXD1,	GPIO_FN_RMII_TX_EN,	GPIO_FN_RMII_TXD0,
+	GPIO_FN_RMII_MDC,	GPIO_FN_RMII_TXD1,	GPIO_FN_RMII_MDIO,
+	GPIO_FN_RMII_REF50CK,	/* for RMII */
+	GPIO_FN_RMII_REF125CK,	/* for GMII */
+
+	/* GEther */
+	GPIO_FN_ET_TX_CLK,	GPIO_FN_ET_TX_EN,	GPIO_FN_ET_ETXD0,
+	GPIO_FN_ET_ETXD1,	GPIO_FN_ET_ETXD2,	GPIO_FN_ET_ETXD3,
+	GPIO_FN_ET_ETXD4,	GPIO_FN_ET_ETXD5, /* for GEther */
+	GPIO_FN_ET_ETXD6,	GPIO_FN_ET_ETXD7, /* for GEther */
+	GPIO_FN_ET_COL,		GPIO_FN_ET_TX_ER,
+	GPIO_FN_ET_RX_CLK,	GPIO_FN_ET_RX_DV,
+	GPIO_FN_ET_ERXD0,	GPIO_FN_ET_ERXD1,
+	GPIO_FN_ET_ERXD2,	GPIO_FN_ET_ERXD3,
+	GPIO_FN_ET_ERXD4,	GPIO_FN_ET_ERXD5, /* for GEther */
+	GPIO_FN_ET_ERXD6,	GPIO_FN_ET_ERXD7, /* for GEther */
+	GPIO_FN_ET_RX_ER,	GPIO_FN_ET_CRS,
+	GPIO_FN_ET_MDC,		GPIO_FN_ET_MDIO,
+	GPIO_FN_ET_LINK,	GPIO_FN_ET_PHY_INT,
+	GPIO_FN_ET_WOL,		GPIO_FN_ET_GTX_CLK,
+
+	/* DMA0 */
+	GPIO_FN_DREQ0,		GPIO_FN_DACK0,
+
+	/* DMA1 */
+	GPIO_FN_DREQ1,		GPIO_FN_DACK1,
+
+	/* SYSC */
+	GPIO_FN_RESETOUTS,
+	GPIO_FN_RESETP_PULLUP,
+	GPIO_FN_RESETP_PLAIN,
+
+	/* SDENC */
+	GPIO_FN_SDENC_CPG,
+	GPIO_FN_SDENC_DV_CLKI,
+
+	/* IRREM */
+	GPIO_FN_IROUT,
+
+	/* DEBUG */
+	GPIO_FN_EDEBGREQ_PULLDOWN,
+	GPIO_FN_EDEBGREQ_PULLUP,
+
+	GPIO_FN_TRACEAUD_FROM_VIO,
+	GPIO_FN_TRACEAUD_FROM_LCDC0,
+	GPIO_FN_TRACEAUD_FROM_MEMC,
+};
+
+#endif /* __ASM_R8A7740_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740.h
new file mode 100644
index 000000000..8f179505d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7740.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_R8A7740_H
+#define __ASM_ARCH_R8A7740_H
+
+/*
+ * R8A7740 I/O Addresses
+ */
+
+#define MERAM_BASE	0xE5580000
+#define DDRP_BASE	0xC12A0000
+#define HPB_BASE	0xE6000000
+#define RWDT0_BASE	0xE6020000
+#define RWDT1_BASE	0xE6030000
+#define GPIO_BASE	0xE6050000
+#define CMT1_BASE	0xE6138000
+#define CPG_BASE	0xE6150000
+#define SYSC_BASE	0xE6180000
+#define SDHI0_BASE	0xE6850000
+#define SDHI1_BASE	0xE6860000
+#define MMCIF_BASE	0xE6BD0000
+#define SCIF5_BASE	0xE6CB0000
+#define SCIF6_BASE	0xE6CC0000
+#define DBSC_BASE	0xFE400000
+#define BSC_BASE	0xFEC10000
+#define I2C0_BASE	0xFFF20000
+#define I2C1_BASE	0xE6C20000
+#define TMU_BASE	0xFFF80000
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct r8a7740_rwdt {
+	u16 rwtcnt0;	/* 0x00 */
+	u16 dummy0;		/* 0x02 */
+	u16 rwtcsra0;	/* 0x04 */
+	u16 dummy1;		/* 0x06 */
+	u16 rwtcsrb0;	/* 0x08 */
+	u16 dummy2;		/* 0x0A */
+};
+
+/* HPB Semaphore Control Registers */
+struct r8a7740_hpb {
+	u32 hpbctrl0;
+	u32 hpbctrl1;
+	u32 hpbctrl2;
+	u32 cccr;
+	u32 dummy0; /* 0x20 */
+	u32 hpbctrl4;
+	u32 hpbctrl5;
+};
+
+/* CPG */
+struct r8a7740_cpg {
+	u32 frqcra;
+	u32 frqcrb;
+	u32 vclkcr1;
+	u32 vclkcr2;
+	u32 fmsickcr;
+	u32 fmsockcr;
+	u32 fsiackcr;
+	u32 dummy0; /* 0x1c */
+	u32 rtstbcr;
+	u32 systbcr;
+	u32 pllc01cr;
+	u32 pllc2cr;
+	u32 mstpsr0;
+	u32 dummy1; /* 0x34 */
+	u32 mstpsr1;
+	u32 mstpsr5;
+	u32 mstpsr2;
+	u32 dummy2; /* 0x44 */
+	u32 mstpsr3;
+	u32 mstpsr4;
+	u32 dummy3; /* 0x50 */
+	u32 astat;
+	u32 dummy4[4]; /* 0x58 .. 0x64 */
+	u32 ztrckcr;
+	u32 dummy5[5]; /* 0x6c .. 0x7c */
+	u32 subckcr;
+	u32 spuckcr;
+	u32 vouckcr;
+	u32 usbckcr;
+	u32 dummy6[3]; /* 0x90 .. 0x98 */
+	u32 stprckcr;
+	u32 srcr0;
+	u32 dummy7; /* 0xa4 */
+	u32 srcr1;
+	u32 dummy8; /* 0xac */
+	u32 srcr2;
+	u32 dummy9; /* 0xb4 */
+	u32 srcr3;
+	u32 srcr4;
+	u32 dummy10; /* 0xc0 */
+	u32 srcr5;
+	u32 pllc01stpcr;
+	u32 dummy11[5]; /* 0xcc .. 0xdc */
+	u32 frqcrc;
+	u32 frqcrd;
+	u32 dummy12[10]; /* 0xe8 .. 0x10c */
+	u32 rmstpcr0;
+	u32 rmstpcr1;
+	u32 rmstpcr2;
+	u32 rmstpcr3;
+	u32 rmstpcr4;
+	u32 rmstpcr5;
+	u32 dummy13[2]; /* 0x128 .. 0x12c */
+	u32 smstpcr0;
+	u32 smstpcr1;
+	u32 smstpcr2;
+	u32 smstpcr3;
+	u32 smstpcr4;
+	u32 smstpcr5;
+};
+
+/* BSC */
+struct r8a7740_bsc {
+	u32 cmncr;
+	u32 cs0bcr;
+	u32 cs2bcr;
+	u32 dummy0; /* 0x0c */
+	u32 cs4bcr;
+	u32 cs5abcr;
+	u32 cs5bbcr;
+	u32 cs6abcr;
+	u32 dummy1; /* 0x20 */
+	u32 cs0wcr;
+	u32 cs2wcr;
+	u32 dummy2; /* 0x2c */
+	u32 cs4wcr;
+	u32 cs5awcr;
+	u32 cs5bwcr;
+	u32 cs6awcr;
+	u32 dummy3[5]; /* 0x40 .. 0x50 */
+	u32 rbwtcnt;
+	u32 busycr;
+	u32 dummy4[5]; /* 0x5c .. 0x6c */
+	u32 bromtimcr;
+	u32 dummy5[7]; /* 0x74 .. 0x8c */
+	u32 bptcr00;
+	u32 bptcr01;
+	u32 bptcr02;
+	u32 bptcr03;
+	u32 bptcr04;
+	u32 bptcr05;
+	u32 bptcr06;
+	u32 bptcr07;
+	u32 bptcr08;
+	u32 bptcr09;
+	u32 bptcr10;
+	u32 bptcr11;
+	u32 bptcr12;
+	u32 bptcr13;
+	u32 bptcr14;
+	u32 bptcr15;
+	u32 bptcr16;
+	u32 bptcr17;
+	u32 bptcr18;
+	u32 bptcr19;
+	u32 bptcr20;
+	u32 bptcr21;
+	u32 bptcr22;
+	u32 bptcr23;
+	u32 bptcr24;
+	u32 bptcr25;
+	u32 bptcr26;
+	u32 bptcr27;
+	u32 bptcr28;
+	u32 bptcr29;
+	u32 bptcr30;
+	u32 bptcr31;
+	u32 bswcr;
+	u32 dummy6[68]; /* 0x114 .. 0x220 */
+	u32 cs0wcr2;
+	u32 cs2wcr2;
+	u32 dummy7; /* 0x22c */
+	u32 cs4wcr2;
+};
+
+#define CS0WCR2 0xFEC10224
+#define CS2WCR2 0xFEC10228
+#define CS4WCR2 0xFEC10230
+
+/* DDRP */
+struct r8a7740_ddrp {
+	u32 funcctrl;
+	u32 dllctrl;
+	u32 zqcalctrl;
+	u32 zqodtctrl;
+	u32 rdctrl;
+	u32 rdtmg;
+	u32 fifoinit;
+	u32 outctrl;
+	u32 dummy0[50]; /* 0x20 .. 0xe4 */
+	u32 dqcalofs1;
+	u32 dqcalofs2;
+	u32 dummy1[2]; /* 0xf0 .. 0xf4 */
+	u32 dqcalexp;
+};
+
+#define DDRPNCNT 0xE605803C
+#define DDRVREFCNT 0xE61500EC
+
+/* DBSC */
+struct r8a7740_dbsc {
+	u32 dummy0;
+	u32 dbsvcr;
+	u32 dbstate0;
+	u32 dbstate1;
+	u32 dbacen;
+	u32 dbrfen;
+	u32 dbcmd;
+	u32 dbwait;
+	u32 dbkind;
+	u32 dbconf0;
+	u32 dummy1[2]; /* 0x28 .. 0x2c */
+	u32 dbphytype;
+	u32 dummy2[3]; /* 0x34 .. 0x3c */
+	u32 dbtr0;
+	u32 dbtr1;
+	u32 dbtr2;
+	u32 dummy3; /* 0x4c */
+	u32 dbtr3;
+	u32 dbtr4;
+	u32 dbtr5;
+	u32 dbtr6;
+	u32 dbtr7;
+	u32 dbtr8;
+	u32 dbtr9;
+	u32 dbtr10;
+	u32 dbtr11;
+	u32 dbtr12;
+	u32 dbtr13;
+	u32 dbtr14;
+	u32 dbtr15;
+	u32 dbtr16;
+	u32 dbtr17;
+	u32 dbtr18;
+	u32 dbtr19;
+	u32 dummy4[7]; /* 0x94 .. 0xac */
+	u32 dbbl;
+	u32 dummy5[3]; /* 0xb4 .. 0xbc */
+	u32 dbadj0;
+	u32 dbadj1;
+	u32 dbadj2;
+	u32 dummy6[5]; /* 0xcc .. 0xdc */
+	u32 dbrfcnf0;
+	u32 dbrfcnf1;
+	u32 dbrfcnf2;
+	u32 dbrfcnf3;
+	u32 dummy7; /* 0xf0 */
+	u32 dbcalcnf;
+	u32 dbcaltr;
+	u32 dummy8; /* 0xfc */;
+	u32 dbrnk0;
+	u32 dummy9[31]; /* 0x104 .. 0x17C */
+	u32 dbpdncnf;
+	u32 dummy10[7]; /* 0x184 .. 0x19C */
+	u32 dbmrrdr;
+	u32 dummy11[39]; /* 0x1A4 .. 0x23C */
+	u32 dbdfistat;
+	u32 dbdficnt;
+	u32 dummy12[46]; /* 0x248 .. 0x2FC */
+	u32 dbbs0cnt0;
+	u32 dbbs0cnt1;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_R8A7740_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h
new file mode 100644
index 000000000..444e361c0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h
@@ -0,0 +1,387 @@
+#ifndef __ASM_R8A7790_H__
+#define __ASM_R8A7790_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+	GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
+
+	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+	GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
+	GPIO_GP_1_28, GPIO_GP_1_29,
+
+	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+	GPIO_GP_2_28, GPIO_GP_2_29,
+
+	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+	GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
+
+	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
+	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
+	GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
+	GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
+
+	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+	GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
+	GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
+
+	GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS,
+	GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2,
+	GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2,
+
+	/* IPSR0 */
+	GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5,
+	GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2,
+	GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B,
+	GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4,
+	GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4,
+	GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5,
+	GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5,
+	GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6,
+	GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B,
+	GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C,
+	GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C,
+	GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0,
+	GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0,
+
+	/* IPSR1 */
+	GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1,
+	GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10,
+	GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2,
+	GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11,
+	GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3,
+	GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3,
+	GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4,
+	GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4,
+	GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N,
+	GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14,
+	GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B,
+	GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6,
+	GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B,
+	GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7,
+	GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4,
+
+	/* IPSR2 */
+	GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3,
+	GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B,
+	GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1,
+	GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7,
+	GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3,
+	GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4,
+	GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B,
+	GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5,
+	GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B,
+	GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6,
+	GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B,
+
+	/* IPSR3 */
+	GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0,
+	GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B,
+	GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1,
+	GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B,
+	GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2,
+	GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2,
+	GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B,
+	GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15,
+	GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16,
+	GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N,
+	GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19,
+	GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20,
+	GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4,
+
+	/* IPSR4 */
+	GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B,
+	GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5,
+	GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2,
+	GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24,
+	GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB,
+	GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6,
+	GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N,
+	GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B,
+	GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B,
+	GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B,
+	GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B,
+	GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK,
+	GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B,
+	GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B,
+	GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2,
+
+	/* IPSR5 */
+	GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1,
+	GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N,
+	GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N,
+	GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B,
+	GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX,
+	GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2,
+	GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N,
+	GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B,
+	GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N,
+	GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3,
+	GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B,
+	GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK,
+	GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B,
+	GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4,
+	GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B,
+	GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N,
+	GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B,
+	GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N,
+	GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C,
+	GPIO_FN_SSI_WS78_B,
+
+	/* IPSR6 */
+	GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B,
+	GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C,
+	GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B,
+	GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1,
+	GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C,
+	GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B,
+	GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N,
+	GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B,
+	GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B,
+	GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E,
+	GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER,
+	GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C,
+	GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0,
+	GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C,
+	GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1,
+	GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B,
+	GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G,
+	GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E,
+	GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E,
+	GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E,
+	GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F,
+
+	/* IPSR7 */
+	GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E,
+	GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1,
+	GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F,
+	GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C,
+	GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC,
+	GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0,
+	GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C,
+	GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B,
+	GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0,
+	GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C,
+	GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C,
+	GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C,
+	GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C,
+	GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN,
+	GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK,
+	GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1,
+	GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2,
+	GPIO_FN_MII_RXD2,
+
+	/* IPSR8 */
+	GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3,
+	GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N,
+	GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N,
+	GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N,
+	GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1,
+	GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER,
+	GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK,
+	GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV,
+	GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D,
+	GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1,
+	GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC,
+	GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO,
+	GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D,
+	GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D,
+	GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5,
+	GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK,
+	GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD,
+	GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B,
+
+	/* IPSR9 */
+	GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B,
+	GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B,
+	GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B,
+	GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B,
+	GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP,
+	GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B,
+	GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP,
+	GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN,
+	GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B,
+	GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK,
+	GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD,
+	GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B,
+	GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK,
+	GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK,
+	GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2,
+	GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B,
+	GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0,
+	GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6,
+	GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B,
+	GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B,
+	GPIO_FN_VI3_CLK_B,
+
+	/* IPSR10 */
+	GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN,
+	GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D,
+	GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK,
+	GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B,
+	GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D,
+	GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D,
+	GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B,
+	GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B,
+	GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D,
+	GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B,
+	GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA,
+	GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D,
+	GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B,
+	GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK,
+	GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B,
+	GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3,
+	GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B,
+	GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B,
+	GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4,
+	GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0,
+	GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B,
+	GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B,
+
+	/* IPSR11 */
+	GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN,
+	GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D,
+	GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B,
+	GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD,
+	GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N,
+	GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2,
+	GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3,
+	GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1,
+	GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP,
+	GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C,
+	GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F,
+	GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B,
+	GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B,
+	GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN,
+	GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C,
+	GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B,
+	GPIO_FN_MOUT0,
+
+	/* IPSR12 */
+	GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1,
+	GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2,
+	GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5,
+	GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6,
+	GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK,
+	GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34,
+	GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC,
+	GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0,
+	GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK,
+	GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N,
+	GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0,
+	GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N,
+	GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1,
+	GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD,
+	GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK,
+	GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS,
+	GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD,
+	GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE,
+	GPIO_FN_CAN_DEBUGOUT4,
+
+	/* IPSR13 */
+	GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2,
+	GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6,
+	GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C,
+	GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6,
+	GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6,
+	GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4,
+	GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6,
+	GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5,
+	GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1,
+	GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6,
+	GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1,
+	GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7,
+	GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7,
+	GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N,
+	GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11,
+	GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B,
+	GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8,
+	GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C,
+	GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9,
+	GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1,
+	GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA,
+	GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14,
+
+	/* IPSR14 */
+	GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D,
+	GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15,
+	GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0,
+	GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C,
+	GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0,
+	GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1,
+	GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N,
+	GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3,
+	GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C,
+	GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS,
+	GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B,
+	GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1,
+	GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+	GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1,
+	GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK,
+	GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK,
+	GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS,
+	GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE,
+	GPIO_FN_HRTS0_N_C,
+
+	/* IPSR15 */
+	GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7,
+	GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN,
+	GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS,
+	GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17,
+	GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0,
+	GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0,
+	GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3,
+	GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4,
+	GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5,
+	GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK,
+	GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0,
+	GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23,
+	GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0,
+	GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1,
+	GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14,
+
+	/* IPSR16 */
+	GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2,
+	GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B,
+	GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2,
+	GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C,
+	GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC,
+	GPIO_FN_TCLK1_B,
+};
+
+#endif /* __ASM_R8A7790_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h
new file mode 100644
index 000000000..d9ea71fa1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -0,0 +1,615 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7790.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_R8A7790_H
+#define __ASM_ARCH_R8A7790_H
+
+/*
+ * R8A7790 I/O Addresses
+ */
+#define	RWDT_BASE		0xE6020000
+#define	SWDT_BASE		0xE6030000
+#define	LBSC_BASE		0xFEC00200
+#define DBSC3_0_BASE		0xE6790000
+#define DBSC3_1_BASE		0xE67A0000
+#define TMU_BASE		0xE61E0000
+#define	GPIO5_BASE		0xE6055000
+#define SH_QSPI_BASE	0xE6B10000
+
+#define S3C_BASE		0xE6784000
+#define S3C_INT_BASE		0xE6784A00
+#define S3C_MEDIA_BASE		0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE	0xE6784BDC
+#define S3C_QOS_CCI0_BASE	0xE6784C00
+#define S3C_QOS_CCI1_BASE	0xE6784C24
+#define S3C_QOS_MXI_BASE	0xE6784C48
+#define S3C_QOS_AXI_BASE	0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE	0xE6791000
+#define DBSC3_0_QOS_R1_BASE	0xE6791100
+#define DBSC3_0_QOS_R2_BASE	0xE6791200
+#define DBSC3_0_QOS_R3_BASE	0xE6791300
+#define DBSC3_0_QOS_R4_BASE	0xE6791400
+#define DBSC3_0_QOS_R5_BASE	0xE6791500
+#define DBSC3_0_QOS_R6_BASE	0xE6791600
+#define DBSC3_0_QOS_R7_BASE	0xE6791700
+#define DBSC3_0_QOS_R8_BASE	0xE6791800
+#define DBSC3_0_QOS_R9_BASE	0xE6791900
+#define DBSC3_0_QOS_R10_BASE	0xE6791A00
+#define DBSC3_0_QOS_R11_BASE	0xE6791B00
+#define DBSC3_0_QOS_R12_BASE	0xE6791C00
+#define DBSC3_0_QOS_R13_BASE	0xE6791D00
+#define DBSC3_0_QOS_R14_BASE	0xE6791E00
+#define DBSC3_0_QOS_R15_BASE	0xE6791F00
+#define DBSC3_0_QOS_W0_BASE	0xE6792000
+#define DBSC3_0_QOS_W1_BASE	0xE6792100
+#define DBSC3_0_QOS_W2_BASE	0xE6792200
+#define DBSC3_0_QOS_W3_BASE	0xE6792300
+#define DBSC3_0_QOS_W4_BASE	0xE6792400
+#define DBSC3_0_QOS_W5_BASE	0xE6792500
+#define DBSC3_0_QOS_W6_BASE	0xE6792600
+#define DBSC3_0_QOS_W7_BASE	0xE6792700
+#define DBSC3_0_QOS_W8_BASE	0xE6792800
+#define DBSC3_0_QOS_W9_BASE	0xE6792900
+#define DBSC3_0_QOS_W10_BASE	0xE6792A00
+#define DBSC3_0_QOS_W11_BASE	0xE6792B00
+#define DBSC3_0_QOS_W12_BASE	0xE6792C00
+#define DBSC3_0_QOS_W13_BASE	0xE6792D00
+#define DBSC3_0_QOS_W14_BASE	0xE6792E00
+#define DBSC3_0_QOS_W15_BASE	0xE6792F00
+
+#define DBSC3_0_DBADJ2		0xE67900C8
+
+#define CCI_400_MAXOT_1		0xF0091110
+#define CCI_400_MAXOT_2		0xF0092110
+#define CCI_400_QOSCNTL_1	0xF009110C
+#define CCI_400_QOSCNTL_2	0xF009210C
+
+#define	MXI_BASE		0xFE960000
+#define	MXI_QOS_BASE		0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE	0xFF800300
+#define SYS_AXI_AVB_BASE	0xFF800340
+#define SYS_AXI_G2D_BASE	0xFF800540
+#define SYS_AXI_IMP0_BASE	0xFF800580
+#define SYS_AXI_IMP1_BASE	0xFF8005C0
+#define SYS_AXI_IMUX0_BASE	0xFF800600
+#define SYS_AXI_IMUX1_BASE	0xFF800640
+#define SYS_AXI_IMUX2_BASE	0xFF800680
+#define SYS_AXI_LBS_BASE	0xFF8006C0
+#define SYS_AXI_MMUDS_BASE	0xFF800700
+#define SYS_AXI_MMUM_BASE	0xFF800740
+#define SYS_AXI_MMUR_BASE	0xFF800780
+#define SYS_AXI_MMUS0_BASE	0xFF8007C0
+#define SYS_AXI_MMUS1_BASE	0xFF800800
+#define SYS_AXI_MTSB0_BASE	0xFF800880
+#define SYS_AXI_MTSB1_BASE	0xFF8008C0
+#define SYS_AXI_PCI_BASE	0xFF800900
+#define SYS_AXI_RTX_BASE	0xFF800940
+#define SYS_AXI_SDS0_BASE	0xFF800A80
+#define SYS_AXI_SDS1_BASE	0xFF800AC0
+#define SYS_AXI_USB20_BASE	0xFF800C00
+#define SYS_AXI_USB21_BASE	0xFF800C40
+#define SYS_AXI_USB22_BASE	0xFF800C80
+#define SYS_AXI_USB30_BASE	0xFF800CC0
+
+#define RT_AXI_SHX_BASE		0xFF810100
+#define RT_AXI_RDS_BASE		0xFF8101C0
+#define RT_AXI_RTX64TO128_BASE	0xFF810200
+#define RT_AXI_STPRO_BASE	0xFF810240
+
+#define MP_AXI_ADSP_BASE	0xFF820100
+#define MP_AXI_ASDS0_BASE	0xFF8201C0
+#define MP_AXI_ASDS1_BASE	0xFF820200
+#define MP_AXI_MLP_BASE		0xFF820240
+#define MP_AXI_MMUMP_BASE	0xFF820280
+#define MP_AXI_SPU_BASE		0xFF8202C0
+#define MP_AXI_SPUC_BASE	0xFF820300
+
+#define SYS_AXI256_AXI128TO256_BASE	0xFF860100
+#define SYS_AXI256_SYX_BASE	0xFF860140
+#define SYS_AXI256_MPX_BASE	0xFF860180
+#define SYS_AXI256_MXI_BASE	0xFF8601C0
+
+#define CCI_AXI_MMUS0_BASE	0xFF880100
+#define CCI_AXI_SYX2_BASE	0xFF880140
+#define CCI_AXI_MMUR_BASE	0xFF880180
+#define CCI_AXI_MMUDS_BASE	0xFF8801C0
+#define CCI_AXI_MMUM_BASE	0xFF880200
+#define CCI_AXI_MXI_BASE	0xFF880240
+#define CCI_AXI_MMUS1_BASE	0xFF880280
+#define CCI_AXI_MMUMP_BASE	0xFF8802C0
+
+#define MEDIA_AXI_JPR_BASE	0xFE964100
+#define MEDIA_AXI_JPW_BASE	0xFE966100
+#define MEDIA_AXI_GCU0R_BASE	0xFE964140
+#define MEDIA_AXI_GCU0W_BASE	0xFE966140
+#define MEDIA_AXI_GCU1R_BASE	0xFE964180
+#define MEDIA_AXI_GCU1W_BASE	0xFE966180
+#define MEDIA_AXI_TDMR_BASE	0xFE964500
+#define MEDIA_AXI_TDMW_BASE	0xFE966500
+#define MEDIA_AXI_VSP0CR_BASE	0xFE964540
+#define MEDIA_AXI_VSP0CW_BASE	0xFE966540
+#define MEDIA_AXI_VSP1CR_BASE	0xFE964580
+#define MEDIA_AXI_VSP1CW_BASE	0xFE966580
+#define MEDIA_AXI_VSPDU0CR_BASE	0xFE9645C0
+#define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
+#define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
+#define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
+#define MEDIA_AXI_VIN0W_BASE	0xFE966900
+#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
+#define MEDIA_AXI_FDP0R_BASE	0xFE964D40
+#define MEDIA_AXI_FDP0W_BASE	0xFE966D40
+#define MEDIA_AXI_IMSR_BASE	0xFE964D80
+#define MEDIA_AXI_IMSW_BASE	0xFE966D80
+#define MEDIA_AXI_VSP1R_BASE	0xFE965100
+#define MEDIA_AXI_VSP1W_BASE	0xFE967100
+#define MEDIA_AXI_FDP1R_BASE	0xFE965140
+#define MEDIA_AXI_FDP1W_BASE	0xFE967140
+#define MEDIA_AXI_IMRR_BASE	0xFE965180
+#define MEDIA_AXI_IMRW_BASE	0xFE967180
+#define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
+#define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
+#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
+#define MEDIA_AXI_DU0R_BASE	0xFE965580
+#define MEDIA_AXI_DU0W_BASE	0xFE967580
+#define MEDIA_AXI_DU1R_BASE	0xFE9655C0
+#define MEDIA_AXI_DU1W_BASE	0xFE9675C0
+#define MEDIA_AXI_VCP0CR_BASE	0xFE965900
+#define MEDIA_AXI_VCP0CW_BASE	0xFE967900
+#define MEDIA_AXI_VCP0VR_BASE	0xFE965940
+#define MEDIA_AXI_VCP0VW_BASE	0xFE967940
+#define MEDIA_AXI_VPC0R_BASE	0xFE965980
+#define MEDIA_AXI_VCP1CR_BASE	0xFE965D00
+#define MEDIA_AXI_VCP1CW_BASE	0xFE967D00
+#define MEDIA_AXI_VCP1VR_BASE	0xFE965D40
+#define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
+#define MEDIA_AXI_VPC1R_BASE	0xFE965D80
+
+#define SYS_AXI_AVBDMSCR	0xFF802000
+#define SYS_AXI_SYX2DMSCR	0xFF802004
+#define SYS_AXI_CC50DMSCR	0xFF802008
+#define SYS_AXI_CC51DMSCR	0xFF80200C
+#define SYS_AXI_CCIDMSCR	0xFF802010
+#define SYS_AXI_CSDMSCR		0xFF802014
+#define SYS_AXI_DDMDMSCR	0xFF802018
+#define SYS_AXI_ETHDMSCR	0xFF80201C
+#define SYS_AXI_G2DDMSCR	0xFF802020
+#define SYS_AXI_IMP0DMSCR	0xFF802024
+#define SYS_AXI_IMP1DMSCR	0xFF802028
+#define SYS_AXI_LBSDMSCR	0xFF80202C
+#define SYS_AXI_MMUDSDMSCR	0xFF802030
+#define SYS_AXI_MMUMXDMSCR	0xFF802034
+#define SYS_AXI_MMURDDMSCR	0xFF802038
+#define SYS_AXI_MMUS0DMSCR	0xFF80203C
+#define SYS_AXI_MMUS1DMSCR	0xFF802040
+#define SYS_AXI_MPXDMSCR	0xFF802044
+#define SYS_AXI_MTSB0DMSCR	0xFF802048
+#define SYS_AXI_MTSB1DMSCR	0xFF80204C
+#define SYS_AXI_PCIDMSCR	0xFF802050
+#define SYS_AXI_RTXDMSCR	0xFF802054
+#define SYS_AXI_SAT0DMSCR	0xFF802058
+#define SYS_AXI_SAT1DMSCR	0xFF80205C
+#define SYS_AXI_SDM0DMSCR	0xFF802060
+#define SYS_AXI_SDM1DMSCR	0xFF802064
+#define SYS_AXI_SDS0DMSCR	0xFF802068
+#define SYS_AXI_SDS1DMSCR	0xFF80206C
+#define SYS_AXI_ETRABDMSCR	0xFF802070
+#define SYS_AXI_ETRKFDMSCR	0xFF802074
+#define SYS_AXI_UDM0DMSCR	0xFF802078
+#define SYS_AXI_UDM1DMSCR	0xFF80207C
+#define SYS_AXI_USB20DMSCR	0xFF802080
+#define SYS_AXI_USB21DMSCR	0xFF802084
+#define SYS_AXI_USB22DMSCR	0xFF802088
+#define SYS_AXI_USB30DMSCR	0xFF80208C
+#define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
+#define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
+#define SYS_AXI_AVBSLVDMSCR	0xFF802108
+#define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
+#define SYS_AXI_ETHSLVDMSCR	0xFF802110
+#define SYS_AXI_GICSLVDMSCR	0xFF802114
+#define SYS_AXI_IMPSLVDMSCR	0xFF802118
+#define SYS_AXI_IMX0SLVDMSCR	0xFF80211C
+#define SYS_AXI_IMX1SLVDMSCR	0xFF802120
+#define SYS_AXI_IMX2SLVDMSCR	0xFF802124
+#define SYS_AXI_LBSSLVDMSCR	0xFF802128
+#define SYS_AXI_MMC0SLVDMSCR	0xFF80212C
+#define SYS_AXI_MMC1SLVDMSCR	0xFF802130
+#define SYS_AXI_MPXSLVDMSCR	0xFF802134
+#define SYS_AXI_MTSB0SLVDMSCR	0xFF802138
+#define SYS_AXI_MTSB1SLVDMSCR	0xFF80213C
+#define SYS_AXI_MXTSLVDMSCR	0xFF802140
+#define SYS_AXI_PCISLVDMSCR	0xFF802144
+#define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
+#define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
+#define SYS_AXI_RTXSLVDMSCR	0xFF802150
+#define SYS_AXI_SAT0SLVDMSCR	0xFF802168
+#define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
+#define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
+#define SYS_AXI_SDAP1SLVDMSCR	0xFF802174
+#define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
+#define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
+#define SYS_AXI_SGXSLVDMSCR	0xFF802180
+#define SYS_AXI_STBSLVDMSCR	0xFF802188
+#define SYS_AXI_STMSLVDMSCR	0xFF80218C
+#define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
+#define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
+#define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
+#define SYS_AXI_USB20SLVDMSCR	0xFF8021A0
+#define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
+#define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
+#define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
+
+#define RT_AXI_CBMDMSCR		0xFF812000
+#define RT_AXI_DBDMSCR		0xFF812004
+#define RT_AXI_RDMDMSCR		0xFF812008
+#define RT_AXI_RDSDMSCR		0xFF81200C
+#define RT_AXI_STRDMSCR		0xFF812010
+#define RT_AXI_SY2RTDMSCR	0xFF812014
+#define RT_AXI_CBSSLVDMSCR	0xFF812100
+#define RT_AXI_DBSSLVDMSCR	0xFF812104
+#define RT_AXI_RTAP1SLVDMSCR	0xFF812108
+#define RT_AXI_RTAP2SLVDMSCR	0xFF81210C
+#define RT_AXI_RTAP3SLVDMSCR	0xFF812110
+#define RT_AXI_RT2SYSLVDMSCR	0xFF812114
+#define RT_AXI_A128TO64SLVDMSCR	0xFF812118
+#define RT_AXI_A64TO128SLVDMSCR	0xFF81211C
+#define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
+#define RT_AXI_UTLBRSLVDMSCR	0xFF812128
+
+#define MP_AXI_ADSPDMSCR	0xFF822000
+#define MP_AXI_ASDM0DMSCR	0xFF822004
+#define MP_AXI_ASDM1DMSCR	0xFF822008
+#define MP_AXI_ASDS0DMSCR	0xFF82200C
+#define MP_AXI_ASDS1DMSCR	0xFF822010
+#define MP_AXI_MLPDMSCR		0xFF822014
+#define MP_AXI_MMUMPDMSCR	0xFF822018
+#define MP_AXI_SPUDMSCR		0xFF82201C
+#define MP_AXI_SPUCDMSCR	0xFF822020
+#define MP_AXI_SY2MPDMSCR	0xFF822024
+#define MP_AXI_ADSPSLVDMSCR	0xFF822100
+#define MP_AXI_MLMSLVDMSCR	0xFF822104
+#define MP_AXI_MPAP4SLVDMSCR	0xFF822108
+#define MP_AXI_MPAP5SLVDMSCR	0xFF82210C
+#define MP_AXI_MPAP6SLVDMSCR	0xFF822110
+#define MP_AXI_MPAP7SLVDMSCR	0xFF822114
+#define MP_AXI_MP2SYSLVDMSCR	0xFF822118
+#define MP_AXI_MP2SY2SLVDMSCR	0xFF82211C
+#define MP_AXI_MPXAPSLVDMSCR	0xFF822124
+#define MP_AXI_SPUSLVDMSCR	0xFF822128
+#define MP_AXI_UTLBMPSLVDMSCR	0xFF82212C
+
+#define ADM_AXI_ASDM0DMSCR	0xFF842000
+#define ADM_AXI_ASDM1DMSCR	0xFF842004
+#define ADM_AXI_MPAP1SLVDMSCR	0xFF842104
+#define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
+#define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
+
+#define DM_AXI_RDMDMSCR		0xFF852000
+#define DM_AXI_SDM0DMSCR	0xFF852004
+#define DM_AXI_SDM1DMSCR	0xFF852008
+#define DM_AXI_MMAP0SLVDMSCR	0xFF852100
+#define DM_AXI_MMAP1SLVDMSCR	0xFF852104
+#define DM_AXI_QSPAPSLVDMSCR	0xFF852108
+#define DM_AXI_RAP4SLVDMSCR	0xFF85210C
+#define DM_AXI_RAP5SLVDMSCR	0xFF852110
+#define DM_AXI_SAP4SLVDMSCR	0xFF852114
+#define DM_AXI_SAP5SLVDMSCR	0xFF852118
+#define DM_AXI_SAP6SLVDMSCR	0xFF85211C
+#define DM_AXI_SAP65SLVDMSCR	0xFF852120
+#define DM_AXI_SDAP0SLVDMSCR	0xFF852124
+#define DM_AXI_SDAP1SLVDMSCR	0xFF852128
+#define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
+#define DM_AXI_SDAP3SLVDMSCR	0xFF852130
+
+#define SYS_AXI256_SYXDMSCR	0xFF862000
+#define SYS_AXI256_MPXDMSCR	0xFF862004
+#define SYS_AXI256_MXIDMSCR	0xFF862008
+#define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
+#define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
+#define SYS_AXI256_SYXSLVDMSCR	0xFF862108
+#define SYS_AXI256_CCXSLVDMSCR	0xFF86210C
+#define SYS_AXI256_S3CSLVDMSCR	0xFF862110
+
+#define MXT_SYXDMSCR		0xFF872000
+#define MXT_CMM0SLVDMSCR	0xFF872100
+#define MXT_CMM1SLVDMSCR	0xFF872104
+#define MXT_CMM2SLVDMSCR	0xFF872108
+#define MXT_FDPSLVDMSCR		0xFF87210C
+#define MXT_IMRSLVDMSCR		0xFF872110
+#define MXT_VINSLVDMSCR		0xFF872114
+#define MXT_VPC0SLVDMSCR	0xFF872118
+#define MXT_VPC1SLVDMSCR	0xFF87211C
+#define MXT_VSP0SLVDMSCR	0xFF872120
+#define MXT_VSP1SLVDMSCR	0xFF872124
+#define MXT_VSPD0SLVDMSCR	0xFF872128
+#define MXT_VSPD1SLVDMSCR	0xFF87212C
+#define MXT_MAP1SLVDMSCR	0xFF872130
+#define MXT_MAP2SLVDMSCR	0xFF872134
+
+#define CCI_AXI_MMUS0DMSCR	0xFF882000
+#define CCI_AXI_SYX2DMSCR	0xFF882004
+#define CCI_AXI_MMURDMSCR	0xFF882008
+#define CCI_AXI_MMUDSDMSCR	0xFF88200C
+#define CCI_AXI_MMUMDMSCR	0xFF882010
+#define CCI_AXI_MXIDMSCR	0xFF882014
+#define CCI_AXI_MMUS1DMSCR	0xFF882018
+#define CCI_AXI_MMUMPDMSCR	0xFF88201C
+#define CCI_AXI_DVMDMSCR	0xFF882020
+#define CCI_AXI_CCISLVDMSCR	0xFF882100
+
+#define CCI_AXI_IPMMUIDVMCR	0xFF880400
+#define CCI_AXI_IPMMURDVMCR	0xFF880404
+#define CCI_AXI_IPMMUS0DVMCR	0xFF880408
+#define CCI_AXI_IPMMUS1DVMCR	0xFF88040C
+#define CCI_AXI_IPMMUMPDVMCR	0xFF880410
+#define CCI_AXI_IPMMUDSDVMCR	0xFF880414
+#define CCI_AXI_AX2ADDRMASK	0xFF88041C
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct r8a7790_rwdt {
+	u32 rwtcnt;	/* 0x00 */
+	u32 rwtcsra;	/* 0x04 */
+	u16 rwtcsrb;	/* 0x08 */
+};
+
+/* SWDT */
+struct r8a7790_swdt {
+	u32 swtcnt;	/* 0x00 */
+	u32 swtcsra;	/* 0x04 */
+	u16 swtcsrb;	/* 0x08 */
+};
+
+/* LBSC */
+struct r8a7790_lbsc {
+	u32 cs0ctrl;
+	u32 cs1ctrl;
+	u32 ecs0ctrl;
+	u32 ecs1ctrl;
+	u32 ecs2ctrl;
+	u32 ecs3ctrl;
+	u32 ecs4ctrl;
+	u32 ecs5ctrl;
+	u32 dummy0[4];	/* 0x20 .. 0x2C */
+	u32 cswcr0;
+	u32 cswcr1;
+	u32 ecswcr0;
+	u32 ecswcr1;
+	u32 ecswcr2;
+	u32 ecswcr3;
+	u32 ecswcr4;
+	u32 ecswcr5;
+	u32 exdmawcr0;
+	u32 exdmawcr1;
+	u32 exdmawcr2;
+	u32 dummy1[9];	/* 0x5C .. 0x7C */
+	u32 cspwcr0;
+	u32 cspwcr1;
+	u32 ecspwcr0;
+	u32 ecspwcr1;
+	u32 ecspwcr2;
+	u32 ecspwcr3;
+	u32 ecspwcr4;
+	u32 ecspwcr5;
+	u32 exwtsync;
+	u32 dummy2[3];	/* 0xA4 .. 0xAC */
+	u32 cs0bstctl;
+	u32 cs0btph;
+	u32 dummy3[2];	/* 0xB8 .. 0xBC */
+	u32 cs1gdst;
+	u32 ecs0gdst;
+	u32 ecs1gdst;
+	u32 ecs2gdst;
+	u32 ecs3gdst;
+	u32 ecs4gdst;
+	u32 ecs5gdst;
+	u32 dummy4[5];	/* 0xDC .. 0xEC */
+	u32 exdmaset0;
+	u32 exdmaset1;
+	u32 exdmaset2;
+	u32 dummy5[5];	/* 0xFC .. 0x10C */
+	u32 exdmcr0;
+	u32 exdmcr1;
+	u32 exdmcr2;
+	u32 dummy6[5];	/* 0x11C .. 0x12C */
+	u32 bcintsr;
+	u32 bcintcr;
+	u32 bcintmr;
+	u32 dummy7;	/* 0x13C */
+	u32 exbatlv;
+	u32 exwtsts;
+	u32 dummy8[14];	/* 0x148 .. 0x17C */
+	u32 atacsctrl;
+	u32 dummy9[15]; /* 0x184 .. 0x1BC */
+	u32 exbct;
+	u32 extct;
+};
+
+/* DBSC3 */
+struct r8a7790_dbsc3 {
+	u32 dummy0[3];	/* 0x00 .. 0x08 */
+	u32 dbstate1;
+	u32 dbacen;
+	u32 dbrfen;
+	u32 dbcmd;
+	u32 dbwait;
+	u32 dbkind;
+	u32 dbconf0;
+	u32 dummy1[2];	/* 0x28 .. 0x2C */
+	u32 dbphytype;
+	u32 dummy2[3];	/* 0x34 .. 0x3C */
+	u32 dbtr0;
+	u32 dbtr1;
+	u32 dbtr2;
+	u32 dummy3;	/* 0x4C */
+	u32 dbtr3;
+	u32 dbtr4;
+	u32 dbtr5;
+	u32 dbtr6;
+	u32 dbtr7;
+	u32 dbtr8;
+	u32 dbtr9;
+	u32 dbtr10;
+	u32 dbtr11;
+	u32 dbtr12;
+	u32 dbtr13;
+	u32 dbtr14;
+	u32 dbtr15;
+	u32 dbtr16;
+	u32 dbtr17;
+	u32 dbtr18;
+	u32 dbtr19;
+	u32 dummy4[7];	/* 0x94 .. 0xAC */
+	u32 dbbl;
+	u32 dummy5[3];	/* 0xB4 .. 0xBC */
+	u32 dbadj0;
+	u32 dummy6;	/* 0xC4 */
+	u32 dbadj2;
+	u32 dummy7[5];	/* 0xCC .. 0xDC */
+	u32 dbrfcnf0;
+	u32 dbrfcnf1;
+	u32 dbrfcnf2;
+	u32 dummy8[2];	/* 0xEC .. 0xF0 */
+	u32 dbcalcnf;
+	u32 dbcaltr;
+	u32 dummy9;	/* 0xFC */
+	u32 dbrnk0;
+	u32 dummy10[31];	/* 0x104 .. 0x17C */
+	u32 dbpdncnf;
+	u32 dummy11[47];	/* 0x184 ..0x23C */
+	u32 dbdfistat;
+	u32 dbdficnt;
+	u32 dummy12[14];	/* 0x248 .. 0x27C */
+	u32 dbpdlck;
+	u32 dummy13[3];	/* 0x284 .. 0x28C */
+	u32 dbpdrga;
+	u32 dummy14[3];	/* 0x294 .. 0x29C */
+	u32 dbpdrgd;
+	u32 dummy15[24];	/* 0x2A4 .. 0x300 */
+	u32 dbbs0cnt1;
+	u32 dummy16[30];	/* 0x308 .. 0x37C */
+	u32 dbwt0cnf0;
+	u32 dbwt0cnf1;
+	u32 dbwt0cnf2;
+	u32 dbwt0cnf3;
+	u32 dbwt0cnf4;
+};
+
+/* GPIO */
+struct r8a7790_gpio {
+	u32 iointsel;
+	u32 inoutsel;
+	u32 outdt;
+	u32 indt;
+	u32 intdt;
+	u32 intclr;
+	u32 intmsk;
+	u32 posneg;
+	u32 edglevel;
+	u32 filonoff;
+	u32 intmsks;
+	u32 mskclrs;
+	u32 outdtsel;
+	u32 outdth;
+	u32 outdtl;
+	u32 bothedge;
+};
+
+/* S3C(QoS) */
+struct r8a7790_s3c {
+	u32 s3cexcladdmsk;
+	u32 s3cexclidmsk;
+	u32 s3cadsplcr;
+	u32 s3cmaar;
+	u32 s3carcr11;
+	u32 s3crorr;
+	u32 s3cworr;
+	u32 s3carcr22;
+	u32 dummy1[2];	/* 0x20 .. 0x24 */
+	u32 s3cmctr;
+	u32 dummy2;	/* 0x2C */
+	u32 cconf0;
+	u32 cconf1;
+	u32 cconf2;
+	u32 cconf3;
+};
+
+struct r8a7790_s3c_qos {
+	u32 s3cqos0;
+	u32 s3cqos1;
+	u32 s3cqos2;
+	u32 s3cqos3;
+	u32 s3cqos4;
+	u32 s3cqos5;
+	u32 s3cqos6;
+	u32 s3cqos7;
+	u32 s3cqos8;
+};
+
+/* DBSC(QoS) */
+struct r8a7790_dbsc3_qos {
+	u32 dblgcnt;
+	u32 dbtmval0;
+	u32 dbtmval1;
+	u32 dbtmval2;
+	u32 dbtmval3;
+	u32 dbrqctr;
+	u32 dbthres0;
+	u32 dbthres1;
+	u32 dbthres2;
+	u32 dummy0;	/* 0x24 */
+	u32 dblgqon;
+};
+
+/* MXI(QoS) */
+struct r8a7790_mxi {
+	u32 mxsaar0;
+	u32 mxsaar1;
+	u32 dummy0[7];	/* 0x08 .. 0x20 */
+	u32 mxaxiracr;
+	u32 mxs3cracr;
+	u32 dummy1[2];	/* 0x2C .. 0x30 */
+	u32 mxaxiwacr;
+	u32 mxs3cwacr;
+	u32 dummy2;	/* 0x3C */
+	u32 mxrtcr;
+	u32 mxwtcr;
+};
+
+struct r8a7790_mxi_qos {
+	u32 vspdu0;
+	u32 vspdu1;
+	u32 du0;
+	u32 du1;
+};
+
+/* AXI(QoS) */
+struct r8a7790_axi_qos {
+	u32 qosconf;
+	u32 qosctset0;
+	u32 qosctset1;
+	u32 qosctset2;
+	u32 qosctset3;
+	u32 qosreqctr;
+	u32 qosthres0;
+	u32 qosthres1;
+	u32 qosthres2;
+	u32 qosqon;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_R8A7790_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h
new file mode 100644
index 000000000..d3cf0c10a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h
@@ -0,0 +1,438 @@
+#ifndef __ASM_R8A7791_H__
+#define __ASM_R8A7791_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+	GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
+
+	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+	GPIO_GP_1_24, GPIO_GP_1_25,
+
+	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+	GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
+
+	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+	GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
+
+	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
+	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
+	GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
+	GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
+
+	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+	GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
+	GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
+
+	GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+	GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+	GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
+	GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
+	GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
+	GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
+	GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,
+	GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,
+
+	GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
+	GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
+	GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
+	GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
+	GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19,
+	GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23,
+	GPIO_GP_7_24, GPIO_GP_7_25,
+
+	GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA,
+	GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0,
+	GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2,
+	GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5,
+	GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7,
+	GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
+
+	/* IPSR0 */
+	GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
+	GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10,
+	GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15,
+	GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B,
+	GPIO_FN_SCL0_C, GPIO_FN_PWM2_B,
+	GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B,
+	GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B,
+	GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK,
+
+	/* IPSR1 */
+	GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8,
+	GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0,
+	GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0,
+	GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D,
+	GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D,
+	GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D,
+	GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D,
+	GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN,
+	GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D,
+	GPIO_FN_A15, GPIO_FN_BPFCLK_C,
+	GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B,
+	GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C,
+	GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C,
+
+	/* IPSR2 */
+	GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C,
+	GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B,
+	GPIO_FN_A20, GPIO_FN_SPCLK,
+	GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0,
+	GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B,
+	GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD,
+	GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B,
+	GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD,
+	GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3,
+	GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD,
+	GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C,
+	GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD,
+	GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1,
+	GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1,
+	GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK,
+	GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC,
+	GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD,
+	GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1,
+
+	/* IPSR3 */
+	GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N,
+	GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2,
+	GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1,
+	GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B,
+	GPIO_FN_PWM1, GPIO_FN_TPU_TO1,
+	GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2,
+	GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B,
+	GPIO_FN_PWM2, GPIO_FN_TPU_TO2,
+	GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B,
+	GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D,
+	GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B,
+	GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B,
+	GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B,
+	GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B,
+	GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3,
+	GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON,
+	GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C,
+	GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B,
+	GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D,
+	GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C,
+	GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C,
+	GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C,
+	GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C,
+
+	/* IPSR4 */
+	GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B,
+	GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C,
+	GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B,
+	GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D,
+	GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B,
+	GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D,
+	GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B,
+	GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C,
+	GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B,
+	GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E,
+	GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B,
+	GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E,
+	GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B,
+	GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E,
+	GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3,
+	GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D,
+	GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D,
+	GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D,
+	GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C,
+	GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0,
+	GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B,
+
+	/* IPSR5 */
+	GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0,
+	GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B,
+	GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0,
+	GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B,
+	GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0,
+	GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B,
+	GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK,
+	GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B,
+	GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B,
+	GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B,
+	GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS,
+	GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON,
+	GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B,
+	GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B,
+	GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D,
+	GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D,
+	GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D,
+
+	/* IPSR6 */
+	GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B,
+	GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E,
+	GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B,
+	GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E,
+	GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B,
+	GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD,
+	GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N,
+	GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N,
+	GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N,
+	GPIO_FN_IRQ3, GPIO_FN_SCL4_C,
+	GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N,
+	GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C,
+	GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N,
+	GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E,
+	GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B,
+	GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E,
+	GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B,
+	GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D,
+	GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B,
+	GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D,
+
+	/* IPSR7 */
+	GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D,
+	GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D,
+	GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B,
+	GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B,
+	GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B,
+	GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B,
+	GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B,
+	GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B,
+	GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B,
+	GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B,
+	GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B,
+	GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B,
+	GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B,
+	GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B,
+	GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B,
+	GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B,
+	GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B,
+	GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B,
+
+	/* IPSR8 */
+	GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11,
+	GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B,
+	GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B,
+	GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B,
+	GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B,
+	GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B,
+	GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B,
+	GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B,
+	GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B,
+	GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B,
+	GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B,
+	GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B,
+	GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B,
+	GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B,
+	GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B,
+	GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B,
+	GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B,
+	GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20,
+	GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX,
+	GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3,
+	GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX,
+
+	/* IPSR9 */
+	GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C,
+	GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD,
+	GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C,
+	GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK,
+	GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS,
+	GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK,
+	GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX,
+	GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4,
+	GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS,
+	GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE,
+	GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+	GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B,
+	GPIO_FN_DU1_DISP, GPIO_FN_QPOLA,
+	GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B,
+	GPIO_FN_VI0_CLKENB, GPIO_FN_TX4,
+	GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D,
+	GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D,
+	GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5,
+	GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D,
+	GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5,
+	GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D,
+	GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B,
+	GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4,
+	GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N,
+
+	/* IPSR10 */
+	GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4,
+	GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N,
+	GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C,
+	GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N,
+	GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C,
+	GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N,
+	GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C,
+	GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D,
+	GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C,
+	GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E,
+	GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D,
+	GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D,
+	GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D,
+	GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B,
+	GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N,
+	GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B,
+	GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N,
+	GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3,
+	GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C,
+	GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4,
+	GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C,
+	GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B,
+	GPIO_FN_TX0_C, GPIO_FN_SCL1_D,
+
+	/* IPSR11 */
+	GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B,
+	GPIO_FN_RX0_C, GPIO_FN_SDA1_D,
+	GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B,
+	GPIO_FN_TX1_C, GPIO_FN_SCL4_B,
+	GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E,
+	GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D,
+	GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B,
+	GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B,
+	GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B,
+	GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B,
+	GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B,
+	GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B,
+	GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5,
+	GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6,
+	GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7,
+	GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER,
+	GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO,
+	GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV,
+	GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC,
+	GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC,
+	GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C,
+	GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C,
+
+	/* IPSR12 */
+	GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7,
+	GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7,
+	GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C,
+	GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E,
+	GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C,
+	GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E,
+	GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B,
+	GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E,
+	GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B,
+	GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E,
+	GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3,
+	GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B,
+	GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C,
+	GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C,
+	GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C,
+	GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D,
+	GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C,
+	GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D,
+	GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C,
+
+	/* IPSR13 */
+	GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C,
+	GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C,
+	GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK,
+	GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C,
+	GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL,
+	GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C,
+	GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B,
+	GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C,
+	GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B,
+	GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B,
+	GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B,
+	GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B,
+	GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B,
+	GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F,
+	GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C,
+	GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F,
+	GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C,
+	GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B,
+	GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B,
+	GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B,
+	GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B,
+	GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C,
+
+	/* IPSR14 */
+	GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C,
+	GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD,
+	GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1,
+	GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3,
+	GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C,
+	GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C,
+	GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C,
+	GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C,
+	GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA,
+	GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B,
+	GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP,
+	GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B,
+	GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK,
+	GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B,
+	GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0,
+	GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B,
+	GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E,
+	GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B,
+	GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E,
+	GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B,
+
+	/* IPSR15 */
+	GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D,
+	GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C,
+	GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D,
+	GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B,
+	GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C,
+	GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5,
+	GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C,
+	GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6,
+	GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C,
+	GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C,
+	GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C,
+	GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N,
+	GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C,
+	GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK,
+	GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C,
+	GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C,
+	GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C,
+	GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C,
+	GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C,
+
+	/* IPSR16 */
+	GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B,
+	GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C,
+	GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B,
+	GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C,
+	GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C,
+	GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N,
+	GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B,
+	GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N,
+	GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B,
+};
+
+#endif /* __ASM_R8A7791_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h
new file mode 100644
index 000000000..ff3018059
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -0,0 +1,665 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7791.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_R8A7791_H
+#define __ASM_ARCH_R8A7791_H
+
+/*
+ * R8A7791 I/O Addresses
+ */
+#define	RWDT_BASE	0xE6020000
+#define	SWDT_BASE	0xE6030000
+#define	LBSC_BASE	0xFEC00200
+#define DBSC3_0_BASE	0xE6790000
+#define DBSC3_1_BASE	0xE67A0000
+#define TMU_BASE	0xE61E0000
+#define	GPIO5_BASE	0xE6055000
+#define SH_QSPI_BASE	0xE6B10000
+
+#define S3C_BASE	0xE6784000
+#define S3C_INT_BASE	0xE6784A00
+#define S3C_MEDIA_BASE	0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE	0xE6784BDC
+#define S3C_QOS_CCI0_BASE	0xE6784C00
+#define S3C_QOS_CCI1_BASE	0xE6784C24
+#define S3C_QOS_MXI_BASE	0xE6784C48
+#define S3C_QOS_AXI_BASE	0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE	0xE6791000
+#define DBSC3_0_QOS_R1_BASE	0xE6791100
+#define DBSC3_0_QOS_R2_BASE	0xE6791200
+#define DBSC3_0_QOS_R3_BASE	0xE6791300
+#define DBSC3_0_QOS_R4_BASE	0xE6791400
+#define DBSC3_0_QOS_R5_BASE	0xE6791500
+#define DBSC3_0_QOS_R6_BASE	0xE6791600
+#define DBSC3_0_QOS_R7_BASE	0xE6791700
+#define DBSC3_0_QOS_R8_BASE	0xE6791800
+#define DBSC3_0_QOS_R9_BASE	0xE6791900
+#define DBSC3_0_QOS_R10_BASE	0xE6791A00
+#define DBSC3_0_QOS_R11_BASE	0xE6791B00
+#define DBSC3_0_QOS_R12_BASE	0xE6791C00
+#define DBSC3_0_QOS_R13_BASE	0xE6791D00
+#define DBSC3_0_QOS_R14_BASE	0xE6791E00
+#define DBSC3_0_QOS_R15_BASE	0xE6791F00
+#define DBSC3_0_QOS_W0_BASE	0xE6792000
+#define DBSC3_0_QOS_W1_BASE	0xE6792100
+#define DBSC3_0_QOS_W2_BASE	0xE6792200
+#define DBSC3_0_QOS_W3_BASE	0xE6792300
+#define DBSC3_0_QOS_W4_BASE	0xE6792400
+#define DBSC3_0_QOS_W5_BASE	0xE6792500
+#define DBSC3_0_QOS_W6_BASE	0xE6792600
+#define DBSC3_0_QOS_W7_BASE	0xE6792700
+#define DBSC3_0_QOS_W8_BASE	0xE6792800
+#define DBSC3_0_QOS_W9_BASE	0xE6792900
+#define DBSC3_0_QOS_W10_BASE	0xE6792A00
+#define DBSC3_0_QOS_W11_BASE	0xE6792B00
+#define DBSC3_0_QOS_W12_BASE	0xE6792C00
+#define DBSC3_0_QOS_W13_BASE	0xE6792D00
+#define DBSC3_0_QOS_W14_BASE	0xE6792E00
+#define DBSC3_0_QOS_W15_BASE	0xE6792F00
+
+#define DBSC3_1_QOS_R0_BASE	0xE67A1000
+#define DBSC3_1_QOS_R1_BASE	0xE67A1100
+#define DBSC3_1_QOS_R2_BASE	0xE67A1200
+#define DBSC3_1_QOS_R3_BASE	0xE67A1300
+#define DBSC3_1_QOS_R4_BASE	0xE67A1400
+#define DBSC3_1_QOS_R5_BASE	0xE67A1500
+#define DBSC3_1_QOS_R6_BASE	0xE67A1600
+#define DBSC3_1_QOS_R7_BASE	0xE67A1700
+#define DBSC3_1_QOS_R8_BASE	0xE67A1800
+#define DBSC3_1_QOS_R9_BASE	0xE67A1900
+#define DBSC3_1_QOS_R10_BASE	0xE67A1A00
+#define DBSC3_1_QOS_R11_BASE	0xE67A1B00
+#define DBSC3_1_QOS_R12_BASE	0xE67A1C00
+#define DBSC3_1_QOS_R13_BASE	0xE67A1D00
+#define DBSC3_1_QOS_R14_BASE	0xE67A1E00
+#define DBSC3_1_QOS_R15_BASE	0xE67A1F00
+#define DBSC3_1_QOS_W0_BASE	0xE67A2000
+#define DBSC3_1_QOS_W1_BASE	0xE67A2100
+#define DBSC3_1_QOS_W2_BASE	0xE67A2200
+#define DBSC3_1_QOS_W3_BASE	0xE67A2300
+#define DBSC3_1_QOS_W4_BASE	0xE67A2400
+#define DBSC3_1_QOS_W5_BASE	0xE67A2500
+#define DBSC3_1_QOS_W6_BASE	0xE67A2600
+#define DBSC3_1_QOS_W7_BASE	0xE67A2700
+#define DBSC3_1_QOS_W8_BASE	0xE67A2800
+#define DBSC3_1_QOS_W9_BASE	0xE67A2900
+#define DBSC3_1_QOS_W10_BASE	0xE67A2A00
+#define DBSC3_1_QOS_W11_BASE	0xE67A2B00
+#define DBSC3_1_QOS_W12_BASE	0xE67A2C00
+#define DBSC3_1_QOS_W13_BASE	0xE67A2D00
+#define DBSC3_1_QOS_W14_BASE	0xE67A2E00
+#define DBSC3_1_QOS_W15_BASE	0xE67A2F00
+
+#define DBSC3_0_DBADJ2		0xE67900C8
+
+#define CCI_400_MAXOT_1		0xF0091110
+#define CCI_400_MAXOT_2		0xF0092110
+#define CCI_400_QOSCNTL_1	0xF009110C
+#define CCI_400_QOSCNTL_2	0xF009210C
+
+#define	MXI_BASE		0xFE960000
+#define	MXI_QOS_BASE		0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE	0xFF800300
+#define SYS_AXI_AVB_BASE	0xFF800340
+#define SYS_AXI_G2D_BASE	0xFF800540
+#define SYS_AXI_IMP0_BASE	0xFF800580
+#define SYS_AXI_IMP1_BASE	0xFF8005C0
+#define SYS_AXI_IMUX0_BASE	0xFF800600
+#define SYS_AXI_IMUX1_BASE	0xFF800640
+#define SYS_AXI_IMUX2_BASE	0xFF800680
+#define SYS_AXI_LBS_BASE	0xFF8006C0
+#define SYS_AXI_MMUDS_BASE	0xFF800700
+#define SYS_AXI_MMUM_BASE	0xFF800740
+#define SYS_AXI_MMUR_BASE	0xFF800780
+#define SYS_AXI_MMUS0_BASE	0xFF8007C0
+#define SYS_AXI_MMUS1_BASE	0xFF800800
+#define SYS_AXI_MTSB0_BASE	0xFF800880
+#define SYS_AXI_MTSB1_BASE	0xFF8008C0
+#define SYS_AXI_PCI_BASE	0xFF800900
+#define SYS_AXI_RTX_BASE	0xFF800940
+#define SYS_AXI_SDS0_BASE	0xFF800A80
+#define SYS_AXI_SDS1_BASE	0xFF800AC0
+#define SYS_AXI_USB20_BASE	0xFF800C00
+#define SYS_AXI_USB21_BASE	0xFF800C40
+#define SYS_AXI_USB22_BASE	0xFF800C80
+#define SYS_AXI_USB30_BASE	0xFF800CC0
+#define SYS_AXI_AX2M_BASE	0xFF800380
+#define SYS_AXI_CC50_BASE	0xFF8003C0
+#define SYS_AXI_CCI_BASE	0xFF800440
+#define SYS_AXI_CS_BASE		0xFF800480
+#define SYS_AXI_DDM_BASE	0xFF8004C0
+#define SYS_AXI_ETH_BASE	0xFF800500
+#define SYS_AXI_MPXM_BASE	0xFF800840
+#define SYS_AXI_SAT0_BASE	0xFF800980
+#define SYS_AXI_SAT1_BASE	0xFF8009C0
+#define SYS_AXI_SDM0_BASE	0xFF800A00
+#define SYS_AXI_SDM1_BASE	0xFF800A40
+#define SYS_AXI_TRAB_BASE	0xFF800B00
+#define SYS_AXI_UDM0_BASE	0xFF800B80
+#define SYS_AXI_UDM1_BASE	0xFF800BC0
+
+#define RT_AXI_SHX_BASE		0xFF810100
+#define RT_AXI_DBG_BASE		0xFF810140
+#define RT_AXI_RDM_BASE		0xFF810180
+#define RT_AXI_RDS_BASE		0xFF8101C0
+#define RT_AXI_RTX64TO128_BASE	0xFF810200
+#define RT_AXI_STPRO_BASE	0xFF810240
+#define RT_AXI_SY2RT_BASE	0xFF810280
+
+#define MP_AXI_ADSP_BASE	0xFF820100
+#define MP_AXI_ASDS0_BASE	0xFF8201C0
+#define MP_AXI_ASDS1_BASE	0xFF820200
+#define MP_AXI_MLP_BASE		0xFF820240
+#define MP_AXI_MMUMP_BASE	0xFF820280
+#define MP_AXI_SPU_BASE		0xFF8202C0
+#define MP_AXI_SPUC_BASE	0xFF820300
+
+#define SYS_AXI256_AXI128TO256_BASE	0xFF860100
+#define SYS_AXI256_SYX_BASE	0xFF860140
+#define SYS_AXI256_MPX_BASE	0xFF860180
+#define SYS_AXI256_MXI_BASE	0xFF8601C0
+
+#define CCI_AXI_MMUS0_BASE	0xFF880100
+#define CCI_AXI_SYX2_BASE	0xFF880140
+#define CCI_AXI_MMUR_BASE	0xFF880180
+#define CCI_AXI_MMUDS_BASE	0xFF8801C0
+#define CCI_AXI_MMUM_BASE	0xFF880200
+#define CCI_AXI_MXI_BASE	0xFF880240
+#define CCI_AXI_MMUS1_BASE	0xFF880280
+#define CCI_AXI_MMUMP_BASE	0xFF8802C0
+
+#define MEDIA_AXI_MXR_BASE	0xFE960080
+#define MEDIA_AXI_MXW_BASE	0xFE9600C0
+#define MEDIA_AXI_JPR_BASE	0xFE964100
+#define MEDIA_AXI_JPW_BASE	0xFE966100
+#define MEDIA_AXI_GCU0R_BASE	0xFE964140
+#define MEDIA_AXI_GCU0W_BASE	0xFE966140
+#define MEDIA_AXI_GCU1R_BASE	0xFE964180
+#define MEDIA_AXI_GCU1W_BASE	0xFE966180
+#define MEDIA_AXI_TDMR_BASE	0xFE964500
+#define MEDIA_AXI_TDMW_BASE	0xFE966500
+#define MEDIA_AXI_VSP0CR_BASE	0xFE964540
+#define MEDIA_AXI_VSP0CW_BASE	0xFE966540
+#define MEDIA_AXI_VSP1CR_BASE	0xFE964580
+#define MEDIA_AXI_VSP1CW_BASE	0xFE966580
+#define MEDIA_AXI_VSPDU0CR_BASE	0xFE9645C0
+#define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
+#define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
+#define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
+#define MEDIA_AXI_VIN0W_BASE	0xFE966900
+#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
+#define MEDIA_AXI_FDP0R_BASE	0xFE964D40
+#define MEDIA_AXI_FDP0W_BASE	0xFE966D40
+#define MEDIA_AXI_IMSR_BASE	0xFE964D80
+#define MEDIA_AXI_IMSW_BASE	0xFE966D80
+#define MEDIA_AXI_VSP1R_BASE	0xFE965100
+#define MEDIA_AXI_VSP1W_BASE	0xFE967100
+#define MEDIA_AXI_FDP1R_BASE	0xFE965140
+#define MEDIA_AXI_FDP1W_BASE	0xFE967140
+#define MEDIA_AXI_IMRR_BASE	0xFE965180
+#define MEDIA_AXI_IMRW_BASE	0xFE967180
+#define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
+#define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
+#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
+#define MEDIA_AXI_DU0R_BASE	0xFE965580
+#define MEDIA_AXI_DU0W_BASE	0xFE967580
+#define MEDIA_AXI_DU1R_BASE	0xFE9655C0
+#define MEDIA_AXI_DU1W_BASE	0xFE9675C0
+#define MEDIA_AXI_VCP0CR_BASE	0xFE965900
+#define MEDIA_AXI_VCP0CW_BASE	0xFE967900
+#define MEDIA_AXI_VCP0VR_BASE	0xFE965940
+#define MEDIA_AXI_VCP0VW_BASE	0xFE967940
+#define MEDIA_AXI_VPC0R_BASE	0xFE965980
+#define MEDIA_AXI_VCP1CR_BASE	0xFE965D00
+#define MEDIA_AXI_VCP1CW_BASE	0xFE967D00
+#define MEDIA_AXI_VCP1VR_BASE	0xFE965D40
+#define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
+#define MEDIA_AXI_VPC1R_BASE	0xFE965D80
+
+#define SYS_AXI_AVBDMSCR	0xFF802000
+#define SYS_AXI_SYX2DMSCR	0xFF802004
+#define SYS_AXI_CC50DMSCR	0xFF802008
+#define SYS_AXI_CC51DMSCR	0xFF80200C
+#define SYS_AXI_CCIDMSCR	0xFF802010
+#define SYS_AXI_CSDMSCR		0xFF802014
+#define SYS_AXI_DDMDMSCR	0xFF802018
+#define SYS_AXI_ETHDMSCR	0xFF80201C
+#define SYS_AXI_G2DDMSCR	0xFF802020
+#define SYS_AXI_IMP0DMSCR	0xFF802024
+#define SYS_AXI_IMP1DMSCR	0xFF802028
+#define SYS_AXI_LBSDMSCR	0xFF80202C
+#define SYS_AXI_MMUDSDMSCR	0xFF802030
+#define SYS_AXI_MMUMXDMSCR	0xFF802034
+#define SYS_AXI_MMURDDMSCR	0xFF802038
+#define SYS_AXI_MMUS0DMSCR	0xFF80203C
+#define SYS_AXI_MMUS1DMSCR	0xFF802040
+#define SYS_AXI_MPXDMSCR	0xFF802044
+#define SYS_AXI_MTSB0DMSCR	0xFF802048
+#define SYS_AXI_MTSB1DMSCR	0xFF80204C
+#define SYS_AXI_PCIDMSCR	0xFF802050
+#define SYS_AXI_RTXDMSCR	0xFF802054
+#define SYS_AXI_SAT0DMSCR	0xFF802058
+#define SYS_AXI_SAT1DMSCR	0xFF80205C
+#define SYS_AXI_SDM0DMSCR	0xFF802060
+#define SYS_AXI_SDM1DMSCR	0xFF802064
+#define SYS_AXI_SDS0DMSCR	0xFF802068
+#define SYS_AXI_SDS1DMSCR	0xFF80206C
+#define SYS_AXI_ETRABDMSCR	0xFF802070
+#define SYS_AXI_ETRKFDMSCR	0xFF802074
+#define SYS_AXI_UDM0DMSCR	0xFF802078
+#define SYS_AXI_UDM1DMSCR	0xFF80207C
+#define SYS_AXI_USB20DMSCR	0xFF802080
+#define SYS_AXI_USB21DMSCR	0xFF802084
+#define SYS_AXI_USB22DMSCR	0xFF802088
+#define SYS_AXI_USB30DMSCR	0xFF80208C
+#define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
+#define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
+#define SYS_AXI_AVBSLVDMSCR	0xFF802108
+#define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
+#define SYS_AXI_ETHSLVDMSCR	0xFF802110
+#define SYS_AXI_GICSLVDMSCR	0xFF802114
+#define SYS_AXI_IMPSLVDMSCR	0xFF802118
+#define SYS_AXI_IMX0SLVDMSCR	0xFF80211C
+#define SYS_AXI_IMX1SLVDMSCR	0xFF802120
+#define SYS_AXI_IMX2SLVDMSCR	0xFF802124
+#define SYS_AXI_LBSSLVDMSCR	0xFF802128
+#define SYS_AXI_MMC0SLVDMSCR	0xFF80212C
+#define SYS_AXI_MMC1SLVDMSCR	0xFF802130
+#define SYS_AXI_MPXSLVDMSCR	0xFF802134
+#define SYS_AXI_MTSB0SLVDMSCR	0xFF802138
+#define SYS_AXI_MTSB1SLVDMSCR	0xFF80213C
+#define SYS_AXI_MXTSLVDMSCR	0xFF802140
+#define SYS_AXI_PCISLVDMSCR	0xFF802144
+#define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
+#define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
+#define SYS_AXI_RTXSLVDMSCR	0xFF802150
+#define SYS_AXI_SAT0SLVDMSCR	0xFF802168
+#define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
+#define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
+#define SYS_AXI_SDAP1SLVDMSCR	0xFF802174
+#define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
+#define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
+#define SYS_AXI_SGXSLVDMSCR	0xFF802180
+#define SYS_AXI_STBSLVDMSCR	0xFF802188
+#define SYS_AXI_STMSLVDMSCR	0xFF80218C
+#define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
+#define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
+#define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
+#define SYS_AXI_USB20SLVDMSCR	0xFF8021A0
+#define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
+#define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
+#define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
+
+#define RT_AXI_CBMDMSCR		0xFF812000
+#define RT_AXI_DBDMSCR		0xFF812004
+#define RT_AXI_RDMDMSCR		0xFF812008
+#define RT_AXI_RDSDMSCR		0xFF81200C
+#define RT_AXI_STRDMSCR		0xFF812010
+#define RT_AXI_SY2RTDMSCR	0xFF812014
+#define RT_AXI_CBSSLVDMSCR	0xFF812100
+#define RT_AXI_DBSSLVDMSCR	0xFF812104
+#define RT_AXI_RTAP1SLVDMSCR	0xFF812108
+#define RT_AXI_RTAP2SLVDMSCR	0xFF81210C
+#define RT_AXI_RTAP3SLVDMSCR	0xFF812110
+#define RT_AXI_RT2SYSLVDMSCR	0xFF812114
+#define RT_AXI_A128TO64SLVDMSCR	0xFF812118
+#define RT_AXI_A64TO128SLVDMSCR	0xFF81211C
+#define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
+#define RT_AXI_UTLBRSLVDMSCR	0xFF812128
+
+#define MP_AXI_ADSPDMSCR	0xFF822000
+#define MP_AXI_ASDM0DMSCR	0xFF822004
+#define MP_AXI_ASDM1DMSCR	0xFF822008
+#define MP_AXI_ASDS0DMSCR	0xFF82200C
+#define MP_AXI_ASDS1DMSCR	0xFF822010
+#define MP_AXI_MLPDMSCR		0xFF822014
+#define MP_AXI_MMUMPDMSCR	0xFF822018
+#define MP_AXI_SPUDMSCR		0xFF82201C
+#define MP_AXI_SPUCDMSCR	0xFF822020
+#define MP_AXI_SY2MPDMSCR	0xFF822024
+#define MP_AXI_ADSPSLVDMSCR	0xFF822100
+#define MP_AXI_MLMSLVDMSCR	0xFF822104
+#define MP_AXI_MPAP4SLVDMSCR	0xFF822108
+#define MP_AXI_MPAP5SLVDMSCR	0xFF82210C
+#define MP_AXI_MPAP6SLVDMSCR	0xFF822110
+#define MP_AXI_MPAP7SLVDMSCR	0xFF822114
+#define MP_AXI_MP2SYSLVDMSCR	0xFF822118
+#define MP_AXI_MP2SY2SLVDMSCR	0xFF82211C
+#define MP_AXI_MPXAPSLVDMSCR	0xFF822124
+#define MP_AXI_SPUSLVDMSCR	0xFF822128
+#define MP_AXI_UTLBMPSLVDMSCR	0xFF82212C
+
+#define ADM_AXI_ASDM0DMSCR	0xFF842000
+#define ADM_AXI_ASDM1DMSCR	0xFF842004
+#define ADM_AXI_MPAP1SLVDMSCR	0xFF842104
+#define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
+#define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
+
+#define DM_AXI_RDMDMSCR		0xFF852000
+#define DM_AXI_SDM0DMSCR	0xFF852004
+#define DM_AXI_SDM1DMSCR	0xFF852008
+#define DM_AXI_MMAP0SLVDMSCR	0xFF852100
+#define DM_AXI_MMAP1SLVDMSCR	0xFF852104
+#define DM_AXI_QSPAPSLVDMSCR	0xFF852108
+#define DM_AXI_RAP4SLVDMSCR	0xFF85210C
+#define DM_AXI_RAP5SLVDMSCR	0xFF852110
+#define DM_AXI_SAP4SLVDMSCR	0xFF852114
+#define DM_AXI_SAP5SLVDMSCR	0xFF852118
+#define DM_AXI_SAP6SLVDMSCR	0xFF85211C
+#define DM_AXI_SAP65SLVDMSCR	0xFF852120
+#define DM_AXI_SDAP0SLVDMSCR	0xFF852124
+#define DM_AXI_SDAP1SLVDMSCR	0xFF852128
+#define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
+#define DM_AXI_SDAP3SLVDMSCR	0xFF852130
+
+#define SYS_AXI256_SYXDMSCR	0xFF862000
+#define SYS_AXI256_MPXDMSCR	0xFF862004
+#define SYS_AXI256_MXIDMSCR	0xFF862008
+#define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
+#define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
+#define SYS_AXI256_SYXSLVDMSCR	0xFF862108
+#define SYS_AXI256_CCXSLVDMSCR	0xFF86210C
+#define SYS_AXI256_S3CSLVDMSCR	0xFF862110
+
+#define MXT_SYXDMSCR		0xFF872000
+#define MXT_CMM0SLVDMSCR	0xFF872100
+#define MXT_CMM1SLVDMSCR	0xFF872104
+#define MXT_CMM2SLVDMSCR	0xFF872108
+#define MXT_FDPSLVDMSCR		0xFF87210C
+#define MXT_IMRSLVDMSCR		0xFF872110
+#define MXT_VINSLVDMSCR		0xFF872114
+#define MXT_VPC0SLVDMSCR	0xFF872118
+#define MXT_VPC1SLVDMSCR	0xFF87211C
+#define MXT_VSP0SLVDMSCR	0xFF872120
+#define MXT_VSP1SLVDMSCR	0xFF872124
+#define MXT_VSPD0SLVDMSCR	0xFF872128
+#define MXT_VSPD1SLVDMSCR	0xFF87212C
+#define MXT_MAP1SLVDMSCR	0xFF872130
+#define MXT_MAP2SLVDMSCR	0xFF872134
+
+#define CCI_AXI_MMUS0DMSCR	0xFF882000
+#define CCI_AXI_SYX2DMSCR	0xFF882004
+#define CCI_AXI_MMURDMSCR	0xFF882008
+#define CCI_AXI_MMUDSDMSCR	0xFF88200C
+#define CCI_AXI_MMUMDMSCR	0xFF882010
+#define CCI_AXI_MXIDMSCR	0xFF882014
+#define CCI_AXI_MMUS1DMSCR	0xFF882018
+#define CCI_AXI_MMUMPDMSCR	0xFF88201C
+#define CCI_AXI_DVMDMSCR	0xFF882020
+#define CCI_AXI_CCISLVDMSCR	0xFF882100
+
+#define CCI_AXI_IPMMUIDVMCR	0xFF880400
+#define CCI_AXI_IPMMURDVMCR	0xFF880404
+#define CCI_AXI_IPMMUS0DVMCR	0xFF880408
+#define CCI_AXI_IPMMUS1DVMCR	0xFF88040C
+#define CCI_AXI_IPMMUMPDVMCR	0xFF880410
+#define CCI_AXI_IPMMUDSDVMCR	0xFF880414
+#define CCI_AXI_AX2ADDRMASK	0xFF88041C
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct r8a7791_rwdt {
+	u32 rwtcnt;	/* 0x00 */
+	u32 rwtcsra;	/* 0x04 */
+	u16 rwtcsrb;	/* 0x08 */
+};
+
+/* SWDT */
+struct r8a7791_swdt {
+	u32 swtcnt;	/* 0x00 */
+	u32 swtcsra;	/* 0x04 */
+	u16 swtcsrb;	/* 0x08 */
+};
+
+/* LBSC */
+struct r8a7791_lbsc {
+	u32 cs0ctrl;
+	u32 cs1ctrl;
+	u32 ecs0ctrl;
+	u32 ecs1ctrl;
+	u32 ecs2ctrl;
+	u32 ecs3ctrl;
+	u32 ecs4ctrl;
+	u32 ecs5ctrl;
+	u32 dummy0[4];	/* 0x20 .. 0x2C */
+	u32 cswcr0;
+	u32 cswcr1;
+	u32 ecswcr0;
+	u32 ecswcr1;
+	u32 ecswcr2;
+	u32 ecswcr3;
+	u32 ecswcr4;
+	u32 ecswcr5;
+	u32 exdmawcr0;
+	u32 exdmawcr1;
+	u32 exdmawcr2;
+	u32 dummy1[9];	/* 0x5C .. 0x7C */
+	u32 cspwcr0;
+	u32 cspwcr1;
+	u32 ecspwcr0;
+	u32 ecspwcr1;
+	u32 ecspwcr2;
+	u32 ecspwcr3;
+	u32 ecspwcr4;
+	u32 ecspwcr5;
+	u32 exwtsync;
+	u32 dummy2[3];	/* 0xA4 .. 0xAC */
+	u32 cs0bstctl;
+	u32 cs0btph;
+	u32 dummy3[2];	/* 0xB8 .. 0xBC */
+	u32 cs1gdst;
+	u32 ecs0gdst;
+	u32 ecs1gdst;
+	u32 ecs2gdst;
+	u32 ecs3gdst;
+	u32 ecs4gdst;
+	u32 ecs5gdst;
+	u32 dummy4[5];	/* 0xDC .. 0xEC */
+	u32 exdmaset0;
+	u32 exdmaset1;
+	u32 exdmaset2;
+	u32 dummy5[5];	/* 0xFC .. 0x10C */
+	u32 exdmcr0;
+	u32 exdmcr1;
+	u32 exdmcr2;
+	u32 dummy6[5];	/* 0x11C .. 0x12C */
+	u32 bcintsr;
+	u32 bcintcr;
+	u32 bcintmr;
+	u32 dummy7;	/* 0x13C */
+	u32 exbatlv;
+	u32 exwtsts;
+	u32 dummy8[14];	/* 0x148 .. 0x17C */
+	u32 atacsctrl;
+	u32 dummy9[15]; /* 0x184 .. 0x1BC */
+	u32 exbct;
+	u32 extct;
+};
+
+/* DBSC3 */
+struct r8a7791_dbsc3 {
+	u32 dummy0[3];	/* 0x00 .. 0x08 */
+	u32 dbstate1;
+	u32 dbacen;
+	u32 dbrfen;
+	u32 dbcmd;
+	u32 dbwait;
+	u32 dbkind;
+	u32 dbconf0;
+	u32 dummy1[2];	/* 0x28 .. 0x2C */
+	u32 dbphytype;
+	u32 dummy2[3];	/* 0x34 .. 0x3C */
+	u32 dbtr0;
+	u32 dbtr1;
+	u32 dbtr2;
+	u32 dummy3;	/* 0x4C */
+	u32 dbtr3;
+	u32 dbtr4;
+	u32 dbtr5;
+	u32 dbtr6;
+	u32 dbtr7;
+	u32 dbtr8;
+	u32 dbtr9;
+	u32 dbtr10;
+	u32 dbtr11;
+	u32 dbtr12;
+	u32 dbtr13;
+	u32 dbtr14;
+	u32 dbtr15;
+	u32 dbtr16;
+	u32 dbtr17;
+	u32 dbtr18;
+	u32 dbtr19;
+	u32 dummy4[7];	/* 0x94 .. 0xAC */
+	u32 dbbl;
+	u32 dummy5[3];	/* 0xB4 .. 0xBC */
+	u32 dbadj0;
+	u32 dummy6;	/* 0xC4 */
+	u32 dbadj2;
+	u32 dummy7[5];	/* 0xCC .. 0xDC */
+	u32 dbrfcnf0;
+	u32 dbrfcnf1;
+	u32 dbrfcnf2;
+	u32 dummy8[2];	/* 0xEC .. 0xF0 */
+	u32 dbcalcnf;
+	u32 dbcaltr;
+	u32 dummy9;	/* 0xFC */
+	u32 dbrnk0;
+	u32 dummy10[31];	/* 0x104 .. 0x17C */
+	u32 dbpdncnf;
+	u32 dummy11[47];	/* 0x184 ..0x23C */
+	u32 dbdfistat;
+	u32 dbdficnt;
+	u32 dummy12[14];	/* 0x248 .. 0x27C */
+	u32 dbpdlck;
+	u32 dummy13[3];	/* 0x284 .. 0x28C */
+	u32 dbpdrga;
+	u32 dummy14[3];	/* 0x294 .. 0x29C */
+	u32 dbpdrgd;
+	u32 dummy15[24];	/* 0x2A4 .. 0x300 */
+	u32 dbbs0cnt1;
+	u32 dummy16[30];	/* 0x308 .. 0x37C */
+	u32 dbwt0cnf0;
+	u32 dbwt0cnf1;
+	u32 dbwt0cnf2;
+	u32 dbwt0cnf3;
+	u32 dbwt0cnf4;
+};
+
+/* GPIO */
+struct r8a7791_gpio {
+	u32 iointsel;
+	u32 inoutsel;
+	u32 outdt;
+	u32 indt;
+	u32 intdt;
+	u32 intclr;
+	u32 intmsk;
+	u32 posneg;
+	u32 edglevel;
+	u32 filonoff;
+	u32 intmsks;
+	u32 mskclrs;
+	u32 outdtsel;
+	u32 outdth;
+	u32 outdtl;
+	u32 bothedge;
+};
+
+/* S3C(QoS) */
+struct r8a7791_s3c {
+	u32 s3cexcladdmsk;
+	u32 s3cexclidmsk;
+	u32 s3cadsplcr;
+	u32 s3cmaar;
+	u32 dummy0;	/* 0x10 */
+	u32 s3crorr;
+	u32 s3cworr;
+	u32 s3carcr22;
+	u32 dummy1[2];	/* 0x20 .. 0x24 */
+	u32 s3cmctr;
+	u32 dummy2;	/* 0x2C */
+	u32 cconf0;
+	u32 cconf1;
+	u32 cconf2;
+	u32 cconf3;
+};
+
+struct r8a7791_s3c_qos {
+	u32 s3cqos0;
+	u32 s3cqos1;
+	u32 s3cqos2;
+	u32 s3cqos3;
+	u32 s3cqos4;
+	u32 s3cqos5;
+	u32 s3cqos6;
+	u32 s3cqos7;
+	u32 s3cqos8;
+};
+
+/* DBSC(QoS) */
+struct r8a7791_dbsc3_qos {
+	u32 dblgcnt;
+	u32 dbtmval0;
+	u32 dbtmval1;
+	u32 dbtmval2;
+	u32 dbtmval3;
+	u32 dbrqctr;
+	u32 dbthres0;
+	u32 dbthres1;
+	u32 dbthres2;
+	u32 dummy0;	/* 0x24 */
+	u32 dblgqon;
+};
+
+/* MXI(QoS) */
+struct r8a7791_mxi {
+	u32 mxsaar0;
+	u32 mxsaar1;
+	u32 dummy0[8];	/* 0x08 .. 0x24 */
+	u32 mxs3cracr;
+	u32 dummy1[3];	/* 0x2C .. 0x34 */
+	u32 mxs3cwacr;
+	u32 dummy2;	/* 0x3C */
+	u32 mxrtcr;
+	u32 mxwtcr;
+};
+
+struct r8a7791_mxi_qos {
+	u32 vspdu0;
+	u32 vspdu1;
+	u32 du0;
+	u32 du1;
+};
+
+/* AXI(QoS) */
+struct r8a7791_axi_qos {
+	u32 qosconf;
+	u32 qosctset0;
+	u32 qosctset1;
+	u32 qosctset2;
+	u32 qosctset3;
+	u32 qosreqctr;
+	u32 qosthres0;
+	u32 qosthres1;
+	u32 qosthres2;
+	u32 qosqon;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_R8A7791_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/rmobile.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/rmobile.h
new file mode 100644
index 000000000..238256502
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/rmobile.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_ARCH_RMOBILE_H
+#define __ASM_ARCH_RMOBILE_H
+
+#if defined(CONFIG_RMOBILE)
+#if defined(CONFIG_SH73A0)
+#include <asm/arch/sh73a0.h>
+#elif defined(CONFIG_R8A7740)
+#include <asm/arch/r8a7740.h>
+#elif defined(CONFIG_R8A7790)
+#include <asm/arch/r8a7790.h>
+#elif defined(CONFIG_R8A7791)
+#include <asm/arch/r8a7791.h>
+#else
+#error "SOC Name not defined"
+#endif
+#endif /* CONFIG_RMOBILE */
+
+#endif /* __ASM_ARCH_RMOBILE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h
new file mode 100644
index 000000000..398e2c109
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h
@@ -0,0 +1,553 @@
+#ifndef __ASM_SH73A0_H__
+#define __ASM_SH73A0_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function and MSEL switch
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	/* Hardware manual Table 25-1 (GPIO) */
+	GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+	GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+	GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+	GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+	GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+	GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+	GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+	GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+	GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+	GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+	GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+	GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+	GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+	GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+	GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+	GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+	GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+	GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+	GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+	GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+	GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+	GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+	GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+	GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
+
+	GPIO_PORT128, GPIO_PORT129,
+
+	GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+	GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+	GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+	GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+	GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+	GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+	GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+
+	GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+	GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+	GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+	GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+	GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+	GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+
+	GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
+	GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+
+	GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+	GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+
+	GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+	GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+
+	GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
+	GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+
+	GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+	GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
+
+	GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
+	GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
+
+	GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
+
+	GPIO_PORT288, GPIO_PORT289,
+
+	GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
+	GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
+
+	GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
+	GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
+
+	/* Table 25-1 (Function 0-7) */
+	GPIO_FN_VBUS_0,
+	GPIO_FN_GPI0,
+	GPIO_FN_GPI1,
+	GPIO_FN_GPI2,
+	GPIO_FN_GPI3,
+	GPIO_FN_GPI4,
+	GPIO_FN_GPI5,
+	GPIO_FN_GPI6,
+	GPIO_FN_GPI7,
+	GPIO_FN_SCIFA7_RXD,
+	GPIO_FN_SCIFA7_CTS_,
+	GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
+	GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
+	GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+	GPIO_FN_PORT16_VIO_CKOR,
+	GPIO_FN_SCIFA0_TXD,
+	GPIO_FN_SCIFA7_TXD,
+	GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+	GPIO_FN_GPO0,
+	GPIO_FN_GPO1,
+	GPIO_FN_GPO2, GPIO_FN_STATUS0,
+	GPIO_FN_GPO3, GPIO_FN_STATUS1,
+	GPIO_FN_GPO4, GPIO_FN_STATUS2,
+	GPIO_FN_VINT,
+	GPIO_FN_TCKON,
+	GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+	GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
+	GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+	GPIO_FN_PORT28_TPU1TO1,
+	GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
+	GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
+	GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
+	GPIO_FN_SCIFA4_TXD,
+	GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
+	GPIO_FN_SCIFA4_RTS_,
+	GPIO_FN_SCIFA4_CTS_,
+	GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
+	GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
+	GPIO_FN_FSIBOSLD,
+	GPIO_FN_FSIBISLD,
+	GPIO_FN_VACK,
+	GPIO_FN_XTAL1L,
+	GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
+	GPIO_FN_SCIFA0_RXD,
+	GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
+	GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
+	GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
+	GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
+	GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
+	GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
+	GPIO_FN_FSIAOMC,
+	GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
+
+	GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
+	GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
+	GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
+	GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
+	GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
+	GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
+	GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+	GPIO_FN_A0, GPIO_FN_BS_,
+	GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
+	GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
+	GPIO_FN_A14, GPIO_FN_KEYOUT5,
+	GPIO_FN_A15, GPIO_FN_KEYOUT4,
+	GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
+	GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
+	GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
+	GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
+	GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
+	GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
+	GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
+	GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
+	GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
+	GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
+	GPIO_FN_A26, GPIO_FN_KEYIN6,
+	GPIO_FN_KEYIN7,
+	GPIO_FN_D0_NAF0,
+	GPIO_FN_D1_NAF1,
+	GPIO_FN_D2_NAF2,
+	GPIO_FN_D3_NAF3,
+	GPIO_FN_D4_NAF4,
+	GPIO_FN_D5_NAF5,
+	GPIO_FN_D6_NAF6,
+	GPIO_FN_D7_NAF7,
+	GPIO_FN_D8_NAF8,
+	GPIO_FN_D9_NAF9,
+	GPIO_FN_D10_NAF10,
+	GPIO_FN_D11_NAF11,
+	GPIO_FN_D12_NAF12,
+	GPIO_FN_D13_NAF13,
+	GPIO_FN_D14_NAF14,
+	GPIO_FN_D15_NAF15,
+	GPIO_FN_CS4_,
+	GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
+	GPIO_FN_CS5B_, GPIO_FN_FCE1_,
+	GPIO_FN_CS6B_, GPIO_FN_DACK0,
+	GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+	GPIO_FN_WAIT_, GPIO_FN_DREQ0,
+	GPIO_FN_RD__FSC,
+	GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
+	GPIO_FN_WE1_,
+	GPIO_FN_FRB,
+	GPIO_FN_CKO,
+	GPIO_FN_NBRSTOUT_,
+	GPIO_FN_NBRST_,
+	GPIO_FN_BBIF2_TXD,
+	GPIO_FN_BBIF2_RXD,
+	GPIO_FN_BBIF2_SYNC,
+	GPIO_FN_BBIF2_SCK,
+	GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
+	GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
+	GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
+	GPIO_FN_SCIFA3_TXD,
+	GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
+	GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
+	GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
+	GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
+	GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
+	GPIO_FN_PORT115_I2C_SCL3,
+	GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
+	GPIO_FN_PORT116_I2C_SDA3,
+	GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
+	GPIO_FN_HSI_TX_FLAG,
+	GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
+	GPIO_FN_LCD2D0,
+
+	GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
+	GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
+	GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
+	GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
+	GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
+	GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
+	GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
+	GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
+	GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
+	GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
+	GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
+	GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
+	GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
+	GPIO_FN_LCD2D6,
+	GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
+	GPIO_FN_LCD2D7,
+	GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
+	GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
+	GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
+	GPIO_FN_LCD2D2,
+	GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
+	GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
+	GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
+	GPIO_FN_LCD2D4,
+	GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
+	GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
+	GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
+	GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
+	GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+	GPIO_FN_VIO_CKO,
+	GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
+	GPIO_FN_PORT149_KEYOUT9,
+	GPIO_FN_MFG0_IN2,
+	GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
+	GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
+	GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
+	GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
+	GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
+	GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
+	GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
+	GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
+	GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
+	GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
+	GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
+	GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
+	GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+	GPIO_FN_TPU3TO0,
+	GPIO_FN_LCDD0,
+	GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
+	GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
+	GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
+	GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
+	GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+	GPIO_FN_TPU2TO1,
+	GPIO_FN_LCDD6,
+	GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+	GPIO_FN_LCDD8, GPIO_FN_D16,
+	GPIO_FN_LCDD9, GPIO_FN_D17,
+	GPIO_FN_LCDD10, GPIO_FN_D18,
+	GPIO_FN_LCDD11, GPIO_FN_D19,
+	GPIO_FN_LCDD12, GPIO_FN_D20,
+	GPIO_FN_LCDD13, GPIO_FN_D21,
+	GPIO_FN_LCDD14, GPIO_FN_D22,
+	GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+	GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+	GPIO_FN_LCDD17, GPIO_FN_D25,
+	GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+	GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+	GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+	GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+	GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+	GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+	GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
+	GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
+	GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
+	GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+	GPIO_FN_PORT218_VIO_CKOR,
+	GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
+	GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
+	GPIO_FN_LCD2DCK_2,
+	GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
+	GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+	GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
+	GPIO_FN_PORT221_LCD2HSYN,
+	GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
+	GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
+
+	GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
+	GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
+	GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
+	GPIO_FN_SCIFA1_RXD,
+	GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
+	GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
+	GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
+	GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
+	GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
+	GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
+	GPIO_FN_LCD2D20,
+	GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
+	GPIO_FN_LCD2D21,
+	GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
+	GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
+	GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
+	GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
+	GPIO_FN_SCIFA6_TXD,
+	GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+	GPIO_FN_TPU4TO0,
+	GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
+	GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
+	GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
+	GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
+	GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
+	GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
+	GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
+	GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
+	GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
+	GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
+	GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
+	GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
+	GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+	GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
+	GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+	GPIO_FN_SDHICLK0,
+	GPIO_FN_SDHICD0,
+	GPIO_FN_SDHID0_0,
+	GPIO_FN_SDHID0_1,
+	GPIO_FN_SDHID0_2,
+	GPIO_FN_SDHID0_3,
+	GPIO_FN_SDHICMD0,
+	GPIO_FN_SDHIWP0,
+	GPIO_FN_SDHICLK1,
+	GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
+	GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
+	GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
+	GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
+	GPIO_FN_SDHICMD1,
+	GPIO_FN_SDHICLK2,
+	GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
+	GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
+	GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
+	GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
+	GPIO_FN_SDHICMD2,
+	GPIO_FN_MMCCLK0,
+	GPIO_FN_MMCD0_0,
+	GPIO_FN_MMCD0_1,
+	GPIO_FN_MMCD0_2,
+	GPIO_FN_MMCD0_3,
+	GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
+	GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
+	GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
+	GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
+	GPIO_FN_MMCCMD0,
+	GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
+	GPIO_FN_MCP_WAIT__MCP_FRB,
+	GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
+	GPIO_FN_MCP_D15_MCP_NAF15,
+	GPIO_FN_MCP_D14_MCP_NAF14,
+	GPIO_FN_MCP_D13_MCP_NAF13,
+	GPIO_FN_MCP_D12_MCP_NAF12,
+	GPIO_FN_MCP_D11_MCP_NAF11,
+	GPIO_FN_MCP_D10_MCP_NAF10,
+	GPIO_FN_MCP_D9_MCP_NAF9,
+	GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
+	GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
+
+	GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
+	GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
+	GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
+	GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
+	GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
+	GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
+	GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
+	GPIO_FN_MCP_NBRSTOUT_,
+	GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
+
+	/* MSEL2 special case */
+	GPIO_FN_TSIF2_TS_XX1,
+	GPIO_FN_TSIF2_TS_XX2,
+	GPIO_FN_TSIF2_TS_XX3,
+	GPIO_FN_TSIF2_TS_XX4,
+	GPIO_FN_TSIF2_TS_XX5,
+	GPIO_FN_TSIF1_TS_XX1,
+	GPIO_FN_TSIF1_TS_XX2,
+	GPIO_FN_TSIF1_TS_XX3,
+	GPIO_FN_TSIF1_TS_XX4,
+	GPIO_FN_TSIF1_TS_XX5,
+	GPIO_FN_TSIF0_TS_XX1,
+	GPIO_FN_TSIF0_TS_XX2,
+	GPIO_FN_TSIF0_TS_XX3,
+	GPIO_FN_TSIF0_TS_XX4,
+	GPIO_FN_TSIF0_TS_XX5,
+	GPIO_FN_MST1_TS_XX1,
+	GPIO_FN_MST1_TS_XX2,
+	GPIO_FN_MST1_TS_XX3,
+	GPIO_FN_MST1_TS_XX4,
+	GPIO_FN_MST1_TS_XX5,
+	GPIO_FN_MST0_TS_XX1,
+	GPIO_FN_MST0_TS_XX2,
+	GPIO_FN_MST0_TS_XX3,
+	GPIO_FN_MST0_TS_XX4,
+	GPIO_FN_MST0_TS_XX5,
+
+	/* MSEL3 special cases */
+	GPIO_FN_SDHI0_VCCQ_MC0_ON,
+	GPIO_FN_SDHI0_VCCQ_MC0_OFF,
+	GPIO_FN_DEBUG_MON_VIO,
+	GPIO_FN_DEBUG_MON_LCDD,
+	GPIO_FN_LCDC_LCDC0,
+	GPIO_FN_LCDC_LCDC1,
+
+	/* MSEL4 special cases */
+	GPIO_FN_IRQ9_MEM_INT,
+	GPIO_FN_IRQ9_MCP_INT,
+	GPIO_FN_A11,
+	GPIO_FN_KEYOUT8,
+	GPIO_FN_TPU4TO3,
+	GPIO_FN_RESETA_N_PU_ON,
+	GPIO_FN_RESETA_N_PU_OFF,
+	GPIO_FN_EDBGREQ_PD,
+	GPIO_FN_EDBGREQ_PU,
+
+	/* Functions with pull-ups */
+	GPIO_FN_KEYIN0_PU,
+	GPIO_FN_KEYIN1_PU,
+	GPIO_FN_KEYIN2_PU,
+	GPIO_FN_KEYIN3_PU,
+	GPIO_FN_KEYIN4_PU,
+	GPIO_FN_KEYIN5_PU,
+	GPIO_FN_KEYIN6_PU,
+	GPIO_FN_KEYIN7_PU,
+	GPIO_FN_SDHICD0_PU,
+	GPIO_FN_SDHID0_0_PU,
+	GPIO_FN_SDHID0_1_PU,
+	GPIO_FN_SDHID0_2_PU,
+	GPIO_FN_SDHID0_3_PU,
+	GPIO_FN_SDHICMD0_PU,
+	GPIO_FN_SDHIWP0_PU,
+	GPIO_FN_SDHID1_0_PU,
+	GPIO_FN_SDHID1_1_PU,
+	GPIO_FN_SDHID1_2_PU,
+	GPIO_FN_SDHID1_3_PU,
+	GPIO_FN_SDHICMD1_PU,
+	GPIO_FN_SDHID2_0_PU,
+	GPIO_FN_SDHID2_1_PU,
+	GPIO_FN_SDHID2_2_PU,
+	GPIO_FN_SDHID2_3_PU,
+	GPIO_FN_SDHICMD2_PU,
+	GPIO_FN_MMCCMD0_PU,
+	GPIO_FN_MMCCMD1_PU,
+	GPIO_FN_MMCD0_0_PU,
+	GPIO_FN_MMCD0_1_PU,
+	GPIO_FN_MMCD0_2_PU,
+	GPIO_FN_MMCD0_3_PU,
+	GPIO_FN_MMCD0_4_PU,
+	GPIO_FN_MMCD0_5_PU,
+	GPIO_FN_MMCD0_6_PU,
+	GPIO_FN_MMCD0_7_PU,
+	GPIO_FN_FSIACK_PU,
+	GPIO_FN_FSIAILR_PU,
+	GPIO_FN_FSIAIBT_PU,
+	GPIO_FN_FSIAISLD_PU,
+
+	/* end of GPIO */
+	GPIO_NR,
+};
+
+/* DMA slave IDs */
+enum {
+	SHDMA_SLAVE_INVALID,
+	SHDMA_SLAVE_SCIF0_TX,
+	SHDMA_SLAVE_SCIF0_RX,
+	SHDMA_SLAVE_SCIF1_TX,
+	SHDMA_SLAVE_SCIF1_RX,
+	SHDMA_SLAVE_SCIF2_TX,
+	SHDMA_SLAVE_SCIF2_RX,
+	SHDMA_SLAVE_SCIF3_TX,
+	SHDMA_SLAVE_SCIF3_RX,
+	SHDMA_SLAVE_SCIF4_TX,
+	SHDMA_SLAVE_SCIF4_RX,
+	SHDMA_SLAVE_SCIF5_TX,
+	SHDMA_SLAVE_SCIF5_RX,
+	SHDMA_SLAVE_SCIF6_TX,
+	SHDMA_SLAVE_SCIF6_RX,
+	SHDMA_SLAVE_SCIF7_TX,
+	SHDMA_SLAVE_SCIF7_RX,
+	SHDMA_SLAVE_SCIF8_TX,
+	SHDMA_SLAVE_SCIF8_RX,
+	SHDMA_SLAVE_SDHI0_TX,
+	SHDMA_SLAVE_SDHI0_RX,
+	SHDMA_SLAVE_SDHI1_TX,
+	SHDMA_SLAVE_SDHI1_RX,
+	SHDMA_SLAVE_SDHI2_TX,
+	SHDMA_SLAVE_SDHI2_RX,
+	SHDMA_SLAVE_MMCIF_TX,
+	SHDMA_SLAVE_MMCIF_RX,
+};
+
+/*
+ *		SH73A0 IRQ LOCATION TABLE
+ *
+ * 416	-----------------------------------------
+ *		IRQ0-IRQ15
+ * 431	-----------------------------------------
+ * ...
+ * 448	-----------------------------------------
+ *		sh73a0-intcs
+ *		sh73a0-intca-irq-pins
+ * 680	-----------------------------------------
+ * ...
+ * 700	-----------------------------------------
+ *		sh73a0-pint0
+ * 731	-----------------------------------------
+ * 732	-----------------------------------------
+ *		sh73a0-pint1
+ * 739	-----------------------------------------
+ * ...
+ * 800	-----------------------------------------
+ *		IRQ16-IRQ31
+ * 815	-----------------------------------------
+ * ...
+ * 928	-----------------------------------------
+ *		sh73a0-intca-irq-pins
+ * 943	-----------------------------------------
+ */
+
+/* PINT interrupts are located at Linux IRQ 700 and up */
+#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
+#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
+
+#endif /* __ASM_SH73A0_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0.h
new file mode 100644
index 000000000..bdbb40864
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sh73a0.h
@@ -0,0 +1,289 @@
+#ifndef __ASM_ARCH_RMOBILE_SH73A0_H
+#define __ASM_ARCH_RMOBILE_SH73A0_H
+
+/* Global Timer */
+#define GLOBAL_TIMER_BASE_ADDR	(0xF0000200)
+#define MERAM_BASE	(0xE5580000)
+
+/* GIC */
+#define GIC_BASE	(0xF0000100)
+#define ICCICR	GIC_BASE
+
+/* Secure control register */
+#define LIFEC_SEC_SRC	(0xE6110008)
+
+/* RWDT */
+#define	RWDT_BASE   (0xE6020000)
+
+/* HPB Semaphore Control Registers */
+#define HPB_BASE	(0xE6001010)
+
+/* Bus Semaphore Control Registers */
+#define HPBSCR_BASE (0xE6001600)
+
+/* SBSC1 */
+#define SBSC1_BASE	(0xFE400000)
+#define	SDMRA1A		(SBSC1_BASE + 0x100000)
+#define	SDMRA2A		(SBSC1_BASE + 0x1C0000)
+#define	SDMRA3A		(SBSC1_BASE + 0x104000)
+
+/* SBSC2 */
+#define SBSC2_BASE	(0xFB400000)
+#define	SDMRA1B		(SBSC2_BASE + 0x100000)
+#define	SDMRA2B		(SBSC2_BASE + 0x1C0000)
+#define	SDMRA3B		(SBSC2_BASE + 0x104000)
+
+/* CPG */
+#define CPG_BASE   (0xE6150000)
+#define	CPG_SRCR_BASE	(CPG_BASE + 0x80A0)
+#define WUPCR	(CPG_BASE + 0x1010)
+#define SRESCR	(CPG_BASE + 0x1018)
+#define PCLKCR	(CPG_BASE + 0x1020)
+
+/* SYSC */
+#define SYSC_BASE   (0xE6180000)
+#define RESCNT2	(SYSC_BASE + 0x8020)
+
+/* BSC */
+#define BSC_BASE (0xFEC10000)
+
+/* SCIF */
+#define SCIF0_BASE	(0xE6C40000)
+#define SCIF1_BASE	(0xE6C50000)
+#define SCIF2_BASE	(0xE6C60000)
+#define SCIF3_BASE	(0xE6C70000)
+#define SCIF4_BASE	(0xE6C80000)
+#define SCIF5_BASE	(0xE6CB0000)
+#define SCIF6_BASE	(0xE6CC0000)
+#define SCIF7_BASE	(0xE6CD0000)
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct sh73a0_rwdt {
+	u16 rwtcnt0;	/* 0x00 */
+	u16 dummy0;	/* 0x02 */
+	u16 rwtcsra0;	/* 0x04 */
+	u16 dummy1;	/* 0x06 */
+	u16 rwtcsrb0;	/* 0x08 */
+};
+
+/* HPB Semaphore Control Registers */
+struct sh73a0_hpb {
+	u32 hpbctrl0;
+	u32 hpbctrl1;
+	u32 hpbctrl2;
+	u32 cccr;
+	u32 dummy0; /* 0x20 */
+	u32 hpbctrl4;
+	u32 hpbctrl5;
+	u32 dummy1; /* 0x2C */
+	u32 hpbctrl6;
+};
+
+/* Bus Semaphore Control Registers */
+struct sh73a0_hpb_bscr {
+	u32 mpsrc; /* 0x00 */
+	u32 mpacctl; /* 0x04 */
+	u32 dummy0[6];
+	u32 smgpiosrc; /* 0x20 */
+	u32 smgpioerr;
+	u32 smgpiotime;
+	u32 smgpiocnt;
+	u32 dummy1[4]; /* 0x30 .. 0x3C */
+	u32 smcmt2src;
+	u32 smcmt2err;
+	u32 smcmt2time;
+	u32 smcmt2cnt;
+	u32 smcpgsrc;
+	u32 smcpgerr;
+	u32 smcpgtime;
+	u32 smcpgcnt;
+	u32 dummy2[4]; /* 0x60 - 0x6C */
+	u32 smsyscsrc;
+	u32 smsyscerr;
+	u32 smsysctime;
+	u32 smsysccnt;
+};
+
+/* SBSC */
+struct sh73a0_sbsc {
+	u32 dummy0[2]; /* 0x00, 0x04 */
+	u32 sdcr0;
+	u32 sdcr1;
+	u32 sdpcr;
+	u32 dummy1; /* 0x14 */
+	u32 sdcr0s;
+	u32 sdcr1s;
+	u32 rtcsr;
+	u32 dummy2; /* 0x24 */
+	u32 rtcor;
+	u32 rtcorh;
+	u32 rtcors;
+	u32 rtcorsh;
+	u32 dummy3[2]; /* 0x38, 0x3C */
+	u32 sdwcrc0;
+	u32 sdwcrc1;
+	u32 sdwcr00;
+	u32 sdwcr01;
+	u32 sdwcr10;
+	u32 sdwcr11;
+	u32 sdpdcr0;
+	u32 dummy4; /* 0x5C */
+	u32 sdwcr2;
+	u32 sdwcrc2;
+	u32 zqccr;
+	u32 dummy5[6]; /* 0x6C .. 0x80 */
+	u32 sdmracr0;
+	u32 dummy6; /* 0x88 */
+	u32 sdmrtmpcr;
+	u32 dummy7; /* 0x90 */
+	u32 sdmrtmpmsk;
+	u32 dummy8; /* 0x98 */
+	u32 sdgencnt;
+	u32 dphycnt0;
+	u32 dphycnt1;
+	u32 dphycnt2;
+	u32 dummy9[2]; /* 0xAC .. 0xB0 */
+	u32 sddrvcr0;
+	u32 dummy10[14]; /* 0xB8 .. 0xEC */
+	u32 dptdivcr0;
+	u32 dptdivcr1;
+	u32 dptdivcr2;
+	u32 dummy11; /* 0xFC */
+	u32 sdptcr0;
+	u32 sdptcr1;
+	u32 sdptcr2;
+	u32 sdptcr3; /* 0x10C */
+	u32 dummy12[145]; /* 0x110 .. 0x350 */
+	u32 dllcnt0; /* 0x354 */
+	u32 sbscmon0;
+};
+
+/* CPG */
+struct sh73a0_sbsc_cpg {
+	u32 frqcra; /* 0x00 */
+	u32 frqcrb;
+	u32 vclkcr1;
+	u32 vclkcr2;
+	u32 zbckcr;
+	u32 flckcr;
+	u32 fsiackcr;
+	u32 vclkcr3;
+	u32 rtstbcr;
+	u32 systbcr;
+	u32 pll1cr;
+	u32 pll2cr;
+	u32 mstpsr0;
+	u32 dummy0; /* 0x34 */
+	u32 mstpsr1;
+	u32 mstpsr5;
+	u32 mstpsr2;
+	u32 dummy1; /* 0x44 */
+	u32 mstpsr3;
+	u32 mstpsr4;
+	u32 dummy2; /* 0x50 */
+	u32 astat;
+	u32 dvfscr0;
+	u32 dvfscr1;
+	u32 dsitckcr;
+	u32 dsi0pckcr;
+	u32 dsi1pckcr;
+	u32 dsi0phycr;
+	u32 dsi1phycr;
+	u32 sd0ckcr;
+	u32 sd1ckcr;
+	u32 sd2ckcr;
+	u32 subckcr;
+	u32 spuackcr;
+	u32 msuckcr;
+	u32 hsickcr;
+	u32 fsibckcr;
+	u32 spuvckcr;
+	u32 mfck1cr;
+	u32 mfck2cr;
+	u32 dummy3[8]; /* 0xA0 .. 0xBC */
+	u32 ckscr;
+	u32 dummy4; /* 0xC4 */
+	u32 pll1stpcr;
+	u32 mpmode;
+	u32 pllecr;
+	u32 dummy5; /* 0xD4 */
+	u32 pll0cr;
+	u32 pll3cr;
+	u32 dummy6; /* 0xE0 */
+	u32 frqcrd;
+	u32 dummyi7; /* 0xE8 */
+	u32 vrefcr;
+	u32 pll0stpcr;
+	u32 dummy8; /* 0xF4 */
+	u32 pll2stpcr;
+	u32 pll3stpcr;
+	u32 dummy9[4]; /* 0x100 .. 0x10c */
+	u32 rmstpcr0;
+	u32 rmstpcr1;
+	u32 rmstpcr2;
+	u32 rmstpcr3;
+	u32 rmstpcr4;
+	u32 rmstpcr5;
+	u32 dummy10[2]; /* 0x128 .. 0x12c */
+	u32 smstpcr0;
+	u32 smstpcr1;
+	u32 smstpcr2;
+	u32 smstpcr3;
+	u32 smstpcr4;
+	u32 smstpcr5;
+	u32 dummy11[2]; /* 0x148 .. 0x14c */
+	u32 cpgxxcs4;
+	u32 dummy12[7]; /* 0x154 .. 0x16c */
+	u32 dvfscr2;
+	u32 dvfscr3;
+	u32 dvfscr4;
+	u32 dvfscr5; /* 0x17C */
+};
+
+/* CPG SRCR part OK */
+struct sh73a0_sbsc_cpg_srcr {
+	u32 srcr0;
+	u32 dummy0; /* 0xA4 */
+	u32 srcr1;
+	u32 dummy1; /* 0xAC */
+	u32 srcr2;
+	u32 dummy2; /* 0xB4 */
+	u32 srcr3;
+	u32 srcr4;
+	u32 dummy3; /* 0xC0 */
+	u32 srcr5;
+};
+
+/* BSC */
+struct sh73a0_bsc {
+	u32 cmncr;
+	u32 cs0bcr;
+	u32 cs2bcr;
+	u32 dummy0; /* 0x0C */
+	u32 cs4bcr;
+	u32 cs5abcr;
+	u32 cs5bbcr;
+	u32 cs6abcr;
+	u32 cs6bbcr;
+	u32 cs0wcr;
+	u32 cs2wcr;
+	u32 dummy1; /* 0x2C */
+	u32 cs4wcr;
+	u32 cs5awcr;
+	u32 cs5bwcr;
+	u32 cs6awcr;
+	u32 cs6bwcr;
+	u32 rbwtcnt;
+	u32 busycr;
+	u32 dummy2; /* 0x5c */
+	u32 cs7abcr;
+	u32 cs7awcr;
+	u32 dummy3[2]; /* 0x68, 0x6C */
+	u32 bromtimcr;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sys_proto.h
new file mode 100644
index 000000000..326f6b148
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-rmobile/sys_proto.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+struct rmobile_sysinfo {
+	char *board_string;
+};
+extern const struct rmobile_sysinfo sysinfo;
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/gpio.h
new file mode 100644
index 000000000..a749b6491
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/gpio.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2012.
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+enum s3c2440_gpio {
+	GPA0,
+	GPA1,
+	GPA2,
+	GPA3,
+	GPA4,
+	GPA5,
+	GPA6,
+	GPA7,
+	GPA8,
+	GPA9,
+	GPA10,
+	GPA11,
+	GPA12,
+	GPA13,
+	GPA14,
+	GPA15,
+	GPA16,
+	GPA17,
+	GPA18,
+	GPA19,
+	GPA20,
+	GPA21,
+	GPA22,
+	GPA23,
+	GPA24,
+
+	GPB0 = 32,
+	GPB1,
+	GPB2,
+	GPB3,
+	GPB4,
+	GPB5,
+	GPB6,
+	GPB7,
+	GPB8,
+	GPB9,
+	GPB10,
+
+	GPC0 = 64,
+	GPC1,
+	GPC2,
+	GPC3,
+	GPC4,
+	GPC5,
+	GPC6,
+	GPC7,
+	GPC8,
+	GPC9,
+	GPC10,
+	GPC11,
+	GPC12,
+	GPC13,
+	GPC14,
+	GPC15,
+
+	GPD0 = 96,
+	GPD1,
+	GPD2,
+	GPD3,
+	GPD4,
+	GPD5,
+	GPD6,
+	GPD7,
+	GPD8,
+	GPD9,
+	GPD10,
+	GPD11,
+	GPD12,
+	GPD13,
+	GPD14,
+	GPD15,
+
+	GPE0 = 128,
+	GPE1,
+	GPE2,
+	GPE3,
+	GPE4,
+	GPE5,
+	GPE6,
+	GPE7,
+	GPE8,
+	GPE9,
+	GPE10,
+	GPE11,
+	GPE12,
+	GPE13,
+	GPE14,
+	GPE15,
+
+	GPF0 = 160,
+	GPF1,
+	GPF2,
+	GPF3,
+	GPF4,
+	GPF5,
+	GPF6,
+	GPF7,
+
+	GPG0 = 192,
+	GPG1,
+	GPG2,
+	GPG3,
+	GPG4,
+	GPG5,
+	GPG6,
+	GPG7,
+	GPG8,
+	GPG9,
+	GPG10,
+	GPG11,
+	GPG12,
+	GPG13,
+	GPG14,
+	GPG15,
+
+	GPH0 = 224,
+	GPH1,
+	GPH2,
+	GPH3,
+	GPH4,
+	GPH5,
+	GPH6,
+	GPH7,
+	GPH8,
+	GPH9,
+	GPH10,
+
+	GPJ0 = 256,
+	GPJ1,
+	GPJ2,
+	GPJ3,
+	GPJ4,
+	GPJ5,
+	GPJ6,
+	GPJ7,
+	GPJ8,
+	GPJ9,
+	GPJ10,
+	GPJ11,
+	GPJ12,
+};
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/iomux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/iomux.h
new file mode 100644
index 000000000..981164434
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/iomux.h
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2012
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _S3C24X0_IOMUX_H_
+#define _S3C24X0_IOMUX_H_
+
+enum s3c2440_iomux_func {
+	/* PORT A */
+	IOMUXA_ADDR0	= 1,
+	IOMUXA_ADDR16	= (1 << 1),
+	IOMUXA_ADDR17	= (1 << 2),
+	IOMUXA_ADDR18	= (1 << 3),
+	IOMUXA_ADDR19	= (1 << 4),
+	IOMUXA_ADDR20	= (1 << 5),
+	IOMUXA_ADDR21	= (1 << 6),
+	IOMUXA_ADDR22	= (1 << 7),
+	IOMUXA_ADDR23	= (1 << 8),
+	IOMUXA_ADDR24	= (1 << 9),
+	IOMUXA_ADDR25	= (1 << 10),
+	IOMUXA_ADDR26	= (1 << 11),
+	IOMUXA_nGCS1	= (1 << 12),
+	IOMUXA_nGCS2	= (1 << 13),
+	IOMUXA_nGCS3	= (1 << 14),
+	IOMUXA_nGCS4	= (1 << 15),
+	IOMUXA_nGCS5	= (1 << 16),
+	IOMUXA_CLE	= (1 << 17),
+	IOMUXA_ALE	= (1 << 18),
+	IOMUXA_nFWE	= (1 << 19),
+	IOMUXA_nFRE	= (1 << 20),
+	IOMUXA_nRSTOUT	= (1 << 21),
+	IOMUXA_nFCE		= (1 << 22),
+
+	/* PORT B */
+	IOMUXB_nXDREQ0	= (2 << 20),
+	IOMUXB_nXDACK0	= (2 << 18),
+	IOMUXB_nXDREQ1	= (2 << 16),
+	IOMUXB_nXDACK1	= (2 << 14),
+	IOMUXB_nXBREQ	= (2 << 12),
+	IOMUXB_nXBACK	= (2 << 10),
+	IOMUXB_TCLK0	= (2 << 8),
+	IOMUXB_TOUT3	= (2 << 6),
+	IOMUXB_TOUT2	= (2 << 4),
+	IOMUXB_TOUT1	= (2 << 2),
+	IOMUXB_TOUT0	= 2,
+
+	/* PORT C */
+	IOMUXC_VS7	= (2 << 30),
+	IOMUXC_VS6	= (2 << 28),
+	IOMUXC_VS5	= (2 << 26),
+	IOMUXC_VS4	= (2 << 24),
+	IOMUXC_VS3	= (2 << 22),
+	IOMUXC_VS2	= (2 << 20),
+	IOMUXC_VS1	= (2 << 18),
+	IOMUXC_VS0	= (2 << 16),
+	IOMUXC_LCD_LPCREVB	= (2 << 14),
+	IOMUXC_LCD_LPCREV	= (2 << 12),
+	IOMUXC_LCD_LPCOE	= (2 << 10),
+	IOMUXC_VM		= (2 << 8),
+	IOMUXC_VFRAME	= (2 << 6),
+	IOMUXC_VLINE	= (2 << 4),
+	IOMUXC_VCLK		= (2 << 2),
+	IOMUXC_LEND		= 2,
+	IOMUXC_I2SSDI	= (3 << 8),
+
+	/* PORT D */
+	IOMUXD_VS23	= (2 << 30),
+	IOMUXD_VS22	= (2 << 28),
+	IOMUXD_VS21	= (2 << 26),
+	IOMUXD_VS20	= (2 << 24),
+	IOMUXD_VS19	= (2 << 22),
+	IOMUXD_VS18	= (2 << 20),
+	IOMUXD_VS17	= (2 << 18),
+	IOMUXD_VS16	= (2 << 16),
+	IOMUXD_VS15	= (2 << 14),
+	IOMUXD_VS14	= (2 << 12),
+	IOMUXD_VS13	= (2 << 10),
+	IOMUXD_VS12	= (2 << 8),
+	IOMUXD_VS11	= (2 << 6),
+	IOMUXD_VS10	= (2 << 4),
+	IOMUXD_VS9	= (2 << 2),
+	IOMUXD_VS8	= 2,
+	IOMUXD_nSS0	= (3 << 30),
+	IOMUXD_nSS1	= (3 << 28),
+	IOMUXD_SPICLK1	= (3 << 20),
+	IOMUXD_SPIMOSI1	= (3 << 18),
+	IOMUXD_SPIMISO1	= (3 << 16),
+
+	/* PORT E */
+	IOMUXE_IICSDA	= (2 << 30),
+	IOMUXE_IICSCL	= (2 << 28),
+	IOMUXE_SPICLK0	= (2 << 26),
+	IOMUXE_SPIMOSI0	= (2 << 24),
+	IOMUXE_SPIMISO0	= (2 << 22),
+	IOMUXE_SDDAT3	= (2 << 20),
+	IOMUXE_SDDAT2	= (2 << 18),
+	IOMUXE_SDDAT1	= (2 << 16),
+	IOMUXE_SDDAT0	= (2 << 14),
+	IOMUXE_SDCMD	= (2 << 12),
+	IOMUXE_SDCLK	= (2 << 10),
+	IOMUXE_I2SDO	= (2 << 8),
+	IOMUXE_I2SDI	= (2 << 6),
+	IOMUXE_CDCLK	= (2 << 4),
+	IOMUXE_I2SSCLK	= (2 << 2),
+	IOMUXE_I2SLRCK	= 2,
+	IOMUXE_AC_SDATA_OUT	= (3 << 8),
+	IOMUXE_AC_SDATA_IN	= (3 << 6),
+	IOMUXE_AC_nRESET	= (3 << 4),
+	IOMUXE_AC_BIT_CLK	= (3 << 2),
+	IOMUXE_AC_SYNC		= 3,
+
+	/* PORT F */
+	IOMUXF_EINT7	= (2 << 14),
+	IOMUXF_EINT6	= (2 << 12),
+	IOMUXF_EINT5	= (2 << 10),
+	IOMUXF_EINT4	= (2 << 8),
+	IOMUXF_EINT3	= (2 << 6),
+	IOMUXF_EINT2	= (2 << 4),
+	IOMUXF_EINT1	= (2 << 2),
+	IOMUXF_EINT0	= 2,
+
+	/* PORT G */
+	IOMUXG_EINT23	= (2 << 30),
+	IOMUXG_EINT22	= (2 << 28),
+	IOMUXG_EINT21	= (2 << 26),
+	IOMUXG_EINT20	= (2 << 24),
+	IOMUXG_EINT19	= (2 << 22),
+	IOMUXG_EINT18	= (2 << 20),
+	IOMUXG_EINT17	= (2 << 18),
+	IOMUXG_EINT16	= (2 << 16),
+	IOMUXG_EINT15	= (2 << 14),
+	IOMUXG_EINT14	= (2 << 12),
+	IOMUXG_EINT13	= (2 << 10),
+	IOMUXG_EINT12	= (2 << 8),
+	IOMUXG_EINT11	= (2 << 6),
+	IOMUXG_EINT10	= (2 << 4),
+	IOMUXG_EINT9	= (2 << 2),
+	IOMUXG_EINT8	= 2,
+	IOMUXG_TCLK1	= (3 << 22),
+	IOMUXG_nCTS1	= (3 << 20),
+	IOMUXG_nRTS1	= (3 << 18),
+	IOMUXG_SPICLK1	= (3 << 14),
+	IOMUXG_SPIMOSI1	= (3 << 12),
+	IOMUXG_SPIMISO1	= (3 << 10),
+	IOMUXG_LCD_PWRDN	= (3 << 8),
+	IOMUXG_nSS1			= (3 << 6),
+	IOMUXG_nSS0			= (3 << 4),
+
+	/* PORT H */
+	IOMUXH_CLKOUT1	= (2 << 20),
+	IOMUXH_CLKOUT0	= (2 << 18),
+	IOMUXH_UEXTCLK	= (2 << 16),
+	IOMUXH_RXD2		= (2 << 14),
+	IOMUXH_TXD2		= (2 << 12),
+	IOMUXH_RXD1		= (2 << 10),
+	IOMUXH_TXD1		= (2 << 8),
+	IOMUXH_RXD0		= (2 << 6),
+	IOMUXH_TXD0		= (2 << 4),
+	IOMUXH_nRTS0	= (2 << 2),
+	IOMUXH_nCTS0	= 2,
+	IOMUXH_nCTS1	= (3 << 14),
+	IOMUXH_nRTS1	= (3 << 12),
+
+	/* PORT J */
+	IOMUXJ_CAMRESET		= (2 << 24),
+	IOMUXJ_CAMCLKOUT	= (2 << 22),
+	IOMUXJ_CAMHREF		= (2 << 20),
+	IOMUXJ_CAMVSYNC		= (2 << 18),
+	IOMUXJ_CAMPCLK		= (2 << 16),
+	IOMUXJ_CAMDATA7		= (2 << 14),
+	IOMUXJ_CAMDATA6		= (2 << 12),
+	IOMUXJ_CAMDATA5		= (2 << 10),
+	IOMUXJ_CAMDATA4		= (2 << 8),
+	IOMUXJ_CAMDATA3		= (2 << 6),
+	IOMUXJ_CAMDATA2		= (2 << 4),
+	IOMUXJ_CAMDATA1		= (2 << 2),
+	IOMUXJ_CAMDATA0		= 2
+};
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/memory.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/memory.h
new file mode 100644
index 000000000..d6a787b66
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/memory.h
@@ -0,0 +1,159 @@
+/*
+ * linux/include/asm-arm/arch-s3c2400/memory.h by garyj@denx.de
+ * based on
+ * linux/include/asm-arm/arch-sa1100/memory.h
+ *
+ * Copyright (c) 1999 Nicolas Pitre <nico@visuaide.com>
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE       (0xc0000000UL)
+#define TASK_SIZE_26	(0x04000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET     (0xc0000000UL)
+
+/*
+ * Physical DRAM offset is 0x0c000000 on the S3C2400
+ */
+#define PHYS_OFFSET	(0x0c000000UL)
+
+/* Modified for S3C2400, by chc, 20010509 */
+#define RAM_IN_BANK_0  32*1024*1024
+#define RAM_IN_BANK_1  0
+#define RAM_IN_BANK_2  0
+#define RAM_IN_BANK_3  0
+
+#define MEM_SIZE  (RAM_IN_BANK_0+RAM_IN_BANK_1+RAM_IN_BANK_2+RAM_IN_BANK_3)
+
+
+/* translation macros */
+#define __virt_to_phys__is_a_macro
+#define __phys_to_virt__is_a_macro
+
+#if (RAM_IN_BANK_1 + RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0)
+
+#define __virt_to_phys(x) ( (x) - PAGE_OFFSET + 0x0c000000 )
+#define __phys_to_virt(x) ( (x) - 0x0c000000 + PAGE_OFFSET )
+
+#elif (RAM_IN_BANK_0 == RAM_IN_BANK_1) && \
+      (RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0)
+
+/* Two identical banks */
+#define __virt_to_phys(x) \
+	  ( ((x) < PAGE_OFFSET+RAM_IN_BANK_0) ? \
+	    ((x) - PAGE_OFFSET + _DRAMBnk0) : \
+	    ((x) - PAGE_OFFSET - RAM_IN_BANK_0 + _DRAMBnk1) )
+#define __phys_to_virt(x) \
+	  ( ((x)&0x07ffffff) + \
+	    (((x)&0x08000000) ? PAGE_OFFSET+RAM_IN_BANK_0 : PAGE_OFFSET) )
+#else
+
+/* It's more efficient for all other cases to use the function call */
+#undef __virt_to_phys__is_a_macro
+#undef __phys_to_virt__is_a_macro
+extern unsigned long __virt_to_phys(unsigned long vpage);
+extern unsigned long __phys_to_virt(unsigned long ppage);
+
+#endif
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ *
+ * On the SA1100, bus addresses are equivalent to physical addresses.
+ */
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#ifdef CONFIG_DISCONTIGMEM
+#error "CONFIG_DISCONTIGMEM will not work on S3C2400"
+/*
+ * Because of the wide memory address space between physical RAM banks on the
+ * SA1100, it's much more convenient to use Linux's NUMA support to implement
+ * our memory map representation.  Assuming all memory nodes have equal access
+ * characteristics, we then have generic discontiguous memory support.
+ *
+ * Of course, all this isn't mandatory for SA1100 implementations with only
+ * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
+ *
+ * The nodes are matched with the physical memory bank addresses which are
+ * incidentally the same as virtual addresses.
+ *
+ *	node 0:  0xc0000000 - 0xc7ffffff
+ *	node 1:  0xc8000000 - 0xcfffffff
+ *	node 2:  0xd0000000 - 0xd7ffffff
+ *	node 3:  0xd8000000 - 0xdfffffff
+ */
+
+#define NR_NODES	4
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) \
+		(((unsigned long)(addr) - 0xc0000000) >> 27)
+
+/*
+ * Given a physical address, convert it to a node id.
+ */
+#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr))
+
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr) \
+			NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+#define LOCAL_MAP_NR(kvaddr) \
+	(((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT)
+
+/*
+ * Given a kaddr, virt_to_page returns a pointer to the corresponding
+ * mem_map entry.
+ */
+#define virt_to_page(kaddr) \
+	(ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
+
+/*
+ * VALID_PAGE returns a non-zero value if given page pointer is valid.
+ * This assumes all node's mem_maps are stored within the node they refer to.
+ */
+#define VALID_PAGE(page) \
+({ unsigned int node = KVADDR_TO_NID(page); \
+   ( (node < NR_NODES) && \
+     ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \
+})
+
+#else
+
+#define PHYS_TO_NID(addr)	(0)
+
+#endif
+#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2400.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2400.h
new file mode 100644
index 000000000..2389118e7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2400.h
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************
+ * NAME	    : s3c2400.h
+ * Version  : 31.3.2003
+ *
+ * Based on S3C2400X User's manual Rev 1.1
+ ************************************************/
+
+#ifndef __S3C2400_H__
+#define __S3C2400_H__
+
+#define S3C24X0_UART_CHANNELS	2
+#define S3C24X0_SPI_CHANNELS	1
+#define PALETTE			(0x14A00400)	/* SJS */
+
+enum s3c24x0_uarts_nr {
+	S3C24X0_UART0,
+	S3C24X0_UART1,
+};
+
+/*S3C2400 device base addresses */
+#define S3C24X0_MEMCTL_BASE		0x14000000
+#define S3C24X0_USB_HOST_BASE		0x14200000
+#define S3C24X0_INTERRUPT_BASE		0x14400000
+#define S3C24X0_DMA_BASE		0x14600000
+#define S3C24X0_CLOCK_POWER_BASE	0x14800000
+#define S3C24X0_LCD_BASE		0x14A00000
+#define S3C24X0_UART_BASE		0x15000000
+#define S3C24X0_TIMER_BASE		0x15100000
+#define S3C24X0_USB_DEVICE_BASE		0x15200140
+#define S3C24X0_WATCHDOG_BASE		0x15300000
+#define S3C24X0_I2C_BASE		0x15400000
+#define S3C24X0_I2S_BASE		0x15508000
+#define S3C24X0_GPIO_BASE		0x15600000
+#define S3C24X0_RTC_BASE		0x15700000
+#define S3C24X0_ADC_BASE		0x15800000
+#define S3C24X0_SPI_BASE		0x15900000
+#define S3C2400_MMC_BASE		0x15A00000
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+	return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+	return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+	return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+	return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
+{
+	return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+	return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+
+static inline struct s3c24x0_uart
+	*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+	return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+	return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+	return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+	return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+	return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+	return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+	return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+	return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+
+static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
+{
+	return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
+}
+
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+
+static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
+{
+	return (struct s3c2400_mmc *)S3C2400_MMC_BASE;
+}
+
+#endif /*__S3C2400_H__*/
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
new file mode 100644
index 000000000..01fe0f27e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************
+ * NAME	    : s3c2410.h
+ * Version  : 31.3.2003
+ *
+ * Based on S3C2410X User's manual Rev 1.1
+ ************************************************/
+
+#ifndef __S3C2410_H__
+#define __S3C2410_H__
+
+#define S3C24X0_UART_CHANNELS	3
+#define S3C24X0_SPI_CHANNELS	2
+
+/* S3C2410 only supports 512 Byte HW ECC */
+#define S3C2410_ECCSIZE		512
+#define S3C2410_ECCBYTES	3
+
+enum s3c24x0_uarts_nr {
+	S3C24X0_UART0,
+	S3C24X0_UART1,
+	S3C24X0_UART2
+};
+
+/* S3C2410 device base addresses */
+#define S3C24X0_MEMCTL_BASE		0x48000000
+#define S3C24X0_USB_HOST_BASE		0x49000000
+#define S3C24X0_INTERRUPT_BASE		0x4A000000
+#define S3C24X0_DMA_BASE		0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE	0x4C000000
+#define S3C24X0_LCD_BASE		0x4D000000
+#define S3C2410_NAND_BASE		0x4E000000
+#define S3C24X0_UART_BASE		0x50000000
+#define S3C24X0_TIMER_BASE		0x51000000
+#define S3C24X0_USB_DEVICE_BASE		0x52000140
+#define S3C24X0_WATCHDOG_BASE		0x53000000
+#define S3C24X0_I2C_BASE		0x54000000
+#define S3C24X0_I2S_BASE		0x55000000
+#define S3C24X0_GPIO_BASE		0x56000000
+#define S3C24X0_RTC_BASE		0x57000000
+#define S3C2410_ADC_BASE		0x58000000
+#define S3C24X0_SPI_BASE		0x59000000
+#define S3C2410_SDI_BASE		0x5A000000
+
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+	return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+	return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+	return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+	return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
+{
+	return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+	return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+
+static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
+{
+	return (struct s3c2410_nand *)S3C2410_NAND_BASE;
+}
+
+static inline struct s3c24x0_uart
+	*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+	return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+	return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+	return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+	return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+	return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+	return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+	return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+	return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+
+static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
+{
+	return (struct s3c2410_adc *)S3C2410_ADC_BASE;
+}
+
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+
+static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
+{
+	return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
+}
+
+#endif /*__S3C2410_H__*/
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
new file mode 100644
index 000000000..15a7cb43d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2003
+ * David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************
+ * NAME	    : s3c2440.h
+ * Version  : 31.3.2003
+ *
+ * Based on S3C2440 User's manual Rev x.x
+ ************************************************/
+
+#ifndef __S3C2440_H__
+#define __S3C2440_H__
+
+#define S3C24X0_UART_CHANNELS	3
+#define S3C24X0_SPI_CHANNELS	2
+
+/* S3C2440 only supports 512 Byte HW ECC */
+#define S3C2440_ECCSIZE		512
+#define S3C2440_ECCBYTES	3
+
+enum s3c24x0_uarts_nr {
+	S3C24X0_UART0,
+	S3C24X0_UART1,
+	S3C24X0_UART2
+};
+
+/* S3C2440 device base addresses */
+#define S3C24X0_MEMCTL_BASE		0x48000000
+#define S3C24X0_USB_HOST_BASE		0x49000000
+#define S3C24X0_INTERRUPT_BASE		0x4A000000
+#define S3C24X0_DMA_BASE		0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE	0x4C000000
+#define S3C24X0_LCD_BASE		0x4D000000
+#define S3C2440_NAND_BASE		0x4E000000
+#define S3C24X0_UART_BASE		0x50000000
+#define S3C24X0_TIMER_BASE		0x51000000
+#define S3C24X0_USB_DEVICE_BASE		0x52000140
+#define S3C24X0_WATCHDOG_BASE		0x53000000
+#define S3C24X0_I2C_BASE		0x54000000
+#define S3C24X0_I2S_BASE		0x55000000
+#define S3C24X0_GPIO_BASE		0x56000000
+#define S3C24X0_RTC_BASE		0x57000000
+#define S3C2440_ADC_BASE		0x58000000
+#define S3C24X0_SPI_BASE		0x59000000
+#define S3C2440_SDI_BASE		0x5A000000
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+	return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+	return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+	return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+	return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
+{
+	return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+	return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+
+static inline struct s3c2440_nand *s3c2440_get_base_nand(void)
+{
+	return (struct s3c2440_nand *)S3C2440_NAND_BASE;
+}
+
+static inline struct s3c24x0_uart
+	*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+	return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+	return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+	return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+	return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+	return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+	return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+	return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+	return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+
+static inline struct s3c2440_adc *s3c2440_get_base_adc(void)
+{
+	return (struct s3c2440_adc *)S3C2440_ADC_BASE;
+}
+
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+	return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+
+static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void)
+{
+	return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
+}
+
+#endif /*__S3C2440_H__*/
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
new file mode 100644
index 000000000..86d720c06
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -0,0 +1,704 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************
+ * NAME	    : s3c24x0.h
+ * Version  : 31.3.2003
+ *
+ * common stuff for SAMSUNG S3C24X0 SoC
+ ************************************************/
+
+#ifndef __S3C24X0_H__
+#define __S3C24X0_H__
+
+/* Memory controller (see manual chapter 5) */
+struct s3c24x0_memctl {
+	u32	bwscon;
+	u32	bankcon[8];
+	u32	refresh;
+	u32	banksize;
+	u32	mrsrb6;
+	u32	mrsrb7;
+};
+
+
+/* USB HOST (see manual chapter 12) */
+struct s3c24x0_usb_host {
+	u32	HcRevision;
+	u32	HcControl;
+	u32	HcCommonStatus;
+	u32	HcInterruptStatus;
+	u32	HcInterruptEnable;
+	u32	HcInterruptDisable;
+	u32	HcHCCA;
+	u32	HcPeriodCuttendED;
+	u32	HcControlHeadED;
+	u32	HcControlCurrentED;
+	u32	HcBulkHeadED;
+	u32	HcBuldCurrentED;
+	u32	HcDoneHead;
+	u32	HcRmInterval;
+	u32	HcFmRemaining;
+	u32	HcFmNumber;
+	u32	HcPeriodicStart;
+	u32	HcLSThreshold;
+	u32	HcRhDescriptorA;
+	u32	HcRhDescriptorB;
+	u32	HcRhStatus;
+	u32	HcRhPortStatus1;
+	u32	HcRhPortStatus2;
+};
+
+
+/* INTERRUPT (see manual chapter 14) */
+struct s3c24x0_interrupt {
+	u32	srcpnd;
+	u32	intmod;
+	u32	intmsk;
+	u32	priority;
+	u32	intpnd;
+	u32	intoffset;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+	u32	subsrcpnd;
+	u32	intsubmsk;
+#endif
+};
+
+
+/* DMAS (see manual chapter 8) */
+struct s3c24x0_dma {
+	u32	disrc;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+	u32	disrcc;
+#endif
+	u32	didst;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+	u32	didstc;
+#endif
+	u32	dcon;
+	u32	dstat;
+	u32	dcsrc;
+	u32	dcdst;
+	u32	dmasktrig;
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \
+		|| defined(CONFIG_S3C2440)
+	u32	res[1];
+#endif
+};
+
+struct s3c24x0_dmas {
+	struct s3c24x0_dma	dma[4];
+};
+
+
+/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
+/*                          (see S3C2410 manual chapter 7) */
+struct s3c24x0_clock_power {
+	u32	locktime;
+	u32	mpllcon;
+	u32	upllcon;
+	u32	clkcon;
+	u32	clkslow;
+	u32	clkdivn;
+#if defined(CONFIG_S3C2440)
+	u32	camdivn;
+#endif
+};
+
+
+/* LCD CONTROLLER (see manual chapter 15) */
+struct s3c24x0_lcd {
+	u32	lcdcon1;
+	u32	lcdcon2;
+	u32	lcdcon3;
+	u32	lcdcon4;
+	u32	lcdcon5;
+	u32	lcdsaddr1;
+	u32	lcdsaddr2;
+	u32	lcdsaddr3;
+	u32	redlut;
+	u32	greenlut;
+	u32	bluelut;
+	u32	res[8];
+	u32	dithmode;
+	u32	tpal;
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+	u32	lcdintpnd;
+	u32	lcdsrcpnd;
+	u32	lcdintmsk;
+	u32	lpcsel;
+#endif
+};
+
+
+#ifdef CONFIG_S3C2410
+/* NAND FLASH (see S3C2410 manual chapter 6) */
+struct s3c2410_nand {
+	u32	nfconf;
+	u32	nfcmd;
+	u32	nfaddr;
+	u32	nfdata;
+	u32	nfstat;
+	u32	nfecc;
+};
+#endif
+#ifdef CONFIG_S3C2440
+/* NAND FLASH (see S3C2440 manual chapter 6) */
+struct s3c2440_nand {
+	u32	nfconf;
+	u32	nfcont;
+	u32	nfcmd;
+	u32	nfaddr;
+	u32	nfdata;
+	u32	nfeccd0;
+	u32	nfeccd1;
+	u32	nfeccd;
+	u32	nfstat;
+	u32	nfstat0;
+	u32	nfstat1;
+};
+#endif
+
+
+/* UART (see manual chapter 11) */
+struct s3c24x0_uart {
+	u32	ulcon;
+	u32	ucon;
+	u32	ufcon;
+	u32	umcon;
+	u32	utrstat;
+	u32	uerstat;
+	u32	ufstat;
+	u32	umstat;
+#ifdef __BIG_ENDIAN
+	u8	res1[3];
+	u8	utxh;
+	u8	res2[3];
+	u8	urxh;
+#else /* Little Endian */
+	u8	utxh;
+	u8	res1[3];
+	u8	urxh;
+	u8	res2[3];
+#endif
+	u32	ubrdiv;
+};
+
+
+/* PWM TIMER (see manual chapter 10) */
+struct s3c24x0_timer {
+	u32	tcntb;
+	u32	tcmpb;
+	u32	tcnto;
+};
+
+struct s3c24x0_timers {
+	u32	tcfg0;
+	u32	tcfg1;
+	u32	tcon;
+	struct s3c24x0_timer	ch[4];
+	u32	tcntb4;
+	u32	tcnto4;
+};
+
+
+/* USB DEVICE (see manual chapter 13) */
+struct s3c24x0_usb_dev_fifos {
+#ifdef __BIG_ENDIAN
+	u8	res[3];
+	u8	ep_fifo_reg;
+#else /*  little endian */
+	u8	ep_fifo_reg;
+	u8	res[3];
+#endif
+};
+
+struct s3c24x0_usb_dev_dmas {
+#ifdef __BIG_ENDIAN
+	u8	res1[3];
+	u8	ep_dma_con;
+	u8	res2[3];
+	u8	ep_dma_unit;
+	u8	res3[3];
+	u8	ep_dma_fifo;
+	u8	res4[3];
+	u8	ep_dma_ttc_l;
+	u8	res5[3];
+	u8	ep_dma_ttc_m;
+	u8	res6[3];
+	u8	ep_dma_ttc_h;
+#else /*  little endian */
+	u8	ep_dma_con;
+	u8	res1[3];
+	u8	ep_dma_unit;
+	u8	res2[3];
+	u8	ep_dma_fifo;
+	u8	res3[3];
+	u8	ep_dma_ttc_l;
+	u8	res4[3];
+	u8	ep_dma_ttc_m;
+	u8	res5[3];
+	u8	ep_dma_ttc_h;
+	u8	res6[3];
+#endif
+};
+
+struct s3c24x0_usb_device {
+#ifdef __BIG_ENDIAN
+	u8	res1[3];
+	u8	func_addr_reg;
+	u8	res2[3];
+	u8	pwr_reg;
+	u8	res3[3];
+	u8	ep_int_reg;
+	u8	res4[15];
+	u8	usb_int_reg;
+	u8	res5[3];
+	u8	ep_int_en_reg;
+	u8	res6[15];
+	u8	usb_int_en_reg;
+	u8	res7[3];
+	u8	frame_num1_reg;
+	u8	res8[3];
+	u8	frame_num2_reg;
+	u8	res9[3];
+	u8	index_reg;
+	u8	res10[7];
+	u8	maxp_reg;
+	u8	res11[3];
+	u8	ep0_csr_in_csr1_reg;
+	u8	res12[3];
+	u8	in_csr2_reg;
+	u8	res13[7];
+	u8	out_csr1_reg;
+	u8	res14[3];
+	u8	out_csr2_reg;
+	u8	res15[3];
+	u8	out_fifo_cnt1_reg;
+	u8	res16[3];
+	u8	out_fifo_cnt2_reg;
+#else /*  little endian */
+	u8	func_addr_reg;
+	u8	res1[3];
+	u8	pwr_reg;
+	u8	res2[3];
+	u8	ep_int_reg;
+	u8	res3[15];
+	u8	usb_int_reg;
+	u8	res4[3];
+	u8	ep_int_en_reg;
+	u8	res5[15];
+	u8	usb_int_en_reg;
+	u8	res6[3];
+	u8	frame_num1_reg;
+	u8	res7[3];
+	u8	frame_num2_reg;
+	u8	res8[3];
+	u8	index_reg;
+	u8	res9[7];
+	u8	maxp_reg;
+	u8	res10[7];
+	u8	ep0_csr_in_csr1_reg;
+	u8	res11[3];
+	u8	in_csr2_reg;
+	u8	res12[3];
+	u8	out_csr1_reg;
+	u8	res13[7];
+	u8	out_csr2_reg;
+	u8	res14[3];
+	u8	out_fifo_cnt1_reg;
+	u8	res15[3];
+	u8	out_fifo_cnt2_reg;
+	u8	res16[3];
+#endif /*  __BIG_ENDIAN */
+	struct s3c24x0_usb_dev_fifos	fifo[5];
+	struct s3c24x0_usb_dev_dmas	dma[5];
+};
+
+
+/* WATCH DOG TIMER (see manual chapter 18) */
+struct s3c24x0_watchdog {
+	u32	wtcon;
+	u32	wtdat;
+	u32	wtcnt;
+};
+
+/* IIS (see manual chapter 21) */
+struct s3c24x0_i2s {
+#ifdef __BIG_ENDIAN
+	u16	res1;
+	u16	iiscon;
+	u16	res2;
+	u16	iismod;
+	u16	res3;
+	u16	iispsr;
+	u16	res4;
+	u16	iisfcon;
+	u16	res5;
+	u16	iisfifo;
+#else /*  little endian */
+	u16	iiscon;
+	u16	res1;
+	u16	iismod;
+	u16	res2;
+	u16	iispsr;
+	u16	res3;
+	u16	iisfcon;
+	u16	res4;
+	u16	iisfifo;
+	u16	res5;
+#endif
+};
+
+
+/* I/O PORT (see manual chapter 9) */
+struct s3c24x0_gpio {
+#ifdef CONFIG_S3C2400
+	u32	pacon;
+	u32	padat;
+
+	u32	pbcon;
+	u32	pbdat;
+	u32	pbup;
+
+	u32	pccon;
+	u32	pcdat;
+	u32	pcup;
+
+	u32	pdcon;
+	u32	pddat;
+	u32	pdup;
+
+	u32	pecon;
+	u32	pedat;
+	u32	peup;
+
+	u32	pfcon;
+	u32	pfdat;
+	u32	pfup;
+
+	u32	pgcon;
+	u32	pgdat;
+	u32	pgup;
+
+	u32	opencr;
+
+	u32	misccr;
+	u32	extint;
+#endif
+#ifdef CONFIG_S3C2410
+	u32	gpacon;
+	u32	gpadat;
+	u32	res1[2];
+	u32	gpbcon;
+	u32	gpbdat;
+	u32	gpbup;
+	u32	res2;
+	u32	gpccon;
+	u32	gpcdat;
+	u32	gpcup;
+	u32	res3;
+	u32	gpdcon;
+	u32	gpddat;
+	u32	gpdup;
+	u32	res4;
+	u32	gpecon;
+	u32	gpedat;
+	u32	gpeup;
+	u32	res5;
+	u32	gpfcon;
+	u32	gpfdat;
+	u32	gpfup;
+	u32	res6;
+	u32	gpgcon;
+	u32	gpgdat;
+	u32	gpgup;
+	u32	res7;
+	u32	gphcon;
+	u32	gphdat;
+	u32	gphup;
+	u32	res8;
+
+	u32	misccr;
+	u32	dclkcon;
+	u32	extint0;
+	u32	extint1;
+	u32	extint2;
+	u32	eintflt0;
+	u32	eintflt1;
+	u32	eintflt2;
+	u32	eintflt3;
+	u32	eintmask;
+	u32	eintpend;
+	u32	gstatus0;
+	u32	gstatus1;
+	u32	gstatus2;
+	u32	gstatus3;
+	u32	gstatus4;
+#endif
+#if defined(CONFIG_S3C2440)
+	u32	gpacon;
+	u32	gpadat;
+	u32	res1[2];
+	u32	gpbcon;
+	u32	gpbdat;
+	u32	gpbup;
+	u32	res2;
+	u32	gpccon;
+	u32	gpcdat;
+	u32	gpcup;
+	u32	res3;
+	u32	gpdcon;
+	u32	gpddat;
+	u32	gpdup;
+	u32	res4;
+	u32	gpecon;
+	u32	gpedat;
+	u32	gpeup;
+	u32	res5;
+	u32	gpfcon;
+	u32	gpfdat;
+	u32	gpfup;
+	u32	res6;
+	u32	gpgcon;
+	u32	gpgdat;
+	u32	gpgup;
+	u32	res7;
+	u32	gphcon;
+	u32	gphdat;
+	u32	gphup;
+	u32	res8;
+
+	u32	misccr;
+	u32	dclkcon;
+	u32	extint0;
+	u32	extint1;
+	u32	extint2;
+	u32	eintflt0;
+	u32	eintflt1;
+	u32	eintflt2;
+	u32	eintflt3;
+	u32	eintmask;
+	u32	eintpend;
+	u32	gstatus0;
+	u32	gstatus1;
+	u32	gstatus2;
+	u32	gstatus3;
+	u32	gstatus4;
+
+	u32	res9;
+	u32	dsc0;
+	u32	dsc1;
+	u32	mslcon;
+	u32	gpjcon;
+	u32	gpjdat;
+	u32	gpjup;
+	u32	res10;
+#endif
+};
+
+
+/* RTC (see manual chapter 17) */
+struct s3c24x0_rtc {
+#ifdef __BIG_ENDIAN
+	u8	res1[67];
+	u8	rtccon;
+	u8	res2[3];
+	u8	ticnt;
+	u8	res3[11];
+	u8	rtcalm;
+	u8	res4[3];
+	u8	almsec;
+	u8	res5[3];
+	u8	almmin;
+	u8	res6[3];
+	u8	almhour;
+	u8	res7[3];
+	u8	almdate;
+	u8	res8[3];
+	u8	almmon;
+	u8	res9[3];
+	u8	almyear;
+	u8	res10[3];
+	u8	rtcrst;
+	u8	res11[3];
+	u8	bcdsec;
+	u8	res12[3];
+	u8	bcdmin;
+	u8	res13[3];
+	u8	bcdhour;
+	u8	res14[3];
+	u8	bcddate;
+	u8	res15[3];
+	u8	bcdday;
+	u8	res16[3];
+	u8	bcdmon;
+	u8	res17[3];
+	u8	bcdyear;
+#else /*  little endian */
+	u8	res0[64];
+	u8	rtccon;
+	u8	res1[3];
+	u8	ticnt;
+	u8	res2[11];
+	u8	rtcalm;
+	u8	res3[3];
+	u8	almsec;
+	u8	res4[3];
+	u8	almmin;
+	u8	res5[3];
+	u8	almhour;
+	u8	res6[3];
+	u8	almdate;
+	u8	res7[3];
+	u8	almmon;
+	u8	res8[3];
+	u8	almyear;
+	u8	res9[3];
+	u8	rtcrst;
+	u8	res10[3];
+	u8	bcdsec;
+	u8	res11[3];
+	u8	bcdmin;
+	u8	res12[3];
+	u8	bcdhour;
+	u8	res13[3];
+	u8	bcddate;
+	u8	res14[3];
+	u8	bcdday;
+	u8	res15[3];
+	u8	bcdmon;
+	u8	res16[3];
+	u8	bcdyear;
+	u8	res17[3];
+#endif
+};
+
+
+/* ADC (see manual chapter 16) */
+struct s3c2400_adc {
+	u32	adccon;
+	u32	adcdat;
+};
+
+
+/* ADC (see manual chapter 16) */
+struct s3c2410_adc {
+	u32	adccon;
+	u32	adctsc;
+	u32	adcdly;
+	u32	adcdat0;
+	u32	adcdat1;
+};
+
+
+/* SPI (see manual chapter 22) */
+struct s3c24x0_spi_channel {
+	u8	spcon;
+	u8	res1[3];
+	u8	spsta;
+	u8	res2[3];
+	u8	sppin;
+	u8	res3[3];
+	u8	sppre;
+	u8	res4[3];
+	u8	sptdat;
+	u8	res5[3];
+	u8	sprdat;
+	u8	res6[3];
+	u8	res7[16];
+};
+
+struct s3c24x0_spi {
+	struct s3c24x0_spi_channel	ch[S3C24X0_SPI_CHANNELS];
+};
+
+
+/* MMC INTERFACE (see S3C2400 manual chapter 19) */
+struct s3c2400_mmc {
+#ifdef __BIG_ENDIAN
+	u8	res1[3];
+	u8	mmcon;
+	u8	res2[3];
+	u8	mmcrr;
+	u8	res3[3];
+	u8	mmfcon;
+	u8	res4[3];
+	u8	mmsta;
+	u16	res5;
+	u16	mmfsta;
+	u8	res6[3];
+	u8	mmpre;
+	u16	res7;
+	u16	mmlen;
+	u8	res8[3];
+	u8	mmcr7;
+	u32	mmrsp[4];
+	u8	res9[3];
+	u8	mmcmd0;
+	u32	mmcmd1;
+	u16	res10;
+	u16	mmcr16;
+	u8	res11[3];
+	u8	mmdat;
+#else
+	u8	mmcon;
+	u8	res1[3];
+	u8	mmcrr;
+	u8	res2[3];
+	u8	mmfcon;
+	u8	res3[3];
+	u8	mmsta;
+	u8	res4[3];
+	u16	mmfsta;
+	u16	res5;
+	u8	mmpre;
+	u8	res6[3];
+	u16	mmlen;
+	u16	res7;
+	u8	mmcr7;
+	u8	res8[3];
+	u32	mmrsp[4];
+	u8	mmcmd0;
+	u8	res9[3];
+	u32	mmcmd1;
+	u16	mmcr16;
+	u16	res10;
+	u8	mmdat;
+	u8	res11[3];
+#endif
+};
+
+
+/* SD INTERFACE (see S3C2410 manual chapter 19) */
+struct s3c2410_sdi {
+	u32	sdicon;
+	u32	sdipre;
+	u32	sdicarg;
+	u32	sdiccon;
+	u32	sdicsta;
+	u32	sdirsp0;
+	u32	sdirsp1;
+	u32	sdirsp2;
+	u32	sdirsp3;
+	u32	sdidtimer;
+	u32	sdibsize;
+	u32	sdidcon;
+	u32	sdidcnt;
+	u32	sdidsta;
+	u32	sdifsta;
+#ifdef __BIG_ENDIAN
+	u8	res[3];
+	u8	sdidat;
+#else
+	u8	sdidat;
+	u8	res[3];
+#endif
+	u32	sdiimsk;
+};
+
+#endif /*__S3C24X0_H__*/
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
new file mode 100644
index 000000000..393cc9d9f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2009
+ * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifdef CONFIG_S3C2400
+	#include <asm/arch/s3c2400.h>
+#elif defined CONFIG_S3C2410
+	#include <asm/arch/s3c2410.h>
+#elif defined CONFIG_S3C2440
+	#include <asm/arch/s3c2440.h>
+#else
+	#error Please define the s3c24x0 cpu type
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clk.h
new file mode 100644
index 000000000..6457ac738
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clk.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_CLK_H_
+#define __ASM_ARM_ARCH_CLK_H_
+
+#define APLL	0
+#define MPLL	1
+#define EPLL	2
+#define HPLL	3
+#define VPLL	4
+
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+void set_mmc_clk(int dev_index, unsigned int div);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clock.h
new file mode 100644
index 000000000..858496af5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/clock.h
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H_
+#define __ASM_ARM_ARCH_CLOCK_H_
+
+#ifndef __ASSEMBLY__
+struct s5pc100_clock {
+	unsigned int	apll_lock;
+	unsigned int	mpll_lock;
+	unsigned int	epll_lock;
+	unsigned int	hpll_lock;
+	unsigned char	res1[0xf0];
+	unsigned int	apll_con;
+	unsigned int	mpll_con;
+	unsigned int	epll_con;
+	unsigned int	hpll_con;
+	unsigned char	res2[0xf0];
+	unsigned int	src0;
+	unsigned int	src1;
+	unsigned int	src2;
+	unsigned int	src3;
+	unsigned char	res3[0xf0];
+	unsigned int	div0;
+	unsigned int	div1;
+	unsigned int	div2;
+	unsigned int	div3;
+	unsigned int	div4;
+	unsigned char	res4[0x1ec];
+	unsigned int	gate_d00;
+	unsigned int	gate_d01;
+	unsigned int	gate_d02;
+	unsigned char	res5[0x54];
+	unsigned int	gate_sclk0;
+	unsigned int	gate_sclk1;
+};
+
+struct s5pc110_clock {
+	unsigned int	apll_lock;
+	unsigned char	res1[0x4];
+	unsigned int	mpll_lock;
+	unsigned char	res2[0x4];
+	unsigned int	epll_lock;
+	unsigned char	res3[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res4[0xdc];
+	unsigned int	apll_con;
+	unsigned char	res5[0x4];
+	unsigned int	mpll_con;
+	unsigned char	res6[0x4];
+	unsigned int	epll_con;
+	unsigned char	res7[0xc];
+	unsigned int	vpll_con;
+	unsigned char	res8[0xdc];
+	unsigned int	src0;
+	unsigned int	src1;
+	unsigned int	src2;
+	unsigned int	src3;
+	unsigned char	res9[0xf0];
+	unsigned int	div0;
+	unsigned int	div1;
+	unsigned int	div2;
+	unsigned int	div3;
+	unsigned int	div4;
+	unsigned char	res10[0x1ec];
+	unsigned int	gate_d00;
+	unsigned int	gate_d01;
+	unsigned int	gate_d02;
+	unsigned char	res11[0x54];
+	unsigned int	gate_sclk0;
+	unsigned int	gate_sclk1;
+};
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/cpu.h
new file mode 100644
index 000000000..5ae5c8716
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/cpu.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _S5PC1XX_CPU_H
+#define _S5PC1XX_CPU_H
+
+#define S5P_CPU_NAME		"S5P"
+#define S5PC1XX_ADDR_BASE	0xE0000000
+
+/* S5PC100 */
+#define S5PC100_PRO_ID		0xE0000000
+#define S5PC100_CLOCK_BASE	0xE0100000
+#define S5PC100_GPIO_BASE	0xE0300000
+#define S5PC100_VIC0_BASE	0xE4000000
+#define S5PC100_VIC1_BASE	0xE4100000
+#define S5PC100_VIC2_BASE	0xE4200000
+#define S5PC100_DMC_BASE	0xE6000000
+#define S5PC100_SROMC_BASE	0xE7000000
+#define S5PC100_ONENAND_BASE	0xE7100000
+#define S5PC100_PWMTIMER_BASE	0xEA000000
+#define S5PC100_WATCHDOG_BASE	0xEA200000
+#define S5PC100_UART_BASE	0xEC000000
+#define S5PC100_MMC_BASE	0xED800000
+
+/* S5PC110 */
+#define S5PC110_PRO_ID		0xE0000000
+#define S5PC110_CLOCK_BASE	0xE0100000
+#define S5PC110_GPIO_BASE	0xE0200000
+#define S5PC110_PWMTIMER_BASE	0xE2500000
+#define S5PC110_WATCHDOG_BASE	0xE2700000
+#define S5PC110_UART_BASE	0xE2900000
+#define S5PC110_SROMC_BASE	0xE8000000
+#define S5PC110_MMC_BASE	0xEB000000
+#define S5PC110_DMC0_BASE	0xF0000000
+#define S5PC110_DMC1_BASE	0xF1400000
+#define S5PC110_VIC0_BASE	0xF2000000
+#define S5PC110_VIC1_BASE	0xF2100000
+#define S5PC110_VIC2_BASE	0xF2200000
+#define S5PC110_VIC3_BASE	0xF2300000
+#define S5PC110_OTG_BASE	0xEC000000
+#define S5PC110_PHY_BASE	0xEC100000
+#define S5PC110_USB_PHY_CONTROL 0xE010E80C
+
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+/* CPU detection macros */
+extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+	return s5p_cpu_rev;
+}
+
+static inline void s5p_set_cpu_id(void)
+{
+	s5p_cpu_id = readl(S5PC100_PRO_ID);
+	s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
+	s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
+}
+
+static inline char *s5p_get_cpu_name(void)
+{
+	return S5P_CPU_NAME;
+}
+
+#define IS_SAMSUNG_TYPE(type, id)			\
+static inline int cpu_is_##type(void)			\
+{							\
+	return s5p_cpu_id == id ? 1 : 0;		\
+}
+
+IS_SAMSUNG_TYPE(s5pc100, 0xc100)
+IS_SAMSUNG_TYPE(s5pc110, 0xc110)
+
+#define SAMSUNG_BASE(device, base)				\
+static inline unsigned int samsung_get_base_##device(void)	\
+{								\
+	if (cpu_is_s5pc100())					\
+		return S5PC100_##base;				\
+	else if (cpu_is_s5pc110())				\
+		return S5PC110_##base;				\
+	else							\
+		return 0;					\
+}
+
+SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(gpio, GPIO_BASE)
+SAMSUNG_BASE(pro_id, PRO_ID)
+SAMSUNG_BASE(mmc, MMC_BASE)
+SAMSUNG_BASE(sromc, SROMC_BASE)
+SAMSUNG_BASE(timer, PWMTIMER_BASE)
+SAMSUNG_BASE(uart, UART_BASE)
+SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
+#endif
+
+#endif	/* _S5PC1XX_CPU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/gpio.h
new file mode 100644
index 000000000..da8df74a1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+struct s5p_gpio_bank {
+	unsigned int	con;
+	unsigned int	dat;
+	unsigned int	pull;
+	unsigned int	drv;
+	unsigned int	pdn_con;
+	unsigned int	pdn_pull;
+	unsigned char	res1[8];
+};
+
+struct s5pc100_gpio {
+	struct s5p_gpio_bank a0;
+	struct s5p_gpio_bank a1;
+	struct s5p_gpio_bank b;
+	struct s5p_gpio_bank c;
+	struct s5p_gpio_bank d;
+	struct s5p_gpio_bank e0;
+	struct s5p_gpio_bank e1;
+	struct s5p_gpio_bank f0;
+	struct s5p_gpio_bank f1;
+	struct s5p_gpio_bank f2;
+	struct s5p_gpio_bank f3;
+	struct s5p_gpio_bank g0;
+	struct s5p_gpio_bank g1;
+	struct s5p_gpio_bank g2;
+	struct s5p_gpio_bank g3;
+	struct s5p_gpio_bank i;
+	struct s5p_gpio_bank j0;
+	struct s5p_gpio_bank j1;
+	struct s5p_gpio_bank j2;
+	struct s5p_gpio_bank j3;
+	struct s5p_gpio_bank j4;
+	struct s5p_gpio_bank k0;
+	struct s5p_gpio_bank k1;
+	struct s5p_gpio_bank k2;
+	struct s5p_gpio_bank k3;
+	struct s5p_gpio_bank l0;
+	struct s5p_gpio_bank l1;
+	struct s5p_gpio_bank l2;
+	struct s5p_gpio_bank l3;
+	struct s5p_gpio_bank l4;
+	struct s5p_gpio_bank h0;
+	struct s5p_gpio_bank h1;
+	struct s5p_gpio_bank h2;
+	struct s5p_gpio_bank h3;
+};
+
+struct s5pc110_gpio {
+	struct s5p_gpio_bank a0;
+	struct s5p_gpio_bank a1;
+	struct s5p_gpio_bank b;
+	struct s5p_gpio_bank c0;
+	struct s5p_gpio_bank c1;
+	struct s5p_gpio_bank d0;
+	struct s5p_gpio_bank d1;
+	struct s5p_gpio_bank e0;
+	struct s5p_gpio_bank e1;
+	struct s5p_gpio_bank f0;
+	struct s5p_gpio_bank f1;
+	struct s5p_gpio_bank f2;
+	struct s5p_gpio_bank f3;
+	struct s5p_gpio_bank g0;
+	struct s5p_gpio_bank g1;
+	struct s5p_gpio_bank g2;
+	struct s5p_gpio_bank g3;
+	struct s5p_gpio_bank i;
+	struct s5p_gpio_bank j0;
+	struct s5p_gpio_bank j1;
+	struct s5p_gpio_bank j2;
+	struct s5p_gpio_bank j3;
+	struct s5p_gpio_bank j4;
+	struct s5p_gpio_bank mp0_1;
+	struct s5p_gpio_bank mp0_2;
+	struct s5p_gpio_bank mp0_3;
+	struct s5p_gpio_bank mp0_4;
+	struct s5p_gpio_bank mp0_5;
+	struct s5p_gpio_bank mp0_6;
+	struct s5p_gpio_bank mp0_7;
+	struct s5p_gpio_bank mp1_0;
+	struct s5p_gpio_bank mp1_1;
+	struct s5p_gpio_bank mp1_2;
+	struct s5p_gpio_bank mp1_3;
+	struct s5p_gpio_bank mp1_4;
+	struct s5p_gpio_bank mp1_5;
+	struct s5p_gpio_bank mp1_6;
+	struct s5p_gpio_bank mp1_7;
+	struct s5p_gpio_bank mp1_8;
+	struct s5p_gpio_bank mp2_0;
+	struct s5p_gpio_bank mp2_1;
+	struct s5p_gpio_bank mp2_2;
+	struct s5p_gpio_bank mp2_3;
+	struct s5p_gpio_bank mp2_4;
+	struct s5p_gpio_bank mp2_5;
+	struct s5p_gpio_bank mp2_6;
+	struct s5p_gpio_bank mp2_7;
+	struct s5p_gpio_bank mp2_8;
+	struct s5p_gpio_bank res1[48];
+	struct s5p_gpio_bank h0;
+	struct s5p_gpio_bank h1;
+	struct s5p_gpio_bank h2;
+	struct s5p_gpio_bank h3;
+};
+
+/* functions */
+void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
+void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
+void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
+unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+
+/* GPIO pins per bank  */
+#define GPIO_PER_BANK 8
+
+#define S5P_GPIO_PART_SHIFT	(24)
+#define S5P_GPIO_PART_MASK	(0xff)
+#define S5P_GPIO_BANK_SHIFT	(8)
+#define S5P_GPIO_BANK_MASK	(0xffff)
+#define S5P_GPIO_PIN_MASK	(0xff)
+
+#define S5P_GPIO_SET_PART(x) \
+			(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+
+#define S5P_GPIO_GET_PART(x) \
+			(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+
+#define S5P_GPIO_SET_PIN(x) \
+			((x) & S5P_GPIO_PIN_MASK)
+
+#define S5PC100_SET_BANK(bank) \
+			(((unsigned)&(((struct s5pc100_gpio *) \
+			S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define S5PC110_SET_BANK(bank) \
+			((((unsigned)&(((struct s5pc110_gpio *) \
+			S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
+			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define s5pc100_gpio_get(bank, pin) \
+			(S5P_GPIO_SET_PART(0) | \
+			S5PC100_SET_BANK(bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+#define s5pc110_gpio_get(bank, pin) \
+			(S5P_GPIO_SET_PART(0) | \
+			S5PC110_SET_BANK(bank) | \
+			S5P_GPIO_SET_PIN(pin))
+
+static inline unsigned int s5p_gpio_base(int nr)
+{
+	return samsung_get_base_gpio();
+}
+#endif
+
+/* Pin configurations */
+#define GPIO_INPUT	0x0
+#define GPIO_OUTPUT	0x1
+#define GPIO_IRQ	0xf
+#define GPIO_FUNC(x)	(x)
+
+/* Pull mode */
+#define GPIO_PULL_NONE	0x0
+#define GPIO_PULL_DOWN	0x1
+#define GPIO_PULL_UP	0x2
+
+/* Drive Strength level */
+#define GPIO_DRV_1X	0x0
+#define GPIO_DRV_3X	0x1
+#define GPIO_DRV_2X	0x2
+#define GPIO_DRV_4X	0x3
+#define GPIO_DRV_FAST	0x0
+#define GPIO_DRV_SLOW	0x1
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/mmc.h
new file mode 100644
index 000000000..dd473c8ec
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MMC_H_
+#define __ASM_ARCH_MMC_H_
+
+#define S5P_MMC_DEV_OFFSET	0x100000
+
+#define SDHCI_CONTROL2		0x80
+#define SDHCI_CONTROL3		0x84
+#define SDHCI_CONTROL4		0x8C
+
+#define SDHCI_CTRL2_ENSTAASYNCCLR	(1 << 31)
+#define SDHCI_CTRL2_ENCMDCNFMSK		(1 << 30)
+#define SDHCI_CTRL2_CDINVRXD3		(1 << 29)
+#define SDHCI_CTRL2_SLCARDOUT		(1 << 28)
+
+#define SDHCI_CTRL2_FLTCLKSEL_MASK	(0xf << 24)
+#define SDHCI_CTRL2_FLTCLKSEL_SHIFT	(24)
+#define SDHCI_CTRL2_FLTCLKSEL(_x)	((_x) << 24)
+
+#define SDHCI_CTRL2_LVLDAT_MASK		(0xff << 16)
+#define SDHCI_CTRL2_LVLDAT_SHIFT	(16)
+#define SDHCI_CTRL2_LVLDAT(_x)		((_x) << 16)
+
+#define SDHCI_CTRL2_ENFBCLKTX		(1 << 15)
+#define SDHCI_CTRL2_ENFBCLKRX		(1 << 14)
+#define SDHCI_CTRL2_SDCDSEL		(1 << 13)
+#define SDHCI_CTRL2_SDSIGPC		(1 << 12)
+#define SDHCI_CTRL2_ENBUSYCHKTXSTART	(1 << 11)
+
+#define SDHCI_CTRL2_DFCNT_MASK(_x)	((_x) << 9)
+#define SDHCI_CTRL2_DFCNT_SHIFT		(9)
+
+#define SDHCI_CTRL2_ENCLKOUTHOLD	(1 << 8)
+#define SDHCI_CTRL2_RWAITMODE		(1 << 7)
+#define SDHCI_CTRL2_DISBUFRD		(1 << 6)
+#define SDHCI_CTRL2_SELBASECLK_MASK(_x)	((_x) << 4)
+#define SDHCI_CTRL2_SELBASECLK_SHIFT	(4)
+#define SDHCI_CTRL2_PWRSYNC		(1 << 3)
+#define SDHCI_CTRL2_ENCLKOUTMSKCON	(1 << 1)
+#define SDHCI_CTRL2_HWINITFIN		(1 << 0)
+
+#define SDHCI_CTRL3_FCSEL3		(1 << 31)
+#define SDHCI_CTRL3_FCSEL2		(1 << 23)
+#define SDHCI_CTRL3_FCSEL1		(1 << 15)
+#define SDHCI_CTRL3_FCSEL0		(1 << 7)
+
+#define SDHCI_CTRL4_DRIVE_MASK(_x)	((_x) << 16)
+#define SDHCI_CTRL4_DRIVE_SHIFT		(16)
+
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
+
+static inline int s5p_mmc_init(int index, int bus_width)
+{
+	unsigned int base = samsung_get_base_mmc() +
+				 (S5P_MMC_DEV_OFFSET * index);
+
+	return s5p_sdhci_init(base, index, bus_width);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/power.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/power.h
new file mode 100644
index 000000000..8400cda1e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/power.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_POWER_H_
+#define __ASM_ARM_ARCH_POWER_H_
+
+/*
+ * Power control
+ */
+#define S5PC100_OTHERS			0xE0108200
+#define S5PC100_RST_STAT		0xE0108300
+#define S5PC100_SLEEP_WAKEUP		(1 << 3)
+#define S5PC100_WAKEUP_STAT		0xE0108304
+#define S5PC100_INFORM0			0xE0108400
+
+#define S5PC110_RST_STAT		0xE010A000
+#define S5PC110_SLEEP_WAKEUP		(1 << 3)
+#define S5PC110_WAKEUP_STAT		0xE010C200
+#define S5PC110_OTHERS			0xE010E000
+#define S5PC110_USB_PHY_CON		0xE010E80C
+#define S5PC110_INFORM0			0xE010F000
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/pwm.h
new file mode 100644
index 000000000..7a33ed895
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/pwm.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+#define PRESCALER_0		(8 - 1)		/* prescaler of timer 0, 1 */
+#define PRESCALER_1		(16 - 1)	/* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1		0		/* 1/1 period */
+#define MUX_DIV_2		1		/* 1/2 period */
+#define MUX_DIV_4		2		/* 1/4 period */
+#define MUX_DIV_8		3		/* 1/8 period */
+#define MUX_DIV_16		4		/* 1/16 period */
+
+#define MUX_DIV_SHIFT(x)	(x * 4)
+
+#define TCON_OFFSET(x)		((x + 1) * (!!x) << 2)
+
+#define TCON_START(x)		(1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x)		(1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x)	(1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x)	(1 << (TCON_OFFSET(x) + 3))
+#define TCON4_AUTO_RELOAD	(1 << 22)
+
+#ifndef __ASSEMBLY__
+struct s5p_timer {
+	unsigned int	tcfg0;
+	unsigned int	tcfg1;
+	unsigned int	tcon;
+	unsigned int	tcntb0;
+	unsigned int	tcmpb0;
+	unsigned int	tcnto0;
+	unsigned int	tcntb1;
+	unsigned int	tcmpb1;
+	unsigned int	tcnto1;
+	unsigned int	tcntb2;
+	unsigned int	tcmpb2;
+	unsigned int	tcnto2;
+	unsigned int	tcntb3;
+	unsigned int	res1;
+	unsigned int	tcnto3;
+	unsigned int	tcntb4;
+	unsigned int	tcnto4;
+	unsigned int	tintcstat;
+};
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sromc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sromc.h
new file mode 100644
index 000000000..df1bf51bf
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sromc.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Note: This file contains the register description for Memory subsystem
+ * 	 (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *
+ * 	 Only SROMC is defined as of now
+ */
+
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
+
+#define SMC_DATA16_WIDTH(x)    (1<<((x*4)+0))
+#define SMC_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/
+						/* 1-> Byte base address*/
+#define SMC_WAIT_ENABLE(x)     (1<<((x*4)+2))
+#define SMC_BYTE_ENABLE(x)     (1<<((x*4)+3))
+
+#define SMC_BC_TACS(x) (x << 28) /* 0clk     address set-up */
+#define SMC_BC_TCOS(x) (x << 24) /* 4clk     chip selection set-up */
+#define SMC_BC_TACC(x) (x << 16) /* 14clk    access cycle */
+#define SMC_BC_TCOH(x) (x << 12) /* 1clk     chip selection hold */
+#define SMC_BC_TAH(x)  (x << 8)  /* 4clk     address holding time */
+#define SMC_BC_TACP(x) (x << 4)  /* 6clk     page mode access cycle */
+#define SMC_BC_PMC(x)  (x << 0)  /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5p_sromc {
+	unsigned int	bw;
+	unsigned int	bc[6];
+};
+#endif	/* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+#endif /* __ASM_ARCH_SMC_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h
new file mode 100644
index 000000000..647d6c438
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2009 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_device_type(void);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/uart.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/uart.h
new file mode 100644
index 000000000..26db09884
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/uart.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+/* baudrate rest value */
+union br_rest {
+	unsigned short	slot;		/* udivslot */
+	unsigned char	value;		/* ufracval */
+};
+
+struct s5p_uart {
+	unsigned int	ulcon;
+	unsigned int	ucon;
+	unsigned int	ufcon;
+	unsigned int	umcon;
+	unsigned int	utrstat;
+	unsigned int	uerstat;
+	unsigned int	ufstat;
+	unsigned int	umstat;
+	unsigned char	utxh;
+	unsigned char	res1[3];
+	unsigned char	urxh;
+	unsigned char	res2[3];
+	unsigned int	ubrdiv;
+	union br_rest	rest;
+	unsigned char	res3[0x3d0];
+};
+
+static inline int s5p_uart_divslot(void)
+{
+	return 1;
+}
+
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/watchdog.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/watchdog.h
new file mode 100644
index 000000000..2f9746c2f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-s5pc1xx/watchdog.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_WATCHDOG_H_
+#define __ASM_ARM_ARCH_WATCHDOG_H_
+
+#define WTCON_RESET_OFFSET	0
+#define WTCON_INTEN_OFFSET	2
+#define WTCON_CLKSEL_OFFSET	3
+#define WTCON_EN_OFFSET		5
+#define WTCON_PRE_OFFSET	8
+
+#define WTCON_CLK_16		0x0
+#define WTCON_CLK_32		0x1
+#define WTCON_CLK_64		0x2
+#define WTCON_CLK_128		0x3
+
+#define WTCON_CLK(x)		((x & 0x3) << WTCON_CLKSEL_OFFSET)
+#define WTCON_PRESCALER(x)	((x) << WTCON_PRE_OFFSET)
+#define WTCON_EN		(0x1 << WTCON_EN_OFFSET)
+#define WTCON_RESET		(0x1 << WTCON_RESET_OFFSET)
+#define WTCON_INT		(0x1 << WTCON_INTEN_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct s5p_watchdog {
+	unsigned int wtcon;
+	unsigned int wtdat;
+	unsigned int wtcnt;
+	unsigned int wtclrint;
+};
+
+/* functions */
+void wdt_stop(void);
+void wdt_start(unsigned int timeout);
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-sa1100/bitfield.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-sa1100/bitfield.h
new file mode 100644
index 000000000..104a21c2e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-sa1100/bitfield.h
@@ -0,0 +1,112 @@
+/*
+ *	FILE		bitfield.h
+ *
+ *	Version		1.1
+ *	Author		Copyright (c) Marc A. Viredaz, 1998
+ *			DEC Western Research Laboratory, Palo Alto, CA
+ *	Date		April 1998 (April 1997)
+ *	System		Advanced RISC Machine (ARM)
+ *	Language	C or ARM Assembly
+ *	Purpose		Definition of macros to operate on bit fields.
+ */
+
+
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
+
+#ifndef __ASSEMBLY__
+#define UData(Data)	((unsigned long) (Data))
+#else
+#define UData(Data)	(Data)
+#endif
+
+
+/*
+ * MACRO: Fld
+ *
+ * Purpose
+ *    The macro "Fld" encodes a bit field, given its size and its shift value
+ *    with respect to bit 0.
+ *
+ * Note
+ *    A more intuitive way to encode bit fields would have been to use their
+ *    mask. However, extracting size and shift value information from a bit
+ *    field's mask is cumbersome and might break the assembler (255-character
+ *    line-size limit).
+ *
+ * Input
+ *    Size		Size of the bit field, in number of bits.
+ *    Shft		Shift value of the bit field with respect to bit 0.
+ *
+ * Output
+ *    Fld		Encoded bit field.
+ */
+
+#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
+
+
+/*
+ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
+ *
+ * Purpose
+ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
+ *    the size, shift value, mask, aligned mask, and first bit of a
+ *    bit field.
+ *
+ * Input
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FSize		Size of the bit field, in number of bits.
+ *    FShft		Shift value of the bit field with respect to bit 0.
+ *    FMsk		Mask for the bit field.
+ *    FAlnMsk		Mask for the bit field, aligned on bit 0.
+ *    F1stBit		First bit of the bit field.
+ */
+
+#define FSize(Field)	((Field) >> 16)
+#define FShft(Field)	((Field) & 0x0000FFFF)
+#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field)	(UData (1) << FShft (Field))
+
+
+/*
+ * MACRO: FInsrt
+ *
+ * Purpose
+ *    The macro "FInsrt" inserts a value into a bit field by shifting the
+ *    former appropriately.
+ *
+ * Input
+ *    Value		Bit-field value.
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FInsrt		Bit-field value positioned appropriately.
+ */
+
+#define FInsrt(Value, Field) \
+			(UData (Value) << FShft (Field))
+
+
+/*
+ * MACRO: FExtr
+ *
+ * Purpose
+ *    The macro "FExtr" extracts the value of a bit field by masking and
+ *    shifting it appropriately.
+ *
+ * Input
+ *    Data		Data containing the bit-field to be extracted.
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FExtr		Bit-field value.
+ */
+
+#define FExtr(Data, Field) \
+			((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+
+#endif /* __BITFIELD_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h
new file mode 100644
index 000000000..966add3e9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h
@@ -0,0 +1,205 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_CLOCK_MANAGER_H_
+#define	_CLOCK_MANAGER_H_
+
+typedef struct {
+	/* main group */
+	uint32_t main_vco_base;
+	uint32_t mpuclk;
+	uint32_t mainclk;
+	uint32_t dbgatclk;
+	uint32_t mainqspiclk;
+	uint32_t mainnandsdmmcclk;
+	uint32_t cfg2fuser0clk;
+	uint32_t maindiv;
+	uint32_t dbgdiv;
+	uint32_t tracediv;
+	uint32_t l4src;
+
+	/* peripheral group */
+	uint32_t peri_vco_base;
+	uint32_t emac0clk;
+	uint32_t emac1clk;
+	uint32_t perqspiclk;
+	uint32_t pernandsdmmcclk;
+	uint32_t perbaseclk;
+	uint32_t s2fuser1clk;
+	uint32_t perdiv;
+	uint32_t gpiodiv;
+	uint32_t persrc;
+
+	/* sdram pll group */
+	uint32_t sdram_vco_base;
+	uint32_t ddrdqsclk;
+	uint32_t ddr2xdqsclk;
+	uint32_t ddrdqclk;
+	uint32_t s2fuser2clk;
+} cm_config_t;
+
+extern void cm_basic_init(const cm_config_t *cfg);
+
+struct socfpga_clock_manager {
+	u32	ctrl;
+	u32	bypass;
+	u32	inter;
+	u32	intren;
+	u32	dbctrl;
+	u32	stat;
+	u32	_pad_0x18_0x3f[10];
+	u32	mainpllgrp;
+	u32	perpllgrp;
+	u32	sdrpllgrp;
+	u32	_pad_0xe0_0x200[72];
+
+	u32	main_pll_vco;
+	u32	main_pll_misc;
+	u32	main_pll_mpuclk;
+	u32	main_pll_mainclk;
+	u32	main_pll_dbgatclk;
+	u32	main_pll_mainqspiclk;
+	u32	main_pll_mainnandsdmmcclk;
+	u32	main_pll_cfgs2fuser0clk;
+	u32	main_pll_en;
+	u32	main_pll_maindiv;
+	u32	main_pll_dbgdiv;
+	u32	main_pll_tracediv;
+	u32	main_pll_l4src;
+	u32	main_pll_stat;
+	u32	main_pll__pad_0x38_0x40[2];
+
+	u32	per_pll_vco;
+	u32	per_pll_misc;
+	u32	per_pll_emac0clk;
+	u32	per_pll_emac1clk;
+	u32	per_pll_perqspiclk;
+	u32	per_pll_pernandsdmmcclk;
+	u32	per_pll_perbaseclk;
+	u32	per_pll_s2fuser1clk;
+	u32	per_pll_en;
+	u32	per_pll_div;
+	u32	per_pll_gpiodiv;
+	u32	per_pll_src;
+	u32	per_pll_stat;
+	u32	per_pll__pad_0x34_0x40[3];
+
+	u32	sdr_pll_vco;
+	u32	sdr_pll_ctrl;
+	u32	sdr_pll_ddrdqsclk;
+	u32	sdr_pll_ddr2xdqsclk;
+	u32	sdr_pll_ddrdqclk;
+	u32	sdr_pll_s2fuser2clk;
+	u32	sdr_pll_en;
+	u32	sdr_pll_stat;
+};
+
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x)  (((x) << 7) & 0x00000380)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
+#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
+#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
+	(((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
+	(((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
+#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
+#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
+#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
+#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
+#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
+
+#define MAIN_VCO_BASE \
+	(CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
+	CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
+
+#define PERI_VCO_BASE \
+	(CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
+	CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
+	CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
+
+#define SDR_VCO_BASE \
+	(CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
+	CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
+	CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
+
+#endif /* _CLOCK_MANAGER_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/dwmmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/dwmmc.h
new file mode 100644
index 000000000..945eb646c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/dwmmc.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_SOCFPGA_DWMMC_H_
+#define	_SOCFPGA_DWMMC_H_
+
+extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index);
+
+#endif /* _SOCFPGA_SDMMC_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h
new file mode 100644
index 000000000..120f20e03
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_FREEZE_CONTROLLER_H_
+#define	_FREEZE_CONTROLLER_H_
+
+struct socfpga_freeze_controller {
+	u32	vioctrl;
+	u32	padding[3];
+	u32	hioctrl;
+	u32	src;
+	u32	hwctrl;
+};
+
+#define FREEZE_CHANNEL_NUM		(4)
+
+typedef enum {
+	FREEZE_CTRL_FROZEN = 0,
+	FREEZE_CTRL_THAWED = 1
+} FREEZE_CTRL_CHAN_STATE;
+
+#define SYSMGR_FRZCTRL_ADDRESS 0x40
+#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
+#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
+#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
+#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
+#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
+#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
+#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
+#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
+#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
+#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
+#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
+#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
+#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
+#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
+#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
+
+void sys_mgr_frzctrl_freeze_req(void);
+void sys_mgr_frzctrl_thaw_req(void);
+
+#endif /* _FREEZE_CONTROLLER_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/reset_manager.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/reset_manager.h
new file mode 100644
index 000000000..3e9547682
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -0,0 +1,30 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_RESET_MANAGER_H_
+#define	_RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+	u32	status;
+	u32	ctrl;
+	u32	counts;
+	u32	padding1;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+};
+
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
+#else
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+#endif
+
+#endif /* _RESET_MANAGER_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
new file mode 100644
index 000000000..f564046bc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -0,0 +1,18 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/spl.h
new file mode 100644
index 000000000..7e310d5a0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/spl.h
@@ -0,0 +1,15 @@
+/*
+ *  Copyright (C) 2012 Pavel Machek <pavel@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_SPL_H_
+#define _SOCFPGA_SPL_H_
+
+/* Symbols from linker script */
+extern char __malloc_start, __malloc_end, __stack_start;
+
+#define BOOT_DEVICE_RAM 1
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/system_manager.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/system_manager.h
new file mode 100644
index 000000000..838d21053
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -0,0 +1,87 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_SYSTEM_MANAGER_H_
+#define	_SYSTEM_MANAGER_H_
+
+#ifndef __ASSEMBLY__
+
+void sysmgr_pinmux_init(void);
+
+/* declaration for handoff table type */
+extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
+
+#endif
+
+
+#define CONFIG_SYSMGR_PINMUXGRP_OFFSET	(0x400)
+
+#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
+	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+
+struct socfpga_system_manager {
+	u32	siliconid1;
+	u32	siliconid2;
+	u32	_pad_0x8_0xf[2];
+	u32	wddbg;
+	u32	bootinfo;
+	u32	hpsinfo;
+	u32	parityinj;
+	u32	fpgaintfgrp_gbl;
+	u32	fpgaintfgrp_indiv;
+	u32	fpgaintfgrp_module;
+	u32	_pad_0x2c_0x2f;
+	u32	scanmgrgrp_ctrl;
+	u32	_pad_0x34_0x3f[3];
+	u32	frzctrl_vioctrl;
+	u32	_pad_0x44_0x4f[3];
+	u32	frzctrl_hioctrl;
+	u32	frzctrl_src;
+	u32	frzctrl_hwctrl;
+	u32	_pad_0x5c_0x5f;
+	u32	emacgrp_ctrl;
+	u32	emacgrp_l3master;
+	u32	_pad_0x68_0x6f[2];
+	u32	dmagrp_ctrl;
+	u32	dmagrp_persecurity;
+	u32	_pad_0x78_0x7f[2];
+	u32	iswgrp_handoff[8];
+	u32	_pad_0xa0_0xbf[8];
+	u32	romcodegrp_ctrl;
+	u32	romcodegrp_cpu1startaddr;
+	u32	romcodegrp_initswstate;
+	u32	romcodegrp_initswlastld;
+	u32	romcodegrp_bootromswstate;
+	u32	__pad_0xd4_0xdf[3];
+	u32	romcodegrp_warmramgrp_enable;
+	u32	romcodegrp_warmramgrp_datastart;
+	u32	romcodegrp_warmramgrp_length;
+	u32	romcodegrp_warmramgrp_execution;
+	u32	romcodegrp_warmramgrp_crc;
+	u32	__pad_0xf4_0xff[3];
+	u32	romhwgrp_ctrl;
+	u32	_pad_0x104_0x107;
+	u32	sdmmcgrp_ctrl;
+	u32	sdmmcgrp_l3master;
+	u32	nandgrp_bootstrap;
+	u32	nandgrp_l3master;
+	u32	usbgrp_l3master;
+	u32	_pad_0x11c_0x13f[9];
+	u32	eccgrp_l2;
+	u32	eccgrp_ocram;
+	u32	eccgrp_usb0;
+	u32	eccgrp_usb1;
+	u32	eccgrp_emac0;
+	u32	eccgrp_emac1;
+	u32	eccgrp_dma;
+	u32	eccgrp_can0;
+	u32	eccgrp_can1;
+	u32	eccgrp_nand;
+	u32	eccgrp_qspi;
+	u32	eccgrp_sdmmc;
+};
+
+#endif /* _SYSTEM_MANAGER_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/timer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/timer.h
new file mode 100644
index 000000000..ee6969bac
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-socfpga/timer.h
@@ -0,0 +1,18 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_TIMER_H_
+#define _SOCFPGA_TIMER_H_
+
+struct socfpga_timer {
+	u32	load_val;
+	u32	curr_val;
+	u32	ctrl;
+	u32	eoi;
+	u32	int_stat;
+};
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/clk.h
new file mode 100644
index 000000000..a07d0d5f9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/clk.h
@@ -0,0 +1,11 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+	return 83000000;
+}
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h
new file mode 100644
index 000000000..54e6b5bfd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/gpio.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __ASM_ARCH_SPEAR_GPIO_H
+#define __ASM_ARCH_SPEAR_GPIO_H
+
+enum gpio_direction {
+	GPIO_DIRECTION_IN,
+	GPIO_DIRECTION_OUT,
+};
+
+struct gpio_regs {
+	u32 gpiodata[0x100];	/* 0x000 ... 0x3fc */
+	u32 gpiodir;		/* 0x400 */
+};
+
+#define SPEAR_GPIO_COUNT		8
+#define DATA_REG_ADDR(gpio)		(1 << (gpio + 2))
+
+#endif	/* __ASM_ARCH_SPEAR_GPIO_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/hardware.h
new file mode 100644
index 000000000..c6da405cc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/hardware.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define CONFIG_SYS_USBD_BASE			0xE1100000
+#define CONFIG_SYS_PLUG_BASE			0xE1200000
+#define CONFIG_SYS_FIFO_BASE			0xE1000800
+#define CONFIG_SYS_SMI_BASE			0xFC000000
+#define CONFIG_SPEAR_SYSCNTLBASE		0xFCA00000
+#define CONFIG_SPEAR_TIMERBASE			0xFC800000
+#define CONFIG_SPEAR_MISCBASE			0xFCA80000
+#define CONFIG_SPEAR_ETHBASE			0xE0800000
+#define CONFIG_SPEAR_MPMCBASE			0xFC600000
+#define CONFIG_SSP1_BASE			0xD0100000
+#define CONFIG_SSP2_BASE			0xD0180000
+#define CONFIG_SSP3_BASE			0xD8180000
+#define CONFIG_GPIO_BASE			0xD8100000
+
+#define CONFIG_SYS_NAND_CLE			(1 << 16)
+#define CONFIG_SYS_NAND_ALE			(1 << 17)
+
+#if defined(CONFIG_SPEAR600)
+#define CONFIG_SYS_FSMC_BASE			0xD1800000
+#define CONFIG_FSMC_NAND_BASE			0xD2000000
+
+#define CONFIG_SPEAR_BOOTSTRAPCFG		0xFCA80000
+#define CONFIG_SPEAR_BOOTSTRAPSHFT		16
+#define CONFIG_SPEAR_BOOTSTRAPMASK		0xB
+#define CONFIG_SPEAR_ONLYSNORBOOT		0xA
+#define CONFIG_SPEAR_NORNANDBOOT		0xB
+#define CONFIG_SPEAR_NORNAND8BOOT		0x8
+#define CONFIG_SPEAR_NORNAND16BOOT		0x9
+#define CONFIG_SPEAR_USBBOOT			0x8
+
+#define CONFIG_SPEAR_MPMCREGS			100
+
+#elif defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_FSMC_BASE			0x94000000
+
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_FSMC_BASE			0x44000000
+
+#undef CONFIG_SYS_NAND_CLE
+#undef CONFIG_SYS_NAND_ALE
+#define CONFIG_SYS_NAND_CLE			(1 << 17)
+#define CONFIG_SYS_NAND_ALE			(1 << 16)
+
+#define CONFIG_SPEAR_EMIBASE			0x4F000000
+#define CONFIG_SPEAR_RASBASE			0xB4000000
+
+#define CONFIG_SYS_MACB0_BASE			0xB0000000
+#define CONFIG_SYS_MACB1_BASE			0xB0800000
+#define CONFIG_SYS_MACB2_BASE			0xB1000000
+#define CONFIG_SYS_MACB3_BASE			0xB1800000
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_FSMC_BASE			0x4C000000
+
+#define CONFIG_SPEAR_EMIBASE			0x40000000
+#define CONFIG_SPEAR_RASBASE			0xB3000000
+
+#define CONFIG_SYS_MACB0_BASE			0xAA000000
+
+#endif
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_defs.h
new file mode 100644
index 000000000..7e77a3033
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_defs.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SPR_DEFS_H__
+#define __SPR_DEFS_H__
+
+extern int spear_board_init(ulong);
+extern void setfreq(unsigned int, unsigned int);
+extern unsigned int setfreq_sz;
+
+void plat_ddr_init(void);
+void soc_init(void);
+void spear_late_init(void);
+void plat_late_init(void);
+
+int snor_boot_selected(void);
+int nand_boot_selected(void);
+int pnor_boot_selected(void);
+int usb_boot_selected(void);
+int uart_boot_selected(void);
+int tftp_boot_selected(void);
+int i2c_boot_selected(void);
+int spi_boot_selected(void);
+int mmc_boot_selected(void);
+
+extern u32 mpmc_conf_vals[];
+
+struct chip_data {
+	int cpufreq;
+	int dramfreq;
+	int dramtype;
+	uchar version[32];
+};
+
+/* HW mac id in i2c memory definitions */
+#define MAGIC_OFF	0x0
+#define MAGIC_LEN	0x2
+#define MAGIC_BYTE0	0x55
+#define MAGIC_BYTE1	0xAA
+#define MAC_OFF		0x2
+#define MAC_LEN		0x6
+
+#define PNOR_WIDTH_8			0
+#define	PNOR_WIDTH_16			1
+#define	PNOR_WIDTH_32			2
+#define PNOR_WIDTH_NUM			3
+#define PNOR_WIDTH_SEARCH		0xff
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_emi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_emi.h
new file mode 100644
index 000000000..3a6acb58c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_emi.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2009
+ * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SPEAR_EMI_H__
+#define __SPEAR_EMI_H__
+
+#ifdef CONFIG_SPEAR_EMI
+
+struct emi_bank_regs {
+	u32 tap;
+	u32 tsdp;
+	u32 tdpw;
+	u32 tdpr;
+	u32 tdcs;
+	u32 control;
+};
+
+struct emi_regs {
+	struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS];
+	u32 tout;
+	u32 ack;
+	u32 irq;
+};
+
+#define EMI_ACKMSK		0x40
+
+/* control register definitions */
+#define EMI_CNTL_ENBBYTEW	(1 << 2)
+#define EMI_CNTL_ENBBYTER	(1 << 3)
+#define EMI_CNTL_ENBBYTERW	(EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
+
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_gpt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_gpt.h
new file mode 100644
index 000000000..687e08017
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_gpt.h
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SPR_GPT_H
+#define _SPR_GPT_H
+
+struct gpt_regs {
+	u8 reserved[0x80];
+	u32 control;
+	u32 status;
+	u32 compare;
+	u32 count;
+	u32 capture_re;
+	u32 capture_fe;
+};
+
+/*
+ * TIMER_CONTROL register settings
+ */
+
+#define GPT_PRESCALER_MASK		0x000F
+#define GPT_PRESCALER_1			0x0000
+#define GPT_PRESCALER_2 		0x0001
+#define GPT_PRESCALER_4 		0x0002
+#define GPT_PRESCALER_8 		0x0003
+#define GPT_PRESCALER_16		0x0004
+#define GPT_PRESCALER_32		0x0005
+#define GPT_PRESCALER_64		0x0006
+#define GPT_PRESCALER_128		0x0007
+#define GPT_PRESCALER_256		0x0008
+
+#define GPT_MODE_SINGLE_SHOT		0x0010
+#define GPT_MODE_AUTO_RELOAD		0x0000
+
+#define GPT_ENABLE			0x0020
+
+#define GPT_CAPT_MODE_MASK		0x00C0
+#define GPT_CAPT_MODE_NONE		0x0000
+#define GPT_CAPT_MODE_RE		0x0040
+#define GPT_CAPT_MODE_FE		0x0080
+#define GPT_CAPT_MODE_BOTH		0x00C0
+
+#define GPT_INT_MATCH			0x0100
+#define GPT_INT_FE			0x0200
+#define GPT_INT_RE			0x0400
+
+/*
+ * TIMER_STATUS register settings
+ */
+
+#define GPT_STS_MATCH			0x0001
+#define GPT_STS_FE			0x0002
+#define GPT_STS_RE			0x0004
+
+/*
+ * TIMER_COMPARE register settings
+ */
+
+#define GPT_FREE_RUNNING		0xFFFF
+
+/* Timer, HZ specific defines */
+#define CONFIG_SPEAR_HZ			1000
+#define CONFIG_SPEAR_HZ_CLOCK		8300000
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_misc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_misc.h
new file mode 100644
index 000000000..b55026ecd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SPR_MISC_H
+#define _SPR_MISC_H
+
+struct misc_regs {
+	u32 auto_cfg_reg;	/* 0x0 */
+	u32 armdbg_ctr_reg;	/* 0x4 */
+	u32 pll1_cntl;		/* 0x8 */
+	u32 pll1_frq;		/* 0xc */
+	u32 pll1_mod;		/* 0x10 */
+	u32 pll2_cntl;		/* 0x14 */
+	u32 pll2_frq;		/* 0x18 */
+	u32 pll2_mod;		/* 0x1C */
+	u32 pll_ctr_reg;	/* 0x20 */
+	u32 amba_clk_cfg;	/* 0x24 */
+	u32 periph_clk_cfg;	/* 0x28 */
+	u32 periph1_clken;	/* 0x2C */
+	u32 soc_core_id;	/* 0x30 */
+	u32 ras_clken;		/* 0x34 */
+	u32 periph1_rst;	/* 0x38 */
+	u32 periph2_rst;	/* 0x3C */
+	u32 ras_rst;		/* 0x40 */
+	u32 prsc1_clk_cfg;	/* 0x44 */
+	u32 prsc2_clk_cfg;	/* 0x48 */
+	u32 prsc3_clk_cfg;	/* 0x4C */
+	u32 amem_cfg_ctrl;	/* 0x50 */
+	u32 expi_clk_cfg;	/* 0x54 */
+	u32 reserved_1;		/* 0x58 */
+	u32 clcd_synth_clk;	/* 0x5C */
+	u32 irda_synth_clk;	/* 0x60 */
+	u32 uart_synth_clk;	/* 0x64 */
+	u32 gmac_synth_clk;	/* 0x68 */
+	u32 ras_synth1_clk;	/* 0x6C */
+	u32 ras_synth2_clk;	/* 0x70 */
+	u32 ras_synth3_clk;	/* 0x74 */
+	u32 ras_synth4_clk;	/* 0x78 */
+	u32 arb_icm_ml1;	/* 0x7C */
+	u32 arb_icm_ml2;	/* 0x80 */
+	u32 arb_icm_ml3;	/* 0x84 */
+	u32 arb_icm_ml4;	/* 0x88 */
+	u32 arb_icm_ml5;	/* 0x8C */
+	u32 arb_icm_ml6;	/* 0x90 */
+	u32 arb_icm_ml7;	/* 0x94 */
+	u32 arb_icm_ml8;	/* 0x98 */
+	u32 arb_icm_ml9;	/* 0x9C */
+	u32 dma_src_sel;	/* 0xA0 */
+	u32 uphy_ctr_reg;	/* 0xA4 */
+	u32 gmac_ctr_reg;	/* 0xA8 */
+	u32 port_bridge_ctrl;	/* 0xAC */
+	u32 reserved_2[4];	/* 0xB0--0xBC */
+	u32 prc1_ilck_ctrl_reg;	/* 0xC0 */
+	u32 prc2_ilck_ctrl_reg;	/* 0xC4 */
+	u32 prc3_ilck_ctrl_reg;	/* 0xC8 */
+	u32 prc4_ilck_ctrl_reg;	/* 0xCC */
+	u32 prc1_intr_ctrl_reg;	/* 0xD0 */
+	u32 prc2_intr_ctrl_reg;	/* 0xD4 */
+	u32 prc3_intr_ctrl_reg;	/* 0xD8 */
+	u32 prc4_intr_ctrl_reg;	/* 0xDC */
+	u32 powerdown_cfg_reg;	/* 0xE0 */
+	u32 ddr_1v8_compensation;	/* 0xE4  */
+	u32 ddr_2v5_compensation;	/* 0xE8 */
+	u32 core_3v3_compensation;	/* 0xEC */
+	u32 ddr_pad;		/* 0xF0 */
+	u32 bist1_ctr_reg;	/* 0xF4 */
+	u32 bist2_ctr_reg;	/* 0xF8 */
+	u32 bist3_ctr_reg;	/* 0xFC */
+	u32 bist4_ctr_reg;	/* 0x100 */
+	u32 bist5_ctr_reg;	/* 0x104 */
+	u32 bist1_rslt_reg;	/* 0x108 */
+	u32 bist2_rslt_reg;	/* 0x10C */
+	u32 bist3_rslt_reg;	/* 0x110 */
+	u32 bist4_rslt_reg;	/* 0x114 */
+	u32 bist5_rslt_reg;	/* 0x118 */
+	u32 syst_error_reg;	/* 0x11C */
+	u32 reserved_3[0x1FB8];	/* 0x120--0x7FFC */
+	u32 ras_gpp1_in;	/* 0x8000 */
+	u32 ras_gpp2_in;	/* 0x8004 */
+	u32 ras_gpp1_out;	/* 0x8008 */
+	u32 ras_gpp2_out;	/* 0x800C */
+};
+
+/* SYNTH_CLK value*/
+#define SYNTH23			0x00020003
+
+/* PLLx_FRQ value */
+#if defined(CONFIG_SPEAR3XX)
+#define FREQ_332		0xA600010C
+#define FREQ_266		0x8500010C
+#elif defined(CONFIG_SPEAR600)
+#define FREQ_332		0xA600010F
+#define FREQ_266		0x8500010F
+#endif
+
+/* PLL_CTR_REG   */
+#define MEM_CLK_SEL_MSK		0x70000000
+#define MEM_CLK_HCLK		0x00000000
+#define MEM_CLK_2HCLK		0x10000000
+#define MEM_CLK_PLL2		0x30000000
+
+#define EXPI_CLK_CFG_LOW_COMPR	0x2000
+#define EXPI_CLK_CFG_CLK_EN	0x0400
+#define EXPI_CLK_CFG_RST	0x0200
+#define EXPI_CLK_SYNT_EN	0x0010
+#define EXPI_CLK_CFG_SEL_PLL2	0x0004
+#define EXPI_CLK_CFG_INT_CLK_EN	0x0001
+
+#define PLL2_CNTL_6UA		0x1c00
+#define PLL2_CNTL_SAMPLE	0x0008
+#define PLL2_CNTL_ENABLE	0x0004
+#define PLL2_CNTL_RESETN	0x0002
+#define PLL2_CNTL_LOCK		0x0001
+
+/* AUTO_CFG_REG value */
+#define MISC_SOCCFGMSK                  0x0000003F
+#define MISC_SOCCFG30                   0x0000000C
+#define MISC_SOCCFG31                   0x0000000D
+#define MISC_NANDDIS			0x00020000
+
+/* PERIPH_CLK_CFG value */
+#define MISC_GPT3SYNTH			0x00000400
+#define MISC_GPT4SYNTH			0x00000800
+#define CONFIG_SPEAR_UART48M		0
+#define CONFIG_SPEAR_UARTCLKMSK		(0x1 << 4)
+
+/* PRSC_CLK_CFG value */
+/*
+ * Fout = Fin / (2^(N+1) * (M + 1))
+ */
+#define MISC_PRSC_N_1			0x00001000
+#define MISC_PRSC_M_9			0x00000009
+#define MISC_PRSC_N_4			0x00004000
+#define MISC_PRSC_M_399			0x0000018F
+#define MISC_PRSC_N_6			0x00006000
+#define MISC_PRSC_M_2593		0x00000A21
+#define MISC_PRSC_M_124			0x0000007C
+#define MISC_PRSC_CFG			(MISC_PRSC_N_1 | MISC_PRSC_M_9)
+
+/* PERIPH1_CLKEN, PERIPH1_RST value */
+#define MISC_USBDENB			0x01000000
+#define MISC_ETHENB			0x00800000
+#define MISC_SMIENB			0x00200000
+#define MISC_GPT3ENB			0x00010000
+#define MISC_GPIO4ENB			0x00002000
+#define MISC_GPT2ENB			0x00000800
+#define MISC_FSMCENB			0x00000200
+#define MISC_I2CENB			0x00000080
+#define MISC_SSP2ENB			0x00000070
+#define MISC_UART0ENB			0x00000008
+
+/*   PERIPH_CLK_CFG   */
+#define  XTALTIMEEN		0x00000001
+#define  PLLTIMEEN		0x00000002
+#define  CLCDCLK_SYNTH		0x00000000
+#define  CLCDCLK_48MHZ		0x00000004
+#define  CLCDCLK_EXT		0x00000008
+#define  UARTCLK_MASK		(0x1 << 4)
+#define  UARTCLK_48MHZ		0x00000000
+#define  UARTCLK_SYNTH		0x00000010
+#define  IRDACLK_48MHZ		0x00000000
+#define  IRDACLK_SYNTH		0x00000020
+#define  IRDACLK_EXT		0x00000040
+#define  RTC_DISABLE		0x00000080
+#define  GPT1CLK_48MHZ		0x00000000
+#define  GPT1CLK_SYNTH		0x00000100
+#define  GPT2CLK_48MHZ		0x00000000
+#define  GPT2CLK_SYNTH		0x00000200
+#define  GPT3CLK_48MHZ		0x00000000
+#define  GPT3CLK_SYNTH		0x00000400
+#define  GPT4CLK_48MHZ		0x00000000
+#define  GPT4CLK_SYNTH		0x00000800
+#define  GPT5CLK_48MHZ		0x00000000
+#define  GPT5CLK_SYNTH		0x00001000
+#define  GPT1_FREEZE		0x00002000
+#define  GPT2_FREEZE		0x00004000
+#define  GPT3_FREEZE		0x00008000
+#define  GPT4_FREEZE		0x00010000
+#define  GPT5_FREEZE		0x00020000
+
+/*  PERIPH1_CLKEN bits  */
+#define PERIPH_ARM1_WE		0x00000001
+#define PERIPH_ARM1		0x00000002
+#define PERIPH_ARM2		0x00000004
+#define PERIPH_UART1		0x00000008
+#define PERIPH_UART2		0x00000010
+#define PERIPH_SSP1		0x00000020
+#define PERIPH_SSP2		0x00000040
+#define PERIPH_I2C		0x00000080
+#define PERIPH_JPEG		0x00000100
+#define PERIPH_FSMC		0x00000200
+#define PERIPH_FIRDA		0x00000400
+#define PERIPH_GPT4		0x00000800
+#define PERIPH_GPT5		0x00001000
+#define PERIPH_GPIO4		0x00002000
+#define PERIPH_SSP3		0x00004000
+#define PERIPH_ADC		0x00008000
+#define PERIPH_GPT3		0x00010000
+#define PERIPH_RTC		0x00020000
+#define PERIPH_GPIO3		0x00040000
+#define PERIPH_DMA		0x00080000
+#define PERIPH_ROM		0x00100000
+#define PERIPH_SMI		0x00200000
+#define PERIPH_CLCD		0x00400000
+#define PERIPH_GMAC		0x00800000
+#define PERIPH_USBD		0x01000000
+#define PERIPH_USBH1		0x02000000
+#define PERIPH_USBH2		0x04000000
+#define PERIPH_MPMC		0x08000000
+#define PERIPH_RAMW		0x10000000
+#define PERIPH_MPMC_EN		0x20000000
+#define PERIPH_MPMC_WE		0x40000000
+#define PERIPH_MPMCMSK		0x60000000
+
+#define PERIPH_CLK_ALL		0x0FFFFFF8
+#define PERIPH_RST_ALL		0x00000004
+
+/* DDR_PAD values */
+#define DDR_PAD_CNF_MSK		0x0000ffff
+#define DDR_PAD_SW_CONF		0x00060000
+#define DDR_PAD_SSTL_SEL	0x00000001
+#define DDR_PAD_DRAM_TYPE	0x00008000
+
+/* DDR_COMP values */
+#define DDR_COMP_ACCURATE	0x00000010
+
+/* SoC revision stuff */
+#define SOC_PRI_SHFT		16
+#define SOC_SEC_SHFT		8
+
+/* Revision definitions */
+#define SOC_SPEAR_NA		0
+
+/*
+ * The definitons have started from
+ * 101 for SPEAr6xx
+ * 201 for SPEAr3xx
+ * 301 for SPEAr13xx
+ */
+#define SOC_SPEAR600_AA		101
+#define SOC_SPEAR600_AB		102
+#define SOC_SPEAR600_BA		103
+#define SOC_SPEAR600_BB		104
+#define SOC_SPEAR600_BC		105
+#define SOC_SPEAR600_BD		106
+
+#define SOC_SPEAR300		201
+#define SOC_SPEAR310		202
+#define SOC_SPEAR320		203
+
+extern int get_socrev(void);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_ssp.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_ssp.h
new file mode 100644
index 000000000..b13db573f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_ssp.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SPR_SSP_H
+#define _SPR_SSP_H
+
+struct ssp_regs {
+	u32 sspcr0;
+	u32 sspcr1;
+	u32 sspdr;
+	u32 sspsr;
+	u32 sspcpsr;
+	u32 sspimsc;
+	u32 sspicr;
+	u32 sspdmacr;
+};
+
+#define SSPCR0_FRF_MOT_SPI	0x0000
+#define SSPCR0_DSS_16BITS	0x000f
+
+#define SSPCR1_SSE		0x0002
+
+#define SSPSR_TNF		0x2
+#define SSPSR_TFE		0x1
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_syscntl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_syscntl.h
new file mode 100644
index 000000000..95bd443da
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-spear/spr_syscntl.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2009
+ * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SYSCTRL_H
+#define __SYSCTRL_H
+
+struct syscntl_regs {
+	u32 scctrl;
+	u32 scsysstat;
+	u32 scimctrl;
+	u32 scimsysstat;
+	u32 scxtalctrl;
+	u32 scpllctrl;
+	u32 scpllfctrl;
+	u32 scperctrl0;
+	u32 scperctrl1;
+	u32 scperen;
+	u32 scperdis;
+	const u32 scperclken;
+	const u32 scperstat;
+};
+
+#define MODE_SHIFT          0x00000003
+
+#define NORMAL              0x00000004
+#define SLOW                0x00000002
+#define DOZE                0x00000001
+#define SLEEP               0x00000000
+
+#define PLL_TIM             0x01FFFFFF
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/ap.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/ap.h
new file mode 100644
index 000000000..bc5851c1d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/ap.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2010-2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <asm/types.h>
+
+/* Stabilization delays, in usec */
+#define PLL_STABILIZATION_DELAY	(300)
+#define IO_STABILIZATION_DELAY	(1000)
+
+#define PLLX_ENABLED		(1 << 30)
+#define CCLK_BURST_POLICY	0x20008888
+#define SUPER_CCLK_DIVIDER	0x80000000
+
+/* Calculate clock fractional divider value from ref and target frequencies */
+#define CLK_DIVIDER(REF, FREQ)	((((REF) * 2) / FREQ) - 2)
+
+/* Calculate clock frequency value from reference and clock divider value */
+#define CLK_FREQUENCY(REF, REG)	(((REF) * 2) / (REG + 2))
+
+/* AVP/CPU ID */
+#define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
+#define PG_UP_TAG_0		0x0
+
+#define CORESIGHT_UNLOCK	0xC5ACCE55;
+
+/* AP base physical address of internal SRAM */
+#define NV_PA_BASE_SRAM		0x40000000
+
+#define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
+#define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
+#define CSITE_CPU_DBG1_LAR		(NV_PA_CSITE_BASE + 0x12FB0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS	(NV_PA_FLOW_BASE + 4)
+#define FLOW_MODE_STOP			2
+#define HALT_COP_EVENT_JTAG		(1 << 28)
+#define HALT_COP_EVENT_IRQ_1		(1 << 11)
+#define HALT_COP_EVENT_FIQ_1		(1 << 9)
+
+/* This is the main entry into U-Boot, used by the Cortex-A9 */
+extern void _start(void);
+
+/**
+ * Works out the SOC/SKU type used for clocks settings
+ *
+ * @return	SOC type - see TEGRA_SOC...
+ */
+int tegra_get_chip_sku(void);
+
+/**
+ * Returns the pure SOC (chip ID) from the HIDREV register
+ *
+ * @return	SOC ID - see CHIPID_TEGRAxx...
+ */
+int tegra_get_chip(void);
+
+/**
+ * Returns the SKU ID from the sku_info register
+ *
+ * @return	SKU ID - see SKU_ID_Txx...
+ */
+int tegra_get_sku_info(void);
+
+/* Do any chip-specific cache config */
+void config_cache(void);
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/apb_misc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/apb_misc.h
new file mode 100644
index 000000000..a5bc092ff
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/apb_misc.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _GP_PADCTRL_H_
+#define _GP_PADCTRL_H_
+
+/* APB_MISC_PP registers */
+struct apb_misc_pp_ctlr {
+	u32	reserved0[2];
+	u32	strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
+	u32	reserved1[6];	/* 0x0c .. 0x20 */
+	u32	cfg_ctl;	/* 0x24 */
+};
+
+/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
+#define RAM_CODE_SHIFT		4
+#define RAM_CODE_MASK		(0xf << RAM_CODE_SHIFT)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/board.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/board.h
new file mode 100644
index 000000000..ff773646c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/board.h
@@ -0,0 +1,33 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA_BOARD_H_
+#define _TEGRA_BOARD_H_
+
+/* Set up pinmux to make UART usable */
+void gpio_early_init_uart(void);
+
+/* Set up early UART output */
+void board_init_uart_f(void);
+
+/* Set up any early GPIOs the board might need for proper operation */
+void gpio_early_init(void);  /* overrideable GPIO config        */
+
+/*
+ * Hooks to allow boards to set up the pinmux for a specific function.
+ * Has to be implemented in the board files as we don't yet support pinmux
+ * setup from FTD. If a board file does not implement one of those functions
+ * an empty stub function will be called.
+ */
+
+void pinmux_init(void);      /* overrideable general pinmux setup */
+void pin_mux_usb(void);      /* overrideable USB pinmux setup     */
+void pin_mux_spi(void);      /* overrideable SPI pinmux setup     */
+void pin_mux_nand(void);     /* overrideable NAND pinmux setup    */
+void pin_mux_display(void);  /* overrideable DISPLAY pinmux setup */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clk_rst.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clk_rst.h
new file mode 100644
index 000000000..7d28e16f1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -0,0 +1,443 @@
+/*
+ *  (C) Copyright 2010-2014
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA_CLK_RST_H_
+#define _TEGRA_CLK_RST_H_
+
+/* PLL registers - there are several PLLs in the clock controller */
+struct clk_pll {
+	uint pll_base;		/* the control register */
+	/* pll_out[0] is output A control, pll_out[1] is output B control */
+	uint pll_out[2];
+	uint pll_misc;		/* other misc things */
+};
+
+/* PLL registers - there are several PLLs in the clock controller */
+struct clk_pll_simple {
+	uint pll_base;		/* the control register */
+	uint pll_misc;		/* other misc things */
+};
+
+struct clk_pllm {
+	uint pllm_base;		/* the control register */
+	uint pllm_out;		/* output control */
+	uint pllm_misc1;	/* misc1 */
+	uint pllm_misc2;	/* misc2 */
+};
+
+/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
+struct clk_set_clr {
+	uint set;
+	uint clr;
+};
+
+/*
+ * Most PLLs use the clk_pll structure, but some have a simpler two-member
+ * structure for which we use clk_pll_simple. The reason for this non-
+ * othogonal setup is not stated.
+ */
+enum {
+	TEGRA_CLK_PLLS		= 6,	/* Number of normal PLLs */
+	TEGRA_CLK_SIMPLE_PLLS	= 3,	/* Number of simple PLLs */
+	TEGRA_CLK_REGS		= 3,	/* Number of clock enable regs L/H/U */
+	TEGRA_CLK_SOURCES	= 64,	/* Number of ppl clock sources L/H/U */
+	TEGRA_CLK_REGS_VW	= 2,	/* Number of clock enable regs V/W */
+	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W */
+	TEGRA_CLK_SOURCES_X	= 32,	/* Number of ppl clock sources X */
+};
+
+/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
+struct clk_rst_ctlr {
+	uint crc_rst_src;			/* _RST_SOURCE_0,0x00 */
+	uint crc_rst_dev[TEGRA_CLK_REGS];	/* _RST_DEVICES_L/H/U_0 */
+	uint crc_clk_out_enb[TEGRA_CLK_REGS];	/* _CLK_OUT_ENB_L/H/U_0 */
+	uint crc_reserved0;		/* reserved_0,		0x1C */
+	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0, 0x20 */
+	uint crc_super_cclk_div;	/* _SUPER_CCLK_DIVIDER_0,0x24 */
+	uint crc_sclk_brst_pol;		/* _SCLK_BURST_POLICY_0, 0x28 */
+	uint crc_super_sclk_div;	/* _SUPER_SCLK_DIVIDER_0,0x2C */
+	uint crc_clk_sys_rate;		/* _CLK_SYSTEM_RATE_0,	0x30 */
+	uint crc_prog_dly_clk;		/* _PROG_DLY_CLK_0,	0x34 */
+	uint crc_aud_sync_clk_rate;	/* _AUDIO_SYNC_CLK_RATE_0,0x38 */
+	uint crc_reserved1;		/* reserved_1,		0x3C */
+	uint crc_cop_clk_skip_plcy;	/* _COP_CLK_SKIP_POLICY_0,0x40 */
+	uint crc_clk_mask_arm;		/* _CLK_MASK_ARM_0,	0x44 */
+	uint crc_misc_clk_enb;		/* _MISC_CLK_ENB_0,	0x48 */
+	uint crc_clk_cpu_cmplx;		/* _CLK_CPU_CMPLX_0,	0x4C */
+	uint crc_osc_ctrl;		/* _OSC_CTRL_0,		0x50 */
+	uint crc_pll_lfsr;		/* _PLL_LFSR_0,		0x54 */
+	uint crc_osc_freq_det;		/* _OSC_FREQ_DET_0,	0x58 */
+	uint crc_osc_freq_det_stat;	/* _OSC_FREQ_DET_STATUS_0,0x5C */
+	uint crc_reserved2[8];		/* reserved_2[8],	0x60-7C */
+
+	struct clk_pll crc_pll[TEGRA_CLK_PLLS];	/* PLLs from 0x80 to 0xdc */
+
+	/* PLLs from 0xe0 to 0xf4    */
+	struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
+
+	uint crc_reserved10;		/* _reserved_10,	0xF8 */
+	uint crc_reserved11;		/* _reserved_11,	0xFC */
+
+	uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...	0x100-1fc */
+
+	uint crc_reserved20[32];	/* _reserved_20,	0x200-27c */
+
+	uint crc_clk_out_enb_x;		/* _CLK_OUT_ENB_X_0,	0x280 */
+	uint crc_clk_enb_x_set;		/* _CLK_ENB_X_SET_0,	0x284 */
+	uint crc_clk_enb_x_clr;		/* _CLK_ENB_X_CLR_0,	0x288 */
+
+	uint crc_rst_devices_x;		/* _RST_DEVICES_X_0,	0x28c */
+	uint crc_rst_dev_x_set;		/* _RST_DEV_X_SET_0,	0x290 */
+	uint crc_rst_dev_x_clr;		/* _RST_DEV_X_CLR_0,	0x294 */
+
+	uint crc_reserved21[23];	/* _reserved_21,	0x298-2f0 */
+
+	uint crc_dfll_base;		/* _DFLL_BASE_0,	0x2f4 */
+
+	uint crc_reserved22[2];		/* _reserved_22,	0x2f8-2fc */
+
+	/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
+	struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
+
+	uint crc_reserved30[2];		/* _reserved_30,	0x318, 0x31c */
+
+	/* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
+	struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
+
+	uint crc_reserved31[2];		/* _reserved_31,	0x338, 0x33c */
+
+	uint crc_cpu_cmplx_set;		/* _RST_CPU_CMPLX_SET_0,    0x340 */
+	uint crc_cpu_cmplx_clr;		/* _RST_CPU_CMPLX_CLR_0,    0x344 */
+
+	/* Additional (T30) registers */
+	uint crc_clk_cpu_cmplx_set;	/* _CLK_CPU_CMPLX_SET_0,    0x348 */
+	uint crc_clk_cpu_cmplx_clr;	/* _CLK_CPU_CMPLX_SET_0,    0x34c */
+
+	uint crc_reserved32[2];		/* _reserved_32,      0x350,0x354 */
+
+	uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
+	uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
+	uint crc_cclkg_brst_pol;	/* _CCLKG_BURST_POLICY_0,   0x368 */
+	uint crc_super_cclkg_div;	/* _SUPER_CCLKG_DIVIDER_0,  0x36C */
+	uint crc_cclklp_brst_pol;	/* _CCLKLP_BURST_POLICY_0,  0x370 */
+	uint crc_super_cclkp_div;	/* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
+	uint crc_clk_cpug_cmplx;	/* _CLK_CPUG_CMPLX_0,       0x378 */
+	uint crc_clk_cpulp_cmplx;	/* _CLK_CPULP_CMPLX_0,      0x37C */
+	uint crc_cpu_softrst_ctrl;	/* _CPU_SOFTRST_CTRL_0,     0x380 */
+	uint crc_cpu_softrst_ctrl1;	/* _CPU_SOFTRST_CTRL1_0,    0x384 */
+	uint crc_cpu_softrst_ctrl2;	/* _CPU_SOFTRST_CTRL2_0,    0x388 */
+	uint crc_reserved33[9];		/* _reserved_33,        0x38c-3ac */
+	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW];	/* 0x3B0-0x42C */
+	/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
+	struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
+	/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
+	struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
+	/* Additional (T114) registers */
+	uint crc_rst_cpug_cmplx_set;	/* _RST_CPUG_CMPLX_SET_0,  0x450 */
+	uint crc_rst_cpug_cmplx_clr;	/* _RST_CPUG_CMPLX_CLR_0,  0x454 */
+	uint crc_rst_cpulp_cmplx_set;	/* _RST_CPULP_CMPLX_SET_0, 0x458 */
+	uint crc_rst_cpulp_cmplx_clr;	/* _RST_CPULP_CMPLX_CLR_0, 0x45C */
+	uint crc_clk_cpug_cmplx_set;	/* _CLK_CPUG_CMPLX_SET_0,  0x460 */
+	uint crc_clk_cpug_cmplx_clr;	/* _CLK_CPUG_CMPLX_CLR_0,  0x464 */
+	uint crc_clk_cpulp_cmplx_set;	/* _CLK_CPULP_CMPLX_SET_0, 0x468 */
+	uint crc_clk_cpulp_cmplx_clr;	/* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
+	uint crc_cpu_cmplx_status;	/* _CPU_CMPLX_STATUS_0,    0x470 */
+	uint crc_reserved40[1];		/* _reserved_40,        0x474 */
+	uint crc_intstatus;		/* __INTSTATUS_0,       0x478 */
+	uint crc_intmask;		/* __INTMASK_0,         0x47C */
+	uint crc_utmip_pll_cfg0;	/* _UTMIP_PLL_CFG0_0,	0x480 */
+	uint crc_utmip_pll_cfg1;	/* _UTMIP_PLL_CFG1_0,	0x484 */
+	uint crc_utmip_pll_cfg2;	/* _UTMIP_PLL_CFG2_0,	0x488 */
+
+	uint crc_plle_aux;		/* _PLLE_AUX_0,		0x48C */
+	uint crc_sata_pll_cfg0;		/* _SATA_PLL_CFG0_0,	0x490 */
+	uint crc_sata_pll_cfg1;		/* _SATA_PLL_CFG1_0,	0x494 */
+	uint crc_pcie_pll_cfg0;		/* _PCIE_PLL_CFG0_0,	0x498 */
+
+	uint crc_prog_audio_dly_clk;	/* _PROG_AUDIO_DLY_CLK_0, 0x49C */
+	uint crc_audio_sync_clk_i2s0;	/* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
+	uint crc_audio_sync_clk_i2s1;	/* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
+	uint crc_audio_sync_clk_i2s2;	/* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
+	uint crc_audio_sync_clk_i2s3;	/* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
+	uint crc_audio_sync_clk_i2s4;	/* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
+	uint crc_audio_sync_clk_spdif;	/* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
+
+	uint crc_plld2_base;		/* _PLLD2_BASE_0, 0x4B8 */
+	uint crc_plld2_misc;		/* _PLLD2_MISC_0, 0x4BC */
+	uint crc_utmip_pll_cfg3;	/* _UTMIP_PLL_CFG3_0, 0x4C0 */
+	uint crc_pllrefe_base;		/* _PLLREFE_BASE_0, 0x4C4 */
+	uint crc_pllrefe_misc;		/* _PLLREFE_MISC_0, 0x4C8 */
+	uint crs_reserved_50[7];	/* _reserved_50, 0x4CC-0x4E4 */
+	uint crc_pllc2_base;		/* _PLLC2_BASE_0, 0x4E8 */
+	uint crc_pllc2_misc0;		/* _PLLC2_MISC_0_0, 0x4EC */
+	uint crc_pllc2_misc1;		/* _PLLC2_MISC_1_0, 0x4F0 */
+	uint crc_pllc2_misc2;		/* _PLLC2_MISC_2_0, 0x4F4 */
+	uint crc_pllc2_misc3;		/* _PLLC2_MISC_3_0, 0x4F8 */
+	uint crc_pllc3_base;		/* _PLLC3_BASE_0, 0x4FC */
+	uint crc_pllc3_misc0;		/* _PLLC3_MISC_0_0, 0x500 */
+	uint crc_pllc3_misc1;		/* _PLLC3_MISC_1_0, 0x504 */
+	uint crc_pllc3_misc2;		/* _PLLC3_MISC_2_0, 0x508 */
+	uint crc_pllc3_misc3;		/* _PLLC3_MISC_3_0, 0x50C */
+	uint crc_pllx_misc1;		/* _PLLX_MISC_1_0, 0x510 */
+	uint crc_pllx_misc2;		/* _PLLX_MISC_2_0, 0x514 */
+	uint crc_pllx_misc3;		/* _PLLX_MISC_3_0, 0x518 */
+	uint crc_xusbio_pll_cfg0;	/* _XUSBIO_PLL_CFG0_0, 0x51C */
+	uint crc_xusbio_pll_cfg1;	/* _XUSBIO_PLL_CFG0_1, 0x520 */
+	uint crc_plle_aux1;		/* _PLLE_AUX1_0, 0x524 */
+	uint crc_pllp_reshift;		/* _PLLP_RESHIFT_0, 0x528 */
+	uint crc_utmipll_hw_pwrdn_cfg0;	/* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
+	uint crc_pllu_hw_pwrdn_cfg0;	/* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
+	uint crc_xusb_pll_cfg0;		/* _XUSB_PLL_CFG0_0, 0x534 */
+	uint crc_reserved51[1];		/* _reserved_51, 0x538 */
+	uint crc_clk_cpu_misc;		/* _CLK_CPU_MISC_0, 0x53C */
+	uint crc_clk_cpug_misc;		/* _CLK_CPUG_MISC_0, 0x540 */
+	uint crc_clk_cpulp_misc;	/* _CLK_CPULP_MISC_0, 0x544 */
+	uint crc_pllx_hw_ctrl_cfg;	/* _PLLX_HW_CTRL_CFG_0, 0x548 */
+	uint crc_pllx_sw_ramp_cfg;	/* _PLLX_SW_RAMP_CFG_0, 0x54C */
+	uint crc_pllx_hw_ctrl_status;	/* _PLLX_HW_CTRL_STATUS_0, 0x550 */
+	uint crc_reserved52[1];		/* _reserved_52, 0x554 */
+	uint crc_super_gr3d_clk_div;	/* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
+	uint crc_spare_reg0;		/* _SPARE_REG0_0, 0x55C */
+
+	/* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */
+	uint crc_reserved60[40];	/* _reserved_60, 0x560 - 0x5FC */
+	uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
+};
+
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
+#define CPU3_CLK_STP_SHIFT	11
+#define CPU2_CLK_STP_SHIFT	10
+#define CPU1_CLK_STP_SHIFT	9
+#define CPU0_CLK_STP_SHIFT	8
+#define CPU0_CLK_STP_MASK	(1U << CPU0_CLK_STP_SHIFT)
+
+/* CLK_RST_CONTROLLER_PLLx_BASE_0 */
+#define PLL_BYPASS_SHIFT	31
+#define PLL_BYPASS_MASK		(1U << PLL_BYPASS_SHIFT)
+
+#define PLL_ENABLE_SHIFT	30
+#define PLL_ENABLE_MASK		(1U << PLL_ENABLE_SHIFT)
+
+#define PLL_BASE_OVRRIDE_MASK	(1U << 28)
+
+#define PLL_LOCK_SHIFT		27
+#define PLL_LOCK_MASK		(1U << PLL_LOCK_SHIFT)
+
+#define PLL_DIVP_SHIFT		20
+#define PLL_DIVP_MASK		(7U << PLL_DIVP_SHIFT)
+
+#define PLL_DIVN_SHIFT		8
+#define PLL_DIVN_MASK		(0x3ffU << PLL_DIVN_SHIFT)
+
+#define PLL_DIVM_SHIFT		0
+#define PLL_DIVM_MASK		(0x1f << PLL_DIVM_SHIFT)
+
+/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
+#define PLL_OUT_RSTN		(1 << 0)
+#define PLL_OUT_CLKEN		(1 << 1)
+#define PLL_OUT_OVRRIDE		(1 << 2)
+
+#define PLL_OUT_RATIO_SHIFT	8
+#define PLL_OUT_RATIO_MASK	(0xffU << PLL_OUT_RATIO_SHIFT)
+
+/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
+#define PLL_DCCON_SHIFT		20
+#define PLL_DCCON_MASK		(1U << PLL_DCCON_SHIFT)
+
+#define PLL_LOCK_ENABLE_SHIFT	18
+#define PLL_LOCK_ENABLE_MASK	(1U << PLL_LOCK_ENABLE_SHIFT)
+
+#define PLL_CPCON_SHIFT		8
+#define PLL_CPCON_MASK		(15U << PLL_CPCON_SHIFT)
+
+#define PLL_LFCON_SHIFT		4
+#define PLL_LFCON_MASK		(15U << PLL_LFCON_SHIFT)
+
+#define PLLU_VCO_FREQ_SHIFT	20
+#define PLLU_VCO_FREQ_MASK	(1U << PLLU_VCO_FREQ_SHIFT)
+
+#define PLLP_OUT1_OVR		(1 << 2)
+#define PLLP_OUT2_OVR		(1 << 18)
+#define PLLP_OUT3_OVR		(1 << 2)
+#define PLLP_OUT4_OVR		(1 << 18)
+#define PLLP_OUT1_RATIO		8
+#define PLLP_OUT2_RATIO		24
+#define PLLP_OUT3_RATIO		8
+#define PLLP_OUT4_RATIO		24
+
+enum {
+	IN_408_OUT_204_DIVISOR = 2,
+	IN_408_OUT_102_DIVISOR = 6,
+	IN_408_OUT_48_DIVISOR = 15,
+	IN_408_OUT_9_6_DIVISOR = 83,
+};
+
+#define PLLP_OUT1_RSTN_DIS	(1 << 0)
+#define PLLP_OUT1_RSTN_EN	(0 << 0)
+#define PLLP_OUT1_CLKEN		(1 << 1)
+#define PLLP_OUT2_RSTN_DIS	(1 << 16)
+#define PLLP_OUT2_RSTN_EN	(0 << 16)
+#define PLLP_OUT2_CLKEN		(1 << 17)
+
+#define PLLP_OUT3_RSTN_DIS	(1 << 0)
+#define PLLP_OUT3_RSTN_EN	(0 << 0)
+#define PLLP_OUT3_CLKEN		(1 << 1)
+#define PLLP_OUT4_RSTN_DIS	(1 << 16)
+#define PLLP_OUT4_RSTN_EN	(0 << 16)
+#define PLLP_OUT4_CLKEN		(1 << 17)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
+#define PLLU_POWERDOWN		(1 << 16)
+#define PLL_ENABLE_POWERDOWN	(1 << 14)
+#define PLL_ACTIVE_POWERDOWN	(1 << 12)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN		(1 << 4)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN		(1 << 2)
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN		(1 << 0)
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
+#define OSC_XOE_SHIFT			0
+#define OSC_XOE_MASK			(1 << OSC_XOE_SHIFT)
+#define OSC_XOE_ENABLE			(1 << OSC_XOE_SHIFT)
+#define OSC_XOBP_SHIFT			1
+#define OSC_XOBP_MASK			(1U << OSC_XOBP_SHIFT)
+#define OSC_XOFS_SHIFT			4
+#define OSC_XOFS_MASK			(0x3F << OSC_XOFS_SHIFT)
+#define OSC_DRIVE_STRENGTH		7
+
+/*
+ * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
+ * but can be 16. We could use knowledge we have to restrict the mask in
+ * the 8-bit cases (the divider_bits value returned by
+ * get_periph_clock_source()) but it does not seem worth it since the code
+ * already checks the ranges of values it is writing, in clk_get_divider().
+ */
+#define OUT_CLK_DIVISOR_SHIFT	0
+#define OUT_CLK_DIVISOR_MASK	(0xffff << OUT_CLK_DIVISOR_SHIFT)
+
+#define OUT_CLK_SOURCE_31_30_SHIFT	30
+#define OUT_CLK_SOURCE_31_30_MASK	(3U << OUT_CLK_SOURCE_31_30_SHIFT)
+
+#define OUT_CLK_SOURCE_31_29_SHIFT	29
+#define OUT_CLK_SOURCE_31_29_MASK	(7U << OUT_CLK_SOURCE_31_29_SHIFT)
+
+/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
+#define OUT_CLK_SOURCE_31_28_SHIFT	28
+#define OUT_CLK_SOURCE_31_28_MASK	(15U << OUT_CLK_SOURCE_31_28_SHIFT)
+
+/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
+#define SCLK_SYS_STATE_SHIFT    28U
+#define SCLK_SYS_STATE_MASK     (15U << SCLK_SYS_STATE_SHIFT)
+enum {
+	SCLK_SYS_STATE_STDBY,
+	SCLK_SYS_STATE_IDLE,
+	SCLK_SYS_STATE_RUN,
+	SCLK_SYS_STATE_IRQ = 4U,
+	SCLK_SYS_STATE_FIQ = 8U,
+};
+#define SCLK_COP_FIQ_MASK       (1 << 27)
+#define SCLK_CPU_FIQ_MASK       (1 << 26)
+#define SCLK_COP_IRQ_MASK       (1 << 25)
+#define SCLK_CPU_IRQ_MASK       (1 << 24)
+
+#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT		12
+#define SCLK_SWAKEUP_FIQ_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT		8
+#define SCLK_SWAKEUP_IRQ_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT		4
+#define SCLK_SWAKEUP_RUN_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT		0
+
+#define SCLK_SWAKEUP_IDLE_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+enum {
+	SCLK_SOURCE_CLKM,
+	SCLK_SOURCE_PLLC_OUT1,
+	SCLK_SOURCE_PLLP_OUT4,
+	SCLK_SOURCE_PLLP_OUT3,
+	SCLK_SOURCE_PLLP_OUT2,
+	SCLK_SOURCE_CLKD,
+	SCLK_SOURCE_CLKS,
+	SCLK_SOURCE_PLLM_OUT1,
+};
+#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1    (7 << 12)
+#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1    (7 << 8)
+#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1    (7 << 4)
+#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1   (7 << 0)
+
+/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
+#define SUPER_SCLK_ENB_SHIFT		31U
+#define SUPER_SCLK_ENB_MASK		(1U << 31)
+#define SUPER_SCLK_DIVIDEND_SHIFT	8
+#define SUPER_SCLK_DIVIDEND_MASK	(0xff << SUPER_SCLK_DIVIDEND_SHIFT)
+#define SUPER_SCLK_DIVISOR_SHIFT	0
+#define SUPER_SCLK_DIVISOR_MASK		(0xff << SUPER_SCLK_DIVISOR_SHIFT)
+
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
+#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
+#define CLK_SYS_RATE_HCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
+#define CLK_SYS_RATE_AHB_RATE_SHIFT     4
+#define CLK_SYS_RATE_AHB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
+#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
+#define CLK_SYS_RATE_PCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
+#define CLK_SYS_RATE_APB_RATE_SHIFT     0
+#define CLK_SYS_RATE_APB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
+
+/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
+#define CLR_CPURESET0			(1 << 0)
+#define CLR_CPURESET1			(1 << 1)
+#define CLR_CPURESET2			(1 << 2)
+#define CLR_CPURESET3			(1 << 3)
+#define CLR_DBGRESET0			(1 << 12)
+#define CLR_DBGRESET1			(1 << 13)
+#define CLR_DBGRESET2			(1 << 14)
+#define CLR_DBGRESET3			(1 << 15)
+#define CLR_CORERESET0			(1 << 16)
+#define CLR_CORERESET1			(1 << 17)
+#define CLR_CORERESET2			(1 << 18)
+#define CLR_CORERESET3			(1 << 19)
+#define CLR_CXRESET0			(1 << 20)
+#define CLR_CXRESET1			(1 << 21)
+#define CLR_CXRESET2			(1 << 22)
+#define CLR_CXRESET3			(1 << 23)
+#define CLR_L2RESET			(1 << 24)
+#define CLR_NONCPURESET			(1 << 29)
+#define CLR_PRESETDBG			(1 << 30)
+
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
+#define CLR_CPU0_CLK_STP		(1 << 8)
+#define CLR_CPU1_CLK_STP		(1 << 9)
+#define CLR_CPU2_CLK_STP		(1 << 10)
+#define CLR_CPU3_CLK_STP		(1 << 11)
+
+/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
+#define MSELECT_CLK_SRC_PLLP_OUT0	(0 << 29)
+
+/* CRC_CLK_ENB_V_SET_0 0x440 */
+#define SET_CLK_ENB_CPUG_ENABLE		(1 << 0)
+#define SET_CLK_ENB_CPULP_ENABLE	(1 << 1)
+#define SET_CLK_ENB_MSELECT_ENABLE	(1 << 3)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
+#define PLL_ACTIVE_POWERDOWN		(1 << 12)
+#define PLL_ENABLE_POWERDOWN		(1 << 14)
+#define PLLU_POWERDOWN			(1 << 16)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN	(1 << 0)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN	(1 << 2)
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN	(1 << 4)
+
+/* CLK_RST_CONTROLLER_PLLX_MISC_3 */
+#define PLLX_IDDQ_SHIFT			3
+#define PLLX_IDDQ_MASK			(1U << PLLX_IDDQ_SHIFT)
+
+#endif	/* _TEGRA_CLK_RST_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clock.h
new file mode 100644
index 000000000..9d8114c4e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/clock.h
@@ -0,0 +1,325 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Tegra clock control functions */
+
+#ifndef _TEGRA_CLOCK_H_
+#define _TEGRA_CLOCK_H_
+
+/* Set of oscillator frequencies supported in the internal API. */
+enum clock_osc_freq {
+	/* All in MHz, so 13_0 is 13.0MHz */
+	CLOCK_OSC_FREQ_13_0,
+	CLOCK_OSC_FREQ_19_2,
+	CLOCK_OSC_FREQ_12_0,
+	CLOCK_OSC_FREQ_26_0,
+
+	CLOCK_OSC_FREQ_COUNT,
+};
+
+/*
+ * Note that no Tegra clock register actually uses all of bits 31:28 as
+ * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
+ * those cases, nothing is stored in the bits about the mux field, so it's
+ * safe to pretend that the mux field extends all the way to the end of the
+ * register. As such, the U-Boot clock driver is currently a bit lazy, and
+ * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
+ * them all together and pretends they're all 31:28.
+ */
+enum {
+	MASK_BITS_31_30,
+	MASK_BITS_31_29,
+	MASK_BITS_31_28,
+};
+
+#include <asm/arch/clock-tables.h>
+/* PLL stabilization delay in usec */
+#define CLOCK_PLL_STABLE_DELAY_US 300
+
+/* return the current oscillator clock frequency */
+enum clock_osc_freq clock_get_osc_freq(void);
+
+/**
+ * Start PLL using the provided configuration parameters.
+ *
+ * @param id	clock id
+ * @param divm	input divider
+ * @param divn	feedback divider
+ * @param divp	post divider 2^n
+ * @param cpcon	charge pump setup control
+ * @param lfcon	loop filter setup control
+ *
+ * @returns monotonic time in us that the PLL will be stable
+ */
+unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
+		u32 divp, u32 cpcon, u32 lfcon);
+
+/**
+ * Set PLL output frequency
+ *
+ * @param clkid	clock id
+ * @param pllout	pll output id
+ * @param rate		desired output rate
+ *
+ * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
+ */
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
+		unsigned rate);
+
+/**
+ * Read low-level parameters of a PLL.
+ *
+ * @param id	clock id to read (note: USB is not supported)
+ * @param divm	returns input divider
+ * @param divn	returns feedback divider
+ * @param divp	returns post divider 2^n
+ * @param cpcon	returns charge pump setup control
+ * @param lfcon	returns loop filter setup control
+ *
+ * @returns 0 if ok, -1 on error (invalid clock id)
+ */
+int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
+		u32 *divp, u32 *cpcon, u32 *lfcon);
+
+/*
+ * Enable a clock
+ *
+ * @param id	clock id
+ */
+void clock_enable(enum periph_id clkid);
+
+/*
+ * Disable a clock
+ *
+ * @param id	clock id
+ */
+void clock_disable(enum periph_id clkid);
+
+/*
+ * Set whether a clock is enabled or disabled.
+ *
+ * @param id		clock id
+ * @param enable	1 to enable, 0 to disable
+ */
+void clock_set_enable(enum periph_id clkid, int enable);
+
+/**
+ * Reset a peripheral. This puts it in reset, waits for a delay, then takes
+ * it out of reset and waits for th delay again.
+ *
+ * @param periph_id	peripheral to reset
+ * @param us_delay	time to delay in microseconds
+ */
+void reset_periph(enum periph_id periph_id, int us_delay);
+
+/**
+ * Put a peripheral into or out of reset.
+ *
+ * @param periph_id	peripheral to reset
+ * @param enable	1 to put into reset, 0 to take out of reset
+ */
+void reset_set_enable(enum periph_id periph_id, int enable);
+
+
+/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
+enum crc_reset_id {
+	/* Things we can hold in reset for each CPU */
+	crc_rst_cpu = 1,
+	crc_rst_de = 1 << 4,	/* What is de? */
+	crc_rst_watchdog = 1 << 8,
+	crc_rst_debug = 1 << 12,
+};
+
+/**
+ * Put parts of the CPU complex into or out of reset.\
+ *
+ * @param cpu		cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
+ * @param which		which parts of the complex to affect (OR of crc_reset_id)
+ * @param reset		1 to assert reset, 0 to de-assert
+ */
+void reset_cmplx_set_enable(int cpu, int which, int reset);
+
+/**
+ * Set the source for a peripheral clock. This plus the divisor sets the
+ * clock rate. You need to look up the datasheet to see the meaning of the
+ * source parameter as it changes for each peripheral.
+ *
+ * Warning: This function is only for use pre-relocation. Please use
+ * clock_start_periph_pll() instead.
+ *
+ * @param periph_id	peripheral to adjust
+ * @param source	source clock (0, 1, 2 or 3)
+ */
+void clock_ll_set_source(enum periph_id periph_id, unsigned source);
+
+/**
+ * Set the source and divisor for a peripheral clock. This sets the
+ * clock rate. You need to look up the datasheet to see the meaning of the
+ * source parameter as it changes for each peripheral.
+ *
+ * Warning: This function is only for use pre-relocation. Please use
+ * clock_start_periph_pll() instead.
+ *
+ * @param periph_id	peripheral to adjust
+ * @param source	source clock (0, 1, 2 or 3)
+ * @param divisor	divisor value to use
+ */
+void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
+		unsigned divisor);
+
+/**
+ * Start a peripheral PLL clock at the given rate. This also resets the
+ * peripheral.
+ *
+ * @param periph_id	peripheral to start
+ * @param parent	PLL id of required parent clock
+ * @param rate		Required clock rate in Hz
+ * @return rate selected in Hz, or -1U if something went wrong
+ */
+unsigned clock_start_periph_pll(enum periph_id periph_id,
+		enum clock_id parent, unsigned rate);
+
+/**
+ * Returns the rate of a peripheral clock in Hz. Since the caller almost
+ * certainly knows the parent clock (having just set it) we require that
+ * this be passed in so we don't need to work it out.
+ *
+ * @param periph_id	peripheral to start
+ * @param parent	PLL id of parent clock (used to calculate rate, you
+ *			must know this!)
+ * @return clock rate of peripheral in Hz
+ */
+unsigned long clock_get_periph_rate(enum periph_id periph_id,
+		enum clock_id parent);
+
+/**
+ * Adjust peripheral PLL clock to the given rate. This does not reset the
+ * peripheral. If a second stage divisor is not available, pass NULL for
+ * extra_div. If it is available, then this parameter will return the
+ * divisor selected (which will be a power of 2 from 1 to 256).
+ *
+ * @param periph_id	peripheral to start
+ * @param parent	PLL id of required parent clock
+ * @param rate		Required clock rate in Hz
+ * @param extra_div	value for the second-stage divisor (NULL if one is
+			not available)
+ * @return rate selected in Hz, or -1U if something went wrong
+ */
+unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
+		enum clock_id parent, unsigned rate, int *extra_div);
+
+/**
+ * Returns the clock rate of a specified clock, in Hz.
+ *
+ * @param parent	PLL id of clock to check
+ * @return rate of clock in Hz
+ */
+unsigned clock_get_rate(enum clock_id clkid);
+
+/**
+ * Start up a UART using low-level calls
+ *
+ * Prior to relocation clock_start_periph_pll() cannot be called. This
+ * function provides a way to set up a UART using low-level calls which
+ * do not require BSS.
+ *
+ * @param periph_id	Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
+ */
+void clock_ll_start_uart(enum periph_id periph_id);
+
+/**
+ * Decode a peripheral ID from a device tree node.
+ *
+ * This works by looking up the peripheral's 'clocks' node and reading out
+ * the second cell, which is the clock number / peripheral ID.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Node to look at
+ * @return peripheral ID, or PERIPH_ID_NONE if none
+ */
+enum periph_id clock_decode_periph_id(const void *blob, int node);
+
+/**
+ * Checks if the oscillator bypass is enabled (XOBP bit)
+ *
+ * @return 1 if bypass is enabled, 0 if not
+ */
+int clock_get_osc_bypass(void);
+
+/*
+ * Checks that clocks are valid and prints a warning if not
+ *
+ * @return 0 if ok, -1 on error
+ */
+int clock_verify(void);
+
+/* Initialize the clocks */
+void clock_init(void);
+
+/* Initialize the PLLs */
+void clock_early_init(void);
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id);
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id     peripheral to start
+ * @param source        PLL id of required parent clock
+ * @param mux_bits      Set to number of bits in mux register: 2 or 4
+ * @param divider_bits  Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+		enum clock_id parent, int *mux_bits, int *divider_bits);
+
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id        Clock ID according to tegra30 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id);
+
+/**
+ * Set the output frequency you want for each PLL clock.
+ * PLL output frequencies are programmed by setting their N, M and P values.
+ * The governing equations are:
+ *     VCO = (Fi / m) * n, Fo = VCO / (2^p)
+ *     where Fo is the output frequency from the PLL.
+ * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
+ *     216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
+ * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
+ *
+ * @param n PLL feedback divider(DIVN)
+ * @param m PLL input divider(DIVN)
+ * @param p post divider(DIVP)
+ * @param cpcon base PLL charge pump(CPCON)
+ * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
+ *              be overriden), 1 if PLL is already correct
+ */
+int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
+
+/* return 1 if a peripheral ID is in range */
+#define clock_type_id_isvalid(id) ((id) >= 0 && \
+		(id) < CLOCK_TYPE_COUNT)
+
+/* return 1 if a periphc_internal_id is in range */
+#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
+		(id) < PERIPHC_COUNT)
+
+/* SoC-specific TSC init */
+void arch_timer_init(void);
+
+void tegra30_set_up_pllp(void);
+
+#endif  /* _TEGRA_CLOCK_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/funcmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/funcmux.h
new file mode 100644
index 000000000..f101e5ef6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/funcmux.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra high-level function multiplexing */
+
+#ifndef _TEGRA_FUNCMUX_H_
+#define _TEGRA_FUNCMUX_H_
+
+/**
+ * Select a config for a particular peripheral.
+ *
+ * Each peripheral can operate through a number of configurations,
+ * which are sets of pins that it uses to bring out its signals.
+ * The basic config is 0, and higher numbers indicate different
+ * pinmux settings to bring the peripheral out on other pins,
+ *
+ * This function also disables tristate for the function's pins,
+ * so that they operate in normal mode.
+ *
+ * @param id		Peripheral id
+ * @param config	Configuration to use (FUNCMUX_...), 0 for default
+ * @return 0 if ok, -1 on error (e.g. incorrect id or config)
+ */
+int funcmux_select(enum periph_id id, int config);
+
+#endif	/* _TEGRA_FUNCMUX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/fuse.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/fuse.h
new file mode 100644
index 000000000..39b578c00
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/fuse.h
@@ -0,0 +1,23 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FUSE_H_
+#define _FUSE_H_
+
+/* FUSE registers */
+struct fuse_regs {
+	u32 reserved0[64];		/* 0x00 - 0xFC: */
+	u32 production_mode;		/* 0x100: FUSE_PRODUCTION_MODE */
+	u32 reserved1[3];		/* 0x104 - 0x10c: */
+	u32 sku_info;			/* 0x110 */
+	u32 reserved2[13];		/* 0x114 - 0x144: */
+	u32 fa;				/* 0x148: FUSE_FA */
+	u32 reserved3[21];		/* 0x14C - 0x19C: */
+	u32 security_mode;		/* 0x1A0: FUSE_SECURITY_MODE */
+};
+
+#endif	/* ifndef _FUSE_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gp_padctrl.h
new file mode 100644
index 000000000..7a86acb1b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gp_padctrl.h
@@ -0,0 +1,25 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA_GP_PADCTRL_H_
+#define _TEGRA_GP_PADCTRL_H_
+
+#define GP_HIDREV			0x804
+
+/* bit fields definitions for APB_MISC_GP_HIDREV register */
+#define HIDREV_CHIPID_SHIFT		8
+#define HIDREV_CHIPID_MASK		(0xff << HIDREV_CHIPID_SHIFT)
+#define HIDREV_MAJORPREV_SHIFT		4
+#define HIDREV_MAJORPREV_MASK		(0xf << HIDREV_MAJORPREV_SHIFT)
+
+/* CHIPID field returned from APB_MISC_GP_HIDREV register */
+#define CHIPID_TEGRA20			0x20
+#define CHIPID_TEGRA30			0x30
+#define CHIPID_TEGRA114			0x35
+#define CHIPID_TEGRA124			0x40
+
+#endif	/* _TEGRA_GP_PADCTRL_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gpio.h
new file mode 100644
index 000000000..d97190dd7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/gpio.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA_GPIO_H_
+#define _TEGRA_GPIO_H_
+
+#define MAX_NUM_GPIOS           (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
+#define GPIO_NAME_SIZE		20	/* gpio_request max label len */
+
+#define GPIO_BANK(x)		((x) >> 5)
+#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
+#define GPIO_FULLPORT(x)	((x) >> 3)
+#define GPIO_BIT(x)		((x) & 0x7)
+
+/*
+ * Tegra-specific GPIO API
+ */
+
+void gpio_info(void);
+
+#define gpio_status()	gpio_info()
+#endif	/* TEGRA_GPIO_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/mmc.h
new file mode 100644
index 000000000..c2d52b297
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/mmc.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA_MMC_H_
+#define _TEGRA_MMC_H_
+
+void tegra_mmc_init(void);
+
+#endif /* _TEGRA_MMC_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pinmux.h
new file mode 100644
index 000000000..035159d66
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -0,0 +1,185 @@
+/*
+ * (C) Copyright 2010-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA_PINMUX_H_
+#define _TEGRA_PINMUX_H_
+
+#include <asm/arch/tegra.h>
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+	PMUX_PULL_NORMAL = 0,
+	PMUX_PULL_DOWN,
+	PMUX_PULL_UP,
+};
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+	PMUX_TRI_NORMAL = 0,
+	PMUX_TRI_TRISTATE = 1,
+};
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+enum pmux_pin_io {
+	PMUX_PIN_OUTPUT = 0,
+	PMUX_PIN_INPUT = 1,
+	PMUX_PIN_NONE,
+};
+
+enum pmux_pin_lock {
+	PMUX_PIN_LOCK_DEFAULT = 0,
+	PMUX_PIN_LOCK_DISABLE,
+	PMUX_PIN_LOCK_ENABLE,
+};
+
+enum pmux_pin_od {
+	PMUX_PIN_OD_DEFAULT = 0,
+	PMUX_PIN_OD_DISABLE,
+	PMUX_PIN_OD_ENABLE,
+};
+
+enum pmux_pin_ioreset {
+	PMUX_PIN_IO_RESET_DEFAULT = 0,
+	PMUX_PIN_IO_RESET_DISABLE,
+	PMUX_PIN_IO_RESET_ENABLE,
+};
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+enum pmux_pin_rcv_sel {
+	PMUX_PIN_RCV_SEL_DEFAULT = 0,
+	PMUX_PIN_RCV_SEL_NORMAL,
+	PMUX_PIN_RCV_SEL_HIGH,
+};
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pmux_pingrp_config {
+	u32 pingrp:16;		/* pin group PMUX_PINGRP_...        */
+	u32 func:8;		/* function to assign PMUX_FUNC_... */
+	u32 pull:2;		/* pull up/down/normal PMUX_PULL_...*/
+	u32 tristate:2;		/* tristate or normal PMUX_TRI_...  */
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+	u32 io:2;		/* input or output PMUX_PIN_...     */
+	u32 lock:2;		/* lock enable/disable PMUX_PIN...  */
+	u32 od:2;		/* open-drain or push-pull driver   */
+	u32 ioreset:2;		/* input/output reset PMUX_PIN...   */
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+	u32 rcv_sel:2;		/* select between High and Normal  */
+				/* VIL/VIH receivers */
+#endif
+#endif
+};
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+#endif
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config	List of config items
+ * @param len		Number of config items in list
+ */
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+				int len);
+
+#ifdef TEGRA_PMX_HAS_DRVGRPS
+
+#define PMUX_SLWF_MIN	0
+#define PMUX_SLWF_MAX	3
+#define PMUX_SLWF_NONE	-1
+
+#define PMUX_SLWR_MIN	0
+#define PMUX_SLWR_MAX	3
+#define PMUX_SLWR_NONE	-1
+
+#define PMUX_DRVUP_MIN	0
+#define PMUX_DRVUP_MAX	127
+#define PMUX_DRVUP_NONE	-1
+
+#define PMUX_DRVDN_MIN	0
+#define PMUX_DRVDN_MAX	127
+#define PMUX_DRVDN_NONE	-1
+
+/* Defines a pin group cfg's low-power mode select */
+enum pmux_lpmd {
+	PMUX_LPMD_X8 = 0,
+	PMUX_LPMD_X4,
+	PMUX_LPMD_X2,
+	PMUX_LPMD_X,
+	PMUX_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pmux_schmt {
+	PMUX_SCHMT_DISABLE = 0,
+	PMUX_SCHMT_ENABLE = 1,
+	PMUX_SCHMT_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pmux_hsm {
+	PMUX_HSM_DISABLE = 0,
+	PMUX_HSM_ENABLE = 1,
+	PMUX_HSM_NONE = -1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct pmux_drvgrp_config {
+	u32 drvgrp:16;	/* pin group PMUX_DRVGRP_x   */
+	u32 slwf:3;		/* falling edge slew         */
+	u32 slwr:3;		/* rising edge slew          */
+	u32 drvup:8;		/* pull-up drive strength    */
+	u32 drvdn:8;		/* pull-down drive strength  */
+	u32 lpmd:3;		/* low-power mode selection  */
+	u32 schmt:2;		/* schmidt enable            */
+	u32 hsm:2;		/* high-speed mode enable    */
+};
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config	List of config items
+ * @param len		Number of config items in list
+ */
+void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
+				int len);
+
+#endif /* TEGRA_PMX_HAS_DRVGRPS */
+
+struct pmux_pingrp_desc {
+	u8 funcs[4];
+#if defined(CONFIG_TEGRA20)
+	u8 ctl_id;
+	u8 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+
+#endif /* _TEGRA_PINMUX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pmc.h
new file mode 100644
index 000000000..1dd3154fb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/pmc.h
@@ -0,0 +1,391 @@
+/*
+ *  (C) Copyright 2010,2011,2014
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PMC_H_
+#define _PMC_H_
+
+/* Power Management Controller (APBDEV_PMC_) registers */
+struct pmc_ctlr {
+	uint pmc_cntrl;			/* _CNTRL_0, offset 00 */
+	uint pmc_sec_disable;		/* _SEC_DISABLE_0, offset 04 */
+	uint pmc_pmc_swrst;		/* _PMC_SWRST_0, offset 08 */
+	uint pmc_wake_mask;		/* _WAKE_MASK_0, offset 0C */
+	uint pmc_wake_lvl;		/* _WAKE_LVL_0, offset 10 */
+	uint pmc_wake_status;		/* _WAKE_STATUS_0, offset 14 */
+	uint pmc_sw_wake_status;	/* _SW_WAKE_STATUS_0, offset 18 */
+	uint pmc_dpd_pads_oride;	/* _DPD_PADS_ORIDE_0, offset 1C */
+	uint pmc_dpd_sample;		/* _DPD_PADS_SAMPLE_0, offset 20 */
+	uint pmc_dpd_enable;		/* _DPD_PADS_ENABLE_0, offset 24 */
+	uint pmc_pwrgate_timer_off;	/* _PWRGATE_TIMER_OFF_0, offset 28 */
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
+	uint pmc_pwrgate_timer_on;	/* _PWRGATE_TIMER_ON_0, offset 2C */
+#else
+	uint pmc_clamp_status;		/* _CLAMP_STATUS_0, offset 2C */
+#endif
+	uint pmc_pwrgate_toggle;	/* _PWRGATE_TOGGLE_0, offset 30 */
+	uint pmc_remove_clamping;	/* _REMOVE_CLAMPING_CMD_0, offset 34 */
+	uint pmc_pwrgate_status;	/* _PWRGATE_STATUS_0, offset 38 */
+	uint pmc_pwrgood_timer;		/* _PWRGOOD_TIMER_0, offset 3C */
+	uint pmc_blink_timer;		/* _BLINK_TIMER_0, offset 40 */
+	uint pmc_no_iopower;		/* _NO_IOPOWER_0, offset 44 */
+	uint pmc_pwr_det;		/* _PWR_DET_0, offset 48 */
+	uint pmc_pwr_det_latch;		/* _PWR_DET_LATCH_0, offset 4C */
+
+	uint pmc_scratch0;		/* _SCRATCH0_0, offset 50 */
+	uint pmc_scratch1;		/* _SCRATCH1_0, offset 54 */
+	uint pmc_scratch2;		/* _SCRATCH2_0, offset 58 */
+	uint pmc_scratch3;		/* _SCRATCH3_0, offset 5C */
+	uint pmc_scratch4;		/* _SCRATCH4_0, offset 60 */
+	uint pmc_scratch5;		/* _SCRATCH5_0, offset 64 */
+	uint pmc_scratch6;		/* _SCRATCH6_0, offset 68 */
+	uint pmc_scratch7;		/* _SCRATCH7_0, offset 6C */
+	uint pmc_scratch8;		/* _SCRATCH8_0, offset 70 */
+	uint pmc_scratch9;		/* _SCRATCH9_0, offset 74 */
+	uint pmc_scratch10;		/* _SCRATCH10_0, offset 78 */
+	uint pmc_scratch11;		/* _SCRATCH11_0, offset 7C */
+	uint pmc_scratch12;		/* _SCRATCH12_0, offset 80 */
+	uint pmc_scratch13;		/* _SCRATCH13_0, offset 84 */
+	uint pmc_scratch14;		/* _SCRATCH14_0, offset 88 */
+	uint pmc_scratch15;		/* _SCRATCH15_0, offset 8C */
+	uint pmc_scratch16;		/* _SCRATCH16_0, offset 90 */
+	uint pmc_scratch17;		/* _SCRATCH17_0, offset 94 */
+	uint pmc_scratch18;		/* _SCRATCH18_0, offset 98 */
+	uint pmc_scratch19;		/* _SCRATCH19_0, offset 9C */
+	uint pmc_scratch20;		/* _SCRATCH20_0, offset A0 */
+	uint pmc_scratch21;		/* _SCRATCH21_0, offset A4 */
+	uint pmc_scratch22;		/* _SCRATCH22_0, offset A8 */
+	uint pmc_scratch23;		/* _SCRATCH23_0, offset AC */
+
+	uint pmc_secure_scratch0;	/* _SECURE_SCRATCH0_0, offset B0 */
+	uint pmc_secure_scratch1;	/* _SECURE_SCRATCH1_0, offset B4 */
+	uint pmc_secure_scratch2;	/* _SECURE_SCRATCH2_0, offset B8 */
+	uint pmc_secure_scratch3;	/* _SECURE_SCRATCH3_0, offset BC */
+	uint pmc_secure_scratch4;	/* _SECURE_SCRATCH4_0, offset C0 */
+	uint pmc_secure_scratch5;	/* _SECURE_SCRATCH5_0, offset C4 */
+
+	uint pmc_cpupwrgood_timer;	/* _CPUPWRGOOD_TIMER_0, offset C8 */
+	uint pmc_cpupwroff_timer;	/* _CPUPWROFF_TIMER_0, offset CC */
+	uint pmc_pg_mask;		/* _PG_MASK_0, offset D0 */
+	uint pmc_pg_mask_1;		/* _PG_MASK_1_0, offset D4 */
+	uint pmc_auto_wake_lvl;		/* _AUTO_WAKE_LVL_0, offset D8 */
+	uint pmc_auto_wake_lvl_mask;	/* _AUTO_WAKE_LVL_MASK_0, offset DC */
+	uint pmc_wake_delay;		/* _WAKE_DELAY_0, offset E0 */
+	uint pmc_pwr_det_val;		/* _PWR_DET_VAL_0, offset E4 */
+	uint pmc_ddr_pwr;		/* _DDR_PWR_0, offset E8 */
+	uint pmc_usb_debounce_del;	/* _USB_DEBOUNCE_DEL_0, offset EC */
+	uint pmc_usb_ao;		/* _USB_AO_0, offset F0 */
+	uint pmc_crypto_op;		/* _CRYPTO_OP__0, offset F4 */
+	uint pmc_pllp_wb0_override;	/* _PLLP_WB0_OVERRIDE_0, offset F8 */
+
+	uint pmc_scratch24;		/* _SCRATCH24_0, offset FC */
+	uint pmc_scratch25;		/* _SCRATCH24_0, offset 100 */
+	uint pmc_scratch26;		/* _SCRATCH24_0, offset 104 */
+	uint pmc_scratch27;		/* _SCRATCH24_0, offset 108 */
+	uint pmc_scratch28;		/* _SCRATCH24_0, offset 10C */
+	uint pmc_scratch29;		/* _SCRATCH24_0, offset 110 */
+	uint pmc_scratch30;		/* _SCRATCH24_0, offset 114 */
+	uint pmc_scratch31;		/* _SCRATCH24_0, offset 118 */
+	uint pmc_scratch32;		/* _SCRATCH24_0, offset 11C */
+	uint pmc_scratch33;		/* _SCRATCH24_0, offset 120 */
+	uint pmc_scratch34;		/* _SCRATCH24_0, offset 124 */
+	uint pmc_scratch35;		/* _SCRATCH24_0, offset 128 */
+	uint pmc_scratch36;		/* _SCRATCH24_0, offset 12C */
+	uint pmc_scratch37;		/* _SCRATCH24_0, offset 130 */
+	uint pmc_scratch38;		/* _SCRATCH24_0, offset 134 */
+	uint pmc_scratch39;		/* _SCRATCH24_0, offset 138 */
+	uint pmc_scratch40;		/* _SCRATCH24_0, offset 13C */
+	uint pmc_scratch41;		/* _SCRATCH24_0, offset 140 */
+	uint pmc_scratch42;		/* _SCRATCH24_0, offset 144 */
+
+	uint pmc_bo_mirror0;		/* _BOUNDOUT_MIRROR0_0, offset 148 */
+	uint pmc_bo_mirror1;		/* _BOUNDOUT_MIRROR1_0, offset 14C */
+	uint pmc_bo_mirror2;		/* _BOUNDOUT_MIRROR2_0, offset 150 */
+	uint pmc_sys_33v_en;		/* _SYS_33V_EN_0, offset 154 */
+	uint pmc_bo_mirror_access;	/* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
+	uint pmc_gate;			/* _GATE_0, offset 15C */
+	/* The following fields are in Tegra124 and later only */
+	uint pmc_wake2_mask;		/* _WAKE2_MASK_0, offset 160 */
+	uint pmc_wake2_lvl;		/* _WAKE2_LVL_0,  offset 164 */
+	uint pmc_wake2_stat;		/* _WAKE2_STATUS_0, offset 168 */
+	uint pmc_sw_wake2_stat;		/* _SW_WAKE2_STATUS_0, offset 16C */
+	uint pmc_auto_wake2_lvl_mask;	/* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
+	uint pmc_pg_mask2;		/* _PG_MASK_2_0, offset 174 */
+	uint pmc_pg_mask_ce1;		/* _PG_MASK_CE1_0, offset 178 */
+	uint pmc_pg_mask_ce2;		/* _PG_MASK_CE2_0, offset 17C */
+	uint pmc_pg_mask_ce3;		/* _PG_MASK_CE3_0, offset 180 */
+	uint pmc_pwrgate_timer_ce0;	/* _PWRGATE_TIMER_CE_0_0, offset 184 */
+	uint pmc_pwrgate_timer_ce1;	/* _PWRGATE_TIMER_CE_1_0, offset 188 */
+	uint pmc_pwrgate_timer_ce2;	/* _PWRGATE_TIMER_CE_2_0, offset 18C */
+	uint pmc_pwrgate_timer_ce3;	/* _PWRGATE_TIMER_CE_3_0, offset 190 */
+	uint pmc_pwrgate_timer_ce4;	/* _PWRGATE_TIMER_CE_4_0, offset 194 */
+	uint pmc_pwrgate_timer_ce5;	/* _PWRGATE_TIMER_CE_5_0, offset 198 */
+	uint pmc_pwrgate_timer_ce6;	/* _PWRGATE_TIMER_CE_6_0, offset 19C */
+	uint pmc_pcx_edpd_cntrl;	/* _PCX_EDPD_CNTRL_0, offset 1A0 */
+	uint pmc_osc_edpd_over;		/* _OSC_EDPD_OVER_0, offset 1A4 */
+	uint pmc_clk_out_cntrl;		/* _CLK_OUT_CNTRL_0, offset 1A8 */
+	uint pmc_sata_pwrgate;		/* _SATA_PWRGT_0, offset 1AC */
+	uint pmc_sensor_ctrl;		/* _SENSOR_CTRL_0, offset 1B0 */
+	uint pmc_reset_status;		/* _RTS_STATUS_0, offset 1B4 */
+	uint pmc_io_dpd_req;		/* _IO_DPD_REQ_0, offset 1B8 */
+	uint pmc_io_dpd_stat;		/* _IO_DPD_STATUS_0, offset 1BC */
+	uint pmc_io_dpd2_req;		/* _IO_DPD2_REQ_0, offset 1C0 */
+	uint pmc_io_dpd2_stat;		/* _IO_DPD2_STATUS_0, offset 1C4 */
+	uint pmc_sel_dpd_tim;		/* _SEL_DPD_TIM_0, offset 1C8 */
+	uint pmc_vddp_sel;		/* _VDDP_SEL_0, offset 1CC */
+
+	uint pmc_ddr_cfg;		/* _DDR_CFG_0, offset 1D0 */
+	uint pmc_e_no_vttgen;		/* _E_NO_VTTGEN_0, offset 1D4 */
+	uint pmc_reserved0;		/* _RESERVED, offset 1D8 */
+	uint pmc_pllm_wb0_ovrride_frq;	/* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
+	uint pmc_test_pwrgate;		/* _TEST_PWRGATE_0, offset 1E0 */
+	uint pmc_pwrgate_timer_mult;	/* _PWRGATE_TIMER_MULT_0, offset 1E4 */
+	uint pmc_dsi_sel_dpd;		/* _DSI_SEL_DPD_0, offset 1E8 */
+	uint pmc_utmip_uhsic_triggers;	/* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
+	uint pmc_utmip_uhsic_saved_st;  /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
+	uint pmc_utmip_pad_cfg;		/* _UTMIP_PAD_CFG_0, offset 1F4 */
+	uint pmc_utmip_term_pad_cfg;	/* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
+	uint pmc_utmip_uhsic_sleep_cfg;	/* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
+
+	uint pmc_todo_0[9];		/* offset 200-220 */
+	uint pmc_secure_scratch6;	/* _SECURE_SCRATCH6_0, offset 224 */
+	uint pmc_secure_scratch7;	/* _SECURE_SCRATCH7_0, offset 228 */
+	uint pmc_scratch43;		/* _SCRATCH43_0, offset 22C */
+	uint pmc_scratch44;		/* _SCRATCH44_0, offset 230 */
+	uint pmc_scratch45;
+	uint pmc_scratch46;
+	uint pmc_scratch47;
+	uint pmc_scratch48;
+	uint pmc_scratch49;
+	uint pmc_scratch50;
+	uint pmc_scratch51;
+	uint pmc_scratch52;
+	uint pmc_scratch53;
+	uint pmc_scratch54;
+	uint pmc_scratch55;		/* _SCRATCH55_0, offset 25C */
+	uint pmc_scratch0_eco;		/* _SCRATCH0_ECO_0, offset 260 */
+	uint pmc_por_dpd_ctrl;		/* _POR_DPD_CTRL_0, offset 264 */
+	uint pmc_scratch2_eco;		/* _SCRATCH2_ECO_0, offset 268 */
+	uint pmc_todo_1[17];		/* TODO: 26C ~ 2AC */
+	uint pmc_pllm_wb0_override2;	/* _PLLM_WB0_OVERRIDE2, offset 2B0 */
+	uint pmc_tsc_mult;		/* _TSC_MULT_0, offset 2B4 */
+	uint pmc_cpu_vsense_override;	/* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
+	uint pmc_glb_amap_cfg;		/* _GLB_AMAP_CFG_0, offset 2BC */
+	uint pmc_sticky_bits;		/* _STICKY_BITS_0, offset 2C0 */
+	uint pmc_sec_disable2;		/* _SEC_DISALBE2, offset 2C4 */
+	uint pmc_weak_bias;		/* _WEAK_BIAS_0, offset 2C8 */
+	uint pmc_todo_3[13];		/* TODO: 2CC ~ 2FC */
+	uint pmc_secure_scratch8;	/* _SECURE_SCRATCH8_0, offset 300 */
+	uint pmc_secure_scratch9;
+	uint pmc_secure_scratch10;
+	uint pmc_secure_scratch11;
+	uint pmc_secure_scratch12;
+	uint pmc_secure_scratch13;
+	uint pmc_secure_scratch14;
+	uint pmc_secure_scratch15;
+	uint pmc_secure_scratch16;
+	uint pmc_secure_scratch17;
+	uint pmc_secure_scratch18;
+	uint pmc_secure_scratch19;
+	uint pmc_secure_scratch20;
+	uint pmc_secure_scratch21;
+	uint pmc_secure_scratch22;
+	uint pmc_secure_scratch23;
+	uint pmc_secure_scratch24;	/* _SECURE_SCRATCH24_0, offset 340 */
+	uint pmc_secure_scratch25;
+	uint pmc_secure_scratch26;
+	uint pmc_secure_scratch27;
+	uint pmc_secure_scratch28;
+	uint pmc_secure_scratch29;
+	uint pmc_secure_scratch30;
+	uint pmc_secure_scratch31;
+	uint pmc_secure_scratch32;
+	uint pmc_secure_scratch33;
+	uint pmc_secure_scratch34;
+	uint pmc_secure_scratch35;	/* _SECURE_SCRATCH35_0, offset 36C */
+
+	uint pmc_reserved1[52];		/* RESERVED: 370 ~ 43C */
+	uint pmc_cntrl2;		/* _CNTRL2_0, offset 440 */
+	uint pmc_reserved2[6];		/* RESERVED: 444 ~ 458 */
+	uint pmc_io_dpd3_req;		/* _IO_DPD3_REQ_0, offset 45c */
+	uint pmc_io_dpd3_stat;		/* _IO_DPD3_STATUS_0, offset 460 */
+	uint pmc_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 464 */
+	uint pmc_reserved3[102];	/* RESERVED: 468 ~ 5FC */
+
+	uint pmc_scratch56;		/* _SCRATCH56_0, offset 600 */
+	uint pmc_scratch57;
+	uint pmc_scratch58;
+	uint pmc_scratch59;
+	uint pmc_scratch60;
+	uint pmc_scratch61;
+	uint pmc_scratch62;
+	uint pmc_scratch63;
+	uint pmc_scratch64;
+	uint pmc_scratch65;
+	uint pmc_scratch66;
+	uint pmc_scratch67;
+	uint pmc_scratch68;
+	uint pmc_scratch69;
+	uint pmc_scratch70;
+	uint pmc_scratch71;
+	uint pmc_scratch72;
+	uint pmc_scratch73;
+	uint pmc_scratch74;
+	uint pmc_scratch75;
+	uint pmc_scratch76;
+	uint pmc_scratch77;
+	uint pmc_scratch78;
+	uint pmc_scratch79;
+	uint pmc_scratch80;
+	uint pmc_scratch81;
+	uint pmc_scratch82;
+	uint pmc_scratch83;
+	uint pmc_scratch84;
+	uint pmc_scratch85;
+	uint pmc_scratch86;
+	uint pmc_scratch87;
+	uint pmc_scratch88;
+	uint pmc_scratch89;
+	uint pmc_scratch90;
+	uint pmc_scratch91;
+	uint pmc_scratch92;
+	uint pmc_scratch93;
+	uint pmc_scratch94;
+	uint pmc_scratch95;
+	uint pmc_scratch96;
+	uint pmc_scratch97;
+	uint pmc_scratch98;
+	uint pmc_scratch99;
+	uint pmc_scratch100;
+	uint pmc_scratch101;
+	uint pmc_scratch102;
+	uint pmc_scratch103;
+	uint pmc_scratch104;
+	uint pmc_scratch105;
+	uint pmc_scratch106;
+	uint pmc_scratch107;
+	uint pmc_scratch108;
+	uint pmc_scratch109;
+	uint pmc_scratch110;
+	uint pmc_scratch111;
+	uint pmc_scratch112;
+	uint pmc_scratch113;
+	uint pmc_scratch114;
+	uint pmc_scratch115;
+	uint pmc_scratch116;
+	uint pmc_scratch117;
+	uint pmc_scratch118;
+	uint pmc_scratch119;
+	uint pmc_scratch1_eco;	/* offset 700 */
+};
+
+#define CPU_PWRED	1
+#define CPU_CLMP	1
+
+#define PARTID_CP	0xFFFFFFF8
+#define START_CP	(1 << 8)
+
+#define CPUPWRREQ_OE	(1 << 16)
+#define CPUPWRREQ_POL	(1 << 15)
+
+#define CRAIL		0
+#define CE0		14
+#define C0NC		15
+
+#define PMC_XOFS_SHIFT	1
+#define PMC_XOFS_MASK	(0x3F << PMC_XOFS_SHIFT)
+
+#if defined(CONFIG_TEGRA114)
+#define TIMER_MULT_SHIFT	0
+#define TIMER_MULT_MASK		(3 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT	2
+#define TIMER_MULT_CPU_MASK	(3 << TIMER_MULT_CPU_SHIFT)
+#elif defined(CONFIG_TEGRA124)
+#define TIMER_MULT_SHIFT	0
+#define TIMER_MULT_MASK		(7 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT	3
+#define TIMER_MULT_CPU_MASK	(7 << TIMER_MULT_CPU_SHIFT)
+#endif
+
+#define MULT_1			0
+#define MULT_2			1
+#define MULT_4			2
+#define MULT_8			3
+#if defined(CONFIG_TEGRA124)
+#define MULT_16			4
+#endif
+
+#define AMAP_WRITE_SHIFT	20
+#define AMAP_WRITE_ON		(1 << AMAP_WRITE_SHIFT)
+
+/* SEC_DISABLE_0, 0x04 */
+#define SEC_DISABLE_WRITE0_ON			(1 << 4)
+#define SEC_DISABLE_READ0_ON			(1 << 5)
+#define SEC_DISABLE_WRITE1_ON			(1 << 6)
+#define SEC_DISABLE_READ1_ON			(1 << 7)
+#define SEC_DISABLE_WRITE2_ON			(1 << 8)
+#define SEC_DISABLE_READ2_ON			(1 << 9)
+#define SEC_DISABLE_WRITE3_ON			(1 << 10)
+#define SEC_DISABLE_READ3_ON			(1 << 11)
+#define SEC_DISABLE_AMAP_WRITE_ON		(1 << 20)
+
+/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
+#define PWRGATE_TOGGLE_PARTID_CRAIL		0
+#define PWRGATE_TOGGLE_PARTID_TD		1
+#define PWRGATE_TOGGLE_PARTID_VE		2
+#define PWRGATE_TOGGLE_PARTID_PCX		3
+#define PWRGATE_TOGGLE_PARTID_VDE		4
+#define PWRGATE_TOGGLE_PARTID_L2C		5
+#define PWRGATE_TOGGLE_PARTID_MPE		6
+#define PWRGATE_TOGGLE_PARTID_HEG		7
+#define PWRGATE_TOGGLE_PARTID_SAX		8
+#define PWRGATE_TOGGLE_PARTID_CE1		9
+#define PWRGATE_TOGGLE_PARTID_CE2		10
+#define PWRGATE_TOGGLE_PARTID_CE3		11
+#define PWRGATE_TOGGLE_PARTID_CELP		12
+#define PWRGATE_TOGGLE_PARTID_CE0		14
+#define PWRGATE_TOGGLE_PARTID_C0NC		15
+#define PWRGATE_TOGGLE_PARTID_C1NC		16
+#define PWRGATE_TOGGLE_PARTID_SOR		17
+#define PWRGATE_TOGGLE_PARTID_DIS		18
+#define PWRGATE_TOGGLE_PARTID_DISB		19
+#define PWRGATE_TOGGLE_PARTID_XUSBA		20
+#define PWRGATE_TOGGLE_PARTID_XUSBB		21
+#define PWRGATE_TOGGLE_PARTID_XUSBC		22
+#define PWRGATE_TOGGLE_PARTID_VIC		23
+#define PWRGATE_TOGGLE_PARTID_IRAM		24
+#define PWRGATE_TOGGLE_START			(1 << 8)
+
+/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */
+#define PWRGATE_STATUS_CRAIL_ENABLE		(1 << 0)
+#define PWRGATE_STATUS_TD_ENABLE		(1 << 1)
+#define PWRGATE_STATUS_VE_ENABLE		(1 << 2)
+#define PWRGATE_STATUS_PCX_ENABLE		(1 << 3)
+#define PWRGATE_STATUS_VDE_ENABLE		(1 << 4)
+#define PWRGATE_STATUS_L2C_ENABLE		(1 << 5)
+#define PWRGATE_STATUS_MPE_ENABLE		(1 << 6)
+#define PWRGATE_STATUS_HEG_ENABLE		(1 << 7)
+#define PWRGATE_STATUS_SAX_ENABLE		(1 << 8)
+#define PWRGATE_STATUS_CE1_ENABLE		(1 << 9)
+#define PWRGATE_STATUS_CE2_ENABLE		(1 << 10)
+#define PWRGATE_STATUS_CE3_ENABLE		(1 << 11)
+#define PWRGATE_STATUS_CELP_ENABLE		(1 << 12)
+#define PWRGATE_STATUS_CE0_ENABLE		(1 << 14)
+#define PWRGATE_STATUS_C0NC_ENABLE		(1 << 15)
+#define PWRGATE_STATUS_C1NC_ENABLE		(1 << 16)
+#define PWRGATE_STATUS_SOR_ENABLE		(1 << 17)
+#define PWRGATE_STATUS_DIS_ENABLE		(1 << 18)
+#define PWRGATE_STATUS_DISB_ENABLE		(1 << 19)
+#define PWRGATE_STATUS_XUSBA_ENABLE		(1 << 20)
+#define PWRGATE_STATUS_XUSBB_ENABLE		(1 << 21)
+#define PWRGATE_STATUS_XUSBC_ENABLE		(1 << 22)
+#define PWRGATE_STATUS_VIC_ENABLE		(1 << 23)
+#define PWRGATE_STATUS_IRAM_ENABLE		(1 << 24)
+
+/* APBDEV_PMC_CNTRL2_0 0x440 */
+#define HOLD_CKE_LOW_EN				(1 << 12)
+
+#endif	/* PMC_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/scu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/scu.h
new file mode 100644
index 000000000..987c16ff4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/scu.h
@@ -0,0 +1,27 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SCU_H_
+#define _SCU_H_
+
+/* ARM Snoop Control Unit (SCU) registers */
+struct scu_ctlr {
+	uint scu_ctrl;		/* SCU Control Register, offset 00 */
+	uint scu_cfg;		/* SCU Config Register, offset 04 */
+	uint scu_cpu_pwr_stat;	/* SCU CPU Power Status Register, offset 08 */
+	uint scu_inv_all;	/* SCU Invalidate All Register, offset 0C */
+	uint scu_reserved0[12];	/* reserved, offset 10-3C */
+	uint scu_filt_start;	/* SCU Filtering Start Address Reg, offset 40 */
+	uint scu_filt_end;	/* SCU Filtering End Address Reg, offset 44 */
+	uint scu_reserved1[2];	/* reserved, offset 48-4C */
+	uint scu_acc_ctl;	/* SCU Access Control Register, offset 50 */
+	uint scu_ns_acc_ctl;	/* SCU Non-secure Access Cntrl Reg, offset 54 */
+};
+
+#define SCU_CTRL_ENABLE		(1 << 0)
+
+#endif	/* SCU_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/sys_proto.h
new file mode 100644
index 000000000..8b3fbe12f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/sys_proto.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+struct tegra_sysinfo {
+	char *board_string;
+};
+
+void invalidate_dcache(void);
+
+extern const struct tegra_sysinfo sysinfo;
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra.h
new file mode 100644
index 000000000..d63af0e5f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra.h
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA_H_
+#define _TEGRA_H_
+
+#define NV_PA_ARM_PERIPHBASE	0x50040000
+#define NV_PA_PG_UP_BASE	0x60000000
+#define NV_PA_TMRUS_BASE	0x60005010
+#define NV_PA_CLK_RST_BASE	0x60006000
+#define NV_PA_FLOW_BASE		0x60007000
+#define NV_PA_GPIO_BASE		0x6000D000
+#define NV_PA_EVP_BASE		0x6000F000
+#define NV_PA_APB_MISC_BASE	0x70000000
+#define NV_PA_APB_MISC_GP_BASE	(NV_PA_APB_MISC_BASE + 0x0800)
+#define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
+#define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
+#define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
+#define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
+#define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
+#define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
+#define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_SLINK1_BASE	(NV_PA_APB_MISC_BASE + 0xD400)
+#define NV_PA_SLINK2_BASE	(NV_PA_APB_MISC_BASE + 0xD600)
+#define NV_PA_SLINK3_BASE	(NV_PA_APB_MISC_BASE + 0xD800)
+#define NV_PA_SLINK4_BASE	(NV_PA_APB_MISC_BASE + 0xDA00)
+#define NV_PA_SLINK5_BASE	(NV_PA_APB_MISC_BASE + 0xDC00)
+#define NV_PA_SLINK6_BASE	(NV_PA_APB_MISC_BASE + 0xDE00)
+#define TEGRA_DVC_BASE		(NV_PA_APB_MISC_BASE + 0xD000)
+#define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
+#define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
+#define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+	defined(CONFIG_TEGRA114)
+#define NV_PA_CSITE_BASE	0x70040000
+#else
+#define NV_PA_CSITE_BASE	0x70800000
+#endif
+#define TEGRA_USB_ADDR_MASK	0xFFFFC000
+
+#define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
+#define LOW_LEVEL_SRAM_STACK	0x4000FFFC
+#define EARLY_AVP_STACK		(NV_PA_SDRAM_BASE + 0x20000)
+#define EARLY_CPU_STACK		(EARLY_AVP_STACK - 4096)
+#define PG_UP_TAG_AVP		0xAAAAAAAA
+
+#ifndef __ASSEMBLY__
+struct timerus {
+	unsigned int cntr_1us;
+};
+
+/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
+#define NV_WB_RUN_ADDRESS	0x40020000
+
+#define NVBOOTINFOTABLE_BCTSIZE	0x38	/* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR	0x3C	/* BCT pointer in BIT in IRAM */
+
+/* These are the available SKUs (product types) for Tegra */
+enum {
+	SKU_ID_T20_7		= 0x7,
+	SKU_ID_T20		= 0x8,
+	SKU_ID_T25SE		= 0x14,
+	SKU_ID_AP25		= 0x17,
+	SKU_ID_T25		= 0x18,
+	SKU_ID_AP25E		= 0x1b,
+	SKU_ID_T25E		= 0x1c,
+	SKU_ID_T33		= 0x80,
+	SKU_ID_T30		= 0x81, /* Cardhu value */
+	SKU_ID_TM30MQS_P_A3	= 0xb1,
+	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
+	SKU_ID_T114_1		= 0x01,
+	SKU_ID_T124_ENG		= 0x00, /* Venice2 value, unfused */
+};
+
+/*
+ * These are used to distinguish SOC types for setting up clocks. Mostly
+ * we can tell the clocking required by looking at the SOC sku_id, but
+ * for T30 it is a user option as to whether to run PLLP in fast or slow
+ * mode, so we have two options there.
+ */
+enum {
+	TEGRA_SOC_T20,
+	TEGRA_SOC_T25,
+	TEGRA_SOC_T30,
+	TEGRA_SOC_T114,
+	TEGRA_SOC_T124,
+
+	TEGRA_SOC_CNT,
+	TEGRA_SOC_UNKNOWN	= -1,
+};
+
+#else  /* __ASSEMBLY__ */
+#define PRM_RSTCTRL		NV_PA_PMC_BASE
+#endif
+
+#endif	/* TEGRA_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h
new file mode 100644
index 000000000..853e59bb6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h
@@ -0,0 +1,170 @@
+/*
+ * NVIDIA Tegra I2C controller
+ *
+ * Copyright 2010-2011 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_I2C_H_
+#define _TEGRA_I2C_H_
+
+#include <asm/types.h>
+
+enum {
+	I2C_TIMEOUT_USEC = 10000,	/* Wait time for completion */
+	I2C_FIFO_DEPTH = 8,		/* I2C fifo depth */
+};
+
+enum i2c_transaction_flags {
+	I2C_IS_WRITE = 0x1,		/* for I2C write operation */
+	I2C_IS_10_BIT_ADDRESS = 0x2,	/* for 10-bit I2C slave address */
+	I2C_USE_REPEATED_START = 0x4,	/* for repeat start */
+	I2C_NO_ACK = 0x8,		/* for slave that won't generate ACK */
+	I2C_SOFTWARE_CONTROLLER	= 0x10,	/* for I2C transfer using GPIO */
+	I2C_NO_STOP = 0x20,
+};
+
+/* Contians the I2C transaction details */
+struct i2c_trans_info {
+	/* flags to indicate the transaction details */
+	enum i2c_transaction_flags flags;
+	u32 address;	/* I2C slave device address */
+	u32 num_bytes;	/* number of bytes to be transferred */
+	/*
+	 * Send/receive buffer. For the I2C send operation this buffer should
+	 * be filled with the data to be sent to the slave device. For the I2C
+	 * receive operation this buffer is filled with the data received from
+	 * the slave device.
+	 */
+	u8 *buf;
+	int is_10bit_address;
+};
+
+struct i2c_control {
+	u32 tx_fifo;
+	u32 rx_fifo;
+	u32 packet_status;
+	u32 fifo_control;
+	u32 fifo_status;
+	u32 int_mask;
+	u32 int_status;
+};
+
+struct dvc_ctlr {
+	u32 ctrl1;			/* 00: DVC_CTRL_REG1 */
+	u32 ctrl2;			/* 04: DVC_CTRL_REG2 */
+	u32 ctrl3;			/* 08: DVC_CTRL_REG3 */
+	u32 status;			/* 0C: DVC_STATUS_REG */
+	u32 ctrl;			/* 10: DVC_I2C_CTRL_REG */
+	u32 addr_data;			/* 14: DVC_I2C_ADDR_DATA_REG */
+	u32 reserved_0[2];		/* 18: */
+	u32 req;			/* 20: DVC_REQ_REGISTER */
+	u32 addr_data3;			/* 24: DVC_I2C_ADDR_DATA_REG_3 */
+	u32 reserved_1[6];		/* 28: */
+	u32 cnfg;			/* 40: DVC_I2C_CNFG */
+	u32 cmd_addr0;			/* 44: DVC_I2C_CMD_ADDR0 */
+	u32 cmd_addr1;			/* 48: DVC_I2C_CMD_ADDR1 */
+	u32 cmd_data1;			/* 4C: DVC_I2C_CMD_DATA1 */
+	u32 cmd_data2;			/* 50: DVC_I2C_CMD_DATA2 */
+	u32 reserved_2[2];		/* 54: */
+	u32 i2c_status;			/* 5C: DVC_I2C_STATUS */
+	struct i2c_control control;	/* 60 ~ 78 */
+};
+
+struct i2c_ctlr {
+	u32 cnfg;			/* 00: I2C_I2C_CNFG */
+	u32 cmd_addr0;			/* 04: I2C_I2C_CMD_ADDR0 */
+	u32 cmd_addr1;			/* 08: I2C_I2C_CMD_DATA1 */
+	u32 cmd_data1;			/* 0C: I2C_I2C_CMD_DATA2 */
+	u32 cmd_data2;			/* 10: DVC_I2C_CMD_DATA2 */
+	u32 reserved_0[2];		/* 14: */
+	u32 status;			/* 1C: I2C_I2C_STATUS */
+	u32 sl_cnfg;			/* 20: I2C_I2C_SL_CNFG */
+	u32 sl_rcvd;			/* 24: I2C_I2C_SL_RCVD */
+	u32 sl_status;			/* 28: I2C_I2C_SL_STATUS */
+	u32 sl_addr1;			/* 2C: I2C_I2C_SL_ADDR1 */
+	u32 sl_addr2;			/* 30: I2C_I2C_SL_ADDR2 */
+	u32 reserved_1[2];		/* 34: */
+	u32 sl_delay_count;		/* 3C: I2C_I2C_SL_DELAY_COUNT */
+	u32 reserved_2[4];		/* 40: */
+	struct i2c_control control;	/* 50 ~ 68 */
+	u32 clk_div;			/* 6C: I2C_I2C_CLOCK_DIVISOR */
+};
+
+/* bit fields definitions for IO Packet Header 1 format */
+#define PKT_HDR1_PROTOCOL_SHIFT		4
+#define PKT_HDR1_PROTOCOL_MASK		(0xf << PKT_HDR1_PROTOCOL_SHIFT)
+#define PKT_HDR1_CTLR_ID_SHIFT		12
+#define PKT_HDR1_CTLR_ID_MASK		(0xf << PKT_HDR1_CTLR_ID_SHIFT)
+#define PKT_HDR1_PKT_ID_SHIFT		16
+#define PKT_HDR1_PKT_ID_MASK		(0xff << PKT_HDR1_PKT_ID_SHIFT)
+#define PROTOCOL_TYPE_I2C		1
+
+/* bit fields definitions for IO Packet Header 2 format */
+#define PKT_HDR2_PAYLOAD_SIZE_SHIFT	0
+#define PKT_HDR2_PAYLOAD_SIZE_MASK	(0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
+
+/* bit fields definitions for IO Packet Header 3 format */
+#define PKT_HDR3_READ_MODE_SHIFT	19
+#define PKT_HDR3_READ_MODE_MASK		(1 << PKT_HDR3_READ_MODE_SHIFT)
+#define PKT_HDR3_SLAVE_ADDR_SHIFT	0
+#define PKT_HDR3_SLAVE_ADDR_MASK	(0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
+
+#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT	26
+#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK	\
+				(1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
+
+/* I2C_CNFG */
+#define I2C_CNFG_NEW_MASTER_FSM_SHIFT	11
+#define I2C_CNFG_NEW_MASTER_FSM_MASK	(1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
+#define I2C_CNFG_PACKET_MODE_SHIFT	10
+#define I2C_CNFG_PACKET_MODE_MASK	(1 << I2C_CNFG_PACKET_MODE_SHIFT)
+
+/* I2C_SL_CNFG */
+#define I2C_SL_CNFG_NEWSL_SHIFT		2
+#define I2C_SL_CNFG_NEWSL_MASK		(1 << I2C_SL_CNFG_NEWSL_SHIFT)
+
+/* I2C_FIFO_STATUS */
+#define TX_FIFO_FULL_CNT_SHIFT		0
+#define TX_FIFO_FULL_CNT_MASK		(0xf << TX_FIFO_FULL_CNT_SHIFT)
+#define TX_FIFO_EMPTY_CNT_SHIFT		4
+#define TX_FIFO_EMPTY_CNT_MASK		(0xf << TX_FIFO_EMPTY_CNT_SHIFT)
+
+/* I2C_INTERRUPT_STATUS */
+#define I2C_INT_XFER_COMPLETE_SHIFT	7
+#define I2C_INT_XFER_COMPLETE_MASK	(1 << I2C_INT_XFER_COMPLETE_SHIFT)
+#define I2C_INT_NO_ACK_SHIFT		3
+#define I2C_INT_NO_ACK_MASK		(1 << I2C_INT_NO_ACK_SHIFT)
+#define I2C_INT_ARBITRATION_LOST_SHIFT	2
+#define I2C_INT_ARBITRATION_LOST_MASK	(1 << I2C_INT_ARBITRATION_LOST_SHIFT)
+
+/* I2C_CLK_DIVISOR_REGISTER */
+#define CLK_DIV_STD_FAST_MODE		0x19
+#define CLK_DIV_HS_MODE			1
+#define CLK_MULT_STD_FAST_MODE		8
+
+/**
+ * Returns the bus number of the DVC controller
+ *
+ * @return number of bus, or -1 if there is no DVC active
+ */
+int tegra_i2c_get_dvc_bus_num(void);
+
+#endif	/* _TEGRA_I2C_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_mmc.h
new file mode 100644
index 000000000..310bbd7df
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Portions Copyright (C) 2011-2012 NVIDIA Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TEGRA_MMC_H_
+#define __TEGRA_MMC_H_
+
+#include <fdtdec.h>
+
+/* for mmc_config definition */
+#include <mmc.h>
+
+#define MAX_HOSTS		4	/* Max number of 'hosts'/controllers */
+
+#ifndef __ASSEMBLY__
+struct tegra_mmc {
+	unsigned int	sysad;		/* _SYSTEM_ADDRESS_0 */
+	unsigned short	blksize;	/* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
+	unsigned short	blkcnt;		/* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
+	unsigned int	argument;	/* _ARGUMENT_0 */
+	unsigned short	trnmod;		/* _CMD_XFER_MODE_0 15:00 xfer mode */
+	unsigned short	cmdreg;		/* _CMD_XFER_MODE_0 31:16 cmd reg */
+	unsigned int	rspreg0;	/* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
+	unsigned int	rspreg1;	/* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
+	unsigned int	rspreg2;	/* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
+	unsigned int	rspreg3;	/* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
+	unsigned int	bdata;		/* _BUFFER_DATA_PORT_0 */
+	unsigned int	prnsts;		/* _PRESENT_STATE_0 */
+	unsigned char	hostctl;	/* _POWER_CONTROL_HOST_0 7:00 */
+	unsigned char	pwrcon;		/* _POWER_CONTROL_HOST_0 15:8 */
+	unsigned char	blkgap;		/* _POWER_CONTROL_HOST_9 23:16 */
+	unsigned char	wakcon;		/* _POWER_CONTROL_HOST_0 31:24 */
+	unsigned short	clkcon;		/* _CLOCK_CONTROL_0 15:00 */
+	unsigned char	timeoutcon;	/* _TIMEOUT_CTRL 23:16 */
+	unsigned char	swrst;		/* _SW_RESET_ 31:24 */
+	unsigned int	norintsts;	/* _INTERRUPT_STATUS_0 */
+	unsigned int	norintstsen;	/* _INTERRUPT_STATUS_ENABLE_0 */
+	unsigned int	norintsigen;	/* _INTERRUPT_SIGNAL_ENABLE_0 */
+	unsigned short	acmd12errsts;	/* _AUTO_CMD12_ERR_STATUS_0 15:00 */
+	unsigned char	res1[2];	/* _RESERVED 31:16 */
+	unsigned int	capareg;	/* _CAPABILITIES_0 */
+	unsigned char	res2[4];	/* RESERVED, offset 44h-47h */
+	unsigned int	maxcurr;	/* _MAXIMUM_CURRENT_0 */
+	unsigned char	res3[4];	/* RESERVED, offset 4Ch-4Fh */
+	unsigned short	setacmd12err;	/* offset 50h */
+	unsigned short	setinterr;	/* offset 52h */
+	unsigned char	admaerr;	/* offset 54h */
+	unsigned char	res4[3];	/* RESERVED, offset 55h-57h */
+	unsigned long	admaaddr;	/* offset 58h-5Fh */
+	unsigned char	res5[0xa0];	/* RESERVED, offset 60h-FBh */
+	unsigned short	slotintstatus;	/* offset FCh */
+	unsigned short	hcver;		/* HOST Version */
+	unsigned int	venclkctl;	/* _VENDOR_CLOCK_CNTRL_0,    100h */
+	unsigned int	venspictl;	/* _VENDOR_SPI_CNTRL_0,      104h */
+	unsigned int	venspiintsts;	/* _VENDOR_SPI_INT_STATUS_0, 108h */
+	unsigned int	venceatactl;	/* _VENDOR_CEATA_CNTRL_0,    10Ch */
+	unsigned int	venbootctl;	/* _VENDOR_BOOT_CNTRL_0,     110h */
+	unsigned int	venbootacktout;	/* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
+	unsigned int	venbootdattout;	/* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
+	unsigned int	vendebouncecnt;	/* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
+	unsigned int	venmiscctl;	/* _VENDOR_MISC_CNTRL_0,     120h */
+	unsigned int	res6[47];	/* 0x124 ~ 0x1DC */
+	unsigned int	sdmemcmppadctl;	/* _SDMEMCOMPPADCTRL_0,      1E0h */
+	unsigned int	autocalcfg;	/* _AUTO_CAL_CONFIG_0,       1E4h */
+	unsigned int	autocalintval;	/* _AUTO_CAL_INTERVAL_0,     1E8h */
+	unsigned int	autocalsts;	/* _AUTO_CAL_STATUS_0,       1ECh */
+};
+
+#define TEGRA_MMC_PWRCTL_SD_BUS_POWER				(1 << 0)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8			(5 << 1)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0			(6 << 1)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3			(7 << 1)
+
+#define TEGRA_MMC_HOSTCTL_DMASEL_MASK				(3 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA				(0 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT			(2 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT			(3 << 3)
+
+#define TEGRA_MMC_TRNMOD_DMA_ENABLE				(1 << 0)
+#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE			(1 << 1)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE		(0 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ			(1 << 4)
+#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT			(1 << 5)
+
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK			(3 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE		(0 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136		(1 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48		(2 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY	(3 << 0)
+
+#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK				(1 << 3)
+#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK			(1 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER	(1 << 5)
+
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD			(1 << 0)
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT			(1 << 1)
+
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE			(1 << 0)
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE			(1 << 1)
+#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE			(1 << 2)
+
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT			8
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK			(0xff << 8)
+
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL			(1 << 0)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE			(1 << 1)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE			(1 << 2)
+
+#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE			(1 << 0)
+#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE			(1 << 1)
+#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT			(1 << 3)
+#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT			(1 << 15)
+#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT				(1 << 16)
+
+#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE			(1 << 0)
+#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE			(1 << 1)
+#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT			(1 << 3)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY		(1 << 4)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY			(1 << 5)
+
+#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE			(1 << 1)
+
+/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+#define MEMCOMP_PADCTRL_VREF	7
+#define AUTO_CAL_ENABLED	(1 << 29)
+#define AUTO_CAL_PD_OFFSET	(0x70 << 8)
+#define AUTO_CAL_PU_OFFSET	(0x62 << 0)
+
+struct mmc_host {
+	struct tegra_mmc *reg;
+	int id;			/* device id/number, 0-3 */
+	int enabled;		/* 1 to enable, 0 to disable */
+	int width;		/* Bus Width, 1, 4 or 8 */
+	enum periph_id mmc_id;	/* Peripheral ID: PERIPH_ID_... */
+	struct fdt_gpio_state cd_gpio;		/* Change Detect GPIO */
+	struct fdt_gpio_state pwr_gpio;		/* Power GPIO */
+	struct fdt_gpio_state wp_gpio;		/* Write Protect GPIO */
+	unsigned int version;	/* SDHCI spec. version */
+	unsigned int clock;	/* Current clock (MHz) */
+	struct mmc_config cfg;	/* mmc configuration */
+};
+
+void pad_init_mmc(struct mmc_host *host);
+
+#endif	/* __ASSEMBLY__ */
+#endif	/* __TEGRA_MMC_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/timer.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/timer.h
new file mode 100644
index 000000000..5d5664115
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/timer.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Tegra20 timer functions */
+
+#ifndef _TEGRA_TIMER_H
+#define _TEGRA_TIMER_H
+
+/* returns the current monotonic timer value in microseconds */
+unsigned long timer_get_us(void);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/uart.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/uart.h
new file mode 100644
index 000000000..fef7f8db3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/uart.h
@@ -0,0 +1,31 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _UART_H_
+#define _UART_H_
+
+/* UART registers */
+struct uart_ctlr {
+	uint uart_thr_dlab_0;		/* UART_THR_DLAB_0_0, offset 00 */
+	uint uart_ier_dlab_0;		/* UART_IER_DLAB_0_0, offset 04 */
+	uint uart_iir_fcr;		/* UART_IIR_FCR_0, offset 08 */
+	uint uart_lcr;			/* UART_LCR_0, offset 0C */
+	uint uart_mcr;			/* UART_MCR_0, offset 10 */
+	uint uart_lsr;			/* UART_LSR_0, offset 14 */
+	uint uart_msr;			/* UART_MSR_0, offset 18 */
+	uint uart_spr;			/* UART_SPR_0, offset 1C */
+	uint uart_irda_csr;		/* UART_IRDA_CSR_0, offset 20 */
+	uint uart_reserved[6];		/* Reserved, unused, offset 24-38*/
+	uint uart_asr;			/* UART_ASR_0, offset 3C */
+};
+
+#define NVRM_PLLP_FIXED_FREQ_KHZ	216000
+#define NV_DEFAULT_DEBUG_BAUD		115200
+
+#define UART_FCR_TRIGGER_3	0x30	/* Mask for trigger set at 3 */
+
+#endif	/* UART_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h
new file mode 100644
index 000000000..ceb7bcd9c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/usb.h
@@ -0,0 +1,356 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA_USB_H_
+#define _TEGRA_USB_H_
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[2];
+
+#ifdef CONFIG_TEGRA20
+	/* 0x130 */
+	uint reserved4_2[4];
+
+	/* 0x140 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x150 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint async_tt_sts;
+
+	/* 0x160 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;   /* is this port_sc1 on some controllers? */
+	uint icusb_ctrl;
+
+	/* 0x170 */
+	uint ulpi_viewport;
+	uint reserved7;
+	uint endpt_nak;
+	uint endpt_nak_enable;
+
+	/* 0x180 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x1a0 */
+	uint reserved9;
+	uint otgsc;
+	uint usb_mode;
+	uint endpt_setup_stat;
+
+	/* 0x1b0 */
+	uint reserved10[20];
+
+	/* 0x200 */
+	uint reserved11[0x80];
+#else
+	/* 0x130 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x140 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint reserved5_1;
+
+	/* 0x150 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;
+	uint icusb_ctrl;
+
+	/* 0x160 */
+	uint ulpi_viewport;
+	uint reserved7[3];
+
+	/* 0x170 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x190 */
+	uint reserved9[8];
+
+	/* 0x1b0 */
+	uint reserved10;
+	uint hostpc1_devlc;
+	uint reserved10_1[2];
+
+	/* 0x1c0 */
+	uint reserved10_2[4];
+
+	/* 0x1d0 */
+	uint reserved10_3[4];
+
+	/* 0x1e0 */
+	uint reserved10_4[4];
+
+	/* 0x1f0 */
+	uint reserved10_5;
+	uint otgsc;
+	uint usb_mode;
+	uint reserved10_6;
+
+	/* 0x200 */
+	uint endpt_nak;
+	uint endpt_nak_enable;
+	uint endpt_setup_stat;
+	uint reserved11_1[0x7D];
+#endif
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+#ifdef CONFIG_TEGRA20
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[4];
+
+	/* 0x424 */
+	uint ulpi_timing_ctrl_0;
+	uint ulpi_timing_ctrl_1;
+	uint reserved13[53];
+#else
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+#endif
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE		1
+
+#define VBUS_SENSE_CTL_SHIFT			1
+#define VBUS_SENSE_CTL_MASK			(3 << VBUS_SENSE_CTL_SHIFT)
+#define VBUS_SENSE_CTL_VBUS_WAKEUP		0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP	1
+#define VBUS_SENSE_CTL_AB_SESS_VLD		2
+#define VBUS_SENSE_CTL_A_SESS_VLD		3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB			        (1 << 12)
+#define UTMIP_RESET			        (1 << 11)
+#define USB_PHY_CLK_VALID			(1 << 7)
+#define USB_SUSP_CLR				(1 << 5)
+
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
+/* USB2_IF_USB_SUSP_CTRL_0 */
+#define ULPI_PHY_ENB				(1 << 13)
+
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP			(1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP			(1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD			(1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD		(1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
+#endif
+
+/* USBx_UTMIP_MISC_CFG0 */
+#define UTMIP_SUSPEND_EXIT_ON_EDGE		(1 << 22)
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN			(1 << 30)
+
+/*
+ * Tegra 3 and later: Moved to Clock and Reset register space, see
+ * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
+ */
+#define UTMIP_PLLU_STABLE_COUNT_SHIFT		6
+#define UTMIP_PLLU_STABLE_COUNT_MASK		\
+				(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+/*
+ * Tegra 3 and later: Moved to Clock and Reset register space, see
+ * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
+ */
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT	18
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK		\
+				(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+
+/* USBx_UTMIP_PLL_CFG1_0 */
+/* Tegra 3 and later: Moved to Clock and Reset register space */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT	27
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK	\
+				(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define UTMIP_XTAL_FREQ_COUNT_SHIFT		0
+#define UTMIP_XTAL_FREQ_COUNT_MASK		0xfff
+
+/* USBx_UTMIP_BIAS_CFG0_0 */
+#define UTMIP_HSDISCON_LEVEL_MSB		(1 << 24)
+#define UTMIP_OTGPD				(1 << 11)
+#define UTMIP_BIASPD				(1 << 10)
+#define UTMIP_HSDISCON_LEVEL_SHIFT		2
+#define UTMIP_HSDISCON_LEVEL_MASK		\
+				(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
+#define UTMIP_HSSQUELCH_LEVEL_SHIFT		0
+#define UTMIP_HSSQUELCH_LEVEL_MASK		\
+				(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_FORCE_PDTRK_POWERDOWN		1
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK		\
+				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
+#define UTMIP_DEBOUNCE_CFG0_SHIFT		0
+#define UTMIP_DEBOUNCE_CFG0_MASK		0xffff
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J			(1 << 19)
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG				1
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL				(1 << 3)
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_SHIFT			15
+#define UTMIP_IDLE_WAIT_MASK			(0x1f << UTMIP_IDLE_WAIT_SHIFT)
+#define UTMIP_ELASTIC_LIMIT_SHIFT		10
+#define UTMIP_ELASTIC_LIMIT_MASK		\
+				(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
+
+/* USBx_UTMIP_HSRX_CFG1_0 */
+#define UTMIP_HS_SYNC_START_DLY_SHIFT		1
+#define UTMIP_HS_SYNC_START_DLY_MASK		\
+				(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1					(1 << 3)
+
+#ifdef CONFIG_TEGRA20
+/* PORTSC1, USB1 */
+#define PTS1_SHIFT				31
+#define PTS1_MASK				(1 << PTS1_SHIFT)
+#define STS1					(1 << 30)
+
+/* PORTSC, USB2, USB3 */
+#define PTS_SHIFT		30
+#define PTS_MASK		(3U << PTS_SHIFT)
+#define STS			(1 << 29)
+#else
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT				29
+#define PTS_MASK				(0x7U << PTS_SHIFT)
+#define STS						(1 << 28)
+#endif
+
+#define PTS_UTMI	0
+#define PTS_RESERVED	1
+#define PTS_ULPI	2
+#define PTS_ICUSB_SER	3
+#define PTS_HSIC	4
+
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
+#define WKOC				(1 << 22)
+#define WKDS				(1 << 21)
+#define WKCN				(1 << 20)
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
+#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
+#define UTMIP_XCVR_HSSLEW_MSB_SHIFT		25
+#define UTMIP_XCVR_HSSLEW_MSB_MASK		\
+			(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_MSB_SHIFT	22
+#define UTMIP_XCVR_SETUP_MSB_MASK	(0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_SHIFT		0
+#define UTMIP_XCVR_SETUP_MASK		(0xf << UTMIP_XCVR_SETUP_SHIFT)
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT		18
+#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK		\
+			(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN		(1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN		(1 << 4)
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS			(1 << 26)
+
+/* Setup USB on the board */
+int usb_process_devicetree(const void *blob);
+
+#endif	/* _TEGRA_USB_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/warmboot.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/warmboot.h
new file mode 100644
index 000000000..2e66e0f23
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra/warmboot.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _WARM_BOOT_H_
+#define _WARM_BOOT_H_
+
+#define STRAP_OPT_A_RAM_CODE_SHIFT	4
+#define STRAP_OPT_A_RAM_CODE_MASK	(0xf << STRAP_OPT_A_RAM_CODE_SHIFT)
+
+/* Defines the supported operating modes */
+enum fuse_operating_mode {
+	MODE_PRODUCTION = 3,
+	MODE_UNDEFINED,
+};
+
+/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */
+enum {
+	HASH_LENGTH = 4
+};
+
+/* Defines the storage for a hash value (128 bits) */
+struct hash {
+	u32 hash[HASH_LENGTH];
+};
+
+/*
+ * Defines the code header information for the boot rom.
+ *
+ * The code immediately follows the code header.
+ *
+ * Note that the code header needs to be 16 bytes aligned to preserve
+ * the alignment of relevant data for hash and decryption computations without
+ * requiring extra copies to temporary memory areas.
+ */
+struct wb_header {
+	u32 length_insecure;	/* length of the code header */
+	u32 reserved[3];
+	struct hash hash;	/* hash of header+code, starts next field*/
+	struct hash random_aes_block;	/* a data block to aid security. */
+	u32 length_secure;	/* length of the code header */
+	u32 destination;	/* destination address to put the wb code */
+	u32 entry_point;	/* execution address of the wb code */
+	u32 code_length;	/* length of the code */
+};
+
+/*
+ * The warm boot code needs direct access to these registers since it runs in
+ * SRAM and cannot call other U-Boot code.
+ */
+union osc_ctrl_reg {
+	struct {
+		u32 xoe:1;
+		u32 xobp:1;
+		u32 reserved0:2;
+		u32 xofs:6;
+		u32 reserved1:2;
+		u32 xods:5;
+		u32 reserved2:3;
+		u32 oscfi_spare:8;
+		u32 pll_ref_div:2;
+		u32 osc_freq:2;
+	};
+	u32 word;
+};
+
+union pllx_base_reg {
+	struct {
+		u32 divm:5;
+		u32 reserved0:3;
+		u32 divn:10;
+		u32 reserved1:2;
+		u32 divp:3;
+		u32 reserved2:4;
+		u32 lock:1;
+		u32 reserved3:1;
+		u32 ref_dis:1;
+		u32 enable:1;
+		u32 bypass:1;
+	};
+	u32 word;
+};
+
+union pllx_misc_reg {
+	struct {
+		u32 vcocon:4;
+		u32 lfcon:4;
+		u32 cpcon:4;
+		u32 lock_sel:6;
+		u32 reserved0:1;
+		u32 lock_enable:1;
+		u32 reserved1:1;
+		u32 dccon:1;
+		u32 pts:2;
+		u32 reserved2:6;
+		u32 out1_div_byp:1;
+		u32 out1_inv_clk:1;
+	};
+	u32 word;
+};
+
+/*
+ * TODO: This register is not documented in the TRM yet. We could move this
+ * into the EMC and give it a proper interface, but not while it is
+ * undocumented.
+ */
+union scratch3_reg {
+	struct {
+		u32 pllx_base_divm:5;
+		u32 pllx_base_divn:10;
+		u32 pllx_base_divp:3;
+		u32 pllx_misc_lfcon:4;
+		u32 pllx_misc_cpcon:4;
+	};
+	u32 word;
+};
+
+
+/**
+ * Save warmboot memory settings for a later resume
+ *
+ * @return 0 if ok, -1 on error
+ */
+int warmboot_save_sdram_params(void);
+
+int warmboot_prepare_code(u32 seg_address, u32 seg_length);
+int sign_data_block(u8 *source, u32 length, u8 *signature);
+void wb_start(void);	/* Start of WB assembly code */
+void wb_end(void);	/* End of WB assembly code */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock-tables.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock-tables.h
new file mode 100644
index 000000000..d8fa0e1d2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock-tables.h
@@ -0,0 +1,402 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 clock PLL tables */
+
+#ifndef _TEGRA114_CLOCK_TABLES_H_
+#define _TEGRA114_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SOC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+	CLOCK_ID_DISPLAY2,	/* placeholder */
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 (DEVICES_L) */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_RESERVED3,
+	PERIPH_ID_RTC,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_RESERVED16,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 (DEVICES_H) */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_RESERVED45,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_I2C5,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 (DEVICES_U) */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_NANDSPEED,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+	PERIPH_ID_RESERVED89,
+	PERIPH_ID_MDOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUSOUT,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_RESERVED95,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_3D2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_TSENSOR,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 104 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 112 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_EX_RESERVED17,
+	PERIPH_ID_EX_RESERVED18,
+	PERIPH_ID_EX_RESERVED19,
+	PERIPH_ID_EX_RESERVED20,
+	PERIPH_ID_EX_RESERVED21,
+	PERIPH_ID_EX_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 120 */
+	PERIPH_ID_EX_RESERVED24,
+	PERIPH_ID_EX_RESERVED25,
+	PERIPH_ID_EX_RESERVED26,
+	PERIPH_ID_EX_RESERVED27,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_EX_RESERVED30,
+	PERIPH_ID_EX_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_RESERVED1_SATACOLD,
+	PERIPH_ID_RESERVED2_PCIERX0,
+	PERIPH_ID_RESERVED3_PCIERX1,
+	PERIPH_ID_RESERVED4_PCIERX2,
+	PERIPH_ID_RESERVED5_PCIERX3,
+	PERIPH_ID_RESERVED6_PCIERX4,
+	PERIPH_ID_RESERVED7_PCIERX5,
+
+	/* 136 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_PCIE2_IOBIST,
+	PERIPH_ID_EMC_IOBIST,
+	PERIPH_ID_HDMI_IOBIST,
+	PERIPH_ID_SATA_IOBIST,
+	PERIPH_ID_MIPI_IOBIST,
+	PERIPH_ID_EMC1_IOBIST,
+	PERIPH_ID_XUSB,
+
+	/* 144 */
+	PERIPH_ID_CILAB,
+	PERIPH_ID_CILCD,
+	PERIPH_ID_CILE,
+	PERIPH_ID_DSIA_LP,
+	PERIPH_ID_DSIB_LP,
+	PERIPH_ID_RESERVED21_ENTROPY,
+	PERIPH_ID_RESERVED22_W,
+	PERIPH_ID_RESERVED23_W,
+
+	/* 152 */
+	PERIPH_ID_RESERVED24_W,
+	PERIPH_ID_AMX0,
+	PERIPH_ID_ADX0,
+	PERIPH_ID_DVFS,
+	PERIPH_ID_XUSB_SS,
+	PERIPH_ID_EMC_DLL,
+	PERIPH_ID_MC1,
+	PERIPH_ID_EMC1,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_I2C5,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_CVE,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_EPP,
+	PERIPHC_MPE,
+	PERIPHC_MIPI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_TVO,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_37h,
+
+	PERIPHC_VW_FIRST,
+	/* 0x38 */
+	PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x40 */
+	PERIPHC_AUDIO,
+	PERIPHC_41h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x48 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_SPEEDO,
+	PERIPHC_4eh,
+	PERIPHC_4fh,
+
+	/* 0x50 */
+	PERIPHC_50h,
+	PERIPHC_51h,
+	PERIPHC_52h,
+	PERIPHC_53h,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA114_CLOCK_TABLES_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock.h
new file mode 100644
index 000000000..abbefcd0e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/clock.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 clock control functions */
+
+#ifndef _TEGRA114_CLOCK_H_
+#define _TEGRA114_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+#endif	/* _TEGRA114_CLOCK_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/flow.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/flow.h
new file mode 100644
index 000000000..c7eb051c7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/flow.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_FLOW_H_
+#define _TEGRA114_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;
+	u32 halt_cop_events;
+	u32 cpu_csr;
+	u32 cop_csr;
+	u32 xrq_events;
+	u32 halt_cpu1_events;
+	u32 cpu1_csr;
+	u32 halt_cpu2_events;
+	u32 cpu2_csr;
+	u32 halt_cpu3_events;
+	u32 cpu3_csr;
+	u32 cluster_control;
+};
+
+#endif	/* _TEGRA114_FLOW_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/funcmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/funcmux.h
new file mode 100644
index 000000000..7f48f2510
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/funcmux.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 high-level function multiplexing */
+
+#ifndef _TEGRA114_FUNCMUX_H_
+#define _TEGRA114_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART4_GMI = 0,
+};
+#endif	/* _TEGRA114_FUNCMUX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
new file mode 100644
index 000000000..41ce67780
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_GP_PADCTRL_H_
+#define _TEGRA114_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	reserved1;	/* 0x8C: */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	reserved2[3];	/* 0xA4 - 0xAC: */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	reserved3[9];	/* 0xC8-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+	u32	reserved4[3];	/* 0xF0-0xF8: */
+	u32	ddccfg;		/* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+	u32	gmacfg;		/* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+	u32	reserved5[3];	/* 0x104-0x10C: */
+	u32	gmecfg;		/* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+	u32	gmfcfg;		/* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+	u32	gmgcfg;		/* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+	u32	gmhcfg;		/* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+	u32	owrcfg;		/* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+	u32	uadcfg;		/* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+	u32	reserved6;	/* 0x128: */
+	u32	dev3cfg;	/* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+	u32	reserved7[2];	/* 0x130 - 0x134: */
+	u32	ceccfg;		/* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+	u32	reserved8[22];	/* 0x13C - 0x190: */
+	u32	atcfg6;		/* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+	u32	dap5cfg;	/* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+	u32	vbuscfg;	/* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+	u32	aocfg3;		/* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+	u32	hvccfg0;	/* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+	u32	sdio4cfg;	/* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+	u32	aocfg0;		/* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF	0
+#define SDIOCFG_DRVDN_SLWR	0
+#define SDIOCFG_DRVUP		0x24
+#define SDIOCFG_DRVDN		0x14
+
+#endif	/* _TEGRA114_GP_PADCTRL_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gpio.h
new file mode 100644
index 000000000..21853b6eb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/gpio.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_GPIO_H_
+#define _TEGRA114_GPIO_H_
+
+/*
+ * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+#include <asm/arch-tegra30/gpio.h>
+
+#endif	/* _TEGRA114_GPIO_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/hardware.h
new file mode 100644
index 000000000..c21fbb625
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/hardware.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_HARDWARE_H_
+#define _TEGRA114_HARDWARE_H_
+
+/* include tegra specific hardware definitions */
+
+#endif /* _TEGRA114_HARDWARE_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pinmux.h
new file mode 100644
index 000000000..c1cb3ef16
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA114_PINMUX_H_
+#define _TEGRA114_PINMUX_H_
+
+enum pmux_pingrp {
+	PMUX_PINGRP_ULPI_DATA0_PO1,
+	PMUX_PINGRP_ULPI_DATA1_PO2,
+	PMUX_PINGRP_ULPI_DATA2_PO3,
+	PMUX_PINGRP_ULPI_DATA3_PO4,
+	PMUX_PINGRP_ULPI_DATA4_PO5,
+	PMUX_PINGRP_ULPI_DATA5_PO6,
+	PMUX_PINGRP_ULPI_DATA6_PO7,
+	PMUX_PINGRP_ULPI_DATA7_PO0,
+	PMUX_PINGRP_ULPI_CLK_PY0,
+	PMUX_PINGRP_ULPI_DIR_PY1,
+	PMUX_PINGRP_ULPI_NXT_PY2,
+	PMUX_PINGRP_ULPI_STP_PY3,
+	PMUX_PINGRP_DAP3_FS_PP0,
+	PMUX_PINGRP_DAP3_DIN_PP1,
+	PMUX_PINGRP_DAP3_DOUT_PP2,
+	PMUX_PINGRP_DAP3_SCLK_PP3,
+	PMUX_PINGRP_PV0,
+	PMUX_PINGRP_PV1,
+	PMUX_PINGRP_SDMMC1_CLK_PZ0,
+	PMUX_PINGRP_SDMMC1_CMD_PZ1,
+	PMUX_PINGRP_SDMMC1_DAT3_PY4,
+	PMUX_PINGRP_SDMMC1_DAT2_PY5,
+	PMUX_PINGRP_SDMMC1_DAT1_PY6,
+	PMUX_PINGRP_SDMMC1_DAT0_PY7,
+	PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+	PMUX_PINGRP_CLK2_REQ_PCC5,
+	PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+	PMUX_PINGRP_DDC_SCL_PV4,
+	PMUX_PINGRP_DDC_SDA_PV5,
+	PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+	PMUX_PINGRP_UART2_TXD_PC2,
+	PMUX_PINGRP_UART2_RTS_N_PJ6,
+	PMUX_PINGRP_UART2_CTS_N_PJ5,
+	PMUX_PINGRP_UART3_TXD_PW6,
+	PMUX_PINGRP_UART3_RXD_PW7,
+	PMUX_PINGRP_UART3_CTS_N_PA1,
+	PMUX_PINGRP_UART3_RTS_N_PC0,
+	PMUX_PINGRP_PU0,
+	PMUX_PINGRP_PU1,
+	PMUX_PINGRP_PU2,
+	PMUX_PINGRP_PU3,
+	PMUX_PINGRP_PU4,
+	PMUX_PINGRP_PU5,
+	PMUX_PINGRP_PU6,
+	PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+	PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+	PMUX_PINGRP_DAP4_FS_PP4,
+	PMUX_PINGRP_DAP4_DIN_PP5,
+	PMUX_PINGRP_DAP4_DOUT_PP6,
+	PMUX_PINGRP_DAP4_SCLK_PP7,
+	PMUX_PINGRP_CLK3_OUT_PEE0,
+	PMUX_PINGRP_CLK3_REQ_PEE1,
+	PMUX_PINGRP_GMI_WP_N_PC7,
+	PMUX_PINGRP_GMI_IORDY_PI5,
+	PMUX_PINGRP_GMI_WAIT_PI7,
+	PMUX_PINGRP_GMI_ADV_N_PK0,
+	PMUX_PINGRP_GMI_CLK_PK1,
+	PMUX_PINGRP_GMI_CS0_N_PJ0,
+	PMUX_PINGRP_GMI_CS1_N_PJ2,
+	PMUX_PINGRP_GMI_CS2_N_PK3,
+	PMUX_PINGRP_GMI_CS3_N_PK4,
+	PMUX_PINGRP_GMI_CS4_N_PK2,
+	PMUX_PINGRP_GMI_CS6_N_PI3,
+	PMUX_PINGRP_GMI_CS7_N_PI6,
+	PMUX_PINGRP_GMI_AD0_PG0,
+	PMUX_PINGRP_GMI_AD1_PG1,
+	PMUX_PINGRP_GMI_AD2_PG2,
+	PMUX_PINGRP_GMI_AD3_PG3,
+	PMUX_PINGRP_GMI_AD4_PG4,
+	PMUX_PINGRP_GMI_AD5_PG5,
+	PMUX_PINGRP_GMI_AD6_PG6,
+	PMUX_PINGRP_GMI_AD7_PG7,
+	PMUX_PINGRP_GMI_AD8_PH0,
+	PMUX_PINGRP_GMI_AD9_PH1,
+	PMUX_PINGRP_GMI_AD10_PH2,
+	PMUX_PINGRP_GMI_AD11_PH3,
+	PMUX_PINGRP_GMI_AD12_PH4,
+	PMUX_PINGRP_GMI_AD13_PH5,
+	PMUX_PINGRP_GMI_AD14_PH6,
+	PMUX_PINGRP_GMI_AD15_PH7,
+	PMUX_PINGRP_GMI_A16_PJ7,
+	PMUX_PINGRP_GMI_A17_PB0,
+	PMUX_PINGRP_GMI_A18_PB1,
+	PMUX_PINGRP_GMI_A19_PK7,
+	PMUX_PINGRP_GMI_WR_N_PI0,
+	PMUX_PINGRP_GMI_OE_N_PI1,
+	PMUX_PINGRP_GMI_DQS_P_PJ3,
+	PMUX_PINGRP_GMI_RST_N_PI4,
+	PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+	PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+	PMUX_PINGRP_SDMMC4_CLK_PCC4,
+	PMUX_PINGRP_SDMMC4_CMD_PT7,
+	PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+	PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+	PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+	PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+	PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+	PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+	PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+	PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+	PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+	PMUX_PINGRP_PCC1,
+	PMUX_PINGRP_PBB0,
+	PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+	PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+	PMUX_PINGRP_PBB3,
+	PMUX_PINGRP_PBB4,
+	PMUX_PINGRP_PBB5,
+	PMUX_PINGRP_PBB6,
+	PMUX_PINGRP_PBB7,
+	PMUX_PINGRP_PCC2,
+	PMUX_PINGRP_JTAG_RTCK,
+	PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+	PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+	PMUX_PINGRP_KB_ROW0_PR0,
+	PMUX_PINGRP_KB_ROW1_PR1,
+	PMUX_PINGRP_KB_ROW2_PR2,
+	PMUX_PINGRP_KB_ROW3_PR3,
+	PMUX_PINGRP_KB_ROW4_PR4,
+	PMUX_PINGRP_KB_ROW5_PR5,
+	PMUX_PINGRP_KB_ROW6_PR6,
+	PMUX_PINGRP_KB_ROW7_PR7,
+	PMUX_PINGRP_KB_ROW8_PS0,
+	PMUX_PINGRP_KB_ROW9_PS1,
+	PMUX_PINGRP_KB_ROW10_PS2,
+	PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
+	PMUX_PINGRP_KB_COL1_PQ1,
+	PMUX_PINGRP_KB_COL2_PQ2,
+	PMUX_PINGRP_KB_COL3_PQ3,
+	PMUX_PINGRP_KB_COL4_PQ4,
+	PMUX_PINGRP_KB_COL5_PQ5,
+	PMUX_PINGRP_KB_COL6_PQ6,
+	PMUX_PINGRP_KB_COL7_PQ7,
+	PMUX_PINGRP_CLK_32K_OUT_PA0,
+	PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+	PMUX_PINGRP_CORE_PWR_REQ,
+	PMUX_PINGRP_CPU_PWR_REQ,
+	PMUX_PINGRP_PWR_INT_N,
+	PMUX_PINGRP_CLK_32K_IN,
+	PMUX_PINGRP_OWR,
+	PMUX_PINGRP_DAP1_FS_PN0,
+	PMUX_PINGRP_DAP1_DIN_PN1,
+	PMUX_PINGRP_DAP1_DOUT_PN2,
+	PMUX_PINGRP_DAP1_SCLK_PN3,
+	PMUX_PINGRP_CLK1_REQ_PEE2,
+	PMUX_PINGRP_CLK1_OUT_PW4,
+	PMUX_PINGRP_SPDIF_IN_PK6,
+	PMUX_PINGRP_SPDIF_OUT_PK5,
+	PMUX_PINGRP_DAP2_FS_PA2,
+	PMUX_PINGRP_DAP2_DIN_PA4,
+	PMUX_PINGRP_DAP2_DOUT_PA5,
+	PMUX_PINGRP_DAP2_SCLK_PA3,
+	PMUX_PINGRP_DVFS_PWM_PX0,
+	PMUX_PINGRP_GPIO_X1_AUD_PX1,
+	PMUX_PINGRP_GPIO_X3_AUD_PX3,
+	PMUX_PINGRP_DVFS_CLK_PX2,
+	PMUX_PINGRP_GPIO_X4_AUD_PX4,
+	PMUX_PINGRP_GPIO_X5_AUD_PX5,
+	PMUX_PINGRP_GPIO_X6_AUD_PX6,
+	PMUX_PINGRP_GPIO_X7_AUD_PX7,
+	PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+	PMUX_PINGRP_SDMMC3_CMD_PA7,
+	PMUX_PINGRP_SDMMC3_DAT0_PB7,
+	PMUX_PINGRP_SDMMC3_DAT1_PB6,
+	PMUX_PINGRP_SDMMC3_DAT2_PB5,
+	PMUX_PINGRP_SDMMC3_DAT3_PB4,
+	PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+	PMUX_PINGRP_SDMMC1_WP_N_PV3,
+	PMUX_PINGRP_SDMMC3_CD_N_PV2,
+	PMUX_PINGRP_GPIO_W2_AUD_PW2,
+	PMUX_PINGRP_GPIO_W3_AUD_PW3,
+	PMUX_PINGRP_USB_VBUS_EN0_PN4,
+	PMUX_PINGRP_USB_VBUS_EN1_PN5,
+	PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+	PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+	PMUX_PINGRP_GMI_CLK_LB,
+	PMUX_PINGRP_RESET_OUT_N,
+	PMUX_PINGRP_COUNT,
+};
+
+enum pmux_drvgrp {
+	PMUX_DRVGRP_AO1,
+	PMUX_DRVGRP_AO2,
+	PMUX_DRVGRP_AT1,
+	PMUX_DRVGRP_AT2,
+	PMUX_DRVGRP_AT3,
+	PMUX_DRVGRP_AT4,
+	PMUX_DRVGRP_AT5,
+	PMUX_DRVGRP_CDEV1,
+	PMUX_DRVGRP_CDEV2,
+	PMUX_DRVGRP_DAP1 = (0x28 / 4),
+	PMUX_DRVGRP_DAP2,
+	PMUX_DRVGRP_DAP3,
+	PMUX_DRVGRP_DAP4,
+	PMUX_DRVGRP_DBG,
+	PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+	PMUX_DRVGRP_SPI,
+	PMUX_DRVGRP_UAA,
+	PMUX_DRVGRP_UAB,
+	PMUX_DRVGRP_UART2,
+	PMUX_DRVGRP_UART3,
+	PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+	PMUX_DRVGRP_DDC = (0x94 / 4),
+	PMUX_DRVGRP_GMA,
+	PMUX_DRVGRP_GME = (0xa8 / 4),
+	PMUX_DRVGRP_GMF,
+	PMUX_DRVGRP_GMG,
+	PMUX_DRVGRP_GMH,
+	PMUX_DRVGRP_OWR,
+	PMUX_DRVGRP_UDA,
+	PMUX_DRVGRP_DEV3 = (0xc4 / 4),
+	PMUX_DRVGRP_CEC = (0xd0 / 4),
+	PMUX_DRVGRP_AT6 = (0x12c / 4),
+	PMUX_DRVGRP_DAP5,
+	PMUX_DRVGRP_USB_VBUS_EN,
+	PMUX_DRVGRP_AO3,
+	PMUX_DRVGRP_HV0,
+	PMUX_DRVGRP_SDIO4,
+	PMUX_DRVGRP_AO0,
+	PMUX_DRVGRP_COUNT,
+};
+
+enum pmux_func {
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLDVFS,
+	PMUX_FUNC_CLK,
+	PMUX_FUNC_CLK12,
+	PMUX_FUNC_CPU,
+	PMUX_FUNC_DAP,
+	PMUX_FUNC_DAP1,
+	PMUX_FUNC_DAP2,
+	PMUX_FUNC_DEV3,
+	PMUX_FUNC_DISPLAYA,
+	PMUX_FUNC_DISPLAYA_ALT,
+	PMUX_FUNC_DISPLAYB,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_EMC_DLL,
+	PMUX_FUNC_EXTPERIPH1,
+	PMUX_FUNC_EXTPERIPH2,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_ALT,
+	PMUX_FUNC_HDA,
+	PMUX_FUNC_HSI,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_I2C4,
+	PMUX_FUNC_I2CPWR,
+	PMUX_FUNC_I2S0,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4,
+	PMUX_FUNC_IRDA,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_NAND,
+	PMUX_FUNC_NAND_ALT,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PMI,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_PWRON,
+	PMUX_FUNC_RESET_OUT_N,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC2,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SDMMC4,
+	PMUX_FUNC_SOC,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_SPI5,
+	PMUX_FUNC_SPI6,
+	PMUX_FUNC_SYSCLK,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_USB,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_ALT1,
+	PMUX_FUNC_VI_ALT3,
+	PMUX_FUNC_RSVD1,
+	PMUX_FUNC_RSVD2,
+	PMUX_FUNC_RSVD3,
+	PMUX_FUNC_RSVD4,
+	PMUX_FUNC_COUNT,
+};
+
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_RCV_SEL
+#define TEGRA_PMX_HAS_DRVGRPS
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA114_PINMUX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pmu.h
new file mode 100644
index 000000000..c6e238101
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/pmu.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_PMU_H_
+#define _TEGRA114_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif	/* _TEGRA114_PMU_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/spl.h
new file mode 100644
index 000000000..ebb16fe1d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/spl.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM         1
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h
new file mode 100644
index 000000000..c05e2c328
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/sysctr.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_SYSCTR_H_
+#define _TEGRA114_SYSCTR_H_
+
+struct sysctr_ctlr {
+	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
+	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
+	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+	u32 reserved1[4];	/* 0x10 - 0x1C */
+	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+	u32 reserved2[1002];	/* 0x28 - 0xFCC */
+	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
+#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
+
+#endif	/* _TEGRA114_SYSCTR_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra.h
new file mode 100644
index 000000000..705ca5758
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_H_
+#define _TEGRA114_H_
+
+#define CONFIG_TEGRA114
+
+#define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T114 */
+#define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET	1752	/* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE        0x48    /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C    /* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU            4
+
+#endif /* TEGRA114_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
new file mode 100644
index 000000000..48197bc27
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra114/tegra114_spi.h
@@ -0,0 +1,41 @@
+/*
+ * NVIDIA Tegra SPI controller
+ *
+ * Copyright 2010-2013 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA114_SPI_H_
+#define _TEGRA114_SPI_H_
+
+#include <asm/types.h>
+
+int tegra114_spi_init(int *node_list, int count);
+int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs);
+struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode);
+void tegra114_spi_free_slave(struct spi_slave *slave);
+int tegra114_spi_claim_bus(struct spi_slave *slave);
+void tegra114_spi_cs_activate(struct spi_slave *slave);
+void tegra114_spi_cs_deactivate(struct spi_slave *slave);
+int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+		     const void *data_out, void *data_in, unsigned long flags);
+
+#endif	/* _TEGRA114_SPI_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/ahb.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/ahb.h
new file mode 100644
index 000000000..4e48c43bb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/ahb.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_AHB_H_
+#define _TEGRA124_AHB_H_
+
+struct ahb_ctlr {
+	u32 reserved0;			/* 00h */
+	u32 arbitration_disable;	/* _ARBITRATION_DISABLE_0,	04h */
+	u32 arbitration_priority_ctrl;	/* _ARBITRATION_PRIORITY_CTRL_0,08h */
+	u32 arbitration_usr_protect;	/* _ARBITRATION_USR_PROTECT_0,	0ch */
+	u32 gizmo_ahb_mem;		/* _GIZMO_AHB_MEM_0,		10h */
+	u32 gizmo_apb_dma;		/* _GIZMO_APB_DMA_0,		14h */
+	u32 reserved6[2];		/* 18h, 1ch */
+	u32 gizmo_usb;			/* _GIZMO_USB_0,		20h */
+	u32 gizmo_ahb_xbar_bridge;	/* _GIZMO_AHB_XBAR_BRIDGE_0,	24h */
+	u32 gizmo_cpu_ahb_bridge;	/* _GIZMO_CPU_AHB_BRIDGE_0,	28h */
+	u32 gizmo_cop_ahb_bridge;	/* _GIZMO_COP_AHB_BRIDGE_0,	2ch */
+	u32 gizmo_xbar_apb_ctlr;	/* _GIZMO_XBAR_APB_CTLR_0,	30h */
+	u32 gizmo_vcp_ahb_bridge;	/* _GIZMO_VCP_AHB_BRIDGE_0,	34h */
+	u32 reserved13[2];		/* 38h, 3ch */
+	u32 gizmo_nand;			/* _GIZMO_NAND_0,		40h */
+	u32 reserved15;			/* 44h */
+	u32 gizmo_sdmmc4;		/* _GIZMO_SDMMC4_0,		48h */
+	u32 reserved17;			/* 4ch */
+	u32 gizmo_se;			/* _GIZMO_SE_0,			50h */
+	u32 gizmo_tzram;		/* _GIZMO_TZRAM_0,		54h */
+	u32 reserved20[3];		/* 58h, 5ch, 60h */
+	u32 gizmo_bsev;			/* _GIZMO_BSEV_0,		64h */
+	u32 reserved22[3];		/* 68h, 6ch, 70h */
+	u32 gizmo_bsea;			/* _GIZMO_BSEA_0,		74h */
+	u32 gizmo_nor;			/* _GIZMO_NOR_0,		78h */
+	u32 gizmo_usb2;			/* _GIZMO_USB2_0,		7ch */
+	u32 gizmo_usb3;			/* _GIZMO_USB3_0,		80h */
+	u32 gizmo_sdmmc1;		/* _GIZMO_SDMMC1_0,		84h */
+	u32 gizmo_sdmmc2;		/* _GIZMO_SDMMC2_0,		88h */
+	u32 gizmo_sdmmc3;		/* _GIZMO_SDMMC3_0,		8ch */
+	u32 reserved30[13];		/* 90h ~ c0h */
+	u32 ahb_wrq_empty;		/* _AHB_WRQ_EMPTY_0,		c4h */
+	u32 reserved32[5];		/* c8h ~ d8h */
+	u32 ahb_mem_prefetch_cfg_x;	/* _AHB_MEM_PREFETCH_CFG_X_0,	dch */
+	u32 arbitration_xbar_ctrl;	/* _ARBITRATION_XBAR_CTRL_0,	e0h */
+	u32 ahb_mem_prefetch_cfg3;	/* _AHB_MEM_PREFETCH_CFG3_0,	e4h */
+	u32 ahb_mem_prefetch_cfg4;	/* _AHB_MEM_PREFETCH_CFG3_0,	e8h */
+	u32 avp_ppcs_rd_coh_status;	/* _AVP_PPCS_RD_COH_STATUS_0,	ech */
+	u32 ahb_mem_prefetch_cfg1;	/* _AHB_MEM_PREFETCH_CFG1_0,	f0h */
+	u32 ahb_mem_prefetch_cfg2;	/* _AHB_MEM_PREFETCH_CFG2_0,	f4h */
+	u32 ahbslvmem_status;		/* _AHBSLVMEM_STATUS_0, f8h */
+	/* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
+	u32 arbitration_ahb_mem_wrque_mst_id;
+	u32 arbitration_cpu_abort_addr;	/* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
+	u32 arbitration_cpu_abort_info;	/* _ARBITRATION_CPU_ABORT_INFO_0,104h */
+	u32 arbitration_cop_abort_addr;	/* _ARBITRATION_COP_ABORT_ADDR_0,108h */
+	u32 arbitration_cop_abort_info;	/* _ARBITRATION_COP_ABORT_INFO_0,10ch */
+	u32 reserved46[4];		/* 110h ~ 11ch */
+	u32 avpc_mccif_fifoctrl;	/* _AVPC_MCCIF_FIFOCTRL_0,	120h */
+	u32 timeout_wcoal_avpc;		/* _TIMEOUT_WCOAL_AVPC_0,	124h */
+	u32 mpcorelp_mccif_fifoctrl;	/* _MPCORELP_MCCIF_FIFOCTRL_0,	128h */
+	u32 mpcore_mccif_fifoctrl;	/* _MPCORE_MCCIF_FIFOCTRL_0,	12ch */
+	u32 axicif_fastsync_ctrl;	/* AXICIF_FASTSYNC_CTRL_0,	130h */
+	u32 axicif_fastsync_statistics;	/* _AXICIF_FASTSYNC_STATISTICS_0,134h */
+	/* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0,	138h */
+	u32 axicif_fastsync0_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
+	u32 axicif_fastsync1_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
+	u32 axicif_fastsync2_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
+	u32 axicif_fastsync0_mcclk_to_cpuclk;
+	/* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
+	u32 axicif_fastsync1_mcclk_to_cpuclk;
+	/* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
+	u32 axicif_fastsync2_mcclk_to_cpuclk;
+};
+
+#define PPSB_STOPCLK_ENABLE	(1 << 2)
+
+#define GIZ_ENABLE_SPLIT	(1 << 0)
+#define GIZ_ENB_FAST_REARB	(1 << 2)
+#define GIZ_DONT_SPLIT_AHB_WR	(1 << 7)
+
+#define GIZ_USB_IMMEDIATE	(1 << 18)
+
+/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
+#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE	(1 << 2)
+
+#endif	/* _TEGRA124_AHB_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock-tables.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock-tables.h
new file mode 100644
index 000000000..daf9a2b35
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock-tables.h
@@ -0,0 +1,496 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 clock PLL tables */
+
+#ifndef _TEGRA124_CLOCK_TABLES_H_
+#define _TEGRA124_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SoC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+
+	/*
+	 * These are clock IDs that are used in table clock_source[][]
+	 * but will not be assigned as a clock source for any peripheral.
+	 */
+	CLOCK_ID_DISPLAY2,
+	CLOCK_ID_CGENERAL2,
+	CLOCK_ID_CGENERAL3,
+	CLOCK_ID_MEMORY2,
+	CLOCK_ID_SRC2,
+
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 (DEVICES_L) */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_ISPB,
+	PERIPH_ID_RESERVED4,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_RESERVED13,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_TCW,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_RESERVED19,
+	PERIPH_ID_VI,
+	PERIPH_ID_RESERVED21,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_RESERVED25,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 (DEVICES_H) */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_RESERVED36,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_RESERVED38,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_XIO,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_I2C5,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_RESERVED49,
+	PERIPH_ID_HSI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_RESERVED53,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_MIPI_CAL,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_RESERVED60,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 (DEVICES_U) */
+	PERIPH_ID_RESERVED64,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_LA,
+	PERIPH_ID_TRACECLKIN,
+	PERIPH_ID_SOC_THERM,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_RESERVED80,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_TSEC,
+	PERIPH_ID_RESERVED84,
+	PERIPH_ID_RESERVED85,
+	PERIPH_ID_RESERVED86,
+	PERIPH_ID_EMUCIF,
+
+	/* 88 */
+	PERIPH_ID_RESERVED88,
+	PERIPH_ID_XUSB_HOST,
+	PERIPH_ID_RESERVED90,
+	PERIPH_ID_MSENC,
+	PERIPH_ID_RESERVED92,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_XUSB_DEV,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_V_RESERVED2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_V_RESERVED4,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 104 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 112 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_V_RESERVED17,
+	PERIPH_ID_V_RESERVED18,
+	PERIPH_ID_V_RESERVED19,
+	PERIPH_ID_V_RESERVED20,
+	PERIPH_ID_V_RESERVED21,
+	PERIPH_ID_V_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 120 */
+	PERIPH_ID_EXTPERIPH1,
+	PERIPH_ID_EXTPERIPH2,
+	PERIPH_ID_EXTPERIPH3,
+	PERIPH_ID_OOB,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_V_RESERVED30,
+	PERIPH_ID_V_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_SATACOLD,
+	PERIPH_ID_W_RESERVED2,
+	PERIPH_ID_W_RESERVED3,
+	PERIPH_ID_W_RESERVED4,
+	PERIPH_ID_W_RESERVED5,
+	PERIPH_ID_W_RESERVED6,
+	PERIPH_ID_W_RESERVED7,
+
+	/* 136 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_W_RESERVED9,
+	PERIPH_ID_W_RESERVED10,
+	PERIPH_ID_W_RESERVED11,
+	PERIPH_ID_W_RESERVED12,
+	PERIPH_ID_W_RESERVED13,
+	PERIPH_ID_XUSB_PADCTL,
+	PERIPH_ID_W_RESERVED15,
+
+	/* 144 */
+	PERIPH_ID_W_RESERVED16,
+	PERIPH_ID_W_RESERVED17,
+	PERIPH_ID_W_RESERVED18,
+	PERIPH_ID_W_RESERVED19,
+	PERIPH_ID_W_RESERVED20,
+	PERIPH_ID_ENTROPY,
+	PERIPH_ID_DDS,
+	PERIPH_ID_W_RESERVED23,
+
+	/* 152 */
+	PERIPH_ID_DP2,
+	PERIPH_ID_AMX0,
+	PERIPH_ID_ADX0,
+	PERIPH_ID_DVFS,
+	PERIPH_ID_XUSB_SS,
+	PERIPH_ID_W_RESERVED29,
+	PERIPH_ID_W_RESERVED30,
+	PERIPH_ID_W_RESERVED31,
+
+	PERIPH_ID_X_FIRST,
+	/* X word: 31:0 */
+	PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
+	PERIPH_ID_X_RESERVED1,
+	PERIPH_ID_X_RESERVED2,
+	PERIPH_ID_X_RESERVED3,
+	PERIPH_ID_CAM_MCLK,
+	PERIPH_ID_CAM_MCLK2,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_X_RESERVED7,
+
+	/* 168 */
+	PERIPH_ID_X_RESERVED8,
+	PERIPH_ID_X_RESERVED9,
+	PERIPH_ID_X_RESERVED10,
+	PERIPH_ID_VIM2_CLK,
+	PERIPH_ID_X_RESERVED12,
+	PERIPH_ID_X_RESERVED13,
+	PERIPH_ID_EMC_DLL,
+	PERIPH_ID_X_RESERVED15,
+
+	/* 176 */
+	PERIPH_ID_HDMI_AUDIO,
+	PERIPH_ID_CLK72MHZ,
+	PERIPH_ID_VIC,
+	PERIPH_ID_X_RESERVED19,
+	PERIPH_ID_ADX1,
+	PERIPH_ID_DPAUX,
+	PERIPH_ID_SOR0,
+	PERIPH_ID_X_RESERVED23,
+
+	/* 184 */
+	PERIPH_ID_GPU,
+	PERIPH_ID_AMX1,
+	PERIPH_ID_X_RESERVED26,
+	PERIPH_ID_X_RESERVED27,
+	PERIPH_ID_X_RESERVED28,
+	PERIPH_ID_X_RESERVED29,
+	PERIPH_ID_X_RESERVED30,
+	PERIPH_ID_X_RESERVED31,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_I2C5,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_10h,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_18h,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_1Bh,
+	PERIPHC_1Ch,
+	PERIPHC_HSI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_22h,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_25h,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_DTV,
+
+	/* 0x38 */
+	PERIPHC_38h,
+	PERIPHC_39h,
+	PERIPHC_3ah,
+	PERIPHC_3bh,
+	PERIPHC_MSENC,
+	PERIPHC_TSEC,
+	PERIPHC_3eh,
+	PERIPHC_OSC,
+
+	PERIPHC_VW_FIRST,
+	/* 0x40 */
+	PERIPHC_40h = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x48 */
+	PERIPHC_AUDIO,
+	PERIPHC_49h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x50 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_52h,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_55h,
+	PERIPHC_56h,
+	PERIPHC_57h,
+
+	/* 0x58 */
+	PERIPHC_58h,
+	PERIPHC_59h,
+	PERIPHC_5ah,
+	PERIPHC_5bh,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,		/* 0x428 */
+	PERIPHC_5fh,
+
+	PERIPHC_X_FIRST,
+	/* 0x60 */
+	PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST,	/* 0x600 */
+	PERIPHC_XUSB_FALCON,
+	PERIPHC_XUSB_FS,
+	PERIPHC_XUSB_CORE_DEV,
+	PERIPHC_XUSB_SS,
+	PERIPHC_CILAB,
+	PERIPHC_CILCD,
+	PERIPHC_CILE,
+
+	/* 0x68 */
+	PERIPHC_DSIA_LP,
+	PERIPHC_DSIB_LP,
+	PERIPHC_ENTROPY,
+	PERIPHC_DVFS_REF,
+	PERIPHC_DVFS_SOC,
+	PERIPHC_TRACECLKIN,
+	PERIPHC_ADX0,
+	PERIPHC_AMX0,
+
+	/* 0x70 */
+	PERIPHC_EMC_LATENCY,
+	PERIPHC_SOC_THERM,
+	PERIPHC_72h,
+	PERIPHC_73h,
+	PERIPHC_74h,
+	PERIPHC_75h,
+	PERIPHC_VI_SENSOR2,
+	PERIPHC_I2C6,
+
+	/* 0x78 */
+	PERIPHC_78h,
+	PERIPHC_EMC_DLL,
+	PERIPHC_HDMI_AUDIO,
+	PERIPHC_CLK72MHZ,
+	PERIPHC_ADX1,
+	PERIPHC_AMX1,
+	PERIPHC_VIC,
+	PERIPHC_7fh,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA124_CLOCK_TABLES_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock.h
new file mode 100644
index 000000000..8e39d21a7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/clock.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 clock control definitions */
+
+#ifndef _TEGRA124_CLOCK_H_
+#define _TEGRA124_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+#endif	/* _TEGRA124_CLOCK_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/flow.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/flow.h
new file mode 100644
index 000000000..0db1881bc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/flow.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_FLOW_H_
+#define _TEGRA124_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;	/* offset 0x00 */
+	u32 halt_cop_events;	/* offset 0x04 */
+	u32 cpu_csr;		/* offset 0x08 */
+	u32 cop_csr;		/* offset 0x0c */
+	u32 xrq_events;		/* offset 0x10 */
+	u32 halt_cpu1_events;	/* offset 0x14 */
+	u32 cpu1_csr;		/* offset 0x18 */
+	u32 halt_cpu2_events;	/* offset 0x1c */
+	u32 cpu2_csr;		/* offset 0x20 */
+	u32 halt_cpu3_events;	/* offset 0x24 */
+	u32 cpu3_csr;		/* offset 0x28 */
+	u32 cluster_control;	/* offset 0x2c */
+	u32 halt_cop1_events;	/* offset 0x30 */
+	u32 halt_cop1_csr;	/* offset 0x34 */
+	u32 cpu_pwr_csr;	/* offset 0x38 */
+	u32 mpid;		/* offset 0x3c */
+	u32 ram_repair;		/* offset 0x40 */
+};
+
+/* HALT_COP_EVENTS_0, 0x04 */
+#define EVENT_MSEC		(1 << 24)
+#define EVENT_USEC		(1 << 25)
+#define EVENT_JTAG		(1 << 28)
+#define EVENT_MODE_STOP		(2 << 29)
+
+/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
+#define ACTIVE_LP		(1 << 0)
+
+#endif	/*  _TEGRA124_FLOW_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/funcmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/funcmux.h
new file mode 100644
index 000000000..df94d135f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/funcmux.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#ifndef _TEGRA124_FUNCMUX_H_
+#define _TEGRA124_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART1_KBC = 0,
+	FUNCMUX_UART4_GPIO = 0,
+};
+#endif	/* _TEGRA124_FUNCMUX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
new file mode 100644
index 000000000..440cbbfa3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GP_PADCTRL_H_
+#define _TEGRA124_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	reserved1;	/* 0x8C: */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	reserved2[3];	/* 0xA4 - 0xAC: */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	reserved3[9];	/* 0xC8-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+	u32	reserved4[3];	/* 0xF0-0xF8: */
+	u32	ddccfg;		/* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+	u32	gmacfg;		/* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+	u32	reserved5[3];	/* 0x104-0x10C: */
+	u32	gmecfg;		/* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+	u32	gmfcfg;		/* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+	u32	gmgcfg;		/* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+	u32	gmhcfg;		/* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+	u32	owrcfg;		/* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+	u32	uadcfg;		/* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+	u32	reserved6;	/* 0x128: */
+	u32	dev3cfg;	/* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+	u32	reserved7[2];	/* 0x130 - 0x134: */
+	u32	ceccfg;		/* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+	u32	reserved8[22];	/* 0x13C - 0x190: */
+	u32	atcfg6;		/* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+	u32	dap5cfg;	/* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+	u32	vbuscfg;	/* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+	u32	aocfg3;		/* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+	u32	hvccfg0;	/* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+	u32	sdio4cfg;	/* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+	u32	aocfg0;		/* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF	0
+#define SDIOCFG_DRVDN_SLWR	0
+#define SDIOCFG_DRVUP		0x24
+#define SDIOCFG_DRVDN		0x14
+
+#endif	/* _TEGRA124_GP_PADCTRL_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gpio.h
new file mode 100644
index 000000000..1a6dcb871
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/gpio.h
@@ -0,0 +1,303 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GPIO_H_
+#define _TEGRA124_GPIO_H_
+
+/*
+ * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+	uint gpio_masked_config[TEGRA_GPIO_PORTS];
+	uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_in[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+	GPIO_PA0 = 0,	/* pin 0 */
+	GPIO_PA1,
+	GPIO_PA2,
+	GPIO_PA3,
+	GPIO_PA4,
+	GPIO_PA5,
+	GPIO_PA6,
+	GPIO_PA7,
+	GPIO_PB0,	/* pin 8 */
+	GPIO_PB1,
+	GPIO_PB2,
+	GPIO_PB3,
+	GPIO_PB4,
+	GPIO_PB5,
+	GPIO_PB6,
+	GPIO_PB7,
+	GPIO_PC0,	/* pin 16 */
+	GPIO_PC1,
+	GPIO_PC2,
+	GPIO_PC3,
+	GPIO_PC4,
+	GPIO_PC5,
+	GPIO_PC6,
+	GPIO_PC7,
+	GPIO_PD0,	/* pin 24 */
+	GPIO_PD1,
+	GPIO_PD2,
+	GPIO_PD3,
+	GPIO_PD4,
+	GPIO_PD5,
+	GPIO_PD6,
+	GPIO_PD7,
+	GPIO_PE0,	/* pin 32 */
+	GPIO_PE1,
+	GPIO_PE2,
+	GPIO_PE3,
+	GPIO_PE4,
+	GPIO_PE5,
+	GPIO_PE6,
+	GPIO_PE7,
+	GPIO_PF0,	/* pin 40 */
+	GPIO_PF1,
+	GPIO_PF2,
+	GPIO_PF3,
+	GPIO_PF4,
+	GPIO_PF5,
+	GPIO_PF6,
+	GPIO_PF7,
+	GPIO_PG0,	/* pin 48 */
+	GPIO_PG1,
+	GPIO_PG2,
+	GPIO_PG3,
+	GPIO_PG4,
+	GPIO_PG5,
+	GPIO_PG6,
+	GPIO_PG7,
+	GPIO_PH0,	/* pin 56 */
+	GPIO_PH1,
+	GPIO_PH2,
+	GPIO_PH3,
+	GPIO_PH4,
+	GPIO_PH5,
+	GPIO_PH6,
+	GPIO_PH7,
+	GPIO_PI0,	/* pin 64 */
+	GPIO_PI1,
+	GPIO_PI2,
+	GPIO_PI3,
+	GPIO_PI4,
+	GPIO_PI5,
+	GPIO_PI6,
+	GPIO_PI7,
+	GPIO_PJ0,	/* pin 72 */
+	GPIO_PJ1,
+	GPIO_PJ2,
+	GPIO_PJ3,
+	GPIO_PJ4,
+	GPIO_PJ5,
+	GPIO_PJ6,
+	GPIO_PJ7,
+	GPIO_PK0,	/* pin 80 */
+	GPIO_PK1,
+	GPIO_PK2,
+	GPIO_PK3,
+	GPIO_PK4,
+	GPIO_PK5,
+	GPIO_PK6,
+	GPIO_PK7,
+	GPIO_PL0,	/* pin 88 */
+	GPIO_PL1,
+	GPIO_PL2,
+	GPIO_PL3,
+	GPIO_PL4,
+	GPIO_PL5,
+	GPIO_PL6,
+	GPIO_PL7,
+	GPIO_PM0,	/* pin 96 */
+	GPIO_PM1,
+	GPIO_PM2,
+	GPIO_PM3,
+	GPIO_PM4,
+	GPIO_PM5,
+	GPIO_PM6,
+	GPIO_PM7,
+	GPIO_PN0,	/* pin 104 */
+	GPIO_PN1,
+	GPIO_PN2,
+	GPIO_PN3,
+	GPIO_PN4,
+	GPIO_PN5,
+	GPIO_PN6,
+	GPIO_PN7,
+	GPIO_PO0,	/* pin 112 */
+	GPIO_PO1,
+	GPIO_PO2,
+	GPIO_PO3,
+	GPIO_PO4,
+	GPIO_PO5,
+	GPIO_PO6,
+	GPIO_PO7,
+	GPIO_PP0,	/* pin 120 */
+	GPIO_PP1,
+	GPIO_PP2,
+	GPIO_PP3,
+	GPIO_PP4,
+	GPIO_PP5,
+	GPIO_PP6,
+	GPIO_PP7,
+	GPIO_PQ0,	/* pin 128 */
+	GPIO_PQ1,
+	GPIO_PQ2,
+	GPIO_PQ3,
+	GPIO_PQ4,
+	GPIO_PQ5,
+	GPIO_PQ6,
+	GPIO_PQ7,
+	GPIO_PR0,	/* pin 136 */
+	GPIO_PR1,
+	GPIO_PR2,
+	GPIO_PR3,
+	GPIO_PR4,
+	GPIO_PR5,
+	GPIO_PR6,
+	GPIO_PR7,
+	GPIO_PS0,	/* pin 144 */
+	GPIO_PS1,
+	GPIO_PS2,
+	GPIO_PS3,
+	GPIO_PS4,
+	GPIO_PS5,
+	GPIO_PS6,
+	GPIO_PS7,
+	GPIO_PT0,	/* pin 152 */
+	GPIO_PT1,
+	GPIO_PT2,
+	GPIO_PT3,
+	GPIO_PT4,
+	GPIO_PT5,
+	GPIO_PT6,
+	GPIO_PT7,
+	GPIO_PU0,	/* pin 160 */
+	GPIO_PU1,
+	GPIO_PU2,
+	GPIO_PU3,
+	GPIO_PU4,
+	GPIO_PU5,
+	GPIO_PU6,
+	GPIO_PU7,
+	GPIO_PV0,	/* pin 168 */
+	GPIO_PV1,
+	GPIO_PV2,
+	GPIO_PV3,
+	GPIO_PV4,
+	GPIO_PV5,
+	GPIO_PV6,
+	GPIO_PV7,
+	GPIO_PW0,	/* pin 176 */
+	GPIO_PW1,
+	GPIO_PW2,
+	GPIO_PW3,
+	GPIO_PW4,
+	GPIO_PW5,
+	GPIO_PW6,
+	GPIO_PW7,
+	GPIO_PX0,	/* pin 184 */
+	GPIO_PX1,
+	GPIO_PX2,
+	GPIO_PX3,
+	GPIO_PX4,
+	GPIO_PX5,
+	GPIO_PX6,
+	GPIO_PX7,
+	GPIO_PY0,	/* pin 192 */
+	GPIO_PY1,
+	GPIO_PY2,
+	GPIO_PY3,
+	GPIO_PY4,
+	GPIO_PY5,
+	GPIO_PY6,
+	GPIO_PY7,
+	GPIO_PZ0,	/* pin 200 */
+	GPIO_PZ1,
+	GPIO_PZ2,
+	GPIO_PZ3,
+	GPIO_PZ4,
+	GPIO_PZ5,
+	GPIO_PZ6,
+	GPIO_PZ7,
+	GPIO_PAA0,	/* pin 208 */
+	GPIO_PAA1,
+	GPIO_PAA2,
+	GPIO_PAA3,
+	GPIO_PAA4,
+	GPIO_PAA5,
+	GPIO_PAA6,
+	GPIO_PAA7,
+	GPIO_PBB0,	/* pin 216 */
+	GPIO_PBB1,
+	GPIO_PBB2,
+	GPIO_PBB3,
+	GPIO_PBB4,
+	GPIO_PBB5,
+	GPIO_PBB6,
+	GPIO_PBB7,
+	GPIO_PCC0,	/* pin 224 */
+	GPIO_PCC1,
+	GPIO_PCC2,
+	GPIO_PCC3,
+	GPIO_PCC4,
+	GPIO_PCC5,
+	GPIO_PCC6,
+	GPIO_PCC7,
+	GPIO_PDD0,	/* pin 232 */
+	GPIO_PDD1,
+	GPIO_PDD2,
+	GPIO_PDD3,
+	GPIO_PDD4,
+	GPIO_PDD5,
+	GPIO_PDD6,
+	GPIO_PDD7,
+	GPIO_PEE0,	/* pin 240 */
+	GPIO_PEE1,
+	GPIO_PEE2,
+	GPIO_PEE3,
+	GPIO_PEE4,
+	GPIO_PEE5,
+	GPIO_PEE6,
+	GPIO_PEE7,
+	GPIO_PFF0,	/* pin 248 */
+	GPIO_PFF1,
+	GPIO_PFF2,
+	GPIO_PFF3,
+	GPIO_PFF4,
+	GPIO_PFF5,
+	GPIO_PFF6,
+	GPIO_PFF7,	/* pin 255 */
+};
+
+#endif	/* _TEGRA124_GPIO_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/hardware.h
new file mode 100644
index 000000000..114fce8ad
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/hardware.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_HARDWARE_H_
+#define _TEGRA124_HARDWARE_H_
+
+/*
+ * Include Tegra-specific hardware definitions
+ * Nothing needed currently for Tegra124
+ */
+
+#endif /* _TEGRA124_HARDWARE_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pinmux.h
new file mode 100644
index 000000000..c49801c21
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -0,0 +1,342 @@
+/*
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PINMUX_H_
+#define _TEGRA124_PINMUX_H_
+
+enum pmux_pingrp {
+	PMUX_PINGRP_ULPI_DATA0_PO1,
+	PMUX_PINGRP_ULPI_DATA1_PO2,
+	PMUX_PINGRP_ULPI_DATA2_PO3,
+	PMUX_PINGRP_ULPI_DATA3_PO4,
+	PMUX_PINGRP_ULPI_DATA4_PO5,
+	PMUX_PINGRP_ULPI_DATA5_PO6,
+	PMUX_PINGRP_ULPI_DATA6_PO7,
+	PMUX_PINGRP_ULPI_DATA7_PO0,
+	PMUX_PINGRP_ULPI_CLK_PY0,
+	PMUX_PINGRP_ULPI_DIR_PY1,
+	PMUX_PINGRP_ULPI_NXT_PY2,
+	PMUX_PINGRP_ULPI_STP_PY3,
+	PMUX_PINGRP_DAP3_FS_PP0,
+	PMUX_PINGRP_DAP3_DIN_PP1,
+	PMUX_PINGRP_DAP3_DOUT_PP2,
+	PMUX_PINGRP_DAP3_SCLK_PP3,
+	PMUX_PINGRP_PV0,
+	PMUX_PINGRP_PV1,
+	PMUX_PINGRP_SDMMC1_CLK_PZ0,
+	PMUX_PINGRP_SDMMC1_CMD_PZ1,
+	PMUX_PINGRP_SDMMC1_DAT3_PY4,
+	PMUX_PINGRP_SDMMC1_DAT2_PY5,
+	PMUX_PINGRP_SDMMC1_DAT1_PY6,
+	PMUX_PINGRP_SDMMC1_DAT0_PY7,
+	PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+	PMUX_PINGRP_CLK2_REQ_PCC5,
+	PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+	PMUX_PINGRP_DDC_SCL_PV4,
+	PMUX_PINGRP_DDC_SDA_PV5,
+	PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+	PMUX_PINGRP_UART2_TXD_PC2,
+	PMUX_PINGRP_UART2_RTS_N_PJ6,
+	PMUX_PINGRP_UART2_CTS_N_PJ5,
+	PMUX_PINGRP_UART3_TXD_PW6,
+	PMUX_PINGRP_UART3_RXD_PW7,
+	PMUX_PINGRP_UART3_CTS_N_PA1,
+	PMUX_PINGRP_UART3_RTS_N_PC0,
+	PMUX_PINGRP_PU0,
+	PMUX_PINGRP_PU1,
+	PMUX_PINGRP_PU2,
+	PMUX_PINGRP_PU3,
+	PMUX_PINGRP_PU4,
+	PMUX_PINGRP_PU5,
+	PMUX_PINGRP_PU6,
+	PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+	PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+	PMUX_PINGRP_DAP4_FS_PP4,
+	PMUX_PINGRP_DAP4_DIN_PP5,
+	PMUX_PINGRP_DAP4_DOUT_PP6,
+	PMUX_PINGRP_DAP4_SCLK_PP7,
+	PMUX_PINGRP_CLK3_OUT_PEE0,
+	PMUX_PINGRP_CLK3_REQ_PEE1,
+	PMUX_PINGRP_PC7,
+	PMUX_PINGRP_PI5,
+	PMUX_PINGRP_PI7,
+	PMUX_PINGRP_PK0,
+	PMUX_PINGRP_PK1,
+	PMUX_PINGRP_PJ0,
+	PMUX_PINGRP_PJ2,
+	PMUX_PINGRP_PK3,
+	PMUX_PINGRP_PK4,
+	PMUX_PINGRP_PK2,
+	PMUX_PINGRP_PI3,
+	PMUX_PINGRP_PI6,
+	PMUX_PINGRP_PG0,
+	PMUX_PINGRP_PG1,
+	PMUX_PINGRP_PG2,
+	PMUX_PINGRP_PG3,
+	PMUX_PINGRP_PG4,
+	PMUX_PINGRP_PG5,
+	PMUX_PINGRP_PG6,
+	PMUX_PINGRP_PG7,
+	PMUX_PINGRP_PH0,
+	PMUX_PINGRP_PH1,
+	PMUX_PINGRP_PH2,
+	PMUX_PINGRP_PH3,
+	PMUX_PINGRP_PH4,
+	PMUX_PINGRP_PH5,
+	PMUX_PINGRP_PH6,
+	PMUX_PINGRP_PH7,
+	PMUX_PINGRP_PJ7,
+	PMUX_PINGRP_PB0,
+	PMUX_PINGRP_PB1,
+	PMUX_PINGRP_PK7,
+	PMUX_PINGRP_PI0,
+	PMUX_PINGRP_PI1,
+	PMUX_PINGRP_PI2,
+	PMUX_PINGRP_PI4,
+	PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+	PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+	PMUX_PINGRP_SDMMC4_CLK_PCC4,
+	PMUX_PINGRP_SDMMC4_CMD_PT7,
+	PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+	PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+	PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+	PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+	PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+	PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+	PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+	PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+	PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+	PMUX_PINGRP_PCC1,
+	PMUX_PINGRP_PBB0,
+	PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+	PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+	PMUX_PINGRP_PBB3,
+	PMUX_PINGRP_PBB4,
+	PMUX_PINGRP_PBB5,
+	PMUX_PINGRP_PBB6,
+	PMUX_PINGRP_PBB7,
+	PMUX_PINGRP_PCC2,
+	PMUX_PINGRP_JTAG_RTCK,
+	PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+	PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+	PMUX_PINGRP_KB_ROW0_PR0,
+	PMUX_PINGRP_KB_ROW1_PR1,
+	PMUX_PINGRP_KB_ROW2_PR2,
+	PMUX_PINGRP_KB_ROW3_PR3,
+	PMUX_PINGRP_KB_ROW4_PR4,
+	PMUX_PINGRP_KB_ROW5_PR5,
+	PMUX_PINGRP_KB_ROW6_PR6,
+	PMUX_PINGRP_KB_ROW7_PR7,
+	PMUX_PINGRP_KB_ROW8_PS0,
+	PMUX_PINGRP_KB_ROW9_PS1,
+	PMUX_PINGRP_KB_ROW10_PS2,
+	PMUX_PINGRP_KB_ROW11_PS3,
+	PMUX_PINGRP_KB_ROW12_PS4,
+	PMUX_PINGRP_KB_ROW13_PS5,
+	PMUX_PINGRP_KB_ROW14_PS6,
+	PMUX_PINGRP_KB_ROW15_PS7,
+	PMUX_PINGRP_KB_COL0_PQ0,
+	PMUX_PINGRP_KB_COL1_PQ1,
+	PMUX_PINGRP_KB_COL2_PQ2,
+	PMUX_PINGRP_KB_COL3_PQ3,
+	PMUX_PINGRP_KB_COL4_PQ4,
+	PMUX_PINGRP_KB_COL5_PQ5,
+	PMUX_PINGRP_KB_COL6_PQ6,
+	PMUX_PINGRP_KB_COL7_PQ7,
+	PMUX_PINGRP_CLK_32K_OUT_PA0,
+	PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
+	PMUX_PINGRP_CPU_PWR_REQ,
+	PMUX_PINGRP_PWR_INT_N,
+	PMUX_PINGRP_CLK_32K_IN,
+	PMUX_PINGRP_OWR,
+	PMUX_PINGRP_DAP1_FS_PN0,
+	PMUX_PINGRP_DAP1_DIN_PN1,
+	PMUX_PINGRP_DAP1_DOUT_PN2,
+	PMUX_PINGRP_DAP1_SCLK_PN3,
+	PMUX_PINGRP_DAP_MCLK1_REQ_PEE2,
+	PMUX_PINGRP_DAP_MCLK1_PW4,
+	PMUX_PINGRP_SPDIF_IN_PK6,
+	PMUX_PINGRP_SPDIF_OUT_PK5,
+	PMUX_PINGRP_DAP2_FS_PA2,
+	PMUX_PINGRP_DAP2_DIN_PA4,
+	PMUX_PINGRP_DAP2_DOUT_PA5,
+	PMUX_PINGRP_DAP2_SCLK_PA3,
+	PMUX_PINGRP_DVFS_PWM_PX0,
+	PMUX_PINGRP_GPIO_X1_AUD_PX1,
+	PMUX_PINGRP_GPIO_X3_AUD_PX3,
+	PMUX_PINGRP_DVFS_CLK_PX2,
+	PMUX_PINGRP_GPIO_X4_AUD_PX4,
+	PMUX_PINGRP_GPIO_X5_AUD_PX5,
+	PMUX_PINGRP_GPIO_X6_AUD_PX6,
+	PMUX_PINGRP_GPIO_X7_AUD_PX7,
+	PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+	PMUX_PINGRP_SDMMC3_CMD_PA7,
+	PMUX_PINGRP_SDMMC3_DAT0_PB7,
+	PMUX_PINGRP_SDMMC3_DAT1_PB6,
+	PMUX_PINGRP_SDMMC3_DAT2_PB5,
+	PMUX_PINGRP_SDMMC3_DAT3_PB4,
+	PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
+	PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+	PMUX_PINGRP_PEX_WAKE_N_PDD3,
+	PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
+	PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+	PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+	PMUX_PINGRP_SDMMC1_WP_N_PV3,
+	PMUX_PINGRP_SDMMC3_CD_N_PV2,
+	PMUX_PINGRP_GPIO_W2_AUD_PW2,
+	PMUX_PINGRP_GPIO_W3_AUD_PW3,
+	PMUX_PINGRP_USB_VBUS_EN0_PN4,
+	PMUX_PINGRP_USB_VBUS_EN1_PN5,
+	PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+	PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+	PMUX_PINGRP_GMI_CLK_LB,
+	PMUX_PINGRP_RESET_OUT_N,
+	PMUX_PINGRP_KB_ROW16_PT0,
+	PMUX_PINGRP_KB_ROW17_PT1,
+	PMUX_PINGRP_USB_VBUS_EN2_PFF1,
+	PMUX_PINGRP_PFF2,
+	PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
+	PMUX_PINGRP_COUNT,
+};
+
+enum pmux_drvgrp {
+	PMUX_DRVGRP_AO1,
+	PMUX_DRVGRP_AO2,
+	PMUX_DRVGRP_AT1,
+	PMUX_DRVGRP_AT2,
+	PMUX_DRVGRP_AT3,
+	PMUX_DRVGRP_AT4,
+	PMUX_DRVGRP_AT5,
+	PMUX_DRVGRP_CDEV1,
+	PMUX_DRVGRP_CDEV2,
+	PMUX_DRVGRP_DAP1 = (0x28 / 4),
+	PMUX_DRVGRP_DAP2,
+	PMUX_DRVGRP_DAP3,
+	PMUX_DRVGRP_DAP4,
+	PMUX_DRVGRP_DBG,
+	PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+	PMUX_DRVGRP_SPI,
+	PMUX_DRVGRP_UAA,
+	PMUX_DRVGRP_UAB,
+	PMUX_DRVGRP_UART2,
+	PMUX_DRVGRP_UART3,
+	PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+	PMUX_DRVGRP_DDC = (0x94 / 4),
+	PMUX_DRVGRP_GMA,
+	PMUX_DRVGRP_GME = (0xa8 / 4),
+	PMUX_DRVGRP_GMF,
+	PMUX_DRVGRP_GMG,
+	PMUX_DRVGRP_GMH,
+	PMUX_DRVGRP_OWR,
+	PMUX_DRVGRP_UDA,
+	PMUX_DRVGRP_GPV,
+	PMUX_DRVGRP_DEV3,
+	PMUX_DRVGRP_CEC = (0xd0 / 4),
+	PMUX_DRVGRP_AT6 = (0x12c / 4),
+	PMUX_DRVGRP_DAP5,
+	PMUX_DRVGRP_USB_VBUS_EN,
+	PMUX_DRVGRP_AO3 = (0x140 / 4),
+	PMUX_DRVGRP_AO0 = (0x148 / 4),
+	PMUX_DRVGRP_HV0,
+	PMUX_DRVGRP_SDIO4 = (0x15c / 4),
+	PMUX_DRVGRP_AO4,
+	PMUX_DRVGRP_COUNT,
+};
+
+enum pmux_func {
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CCLA,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLDVFS,
+	PMUX_FUNC_CLK,
+	PMUX_FUNC_CLK12,
+	PMUX_FUNC_CPU,
+	PMUX_FUNC_DAP,
+	PMUX_FUNC_DAP1,
+	PMUX_FUNC_DAP2,
+	PMUX_FUNC_DEV3,
+	PMUX_FUNC_DISPLAYA,
+	PMUX_FUNC_DISPLAYA_ALT,
+	PMUX_FUNC_DISPLAYB,
+	PMUX_FUNC_DP,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_EXTPERIPH1,
+	PMUX_FUNC_EXTPERIPH2,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_ALT,
+	PMUX_FUNC_HDA,
+	PMUX_FUNC_HSI,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_I2C4,
+	PMUX_FUNC_I2CPWR,
+	PMUX_FUNC_I2S0,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4,
+	PMUX_FUNC_IRDA,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PE,
+	PMUX_FUNC_PE0,
+	PMUX_FUNC_PE1,
+	PMUX_FUNC_PMI,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_PWRON,
+	PMUX_FUNC_RESET_OUT_N,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SATA,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC2,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SDMMC4,
+	PMUX_FUNC_SOC,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_SPI5,
+	PMUX_FUNC_SPI6,
+	PMUX_FUNC_SYS,
+	PMUX_FUNC_TMDS,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_USB,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_ALT1,
+	PMUX_FUNC_VI_ALT3,
+	PMUX_FUNC_VIMCLK2,
+	PMUX_FUNC_VIMCLK2_ALT,
+	PMUX_FUNC_RSVD1,
+	PMUX_FUNC_RSVD2,
+	PMUX_FUNC_RSVD3,
+	PMUX_FUNC_RSVD4,
+	PMUX_FUNC_COUNT,
+};
+
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_RCV_SEL
+#define TEGRA_PMX_HAS_DRVGRPS
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA124_PINMUX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pmu.h
new file mode 100644
index 000000000..b10100a63
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/pmu.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PMU_H_
+#define _TEGRA124_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif	/* _TEGRA124_PMU_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/spl.h
new file mode 100644
index 000000000..e2663954b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/spl.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM 1
+
+#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/sysctr.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/sysctr.h
new file mode 100644
index 000000000..3f0309b78
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/sysctr.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_SYSCTR_H_
+#define _TEGRA124_SYSCTR_H_
+
+struct sysctr_ctlr {
+	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
+	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
+	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+	u32 reserved1[4];	/* 0x10 - 0x1C */
+	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+	u32 reserved2[1002];	/* 0x28 - 0xFCC */
+	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
+#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
+
+#endif	/* _TEGRA124_SYSCTR_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/tegra.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/tegra.h
new file mode 100644
index 000000000..86ebd1945
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra124/tegra.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_H_
+#define _TEGRA124_H_
+
+#define CONFIG_TEGRA124
+
+#define NV_PA_SDRAM_BASE	0x80000000
+#define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
+#define NV_PA_MC_BASE		0x70019000	/* Mem Ctlr regs (MCB, etc.) */
+#define NV_PA_AHB_BASE		0x6000C000	/* System regs (AHB, etc.) */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET	1704	/* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE	0x48	/* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR	0x4C	/* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU		4
+#define MCB_EMEM_ARB_OVERRIDE	(NV_PA_MC_BASE + 0xE8)
+
+#define TEGRA_USB1_BASE		0x7D000000
+
+#endif /* _TEGRA124_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock-tables.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock-tables.h
new file mode 100644
index 000000000..a09cb0197
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock-tables.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Tegra20 clock PLL tables */
+
+#ifndef _CLOCK_TABLES_H_
+#define _CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SOC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+
+	CLOCK_ID_COUNT,	/* number of clocks */
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_RESERVED1,
+	PERIPH_ID_RESERVED2,
+	PERIPH_ID_AC97,
+	PERIPH_ID_RTC,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_TWC,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_IDE,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_RESERVED30,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_XIO,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_DVC_I2C,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_RESERVED74,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_RESERVED79,
+
+	/* 80 */
+	PERIPH_ID_RESERVED80,
+	PERIPH_ID_RESERVED81,
+	PERIPH_ID_RESERVED82,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+	PERIPH_ID_SYNC_CLK_DOUBLER,
+	PERIPH_ID_CLK_M_DOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUS_OUT,
+	PERIPH_ID_DEV2_OUT,
+	PERIPH_ID_DEV1_OUT,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
+#define PERIPH_REG(id) ((id) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range, and not a simple PLL */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
+		(id) < CLOCK_ID_FIRST_SIMPLE)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _CLOCK_TABLES_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock.h
new file mode 100644
index 000000000..889c65a16
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/clock.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Tegra20 clock control functions */
+
+#ifndef _TEGRA20_CLOCK_H
+#define _TEGRA20_CLOCK_H
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          30
+#define OSC_FREQ_MASK           (3U << OSC_FREQ_SHIFT)
+
+#endif	/* _TEGRA20_CLOCK_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/dc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/dc.h
new file mode 100644
index 000000000..20790b6c0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/dc.h
@@ -0,0 +1,529 @@
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DC_H
+#define __ASM_ARCH_TEGRA_DC_H
+
+/* Register definitions for the Tegra display controller */
+
+/* CMD register 0x000 ~ 0x43 */
+struct dc_cmd_reg {
+	/* Address 0x000 ~ 0x002 */
+	uint gen_incr_syncpt;		/* _CMD_GENERAL_INCR_SYNCPT_0 */
+	uint gen_incr_syncpt_ctrl;	/* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
+	uint gen_incr_syncpt_err;	/* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
+
+	uint reserved0[5];		/* reserved_0[5] */
+
+	/* Address 0x008 ~ 0x00a */
+	uint win_a_incr_syncpt;		/* _CMD_WIN_A_INCR_SYNCPT_0 */
+	uint win_a_incr_syncpt_ctrl;	/* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
+	uint win_a_incr_syncpt_err;	/* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
+
+	uint reserved1[5];		/* reserved_1[5] */
+
+	/* Address 0x010 ~ 0x012 */
+	uint win_b_incr_syncpt;		/* _CMD_WIN_B_INCR_SYNCPT_0 */
+	uint win_b_incr_syncpt_ctrl;	/* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
+	uint win_b_incr_syncpt_err;	/* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */
+
+	uint reserved2[5];		/* reserved_2[5] */
+
+	/* Address 0x018 ~ 0x01a */
+	uint win_c_incr_syncpt;		/* _CMD_WIN_C_INCR_SYNCPT_0 */
+	uint win_c_incr_syncpt_ctrl;	/* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */
+	uint win_c_incr_syncpt_err;	/* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */
+
+	uint reserved3[13];		/* reserved_3[13] */
+
+	/* Address 0x028 */
+	uint cont_syncpt_vsync;		/* _CMD_CONT_SYNCPT_VSYNC_0 */
+
+	uint reserved4[7];		/* reserved_4[7] */
+
+	/* Address 0x030 ~ 0x033 */
+	uint ctxsw;			/* _CMD_CTXSW_0 */
+	uint disp_cmd_opt0;		/* _CMD_DISPLAY_COMMAND_OPTION0_0 */
+	uint disp_cmd;			/* _CMD_DISPLAY_COMMAND_0 */
+	uint sig_raise;			/* _CMD_SIGNAL_RAISE_0 */
+
+	uint reserved5[2];		/* reserved_0[2] */
+
+	/* Address 0x036 ~ 0x03e */
+	uint disp_pow_ctrl;		/* _CMD_DISPLAY_POWER_CONTROL_0 */
+	uint int_stat;			/* _CMD_INT_STATUS_0 */
+	uint int_mask;			/* _CMD_INT_MASK_0 */
+	uint int_enb;			/* _CMD_INT_ENABLE_0 */
+	uint int_type;			/* _CMD_INT_TYPE_0 */
+	uint int_polarity;		/* _CMD_INT_POLARITY_0 */
+	uint sig_raise1;		/* _CMD_SIGNAL_RAISE1_0 */
+	uint sig_raise2;		/* _CMD_SIGNAL_RAISE2_0 */
+	uint sig_raise3;		/* _CMD_SIGNAL_RAISE3_0 */
+
+	uint reserved6;			/* reserved_6 */
+
+	/* Address 0x040 ~ 0x043 */
+	uint state_access;		/* _CMD_STATE_ACCESS_0 */
+	uint state_ctrl;		/* _CMD_STATE_CONTROL_0 */
+	uint disp_win_header;		/* _CMD_DISPLAY_WINDOW_HEADER_0 */
+	uint reg_act_ctrl;		/* _CMD_REG_ACT_CONTROL_0 */
+};
+
+enum {
+	PIN_REG_COUNT		= 4,
+	PIN_OUTPUT_SEL_COUNT	= 7,
+};
+
+/* COM register 0x300 ~ 0x329 */
+struct dc_com_reg {
+	/* Address 0x300 ~ 0x301 */
+	uint crc_ctrl;			/* _COM_CRC_CONTROL_0 */
+	uint crc_checksum;		/* _COM_CRC_CHECKSUM_0 */
+
+	/* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */
+	uint pin_output_enb[PIN_REG_COUNT];
+
+	/* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */
+	uint pin_output_polarity[PIN_REG_COUNT];
+
+	/* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */
+	uint pin_output_data[PIN_REG_COUNT];
+
+	/* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */
+	uint pin_input_enb[PIN_REG_COUNT];
+
+	/* Address 0x312 ~ 0x313 */
+	uint pin_input_data0;		/* _COM_PIN_INPUT_DATA0_0 */
+	uint pin_input_data1;		/* _COM_PIN_INPUT_DATA1_0 */
+
+	/* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */
+	uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
+
+	/* Address 0x31b ~ 0x329 */
+	uint pin_misc_ctrl;		/* _COM_PIN_MISC_CONTROL_0 */
+	uint pm0_ctrl;			/* _COM_PM0_CONTROL_0 */
+	uint pm0_duty_cycle;		/* _COM_PM0_DUTY_CYCLE_0 */
+	uint pm1_ctrl;			/* _COM_PM1_CONTROL_0 */
+	uint pm1_duty_cycle;		/* _COM_PM1_DUTY_CYCLE_0 */
+	uint spi_ctrl;			/* _COM_SPI_CONTROL_0 */
+	uint spi_start_byte;		/* _COM_SPI_START_BYTE_0 */
+	uint hspi_wr_data_ab;		/* _COM_HSPI_WRITE_DATA_AB_0 */
+	uint hspi_wr_data_cd;		/* _COM_HSPI_WRITE_DATA_CD */
+	uint hspi_cs_dc;		/* _COM_HSPI_CS_DC_0 */
+	uint scratch_reg_a;		/* _COM_SCRATCH_REGISTER_A_0 */
+	uint scratch_reg_b;		/* _COM_SCRATCH_REGISTER_B_0 */
+	uint gpio_ctrl;			/* _COM_GPIO_CTRL_0 */
+	uint gpio_debounce_cnt;		/* _COM_GPIO_DEBOUNCE_COUNTER_0 */
+	uint crc_checksum_latched;	/* _COM_CRC_CHECKSUM_LATCHED_0 */
+};
+
+enum dc_disp_h_pulse_pos {
+	H_PULSE0_POSITION_A,
+	H_PULSE0_POSITION_B,
+	H_PULSE0_POSITION_C,
+	H_PULSE0_POSITION_D,
+	H_PULSE0_POSITION_COUNT,
+};
+
+struct _disp_h_pulse {
+	/* _DISP_H_PULSE0/1/2_CONTROL_0 */
+	uint h_pulse_ctrl;
+	/* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */
+	uint h_pulse_pos[H_PULSE0_POSITION_COUNT];
+};
+
+enum dc_disp_v_pulse_pos {
+	V_PULSE0_POSITION_A,
+	V_PULSE0_POSITION_B,
+	V_PULSE0_POSITION_C,
+	V_PULSE0_POSITION_COUNT,
+};
+
+struct _disp_v_pulse0 {
+	/* _DISP_H_PULSE0/1_CONTROL_0 */
+	uint v_pulse_ctrl;
+	/* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */
+	uint v_pulse_pos[V_PULSE0_POSITION_COUNT];
+};
+
+struct _disp_v_pulse2 {
+	/* _DISP_H_PULSE2/3_CONTROL_0 */
+	uint v_pulse_ctrl;
+	/* _DISP_H_PULSE2/3_POSITION_A_0 */
+	uint v_pulse_pos_a;
+};
+
+enum dc_disp_h_pulse_reg {
+	H_PULSE0,
+	H_PULSE1,
+	H_PULSE2,
+	H_PULSE_COUNT,
+};
+
+enum dc_disp_pp_select {
+	PP_SELECT_A,
+	PP_SELECT_B,
+	PP_SELECT_C,
+	PP_SELECT_D,
+	PP_SELECT_COUNT,
+};
+
+/* DISP register 0x400 ~ 0x4c1 */
+struct dc_disp_reg {
+	/* Address 0x400 ~ 0x40a */
+	uint disp_signal_opt0;		/* _DISP_DISP_SIGNAL_OPTIONS0_0 */
+	uint disp_signal_opt1;		/* _DISP_DISP_SIGNAL_OPTIONS1_0 */
+	uint disp_win_opt;		/* _DISP_DISP_WIN_OPTIONS_0 */
+	uint mem_high_pri;		/* _DISP_MEM_HIGH_PRIORITY_0 */
+	uint mem_high_pri_timer;	/* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */
+	uint disp_timing_opt;		/* _DISP_DISP_TIMING_OPTIONS_0 */
+	uint ref_to_sync;		/* _DISP_REF_TO_SYNC_0 */
+	uint sync_width;		/* _DISP_SYNC_WIDTH_0 */
+	uint back_porch;		/* _DISP_BACK_PORCH_0 */
+	uint disp_active;		/* _DISP_DISP_ACTIVE_0 */
+	uint front_porch;		/* _DISP_FRONT_PORCH_0 */
+
+	/* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_  */
+	struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
+
+	/* Address 0x41a ~ 0x421 */
+	struct _disp_v_pulse0 v_pulse0;	/* _DISP_V_PULSE0_ */
+	struct _disp_v_pulse0 v_pulse1;	/* _DISP_V_PULSE1_ */
+
+	/* Address 0x422 ~ 0x425 */
+	struct _disp_v_pulse2 v_pulse3;	/* _DISP_V_PULSE2_ */
+	struct _disp_v_pulse2 v_pulse4;	/* _DISP_V_PULSE3_ */
+
+	/* Address 0x426 ~ 0x429 */
+	uint m0_ctrl;			/* _DISP_M0_CONTROL_0 */
+	uint m1_ctrl;			/* _DISP_M1_CONTROL_0 */
+	uint di_ctrl;			/* _DISP_DI_CONTROL_0 */
+	uint pp_ctrl;			/* _DISP_PP_CONTROL_0 */
+
+	/* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */
+	uint pp_select[PP_SELECT_COUNT];
+
+	/* Address 0x42e ~ 0x435 */
+	uint disp_clk_ctrl;		/* _DISP_DISP_CLOCK_CONTROL_0 */
+	uint disp_interface_ctrl;	/* _DISP_DISP_INTERFACE_CONTROL_0 */
+	uint disp_color_ctrl;		/* _DISP_DISP_COLOR_CONTROL_0 */
+	uint shift_clk_opt;		/* _DISP_SHIFT_CLOCK_OPTIONS_0 */
+	uint data_enable_opt;		/* _DISP_DATA_ENABLE_OPTIONS_0 */
+	uint serial_interface_opt;	/* _DISP_SERIAL_INTERFACE_OPTIONS_0 */
+	uint lcd_spi_opt;		/* _DISP_LCD_SPI_OPTIONS_0 */
+	uint border_color;		/* _DISP_BORDER_COLOR_0 */
+
+	/* Address 0x436 ~ 0x439 */
+	uint color_key0_lower;		/* _DISP_COLOR_KEY0_LOWER_0 */
+	uint color_key0_upper;		/* _DISP_COLOR_KEY0_UPPER_0 */
+	uint color_key1_lower;		/* _DISP_COLOR_KEY1_LOWER_0 */
+	uint color_key1_upper;		/* _DISP_COLOR_KEY1_UPPER_0 */
+
+	uint reserved0[2];		/* reserved_0[2] */
+
+	/* Address 0x43c ~ 0x442 */
+	uint cursor_foreground;		/* _DISP_CURSOR_FOREGROUND_0 */
+	uint cursor_background;		/* _DISP_CURSOR_BACKGROUND_0 */
+	uint cursor_start_addr;		/* _DISP_CURSOR_START_ADDR_0 */
+	uint cursor_start_addr_ns;	/* _DISP_CURSOR_START_ADDR_NS_0 */
+	uint cursor_pos;		/* _DISP_CURSOR_POSITION_0 */
+	uint cursor_pos_ns;		/* _DISP_CURSOR_POSITION_NS_0 */
+	uint seq_ctrl;			/* _DISP_INIT_SEQ_CONTROL_0 */
+
+	/* Address 0x442 ~ 0x446 */
+	uint spi_init_seq_data_a;	/* _DISP_SPI_INIT_SEQ_DATA_A_0 */
+	uint spi_init_seq_data_b;	/* _DISP_SPI_INIT_SEQ_DATA_B_0 */
+	uint spi_init_seq_data_c;	/* _DISP_SPI_INIT_SEQ_DATA_C_0 */
+	uint spi_init_seq_data_d;	/* _DISP_SPI_INIT_SEQ_DATA_D_0 */
+
+	uint reserved1[0x39];		/* reserved1[0x39], */
+
+	/* Address 0x480 ~ 0x484 */
+	uint dc_mccif_fifoctrl;		/* _DISP_DC_MCCIF_FIFOCTRL_0 */
+	uint mccif_disp0a_hyst;		/* _DISP_MCCIF_DISPLAY0A_HYST_0 */
+	uint mccif_disp0b_hyst;		/* _DISP_MCCIF_DISPLAY0B_HYST_0 */
+	uint mccif_disp0c_hyst;		/* _DISP_MCCIF_DISPLAY0C_HYST_0 */
+	uint mccif_disp1b_hyst;		/* _DISP_MCCIF_DISPLAY1B_HYST_0 */
+
+	uint reserved2[0x3b];		/* reserved2[0x3b] */
+
+	/* Address 0x4c0 ~ 0x4c1 */
+	uint dac_crt_ctrl;		/* _DISP_DAC_CRT_CTRL_0 */
+	uint disp_misc_ctrl;		/* _DISP_DISP_MISC_CONTROL_0 */
+};
+
+enum dc_winc_filter_p {
+	WINC_FILTER_COUNT	= 0x10,
+};
+
+/* Window A/B/C register 0x500 ~ 0x628 */
+struct dc_winc_reg {
+
+	/* Address 0x500 */
+	uint color_palette;		/* _WINC_COLOR_PALETTE_0 */
+
+	uint reserved0[0xff];		/* reserved_0[0xff] */
+
+	/* Address 0x600 */
+	uint palette_color_ext;		/* _WINC_PALETTE_COLOR_EXT_0 */
+
+	/* _WINC_H_FILTER_P00~0F_0 */
+	/* Address 0x601 ~ 0x610 */
+	uint h_filter_p[WINC_FILTER_COUNT];
+
+	/* Address 0x611 ~ 0x618 */
+	uint csc_yof;			/* _WINC_CSC_YOF_0 */
+	uint csc_kyrgb;			/* _WINC_CSC_KYRGB_0 */
+	uint csc_kur;			/* _WINC_CSC_KUR_0 */
+	uint csc_kvr;			/* _WINC_CSC_KVR_0 */
+	uint csc_kug;			/* _WINC_CSC_KUG_0 */
+	uint csc_kvg;			/* _WINC_CSC_KVG_0 */
+	uint csc_kub;			/* _WINC_CSC_KUB_0 */
+	uint csc_kvb;			/* _WINC_CSC_KVB_0 */
+
+	/* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
+	uint v_filter_p[WINC_FILTER_COUNT];
+};
+
+/* WIN A/B/C Register 0x700 ~ 0x714*/
+struct dc_win_reg {
+	/* Address 0x700 ~ 0x714 */
+	uint win_opt;			/* _WIN_WIN_OPTIONS_0 */
+	uint byte_swap;			/* _WIN_BYTE_SWAP_0 */
+	uint buffer_ctrl;		/* _WIN_BUFFER_CONTROL_0 */
+	uint color_depth;		/* _WIN_COLOR_DEPTH_0 */
+	uint pos;			/* _WIN_POSITION_0 */
+	uint size;			/* _WIN_SIZE_0 */
+	uint prescaled_size;		/* _WIN_PRESCALED_SIZE_0 */
+	uint h_initial_dda;		/* _WIN_H_INITIAL_DDA_0 */
+	uint v_initial_dda;		/* _WIN_V_INITIAL_DDA_0 */
+	uint dda_increment;		/* _WIN_DDA_INCREMENT_0 */
+	uint line_stride;		/* _WIN_LINE_STRIDE_0 */
+	uint buf_stride;		/* _WIN_BUF_STRIDE_0 */
+	uint uv_buf_stride;		/* _WIN_UV_BUF_STRIDE_0 */
+	uint buffer_addr_mode;		/* _WIN_BUFFER_ADDR_MODE_0 */
+	uint dv_ctrl;			/* _WIN_DV_CONTROL_0 */
+	uint blend_nokey;		/* _WIN_BLEND_NOKEY_0 */
+	uint blend_1win;		/* _WIN_BLEND_1WIN_0 */
+	uint blend_2win_x;		/* _WIN_BLEND_2WIN_X_0 */
+	uint blend_2win_y;		/* _WIN_BLEND_2WIN_Y_0 */
+	uint blend_3win_xy;		/* _WIN_BLEND_3WIN_XY_0 */
+	uint hp_fetch_ctrl;		/* _WIN_HP_FETCH_CONTROL_0 */
+};
+
+/* WINBUF A/B/C Register 0x800 ~ 0x80a */
+struct dc_winbuf_reg {
+	/* Address 0x800 ~ 0x80a */
+	uint start_addr;		/* _WINBUF_START_ADDR_0 */
+	uint start_addr_ns;		/* _WINBUF_START_ADDR_NS_0 */
+	uint start_addr_u;		/* _WINBUF_START_ADDR_U_0 */
+	uint start_addr_u_ns;		/* _WINBUF_START_ADDR_U_NS_0 */
+	uint start_addr_v;		/* _WINBUF_START_ADDR_V_0 */
+	uint start_addr_v_ns;		/* _WINBUF_START_ADDR_V_NS_0 */
+	uint addr_h_offset;		/* _WINBUF_ADDR_H_OFFSET_0 */
+	uint addr_h_offset_ns;		/* _WINBUF_ADDR_H_OFFSET_NS_0 */
+	uint addr_v_offset;		/* _WINBUF_ADDR_V_OFFSET_0 */
+	uint addr_v_offset_ns;		/* _WINBUF_ADDR_V_OFFSET_NS_0 */
+	uint uflow_status;		/* _WINBUF_UFLOW_STATUS_0 */
+};
+
+/* Display Controller (DC_) regs */
+struct dc_ctlr {
+	struct dc_cmd_reg cmd;		/* CMD register 0x000 ~ 0x43 */
+	uint reserved0[0x2bc];
+
+	struct dc_com_reg com;		/* COM register 0x300 ~ 0x329 */
+	uint reserved1[0xd6];
+
+	struct dc_disp_reg disp;	/* DISP register 0x400 ~ 0x4c1 */
+	uint reserved2[0x3e];
+
+	struct dc_winc_reg winc;	/* Window A/B/C 0x500 ~ 0x628 */
+	uint reserved3[0xd7];
+
+	struct dc_win_reg win;		/* WIN A/B/C 0x700 ~ 0x714*/
+	uint reserved4[0xeb];
+
+	struct dc_winbuf_reg winbuf;	/* WINBUF A/B/C 0x800 ~ 0x80a */
+};
+
+#define BIT(pos)	(1U << pos)
+
+/* DC_CMD_DISPLAY_COMMAND 0x032 */
+#define CTRL_MODE_SHIFT		5
+#define CTRL_MODE_MASK		(0x3 << CTRL_MODE_SHIFT)
+enum {
+	CTRL_MODE_STOP,
+	CTRL_MODE_C_DISPLAY,
+	CTRL_MODE_NC_DISPLAY,
+};
+
+/* _WIN_COLOR_DEPTH_0 */
+enum win_color_depth_id {
+	COLOR_DEPTH_P1,
+	COLOR_DEPTH_P2,
+	COLOR_DEPTH_P4,
+	COLOR_DEPTH_P8,
+	COLOR_DEPTH_B4G4R4A4,
+	COLOR_DEPTH_B5G5R5A,
+	COLOR_DEPTH_B5G6R5,
+	COLOR_DEPTH_AB5G5R5,
+	COLOR_DEPTH_B8G8R8A8 = 12,
+	COLOR_DEPTH_R8G8B8A8,
+	COLOR_DEPTH_B6x2G6x2R6x2A8,
+	COLOR_DEPTH_R6x2G6x2B6x2A8,
+	COLOR_DEPTH_YCbCr422,
+	COLOR_DEPTH_YUV422,
+	COLOR_DEPTH_YCbCr420P,
+	COLOR_DEPTH_YUV420P,
+	COLOR_DEPTH_YCbCr422P,
+	COLOR_DEPTH_YUV422P,
+	COLOR_DEPTH_YCbCr422R,
+	COLOR_DEPTH_YUV422R,
+	COLOR_DEPTH_YCbCr422RA,
+	COLOR_DEPTH_YUV422RA,
+};
+
+/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */
+#define PW0_ENABLE		BIT(0)
+#define PW1_ENABLE		BIT(2)
+#define PW2_ENABLE		BIT(4)
+#define PW3_ENABLE		BIT(6)
+#define PW4_ENABLE		BIT(8)
+#define PM0_ENABLE		BIT(16)
+#define PM1_ENABLE		BIT(18)
+#define SPI_ENABLE		BIT(24)
+#define HSPI_ENABLE		BIT(25)
+
+/* DC_CMD_STATE_CONTROL 0x041 */
+#define GENERAL_ACT_REQ		BIT(0)
+#define WIN_A_ACT_REQ		BIT(1)
+#define WIN_B_ACT_REQ		BIT(2)
+#define WIN_C_ACT_REQ		BIT(3)
+#define GENERAL_UPDATE		BIT(8)
+#define WIN_A_UPDATE		BIT(9)
+#define WIN_B_UPDATE		BIT(10)
+#define WIN_C_UPDATE		BIT(11)
+
+/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
+#define WINDOW_A_SELECT		BIT(4)
+#define WINDOW_B_SELECT		BIT(5)
+#define WINDOW_C_SELECT		BIT(6)
+
+/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
+#define SHIFT_CLK_DIVIDER_SHIFT	0
+#define SHIFT_CLK_DIVIDER_MASK	(0xff << SHIFT_CLK_DIVIDER_SHIFT)
+#define	PIXEL_CLK_DIVIDER_SHIFT	8
+#define	PIXEL_CLK_DIVIDER_MSK	(0xf << PIXEL_CLK_DIVIDER_SHIFT)
+enum {
+	PIXEL_CLK_DIVIDER_PCD1,
+	PIXEL_CLK_DIVIDER_PCD1H,
+	PIXEL_CLK_DIVIDER_PCD2,
+	PIXEL_CLK_DIVIDER_PCD3,
+	PIXEL_CLK_DIVIDER_PCD4,
+	PIXEL_CLK_DIVIDER_PCD6,
+	PIXEL_CLK_DIVIDER_PCD8,
+	PIXEL_CLK_DIVIDER_PCD9,
+	PIXEL_CLK_DIVIDER_PCD12,
+	PIXEL_CLK_DIVIDER_PCD16,
+	PIXEL_CLK_DIVIDER_PCD18,
+	PIXEL_CLK_DIVIDER_PCD24,
+	PIXEL_CLK_DIVIDER_PCD13,
+};
+
+/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */
+#define DATA_FORMAT_SHIFT	0
+#define DATA_FORMAT_MASK	(0xf << DATA_FORMAT_SHIFT)
+enum {
+	DATA_FORMAT_DF1P1C,
+	DATA_FORMAT_DF1P2C24B,
+	DATA_FORMAT_DF1P2C18B,
+	DATA_FORMAT_DF1P2C16B,
+	DATA_FORMAT_DF2S,
+	DATA_FORMAT_DF3S,
+	DATA_FORMAT_DFSPI,
+	DATA_FORMAT_DF1P3C24B,
+	DATA_FORMAT_DF1P3C18B,
+};
+#define DATA_ALIGNMENT_SHIFT	8
+enum {
+	DATA_ALIGNMENT_MSB,
+	DATA_ALIGNMENT_LSB,
+};
+#define DATA_ORDER_SHIFT	9
+enum {
+	DATA_ORDER_RED_BLUE,
+	DATA_ORDER_BLUE_RED,
+};
+
+/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
+#define DE_SELECT_SHIFT		0
+#define DE_SELECT_MASK		(0x3 << DE_SELECT_SHIFT)
+#define DE_SELECT_ACTIVE_BLANK	0x0
+#define DE_SELECT_ACTIVE	0x1
+#define DE_SELECT_ACTIVE_IS	0x2
+#define DE_CONTROL_SHIFT	2
+#define DE_CONTROL_MASK		(0x7 << DE_CONTROL_SHIFT)
+enum {
+	DE_CONTROL_ONECLK,
+	DE_CONTROL_NORMAL,
+	DE_CONTROL_EARLY_EXT,
+	DE_CONTROL_EARLY,
+	DE_CONTROL_ACTIVE_BLANK,
+};
+
+/* DC_WIN_WIN_OPTIONS 0x700 */
+#define H_DIRECTION		BIT(0)
+enum {
+	H_DIRECTION_INCREMENT,
+	H_DIRECTION_DECREMENT,
+};
+#define V_DIRECTION		BIT(2)
+enum {
+	V_DIRECTION_INCREMENT,
+	V_DIRECTION_DECREMENT,
+};
+#define COLOR_EXPAND		BIT(6)
+#define CP_ENABLE		BIT(16)
+#define DV_ENABLE		BIT(20)
+#define WIN_ENABLE		BIT(30)
+
+/* DC_WIN_BYTE_SWAP 0x701 */
+#define BYTE_SWAP_SHIFT		0
+#define BYTE_SWAP_MASK		(3 << BYTE_SWAP_SHIFT)
+enum {
+	BYTE_SWAP_NOSWAP,
+	BYTE_SWAP_SWAP2,
+	BYTE_SWAP_SWAP4,
+	BYTE_SWAP_SWAP4HW
+};
+
+/* DC_WIN_POSITION 0x704 */
+#define H_POSITION_SHIFT	0
+#define H_POSITION_MASK		(0x1FFF << H_POSITION_SHIFT)
+#define V_POSITION_SHIFT	16
+#define V_POSITION_MASK		(0x1FFF << V_POSITION_SHIFT)
+
+/* DC_WIN_SIZE 0x705 */
+#define H_SIZE_SHIFT		0
+#define H_SIZE_MASK		(0x1FFF << H_SIZE_SHIFT)
+#define V_SIZE_SHIFT		16
+#define V_SIZE_MASK		(0x1FFF << V_SIZE_SHIFT)
+
+/* DC_WIN_PRESCALED_SIZE 0x706 */
+#define H_PRESCALED_SIZE_SHIFT	0
+#define H_PRESCALED_SIZE_MASK	(0x7FFF << H_PRESCALED_SIZE)
+#define V_PRESCALED_SIZE_SHIFT	16
+#define V_PRESCALED_SIZE_MASK	(0x1FFF << V_PRESCALED_SIZE)
+
+/* DC_WIN_DDA_INCREMENT 0x709 */
+#define H_DDA_INC_SHIFT		0
+#define H_DDA_INC_MASK		(0xFFFF << H_DDA_INC_SHIFT)
+#define V_DDA_INC_SHIFT		16
+#define V_DDA_INC_MASK		(0xFFFF << V_DDA_INC_SHIFT)
+
+#endif /* __ASM_ARCH_TEGRA_DC_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/display.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/display.h
new file mode 100644
index 000000000..a04c84e54
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/display.h
@@ -0,0 +1,136 @@
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
+#define __ASM_ARCH_TEGRA_DISPLAY_H
+
+#include <asm/arch/dc.h>
+#include <fdtdec.h>
+
+/* This holds information about a window which can be displayed */
+struct disp_ctl_win {
+	enum win_color_depth_id fmt;	/* Color depth/format */
+	unsigned	bpp;		/* Bits per pixel */
+	phys_addr_t	phys_addr;	/* Physical address in memory */
+	unsigned	x;		/* Horizontal address offset (bytes) */
+	unsigned	y;		/* Veritical address offset (bytes) */
+	unsigned	w;		/* Width of source window */
+	unsigned	h;		/* Height of source window */
+	unsigned	stride;		/* Number of bytes per line */
+	unsigned	out_x;		/* Left edge of output window (col) */
+	unsigned	out_y;		/* Top edge of output window (row) */
+	unsigned	out_w;		/* Width of output window in pixels */
+	unsigned	out_h;		/* Height of output window in pixels */
+};
+
+#define FDT_LCD_TIMINGS	4
+
+enum {
+	FDT_LCD_TIMING_REF_TO_SYNC,
+	FDT_LCD_TIMING_SYNC_WIDTH,
+	FDT_LCD_TIMING_BACK_PORCH,
+	FDT_LCD_TIMING_FRONT_PORCH,
+
+	FDT_LCD_TIMING_COUNT,
+};
+
+enum lcd_cache_t {
+	FDT_LCD_CACHE_OFF		= 0,
+	FDT_LCD_CACHE_WRITE_THROUGH	= 1 << 0,
+	FDT_LCD_CACHE_WRITE_BACK	= 1 << 1,
+	FDT_LCD_CACHE_FLUSH		= 1 << 2,
+	FDT_LCD_CACHE_WRITE_BACK_FLUSH	= FDT_LCD_CACHE_WRITE_BACK |
+						FDT_LCD_CACHE_FLUSH,
+};
+
+/* Information about the display controller */
+struct fdt_disp_config {
+	int valid;			/* config is valid */
+	int width;			/* width in pixels */
+	int height;			/* height in pixels */
+	int bpp;			/* number of bits per pixel */
+
+	/*
+	 * log2 of number of bpp, in general, unless it bpp is 24 in which
+	 * case this field holds 24 also! This is a U-Boot thing.
+	 */
+	int log2_bpp;
+	struct disp_ctlr *disp;		/* Display controller to use */
+	fdt_addr_t frame_buffer;	/* Address of frame buffer */
+	unsigned pixel_clock;		/* Pixel clock in Hz */
+	uint horiz_timing[FDT_LCD_TIMING_COUNT];	/* Horizontal timing */
+	uint vert_timing[FDT_LCD_TIMING_COUNT];		/* Vertical timing */
+	int panel_node;			/* node offset of panel information */
+};
+
+/* Information about the LCD panel */
+struct fdt_panel_config {
+	int pwm_channel;		/* PWM channel to use for backlight */
+	enum lcd_cache_t cache_type;
+
+	struct fdt_gpio_state backlight_en;	/* GPIO for backlight enable */
+	struct fdt_gpio_state lvds_shutdown;	/* GPIO for lvds shutdown */
+	struct fdt_gpio_state backlight_vdd;	/* GPIO for backlight vdd */
+	struct fdt_gpio_state panel_vdd;	/* GPIO for panel vdd */
+	/*
+	 * Panel required timings
+	 * Timing 1: delay between panel_vdd-rise and data-rise
+	 * Timing 2: delay between data-rise and backlight_vdd-rise
+	 * Timing 3: delay between backlight_vdd and pwm-rise
+	 * Timing 4: delay between pwm-rise and backlight_en-rise
+	 */
+	uint panel_timings[FDT_LCD_TIMINGS];
+};
+
+/**
+ * Register a new display based on device tree configuration.
+ *
+ * The frame buffer can be positioned by U-Boot or overriden by the fdt.
+ * You should pass in the U-Boot address here, and check the contents of
+ * struct fdt_disp_config to see what was actually chosen.
+ *
+ * @param blob			Device tree blob
+ * @param default_lcd_base	Default address of LCD frame buffer
+ * @return 0 if ok, -1 on error (unsupported bits per pixel)
+ */
+int tegra_display_probe(const void *blob, void *default_lcd_base);
+
+/**
+ * Return the current display configuration
+ *
+ * @return pointer to display configuration, or NULL if there is no valid
+ * config
+ */
+struct fdt_disp_config *tegra_display_get_config(void);
+
+/**
+ * Perform the next stage of the LCD init if it is time to do so.
+ *
+ * LCD init can be time-consuming because of the number of delays we need
+ * while waiting for the backlight power supply, etc. This function can
+ * be called at various times during U-Boot operation to advance the
+ * initialization of the LCD to the next stage if sufficient time has
+ * passed since the last stage. It keeps track of what stage it is up to
+ * and the time that it is permitted to move to the next stage.
+ *
+ * The final call should have wait=1 to complete the init.
+ *
+ * @param blob	fdt blob containing LCD information
+ * @param wait	1 to wait until all init is complete, and then return
+ *		0 to return immediately, potentially doing nothing if it is
+ *		not yet time for the next init.
+ */
+int tegra_lcd_check_next_stage(const void *blob, int wait);
+
+/**
+ * Set up the maximum LCD size so we can size the frame buffer.
+ *
+ * @param blob	fdt blob containing LCD information
+ */
+void tegra_lcd_early_init(const void *blob);
+
+#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/emc.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/emc.h
new file mode 100644
index 000000000..a85f4c3d8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/emc.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ARCH_EMC_H_
+#define _ARCH_EMC_H_
+
+#include <asm/types.h>
+
+#define TEGRA_EMC_NUM_REGS	46
+
+/* EMC Registers */
+struct emc_ctlr {
+	u32 cfg;		/* 0x00: EMC_CFG */
+	u32 reserved0[3];	/* 0x04 ~ 0x0C */
+	u32 adr_cfg;		/* 0x10: EMC_ADR_CFG */
+	u32 adr_cfg1;		/* 0x14: EMC_ADR_CFG_1 */
+	u32 reserved1[2];	/* 0x18 ~ 0x18 */
+	u32 refresh_ctrl;	/* 0x20: EMC_REFCTRL */
+	u32 pin;		/* 0x24: EMC_PIN */
+	u32 timing_ctrl;	/* 0x28: EMC_TIMING_CONTROL */
+	u32 rc;			/* 0x2C: EMC_RC */
+	u32 rfc;		/* 0x30: EMC_RFC */
+	u32 ras;		/* 0x34: EMC_RAS */
+	u32 rp;			/* 0x38: EMC_RP */
+	u32 r2w;		/* 0x3C: EMC_R2W */
+	u32 w2r;		/* 0x40: EMC_W2R */
+	u32 r2p;		/* 0x44: EMC_R2P */
+	u32 w2p;		/* 0x48: EMC_W2P */
+	u32 rd_rcd;		/* 0x4C: EMC_RD_RCD */
+	u32 wd_rcd;		/* 0x50: EMC_WD_RCD */
+	u32 rrd;		/* 0x54: EMC_RRD */
+	u32 rext;		/* 0x58: EMC_REXT */
+	u32 wdv;		/* 0x5C: EMC_WDV */
+	u32 quse;		/* 0x60: EMC_QUSE */
+	u32 qrst;		/* 0x64: EMC_QRST */
+	u32 qsafe;		/* 0x68: EMC_QSAFE */
+	u32 rdv;		/* 0x6C: EMC_RDV */
+	u32 refresh;		/* 0x70: EMC_REFRESH */
+	u32 burst_refresh_num;	/* 0x74: EMC_BURST_REFRESH_NUM */
+	u32 pdex2wr;		/* 0x78: EMC_PDEX2WR */
+	u32 pdex2rd;		/* 0x7c: EMC_PDEX2RD */
+	u32 pchg2pden;		/* 0x80: EMC_PCHG2PDEN */
+	u32 act2pden;		/* 0x84: EMC_ACT2PDEN */
+	u32 ar2pden;		/* 0x88: EMC_AR2PDEN */
+	u32 rw2pden;		/* 0x8C: EMC_RW2PDEN */
+	u32 txsr;		/* 0x90: EMC_TXSR */
+	u32 tcke;		/* 0x94: EMC_TCKE */
+	u32 tfaw;		/* 0x98: EMC_TFAW */
+	u32 trpab;		/* 0x9C: EMC_TRPAB */
+	u32 tclkstable;		/* 0xA0: EMC_TCLKSTABLE */
+	u32 tclkstop;		/* 0xA4: EMC_TCLKSTOP */
+	u32 trefbw;		/* 0xA8: EMC_TREFBW */
+	u32 quse_extra;		/* 0xAC: EMC_QUSE_EXTRA */
+	u32 odt_write;		/* 0xB0: EMC_ODT_WRITE */
+	u32 odt_read;		/* 0xB4: EMC_ODT_READ */
+	u32 reserved2[5];	/* 0xB8 ~ 0xC8 */
+	u32 mrs;		/* 0xCC: EMC_MRS */
+	u32 emrs;		/* 0xD0: EMC_EMRS */
+	u32 ref;		/* 0xD4: EMC_REF */
+	u32 pre;		/* 0xD8: EMC_PRE */
+	u32 nop;		/* 0xDC: EMC_NOP */
+	u32 self_ref;		/* 0xE0: EMC_SELF_REF */
+	u32 dpd;		/* 0xE4: EMC_DPD */
+	u32 mrw;		/* 0xE8: EMC_MRW */
+	u32 mrr;		/* 0xEC: EMC_MRR */
+	u32 reserved3;		/* 0xF0: */
+	u32 fbio_cfg1;		/* 0xF4: EMC_FBIO_CFG1 */
+	u32 fbio_dqsib_dly;	/* 0xF8: EMC_FBIO_DQSIB_DLY */
+	u32 fbio_dqsib_dly_msb;	/* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */
+	u32 fbio_spare;		/* 0x100: SBIO_SPARE */
+				/* There are more registers ... */
+};
+
+/**
+ * Set up the EMC for the given rate. The timing parameters are retrieved
+ * from the device tree "nvidia,tegra20-emc" node and its
+ * "nvidia,tegra20-emc-table" sub-nodes.
+ *
+ * @param blob	Device tree blob
+ * @param rate	Clock speed of memory controller in Hz (=2x memory bus rate)
+ * @return 0 if ok, else -ve error code (look in emc.c to decode it)
+ */
+int tegra_set_emc(const void *blob, unsigned rate);
+
+/**
+ * Get a pointer to the EMC controller from the device tree.
+ *
+ * @param blob	Device tree blob
+ * @return pointer to EMC controller
+ */
+struct emc_ctlr *emc_get_controller(const void *blob);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/flow.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/flow.h
new file mode 100644
index 000000000..8a6a78311
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/flow.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FLOW_H_
+#define _FLOW_H_
+
+struct flow_ctlr {
+	u32	halt_cpu_events;
+	u32	halt_cop_events;
+	u32	cpu_csr;
+	u32	cop_csr;
+	u32	halt_cpu1_events;
+	u32	cpu1_csr;
+};
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/funcmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/funcmux.h
new file mode 100644
index 000000000..39c2c9d82
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/funcmux.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Tegra20 high-level function multiplexing */
+
+#ifndef _TEGRA20_FUNCMUX_H_
+#define _TEGRA20_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART1_IRRX_IRTX = 0,
+	FUNCMUX_UART1_UAA_UAB,
+	FUNCMUX_UART1_GPU,
+	FUNCMUX_UART1_SDIO1,
+	FUNCMUX_UART2_UAD = 0,
+	FUNCMUX_UART4_GMC = 0,
+
+	/* I2C configs */
+	FUNCMUX_DVC_I2CP = 0,
+	FUNCMUX_I2C1_RM = 0,
+	FUNCMUX_I2C2_DDC = 0,
+	FUNCMUX_I2C2_PTA,
+	FUNCMUX_I2C3_DTF = 0,
+
+	/* SDMMC configs */
+	FUNCMUX_SDMMC1_SDIO1_4BIT = 0,
+	FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0,
+	FUNCMUX_SDMMC3_SDB_4BIT = 0,
+	FUNCMUX_SDMMC3_SDB_SLXA_8BIT,
+	FUNCMUX_SDMMC4_ATC_ATD_8BIT = 0,
+	FUNCMUX_SDMMC4_ATB_GMA_4_BIT,
+	FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT,
+
+	/* USB configs */
+	FUNCMUX_USB2_ULPI = 0,
+
+	/* Serial Flash configs */
+	FUNCMUX_SPI1_GMC_GMD = 0,
+
+	/* NAND flags */
+	FUNCMUX_NDFLASH_ATC = 0,
+	FUNCMUX_NDFLASH_KBC_8_BIT,
+};
+#endif	/* _TEGRA20_FUNCMUX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
new file mode 100644
index 000000000..6631871ce
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
@@ -0,0 +1,50 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA20_GP_PADCTRL_H_
+#define _TEGRA20_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	cdevcfg1;	/* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdevcfg2;	/* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	csuscfg;	/* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */
+	u32	dap1cfg;	/* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0x94: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	lcdcfg1;	/* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */
+	u32	lcdcfg2;	/* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */
+	u32	sdmmc2_cfg;	/* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */
+	u32	sdmmc3_cfg;	/* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */
+	u32	spicfg;		/* 0xA8: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xAC: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xB0: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	vicfg1;		/* 0xBC: APB_MISC_GP_VICFG1PADCTRL */
+	u32	vicfg2;		/* 0xC0: APB_MISC_GP_VICFG2PADCTRL */
+	u32	xm2cfga;	/* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */
+	u32	xm2cfgc;	/* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */
+	u32	xm2cfgd;	/* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */
+	u32	xm2clkcfg;	/* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */
+	u32	memcomp;	/* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
+};
+
+#endif	/* _TEGRA20_GP_PADCTRL_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gpio.h
new file mode 100644
index 000000000..b40b1ff9c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/gpio.h
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * Portions Copyright 2011-2012 NVIDIA Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA20_GPIO_H_
+#define _TEGRA20_GPIO_H_
+
+/*
+ * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	7	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+	GPIO_PA0 = 0,	/* pin 0 */
+	GPIO_PA1,
+	GPIO_PA2,
+	GPIO_PA3,
+	GPIO_PA4,
+	GPIO_PA5,
+	GPIO_PA6,
+	GPIO_PA7,
+	GPIO_PB0,	/* pin 8 */
+	GPIO_PB1,
+	GPIO_PB2,
+	GPIO_PB3,
+	GPIO_PB4,
+	GPIO_PB5,
+	GPIO_PB6,
+	GPIO_PB7,
+	GPIO_PC0,	/* pin 16 */
+	GPIO_PC1,
+	GPIO_PC2,
+	GPIO_PC3,
+	GPIO_PC4,
+	GPIO_PC5,
+	GPIO_PC6,
+	GPIO_PC7,
+	GPIO_PD0,	/* pin 24 */
+	GPIO_PD1,
+	GPIO_PD2,
+	GPIO_PD3,
+	GPIO_PD4,
+	GPIO_PD5,
+	GPIO_PD6,
+	GPIO_PD7,
+	GPIO_PE0,	/* pin 32 */
+	GPIO_PE1,
+	GPIO_PE2,
+	GPIO_PE3,
+	GPIO_PE4,
+	GPIO_PE5,
+	GPIO_PE6,
+	GPIO_PE7,
+	GPIO_PF0,	/* pin 40 */
+	GPIO_PF1,
+	GPIO_PF2,
+	GPIO_PF3,
+	GPIO_PF4,
+	GPIO_PF5,
+	GPIO_PF6,
+	GPIO_PF7,
+	GPIO_PG0,	/* pin 48 */
+	GPIO_PG1,
+	GPIO_PG2,
+	GPIO_PG3,
+	GPIO_PG4,
+	GPIO_PG5,
+	GPIO_PG6,
+	GPIO_PG7,
+	GPIO_PH0,	/* pin 56 */
+	GPIO_PH1,
+	GPIO_PH2,
+	GPIO_PH3,
+	GPIO_PH4,
+	GPIO_PH5,
+	GPIO_PH6,
+	GPIO_PH7,
+	GPIO_PI0,	/* pin 64 */
+	GPIO_PI1,
+	GPIO_PI2,
+	GPIO_PI3,
+	GPIO_PI4,
+	GPIO_PI5,
+	GPIO_PI6,
+	GPIO_PI7,
+	GPIO_PJ0,	/* pin 72 */
+	GPIO_PJ1,
+	GPIO_PJ2,
+	GPIO_PJ3,
+	GPIO_PJ4,
+	GPIO_PJ5,
+	GPIO_PJ6,
+	GPIO_PJ7,
+	GPIO_PK0,	/* pin 80 */
+	GPIO_PK1,
+	GPIO_PK2,
+	GPIO_PK3,
+	GPIO_PK4,
+	GPIO_PK5,
+	GPIO_PK6,
+	GPIO_PK7,
+	GPIO_PL0,	/* pin 88 */
+	GPIO_PL1,
+	GPIO_PL2,
+	GPIO_PL3,
+	GPIO_PL4,
+	GPIO_PL5,
+	GPIO_PL6,
+	GPIO_PL7,
+	GPIO_PM0,	/* pin 96 */
+	GPIO_PM1,
+	GPIO_PM2,
+	GPIO_PM3,
+	GPIO_PM4,
+	GPIO_PM5,
+	GPIO_PM6,
+	GPIO_PM7,
+	GPIO_PN0,	/* pin 104 */
+	GPIO_PN1,
+	GPIO_PN2,
+	GPIO_PN3,
+	GPIO_PN4,
+	GPIO_PN5,
+	GPIO_PN6,
+	GPIO_PN7,
+	GPIO_PO0,	/* pin 112 */
+	GPIO_PO1,
+	GPIO_PO2,
+	GPIO_PO3,
+	GPIO_PO4,
+	GPIO_PO5,
+	GPIO_PO6,
+	GPIO_PO7,
+	GPIO_PP0,	/* pin 120 */
+	GPIO_PP1,
+	GPIO_PP2,
+	GPIO_PP3,
+	GPIO_PP4,
+	GPIO_PP5,
+	GPIO_PP6,
+	GPIO_PP7,
+	GPIO_PQ0,	/* pin 128 */
+	GPIO_PQ1,
+	GPIO_PQ2,
+	GPIO_PQ3,
+	GPIO_PQ4,
+	GPIO_PQ5,
+	GPIO_PQ6,
+	GPIO_PQ7,
+	GPIO_PR0,	/* pin 136 */
+	GPIO_PR1,
+	GPIO_PR2,
+	GPIO_PR3,
+	GPIO_PR4,
+	GPIO_PR5,
+	GPIO_PR6,
+	GPIO_PR7,
+	GPIO_PS0,	/* pin 144 */
+	GPIO_PS1,
+	GPIO_PS2,
+	GPIO_PS3,
+	GPIO_PS4,
+	GPIO_PS5,
+	GPIO_PS6,
+	GPIO_PS7,
+	GPIO_PT0,	/* pin 152 */
+	GPIO_PT1,
+	GPIO_PT2,
+	GPIO_PT3,
+	GPIO_PT4,
+	GPIO_PT5,
+	GPIO_PT6,
+	GPIO_PT7,
+	GPIO_PU0,	/* pin 160 */
+	GPIO_PU1,
+	GPIO_PU2,
+	GPIO_PU3,
+	GPIO_PU4,
+	GPIO_PU5,
+	GPIO_PU6,
+	GPIO_PU7,
+	GPIO_PV0,	/* pin 168 */
+	GPIO_PV1,
+	GPIO_PV2,
+	GPIO_PV3,
+	GPIO_PV4,
+	GPIO_PV5,
+	GPIO_PV6,
+	GPIO_PV7,
+	GPIO_PW0,	/* pin 176 */
+	GPIO_PW1,
+	GPIO_PW2,
+	GPIO_PW3,
+	GPIO_PW4,
+	GPIO_PW5,
+	GPIO_PW6,
+	GPIO_PW7,
+	GPIO_PX0,	/* pin 184 */
+	GPIO_PX1,
+	GPIO_PX2,
+	GPIO_PX3,
+	GPIO_PX4,
+	GPIO_PX5,
+	GPIO_PX6,
+	GPIO_PX7,
+	GPIO_PY0,	/* pin 192 */
+	GPIO_PY1,
+	GPIO_PY2,
+	GPIO_PY3,
+	GPIO_PY4,
+	GPIO_PY5,
+	GPIO_PY6,
+	GPIO_PY7,
+	GPIO_PZ0,	/* pin 200 */
+	GPIO_PZ1,
+	GPIO_PZ2,
+	GPIO_PZ3,
+	GPIO_PZ4,
+	GPIO_PZ5,
+	GPIO_PZ6,
+	GPIO_PZ7,
+	GPIO_PAA0,	/* pin 208 */
+	GPIO_PAA1,
+	GPIO_PAA2,
+	GPIO_PAA3,
+	GPIO_PAA4,
+	GPIO_PAA5,
+	GPIO_PAA6,
+	GPIO_PAA7,
+	GPIO_PBB0,	/* pin 216 */
+	GPIO_PBB1,
+	GPIO_PBB2,
+	GPIO_PBB3,
+	GPIO_PBB4,
+	GPIO_PBB5,
+	GPIO_PBB6,
+	GPIO_PBB7,	/* pin 223 */
+};
+
+#endif	/* TEGRA20_GPIO_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/hardware.h
new file mode 100644
index 000000000..a29589490
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/hardware.h
@@ -0,0 +1,13 @@
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporation <www.nvidia.com>
+*
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef __TEGRA2_HW_H
+#define __TEGRA2_HW_H
+
+/* include tegra specific hardware definitions */
+
+#endif /* __TEGRA2_HW_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h
new file mode 100644
index 000000000..11c0104ff
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -0,0 +1,237 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA20_PINMUX_H_
+#define _TEGRA20_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ *	- function
+ *	- pullup / pulldown
+ *	- tristate or normal
+ */
+enum pmux_pingrp {
+	/* APB_MISC_PP_TRISTATE_REG_A_0 */
+	PMUX_PINGRP_ATA,
+	PMUX_PINGRP_ATB,
+	PMUX_PINGRP_ATC,
+	PMUX_PINGRP_ATD,
+	PMUX_PINGRP_CDEV1,
+	PMUX_PINGRP_CDEV2,
+	PMUX_PINGRP_CSUS,
+	PMUX_PINGRP_DAP1,
+
+	PMUX_PINGRP_DAP2,
+	PMUX_PINGRP_DAP3,
+	PMUX_PINGRP_DAP4,
+	PMUX_PINGRP_DTA,
+	PMUX_PINGRP_DTB,
+	PMUX_PINGRP_DTC,
+	PMUX_PINGRP_DTD,
+	PMUX_PINGRP_DTE,
+
+	PMUX_PINGRP_GPU,
+	PMUX_PINGRP_GPV,
+	PMUX_PINGRP_I2CP,
+	PMUX_PINGRP_IRTX,
+	PMUX_PINGRP_IRRX,
+	PMUX_PINGRP_KBCB,
+	PMUX_PINGRP_KBCA,
+	PMUX_PINGRP_PMC,
+
+	PMUX_PINGRP_PTA,
+	PMUX_PINGRP_RM,
+	PMUX_PINGRP_KBCE,
+	PMUX_PINGRP_KBCF,
+	PMUX_PINGRP_GMA,
+	PMUX_PINGRP_GMC,
+	PMUX_PINGRP_SDIO1,
+	PMUX_PINGRP_OWC,
+
+	/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
+	PMUX_PINGRP_GME,
+	PMUX_PINGRP_SDC,
+	PMUX_PINGRP_SDD,
+	PMUX_PINGRP_RESERVED0,
+	PMUX_PINGRP_SLXA,
+	PMUX_PINGRP_SLXC,
+	PMUX_PINGRP_SLXD,
+	PMUX_PINGRP_SLXK,
+
+	PMUX_PINGRP_SPDI,
+	PMUX_PINGRP_SPDO,
+	PMUX_PINGRP_SPIA,
+	PMUX_PINGRP_SPIB,
+	PMUX_PINGRP_SPIC,
+	PMUX_PINGRP_SPID,
+	PMUX_PINGRP_SPIE,
+	PMUX_PINGRP_SPIF,
+
+	PMUX_PINGRP_SPIG,
+	PMUX_PINGRP_SPIH,
+	PMUX_PINGRP_UAA,
+	PMUX_PINGRP_UAB,
+	PMUX_PINGRP_UAC,
+	PMUX_PINGRP_UAD,
+	PMUX_PINGRP_UCA,
+	PMUX_PINGRP_UCB,
+
+	PMUX_PINGRP_RESERVED1,
+	PMUX_PINGRP_ATE,
+	PMUX_PINGRP_KBCC,
+	PMUX_PINGRP_RESERVED2,
+	PMUX_PINGRP_RESERVED3,
+	PMUX_PINGRP_GMB,
+	PMUX_PINGRP_GMD,
+	PMUX_PINGRP_DDC,
+
+	/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
+	PMUX_PINGRP_LD0,
+	PMUX_PINGRP_LD1,
+	PMUX_PINGRP_LD2,
+	PMUX_PINGRP_LD3,
+	PMUX_PINGRP_LD4,
+	PMUX_PINGRP_LD5,
+	PMUX_PINGRP_LD6,
+	PMUX_PINGRP_LD7,
+
+	PMUX_PINGRP_LD8,
+	PMUX_PINGRP_LD9,
+	PMUX_PINGRP_LD10,
+	PMUX_PINGRP_LD11,
+	PMUX_PINGRP_LD12,
+	PMUX_PINGRP_LD13,
+	PMUX_PINGRP_LD14,
+	PMUX_PINGRP_LD15,
+
+	PMUX_PINGRP_LD16,
+	PMUX_PINGRP_LD17,
+	PMUX_PINGRP_LHP0,
+	PMUX_PINGRP_LHP1,
+	PMUX_PINGRP_LHP2,
+	PMUX_PINGRP_LVP0,
+	PMUX_PINGRP_LVP1,
+	PMUX_PINGRP_HDINT,
+
+	PMUX_PINGRP_LM0,
+	PMUX_PINGRP_LM1,
+	PMUX_PINGRP_LVS,
+	PMUX_PINGRP_LSC0,
+	PMUX_PINGRP_LSC1,
+	PMUX_PINGRP_LSCK,
+	PMUX_PINGRP_LDC,
+	PMUX_PINGRP_LCSN,
+
+	/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
+	PMUX_PINGRP_LSPI,
+	PMUX_PINGRP_LSDA,
+	PMUX_PINGRP_LSDI,
+	PMUX_PINGRP_LPW0,
+	PMUX_PINGRP_LPW1,
+	PMUX_PINGRP_LPW2,
+	PMUX_PINGRP_LDI,
+	PMUX_PINGRP_LHS,
+
+	PMUX_PINGRP_LPP,
+	PMUX_PINGRP_RESERVED4,
+	PMUX_PINGRP_KBCD,
+	PMUX_PINGRP_GPU7,
+	PMUX_PINGRP_DTF,
+	PMUX_PINGRP_UDA,
+	PMUX_PINGRP_CRTP,
+	PMUX_PINGRP_SDB,
+
+	/* these pin groups only have pullup and pull down control */
+	PMUX_PINGRP_CK32,
+	PMUX_PINGRP_DDRC,
+	PMUX_PINGRP_PMCA,
+	PMUX_PINGRP_PMCB,
+	PMUX_PINGRP_PMCC,
+	PMUX_PINGRP_PMCD,
+	PMUX_PINGRP_PMCE,
+	PMUX_PINGRP_XM2C,
+	PMUX_PINGRP_XM2D,
+	PMUX_PINGRP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+	PMUX_FUNC_AHB_CLK,
+	PMUX_FUNC_APB_CLK,
+	PMUX_FUNC_AUDIO_SYNC,
+	PMUX_FUNC_CRT,
+	PMUX_FUNC_DAP1,
+	PMUX_FUNC_DAP2,
+	PMUX_FUNC_DAP3,
+	PMUX_FUNC_DAP4,
+	PMUX_FUNC_DAP5,
+	PMUX_FUNC_DISPA,
+	PMUX_FUNC_DISPB,
+	PMUX_FUNC_EMC_TEST0_DLL,
+	PMUX_FUNC_EMC_TEST1_DLL,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_INT,
+	PMUX_FUNC_HDMI,
+	PMUX_FUNC_I2C,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_IDE,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_MIO,
+	PMUX_FUNC_MIPI_HS,
+	PMUX_FUNC_NAND,
+	PMUX_FUNC_OSC,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PCIE,
+	PMUX_FUNC_PLLA_OUT,
+	PMUX_FUNC_PLLC_OUT1,
+	PMUX_FUNC_PLLM_OUT1,
+	PMUX_FUNC_PLLP_OUT2,
+	PMUX_FUNC_PLLP_OUT3,
+	PMUX_FUNC_PLLP_OUT4,
+	PMUX_FUNC_PWM,
+	PMUX_FUNC_PWR_INTR,
+	PMUX_FUNC_PWR_ON,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SDIO1,
+	PMUX_FUNC_SDIO2,
+	PMUX_FUNC_SDIO3,
+	PMUX_FUNC_SDIO4,
+	PMUX_FUNC_SFLASH,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI2_ALT,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_TWC,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_UARTE,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_SENSOR_CLK,
+	PMUX_FUNC_XIO,
+	PMUX_FUNC_RSVD1,
+	PMUX_FUNC_RSVD2,
+	PMUX_FUNC_RSVD3,
+	PMUX_FUNC_RSVD4,
+	PMUX_FUNC_COUNT,
+};
+
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA20_PINMUX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pmu.h
new file mode 100644
index 000000000..46effb47e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pmu.h
@@ -0,0 +1,14 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ARCH_PMU_H_
+#define _ARCH_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif	/* _ARCH_PMU_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pwm.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pwm.h
new file mode 100644
index 000000000..8e7397d0e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/pwm.h
@@ -0,0 +1,60 @@
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TEGRA_PWM_H
+#define __ASM_ARCH_TEGRA_PWM_H
+
+/* This is a single PWM channel */
+struct pwm_ctlr {
+	uint control;		/* Control register */
+	uint reserved[3];	/* Space space */
+};
+
+#define PWM_NUM_CHANNELS	4
+
+/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
+#define PWM_ENABLE_SHIFT	31
+#define PWM_ENABLE_MASK	(0x1 << PWM_ENABLE_SHIFT)
+
+#define PWM_WIDTH_SHIFT	16
+#define PWM_WIDTH_MASK		(0x7FFF << PWM_WIDTH_SHIFT)
+
+#define PWM_DIVIDER_SHIFT	0
+#define PWM_DIVIDER_MASK	(0x1FFF << PWM_DIVIDER_SHIFT)
+
+/**
+ * Program the PWM with the given parameters.
+ *
+ * @param channel	PWM channel to update
+ * @param rate		Clock rate to use for PWM
+ * @param pulse_width	high pulse width: 0=always low, 1=1/256 pulse high,
+ *			n = n/256 pulse high
+ * @param freq_divider	frequency divider value (1 to use rate as is)
+ */
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider);
+
+/**
+ * Request a pwm channel as referenced by a device tree node.
+ *
+ * This channel can then be passed to pwm_enable().
+ *
+ * @param blob		Device tree blob
+ * @param node		Node containing reference to pwm
+ * @param prop_name	Property name of pwm reference
+ * @return channel number, if ok, else -1
+ */
+int pwm_request(const void *blob, int node, const char *prop_name);
+
+/**
+ * Set up the pwm controller, by looking it up in the fdt.
+ *
+ * @return 0 if ok, -1 if the device tree node was not found or invalid.
+ */
+int pwm_init(const void *blob);
+
+#endif	/* __ASM_ARCH_TEGRA_PWM_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/sdram_param.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/sdram_param.h
new file mode 100644
index 000000000..aaf05084e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/sdram_param.h
@@ -0,0 +1,132 @@
+/*
+ *  (C) Copyright 2010, 2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SDRAM_PARAM_H_
+#define _SDRAM_PARAM_H_
+
+/*
+ * Defines the number of 32-bit words provided in each set of SDRAM parameters
+ * for arbitration configuration data.
+ */
+#define BCT_SDRAM_ARB_CONFIG_WORDS 27
+
+enum memory_type {
+	MEMORY_TYPE_NONE = 0,
+	MEMORY_TYPE_DDR,
+	MEMORY_TYPE_LPDDR,
+	MEMORY_TYPE_DDR2,
+	MEMORY_TYPE_LPDDR2,
+	MEMORY_TYPE_NUM,
+	MEMORY_TYPE_FORCE32 = 0x7FFFFFFF
+};
+
+/* Defines the SDRAM parameter structure */
+struct sdram_params {
+	enum memory_type memory_type;
+	u32 pllm_charge_pump_setup_control;
+	u32 pllm_loop_filter_setup_control;
+	u32 pllm_input_divider;
+	u32 pllm_feedback_divider;
+	u32 pllm_post_divider;
+	u32 pllm_stable_time;
+	u32 emc_clock_divider;
+	u32 emc_auto_cal_interval;
+	u32 emc_auto_cal_config;
+	u32 emc_auto_cal_wait;
+	u32 emc_pin_program_wait;
+	u32 emc_rc;
+	u32 emc_rfc;
+	u32 emc_ras;
+	u32 emc_rp;
+	u32 emc_r2w;
+	u32 emc_w2r;
+	u32 emc_r2p;
+	u32 emc_w2p;
+	u32 emc_rd_rcd;
+	u32 emc_wr_rcd;
+	u32 emc_rrd;
+	u32 emc_rext;
+	u32 emc_wdv;
+	u32 emc_quse;
+	u32 emc_qrst;
+	u32 emc_qsafe;
+	u32 emc_rdv;
+	u32 emc_refresh;
+	u32 emc_burst_refresh_num;
+	u32 emc_pdex2wr;
+	u32 emc_pdex2rd;
+	u32 emc_pchg2pden;
+	u32 emc_act2pden;
+	u32 emc_ar2pden;
+	u32 emc_rw2pden;
+	u32 emc_txsr;
+	u32 emc_tcke;
+	u32 emc_tfaw;
+	u32 emc_trpab;
+	u32 emc_tclkstable;
+	u32 emc_tclkstop;
+	u32 emc_trefbw;
+	u32 emc_quseextra;
+	u32 emc_fbioc_fg1;
+	u32 emc_fbio_dqsib_dly;
+	u32 emc_fbio_dqsib_dly_msb;
+	u32 emc_fbio_quse_dly;
+	u32 emc_fbio_quse_dly_msb;
+	u32 emc_fbio_cfg5;
+	u32 emc_fbio_cfg6;
+	u32 emc_fbio_spare;
+	u32 emc_mrs;
+	u32 emc_emrs;
+	u32 emc_mrw1;
+	u32 emc_mrw2;
+	u32 emc_mrw3;
+	u32 emc_mrw_reset_command;
+	u32 emc_mrw_reset_init_wait;
+	u32 emc_adr_cfg;
+	u32 emc_adr_cfg1;
+	u32 emc_emem_cfg;
+	u32 emc_low_latency_config;
+	u32 emc_cfg;
+	u32 emc_cfg2;
+	u32 emc_dbg;
+	u32 ahb_arbitration_xbar_ctrl;
+	u32 emc_cfg_dig_dll;
+	u32 emc_dll_xform_dqs;
+	u32 emc_dll_xform_quse;
+	u32 warm_boot_wait;
+	u32 emc_ctt_term_ctrl;
+	u32 emc_odt_write;
+	u32 emc_odt_read;
+	u32 emc_zcal_ref_cnt;
+	u32 emc_zcal_wait_cnt;
+	u32 emc_zcal_mrw_cmd;
+	u32 emc_mrs_reset_dll;
+	u32 emc_mrw_zq_init_dev0;
+	u32 emc_mrw_zq_init_dev1;
+	u32 emc_mrw_zq_init_wait;
+	u32 emc_mrs_reset_dll_wait;
+	u32 emc_emrs_emr2;
+	u32 emc_emrs_emr3;
+	u32 emc_emrs_ddr2_dll_enable;
+	u32 emc_mrs_ddr2_dll_reset;
+	u32 emc_emrs_ddr2_ocd_calib;
+	u32 emc_edr2_wait;
+	u32 emc_cfg_clktrim0;
+	u32 emc_cfg_clktrim1;
+	u32 emc_cfg_clktrim2;
+	u32 pmc_ddr_pwr;
+	u32 apb_misc_gp_xm2cfga_padctrl;
+	u32 apb_misc_gp_xm2cfgc_padctrl;
+	u32 apb_misc_gp_xm2cfgc_padctrl2;
+	u32 apb_misc_gp_xm2cfgd_padctrl;
+	u32 apb_misc_gp_xm2cfgd_padctrl2;
+	u32 apb_misc_gp_xm2clkcfg_padctrl;
+	u32 apb_misc_gp_xm2comp_padctrl;
+	u32 apb_misc_gp_xm2vttgen_padctrl;
+	u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS];
+};
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/spl.h
new file mode 100644
index 000000000..8953b00a9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/spl.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM         1
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra.h
new file mode 100644
index 000000000..6a4b40ec7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA20_H_
+#define _TEGRA20_H_
+
+#define CONFIG_TEGRA20
+
+#define NV_PA_SDRAM_BASE	0x00000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#define TEGRA_USB1_BASE		0xC5000000
+
+#define BCT_ODMDATA_OFFSET	4068	/* 12 bytes from end of BCT */
+
+#define MAX_NUM_CPU		2
+
+#endif	/* TEGRA20_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
new file mode 100644
index 000000000..e8cc68c6e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h
@@ -0,0 +1,41 @@
+/*
+ * NVIDIA Tegra20 SPI-FLASH controller
+ *
+ * Copyright 2010-2012 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA20_SPI_H_
+#define _TEGRA20_SPI_H_
+
+#include <asm/types.h>
+
+int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs);
+struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode);
+void tegra20_spi_free_slave(struct spi_slave *slave);
+int tegra20_spi_init(int *node_list, int count);
+int tegra20_spi_claim_bus(struct spi_slave *slave);
+void tegra20_spi_cs_activate(struct spi_slave *slave);
+void tegra20_spi_cs_deactivate(struct spi_slave *slave);
+int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+	     const void *data_out, void *data_in, unsigned long flags);
+
+#endif	/* _TEGRA20_SPI_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
new file mode 100644
index 000000000..5aa74ddd6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra20/tegra20_slink.h
@@ -0,0 +1,41 @@
+/*
+ * NVIDIA Tegra SPI-SLINK controller
+ *
+ * Copyright 2010-2013 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA30_SPI_H_
+#define _TEGRA30_SPI_H_
+
+#include <asm/types.h>
+
+int tegra30_spi_init(int *node_list, int count);
+int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs);
+struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode);
+void tegra30_spi_free_slave(struct spi_slave *slave);
+int tegra30_spi_claim_bus(struct spi_slave *slave);
+void tegra30_spi_cs_activate(struct spi_slave *slave);
+void tegra30_spi_cs_deactivate(struct spi_slave *slave);
+int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+		     const void *data_out, void *data_in, unsigned long flags);
+
+#endif	/* _TEGRA30_SPI_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock-tables.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock-tables.h
new file mode 100644
index 000000000..cb619f1f2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock-tables.h
@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 clock PLL tables */
+
+#ifndef _TEGRA30_CLOCK_TABLES_H_
+#define _TEGRA30_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SOC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+	CLOCK_ID_DISPLAY2,	/* Tegra3, placeholder */
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_RESERVED3,
+	PERIPH_ID_RESERVED4,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_RESERVED16,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_RESERVED45,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_DVC_I2C,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_NANDSPEED,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+	PERIPH_ID_RESERVED89,
+	PERIPH_ID_MDOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUSOUT,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_RESERVED95,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_3D2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_TSENSOR,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 08 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 16 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_EX_RESERVED17,
+	PERIPH_ID_EX_RESERVED18,
+	PERIPH_ID_EX_RESERVED19,
+	PERIPH_ID_EX_RESERVED20,
+	PERIPH_ID_EX_RESERVED21,
+	PERIPH_ID_EX_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 24 */
+	PERIPH_ID_EX_RESERVED24,
+	PERIPH_ID_EX_RESERVED25,
+	PERIPH_ID_EX_RESERVED26,
+	PERIPH_ID_EX_RESERVED27,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_EX_RESERVED30,
+	PERIPH_ID_EX_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_SATACOLD,
+	PERIPH_ID_RESERVED0_PCIERX0,
+	PERIPH_ID_RESERVED1_PCIERX1,
+	PERIPH_ID_RESERVED2_PCIERX2,
+	PERIPH_ID_RESERVED3_PCIERX3,
+	PERIPH_ID_RESERVED4_PCIERX4,
+	PERIPH_ID_RESERVED5_PCIERX5,
+
+	/* 40 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_RESERVED6_PCIE2,
+	PERIPH_ID_RESERVED7_EMC,
+	PERIPH_ID_RESERVED8_HDMI,
+	PERIPH_ID_RESERVED9_SATA,
+	PERIPH_ID_RESERVED10_MIPI,
+	PERIPH_ID_EX_RESERVED46,
+	PERIPH_ID_EX_RESERVED47,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_DVC_I2C,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_CVE,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_EPP,
+	PERIPHC_MPE,
+	PERIPHC_MIPI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_TVO,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_37h,
+
+	PERIPHC_VW_FIRST,
+	/* 0x38 */
+	PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x40 */
+	PERIPHC_AUDIO,
+	PERIPHC_41h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x48 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_SPEEDO,
+	PERIPHC_4eh,
+	PERIPHC_4fh,
+
+	/* 0x50 */
+	PERIPHC_50h,
+	PERIPHC_51h,
+	PERIPHC_52h,
+	PERIPHC_53h,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA30_CLOCK_TABLES_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock.h
new file mode 100644
index 000000000..2f24a75cc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/clock.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 clock control functions */
+
+#ifndef _TEGRA30_CLOCK_H_
+#define _TEGRA30_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+#endif	/* _TEGRA30_CLOCK_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/flow.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/flow.h
new file mode 100644
index 000000000..f5966a807
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/flow.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_FLOW_H_
+#define _TEGRA30_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;
+	u32 halt_cop_events;
+	u32 cpu_csr;
+	u32 cop_csr;
+	u32 xrq_events;
+	u32 halt_cpu1_events;
+	u32 cpu1_csr;
+	u32 halt_cpu2_events;
+	u32 cpu2_csr;
+	u32 halt_cpu3_events;
+	u32 cpu3_csr;
+	u32 cluster_control;
+};
+
+#endif	/* _TEGRA30_FLOW_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/funcmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/funcmux.h
new file mode 100644
index 000000000..24b2bca03
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/funcmux.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 high-level function multiplexing */
+
+#ifndef _TEGRA30_FUNCMUX_H_
+#define _TEGRA30_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART1_ULPI = 0,
+};
+#endif	/* _TEGRA30_FUNCMUX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
new file mode 100644
index 000000000..23d184f2d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_GP_PADCTRL_H_
+#define _TEGRA30_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	csuscfg;	/* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	lcdcfg1;	/* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
+	u32	lcdcfg2;	/* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
+	u32	sdio2cfg;	/* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	vicfg1;		/* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
+	u32	vivttgen;	/* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
+	u32	reserved1[7];	/* 0xD0-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+};
+
+/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+#define SDIOCFG_DRVUP_SLWF	1
+#define SDIOCFG_DRVDN_SLWR	1
+#define SDIOCFG_DRVUP		0x2E
+#define SDIOCFG_DRVDN		0x2A
+
+#endif	/* _TEGRA30_GP_PADCTRL_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gpio.h
new file mode 100644
index 000000000..f1c89f5a8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/gpio.h
@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_GPIO_H_
+#define _TEGRA30_GPIO_H_
+
+/*
+ * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+	uint gpio_masked_config[TEGRA_GPIO_PORTS];
+	uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_in[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+	GPIO_PA0 = 0,	/* pin 0 */
+	GPIO_PA1,
+	GPIO_PA2,
+	GPIO_PA3,
+	GPIO_PA4,
+	GPIO_PA5,
+	GPIO_PA6,
+	GPIO_PA7,
+	GPIO_PB0,	/* pin 8 */
+	GPIO_PB1,
+	GPIO_PB2,
+	GPIO_PB3,
+	GPIO_PB4,
+	GPIO_PB5,
+	GPIO_PB6,
+	GPIO_PB7,
+	GPIO_PC0,	/* pin 16 */
+	GPIO_PC1,
+	GPIO_PC2,
+	GPIO_PC3,
+	GPIO_PC4,
+	GPIO_PC5,
+	GPIO_PC6,
+	GPIO_PC7,
+	GPIO_PD0,	/* pin 24 */
+	GPIO_PD1,
+	GPIO_PD2,
+	GPIO_PD3,
+	GPIO_PD4,
+	GPIO_PD5,
+	GPIO_PD6,
+	GPIO_PD7,
+	GPIO_PE0,	/* pin 32 */
+	GPIO_PE1,
+	GPIO_PE2,
+	GPIO_PE3,
+	GPIO_PE4,
+	GPIO_PE5,
+	GPIO_PE6,
+	GPIO_PE7,
+	GPIO_PF0,	/* pin 40 */
+	GPIO_PF1,
+	GPIO_PF2,
+	GPIO_PF3,
+	GPIO_PF4,
+	GPIO_PF5,
+	GPIO_PF6,
+	GPIO_PF7,
+	GPIO_PG0,	/* pin 48 */
+	GPIO_PG1,
+	GPIO_PG2,
+	GPIO_PG3,
+	GPIO_PG4,
+	GPIO_PG5,
+	GPIO_PG6,
+	GPIO_PG7,
+	GPIO_PH0,	/* pin 56 */
+	GPIO_PH1,
+	GPIO_PH2,
+	GPIO_PH3,
+	GPIO_PH4,
+	GPIO_PH5,
+	GPIO_PH6,
+	GPIO_PH7,
+	GPIO_PI0,	/* pin 64 */
+	GPIO_PI1,
+	GPIO_PI2,
+	GPIO_PI3,
+	GPIO_PI4,
+	GPIO_PI5,
+	GPIO_PI6,
+	GPIO_PI7,
+	GPIO_PJ0,	/* pin 72 */
+	GPIO_PJ1,
+	GPIO_PJ2,
+	GPIO_PJ3,
+	GPIO_PJ4,
+	GPIO_PJ5,
+	GPIO_PJ6,
+	GPIO_PJ7,
+	GPIO_PK0,	/* pin 80 */
+	GPIO_PK1,
+	GPIO_PK2,
+	GPIO_PK3,
+	GPIO_PK4,
+	GPIO_PK5,
+	GPIO_PK6,
+	GPIO_PK7,
+	GPIO_PL0,	/* pin 88 */
+	GPIO_PL1,
+	GPIO_PL2,
+	GPIO_PL3,
+	GPIO_PL4,
+	GPIO_PL5,
+	GPIO_PL6,
+	GPIO_PL7,
+	GPIO_PM0,	/* pin 96 */
+	GPIO_PM1,
+	GPIO_PM2,
+	GPIO_PM3,
+	GPIO_PM4,
+	GPIO_PM5,
+	GPIO_PM6,
+	GPIO_PM7,
+	GPIO_PN0,	/* pin 104 */
+	GPIO_PN1,
+	GPIO_PN2,
+	GPIO_PN3,
+	GPIO_PN4,
+	GPIO_PN5,
+	GPIO_PN6,
+	GPIO_PN7,
+	GPIO_PO0,	/* pin 112 */
+	GPIO_PO1,
+	GPIO_PO2,
+	GPIO_PO3,
+	GPIO_PO4,
+	GPIO_PO5,
+	GPIO_PO6,
+	GPIO_PO7,
+	GPIO_PP0,	/* pin 120 */
+	GPIO_PP1,
+	GPIO_PP2,
+	GPIO_PP3,
+	GPIO_PP4,
+	GPIO_PP5,
+	GPIO_PP6,
+	GPIO_PP7,
+	GPIO_PQ0,	/* pin 128 */
+	GPIO_PQ1,
+	GPIO_PQ2,
+	GPIO_PQ3,
+	GPIO_PQ4,
+	GPIO_PQ5,
+	GPIO_PQ6,
+	GPIO_PQ7,
+	GPIO_PR0,	/* pin 136 */
+	GPIO_PR1,
+	GPIO_PR2,
+	GPIO_PR3,
+	GPIO_PR4,
+	GPIO_PR5,
+	GPIO_PR6,
+	GPIO_PR7,
+	GPIO_PS0,	/* pin 144 */
+	GPIO_PS1,
+	GPIO_PS2,
+	GPIO_PS3,
+	GPIO_PS4,
+	GPIO_PS5,
+	GPIO_PS6,
+	GPIO_PS7,
+	GPIO_PT0,	/* pin 152 */
+	GPIO_PT1,
+	GPIO_PT2,
+	GPIO_PT3,
+	GPIO_PT4,
+	GPIO_PT5,
+	GPIO_PT6,
+	GPIO_PT7,
+	GPIO_PU0,	/* pin 160 */
+	GPIO_PU1,
+	GPIO_PU2,
+	GPIO_PU3,
+	GPIO_PU4,
+	GPIO_PU5,
+	GPIO_PU6,
+	GPIO_PU7,
+	GPIO_PV0,	/* pin 168 */
+	GPIO_PV1,
+	GPIO_PV2,
+	GPIO_PV3,
+	GPIO_PV4,
+	GPIO_PV5,
+	GPIO_PV6,
+	GPIO_PV7,
+	GPIO_PW0,	/* pin 176 */
+	GPIO_PW1,
+	GPIO_PW2,
+	GPIO_PW3,
+	GPIO_PW4,
+	GPIO_PW5,
+	GPIO_PW6,
+	GPIO_PW7,
+	GPIO_PX0,	/* pin 184 */
+	GPIO_PX1,
+	GPIO_PX2,
+	GPIO_PX3,
+	GPIO_PX4,
+	GPIO_PX5,
+	GPIO_PX6,
+	GPIO_PX7,
+	GPIO_PY0,	/* pin 192 */
+	GPIO_PY1,
+	GPIO_PY2,
+	GPIO_PY3,
+	GPIO_PY4,
+	GPIO_PY5,
+	GPIO_PY6,
+	GPIO_PY7,
+	GPIO_PZ0,	/* pin 200 */
+	GPIO_PZ1,
+	GPIO_PZ2,
+	GPIO_PZ3,
+	GPIO_PZ4,
+	GPIO_PZ5,
+	GPIO_PZ6,
+	GPIO_PZ7,
+	GPIO_PAA0,	/* pin 208 */
+	GPIO_PAA1,
+	GPIO_PAA2,
+	GPIO_PAA3,
+	GPIO_PAA4,
+	GPIO_PAA5,
+	GPIO_PAA6,
+	GPIO_PAA7,
+	GPIO_PBB0,	/* pin 216 */
+	GPIO_PBB1,
+	GPIO_PBB2,
+	GPIO_PBB3,
+	GPIO_PBB4,
+	GPIO_PBB5,
+	GPIO_PBB6,
+	GPIO_PBB7,
+	GPIO_PCC0,	/* pin 224 */
+	GPIO_PCC1,
+	GPIO_PCC2,
+	GPIO_PCC3,
+	GPIO_PCC4,
+	GPIO_PCC5,
+	GPIO_PCC6,
+	GPIO_PCC7,
+	GPIO_PDD0,	/* pin 232 */
+	GPIO_PDD1,
+	GPIO_PDD2,
+	GPIO_PDD3,
+	GPIO_PDD4,
+	GPIO_PDD5,
+	GPIO_PDD6,
+	GPIO_PDD7,
+	GPIO_PEE0,	/* pin 240 */
+	GPIO_PEE1,
+	GPIO_PEE2,
+	GPIO_PEE3,
+	GPIO_PEE4,
+	GPIO_PEE5,
+	GPIO_PEE6,
+	GPIO_PEE7,	/* pin 247 */
+};
+
+#endif	/* _TEGRA30_GPIO_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/hardware.h
new file mode 100644
index 000000000..b1a5aa9e0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/hardware.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_HARDWARE_H_
+#define _TEGRA30_HARDWARE_H_
+
+/* include tegra specific hardware definitions */
+
+#endif /* _TEGRA30-HARDWARE_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pinmux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pinmux.h
new file mode 100644
index 000000000..6d83061dc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA30_PINMUX_H_
+#define _TEGRA30_PINMUX_H_
+
+enum pmux_pingrp {
+	PMUX_PINGRP_ULPI_DATA0_PO1,
+	PMUX_PINGRP_ULPI_DATA1_PO2,
+	PMUX_PINGRP_ULPI_DATA2_PO3,
+	PMUX_PINGRP_ULPI_DATA3_PO4,
+	PMUX_PINGRP_ULPI_DATA4_PO5,
+	PMUX_PINGRP_ULPI_DATA5_PO6,
+	PMUX_PINGRP_ULPI_DATA6_PO7,
+	PMUX_PINGRP_ULPI_DATA7_PO0,
+	PMUX_PINGRP_ULPI_CLK_PY0,
+	PMUX_PINGRP_ULPI_DIR_PY1,
+	PMUX_PINGRP_ULPI_NXT_PY2,
+	PMUX_PINGRP_ULPI_STP_PY3,
+	PMUX_PINGRP_DAP3_FS_PP0,
+	PMUX_PINGRP_DAP3_DIN_PP1,
+	PMUX_PINGRP_DAP3_DOUT_PP2,
+	PMUX_PINGRP_DAP3_SCLK_PP3,
+	PMUX_PINGRP_PV0,
+	PMUX_PINGRP_PV1,
+	PMUX_PINGRP_SDMMC1_CLK_PZ0,
+	PMUX_PINGRP_SDMMC1_CMD_PZ1,
+	PMUX_PINGRP_SDMMC1_DAT3_PY4,
+	PMUX_PINGRP_SDMMC1_DAT2_PY5,
+	PMUX_PINGRP_SDMMC1_DAT1_PY6,
+	PMUX_PINGRP_SDMMC1_DAT0_PY7,
+	PMUX_PINGRP_PV2,
+	PMUX_PINGRP_PV3,
+	PMUX_PINGRP_CLK2_OUT_PW5,
+	PMUX_PINGRP_CLK2_REQ_PCC5,
+	PMUX_PINGRP_LCD_PWR1_PC1,
+	PMUX_PINGRP_LCD_PWR2_PC6,
+	PMUX_PINGRP_LCD_SDIN_PZ2,
+	PMUX_PINGRP_LCD_SDOUT_PN5,
+	PMUX_PINGRP_LCD_WR_N_PZ3,
+	PMUX_PINGRP_LCD_CS0_N_PN4,
+	PMUX_PINGRP_LCD_DC0_PN6,
+	PMUX_PINGRP_LCD_SCK_PZ4,
+	PMUX_PINGRP_LCD_PWR0_PB2,
+	PMUX_PINGRP_LCD_PCLK_PB3,
+	PMUX_PINGRP_LCD_DE_PJ1,
+	PMUX_PINGRP_LCD_HSYNC_PJ3,
+	PMUX_PINGRP_LCD_VSYNC_PJ4,
+	PMUX_PINGRP_LCD_D0_PE0,
+	PMUX_PINGRP_LCD_D1_PE1,
+	PMUX_PINGRP_LCD_D2_PE2,
+	PMUX_PINGRP_LCD_D3_PE3,
+	PMUX_PINGRP_LCD_D4_PE4,
+	PMUX_PINGRP_LCD_D5_PE5,
+	PMUX_PINGRP_LCD_D6_PE6,
+	PMUX_PINGRP_LCD_D7_PE7,
+	PMUX_PINGRP_LCD_D8_PF0,
+	PMUX_PINGRP_LCD_D9_PF1,
+	PMUX_PINGRP_LCD_D10_PF2,
+	PMUX_PINGRP_LCD_D11_PF3,
+	PMUX_PINGRP_LCD_D12_PF4,
+	PMUX_PINGRP_LCD_D13_PF5,
+	PMUX_PINGRP_LCD_D14_PF6,
+	PMUX_PINGRP_LCD_D15_PF7,
+	PMUX_PINGRP_LCD_D16_PM0,
+	PMUX_PINGRP_LCD_D17_PM1,
+	PMUX_PINGRP_LCD_D18_PM2,
+	PMUX_PINGRP_LCD_D19_PM3,
+	PMUX_PINGRP_LCD_D20_PM4,
+	PMUX_PINGRP_LCD_D21_PM5,
+	PMUX_PINGRP_LCD_D22_PM6,
+	PMUX_PINGRP_LCD_D23_PM7,
+	PMUX_PINGRP_LCD_CS1_N_PW0,
+	PMUX_PINGRP_LCD_M1_PW1,
+	PMUX_PINGRP_LCD_DC1_PD2,
+	PMUX_PINGRP_HDMI_INT_PN7,
+	PMUX_PINGRP_DDC_SCL_PV4,
+	PMUX_PINGRP_DDC_SDA_PV5,
+	PMUX_PINGRP_CRT_HSYNC_PV6,
+	PMUX_PINGRP_CRT_VSYNC_PV7,
+	PMUX_PINGRP_VI_D0_PT4,
+	PMUX_PINGRP_VI_D1_PD5,
+	PMUX_PINGRP_VI_D2_PL0,
+	PMUX_PINGRP_VI_D3_PL1,
+	PMUX_PINGRP_VI_D4_PL2,
+	PMUX_PINGRP_VI_D5_PL3,
+	PMUX_PINGRP_VI_D6_PL4,
+	PMUX_PINGRP_VI_D7_PL5,
+	PMUX_PINGRP_VI_D8_PL6,
+	PMUX_PINGRP_VI_D9_PL7,
+	PMUX_PINGRP_VI_D10_PT2,
+	PMUX_PINGRP_VI_D11_PT3,
+	PMUX_PINGRP_VI_PCLK_PT0,
+	PMUX_PINGRP_VI_MCLK_PT1,
+	PMUX_PINGRP_VI_VSYNC_PD6,
+	PMUX_PINGRP_VI_HSYNC_PD7,
+	PMUX_PINGRP_UART2_RXD_PC3,
+	PMUX_PINGRP_UART2_TXD_PC2,
+	PMUX_PINGRP_UART2_RTS_N_PJ6,
+	PMUX_PINGRP_UART2_CTS_N_PJ5,
+	PMUX_PINGRP_UART3_TXD_PW6,
+	PMUX_PINGRP_UART3_RXD_PW7,
+	PMUX_PINGRP_UART3_CTS_N_PA1,
+	PMUX_PINGRP_UART3_RTS_N_PC0,
+	PMUX_PINGRP_PU0,
+	PMUX_PINGRP_PU1,
+	PMUX_PINGRP_PU2,
+	PMUX_PINGRP_PU3,
+	PMUX_PINGRP_PU4,
+	PMUX_PINGRP_PU5,
+	PMUX_PINGRP_PU6,
+	PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+	PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+	PMUX_PINGRP_DAP4_FS_PP4,
+	PMUX_PINGRP_DAP4_DIN_PP5,
+	PMUX_PINGRP_DAP4_DOUT_PP6,
+	PMUX_PINGRP_DAP4_SCLK_PP7,
+	PMUX_PINGRP_CLK3_OUT_PEE0,
+	PMUX_PINGRP_CLK3_REQ_PEE1,
+	PMUX_PINGRP_GMI_WP_N_PC7,
+	PMUX_PINGRP_GMI_IORDY_PI5,
+	PMUX_PINGRP_GMI_WAIT_PI7,
+	PMUX_PINGRP_GMI_ADV_N_PK0,
+	PMUX_PINGRP_GMI_CLK_PK1,
+	PMUX_PINGRP_GMI_CS0_N_PJ0,
+	PMUX_PINGRP_GMI_CS1_N_PJ2,
+	PMUX_PINGRP_GMI_CS2_N_PK3,
+	PMUX_PINGRP_GMI_CS3_N_PK4,
+	PMUX_PINGRP_GMI_CS4_N_PK2,
+	PMUX_PINGRP_GMI_CS6_N_PI3,
+	PMUX_PINGRP_GMI_CS7_N_PI6,
+	PMUX_PINGRP_GMI_AD0_PG0,
+	PMUX_PINGRP_GMI_AD1_PG1,
+	PMUX_PINGRP_GMI_AD2_PG2,
+	PMUX_PINGRP_GMI_AD3_PG3,
+	PMUX_PINGRP_GMI_AD4_PG4,
+	PMUX_PINGRP_GMI_AD5_PG5,
+	PMUX_PINGRP_GMI_AD6_PG6,
+	PMUX_PINGRP_GMI_AD7_PG7,
+	PMUX_PINGRP_GMI_AD8_PH0,
+	PMUX_PINGRP_GMI_AD9_PH1,
+	PMUX_PINGRP_GMI_AD10_PH2,
+	PMUX_PINGRP_GMI_AD11_PH3,
+	PMUX_PINGRP_GMI_AD12_PH4,
+	PMUX_PINGRP_GMI_AD13_PH5,
+	PMUX_PINGRP_GMI_AD14_PH6,
+	PMUX_PINGRP_GMI_AD15_PH7,
+	PMUX_PINGRP_GMI_A16_PJ7,
+	PMUX_PINGRP_GMI_A17_PB0,
+	PMUX_PINGRP_GMI_A18_PB1,
+	PMUX_PINGRP_GMI_A19_PK7,
+	PMUX_PINGRP_GMI_WR_N_PI0,
+	PMUX_PINGRP_GMI_OE_N_PI1,
+	PMUX_PINGRP_GMI_DQS_PI2,
+	PMUX_PINGRP_GMI_RST_N_PI4,
+	PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+	PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+	PMUX_PINGRP_SDMMC4_CLK_PCC4,
+	PMUX_PINGRP_SDMMC4_CMD_PT7,
+	PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+	PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+	PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+	PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+	PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+	PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+	PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+	PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+	PMUX_PINGRP_SDMMC4_RST_N_PCC3,
+	PMUX_PINGRP_CAM_MCLK_PCC0,
+	PMUX_PINGRP_PCC1,
+	PMUX_PINGRP_PBB0,
+	PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+	PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+	PMUX_PINGRP_PBB3,
+	PMUX_PINGRP_PBB4,
+	PMUX_PINGRP_PBB5,
+	PMUX_PINGRP_PBB6,
+	PMUX_PINGRP_PBB7,
+	PMUX_PINGRP_PCC2,
+	PMUX_PINGRP_JTAG_RTCK_PU7,
+	PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+	PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+	PMUX_PINGRP_KB_ROW0_PR0,
+	PMUX_PINGRP_KB_ROW1_PR1,
+	PMUX_PINGRP_KB_ROW2_PR2,
+	PMUX_PINGRP_KB_ROW3_PR3,
+	PMUX_PINGRP_KB_ROW4_PR4,
+	PMUX_PINGRP_KB_ROW5_PR5,
+	PMUX_PINGRP_KB_ROW6_PR6,
+	PMUX_PINGRP_KB_ROW7_PR7,
+	PMUX_PINGRP_KB_ROW8_PS0,
+	PMUX_PINGRP_KB_ROW9_PS1,
+	PMUX_PINGRP_KB_ROW10_PS2,
+	PMUX_PINGRP_KB_ROW11_PS3,
+	PMUX_PINGRP_KB_ROW12_PS4,
+	PMUX_PINGRP_KB_ROW13_PS5,
+	PMUX_PINGRP_KB_ROW14_PS6,
+	PMUX_PINGRP_KB_ROW15_PS7,
+	PMUX_PINGRP_KB_COL0_PQ0,
+	PMUX_PINGRP_KB_COL1_PQ1,
+	PMUX_PINGRP_KB_COL2_PQ2,
+	PMUX_PINGRP_KB_COL3_PQ3,
+	PMUX_PINGRP_KB_COL4_PQ4,
+	PMUX_PINGRP_KB_COL5_PQ5,
+	PMUX_PINGRP_KB_COL6_PQ6,
+	PMUX_PINGRP_KB_COL7_PQ7,
+	PMUX_PINGRP_CLK_32K_OUT_PA0,
+	PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+	PMUX_PINGRP_CORE_PWR_REQ,
+	PMUX_PINGRP_CPU_PWR_REQ,
+	PMUX_PINGRP_PWR_INT_N,
+	PMUX_PINGRP_CLK_32K_IN,
+	PMUX_PINGRP_OWR,
+	PMUX_PINGRP_DAP1_FS_PN0,
+	PMUX_PINGRP_DAP1_DIN_PN1,
+	PMUX_PINGRP_DAP1_DOUT_PN2,
+	PMUX_PINGRP_DAP1_SCLK_PN3,
+	PMUX_PINGRP_CLK1_REQ_PEE2,
+	PMUX_PINGRP_CLK1_OUT_PW4,
+	PMUX_PINGRP_SPDIF_IN_PK6,
+	PMUX_PINGRP_SPDIF_OUT_PK5,
+	PMUX_PINGRP_DAP2_FS_PA2,
+	PMUX_PINGRP_DAP2_DIN_PA4,
+	PMUX_PINGRP_DAP2_DOUT_PA5,
+	PMUX_PINGRP_DAP2_SCLK_PA3,
+	PMUX_PINGRP_SPI2_MOSI_PX0,
+	PMUX_PINGRP_SPI2_MISO_PX1,
+	PMUX_PINGRP_SPI2_CS0_N_PX3,
+	PMUX_PINGRP_SPI2_SCK_PX2,
+	PMUX_PINGRP_SPI1_MOSI_PX4,
+	PMUX_PINGRP_SPI1_SCK_PX5,
+	PMUX_PINGRP_SPI1_CS0_N_PX6,
+	PMUX_PINGRP_SPI1_MISO_PX7,
+	PMUX_PINGRP_SPI2_CS1_N_PW2,
+	PMUX_PINGRP_SPI2_CS2_N_PW3,
+	PMUX_PINGRP_SDMMC3_CLK_PA6,
+	PMUX_PINGRP_SDMMC3_CMD_PA7,
+	PMUX_PINGRP_SDMMC3_DAT0_PB7,
+	PMUX_PINGRP_SDMMC3_DAT1_PB6,
+	PMUX_PINGRP_SDMMC3_DAT2_PB5,
+	PMUX_PINGRP_SDMMC3_DAT3_PB4,
+	PMUX_PINGRP_SDMMC3_DAT4_PD1,
+	PMUX_PINGRP_SDMMC3_DAT5_PD0,
+	PMUX_PINGRP_SDMMC3_DAT6_PD3,
+	PMUX_PINGRP_SDMMC3_DAT7_PD4,
+	PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0,
+	PMUX_PINGRP_PEX_L0_RST_N_PDD1,
+	PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+	PMUX_PINGRP_PEX_WAKE_N_PDD3,
+	PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4,
+	PMUX_PINGRP_PEX_L1_RST_N_PDD5,
+	PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+	PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7,
+	PMUX_PINGRP_PEX_L2_RST_N_PCC6,
+	PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7,
+	PMUX_PINGRP_HDMI_CEC_PEE3,
+	PMUX_PINGRP_COUNT,
+};
+
+enum pmux_drvgrp {
+	PMUX_DRVGRP_AO1,
+	PMUX_DRVGRP_AO2,
+	PMUX_DRVGRP_AT1,
+	PMUX_DRVGRP_AT2,
+	PMUX_DRVGRP_AT3,
+	PMUX_DRVGRP_AT4,
+	PMUX_DRVGRP_AT5,
+	PMUX_DRVGRP_CDEV1,
+	PMUX_DRVGRP_CDEV2,
+	PMUX_DRVGRP_CSUS,
+	PMUX_DRVGRP_DAP1,
+	PMUX_DRVGRP_DAP2,
+	PMUX_DRVGRP_DAP3,
+	PMUX_DRVGRP_DAP4,
+	PMUX_DRVGRP_DBG,
+	PMUX_DRVGRP_LCD1,
+	PMUX_DRVGRP_LCD2,
+	PMUX_DRVGRP_SDIO2,
+	PMUX_DRVGRP_SDIO3,
+	PMUX_DRVGRP_SPI,
+	PMUX_DRVGRP_UAA,
+	PMUX_DRVGRP_UAB,
+	PMUX_DRVGRP_UART2,
+	PMUX_DRVGRP_UART3,
+	PMUX_DRVGRP_VI1,
+	PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+	PMUX_DRVGRP_CRT = (0x90 / 4),
+	PMUX_DRVGRP_DDC,
+	PMUX_DRVGRP_GMA,
+	PMUX_DRVGRP_GMB,
+	PMUX_DRVGRP_GMC,
+	PMUX_DRVGRP_GMD,
+	PMUX_DRVGRP_GME,
+	PMUX_DRVGRP_GMF,
+	PMUX_DRVGRP_GMG,
+	PMUX_DRVGRP_GMH,
+	PMUX_DRVGRP_OWR,
+	PMUX_DRVGRP_UDA,
+	PMUX_DRVGRP_GPV,
+	PMUX_DRVGRP_DEV3,
+	PMUX_DRVGRP_CEC = (0xd0 / 4),
+	PMUX_DRVGRP_COUNT,
+};
+
+enum pmux_func {
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLK_12M_OUT,
+	PMUX_FUNC_CLK_32K_IN,
+	PMUX_FUNC_CORE_PWR_REQ,
+	PMUX_FUNC_CPU_PWR_REQ,
+	PMUX_FUNC_CRT,
+	PMUX_FUNC_DAP,
+	PMUX_FUNC_DDR,
+	PMUX_FUNC_DEV3,
+	PMUX_FUNC_DISPLAYA,
+	PMUX_FUNC_DISPLAYB,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_EXTPERIPH1,
+	PMUX_FUNC_EXTPERIPH2,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_ALT,
+	PMUX_FUNC_HDA,
+	PMUX_FUNC_HDCP,
+	PMUX_FUNC_HDMI,
+	PMUX_FUNC_HSI,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_I2C4,
+	PMUX_FUNC_I2CPWR,
+	PMUX_FUNC_I2S0,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4,
+	PMUX_FUNC_INVALID,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_MIO,
+	PMUX_FUNC_NAND,
+	PMUX_FUNC_NAND_ALT,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PCIE,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_PWR_INT_N,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SATA,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC2,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SDMMC4,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI2_ALT,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_SPI5,
+	PMUX_FUNC_SPI6,
+	PMUX_FUNC_SYSCLK,
+	PMUX_FUNC_TEST,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_UARTE,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_ALT1,
+	PMUX_FUNC_VI_ALT2,
+	PMUX_FUNC_VI_ALT3,
+	PMUX_FUNC_RSVD1,
+	PMUX_FUNC_RSVD2,
+	PMUX_FUNC_RSVD3,
+	PMUX_FUNC_RSVD4,
+	PMUX_FUNC_COUNT,
+};
+
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_DRVGRPS
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA30_PINMUX_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pmu.h
new file mode 100644
index 000000000..52bea29bb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/pmu.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_PMU_H_
+#define _TEGRA30_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif	/* _TEGRA30_PMU_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/spl.h
new file mode 100644
index 000000000..8953b00a9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/spl.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM         1
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/tegra.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/tegra.h
new file mode 100644
index 000000000..4ad8b1c05
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_H_
+#define _TEGRA30_H_
+
+#define CONFIG_TEGRA30
+
+#define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T30 */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define TEGRA_USB1_BASE		0x7D000000
+
+#define BCT_ODMDATA_OFFSET	6116	/* 12 bytes from end of BCT */
+
+#define MAX_NUM_CPU		4
+
+#endif	/* TEGRA30_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/clock.h
new file mode 100644
index 000000000..dfc3b1bfa
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/clock.h
@@ -0,0 +1,53 @@
+/*
+ * TNETV107X: Clock APIs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#define PSC_MDCTL_NEXT_SWRSTDISABLE	0x0
+#define PSC_MDCTL_NEXT_SYNCRST		0x1
+#define PSC_MDCTL_NEXT_DISABLE		0x2
+#define PSC_MDCTL_NEXT_ENABLE		0x3
+
+#define CONFIG_SYS_INT_OSC_FREQ		24000000
+
+#ifndef __ASSEMBLY__
+
+/* PLL identifiers */
+enum pll_type_e {
+	SYS_PLL,
+	TDM_PLL,
+	ETH_PLL
+};
+
+/* PLL configuration data */
+struct pll_init_data {
+	int pll;
+	int internal_osc;
+	unsigned long pll_freq;
+	unsigned long div_freq[10];
+};
+
+void init_plls(int num_pll, struct pll_init_data *config);
+int  lpsc_status(unsigned int mod);
+void lpsc_control(int mod, unsigned long state, int lrstz);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+static inline void clk_enable(unsigned int mod)
+{
+	lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
+}
+
+static inline void clk_disable(unsigned int mod)
+{
+	lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
+}
+
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/emif_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
new file mode 100644
index 000000000..9969a018e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
@@ -0,0 +1 @@
+#include <asm/arch-davinci/emif_defs.h>
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/hardware.h
new file mode 100644
index 000000000..2a7ca4e00
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/hardware.h
@@ -0,0 +1,158 @@
+/*
+ * TNETV107X: Hardware information
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/sizes.h>
+
+#define ASYNC_EMIF_NUM_CS		4
+#define ASYNC_EMIF_MODE_NOR		0
+#define ASYNC_EMIF_MODE_NAND		1
+#define ASYNC_EMIF_MODE_ONENAND		2
+#define ASYNC_EMIF_PRESERVE		-1
+
+struct async_emif_config {
+	unsigned mode;
+	unsigned select_strobe;
+	unsigned extend_wait;
+	unsigned wr_setup;
+	unsigned wr_strobe;
+	unsigned wr_hold;
+	unsigned rd_setup;
+	unsigned rd_strobe;
+	unsigned rd_hold;
+	unsigned turn_around;
+	enum {
+		ASYNC_EMIF_8	= 0,
+		ASYNC_EMIF_16	= 1,
+		ASYNC_EMIF_32	= 2,
+	} width;
+};
+
+void init_async_emif(int num_cs, struct async_emif_config *config);
+
+int wdt_start(unsigned long msecs);
+int wdt_stop(void);
+int wdt_kick(void);
+
+#endif
+
+/* Chip configuration unlock codes and registers */
+#define TNETV107X_KICK0		(TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
+#define TNETV107X_KICK1		(TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
+#define TNETV107X_PINMUX(n)	(TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
+#define TNETV107X_KICK0_MAGIC	0x83e70b13
+#define TNETV107X_KICK1_MAGIC	0x95a4f1e0
+
+/* Module base addresses */
+#define TNETV107X_TPCC_BASE			0x01C00000
+#define TNETV107X_TPTC0_BASE			0x01C10000
+#define TNETV107X_TPTC1_BASE			0x01C10400
+#define TNETV107X_INTC_BASE			0x03000000
+#define TNETV107X_LCD_CONTROLLER_BASE		0x08030000
+#define TNETV107X_INTD_BASE			0x08038000
+#define TNETV107X_INTD_IPC_BASE			0x08038000
+#define TNETV107X_INTD_FAST_BASE		0x08039000
+#define TNETV107X_INTD_ASYNC_BASE		0x0803A000
+#define TNETV107X_INTD_SLOW_BASE		0x0803B000
+#define TNETV107X_PKA_BASE			0x08040000
+#define TNETV107X_RNG_BASE			0x08044000
+#define TNETV107X_TIMER0_BASE			0x08086500
+#define TNETV107X_TIMER1_BASE			0x08086600
+#define TNETV107X_WDT0_ARM_BASE			0x08086700
+#define TNETV107X_WDT1_DSP_BASE			0x08086800
+#define TNETV107X_CHIP_CONFIG_SYS_BASE		0x08087000
+#define TNETV107X_GPIO_BASE			0x08088000
+#define TNETV107X_UART1_BASE			0x08088400
+#define TNETV107X_TOUCHSCREEN_BASE		0x08088500
+#define TNETV107X_SDIO0_BASE			0x08088700
+#define TNETV107X_SDIO1_BASE			0x08088800
+#define TNETV107X_MDIO_BASE			0x08088900
+#define TNETV107X_KEYPAD_BASE			0x08088A00
+#define TNETV107X_SSP_BASE			0x08088C00
+#define TNETV107X_CLOCK_CONTROL_BASE		0x0808A000
+#define TNETV107X_PSC_BASE			0x0808B000
+#define TNETV107X_TDM0_BASE			0x08100000
+#define TNETV107X_TDM1_BASE			0x08100100
+#define TNETV107X_MCDMA_BASE			0x08108000
+#define TNETV107X_UART0_DMA_BASE		0x08108200
+#define TNETV107X_USBSS_BASE			0x08120000
+#define TNETV107X_VLYNQ_CONTROL_BASE		0x0810D000
+#define TNETV107X_ASYNC_EMIF_CNTRL_BASE		0x08200000
+#define TNETV107X_VLYNQ_MEM_MAP_BASE		0x0C000000
+#define TNETV107X_IMCOP_BASE			0x01CC0000
+#define TNETV107X_MBX_LITE_BASE			0x07000000
+#define TNETV107X_ETHSS_BASE			0x0803C000
+#define TNETV107X_CPSW_BASE			0x0803C000
+#define TNETV107X_SPF_BASE			0x0803C800
+#define TNETV107X_IOPU_ETHSS_BASE		0x0803D000
+#define TNETV107X_VTP_CNTRL_0			0x0803D800
+#define TNETV107X_VTP_CNTRL_1			0x0803D900
+#define TNETV107X_UART2_DMA_BASE		0x08108400
+#define TNETV107X_INTERNAL_MEMORY		0x20000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE	0x30000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE	0x40000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE	0x44000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
+#define TNETV107X_DDR_EMIF_DATA_BASE		0x80000000
+#define TNETV107X_DDR_EMIF_CONTROL_BASE		0x90000000
+
+/* LPSC module definitions */
+#define TNETV107X_LPSC_ARM			0
+#define TNETV107X_LPSC_GEM			1
+#define TNETV107X_LPSC_DDR2_PHY			2
+#define TNETV107X_LPSC_TPCC			3
+#define TNETV107X_LPSC_TPTC0			4
+#define TNETV107X_LPSC_TPTC1			5
+#define TNETV107X_LPSC_RAM			6
+#define TNETV107X_LPSC_MBX_LITE			7
+#define TNETV107X_LPSC_LCD			8
+#define TNETV107X_LPSC_ETHSS			9
+#define TNETV107X_LPSC_AEMIF			10
+#define TNETV107X_LPSC_CHIP_CFG			11
+#define TNETV107X_LPSC_TSC			12
+#define TNETV107X_LPSC_ROM			13
+#define TNETV107X_LPSC_UART2			14
+#define TNETV107X_LPSC_PKTSEC			15
+#define TNETV107X_LPSC_SECCTL			16
+#define TNETV107X_LPSC_KEYMGR			17
+#define TNETV107X_LPSC_KEYPAD			18
+#define TNETV107X_LPSC_GPIO			19
+#define TNETV107X_LPSC_MDIO			20
+#define TNETV107X_LPSC_SDIO0			21
+#define TNETV107X_LPSC_UART0			22
+#define TNETV107X_LPSC_UART1			23
+#define TNETV107X_LPSC_TIMER0			24
+#define TNETV107X_LPSC_TIMER1			25
+#define TNETV107X_LPSC_WDT_ARM			26
+#define TNETV107X_LPSC_WDT_DSP			27
+#define TNETV107X_LPSC_SSP			28
+#define TNETV107X_LPSC_TDM0			29
+#define TNETV107X_LPSC_VLYNQ			30
+#define TNETV107X_LPSC_MCDMA			31
+#define TNETV107X_LPSC_USB0			32
+#define TNETV107X_LPSC_TDM1			33
+#define TNETV107X_LPSC_DEBUGSS			34
+#define TNETV107X_LPSC_ETHSS_RGMII		35
+#define TNETV107X_LPSC_SYSTEM			36
+#define TNETV107X_LPSC_IMCOP			37
+#define TNETV107X_LPSC_SPARE			38
+#define TNETV107X_LPSC_SDIO1			39
+#define TNETV107X_LPSC_USB1			40
+#define TNETV107X_LPSC_USBSS			41
+#define TNETV107X_LPSC_DDR2_EMIF1_VRST		42
+#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST	43
+#define TNETV107X_LPSC_MAX			44
+
+/* Interrupt controller */
+#define INTC_GLB_EN			(TNETV107X_INTC_BASE + 0x10)
+#define INTC_HINT_EN			(TNETV107X_INTC_BASE + 0x1500)
+#define INTC_EN_CLR0			(TNETV107X_INTC_BASE + 0x380)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/mux.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/mux.h
new file mode 100644
index 000000000..3f832c414
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/mux.h
@@ -0,0 +1,291 @@
+/*
+ * TNETV107X: Pinmux APIs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MUX_H
+#define __ASM_ARCH_MUX_H
+
+struct pin_config {
+	unsigned char reg_index;
+	unsigned char mask_offset;
+	unsigned char mode;
+};
+
+#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
+			{ reg, offset, mux_mode }
+
+int mux_select_pin(short index);
+int mux_select_pins(const short *pins);
+
+enum tnetv107x_pin_mux_index {
+	TNETV107X_PIN_ASR_A00,
+	TNETV107X_PIN_GPIO32,
+	TNETV107X_PIN_ASR_A01,
+	TNETV107X_PIN_GPIO33,
+	TNETV107X_PIN_ASR_A02,
+	TNETV107X_PIN_GPIO34,
+	TNETV107X_PIN_ASR_A03,
+	TNETV107X_PIN_GPIO35,
+	TNETV107X_PIN_ASR_A04,
+	TNETV107X_PIN_GPIO36,
+	TNETV107X_PIN_ASR_A05,
+	TNETV107X_PIN_GPIO37,
+	TNETV107X_PIN_ASR_A06,
+	TNETV107X_PIN_GPIO38,
+	TNETV107X_PIN_ASR_A07,
+	TNETV107X_PIN_GPIO39,
+	TNETV107X_PIN_ASR_A08,
+	TNETV107X_PIN_GPIO40,
+	TNETV107X_PIN_ASR_A09,
+	TNETV107X_PIN_GPIO41,
+	TNETV107X_PIN_ASR_A10,
+	TNETV107X_PIN_GPIO42,
+	TNETV107X_PIN_ASR_A11,
+	TNETV107X_PIN_BOOT_STRP_0,
+	TNETV107X_PIN_ASR_A12,
+	TNETV107X_PIN_BOOT_STRP_1,
+	TNETV107X_PIN_ASR_A13,
+	TNETV107X_PIN_GPIO43,
+	TNETV107X_PIN_ASR_A14,
+	TNETV107X_PIN_GPIO44,
+	TNETV107X_PIN_ASR_A15,
+	TNETV107X_PIN_GPIO45,
+	TNETV107X_PIN_ASR_A16,
+	TNETV107X_PIN_GPIO46,
+	TNETV107X_PIN_ASR_A17,
+	TNETV107X_PIN_GPIO47,
+	TNETV107X_PIN_ASR_A18,
+	TNETV107X_PIN_GPIO48,
+	TNETV107X_PIN_SDIO1_DATA3_0,
+	TNETV107X_PIN_ASR_A19,
+	TNETV107X_PIN_GPIO49,
+	TNETV107X_PIN_SDIO1_DATA2_0,
+	TNETV107X_PIN_ASR_A20,
+	TNETV107X_PIN_GPIO50,
+	TNETV107X_PIN_SDIO1_DATA1_0,
+	TNETV107X_PIN_ASR_A21,
+	TNETV107X_PIN_GPIO51,
+	TNETV107X_PIN_SDIO1_DATA0_0,
+	TNETV107X_PIN_ASR_A22,
+	TNETV107X_PIN_GPIO52,
+	TNETV107X_PIN_SDIO1_CMD_0,
+	TNETV107X_PIN_ASR_A23,
+	TNETV107X_PIN_GPIO53,
+	TNETV107X_PIN_SDIO1_CLK_0,
+	TNETV107X_PIN_ASR_BA_1,
+	TNETV107X_PIN_GPIO54,
+	TNETV107X_PIN_SYS_PLL_CLK,
+	TNETV107X_PIN_ASR_CS0,
+	TNETV107X_PIN_ASR_CS1,
+	TNETV107X_PIN_ASR_CS2,
+	TNETV107X_PIN_TDM_PLL_CLK,
+	TNETV107X_PIN_ASR_CS3,
+	TNETV107X_PIN_ETH_PHY_CLK,
+	TNETV107X_PIN_ASR_D00,
+	TNETV107X_PIN_GPIO55,
+	TNETV107X_PIN_ASR_D01,
+	TNETV107X_PIN_GPIO56,
+	TNETV107X_PIN_ASR_D02,
+	TNETV107X_PIN_GPIO57,
+	TNETV107X_PIN_ASR_D03,
+	TNETV107X_PIN_GPIO58,
+	TNETV107X_PIN_ASR_D04,
+	TNETV107X_PIN_GPIO59_0,
+	TNETV107X_PIN_ASR_D05,
+	TNETV107X_PIN_GPIO60_0,
+	TNETV107X_PIN_ASR_D06,
+	TNETV107X_PIN_GPIO61_0,
+	TNETV107X_PIN_ASR_D07,
+	TNETV107X_PIN_GPIO62_0,
+	TNETV107X_PIN_ASR_D08,
+	TNETV107X_PIN_GPIO63_0,
+	TNETV107X_PIN_ASR_D09,
+	TNETV107X_PIN_GPIO64_0,
+	TNETV107X_PIN_ASR_D10,
+	TNETV107X_PIN_SDIO1_DATA3_1,
+	TNETV107X_PIN_ASR_D11,
+	TNETV107X_PIN_SDIO1_DATA2_1,
+	TNETV107X_PIN_ASR_D12,
+	TNETV107X_PIN_SDIO1_DATA1_1,
+	TNETV107X_PIN_ASR_D13,
+	TNETV107X_PIN_SDIO1_DATA0_1,
+	TNETV107X_PIN_ASR_D14,
+	TNETV107X_PIN_SDIO1_CMD_1,
+	TNETV107X_PIN_ASR_D15,
+	TNETV107X_PIN_SDIO1_CLK_1,
+	TNETV107X_PIN_ASR_OE,
+	TNETV107X_PIN_BOOT_STRP_2,
+	TNETV107X_PIN_ASR_RNW,
+	TNETV107X_PIN_GPIO29_0,
+	TNETV107X_PIN_ASR_WAIT,
+	TNETV107X_PIN_GPIO30_0,
+	TNETV107X_PIN_ASR_WE,
+	TNETV107X_PIN_BOOT_STRP_3,
+	TNETV107X_PIN_ASR_WE_DQM0,
+	TNETV107X_PIN_GPIO31,
+	TNETV107X_PIN_LCD_PD17_0,
+	TNETV107X_PIN_ASR_WE_DQM1,
+	TNETV107X_PIN_ASR_BA0_0,
+	TNETV107X_PIN_VLYNQ_CLK,
+	TNETV107X_PIN_GPIO14,
+	TNETV107X_PIN_LCD_PD19_0,
+	TNETV107X_PIN_VLYNQ_RXD0,
+	TNETV107X_PIN_GPIO15,
+	TNETV107X_PIN_LCD_PD20_0,
+	TNETV107X_PIN_VLYNQ_RXD1,
+	TNETV107X_PIN_GPIO16,
+	TNETV107X_PIN_LCD_PD21_0,
+	TNETV107X_PIN_VLYNQ_TXD0,
+	TNETV107X_PIN_GPIO17,
+	TNETV107X_PIN_LCD_PD22_0,
+	TNETV107X_PIN_VLYNQ_TXD1,
+	TNETV107X_PIN_GPIO18,
+	TNETV107X_PIN_LCD_PD23_0,
+	TNETV107X_PIN_SDIO0_CLK,
+	TNETV107X_PIN_GPIO19,
+	TNETV107X_PIN_SDIO0_CMD,
+	TNETV107X_PIN_GPIO20,
+	TNETV107X_PIN_SDIO0_DATA0,
+	TNETV107X_PIN_GPIO21,
+	TNETV107X_PIN_SDIO0_DATA1,
+	TNETV107X_PIN_GPIO22,
+	TNETV107X_PIN_SDIO0_DATA2,
+	TNETV107X_PIN_GPIO23,
+	TNETV107X_PIN_SDIO0_DATA3,
+	TNETV107X_PIN_GPIO24,
+	TNETV107X_PIN_EMU0,
+	TNETV107X_PIN_EMU1,
+	TNETV107X_PIN_RTCK,
+	TNETV107X_PIN_TRST_N,
+	TNETV107X_PIN_TCK,
+	TNETV107X_PIN_TDI,
+	TNETV107X_PIN_TDO,
+	TNETV107X_PIN_TMS,
+	TNETV107X_PIN_TDM1_CLK,
+	TNETV107X_PIN_TDM1_RX,
+	TNETV107X_PIN_TDM1_TX,
+	TNETV107X_PIN_TDM1_FS,
+	TNETV107X_PIN_KEYPAD_R0,
+	TNETV107X_PIN_KEYPAD_R1,
+	TNETV107X_PIN_KEYPAD_R2,
+	TNETV107X_PIN_KEYPAD_R3,
+	TNETV107X_PIN_KEYPAD_R4,
+	TNETV107X_PIN_KEYPAD_R5,
+	TNETV107X_PIN_KEYPAD_R6,
+	TNETV107X_PIN_GPIO12,
+	TNETV107X_PIN_KEYPAD_R7,
+	TNETV107X_PIN_GPIO10,
+	TNETV107X_PIN_KEYPAD_C0,
+	TNETV107X_PIN_KEYPAD_C1,
+	TNETV107X_PIN_KEYPAD_C2,
+	TNETV107X_PIN_KEYPAD_C3,
+	TNETV107X_PIN_KEYPAD_C4,
+	TNETV107X_PIN_KEYPAD_C5,
+	TNETV107X_PIN_KEYPAD_C6,
+	TNETV107X_PIN_GPIO13,
+	TNETV107X_PIN_TEST_CLK_IN,
+	TNETV107X_PIN_KEYPAD_C7,
+	TNETV107X_PIN_GPIO11,
+	TNETV107X_PIN_SSP0_0,
+	TNETV107X_PIN_SCC_DCLK,
+	TNETV107X_PIN_LCD_PD20_1,
+	TNETV107X_PIN_SSP0_1,
+	TNETV107X_PIN_SCC_CS_N,
+	TNETV107X_PIN_LCD_PD21_1,
+	TNETV107X_PIN_SSP0_2,
+	TNETV107X_PIN_SCC_D,
+	TNETV107X_PIN_LCD_PD22_1,
+	TNETV107X_PIN_SSP0_3,
+	TNETV107X_PIN_SCC_RESETN,
+	TNETV107X_PIN_LCD_PD23_1,
+	TNETV107X_PIN_SSP1_0,
+	TNETV107X_PIN_GPIO25,
+	TNETV107X_PIN_UART2_CTS,
+	TNETV107X_PIN_SSP1_1,
+	TNETV107X_PIN_GPIO26,
+	TNETV107X_PIN_UART2_RD,
+	TNETV107X_PIN_SSP1_2,
+	TNETV107X_PIN_GPIO27,
+	TNETV107X_PIN_UART2_RTS,
+	TNETV107X_PIN_SSP1_3,
+	TNETV107X_PIN_GPIO28,
+	TNETV107X_PIN_UART2_TD,
+	TNETV107X_PIN_UART0_CTS,
+	TNETV107X_PIN_UART0_RD,
+	TNETV107X_PIN_UART0_RTS,
+	TNETV107X_PIN_UART0_TD,
+	TNETV107X_PIN_UART1_RD,
+	TNETV107X_PIN_UART1_TD,
+	TNETV107X_PIN_LCD_AC_NCS,
+	TNETV107X_PIN_LCD_HSYNC_RNW,
+	TNETV107X_PIN_LCD_VSYNC_A0,
+	TNETV107X_PIN_LCD_MCLK,
+	TNETV107X_PIN_LCD_PD16_0,
+	TNETV107X_PIN_LCD_PCLK_E,
+	TNETV107X_PIN_LCD_PD00,
+	TNETV107X_PIN_LCD_PD01,
+	TNETV107X_PIN_LCD_PD02,
+	TNETV107X_PIN_LCD_PD03,
+	TNETV107X_PIN_LCD_PD04,
+	TNETV107X_PIN_LCD_PD05,
+	TNETV107X_PIN_LCD_PD06,
+	TNETV107X_PIN_LCD_PD07,
+	TNETV107X_PIN_LCD_PD08,
+	TNETV107X_PIN_GPIO59_1,
+	TNETV107X_PIN_LCD_PD09,
+	TNETV107X_PIN_GPIO60_1,
+	TNETV107X_PIN_LCD_PD10,
+	TNETV107X_PIN_ASR_BA0_1,
+	TNETV107X_PIN_GPIO61_1,
+	TNETV107X_PIN_LCD_PD11,
+	TNETV107X_PIN_GPIO62_1,
+	TNETV107X_PIN_LCD_PD12,
+	TNETV107X_PIN_GPIO63_1,
+	TNETV107X_PIN_LCD_PD13,
+	TNETV107X_PIN_GPIO64_1,
+	TNETV107X_PIN_LCD_PD14,
+	TNETV107X_PIN_GPIO29_1,
+	TNETV107X_PIN_LCD_PD15,
+	TNETV107X_PIN_GPIO30_1,
+	TNETV107X_PIN_EINT0,
+	TNETV107X_PIN_GPIO08,
+	TNETV107X_PIN_EINT1,
+	TNETV107X_PIN_GPIO09,
+	TNETV107X_PIN_GPIO00,
+	TNETV107X_PIN_LCD_PD20_2,
+	TNETV107X_PIN_TDM_CLK_IN_2,
+	TNETV107X_PIN_GPIO01,
+	TNETV107X_PIN_LCD_PD21_2,
+	TNETV107X_PIN_24M_CLK_OUT_1,
+	TNETV107X_PIN_GPIO02,
+	TNETV107X_PIN_LCD_PD22_2,
+	TNETV107X_PIN_GPIO03,
+	TNETV107X_PIN_LCD_PD23_2,
+	TNETV107X_PIN_GPIO04,
+	TNETV107X_PIN_LCD_PD16_1,
+	TNETV107X_PIN_USB0_RXERR,
+	TNETV107X_PIN_GPIO05,
+	TNETV107X_PIN_LCD_PD17_1,
+	TNETV107X_PIN_TDM_CLK_IN_1,
+	TNETV107X_PIN_GPIO06,
+	TNETV107X_PIN_LCD_PD18,
+	TNETV107X_PIN_24M_CLK_OUT_2,
+	TNETV107X_PIN_GPIO07,
+	TNETV107X_PIN_LCD_PD19_1,
+	TNETV107X_PIN_USB1_RXERR,
+	TNETV107X_PIN_ETH_PLL_CLK,
+	TNETV107X_PIN_MDIO,
+	TNETV107X_PIN_MDC,
+	TNETV107X_PIN_AIC_MUTE_STAT_N,
+	TNETV107X_PIN_TDM0_CLK,
+	TNETV107X_PIN_AIC_HNS_EN_N,
+	TNETV107X_PIN_TDM0_FS,
+	TNETV107X_PIN_AIC_HDS_EN_STAT_N,
+	TNETV107X_PIN_TDM0_TX,
+	TNETV107X_PIN_AIC_HNF_EN_STAT_N,
+	TNETV107X_PIN_TDM0_RX,
+};
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/nand_defs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/nand_defs.h
new file mode 100644
index 000000000..b298fba90
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-tnetv107x/nand_defs.h
@@ -0,0 +1,23 @@
+/*
+ * TNETV107X: NAND definitions
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE	TNETV107X_ASYNC_EMIF_CNTRL_BASE
+
+#define	MASK_CLE		0x4000
+#define	MASK_ALE		0x2000
+
+#define NAND_READ_START		0x00
+#define NAND_READ_END		0x30
+#define NAND_STATUS		0x70
+
+extern void davinci_nand_init(struct nand_chip *nand);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/clock.h
new file mode 100644
index 000000000..1b2fdb792
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/clock.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK
+#define __ASM_ARCH_CLOCK
+
+struct prcmu {
+	unsigned int armclkfix_mgt;
+	unsigned int armclk_mgt;
+	unsigned int svammdspclk_mgt;
+	unsigned int siammdspclk_mgt;
+	unsigned int reserved;
+	unsigned int sgaclk_mgt;
+	unsigned int uartclk_mgt;
+	unsigned int msp02clk_mgt;
+	unsigned int i2cclk_mgt;
+	unsigned int sdmmcclk_mgt;
+	unsigned int slimclk_mgt;
+	unsigned int per1clk_mgt;
+	unsigned int per2clk_mgt;
+	unsigned int per3clk_mgt;
+	unsigned int per5clk_mgt;
+	unsigned int per6clk_mgt;
+	unsigned int per7clk_mgt;
+	unsigned int lcdclk_mgt;
+	unsigned int reserved1;
+	unsigned int bmlclk_mgt;
+	unsigned int hsitxclk_mgt;
+	unsigned int hsirxclk_mgt;
+	unsigned int hdmiclk_mgt;
+	unsigned int apeatclk_mgt;
+	unsigned int apetraceclk_mgt;
+	unsigned int mcdeclk_mgt;
+	unsigned int ipi2cclk_mgt;
+	unsigned int dsialtclk_mgt;
+	unsigned int spare2clk_mgt;
+	unsigned int dmaclk_mgt;
+	unsigned int b2r2clk_mgt;
+	unsigned int tvclk_mgt;
+	unsigned int unused[82];
+	unsigned int tcr;
+	unsigned int unused1[23];
+	unsigned int ape_softrst;
+};
+
+extern void u8500_clock_enable(int periph, int kern, int cluster);
+
+void db8500_clocks_init(void);
+
+#endif /* __ASM_ARCH_CLOCK */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_gpio.h
new file mode 100644
index 000000000..7c85a8917
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Structures and registers for GPIO access in the Nomadik SoC
+ *
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot.
+ *
+ * Ported to U-boot by:
+ * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ * Copyright (C) 2008 STMicroelectronics
+ *     Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
+ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DB8500_GPIO_H__
+#define __DB8500_GPIO_H__
+
+/* Alternate functions: function C is set in hw by setting both A and B */
+enum db8500_gpio_alt {
+	DB8500_GPIO_ALT_GPIO = 0,
+	DB8500_GPIO_ALT_A = 1,
+	DB8500_GPIO_ALT_B = 2,
+	DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B)
+};
+
+enum db8500_gpio_pull {
+	DB8500_GPIO_PULL_NONE,
+	DB8500_GPIO_PULL_UP,
+	DB8500_GPIO_PULL_DOWN
+};
+
+void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull);
+void db8500_gpio_make_input(unsigned gpio);
+int db8500_gpio_get_input(unsigned gpio);
+void db8500_gpio_make_output(unsigned gpio, int val);
+void db8500_gpio_set_output(unsigned gpio, int val);
+
+#endif /* __DB8500_GPIO_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_pincfg.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_pincfg.h
new file mode 100644
index 000000000..64957016c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/db8500_pincfg.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot. Ported 2010 to U-boot by:
+ * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ *
+ *
+ * Based on arch/arm/mach-pxa/include/mach/mfp.h:
+ *   Copyright (C) 2007 Marvell International Ltd.
+ *   eric miao <eric.miao@marvell.com>
+ */
+
+#ifndef __DB8500_PINCFG_H
+#define __DB8500_PINCFG_H
+
+#include "db8500_gpio.h"
+
+/*
+ * U-boot info:
+ * SLPM (sleep mode) config will be ignored by U-boot but it is still
+ * possible to configure it in order to keep cut-n-paste compability
+ * with Linux kernel config.
+ *
+ * pin configurations are represented by 32-bit integers:
+ *
+ *	bit  0.. 8 - Pin Number (512 Pins Maximum)
+ *	bit  9..10 - Alternate Function Selection
+ *	bit 11..12 - Pull up/down state
+ *	bit     13 - Sleep mode behaviour (not used in U-boot)
+ *	bit     14 - Direction
+ *	bit     15 - Value (if output)
+ *	bit 16..18 - SLPM pull up/down state (not used in U-boot)
+ *	bit 19..20 - SLPM direction (not used in U-boot)
+ *	bit 21..22 - SLPM Value (if output) (not used in U-boot)
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * PIN_CFG_DEFAULT - default config (0):
+ *		     pull up/down = disabled
+ *		     sleep mode = input/wakeup
+ *		     direction = input
+ *		     value = low
+ *		     SLPM direction = same as normal
+ *		     SLPM pull = same as normal
+ *		     SLPM value = same as normal
+ *
+ * PIN_CFG	   - default config with alternate function
+ * PIN_CFG_PULL	   - default config with alternate function and pull up/down
+ */
+
+/* Sleep mode */
+enum db8500_gpio_slpm {
+	DB8500_GPIO_SLPM_INPUT,
+	DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT,
+	DB8500_GPIO_SLPM_NOCHANGE,
+	DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE,
+};
+
+#define PIN_NUM_MASK		0x1ff
+#define PIN_NUM(x)		((x) & PIN_NUM_MASK)
+
+#define PIN_ALT_SHIFT		9
+#define PIN_ALT_MASK		(0x3 << PIN_ALT_SHIFT)
+#define PIN_ALT(x)		(((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
+#define PIN_GPIO		(DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
+#define PIN_ALT_A		(DB8500_GPIO_ALT_A << PIN_ALT_SHIFT)
+#define PIN_ALT_B		(DB8500_GPIO_ALT_B << PIN_ALT_SHIFT)
+#define PIN_ALT_C		(DB8500_GPIO_ALT_C << PIN_ALT_SHIFT)
+
+#define PIN_PULL_SHIFT		11
+#define PIN_PULL_MASK		(0x3 << PIN_PULL_SHIFT)
+#define PIN_PULL(x)		(((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
+#define PIN_PULL_NONE		(DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT)
+#define PIN_PULL_UP		(DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT)
+#define PIN_PULL_DOWN		(DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
+
+#define PIN_SLPM_SHIFT		13
+#define PIN_SLPM_MASK		(0x1 << PIN_SLPM_SHIFT)
+#define PIN_SLPM(x)		(((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
+#define PIN_SLPM_MAKE_INPUT	(DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
+#define PIN_SLPM_NOCHANGE	(DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
+/* These two replace the above in DB8500v2+ */
+#define PIN_SLPM_WAKEUP_ENABLE \
+	(DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
+#define PIN_SLPM_WAKEUP_DISABLE \
+	(DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
+
+#define PIN_DIR_SHIFT		14
+#define PIN_DIR_MASK		(0x1 << PIN_DIR_SHIFT)
+#define PIN_DIR(x)		(((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
+#define PIN_DIR_INPUT		(0 << PIN_DIR_SHIFT)
+#define PIN_DIR_OUTPUT		(1 << PIN_DIR_SHIFT)
+
+#define PIN_VAL_SHIFT		15
+#define PIN_VAL_MASK		(0x1 << PIN_VAL_SHIFT)
+#define PIN_VAL(x)		(((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
+#define PIN_VAL_LOW		(0 << PIN_VAL_SHIFT)
+#define PIN_VAL_HIGH		(1 << PIN_VAL_SHIFT)
+
+#define PIN_SLPM_PULL_SHIFT	16
+#define PIN_SLPM_PULL_MASK	(0x7 << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL(x)	\
+	(((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_NONE	\
+	((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_UP	\
+	((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_DOWN	\
+	((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
+
+#define PIN_SLPM_DIR_SHIFT	19
+#define PIN_SLPM_DIR_MASK	(0x3 << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR(x)		\
+	(((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_INPUT	((1 + 0) << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_OUTPUT	((1 + 1) << PIN_SLPM_DIR_SHIFT)
+
+#define PIN_SLPM_VAL_SHIFT	21
+#define PIN_SLPM_VAL_MASK	(0x3 << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL(x)		\
+	(((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_LOW	((1 + 0) << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_HIGH	((1 + 1) << PIN_SLPM_VAL_SHIFT)
+
+/* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
+#define PIN_INPUT_PULLDOWN	(PIN_DIR_INPUT | PIN_PULL_DOWN)
+#define PIN_INPUT_PULLUP	(PIN_DIR_INPUT | PIN_PULL_UP)
+#define PIN_INPUT_NOPULL	(PIN_DIR_INPUT | PIN_PULL_NONE)
+#define PIN_OUTPUT_LOW		(PIN_DIR_OUTPUT | PIN_VAL_LOW)
+#define PIN_OUTPUT_HIGH		(PIN_DIR_OUTPUT | PIN_VAL_HIGH)
+
+#define PIN_SLPM_INPUT_PULLDOWN	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
+#define PIN_SLPM_INPUT_PULLUP	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
+#define PIN_SLPM_INPUT_NOPULL	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
+#define PIN_SLPM_OUTPUT_LOW	(PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
+#define PIN_SLPM_OUTPUT_HIGH	(PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
+
+#define PIN_CFG_DEFAULT		(0)
+
+#define PIN_CFG(num, alt)		\
+	(PIN_CFG_DEFAULT |\
+	 (PIN_NUM(num) | PIN_##alt))
+
+#define PIN_CFG_INPUT(num, alt, pull)		\
+	(PIN_CFG_DEFAULT |\
+	 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
+
+#define PIN_CFG_OUTPUT(num, alt, val)		\
+	(PIN_CFG_DEFAULT |\
+	 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
+
+#define PIN_CFG_PULL(num, alt, pull)	\
+	((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
+	 (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
+
+/**
+ * db8500_gpio_config_pins - configure several pins at once
+ * @cfgs: array of pin configurations
+ * @num: number of elments in the array
+ *
+ * Configures several GPIO pins.
+ */
+void db8500_gpio_config_pins(unsigned long *cfgs, size_t num);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/gpio.h
new file mode 100644
index 000000000..afa5942c9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/gpio.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _UX500_GPIO_h
+#define _UX500_GPIO_h
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/u8500.h>
+
+#define GPIO_TOTAL_PINS                 268
+
+#define GPIO_PINS_PER_BLOCK	32
+#define GPIO_BLOCKS_COUNT       (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
+#define GPIO_BLOCK(pin)		(((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
+
+
+struct gpio_register {
+	u32 gpio_dat;	/* data register : 0x000 */
+	u32 gpio_dats;	/* data Set register : 0x004 */
+	u32 gpio_datc;	/* data Clear register : 0x008 */
+	u32 gpio_pdis;	/* Pull disable register : 0x00C */
+	u32 gpio_dir;	/* data direction register : 0x010 */
+	u32 gpio_dirs;	/* data dir Set register : 0x014 */
+	u32 gpio_dirc;	/* data dir Clear register : 0x018 */
+	u32 gpio_slpm;	/* Sleep mode register : 0x01C */
+	u32 gpio_afsa;	/* AltFun A Select reg : 0x020 */
+	u32 gpio_afsb;	/* AltFun B Select reg : 0x024 */
+	u32 gpio_lowemi;/* low EMI Select reg : 0x028 */
+	u32 reserved_1[(0x040 - 0x02C) >> 2];	/*0x028-0x3C Reserved*/
+	u32 gpio_rimsc;	/* rising edge intr set/clear : 0x040 */
+	u32 gpio_fimsc;	/* falling edge intr set/clear register : 0x044 */
+	u32 gpio_mis;	/* masked interrupt status register : 0x048 */
+	u32 gpio_ic;	/* Interrupt Clear register : 0x04C */
+	u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register : 0x050 */
+	u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register : 0x054 */
+	u32 gpio_wks;	/* Wakeup Status register : 0x058 */
+};
+
+/* Error values returned by functions */
+enum gpio_error {
+	GPIO_OK = 0,
+	GPIO_UNSUPPORTED_HW = -2,
+	GPIO_UNSUPPORTED_FEATURE = -3,
+	GPIO_INVALID_PARAMETER = -4,
+	GPIO_REQUEST_NOT_APPLICABLE = -5,
+	GPIO_REQUEST_PENDING = -6,
+	GPIO_NOT_CONFIGURED = -7,
+	GPIO_INTERNAL_ERROR = -8,
+	GPIO_INTERNAL_EVENT = 1,
+	GPIO_REMAINING_EVENT = 2,
+	GPIO_NO_MORE_PENDING_EVENT = 3,
+	GPIO_INVALID_CLIENT = -25,
+	GPIO_INVALID_PIN = -26,
+	GPIO_PIN_BUSY = -27,
+	GPIO_PIN_NOT_ALLOCATED = -28,
+	GPIO_WRONG_CLIENT = -29,
+	GPIO_UNSUPPORTED_ALTFUNC = -30,
+};
+
+/*GPIO DEVICE ID */
+enum gpio_device_id {
+	GPIO_DEVICE_ID_0,
+	GPIO_DEVICE_ID_1,
+	GPIO_DEVICE_ID_2,
+	GPIO_DEVICE_ID_3,
+	GPIO_DEVICE_ID_INVALID
+};
+
+/*
+ * Alternate Function:
+ *  refered in altfun_table to pointout particular altfun to be enabled
+ *  when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
+ */
+enum gpio_alt_function {
+	GPIO_ALT_UART_0_MODEM,
+	GPIO_ALT_UART_0_NO_MODEM,
+	GPIO_ALT_UART_1,
+	GPIO_ALT_UART_2,
+	GPIO_ALT_I2C_0,
+	GPIO_ALT_I2C_1,
+	GPIO_ALT_I2C_2,
+	GPIO_ALT_I2C_3,
+	GPIO_ALT_MSP_0,
+	GPIO_ALT_MSP_1,
+	GPIO_ALT_MSP_2,
+	GPIO_ALT_MSP_3,
+	GPIO_ALT_MSP_4,
+	GPIO_ALT_MSP_5,
+	GPIO_ALT_SSP_0,
+	GPIO_ALT_SSP_1,
+	GPIO_ALT_MM_CARD0,
+	GPIO_ALT_SD_CARD0,
+	GPIO_ALT_DMA_0,
+	GPIO_ALT_DMA_1,
+	GPIO_ALT_HSI0,
+	GPIO_ALT_CCIR656_INPUT,
+	GPIO_ALT_CCIR656_OUTPUT,
+	GPIO_ALT_LCD_PANEL,
+	GPIO_ALT_MDIF,
+	GPIO_ALT_SDRAM,
+	GPIO_ALT_HAMAC_AUDIO_DBG,
+	GPIO_ALT_HAMAC_VIDEO_DBG,
+	GPIO_ALT_CLOCK_RESET,
+	GPIO_ALT_TSP,
+	GPIO_ALT_IRDA,
+	GPIO_ALT_USB_MINIMUM,
+	GPIO_ALT_USB_I2C,
+	GPIO_ALT_OWM,
+	GPIO_ALT_PWL,
+	GPIO_ALT_FSMC,
+	GPIO_ALT_COMP_FLASH,
+	GPIO_ALT_SRAM_NOR_FLASH,
+	GPIO_ALT_FSMC_ADDLINE_0_TO_15,
+	GPIO_ALT_SCROLL_KEY,
+	GPIO_ALT_MSHC,
+	GPIO_ALT_HPI,
+	GPIO_ALT_USB_OTG,
+	GPIO_ALT_SDIO,
+	GPIO_ALT_HSMMC,
+	GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
+	GPIO_ALT_HSI1,
+	GPIO_ALT_NOR,
+	GPIO_ALT_NAND,
+	GPIO_ALT_KEYPAD,
+	GPIO_ALT_VPIP,
+	GPIO_ALT_CAM,
+	GPIO_ALT_CCP1,
+	GPIO_ALT_EMMC,
+	GPIO_ALT_POP_EMMC,
+	GPIO_ALT_FUNMAX		/* Add new alt func before this */
+};
+
+/* Defines pin assignment(Software mode or Alternate mode) */
+enum gpio_mode {
+	GPIO_MODE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_MODE_SOFTWARE,	/* Pin connected to GPIO (SW controlled) */
+	GPIO_ALTF_A,		/* Pin connected to altfunc 1 (HW periph 1) */
+	GPIO_ALTF_B,		/* Pin connected to altfunc 2 (HW periph 2) */
+	GPIO_ALTF_C,		/* Pin connected to altfunc 3 (HW periph 3) */
+	GPIO_ALTF_FIND,		/* Pin connected to altfunc 3 (HW periph 3) */
+	GPIO_ALTF_DISABLE	/* Pin connected to altfunc 3 (HW periph 3) */
+};
+
+/* Defines GPIO pin direction */
+enum gpio_direction {
+	GPIO_DIR_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_DIR_INPUT,		/* GPIO set as input */
+	GPIO_DIR_OUTPUT		/* GPIO set as output */
+};
+
+/* Interrupt trigger mode */
+enum gpio_trig {
+	GPIO_TRIG_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_TRIG_DISABLE,	/* Trigger no IT */
+	GPIO_TRIG_RISING_EDGE,	/* Trigger an IT on rising edge */
+	GPIO_TRIG_FALLING_EDGE,	/* Trigger an IT on falling edge */
+	GPIO_TRIG_BOTH_EDGES,	/* Trigger an IT on rising and falling edge */
+	GPIO_TRIG_HIGH_LEVEL,	/* Trigger an IT on high level */
+	GPIO_TRIG_LOW_LEVEL	/* Trigger an IT on low level */
+};
+
+/* Configuration parameters for one GPIO pin.*/
+struct gpio_config {
+	enum gpio_mode mode;
+	enum gpio_direction direction;
+	enum gpio_trig trig;
+	char *dev_name;		/* Who owns the gpio pin */
+};
+
+/* GPIO pin data*/
+enum gpio_data {
+	GPIO_DATA_LOW,
+	GPIO_DATA_HIGH
+};
+
+/* GPIO behaviour in sleep mode */
+enum gpio_sleep_mode {
+	GPIO_SLEEP_MODE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT,	/* GPIO is an input with pull
+						   up/down enabled when in sleep
+						   mode. */
+	GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO	/* GPIO pin is controlled by
+						   GPIO IP. So mode, direction
+						   and data values for GPIO pin
+						   in sleep mode are determined
+						   by configuration set to GPIO
+						   pin before entering to sleep
+						   mode. */
+};
+
+/* GPIO ability to wake the system up from sleep mode.*/
+enum gpio_wake {
+	GPIO_WAKE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_WAKE_DISABLE,	/* No wake of system from sleep mode. */
+	GPIO_WAKE_LOW_LEVEL,	/* Wake the system up on a LOW level. */
+	GPIO_WAKE_HIGH_LEVEL,	/* Wake the system up on a HIGH level. */
+	GPIO_WAKE_RISING_EDGE,	/* Wake the system up on a RISING edge. */
+	GPIO_WAKE_FALLING_EDGE,	/* Wake the system up on a FALLING edge. */
+	GPIO_WAKE_BOTH_EDGES	/* Wake the system up on both RISE and FALL. */
+};
+
+/* Configuration parameters for one GPIO pin in sleep mode.*/
+struct gpio_sleep_config {
+	enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */
+	enum gpio_wake wake;		/* GPIO ability to wake up system. */
+};
+
+extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config);
+extern int gpio_resetpinconfig(int pin_id, char *dev_name);
+extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name);
+extern int gpio_readpin(int pin_id, enum gpio_data *value);
+extern int gpio_altfuncenable(enum gpio_alt_function altfunc,
+				      char *dev_name);
+extern int gpio_altfuncdisable(enum gpio_alt_function altfunc,
+				       char *dev_name);
+
+struct gpio_altfun_data {
+	u16 altfun;
+	u16 start;
+	u16 end;
+	u16 cont;
+	u8 type;
+};
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/hardware.h
new file mode 100644
index 000000000..e6a899dac
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/hardware.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* Peripheral clusters */
+
+#define U8500_PER3_BASE		0x80000000
+#define U8500_PER2_BASE		0x80110000
+#define U8500_PER1_BASE		0x80120000
+#define U8500_PER4_BASE		0x80150000
+
+#define U8500_PER6_BASE		0xa03c0000
+#define U8500_PER7_BASE		0xa03d0000
+#define U8500_PER5_BASE		0xa03e0000
+
+/* GPIO */
+
+#define U8500_GPIO0_BASE	(U8500_PER1_BASE + 0xE000)
+#define U8500_GPIO1_BASE	(U8500_PER1_BASE + 0xE000 + 0x80)
+
+#define U8500_GPIO2_BASE	(U8500_PER3_BASE + 0xE000)
+#define U8500_GPIO3_BASE	(U8500_PER3_BASE + 0xE000 + 0x80)
+#define U8500_GPIO4_BASE	(U8500_PER3_BASE + 0xE000 + 0x100)
+#define U8500_GPIO5_BASE	(U8500_PER3_BASE + 0xE000 + 0x180)
+
+#define U8500_GPIO6_BASE	(U8500_PER2_BASE + 0xE000)
+#define U8500_GPIO7_BASE	(U8500_PER2_BASE + 0xE000 + 0x80)
+
+#define U8500_GPIO8_BASE	(U8500_PER5_BASE + 0x1E000)
+
+/* Per7 */
+#define U8500_CLKRST7_BASE	(U8500_PER7_BASE + 0xf000)
+
+/* Per6 */
+#define U8500_MTU0_BASE_V1	(U8500_PER6_BASE + 0x6000)
+#define U8500_MTU1_BASE_V1	(U8500_PER6_BASE + 0x7000)
+#define U8500_CLKRST6_BASE	(U8500_PER6_BASE + 0xf000)
+
+/* Per5 */
+#define U8500_CLKRST5_BASE	(U8500_PER5_BASE + 0x1f000)
+
+/* Per4 */
+#define U8500_PRCMU_BASE	(U8500_PER4_BASE + 0x07000)
+#define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
+
+/* Per3 */
+#define U8500_UART2_BASE	(U8500_PER3_BASE + 0x7000)
+#define U8500_CLKRST3_BASE	(U8500_PER3_BASE + 0xf000)
+
+/* Per2 */
+#define U8500_CLKRST2_BASE	(U8500_PER2_BASE + 0xf000)
+
+/* Per1 */
+#define U8500_UART0_BASE	(U8500_PER1_BASE + 0x0000)
+#define U8500_UART1_BASE	(U8500_PER1_BASE + 0x1000)
+#define U8500_CLKRST1_BASE	(U8500_PER1_BASE + 0xf000)
+
+/* Last page of Boot ROM */
+#define U8500_BOOTROM_BASE      0x90000000
+#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4)
+#define U8500_ASIC_ID_LOC_V2    (U8500_BOOTROM_BASE + 0x1DBF4)
+
+/* AB8500 specifics */
+
+/* address bank */
+#define AB8500_REGU_CTRL2	0x0004
+#define AB8500_MISC		0x0010
+
+/* registers */
+#define AB8500_REGU_VRF1VAUX3_REGU_REG	0x040A
+#define AB8500_REGU_VRF1VAUX3_SEL_REG	0x0421
+#define AB8500_REV_REG			0x1080
+
+#define AB8500_GPIO_SEL2_REG	0x1001
+#define AB8500_GPIO_DIR2_REG	0x1011
+#define AB8500_GPIO_DIR4_REG	0x1013
+#define AB8500_GPIO_SEL4_REG	0x1003
+#define AB8500_GPIO_OUT2_REG	0x1021
+#define AB8500_GPIO_OUT4_REG	0x1023
+
+#define LDO_VAUX3_ENABLE_MASK	0x3
+#define LDO_VAUX3_ENABLE_VAL	0x1
+#define LDO_VAUX3_SEL_MASK	0xf
+#define LDO_VAUX3_SEL_2V9	0xd
+#define LDO_VAUX3_V2_SEL_MASK	0x7
+#define LDO_VAUX3_V2_SEL_2V91	0x7
+
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/prcmu.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/prcmu.h
new file mode 100644
index 000000000..e7f045007
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/prcmu.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson SA
+ *
+ * Copied from the Linux version:
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __MACH_PRCMU_FW_V1_H
+#define __MACH_PRCMU_FW_V1_H
+
+#define AP_EXECUTE	2
+#define I2CREAD		1
+#define I2C_WR_OK	1
+#define I2C_RD_OK	2
+#define I2CWRITE	0
+
+#define PRCMU_BASE			U8500_PRCMU_BASE
+#define PRCMU_BASE_TCDM			U8500_PRCMU_TCDM_BASE
+#define PRCM_UARTCLK_MGT_REG		(PRCMU_BASE + 0x018)
+#define PRCM_MSPCLK_MGT_REG		(PRCMU_BASE + 0x01C)
+#define PRCM_I2CCLK_MGT_REG		(PRCMU_BASE + 0x020)
+#define PRCM_SDMMCCLK_MGT_REG		(PRCMU_BASE + 0x024)
+#define PRCM_PER1CLK_MGT_REG		(PRCMU_BASE + 0x02C)
+#define PRCM_PER2CLK_MGT_REG		(PRCMU_BASE + 0x030)
+#define PRCM_PER3CLK_MGT_REG		(PRCMU_BASE + 0x034)
+#define PRCM_PER5CLK_MGT_REG		(PRCMU_BASE + 0x038)
+#define PRCM_PER6CLK_MGT_REG		(PRCMU_BASE + 0x03C)
+#define PRCM_PER7CLK_MGT_REG		(PRCMU_BASE + 0x040)
+#define PRCM_MBOX_CPU_VAL		(PRCMU_BASE + 0x0FC)
+#define PRCM_MBOX_CPU_SET		(PRCMU_BASE + 0x100)
+
+#define PRCM_ARM_IT1_CLEAR		(PRCMU_BASE + 0x48C)
+#define PRCM_ARM_IT1_VAL		(PRCMU_BASE + 0x494)
+#define PRCM_TCR			(PRCMU_BASE + 0x1C8)
+#define PRCM_REQ_MB5			(PRCMU_BASE_TCDM + 0xE44)
+#define PRCM_ACK_MB5			(PRCMU_BASE_TCDM + 0xDF4)
+#define PRCM_XP70_CUR_PWR_STATE		(PRCMU_BASE_TCDM + 0xFFC)
+/* Mailbox 5 Requests */
+#define PRCM_REQ_MB5_I2COPTYPE_REG	(PRCM_REQ_MB5 + 0x0)
+#define PRCM_REQ_MB5_BIT_FIELDS		(PRCM_REQ_MB5 + 0x1)
+#define PRCM_REQ_MB5_I2CSLAVE		(PRCM_REQ_MB5 + 0x2)
+#define PRCM_REQ_MB5_I2CVAL		(PRCM_REQ_MB5 + 0x3)
+
+/* Mailbox 5 ACKs */
+#define PRCM_ACK_MB5_STATUS	(PRCM_ACK_MB5 + 0x1)
+#define PRCM_ACK_MB5_SLAVE	(PRCM_ACK_MB5 + 0x2)
+#define PRCM_ACK_MB5_VAL	(PRCM_ACK_MB5 + 0x3)
+
+#define LOW_POWER_WAKEUP	1
+#define EXE_WAKEUP		0
+
+#define REQ_MB5			5
+
+#define ab8500_read	prcmu_i2c_read
+#define ab8500_write	prcmu_i2c_write
+
+int prcmu_i2c_read(u8 reg, u16 slave);
+int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
+
+void u8500_prcmu_enable(u32 *reg);
+void db8500_prcmu_init(void);
+
+#endif /* __MACH_PRCMU_FW_V1_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/sys_proto.h
new file mode 100644
index 000000000..03a3cd35b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/sys_proto.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+void gpio_init(void);
+int u8500_mmc_power_init(void);
+
+#endif  /* _SYS_PROTO_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/u8500.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/u8500.h
new file mode 100644
index 000000000..16ad081bc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-u8500/u8500.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __U8500_H
+#define __U8500_H
+
+/*
+ * base register values for U8500
+ */
+#define CFG_PRCMU_BASE		0x80157000	/* Power, reset and clock
+						   Management Unit */
+#define CFG_SDRAMC_BASE		0x903CF000	/* SDRAMC cnf registers */
+#define CFG_FSMC_BASE		0x80000000	/* FSMC Controller */
+
+/*
+ * U8500 GPIO register base for 9 banks
+ */
+#define U8500_GPIO_0_BASE			0x8012E000
+#define U8500_GPIO_1_BASE			0x8012E080
+#define U8500_GPIO_2_BASE			0x8000E000
+#define U8500_GPIO_3_BASE			0x8000E080
+#define U8500_GPIO_4_BASE			0x8000E100
+#define U8500_GPIO_5_BASE			0x8000E180
+#define U8500_GPIO_6_BASE			0x8011E000
+#define U8500_GPIO_7_BASE			0x8011E080
+#define U8500_GPIO_8_BASE			0xA03FE000
+
+#endif	/* __U8500_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/clock.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/clock.h
new file mode 100644
index 000000000..535adadd7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/clock.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_BUS_CLK,
+	MXC_IPG_CLK,
+	MXC_UART_CLK,
+	MXC_ESDHC_CLK,
+	MXC_FEC_CLK,
+	MXC_I2C_CLK,
+};
+
+void enable_ocotp_clk(unsigned char enable);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/crm_regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/crm_regs.h
new file mode 100644
index 000000000..e17c7d1f7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
+#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* Clock Controller Module (CCM) */
+struct ccm_reg {
+	u32 ccr;
+	u32 csr;
+	u32 ccsr;
+	u32 cacrr;
+	u32 cscmr1;
+	u32 cscdr1;
+	u32 cscdr2;
+	u32 cscdr3;
+	u32 cscmr2;
+	u32 cscdr4;
+	u32 ctor;
+	u32 clpcr;
+	u32 cisr;
+	u32 cimr;
+	u32 ccosr;
+	u32 cgpr;
+	u32 ccgr0;
+	u32 ccgr1;
+	u32 ccgr2;
+	u32 ccgr3;
+	u32 ccgr4;
+	u32 ccgr5;
+	u32 ccgr6;
+	u32 ccgr7;
+	u32 ccgr8;
+	u32 ccgr9;
+	u32 ccgr10;
+	u32 ccgr11;
+	u32 cmeor0;
+	u32 cmeor1;
+	u32 cmeor2;
+	u32 cmeor3;
+	u32 cmeor4;
+	u32 cmeor5;
+	u32 cppdsr;
+	u32 ccowr;
+	u32 ccpgr0;
+	u32 ccpgr1;
+	u32 ccpgr2;
+	u32 ccpgr3;
+};
+
+/* Analog components control digital interface (ANADIG) */
+struct anadig_reg {
+	u32 reserved_0x000[4];
+	u32 pll3_ctrl;
+	u32 reserved_0x014[3];
+	u32 pll7_ctrl;
+	u32 reserved_0x024[3];
+	u32 pll2_ctrl;
+	u32 reserved_0x034[3];
+	u32 pll2_ss;
+	u32 reserved_0x044[3];
+	u32 pll2_num;
+	u32 reserved_0x054[3];
+	u32 pll2_denom;
+	u32 reserved_0x064[3];
+	u32 pll4_ctrl;
+	u32 reserved_0x074[3];
+	u32 pll4_num;
+	u32 reserved_0x084[3];
+	u32 pll4_denom;
+	u32 reserved_0x094[3];
+	u32 pll6_ctrl;
+	u32 reserved_0x0A4[3];
+	u32 pll6_num;
+	u32 reserved_0x0B4[3];
+	u32 pll6_denom;
+	u32 reserved_0x0C4[7];
+	u32 pll5_ctrl;
+	u32 reserved_0x0E4[3];
+	u32 pll3_pfd;
+	u32 reserved_0x0F4[3];
+	u32 pll2_pfd;
+	u32 reserved_0x104[3];
+	u32 reg_1p1;
+	u32 reserved_0x114[3];
+	u32 reg_3p0;
+	u32 reserved_0x124[3];
+	u32 reg_2p5;
+	u32 reserved_0x134[7];
+	u32 ana_misc0;
+	u32 reserved_0x154[3];
+	u32 ana_misc1;
+	u32 reserved_0x164[63];
+	u32 anadig_digprog;
+	u32 reserved_0x264[3];
+	u32 pll1_ctrl;
+	u32 reserved_0x274[3];
+	u32 pll1_ss;
+	u32 reserved_0x284[3];
+	u32 pll1_num;
+	u32 reserved_0x294[3];
+	u32 pll1_denom;
+	u32 reserved_0x2A4[3];
+	u32 pll1_pdf;
+	u32 reserved_0x2B4[3];
+	u32 pll_lock;
+};
+#endif
+
+#define CCM_CCR_FIRC_EN				(1 << 16)
+#define CCM_CCR_OSCNT_MASK			0xff
+#define CCM_CCR_OSCNT(v)			((v) & 0xff)
+
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET	19
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK		(0x7 << 19)
+#define CCM_CCSR_PLL2_PFD_CLK_SEL(v)		(((v) & 0x7) << 19)
+
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET	16
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK		(0x7 << 16)
+#define CCM_CCSR_PLL1_PFD_CLK_SEL(v)		(((v) & 0x7) << 16)
+
+#define CCM_CCSR_PLL2_PFD4_EN			(1 << 15)
+#define CCM_CCSR_PLL2_PFD3_EN			(1 << 14)
+#define CCM_CCSR_PLL2_PFD2_EN			(1 << 13)
+#define CCM_CCSR_PLL2_PFD1_EN			(1 << 12)
+#define CCM_CCSR_PLL1_PFD4_EN			(1 << 11)
+#define CCM_CCSR_PLL1_PFD3_EN			(1 << 10)
+#define CCM_CCSR_PLL1_PFD2_EN			(1 << 9)
+#define CCM_CCSR_PLL1_PFD1_EN			(1 << 8)
+
+#define CCM_CCSR_DDRC_CLK_SEL(v)		((v) << 6)
+#define CCM_CCSR_FAST_CLK_SEL(v)		((v) << 5)
+
+#define CCM_CCSR_SYS_CLK_SEL_OFFSET		0
+#define CCM_CCSR_SYS_CLK_SEL_MASK		0x7
+#define CCM_CCSR_SYS_CLK_SEL(v)			((v) & 0x7)
+
+#define CCM_CACRR_IPG_CLK_DIV_OFFSET		11
+#define CCM_CACRR_IPG_CLK_DIV_MASK		(0x3 << 11)
+#define CCM_CACRR_IPG_CLK_DIV(v)		(((v) & 0x3) << 11)
+#define CCM_CACRR_BUS_CLK_DIV_OFFSET		3
+#define CCM_CACRR_BUS_CLK_DIV_MASK		(0x7 << 3)
+#define CCM_CACRR_BUS_CLK_DIV(v)		(((v) & 0x7) << 3)
+#define CCM_CACRR_ARM_CLK_DIV_OFFSET		0
+#define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
+#define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)
+
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET	18
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK		(0x3 << 18)
+#define CCM_CSCMR1_ESDHC1_CLK_SEL(v)		(((v) & 0x3) << 18)
+
+#define CCM_CSCDR1_RMII_CLK_EN			(1 << 24)
+
+#define CCM_CSCDR2_ESDHC1_EN			(1 << 29)
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET	20
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
+#define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)
+
+#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET		4
+#define CCM_CSCMR2_RMII_CLK_SEL_MASK		(0x3 << 4)
+#define CCM_CSCMR2_RMII_CLK_SEL(v)		(((v) & 0x3) << 4)
+
+#define CCM_REG_CTRL_MASK			0xffffffff
+#define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
+#define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
+#define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
+#define CCM_CCGR2_IOMUXC_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR2_PORTA_CTRL_MASK		(0x3 << 18)
+#define CCM_CCGR2_PORTB_CTRL_MASK		(0x3 << 20)
+#define CCM_CCGR2_PORTC_CTRL_MASK		(0x3 << 22)
+#define CCM_CCGR2_PORTD_CTRL_MASK		(0x3 << 24)
+#define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
+#define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
+#define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
+#define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
+#define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
+#define CCM_CCGR4_I2C0_CTRL_MASK		(0x3 << 12)
+#define CCM_CCGR6_OCOTP_CTRL_MASK		(0x3 << 10)
+#define CCM_CCGR6_DDRMC_CTRL_MASK		(0x3 << 28)
+#define CCM_CCGR7_SDHC1_CTRL_MASK		(0x3 << 4)
+#define CCM_CCGR9_FEC0_CTRL_MASK		0x3
+#define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
+
+#define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
+#define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)
+#define ANADIG_PLL5_CTRL_POWERDOWN              (1 << 12)
+#define ANADIG_PLL5_CTRL_DIV_SELECT		1
+#define ANADIG_PLL2_CTRL_ENABLE			(1 << 13)
+#define ANADIG_PLL2_CTRL_POWERDOWN		(1 << 12)
+#define ANADIG_PLL2_CTRL_DIV_SELECT		1
+#define ANADIG_PLL1_CTRL_ENABLE			(1 << 13)
+#define ANADIG_PLL1_CTRL_POWERDOWN		(1 << 12)
+#define ANADIG_PLL1_CTRL_DIV_SELECT		1
+
+#define FASE_CLK_FREQ		24000000
+#define SLOW_CLK_FREQ		32000
+#define PLL1_PFD1_FREQ		500000000
+#define PLL1_PFD2_FREQ		452000000
+#define PLL1_PFD3_FREQ		396000000
+#define PLL1_PFD4_FREQ		528000000
+#define PLL1_MAIN_FREQ		528000000
+#define PLL2_PFD1_FREQ		500000000
+#define PLL2_PFD2_FREQ		396000000
+#define PLL2_PFD3_FREQ		339000000
+#define PLL2_PFD4_FREQ		413000000
+#define PLL2_MAIN_FREQ		528000000
+#define PLL3_MAIN_FREQ		480000000
+#define PLL3_PFD3_FREQ		298000000
+#define PLL5_MAIN_FREQ		500000000
+
+#define ENET_EXTERNAL_CLK	50000000
+#define AUDIO_EXTERNAL_CLK	24576000
+
+#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h
new file mode 100644
index 000000000..c2f976184
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -0,0 +1,408 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define IRAM_BASE_ADDR		0x3F000000	/* internal ram */
+#define IRAM_SIZE		0x00080000	/* 512 KB */
+
+#define AIPS0_BASE_ADDR		0x40000000
+#define AIPS1_BASE_ADDR		0x40080000
+
+/* AIPS 0 */
+#define MSCM_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00001000)
+#define MSCM_IR_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00001800)
+#define CA5SCU_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00002000)
+#define CA5_INTD_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00003000)
+#define CA5_L2C_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00006000)
+#define NIC0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00008000)
+#define NIC1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00009000)
+#define NIC2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000A000)
+#define NIC3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000B000)
+#define NIC4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000C000)
+#define NIC5_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000D000)
+#define NIC6_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000E000)
+#define NIC7_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000F000)
+#define AHBTZASC_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00010000)
+#define TZASC_SYS0_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00011000)
+#define TZASC_SYS1_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00012000)
+#define TZASC_GFX_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00013000)
+#define TZASC_DDR0_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00014000)
+#define TZASC_DDR1_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00015000)
+#define CSU_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00017000)
+#define DMA0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00018000)
+#define DMA0_TCD_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00019000)
+#define SEMA4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0001D000)
+#define FB_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0001E000)
+#define DMA_MUX0_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00024000)
+#define UART0_BASE		(AIPS0_BASE_ADDR + 0x00027000)
+#define UART1_BASE		(AIPS0_BASE_ADDR + 0x00028000)
+#define UART2_BASE		(AIPS0_BASE_ADDR + 0x00029000)
+#define UART3_BASE		(AIPS0_BASE_ADDR + 0x0002A000)
+#define SPI0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0002C000)
+#define SPI1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0002D000)
+#define SAI0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0002F000)
+#define SAI1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00030000)
+#define SAI2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00031000)
+#define SAI3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00032000)
+#define CRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00033000)
+#define PDB_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00036000)
+#define PIT_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00037000)
+#define FTM0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00038000)
+#define FTM1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00039000)
+#define ADC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0003B000)
+#define TCON0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0003D000)
+#define WDOG1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0003E000)
+#define LPTMR_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00040000)
+#define RLE_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00042000)
+#define MLB_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00043000)
+#define QSPI0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00044000)
+#define IOMUXC_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00048000)
+#define ANADIG_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00050000)
+#define SCSCM_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
+#define ASRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00060000)
+#define SPDIF_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00061000)
+#define ESAI_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00062000)
+#define ESAI_FIFO_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00063000)
+#define WDOG_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00065000)
+#define I2C0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00066000)
+#define WKUP_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006A000)
+#define CCM_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006B000)
+#define GPC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006C000)
+#define VREG_DIG_BASE_ADDR	(AIPS0_BASE_ADDR + 0x0006D000)
+#define SRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006E000)
+#define CMU_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006F000)
+
+/* AIPS 1 */
+#define OCOTP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00025000)
+#define DDR_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0002E000)
+#define ESDHC0_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00031000)
+#define ESDHC1_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00032000)
+#define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
+#define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
+
+/* MUX mode and PAD ctrl are in one register */
+#define CONFIG_IOMUX_SHARE_CONF_REG
+
+#define FEC_QUIRK_ENET_MAC
+#define I2C_QUIRK_REG
+
+/* MSCM interrupt rounter */
+#define MSCM_IRSPRC_CP0_EN				1
+#define MSCM_IRSPRC_NUM					112
+
+/* DDRMC */
+#define DDRMC_PHY_DQ_TIMING				0x00002613
+#define DDRMC_PHY_DQS_TIMING				0x00002615
+#define DDRMC_PHY_CTRL					0x01210080
+#define DDRMC_PHY_MASTER_CTRL				0x0001012a
+#define DDRMC_PHY_SLAVE_CTRL				0x00012020
+
+#define DDRMC_PHY50_DDR3_MODE				(1 << 12)
+#define DDRMC_PHY50_EN_SW_HALF_CYCLE			(1 << 8)
+
+#define DDRMC_CR00_DRAM_CLASS_DDR3			(0x6 << 8)
+#define DDRMC_CR00_DRAM_CLASS_LPDDR2			(0x5 << 8)
+#define DDRMC_CR00_START				1
+#define DDRMC_CR02_DRAM_TINIT(v)			((v) & 0xffffff)
+#define DDRMC_CR10_TRST_PWRON(v)			(v)
+#define DDRMC_CR11_CKE_INACTIVE(v)			(v)
+#define DDRMC_CR12_WRLAT(v)				(((v) & 0x1f) << 8)
+#define DDRMC_CR12_CASLAT_LIN(v)			((v) & 0x3f)
+#define DDRMC_CR13_TRC(v)				(((v) & 0xff) << 24)
+#define DDRMC_CR13_TRRD(v)				(((v) & 0xff) << 16)
+#define DDRMC_CR13_TCCD(v)				(((v) & 0x1f) << 8)
+#define DDRMC_CR13_TBST_INT_INTERVAL(v)			((v) & 0x7)
+#define DDRMC_CR14_TFAW(v)				(((v) & 0x3f) << 24)
+#define DDRMC_CR14_TRP(v)				(((v) & 0x1f) << 16)
+#define DDRMC_CR14_TWTR(v)				(((v) & 0xf) << 8)
+#define DDRMC_CR14_TRAS_MIN(v)				((v) & 0xff)
+#define DDRMC_CR16_TMRD(v)				(((v) & 0x1f) << 24)
+#define DDRMC_CR16_TRTP(v)				(((v) & 0xf) << 16)
+#define DDRMC_CR17_TRAS_MAX(v)				(((v) & 0x1ffff) << 8)
+#define DDRMC_CR17_TMOD(v)				((v) & 0xff)
+#define DDRMC_CR18_TCKESR(v)				(((v) & 0x1f) << 8)
+#define DDRMC_CR18_TCKE(v)				((v) & 0x7)
+#define DDRMC_CR20_AP_EN				(1 << 24)
+#define DDRMC_CR21_TRCD_INT(v)				(((v) & 0xff) << 16)
+#define DDRMC_CR21_TRAS_LOCKOUT				(1 << 8)
+#define DDRMC_CR21_CCMAP_EN				1
+#define DDRMC_CR22_TDAL(v)				(((v) & 0x3f) << 16)
+#define DDRMC_CR23_BSTLEN(v)				(((v) & 0x7) << 24)
+#define DDRMC_CR23_TDLL(v)				((v) & 0xff)
+#define DDRMC_CR24_TRP_AB(v)				((v) & 0x1f)
+#define DDRMC_CR25_TREF_EN				(1 << 16)
+#define DDRMC_CR26_TREF(v)				(((v) & 0xffff) << 16)
+#define DDRMC_CR26_TRFC(v)				((v) & 0x3ff)
+#define DDRMC_CR28_TREF_INT(v)				((v) & 0xffff)
+#define DDRMC_CR29_TPDEX(v)				((v) & 0xffff)
+#define DDRMC_CR30_TXPDLL(v)				((v) & 0xffff)
+#define DDRMC_CR31_TXSNR(v)				(((v) & 0xffff) << 16)
+#define DDRMC_CR31_TXSR(v)				((v) & 0xffff)
+#define DDRMC_CR33_EN_QK_SREF				(1 << 16)
+#define DDRMC_CR34_CKSRX(v)				(((v) & 0xf) << 16)
+#define DDRMC_CR34_CKSRE(v)				(((v) & 0xf) << 8)
+#define DDRMC_CR38_FREQ_CHG_EN				(1 << 8)
+#define DDRMC_CR39_PHY_INI_COM(v)			(((v) & 0xffff) << 16)
+#define DDRMC_CR39_PHY_INI_STA(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR39_FRQ_CH_DLLOFF(v)			((v) & 0x3)
+#define DDRMC_CR41_PHY_INI_STRT_INI_DIS			1
+#define DDRMC_CR48_MR1_DA_0(v)				(((v) & 0xffff) << 16)
+#define DDRMC_CR48_MR0_DA_0(v)				((v) & 0xffff)
+#define DDRMC_CR66_ZQCL(v)				(((v) & 0xfff) << 16)
+#define DDRMC_CR66_ZQINIT(v)				((v) & 0xfff)
+#define DDRMC_CR67_ZQCS(v)				((v) & 0xfff)
+#define DDRMC_CR69_ZQ_ON_SREF_EX(v)			(((v) & 0xf) << 8)
+#define DDRMC_CR70_REF_PER_ZQ(v)			(v)
+#define DDRMC_CR72_ZQCS_ROTATE				(1 << 24)
+#define DDRMC_CR73_APREBIT(v)				(((v) & 0xf) << 24)
+#define DDRMC_CR73_COL_DIFF(v)				(((v) & 0x7) << 16)
+#define DDRMC_CR73_ROW_DIFF(v)				(((v) & 0x3) << 8)
+#define DDRMC_CR74_BANKSPLT_EN				(1 << 24)
+#define DDRMC_CR74_ADDR_CMP_EN				(1 << 16)
+#define DDRMC_CR74_CMD_AGE_CNT(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR74_AGE_CNT(v)				((v) & 0xff)
+#define DDRMC_CR75_RW_PG_EN				(1 << 24)
+#define DDRMC_CR75_RW_EN				(1 << 16)
+#define DDRMC_CR75_PRI_EN				(1 << 8)
+#define DDRMC_CR75_PLEN					1
+#define DDRMC_CR76_NQENT_ACTDIS(v)			(((v) & 0x7) << 24)
+#define DDRMC_CR76_D_RW_G_BKCN(v)			(((v) & 0x3) << 16)
+#define DDRMC_CR76_W2R_SPLT_EN				(1 << 8)
+#define DDRMC_CR76_CS_EN				1
+#define DDRMC_CR77_CS_MAP				(1 << 24)
+#define DDRMC_CR77_DI_RD_INTLEAVE			(1 << 8)
+#define DDRMC_CR77_SWAP_EN				1
+#define DDRMC_CR78_BUR_ON_FLY_BIT(v)			((v) & 0xf)
+#define DDRMC_CR79_CTLUPD_AREF				(1 << 24)
+#define DDRMC_CR82_INT_MASK				0x1fffffff
+#define DDRMC_CR87_ODT_WR_MAPCS0			(1 << 24)
+#define DDRMC_CR87_ODT_RD_MAPCS0			(1 << 16)
+#define DDRMC_CR88_TODTL_CMD(v)				(((v) & 0x1f) << 16)
+#define DDRMC_CR89_AODT_RWSMCS(v)			((v) & 0xf)
+#define DDRMC_CR91_R2W_SMCSDL(v)			(((v) & 0x7) << 16)
+#define DDRMC_CR96_WLMRD(v)				(((v) & 0x3f) << 8)
+#define DDRMC_CR96_WLDQSEN(v)				((v) & 0x3f)
+#define DDRMC_CR105_RDLVL_DL_0(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR110_RDLVL_DL_1(v)			((v) & 0xff)
+#define DDRMC_CR114_RDLVL_GTDL_2(v)			(((v) & 0xffff) << 8)
+#define DDRMC_CR117_AXI0_W_PRI(v)			(((v) & 0x3) << 8)
+#define DDRMC_CR117_AXI0_R_PRI(v)			((v) & 0x3)
+#define DDRMC_CR118_AXI1_W_PRI(v)			(((v) & 0x3) << 24)
+#define DDRMC_CR118_AXI1_R_PRI(v)			(((v) & 0x3) << 16)
+#define DDRMC_CR120_AXI0_PRI1_RPRI(v)			(((v) & 0xf) << 24)
+#define DDRMC_CR120_AXI0_PRI0_RPRI(v)			(((v) & 0xf) << 16)
+#define DDRMC_CR121_AXI0_PRI3_RPRI(v)			(((v) & 0xf) << 8)
+#define DDRMC_CR121_AXI0_PRI2_RPRI(v)			((v) & 0xf)
+#define DDRMC_CR122_AXI1_PRI1_RPRI(v)			(((v) & 0xf) << 24)
+#define DDRMC_CR122_AXI1_PRI0_RPRI(v)			(((v) & 0xf) << 16)
+#define DDRMC_CR122_AXI0_PRIRLX(v)			((v) & 0x3ff)
+#define DDRMC_CR123_AXI1_PRI3_RPRI(v)			(((v) & 0xf) << 8)
+#define DDRMC_CR123_AXI1_PRI2_RPRI(v)			((v) & 0xf)
+#define DDRMC_CR124_AXI1_PRIRLX(v)			((v) & 0x3ff)
+#define DDRMC_CR126_PHY_RDLAT(v)			(((v) & 0x3f) << 8)
+#define DDRMC_CR132_WRLAT_ADJ(v)			(((v) & 0x1f) << 8)
+#define DDRMC_CR132_RDLAT_ADJ(v)			((v) & 0x3f)
+#define DDRMC_CR139_PHY_WRLV_RESPLAT(v)			(((v) & 0xff) << 24)
+#define DDRMC_CR139_PHY_WRLV_LOAD(v)			(((v) & 0xff) << 16)
+#define DDRMC_CR139_PHY_WRLV_DLL(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR139_PHY_WRLV_EN(v)			((v) & 0xff)
+#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v)	(((v) & 0x1f) << 27)
+#define DDRMC_CR154_PAD_ZQ_MODE(v)			(((v) & 0x3) << 21)
+#define DDRMC_CR155_AXI0_AWCACHE			(1 << 10)
+#define DDRMC_CR155_PAD_ODT_BYTE1(v)			((v) & 0x7)
+#define DDRMC_CR158_TWR(v)				((v) & 0x3f)
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32 scr;
+	u32 sbmr1;
+	u32 srsr;
+	u32 secr;
+	u32 gpsr;
+	u32 sicr;
+	u32 simr;
+	u32 sbmr2;
+	u32 gpr0;
+	u32 gpr1;
+	u32 gpr2;
+	u32 gpr3;
+	u32 gpr4;
+	u32 hab0;
+	u32 hab1;
+	u32 hab2;
+	u32 hab3;
+	u32 hab4;
+	u32 hab5;
+	u32 misc0;
+	u32 misc1;
+	u32 misc2;
+	u32 misc3;
+};
+
+/* Periodic Interrupt Timer (PIT) */
+struct pit_reg {
+	u32 mcr;
+	u32 recv0[55];
+	u32 ltmr64h;
+	u32 ltmr64l;
+	u32 recv1[6];
+	u32 ldval0;
+	u32 cval0;
+	u32 tctrl0;
+	u32 tflg0;
+	u32 ldval1;
+	u32 cval1;
+	u32 tctrl1;
+	u32 tflg1;
+	u32 ldval2;
+	u32 cval2;
+	u32 tctrl2;
+	u32 tflg2;
+	u32 ldval3;
+	u32 cval3;
+	u32 tctrl3;
+	u32 tflg3;
+	u32 ldval4;
+	u32 cval4;
+	u32 tctrl4;
+	u32 tflg4;
+	u32 ldval5;
+	u32 cval5;
+	u32 tctrl5;
+	u32 tflg5;
+	u32 ldval6;
+	u32 cval6;
+	u32 tctrl6;
+	u32 tflg6;
+	u32 ldval7;
+	u32 cval7;
+	u32 tctrl7;
+	u32 tflg7;
+};
+
+/* Watchdog Timer (WDOG) */
+struct wdog_regs {
+	u16 wcr;
+	u16 wsr;
+	u16 wrsr;
+	u16 wicr;
+	u16 wmcr;
+};
+
+/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */
+struct ddrmr_regs {
+	u32 cr[162];
+	u32 rsvd[94];
+	u32 phy[53];
+};
+
+/* On-Chip One Time Programmable Controller (OCOTP) */
+struct ocotp_regs {
+	u32 ctrl;
+	u32 ctrl_set;
+	u32 ctrl_clr;
+	u32 ctrl_tog;
+	u32 timing;
+	u32 rsvd0[3];
+	u32 data;
+	u32 rsvd1[3];
+	u32 read_ctrl;
+	u32 rsvd2[3];
+	u32 read_fuse_data;
+	u32 rsvd3[7];
+	u32 scs;
+	u32 scs_set;
+	u32 scs_clr;
+	u32 scs_tog;
+	u32 crc_addr;
+	u32 rsvd4[3];
+	u32 crc_value;
+	u32 rsvd5[3];
+	u32 version;
+	u32 rsvd6[0xdb];
+
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+	} bank[16];
+};
+
+struct fuse_bank0_regs {
+	u32 lock;
+	u32 rsvd0[3];
+	u32 uid_low;
+	u32 rsvd1[3];
+	u32 uid_high;
+	u32 rsvd2[0x17];
+};
+
+struct fuse_bank4_regs {
+	u32 sjc_resp0;
+	u32 rsvd0[3];
+	u32 sjc_resp1;
+	u32 rsvd1[3];
+	u32 mac_addr0;
+	u32 rsvd2[3];
+	u32 mac_addr1;
+	u32 rsvd3[3];
+	u32 mac_addr2;
+	u32 rsvd4[3];
+	u32 mac_addr3;
+	u32 rsvd5[3];
+	u32 gp1;
+	u32 rsvd6[3];
+	u32 gp2;
+	u32 rsvd7[3];
+};
+
+/* UART */
+struct lpuart_fsl {
+	u8 ubdh;
+	u8 ubdl;
+	u8 uc1;
+	u8 uc2;
+	u8 us1;
+	u8 us2;
+	u8 uc3;
+	u8 ud;
+	u8 uma1;
+	u8 uma2;
+	u8 uc4;
+	u8 uc5;
+	u8 ued;
+	u8 umodem;
+	u8 uir;
+	u8 reserved;
+	u8 upfifo;
+	u8 ucfifo;
+	u8 usfifo;
+	u8 utwfifo;
+	u8 utcfifo;
+	u8 urwfifo;
+	u8 urcfifo;
+	u8 rsvd[28];
+};
+
+/* MSCM Interrupt Router */
+struct mscm_ir {
+	u32 ircp0ir;
+	u32 ircp1ir;
+	u32 rsvd1[6];
+	u32 ircpgir;
+	u32 rsvd2[23];
+	u16 irsprc[112];
+	u16 rsvd3[848];
+};
+
+#endif	/* __ASSEMBLER__*/
+
+#endif	/* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h
new file mode 100644
index 000000000..88807d8db
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IOMUX_VF610_H__
+#define __IOMUX_VF610_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define VF610_UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \
+				PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_SDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \
+				PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+				PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
+#define VF610_I2C_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+				PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
+
+enum {
+	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTA6__RMII0_CLKOUT		= IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTB4__UART1_TX		= IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB5__UART1_RX		= IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB10__UART0_TX		= IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB11__UART0_RX		= IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTC1__RMII0_MDIO		= IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC0__RMII0_MDC		= IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC2__RMII0_CRS_DV		= IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC3__RMII0_RD1		= IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC4__RMII0_RD0		= IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC5__RMII0_RXER		= IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC6__RMII0_TD1		= IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC7__RMII0_TD0		= IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC8__RMII0_TXEN		= IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC10__RMII1_MDIO		= IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC9__RMII1_MDC		= IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC11__RMII1_CRS_DV		= IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC12__RMII1_RD1		= IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC13__RMII1_RD0		= IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC14__RMII1_RXER		= IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC15__RMII1_TD1		= IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC16__RMII1_TD0		= IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC17__RMII1_TXEN		= IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTA24__ESDHC1_CLK		= IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTA25__ESDHC1_CMD		= IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTA26__ESDHC1_DAT0		= IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTA27__ESDHC1_DAT1		= IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTA28__ESDHC1_DAT2		= IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTA29__ESDHC1_DAT3		= IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTB14__I2C0_SCL		= IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
+	VF610_PAD_PTB15__I2C0_SDA		= IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
+	VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A13__DDR_A_13		= IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A12__DDR_A_12		= IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A11__DDR_A_11		= IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A10__DDR_A_10		= IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A9__DDR_A_9		= IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A8__DDR_A_8		= IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A7__DDR_A_7		= IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A6__DDR_A_6		= IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A5__DDR_A_5		= IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A4__DDR_A_4		= IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A3__DDR_A_3		= IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A2__DDR_A_2		= IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A1__DDR_A_1		= IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_BA2__DDR_BA_2		= IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_BA1__DDR_BA_1		= IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_BA0__DDR_BA_0		= IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_CAS__DDR_CAS_B		= IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_CKE__DDR_CKE_0		= IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_CLK__DDR_CLK_0		= IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_CS__DDR_CS_B_0		= IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D15__DDR_D_15		= IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D14__DDR_D_14		= IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D13__DDR_D_13		= IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D12__DDR_D_12		= IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D11__DDR_D_11		= IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D10__DDR_D_10		= IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D9__DDR_D_9		= IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D8__DDR_D_8		= IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D7__DDR_D_7		= IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D6__DDR_D_6		= IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D5__DDR_D_5		= IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D4__DDR_D_4		= IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D3__DDR_D_3		= IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D2__DDR_D_2		= IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D1__DDR_D_1		= IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D0__DDR_D_0		= IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_DQM1__DDR_DQM_1		= IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_DQM0__DDR_DQM_0		= IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_DQS1__DDR_DQS_1		= IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_DQS0__DDR_DQS_0		= IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_RAS__DDR_RAS_B		= IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_WE__DDR_WE_B		= IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_ODT1__DDR_ODT_0		= IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_ODT0__DDR_ODT_1		= IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+};
+
+#endif	/* __IOMUX_VF610_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/clk.h
new file mode 100644
index 000000000..250c5bc07
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/clk.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ZYNQ_CLK_H_
+#define _ZYNQ_CLK_H_
+
+enum zynq_clk {
+	armpll_clk, ddrpll_clk, iopll_clk,
+	cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
+	ddr2x_clk, ddr3x_clk, dci_clk,
+	lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
+	fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
+	sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
+	usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
+	sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
+	can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
+	uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
+	smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
+
+void zynq_clk_early_init(void);
+int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate);
+unsigned long zynq_clk_get_rate(enum zynq_clk clk);
+const char *zynq_clk_get_name(enum zynq_clk clk);
+unsigned long get_uart_clk(int dev_id);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/gpio.h
new file mode 100644
index 000000000..2dbba756d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/gpio.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ZYNQ_GPIO_H
+#define _ZYNQ_GPIO_H
+
+inline int gpio_get_value(unsigned gpio)
+{
+	return 0;
+}
+
+inline int gpio_set_value(unsigned gpio, int val)
+{
+	return 0;
+}
+
+inline int gpio_request(unsigned gpio, const char *label)
+{
+	return 0;
+}
+
+#endif /* _ZYNQ_GPIO_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/hardware.h
new file mode 100644
index 000000000..39184da40
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/hardware.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define ZYNQ_SERIAL_BASEADDR0		0xE0000000
+#define ZYNQ_SERIAL_BASEADDR1		0xE0001000
+#define ZYNQ_SYS_CTRL_BASEADDR		0xF8000000
+#define ZYNQ_DEV_CFG_APB_BASEADDR	0xF8007000
+#define ZYNQ_SCU_BASEADDR		0xF8F00000
+#define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
+#define ZYNQ_GEM_BASEADDR0		0xE000B000
+#define ZYNQ_GEM_BASEADDR1		0xE000C000
+#define ZYNQ_SDHCI_BASEADDR0		0xE0100000
+#define ZYNQ_SDHCI_BASEADDR1		0xE0101000
+#define ZYNQ_I2C_BASEADDR0		0xE0004000
+#define ZYNQ_I2C_BASEADDR1		0xE0005000
+#define ZYNQ_SPI_BASEADDR0		0xE0006000
+#define ZYNQ_SPI_BASEADDR1		0xE0007000
+#define ZYNQ_DDRC_BASEADDR		0xF8006000
+
+/* Bootmode setting values */
+#define ZYNQ_BM_MASK		0xF
+#define ZYNQ_BM_NOR		0x2
+#define ZYNQ_BM_SD		0x5
+#define ZYNQ_BM_JTAG		0x0
+
+/* Reflect slcr offsets */
+struct slcr_regs {
+	u32 scl; /* 0x0 */
+	u32 slcr_lock; /* 0x4 */
+	u32 slcr_unlock; /* 0x8 */
+	u32 reserved0_1[61];
+	u32 arm_pll_ctrl; /* 0x100 */
+	u32 ddr_pll_ctrl; /* 0x104 */
+	u32 io_pll_ctrl; /* 0x108 */
+	u32 reserved0_2[5];
+	u32 arm_clk_ctrl; /* 0x120 */
+	u32 ddr_clk_ctrl; /* 0x124 */
+	u32 dci_clk_ctrl; /* 0x128 */
+	u32 aper_clk_ctrl; /* 0x12c */
+	u32 reserved0_3[2];
+	u32 gem0_rclk_ctrl; /* 0x138 */
+	u32 gem1_rclk_ctrl; /* 0x13c */
+	u32 gem0_clk_ctrl; /* 0x140 */
+	u32 gem1_clk_ctrl; /* 0x144 */
+	u32 smc_clk_ctrl; /* 0x148 */
+	u32 lqspi_clk_ctrl; /* 0x14c */
+	u32 sdio_clk_ctrl; /* 0x150 */
+	u32 uart_clk_ctrl; /* 0x154 */
+	u32 spi_clk_ctrl; /* 0x158 */
+	u32 can_clk_ctrl; /* 0x15c */
+	u32 can_mioclk_ctrl; /* 0x160 */
+	u32 dbg_clk_ctrl; /* 0x164 */
+	u32 pcap_clk_ctrl; /* 0x168 */
+	u32 reserved0_4[1];
+	u32 fpga0_clk_ctrl; /* 0x170 */
+	u32 reserved0_5[3];
+	u32 fpga1_clk_ctrl; /* 0x180 */
+	u32 reserved0_6[3];
+	u32 fpga2_clk_ctrl; /* 0x190 */
+	u32 reserved0_7[3];
+	u32 fpga3_clk_ctrl; /* 0x1a0 */
+	u32 reserved0_8[8];
+	u32 clk_621_true; /* 0x1c4 */
+	u32 reserved1[14];
+	u32 pss_rst_ctrl; /* 0x200 */
+	u32 reserved2[15];
+	u32 fpga_rst_ctrl; /* 0x240 */
+	u32 reserved3[5];
+	u32 reboot_status; /* 0x258 */
+	u32 boot_mode; /* 0x25c */
+	u32 reserved4[116];
+	u32 trust_zone; /* 0x430 */ /* FIXME */
+	u32 reserved5_1[63];
+	u32 pss_idcode; /* 0x530 */
+	u32 reserved5_2[51];
+	u32 ddr_urgent; /* 0x600 */
+	u32 reserved6[6];
+	u32 ddr_urgent_sel; /* 0x61c */
+	u32 reserved7[56];
+	u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+	u32 reserved8[74];
+	u32 lvl_shftr_en; /* 0x900 */
+	u32 reserved9[3];
+	u32 ocm_cfg; /* 0x910 */
+};
+
+#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
+
+struct devcfg_regs {
+	u32 ctrl; /* 0x0 */
+	u32 lock; /* 0x4 */
+	u32 cfg; /* 0x8 */
+	u32 int_sts; /* 0xc */
+	u32 int_mask; /* 0x10 */
+	u32 status; /* 0x14 */
+	u32 dma_src_addr; /* 0x18 */
+	u32 dma_dst_addr; /* 0x1c */
+	u32 dma_src_len; /* 0x20 */
+	u32 dma_dst_len; /* 0x24 */
+	u32 rom_shadow; /* 0x28 */
+	u32 reserved1[2];
+	u32 unlock; /* 0x34 */
+	u32 reserved2[18];
+	u32 mctrl; /* 0x80 */
+	u32 reserved3;
+	u32 write_count; /* 0x88 */
+	u32 read_count; /* 0x8c */
+};
+
+#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
+
+struct scu_regs {
+	u32 reserved1[16];
+	u32 filter_start; /* 0x40 */
+	u32 filter_end; /* 0x44 */
+};
+
+#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
+
+struct ddrc_regs {
+	u32 ddrc_ctrl; /* 0x0 */
+	u32 reserved[60];
+	u32 ecc_scrub; /* 0xF4 */
+};
+#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/spl.h
new file mode 100644
index 000000000..5789d28bb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/spl.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+extern void ps7_init(void);
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_RAM		1
+#define BOOT_DEVICE_SPI		2
+#define BOOT_DEVICE_MMC1	3
+#define BOOT_DEVICE_MMC2	4
+#define BOOT_DEVICE_MMC2_2	5
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/sys_proto.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/sys_proto.h
new file mode 100644
index 000000000..a68e1b3d2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+extern void zynq_slcr_lock(void);
+extern void zynq_slcr_unlock(void);
+extern void zynq_slcr_cpu_reset(void);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
+extern void zynq_slcr_devcfg_disable(void);
+extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_boot_mode(void);
+extern u32 zynq_slcr_get_idcode(void);
+extern void zynq_ddrc_init(void);
+
+/* Driver extern functions */
+extern int zynq_sdhci_init(u32 regbase);
+extern int zynq_sdhci_of_init(const void *blob);
+
+#endif /* _SYS_PROTO_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/armv7.h b/qemu/roms/u-boot/arch/arm/include/asm/armv7.h
new file mode 100644
index 000000000..395444ee4
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/armv7.h
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef ARMV7_H
+#define ARMV7_H
+
+/* Cortex-A9 revisions */
+#define MIDR_CORTEX_A9_R0P1	0x410FC091
+#define MIDR_CORTEX_A9_R1P2	0x411FC092
+#define MIDR_CORTEX_A9_R1P3	0x411FC093
+#define MIDR_CORTEX_A9_R2P10	0x412FC09A
+
+/* Cortex-A15 revisions */
+#define MIDR_CORTEX_A15_R0P0	0x410FC0F0
+#define MIDR_CORTEX_A15_R2P2	0x412FC0F2
+
+/* Cortex-A7 revisions */
+#define MIDR_CORTEX_A7_R0P0	0x410FC070
+
+#define MIDR_PRIMARY_PART_MASK	0xFF0FFFF0
+
+/* ID_PFR1 feature fields */
+#define CPUID_ARM_SEC_SHIFT		4
+#define CPUID_ARM_SEC_MASK		(0xF << CPUID_ARM_SEC_SHIFT)
+#define CPUID_ARM_VIRT_SHIFT		12
+#define CPUID_ARM_VIRT_MASK		(0xF << CPUID_ARM_VIRT_SHIFT)
+#define CPUID_ARM_GENTIMER_SHIFT	16
+#define CPUID_ARM_GENTIMER_MASK		(0xF << CPUID_ARM_GENTIMER_SHIFT)
+
+/* valid bits in CBAR register / PERIPHBASE value */
+#define CBAR_MASK			0xFFFF8000
+
+/* CCSIDR */
+#define CCSIDR_LINE_SIZE_OFFSET		0
+#define CCSIDR_LINE_SIZE_MASK		0x7
+#define CCSIDR_ASSOCIATIVITY_OFFSET	3
+#define CCSIDR_ASSOCIATIVITY_MASK	(0x3FF << 3)
+#define CCSIDR_NUM_SETS_OFFSET		13
+#define CCSIDR_NUM_SETS_MASK		(0x7FFF << 13)
+
+/*
+ * Values for InD field in CSSELR
+ * Selects the type of cache
+ */
+#define ARMV7_CSSELR_IND_DATA_UNIFIED	0
+#define ARMV7_CSSELR_IND_INSTRUCTION	1
+
+/* Values for Ctype fields in CLIDR */
+#define ARMV7_CLIDR_CTYPE_NO_CACHE		0
+#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY	1
+#define ARMV7_CLIDR_CTYPE_DATA_ONLY		2
+#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA	3
+#define ARMV7_CLIDR_CTYPE_UNIFIED		4
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
+/*
+ * CP15 Barrier instructions
+ * Please note that we have separate barrier instructions in ARMv7
+ * However, we use the CP15 based instructtions because we use
+ * -march=armv5 in U-Boot
+ */
+#define CP15ISB	asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
+#define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
+#define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
+
+void v7_outer_cache_enable(void);
+void v7_outer_cache_disable(void);
+void v7_outer_cache_flush_all(void);
+void v7_outer_cache_inval_all(void);
+void v7_outer_cache_flush_range(u32 start, u32 end);
+void v7_outer_cache_inval_range(u32 start, u32 end);
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+
+int armv7_switch_nonsec(void);
+int armv7_switch_hyp(void);
+
+/* defined in assembly file */
+unsigned int _nonsec_init(void);
+void _smp_pen(void);
+void _switch_to_hyp(void);
+#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/armv8/mmu.h b/qemu/roms/u-boot/arch/arm/include/asm/armv8/mmu.h
new file mode 100644
index 000000000..1193e76a8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/armv8/mmu.h
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_MMU_H_
+#define _ASM_ARMV8_MMU_H_
+
+#ifdef __ASSEMBLY__
+#define _AC(X, Y)	X
+#else
+#define _AC(X, Y)	(X##Y)
+#endif
+
+#define UL(x)		_AC(x, UL)
+
+/***************************************************************/
+/*
+ * The following definitions are related each other, shoud be
+ * calculated specifically.
+ */
+#define VA_BITS			(42)	/* 42 bits virtual address */
+
+/* PAGE_SHIFT determines the page size */
+#undef  PAGE_SIZE
+#define PAGE_SHIFT		16
+#define PAGE_SIZE		(1 << PAGE_SHIFT)
+#define PAGE_MASK		(~(PAGE_SIZE-1))
+
+/*
+ * section address mask and size definitions.
+ */
+#define SECTION_SHIFT		29
+#define SECTION_SIZE		(UL(1) << SECTION_SHIFT)
+#define SECTION_MASK		(~(SECTION_SIZE-1))
+/***************************************************************/
+
+/*
+ * Memory types
+ */
+#define MT_DEVICE_NGNRNE	0
+#define MT_DEVICE_NGNRE		1
+#define MT_DEVICE_GRE		2
+#define MT_NORMAL_NC		3
+#define MT_NORMAL		4
+
+#define MEMORY_ATTRIBUTES	((0x00 << (MT_DEVICE_NGNRNE*8)) |	\
+				(0x04 << (MT_DEVICE_NGNRE*8)) |		\
+				(0x0c << (MT_DEVICE_GRE*8)) |		\
+				(0x44 << (MT_NORMAL_NC*8)) |		\
+				(UL(0xff) << (MT_NORMAL*8)))
+
+/*
+ * Hardware page table definitions.
+ *
+ * Level 2 descriptor (PMD).
+ */
+#define PMD_TYPE_MASK		(3 << 0)
+#define PMD_TYPE_FAULT		(0 << 0)
+#define PMD_TYPE_TABLE		(3 << 0)
+#define PMD_TYPE_SECT		(1 << 0)
+
+/*
+ * Section
+ */
+#define PMD_SECT_S		(3 << 8)
+#define PMD_SECT_AF		(1 << 10)
+#define PMD_SECT_NG		(1 << 11)
+#define PMD_SECT_PXN		(UL(1) << 53)
+#define PMD_SECT_UXN		(UL(1) << 54)
+
+/*
+ * AttrIndx[2:0]
+ */
+#define PMD_ATTRINDX(t)		((t) << 2)
+#define PMD_ATTRINDX_MASK	(7 << 2)
+
+/*
+ * TCR flags.
+ */
+#define TCR_T0SZ(x)		((64 - (x)) << 0)
+#define TCR_IRGN_NC		(0 << 8)
+#define TCR_IRGN_WBWA		(1 << 8)
+#define TCR_IRGN_WT		(2 << 8)
+#define TCR_IRGN_WBNWA		(3 << 8)
+#define TCR_IRGN_MASK		(3 << 8)
+#define TCR_ORGN_NC		(0 << 10)
+#define TCR_ORGN_WBWA		(1 << 10)
+#define TCR_ORGN_WT		(2 << 10)
+#define TCR_ORGN_WBNWA		(3 << 10)
+#define TCR_ORGN_MASK		(3 << 10)
+#define TCR_SHARED_NON		(0 << 12)
+#define TCR_SHARED_OUTER	(1 << 12)
+#define TCR_SHARED_INNER	(2 << 12)
+#define TCR_TG0_4K		(0 << 14)
+#define TCR_TG0_64K		(1 << 14)
+#define TCR_TG0_16K		(2 << 14)
+#define TCR_EL1_IPS_BITS	(UL(3) << 32)	/* 42 bits physical address */
+#define TCR_EL2_IPS_BITS	(3 << 16)	/* 42 bits physical address */
+#define TCR_EL3_IPS_BITS	(3 << 16)	/* 42 bits physical address */
+
+/* PTWs cacheable, inner/outer WBWA and non-shareable */
+#define TCR_FLAGS		(TCR_TG0_64K |		\
+				TCR_SHARED_NON |	\
+				TCR_ORGN_WBWA |		\
+				TCR_IRGN_WBWA |		\
+				TCR_T0SZ(VA_BITS))
+
+#endif /* _ASM_ARMV8_MMU_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/assembler.h b/qemu/roms/u-boot/arch/arm/include/asm/assembler.h
new file mode 100644
index 000000000..5e4789b14
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/assembler.h
@@ -0,0 +1,60 @@
+/*
+ *  arch/arm/include/asm/assembler.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This file contains arm architecture specific defines
+ *  for the different processors.
+ *
+ *  Do not include any C declarations in this file - it is included by
+ *  assembler source.
+ */
+
+/*
+ * Endian independent macros for shifting bytes within registers.
+ */
+#ifndef __ARMEB__
+#define pull		lsr
+#define push		lsl
+#define get_byte_0	lsl #0
+#define get_byte_1	lsr #8
+#define get_byte_2	lsr #16
+#define get_byte_3	lsr #24
+#define put_byte_0	lsl #0
+#define put_byte_1	lsl #8
+#define put_byte_2	lsl #16
+#define put_byte_3	lsl #24
+#else
+#define pull		lsl
+#define push		lsr
+#define get_byte_0	lsr #24
+#define get_byte_1	lsr #16
+#define get_byte_2	lsr #8
+#define get_byte_3      lsl #0
+#define put_byte_0	lsl #24
+#define put_byte_1	lsl #16
+#define put_byte_2	lsl #8
+#define put_byte_3      lsl #0
+#endif
+
+/*
+ * Data preload for architectures that support it
+ */
+#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \
+	defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
+	defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \
+	defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \
+	defined(__ARM_ARCH_7R__)
+#define PLD(code...)	code
+#else
+#define PLD(code...)
+#endif
+
+/*
+ * Cache alligned
+ */
+#define CALGN(code...) code
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/atomic.h b/qemu/roms/u-boot/arch/arm/include/asm/atomic.h
new file mode 100644
index 000000000..1b22eeb5f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/atomic.h
@@ -0,0 +1,111 @@
+/*
+ *  linux/include/asm-arm/atomic.h
+ *
+ *  Copyright (c) 1996 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   13-04-1997	RMK	Made functions atomic!
+ *   07-12-1997	RMK	Upgraded for v2.1.
+ *   26-08-1998	PJB	Added #ifdef __KERNEL__
+ */
+#ifndef __ASM_ARM_ATOMIC_H
+#define __ASM_ARM_ATOMIC_H
+
+#ifdef CONFIG_SMP
+#error SMP not supported
+#endif
+
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i)	{ (i) }
+
+#ifdef __KERNEL__
+#include <asm/proc/system.h>
+
+#define atomic_read(v)	((v)->counter)
+#define atomic_set(v,i)	(((v)->counter) = (i))
+
+static inline void atomic_add(int i, volatile atomic_t *v)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	v->counter += i;
+	local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, volatile atomic_t *v)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	v->counter -= i;
+	local_irq_restore(flags);
+}
+
+static inline void atomic_inc(volatile atomic_t *v)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	v->counter += 1;
+	local_irq_restore(flags);
+}
+
+static inline void atomic_dec(volatile atomic_t *v)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	v->counter -= 1;
+	local_irq_restore(flags);
+}
+
+static inline int atomic_dec_and_test(volatile atomic_t *v)
+{
+	unsigned long flags;
+	int val;
+
+	local_irq_save(flags);
+	val = v->counter;
+	v->counter = val -= 1;
+	local_irq_restore(flags);
+
+	return val == 0;
+}
+
+static inline int atomic_add_negative(int i, volatile atomic_t *v)
+{
+	unsigned long flags;
+	int val;
+
+	local_irq_save(flags);
+	val = v->counter;
+	v->counter = val += i;
+	local_irq_restore(flags);
+
+	return val < 0;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	*addr &= ~mask;
+	local_irq_restore(flags);
+}
+
+/* Atomic operations are already serializing on ARM */
+#define smp_mb__before_atomic_dec()	barrier()
+#define smp_mb__after_atomic_dec()	barrier()
+#define smp_mb__before_atomic_inc()	barrier()
+#define smp_mb__after_atomic_inc()	barrier()
+
+#endif
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/bitops.h b/qemu/roms/u-boot/arch/arm/include/asm/bitops.h
new file mode 100644
index 000000000..879e20e02
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/bitops.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_ARM_BITOPS_H
+#define __ASM_ARM_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/proc/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void * addr);
+
+extern void clear_bit(int nr, volatile void * addr);
+
+extern void change_bit(int nr, volatile void * addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p ^= mask;
+}
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old | mask;
+	return (old & mask) != 0;
+}
+
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+	unsigned long flags;
+	int out;
+
+	local_irq_save(flags);
+	out = __test_and_set_bit(nr, addr);
+	local_irq_restore(flags);
+
+	return out;
+}
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old & ~mask;
+	return (old & mask) != 0;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+	unsigned long flags;
+	int out;
+
+	local_irq_save(flags);
+	out = __test_and_clear_bit(nr, addr);
+	local_irq_restore(flags);
+
+	return out;
+}
+
+extern int test_and_change_bit(int nr, volatile void * addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old ^ mask;
+	return (old & mask) != 0;
+}
+
+extern int find_first_zero_bit(void * addr, unsigned size);
+extern int find_next_zero_bit(void * addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void * addr)
+{
+    return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+static inline int __ilog2(unsigned int x)
+{
+	return generic_fls(x) - 1;
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) { k -= 16; word <<= 16; }
+	if (word & 0x00ff0000) { k -= 8;  word <<= 8;  }
+	if (word & 0x0f000000) { k -= 4;  word <<= 4;  }
+	if (word & 0x30000000) { k -= 2;  word <<= 2;  }
+	if (word & 0x40000000) { k -= 1; }
+	return k;
+}
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr,addr)	test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr)		set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr)	test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr)		test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size)	find_first_zero_bit(addr,size)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ARM_BITOPS_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/bootm.h b/qemu/roms/u-boot/arch/arm/include/asm/bootm.h
new file mode 100644
index 000000000..436c35a6d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/bootm.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef ARM_BOOTM_H
+#define ARM_BOOTM_H
+
+extern void udc_disconnect(void);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+		defined(CONFIG_CMDLINE_TAG) || \
+		defined(CONFIG_INITRD_TAG) || \
+		defined(CONFIG_SERIAL_TAG) || \
+		defined(CONFIG_REVISION_TAG)
+# define BOOTM_ENABLE_TAGS		1
+#else
+# define BOOTM_ENABLE_TAGS		0
+#endif
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+# define BOOTM_ENABLE_MEMORY_TAGS	1
+#else
+# define BOOTM_ENABLE_MEMORY_TAGS	0
+#endif
+
+#ifdef CONFIG_CMDLINE_TAG
+ #define BOOTM_ENABLE_CMDLINE_TAG	1
+#else
+ #define BOOTM_ENABLE_CMDLINE_TAG	0
+#endif
+
+#ifdef CONFIG_INITRD_TAG
+ #define BOOTM_ENABLE_INITRD_TAG	1
+#else
+ #define BOOTM_ENABLE_INITRD_TAG	0
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+ #define BOOTM_ENABLE_SERIAL_TAG	1
+void get_board_serial(struct tag_serialnr *serialnr);
+#else
+ #define BOOTM_ENABLE_SERIAL_TAG	0
+static inline void get_board_serial(struct tag_serialnr *serialnr)
+{
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+ #define BOOTM_ENABLE_REVISION_TAG	1
+u32 get_board_rev(void);
+#else
+ #define BOOTM_ENABLE_REVISION_TAG	0
+static inline u32 get_board_rev(void)
+{
+	return 0;
+}
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/byteorder.h b/qemu/roms/u-boot/arch/arm/include/asm/byteorder.h
new file mode 100644
index 000000000..20cce7657
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/byteorder.h
@@ -0,0 +1,32 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+#ifndef __ASM_ARM_BYTEORDER_H
+#define __ASM_ARM_BYTEORDER_H
+
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#if defined(__ARMEB__) || defined(__AARCH64EB__)
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/cache.h b/qemu/roms/u-boot/arch/arm/include/asm/cache.h
new file mode 100644
index 000000000..ddebbc8fc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/cache.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+#include <asm/system.h>
+
+#ifndef CONFIG_ARM64
+
+/*
+ * Invalidate L2 Cache using co-proc instruction
+ */
+static inline void invalidate_l2_cache(void)
+{
+	unsigned int val=0;
+
+	asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
+		: : "r" (val) : "cc");
+	isb();
+}
+
+void l2_cache_enable(void);
+void l2_cache_disable(void);
+void set_section_dcache(int section, enum dcache_option option);
+
+void dram_bank_mmu_setup(int bank);
+
+#endif
+
+/*
+ * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
+ * use that value for aligning DMA buffers unless the board config has specified
+ * an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	64
+#endif
+
+#endif /* _ASM_CACHE_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/config.h b/qemu/roms/u-boot/arch/arm/include/asm/config.h
new file mode 100644
index 000000000..2a20a770b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/config.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#ifdef CONFIG_ARM64
+#define CONFIG_PHYS_64BIT
+#define CONFIG_STATIC_RELA
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/davinci_rtc.h b/qemu/roms/u-boot/arch/arm/include/asm/davinci_rtc.h
new file mode 100644
index 000000000..575b59088
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/davinci_rtc.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * -------------------------------------------------------------------------
+ *
+ *  linux/include/asm-arm/arch-davinci/hardware.h
+ *
+ *  Copyright (C) 2006 Texas Instruments.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef __ASM_DAVINCI_RTC_H
+#define __ASM_DAVINCI_RTC_H
+
+struct davinci_rtc {
+	unsigned int	second;
+	unsigned int	minutes;
+	unsigned int	hours;
+	unsigned int	day;
+	unsigned int	month; /* 0x10 */
+	unsigned int	year;
+	unsigned int	dotw;
+	unsigned int	resv1;
+	unsigned int	alarmsecond; /* 0x20 */
+	unsigned int	alarmminute;
+	unsigned int	alarmhour;
+	unsigned int	alarmday;
+	unsigned int	alarmmonth; /* 0x30 */
+	unsigned int	alarmyear;
+	unsigned int	resv2[2];
+	unsigned int	ctrl; /* 0x40 */
+	unsigned int	status;
+	unsigned int	irq;
+	unsigned int	complsb;
+	unsigned int	compmsb; /* 0x50 */
+	unsigned int	osc;
+	unsigned int	resv3[2];
+	unsigned int	scratch0; /* 0x60 */
+	unsigned int	scratch1;
+	unsigned int	scratch2;
+	unsigned int	kick0r;
+	unsigned int	kick1r; /* 0x70 */
+};
+
+#define RTC_STATE_BUSY	0x01
+#define RTC_STATE_RUN	0x02
+
+#define RTC_KICK0R_WE	0x83e70b13
+#define RTC_KICK1R_WE	0x95a4f1e0
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/dma-mapping.h b/qemu/roms/u-boot/arch/arm/include/asm/dma-mapping.h
new file mode 100644
index 000000000..55a4e266a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/dma-mapping.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARM_DMA_MAPPING_H
+#define __ASM_ARM_DMA_MAPPING_H
+
+enum dma_data_direction {
+	DMA_BIDIRECTIONAL	= 0,
+	DMA_TO_DEVICE		= 1,
+	DMA_FROM_DEVICE		= 2,
+};
+
+static void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+	return (void *)*handle;
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+					   enum dma_data_direction dir)
+{
+	return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+				    unsigned long paddr)
+{
+}
+
+#endif /* __ASM_ARM_DMA_MAPPING_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/ehci-omap.h b/qemu/roms/u-boot/arch/arm/include/asm/ehci-omap.h
new file mode 100644
index 000000000..c7bca0568
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/ehci-omap.h
@@ -0,0 +1,152 @@
+/*
+ * OMAP EHCI port support
+ * Based on LINUX KERNEL
+ * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com*
+ * Author: Govindraj R <govindraj.raja@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2  of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _OMAP_COMMON_EHCI_H_
+#define _OMAP_COMMON_EHCI_H_
+
+enum usbhs_omap_port_mode {
+	OMAP_USBHS_PORT_MODE_UNUSED,
+	OMAP_EHCI_PORT_MODE_PHY,
+	OMAP_EHCI_PORT_MODE_TLL,
+	OMAP_EHCI_PORT_MODE_HSIC,
+};
+
+#ifdef CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
+#define OMAP_HS_USB_PORTS	CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
+#else
+#define OMAP_HS_USB_PORTS	3
+#endif
+
+#define is_ehci_phy_mode(x)	((x) == OMAP_EHCI_PORT_MODE_PHY)
+#define is_ehci_tll_mode(x)	((x) == OMAP_EHCI_PORT_MODE_TLL)
+#define is_ehci_hsic_mode(x)	((x) == OMAP_EHCI_PORT_MODE_HSIC)
+
+/* Values of UHH_REVISION - Note: these are not given in the TRM */
+#define OMAP_USBHS_REV1					0x00000010 /* OMAP3 */
+#define OMAP_USBHS_REV2					0x50700100 /* OMAP4 */
+#define OMAP_USBHS_REV2_1				0x50700101 /* OMAP5 */
+
+/* UHH Register Set */
+#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN		(1 << 2)
+#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN		(1 << 3)
+#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN		(1 << 4)
+#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN		(1 << 5)
+
+#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS		1
+#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS		(1 << 11)
+#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS		(1 << 12)
+#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK		(1 << 31)
+
+#define OMAP_P1_MODE_CLEAR				(3 << 16)
+#define OMAP_P1_MODE_TLL				(1 << 16)
+#define OMAP_P1_MODE_HSIC				(3 << 16)
+#define OMAP_P2_MODE_CLEAR				(3 << 18)
+#define OMAP_P2_MODE_TLL				(1 << 18)
+#define OMAP_P2_MODE_HSIC				(3 << 18)
+#define OMAP_P3_MODE_CLEAR				(3 << 20)
+#define OMAP_P3_MODE_HSIC				(3 << 20)
+
+/* EHCI Register Set */
+#define EHCI_INSNREG04_DISABLE_UNSUSPEND		(1 << 5)
+#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT		31
+#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT		24
+#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT			22
+#define EHCI_INSNREG05_ULPI_REGADD_SHIFT		16
+
+#define OMAP_REV1_TLL_CHANNEL_COUNT			3
+#define OMAP_REV2_TLL_CHANNEL_COUNT			2
+
+/* TLL Register Set */
+#define OMAP_TLL_CHANNEL_CONF(num)			(0x004 * num)
+#define OMAP_TLL_CHANNEL_CONF_DRVVBUS			(1 << 16)
+#define OMAP_TLL_CHANNEL_CONF_CHRGVBUS			(1 << 15)
+#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF		(1 << 11)
+#define OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI	(2 << 1)
+#define OMAP_TLL_CHANNEL_CONF_CHANEN			1
+
+struct omap_usbhs_board_data {
+	enum usbhs_omap_port_mode port_mode[OMAP_HS_USB_PORTS];
+};
+
+struct omap_usbtll {
+	u32 rev;		/* 0x00 */
+	u32 hwinfo;		/* 0x04 */
+	u8 reserved1[0x8];
+	u32 sysc;		/* 0x10 */
+	u32 syss;		/* 0x14 */
+	u32 irqst;		/* 0x18 */
+	u32 irqen;		/* 0x1c */
+	u8 reserved2[0x10];
+	u32 shared_conf;	/* 0x30 */
+	u8 reserved3[0xc];
+	u32 channel_conf;	/* 0x40 */
+};
+
+struct omap_uhh {
+	u32 rev;	/* 0x00 */
+	u32 hwinfo;	/* 0x04 */
+	u8 reserved1[0x8];
+	u32 sysc;	/* 0x10 */
+	u32 syss;	/* 0x14 */
+	u8 reserved2[0x28];
+	u32 hostconfig;	/* 0x40 */
+	u32 debugcsr;	/* 0x44 */
+};
+
+struct omap_ehci {
+	u32 hccapbase;		/* 0x00 */
+	u32 hcsparams;		/* 0x04 */
+	u32 hccparams;		/* 0x08 */
+	u8 reserved1[0x04];
+	u32 usbcmd;		/* 0x10 */
+	u32 usbsts;		/* 0x14 */
+	u32 usbintr;		/* 0x18 */
+	u32 frindex;		/* 0x1c */
+	u32 ctrldssegment;	/* 0x20 */
+	u32 periodiclistbase;	/* 0x24 */
+	u32 asysnclistaddr;	/* 0x28 */
+	u8 reserved2[0x24];
+	u32 configflag;		/* 0x50 */
+	u32 portsc_i;		/* 0x54 */
+	u8 reserved3[0x38];
+	u32 insreg00;		/* 0x90 */
+	u32 insreg01;		/* 0x94 */
+	u32 insreg02;		/* 0x98 */
+	u32 insreg03;		/* 0x9c */
+	u32 insreg04;		/* 0xa0 */
+	u32 insreg05_utmi_ulpi;	/* 0xa4 */
+	u32 insreg06;		/* 0xa8 */
+	u32 insreg07;		/* 0xac */
+	u32 insreg08;		/* 0xb0 */
+};
+
+/*
+ * FIXME: forward declaration of this structs needed because omap got the
+ * ehci implementation backwards. move out ehci_hcd_x from board files
+ */
+struct ehci_hccr;
+struct ehci_hcor;
+
+int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
+		       struct ehci_hccr **hccr, struct ehci_hcor **hcor);
+int omap_ehci_hcd_stop(void);
+
+#endif /* _OMAP_COMMON_EHCI_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/emif.h b/qemu/roms/u-boot/arch/arm/include/asm/emif.h
new file mode 100644
index 000000000..45668ca4d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/emif.h
@@ -0,0 +1,1206 @@
+/*
+ * OMAP44xx EMIF header
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+#include <asm/types.h>
+#include <common.h>
+#include <asm/io.h>
+
+/* Base address */
+#define EMIF1_BASE				0x4c000000
+#define EMIF2_BASE				0x4d000000
+
+#define EMIF_4D					0x4
+#define EMIF_4D5				0x5
+
+/* Registers shifts, masks and values */
+
+/* EMIF_MOD_ID_REV */
+#define EMIF_REG_SCHEME_SHIFT			30
+#define EMIF_REG_SCHEME_MASK			(0x3 << 30)
+#define EMIF_REG_MODULE_ID_SHIFT			16
+#define EMIF_REG_MODULE_ID_MASK			(0xfff << 16)
+#define EMIF_REG_RTL_VERSION_SHIFT			11
+#define EMIF_REG_RTL_VERSION_MASK			(0x1f << 11)
+#define EMIF_REG_MAJOR_REVISION_SHIFT		8
+#define EMIF_REG_MAJOR_REVISION_MASK		(0x7 << 8)
+#define EMIF_REG_MINOR_REVISION_SHIFT		0
+#define EMIF_REG_MINOR_REVISION_MASK		(0x3f << 0)
+
+/* STATUS */
+#define EMIF_REG_BE_SHIFT				31
+#define EMIF_REG_BE_MASK				(1 << 31)
+#define EMIF_REG_DUAL_CLK_MODE_SHIFT		30
+#define EMIF_REG_DUAL_CLK_MODE_MASK			(1 << 30)
+#define EMIF_REG_FAST_INIT_SHIFT			29
+#define EMIF_REG_FAST_INIT_MASK			(1 << 29)
+#define EMIF_REG_PHY_DLL_READY_SHIFT		2
+#define EMIF_REG_PHY_DLL_READY_MASK			(1 << 2)
+
+/* SDRAM_CONFIG */
+#define EMIF_REG_SDRAM_TYPE_SHIFT			29
+#define EMIF_REG_SDRAM_TYPE_MASK			(0x7 << 29)
+#define EMIF_REG_SDRAM_TYPE_DDR1			0
+#define EMIF_REG_SDRAM_TYPE_LPDDR1			1
+#define EMIF_REG_SDRAM_TYPE_DDR2			2
+#define EMIF_REG_SDRAM_TYPE_DDR3			3
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4			4
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2			5
+#define EMIF_REG_IBANK_POS_SHIFT			27
+#define EMIF_REG_IBANK_POS_MASK			(0x3 << 27)
+#define EMIF_REG_DDR_TERM_SHIFT			24
+#define EMIF_REG_DDR_TERM_MASK			(0x7 << 24)
+#define EMIF_REG_DDR2_DDQS_SHIFT			23
+#define EMIF_REG_DDR2_DDQS_MASK			(1 << 23)
+#define EMIF_REG_DYN_ODT_SHIFT			21
+#define EMIF_REG_DYN_ODT_MASK			(0x3 << 21)
+#define EMIF_REG_DDR_DISABLE_DLL_SHIFT		20
+#define EMIF_REG_DDR_DISABLE_DLL_MASK		(1 << 20)
+#define EMIF_REG_SDRAM_DRIVE_SHIFT			18
+#define EMIF_REG_SDRAM_DRIVE_MASK			(0x3 << 18)
+#define EMIF_REG_CWL_SHIFT				16
+#define EMIF_REG_CWL_MASK				(0x3 << 16)
+#define EMIF_REG_NARROW_MODE_SHIFT			14
+#define EMIF_REG_NARROW_MODE_MASK			(0x3 << 14)
+#define EMIF_REG_CL_SHIFT				10
+#define EMIF_REG_CL_MASK				(0xf << 10)
+#define EMIF_REG_ROWSIZE_SHIFT			7
+#define EMIF_REG_ROWSIZE_MASK			(0x7 << 7)
+#define EMIF_REG_IBANK_SHIFT			4
+#define EMIF_REG_IBANK_MASK				(0x7 << 4)
+#define EMIF_REG_EBANK_SHIFT			3
+#define EMIF_REG_EBANK_MASK				(1 << 3)
+#define EMIF_REG_PAGESIZE_SHIFT			0
+#define EMIF_REG_PAGESIZE_MASK			(0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define EMIF_REG_CS1NVMEN_SHIFT			30
+#define EMIF_REG_CS1NVMEN_MASK			(1 << 30)
+#define EMIF_REG_EBANK_POS_SHIFT			27
+#define EMIF_REG_EBANK_POS_MASK			(1 << 27)
+#define EMIF_REG_RDBNUM_SHIFT			4
+#define EMIF_REG_RDBNUM_MASK			(0x3 << 4)
+#define EMIF_REG_RDBSIZE_SHIFT			0
+#define EMIF_REG_RDBSIZE_MASK			(0x7 << 0)
+
+/* SDRAM_REF_CTRL */
+#define EMIF_REG_INITREF_DIS_SHIFT			31
+#define EMIF_REG_INITREF_DIS_MASK			(1 << 31)
+#define EMIF_REG_SRT_SHIFT				29
+#define EMIF_REG_SRT_MASK				(1 << 29)
+#define EMIF_REG_ASR_SHIFT				28
+#define EMIF_REG_ASR_MASK				(1 << 28)
+#define EMIF_REG_PASR_SHIFT				24
+#define EMIF_REG_PASR_MASK				(0x7 << 24)
+#define EMIF_REG_REFRESH_RATE_SHIFT			0
+#define EMIF_REG_REFRESH_RATE_MASK			(0xffff << 0)
+
+/* SDRAM_REF_CTRL_SHDW */
+#define EMIF_REG_REFRESH_RATE_SHDW_SHIFT		0
+#define EMIF_REG_REFRESH_RATE_SHDW_MASK		(0xffff << 0)
+
+/* SDRAM_TIM_1 */
+#define EMIF_REG_T_RP_SHIFT				25
+#define EMIF_REG_T_RP_MASK				(0xf << 25)
+#define EMIF_REG_T_RCD_SHIFT			21
+#define EMIF_REG_T_RCD_MASK				(0xf << 21)
+#define EMIF_REG_T_WR_SHIFT				17
+#define EMIF_REG_T_WR_MASK				(0xf << 17)
+#define EMIF_REG_T_RAS_SHIFT			12
+#define EMIF_REG_T_RAS_MASK				(0x1f << 12)
+#define EMIF_REG_T_RC_SHIFT				6
+#define EMIF_REG_T_RC_MASK				(0x3f << 6)
+#define EMIF_REG_T_RRD_SHIFT			3
+#define EMIF_REG_T_RRD_MASK				(0x7 << 3)
+#define EMIF_REG_T_WTR_SHIFT			0
+#define EMIF_REG_T_WTR_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_1_SHDW */
+#define EMIF_REG_T_RP_SHDW_SHIFT			25
+#define EMIF_REG_T_RP_SHDW_MASK			(0xf << 25)
+#define EMIF_REG_T_RCD_SHDW_SHIFT			21
+#define EMIF_REG_T_RCD_SHDW_MASK			(0xf << 21)
+#define EMIF_REG_T_WR_SHDW_SHIFT			17
+#define EMIF_REG_T_WR_SHDW_MASK			(0xf << 17)
+#define EMIF_REG_T_RAS_SHDW_SHIFT			12
+#define EMIF_REG_T_RAS_SHDW_MASK			(0x1f << 12)
+#define EMIF_REG_T_RC_SHDW_SHIFT			6
+#define EMIF_REG_T_RC_SHDW_MASK			(0x3f << 6)
+#define EMIF_REG_T_RRD_SHDW_SHIFT			3
+#define EMIF_REG_T_RRD_SHDW_MASK			(0x7 << 3)
+#define EMIF_REG_T_WTR_SHDW_SHIFT			0
+#define EMIF_REG_T_WTR_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_2 */
+#define EMIF_REG_T_XP_SHIFT				28
+#define EMIF_REG_T_XP_MASK				(0x7 << 28)
+#define EMIF_REG_T_ODT_SHIFT			25
+#define EMIF_REG_T_ODT_MASK				(0x7 << 25)
+#define EMIF_REG_T_XSNR_SHIFT			16
+#define EMIF_REG_T_XSNR_MASK			(0x1ff << 16)
+#define EMIF_REG_T_XSRD_SHIFT			6
+#define EMIF_REG_T_XSRD_MASK			(0x3ff << 6)
+#define EMIF_REG_T_RTP_SHIFT			3
+#define EMIF_REG_T_RTP_MASK				(0x7 << 3)
+#define EMIF_REG_T_CKE_SHIFT			0
+#define EMIF_REG_T_CKE_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_2_SHDW */
+#define EMIF_REG_T_XP_SHDW_SHIFT			28
+#define EMIF_REG_T_XP_SHDW_MASK			(0x7 << 28)
+#define EMIF_REG_T_ODT_SHDW_SHIFT			25
+#define EMIF_REG_T_ODT_SHDW_MASK			(0x7 << 25)
+#define EMIF_REG_T_XSNR_SHDW_SHIFT			16
+#define EMIF_REG_T_XSNR_SHDW_MASK			(0x1ff << 16)
+#define EMIF_REG_T_XSRD_SHDW_SHIFT			6
+#define EMIF_REG_T_XSRD_SHDW_MASK			(0x3ff << 6)
+#define EMIF_REG_T_RTP_SHDW_SHIFT			3
+#define EMIF_REG_T_RTP_SHDW_MASK			(0x7 << 3)
+#define EMIF_REG_T_CKE_SHDW_SHIFT			0
+#define EMIF_REG_T_CKE_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_3 */
+#define EMIF_REG_T_CKESR_SHIFT			21
+#define EMIF_REG_T_CKESR_MASK			(0x7 << 21)
+#define EMIF_REG_ZQ_ZQCS_SHIFT			15
+#define EMIF_REG_ZQ_ZQCS_MASK			(0x3f << 15)
+#define EMIF_REG_T_TDQSCKMAX_SHIFT			13
+#define EMIF_REG_T_TDQSCKMAX_MASK			(0x3 << 13)
+#define EMIF_REG_T_RFC_SHIFT			4
+#define EMIF_REG_T_RFC_MASK				(0x1ff << 4)
+#define EMIF_REG_T_RAS_MAX_SHIFT			0
+#define EMIF_REG_T_RAS_MAX_MASK			(0xf << 0)
+
+/* SDRAM_TIM_3_SHDW */
+#define EMIF_REG_T_CKESR_SHDW_SHIFT			21
+#define EMIF_REG_T_CKESR_SHDW_MASK			(0x7 << 21)
+#define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT			15
+#define EMIF_REG_ZQ_ZQCS_SHDW_MASK			(0x3f << 15)
+#define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT		13
+#define EMIF_REG_T_TDQSCKMAX_SHDW_MASK		(0x3 << 13)
+#define EMIF_REG_T_RFC_SHDW_SHIFT			4
+#define EMIF_REG_T_RFC_SHDW_MASK			(0x1ff << 4)
+#define EMIF_REG_T_RAS_MAX_SHDW_SHIFT		0
+#define EMIF_REG_T_RAS_MAX_SHDW_MASK		(0xf << 0)
+
+/* LPDDR2_NVM_TIM */
+#define EMIF_REG_NVM_T_XP_SHIFT			28
+#define EMIF_REG_NVM_T_XP_MASK			(0x7 << 28)
+#define EMIF_REG_NVM_T_WTR_SHIFT			24
+#define EMIF_REG_NVM_T_WTR_MASK			(0x7 << 24)
+#define EMIF_REG_NVM_T_RP_SHIFT			20
+#define EMIF_REG_NVM_T_RP_MASK			(0xf << 20)
+#define EMIF_REG_NVM_T_WRA_SHIFT			16
+#define EMIF_REG_NVM_T_WRA_MASK			(0xf << 16)
+#define EMIF_REG_NVM_T_RRD_SHIFT			8
+#define EMIF_REG_NVM_T_RRD_MASK			(0xff << 8)
+#define EMIF_REG_NVM_T_RCDMIN_SHIFT			0
+#define EMIF_REG_NVM_T_RCDMIN_MASK			(0xff << 0)
+
+/* LPDDR2_NVM_TIM_SHDW */
+#define EMIF_REG_NVM_T_XP_SHDW_SHIFT		28
+#define EMIF_REG_NVM_T_XP_SHDW_MASK			(0x7 << 28)
+#define EMIF_REG_NVM_T_WTR_SHDW_SHIFT		24
+#define EMIF_REG_NVM_T_WTR_SHDW_MASK		(0x7 << 24)
+#define EMIF_REG_NVM_T_RP_SHDW_SHIFT		20
+#define EMIF_REG_NVM_T_RP_SHDW_MASK			(0xf << 20)
+#define EMIF_REG_NVM_T_WRA_SHDW_SHIFT		16
+#define EMIF_REG_NVM_T_WRA_SHDW_MASK		(0xf << 16)
+#define EMIF_REG_NVM_T_RRD_SHDW_SHIFT		8
+#define EMIF_REG_NVM_T_RRD_SHDW_MASK		(0xff << 8)
+#define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT		0
+#define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK		(0xff << 0)
+
+/* PWR_MGMT_CTRL */
+#define EMIF_REG_IDLEMODE_SHIFT			30
+#define EMIF_REG_IDLEMODE_MASK			(0x3 << 30)
+#define EMIF_REG_PD_TIM_SHIFT			12
+#define EMIF_REG_PD_TIM_MASK			(0xf << 12)
+#define EMIF_REG_DPD_EN_SHIFT			11
+#define EMIF_REG_DPD_EN_MASK			(1 << 11)
+#define EMIF_REG_LP_MODE_SHIFT			8
+#define EMIF_REG_LP_MODE_MASK			(0x7 << 8)
+#define EMIF_REG_SR_TIM_SHIFT			4
+#define EMIF_REG_SR_TIM_MASK			(0xf << 4)
+#define EMIF_REG_CS_TIM_SHIFT			0
+#define EMIF_REG_CS_TIM_MASK			(0xf << 0)
+
+/* PWR_MGMT_CTRL_SHDW */
+#define EMIF_REG_PD_TIM_SHDW_SHIFT			12
+#define EMIF_REG_PD_TIM_SHDW_MASK			(0xf << 12)
+#define EMIF_REG_SR_TIM_SHDW_SHIFT			4
+#define EMIF_REG_SR_TIM_SHDW_MASK			(0xf << 4)
+#define EMIF_REG_CS_TIM_SHDW_SHIFT			0
+#define EMIF_REG_CS_TIM_SHDW_MASK			(0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define EMIF_REG_VALUE_0_SHIFT			0
+#define EMIF_REG_VALUE_0_MASK			(0x7f << 0)
+
+/* LPDDR2_MODE_REG_CFG */
+#define EMIF_REG_CS_SHIFT				31
+#define EMIF_REG_CS_MASK				(1 << 31)
+#define EMIF_REG_REFRESH_EN_SHIFT			30
+#define EMIF_REG_REFRESH_EN_MASK			(1 << 30)
+#define EMIF_REG_ADDRESS_SHIFT			0
+#define EMIF_REG_ADDRESS_MASK			(0xff << 0)
+
+/* OCP_CONFIG */
+#define EMIF_REG_SYS_THRESH_MAX_SHIFT		24
+#define EMIF_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
+#define EMIF_REG_MPU_THRESH_MAX_SHIFT		20
+#define EMIF_REG_MPU_THRESH_MAX_MASK		(0xf << 20)
+#define EMIF_REG_LL_THRESH_MAX_SHIFT		16
+#define EMIF_REG_LL_THRESH_MAX_MASK			(0xf << 16)
+#define EMIF_REG_PR_OLD_COUNT_SHIFT			0
+#define EMIF_REG_PR_OLD_COUNT_MASK			(0xff << 0)
+
+/* OCP_CFG_VAL_1 */
+#define EMIF_REG_SYS_BUS_WIDTH_SHIFT		30
+#define EMIF_REG_SYS_BUS_WIDTH_MASK			(0x3 << 30)
+#define EMIF_REG_LL_BUS_WIDTH_SHIFT			28
+#define EMIF_REG_LL_BUS_WIDTH_MASK			(0x3 << 28)
+#define EMIF_REG_WR_FIFO_DEPTH_SHIFT		8
+#define EMIF_REG_WR_FIFO_DEPTH_MASK			(0xff << 8)
+#define EMIF_REG_CMD_FIFO_DEPTH_SHIFT		0
+#define EMIF_REG_CMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* OCP_CFG_VAL_2 */
+#define EMIF_REG_RREG_FIFO_DEPTH_SHIFT		16
+#define EMIF_REG_RREG_FIFO_DEPTH_MASK		(0xff << 16)
+#define EMIF_REG_RSD_FIFO_DEPTH_SHIFT		8
+#define EMIF_REG_RSD_FIFO_DEPTH_MASK		(0xff << 8)
+#define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT		0
+#define EMIF_REG_RCMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* IODFT_TLGC */
+#define EMIF_REG_TLEC_SHIFT				16
+#define EMIF_REG_TLEC_MASK				(0xffff << 16)
+#define EMIF_REG_MT_SHIFT				14
+#define EMIF_REG_MT_MASK				(1 << 14)
+#define EMIF_REG_ACT_CAP_EN_SHIFT			13
+#define EMIF_REG_ACT_CAP_EN_MASK			(1 << 13)
+#define EMIF_REG_OPG_LD_SHIFT			12
+#define EMIF_REG_OPG_LD_MASK			(1 << 12)
+#define EMIF_REG_RESET_PHY_SHIFT			10
+#define EMIF_REG_RESET_PHY_MASK			(1 << 10)
+#define EMIF_REG_MMS_SHIFT				8
+#define EMIF_REG_MMS_MASK				(1 << 8)
+#define EMIF_REG_MC_SHIFT				4
+#define EMIF_REG_MC_MASK				(0x3 << 4)
+#define EMIF_REG_PC_SHIFT				1
+#define EMIF_REG_PC_MASK				(0x7 << 1)
+#define EMIF_REG_TM_SHIFT				0
+#define EMIF_REG_TM_MASK				(1 << 0)
+
+/* IODFT_CTRL_MISR_RSLT */
+#define EMIF_REG_DQM_TLMR_SHIFT			16
+#define EMIF_REG_DQM_TLMR_MASK			(0x3ff << 16)
+#define EMIF_REG_CTL_TLMR_SHIFT			0
+#define EMIF_REG_CTL_TLMR_MASK			(0x7ff << 0)
+
+/* IODFT_ADDR_MISR_RSLT */
+#define EMIF_REG_ADDR_TLMR_SHIFT			0
+#define EMIF_REG_ADDR_TLMR_MASK			(0x1fffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_1 */
+#define EMIF_REG_DATA_TLMR_31_0_SHIFT		0
+#define EMIF_REG_DATA_TLMR_31_0_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_2 */
+#define EMIF_REG_DATA_TLMR_63_32_SHIFT		0
+#define EMIF_REG_DATA_TLMR_63_32_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_3 */
+#define EMIF_REG_DATA_TLMR_66_64_SHIFT		0
+#define EMIF_REG_DATA_TLMR_66_64_MASK		(0x7 << 0)
+
+/* PERF_CNT_1 */
+#define EMIF_REG_COUNTER1_SHIFT			0
+#define EMIF_REG_COUNTER1_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_2 */
+#define EMIF_REG_COUNTER2_SHIFT			0
+#define EMIF_REG_COUNTER2_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_CFG */
+#define EMIF_REG_CNTR2_MCONNID_EN_SHIFT		31
+#define EMIF_REG_CNTR2_MCONNID_EN_MASK		(1 << 31)
+#define EMIF_REG_CNTR2_REGION_EN_SHIFT		30
+#define EMIF_REG_CNTR2_REGION_EN_MASK		(1 << 30)
+#define EMIF_REG_CNTR2_CFG_SHIFT			16
+#define EMIF_REG_CNTR2_CFG_MASK			(0xf << 16)
+#define EMIF_REG_CNTR1_MCONNID_EN_SHIFT		15
+#define EMIF_REG_CNTR1_MCONNID_EN_MASK		(1 << 15)
+#define EMIF_REG_CNTR1_REGION_EN_SHIFT		14
+#define EMIF_REG_CNTR1_REGION_EN_MASK		(1 << 14)
+#define EMIF_REG_CNTR1_CFG_SHIFT			0
+#define EMIF_REG_CNTR1_CFG_MASK			(0xf << 0)
+
+/* PERF_CNT_SEL */
+#define EMIF_REG_MCONNID2_SHIFT			24
+#define EMIF_REG_MCONNID2_MASK			(0xff << 24)
+#define EMIF_REG_REGION_SEL2_SHIFT			16
+#define EMIF_REG_REGION_SEL2_MASK			(0x3 << 16)
+#define EMIF_REG_MCONNID1_SHIFT			8
+#define EMIF_REG_MCONNID1_MASK			(0xff << 8)
+#define EMIF_REG_REGION_SEL1_SHIFT			0
+#define EMIF_REG_REGION_SEL1_MASK			(0x3 << 0)
+
+/* PERF_CNT_TIM */
+#define EMIF_REG_TOTAL_TIME_SHIFT			0
+#define EMIF_REG_TOTAL_TIME_MASK			(0xffffffff << 0)
+
+/* READ_IDLE_CTRL */
+#define EMIF_REG_READ_IDLE_LEN_SHIFT		16
+#define EMIF_REG_READ_IDLE_LEN_MASK			(0xf << 16)
+#define EMIF_REG_READ_IDLE_INTERVAL_SHIFT		0
+#define EMIF_REG_READ_IDLE_INTERVAL_MASK		(0x1ff << 0)
+
+/* READ_IDLE_CTRL_SHDW */
+#define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT		16
+#define EMIF_REG_READ_IDLE_LEN_SHDW_MASK		(0xf << 16)
+#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT	0
+#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK	(0x1ff << 0)
+
+/* IRQ_EOI */
+#define EMIF_REG_EOI_SHIFT				0
+#define EMIF_REG_EOI_MASK				(1 << 0)
+
+/* IRQSTATUS_RAW_SYS */
+#define EMIF_REG_DNV_SYS_SHIFT			2
+#define EMIF_REG_DNV_SYS_MASK			(1 << 2)
+#define EMIF_REG_TA_SYS_SHIFT			1
+#define EMIF_REG_TA_SYS_MASK			(1 << 1)
+#define EMIF_REG_ERR_SYS_SHIFT			0
+#define EMIF_REG_ERR_SYS_MASK			(1 << 0)
+
+/* IRQSTATUS_RAW_LL */
+#define EMIF_REG_DNV_LL_SHIFT			2
+#define EMIF_REG_DNV_LL_MASK			(1 << 2)
+#define EMIF_REG_TA_LL_SHIFT			1
+#define EMIF_REG_TA_LL_MASK				(1 << 1)
+#define EMIF_REG_ERR_LL_SHIFT			0
+#define EMIF_REG_ERR_LL_MASK			(1 << 0)
+
+/* IRQSTATUS_SYS */
+
+/* IRQSTATUS_LL */
+
+/* IRQENABLE_SET_SYS */
+#define EMIF_REG_EN_DNV_SYS_SHIFT			2
+#define EMIF_REG_EN_DNV_SYS_MASK			(1 << 2)
+#define EMIF_REG_EN_TA_SYS_SHIFT			1
+#define EMIF_REG_EN_TA_SYS_MASK			(1 << 1)
+#define EMIF_REG_EN_ERR_SYS_SHIFT			0
+#define EMIF_REG_EN_ERR_SYS_MASK			(1 << 0)
+
+/* IRQENABLE_SET_LL */
+#define EMIF_REG_EN_DNV_LL_SHIFT			2
+#define EMIF_REG_EN_DNV_LL_MASK			(1 << 2)
+#define EMIF_REG_EN_TA_LL_SHIFT			1
+#define EMIF_REG_EN_TA_LL_MASK			(1 << 1)
+#define EMIF_REG_EN_ERR_LL_SHIFT			0
+#define EMIF_REG_EN_ERR_LL_MASK			(1 << 0)
+
+/* IRQENABLE_CLR_SYS */
+
+/* IRQENABLE_CLR_LL */
+
+/* ZQ_CONFIG */
+#define EMIF_REG_ZQ_CS1EN_SHIFT			31
+#define EMIF_REG_ZQ_CS1EN_MASK			(1 << 31)
+#define EMIF_REG_ZQ_CS0EN_SHIFT			30
+#define EMIF_REG_ZQ_CS0EN_MASK			(1 << 30)
+#define EMIF_REG_ZQ_DUALCALEN_SHIFT			29
+#define EMIF_REG_ZQ_DUALCALEN_MASK			(1 << 29)
+#define EMIF_REG_ZQ_SFEXITEN_SHIFT			28
+#define EMIF_REG_ZQ_SFEXITEN_MASK			(1 << 28)
+#define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT		18
+#define EMIF_REG_ZQ_ZQINIT_MULT_MASK		(0x3 << 18)
+#define EMIF_REG_ZQ_ZQCL_MULT_SHIFT			16
+#define EMIF_REG_ZQ_ZQCL_MULT_MASK			(0x3 << 16)
+#define EMIF_REG_ZQ_REFINTERVAL_SHIFT		0
+#define EMIF_REG_ZQ_REFINTERVAL_MASK		(0xffff << 0)
+
+/* TEMP_ALERT_CONFIG */
+#define EMIF_REG_TA_CS1EN_SHIFT			31
+#define EMIF_REG_TA_CS1EN_MASK			(1 << 31)
+#define EMIF_REG_TA_CS0EN_SHIFT			30
+#define EMIF_REG_TA_CS0EN_MASK			(1 << 30)
+#define EMIF_REG_TA_SFEXITEN_SHIFT			28
+#define EMIF_REG_TA_SFEXITEN_MASK			(1 << 28)
+#define EMIF_REG_TA_DEVWDT_SHIFT			26
+#define EMIF_REG_TA_DEVWDT_MASK			(0x3 << 26)
+#define EMIF_REG_TA_DEVCNT_SHIFT			24
+#define EMIF_REG_TA_DEVCNT_MASK			(0x3 << 24)
+#define EMIF_REG_TA_REFINTERVAL_SHIFT		0
+#define EMIF_REG_TA_REFINTERVAL_MASK		(0x3fffff << 0)
+
+/* OCP_ERR_LOG */
+#define EMIF_REG_MADDRSPACE_SHIFT			14
+#define EMIF_REG_MADDRSPACE_MASK			(0x3 << 14)
+#define EMIF_REG_MBURSTSEQ_SHIFT			11
+#define EMIF_REG_MBURSTSEQ_MASK			(0x7 << 11)
+#define EMIF_REG_MCMD_SHIFT				8
+#define EMIF_REG_MCMD_MASK				(0x7 << 8)
+#define EMIF_REG_MCONNID_SHIFT			0
+#define EMIF_REG_MCONNID_MASK			(0xff << 0)
+
+/* DDR_PHY_CTRL_1 */
+#define EMIF_REG_DDR_PHY_CTRL_1_SHIFT		4
+#define EMIF_REG_DDR_PHY_CTRL_1_MASK		(0xfffffff << 4)
+#define EMIF_REG_READ_LATENCY_SHIFT			0
+#define EMIF_REG_READ_LATENCY_MASK			(0xf << 0)
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT		4
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK		(0xFF << 4)
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT	12
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT		4
+#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK		(0xfffffff << 4)
+#define EMIF_REG_READ_LATENCY_SHDW_SHIFT		0
+#define EMIF_REG_READ_LATENCY_SHDW_MASK		(0xf << 0)
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT	4
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_2 */
+#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT		0
+#define EMIF_REG_DDR_PHY_CTRL_2_MASK		(0xffffffff << 0)
+
+/*EMIF_READ_WRITE_LEVELING_CONTROL*/
+#define EMIF_REG_RDWRLVLFULL_START_SHIFT	31
+#define EMIF_REG_RDWRLVLFULL_START_MASK		(1 << 31)
+#define EMIF_REG_RDWRLVLINC_PRE_SHIFT		24
+#define EMIF_REG_RDWRLVLINC_PRE_MASK		(0x7F << 24)
+#define EMIF_REG_RDLVLINC_INT_SHIFT		16
+#define EMIF_REG_RDLVLINC_INT_MASK		(0xFF << 16)
+#define EMIF_REG_RDLVLGATEINC_INT_SHIFT		8
+#define EMIF_REG_RDLVLGATEINC_INT_MASK		(0xFF << 8)
+#define EMIF_REG_WRLVLINC_INT_SHIFT		0
+#define EMIF_REG_WRLVLINC_INT_MASK		(0xFF << 0)
+
+/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/
+#define EMIF_REG_RDWRLVL_EN_SHIFT		31
+#define EMIF_REG_RDWRLVL_EN_MASK		(1 << 31)
+#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT	24
+#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK	(0x7F << 24)
+#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT		16
+#define EMIF_REG_RDLVLINC_RMP_INT_MASK		(0xFF << 16)
+#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT	8
+#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK	(0xFF << 8)
+#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT		0
+#define EMIF_REG_WRLVLINC_RMP_INT_MASK		(0xFF << 0)
+
+/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/
+#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT	0
+#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK	(0x1FFF << 0)
+
+/*Leveling Fields */
+#define DDR3_WR_LVL_INT		0x73
+#define DDR3_RD_LVL_INT		0x33
+#define DDR3_RD_LVL_GATE_INT	0x59
+#define RD_RW_LVL_INC_PRE	0x0
+#define DDR3_FULL_LVL		(1 << EMIF_REG_RDWRLVL_EN_SHIFT)
+
+#define DDR3_INC_LVL	((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT)   \
+		| (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \
+		| (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT)      \
+		| (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT))
+
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES	0x0000C1A7
+#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES	0x000001A7
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
+
+/* DMM */
+#define DMM_BASE			0x4E000040
+
+/* Memory Adapter */
+#define MA_BASE				0x482AF040
+
+/* DMM_LISA_MAP */
+#define EMIF_SYS_ADDR_SHIFT		24
+#define EMIF_SYS_ADDR_MASK		(0xff << 24)
+#define EMIF_SYS_SIZE_SHIFT		20
+#define EMIF_SYS_SIZE_MASK		(0x7 << 20)
+#define EMIF_SDRC_INTL_SHIFT	18
+#define EMIF_SDRC_INTL_MASK		(0x3 << 18)
+#define EMIF_SDRC_ADDRSPC_SHIFT	16
+#define EMIF_SDRC_ADDRSPC_MASK	(0x3 << 16)
+#define EMIF_SDRC_MAP_SHIFT		8
+#define EMIF_SDRC_MAP_MASK		(0x3 << 8)
+#define EMIF_SDRC_ADDR_SHIFT	0
+#define EMIF_SDRC_ADDR_MASK		(0xff << 0)
+
+/* DMM_LISA_MAP fields */
+#define DMM_SDRC_MAP_UNMAPPED		0
+#define DMM_SDRC_MAP_EMIF1_ONLY		1
+#define DMM_SDRC_MAP_EMIF2_ONLY		2
+#define DMM_SDRC_MAP_EMIF1_AND_EMIF2	3
+
+#define DMM_SDRC_INTL_NONE		0
+#define DMM_SDRC_INTL_128B		1
+#define DMM_SDRC_INTL_256B		2
+#define DMM_SDRC_INTL_512		3
+
+#define DMM_SDRC_ADDR_SPC_SDRAM		0
+#define DMM_SDRC_ADDR_SPC_NVM		1
+#define DMM_SDRC_ADDR_SPC_INVALID	2
+
+#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL		(\
+	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
+	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
+	(DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
+	(CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
+
+#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
+
+#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
+
+/* Trap for invalid TILER PAT entries */
+#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
+	(0  << EMIF_SDRC_ADDR_SHIFT) |\
+	(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\
+	(0xFF << EMIF_SYS_ADDR_SHIFT))
+
+#define EMIF_EXT_PHY_CTRL_TIMING_REG	0x5
+
+/* Reg mapping structure */
+struct emif_reg_struct {
+	u32 emif_mod_id_rev;
+	u32 emif_status;
+	u32 emif_sdram_config;
+	u32 emif_lpddr2_nvm_config;
+	u32 emif_sdram_ref_ctrl;
+	u32 emif_sdram_ref_ctrl_shdw;
+	u32 emif_sdram_tim_1;
+	u32 emif_sdram_tim_1_shdw;
+	u32 emif_sdram_tim_2;
+	u32 emif_sdram_tim_2_shdw;
+	u32 emif_sdram_tim_3;
+	u32 emif_sdram_tim_3_shdw;
+	u32 emif_lpddr2_nvm_tim;
+	u32 emif_lpddr2_nvm_tim_shdw;
+	u32 emif_pwr_mgmt_ctrl;
+	u32 emif_pwr_mgmt_ctrl_shdw;
+	u32 emif_lpddr2_mode_reg_data;
+	u32 padding1[1];
+	u32 emif_lpddr2_mode_reg_data_es2;
+	u32 padding11[1];
+	u32 emif_lpddr2_mode_reg_cfg;
+	u32 emif_l3_config;
+	u32 emif_l3_cfg_val_1;
+	u32 emif_l3_cfg_val_2;
+	u32 emif_iodft_tlgc;
+	u32 padding2[7];
+	u32 emif_perf_cnt_1;
+	u32 emif_perf_cnt_2;
+	u32 emif_perf_cnt_cfg;
+	u32 emif_perf_cnt_sel;
+	u32 emif_perf_cnt_tim;
+	u32 padding3;
+	u32 emif_read_idlectrl;
+	u32 emif_read_idlectrl_shdw;
+	u32 padding4;
+	u32 emif_irqstatus_raw_sys;
+	u32 emif_irqstatus_raw_ll;
+	u32 emif_irqstatus_sys;
+	u32 emif_irqstatus_ll;
+	u32 emif_irqenable_set_sys;
+	u32 emif_irqenable_set_ll;
+	u32 emif_irqenable_clr_sys;
+	u32 emif_irqenable_clr_ll;
+	u32 padding5;
+	u32 emif_zq_config;
+	u32 emif_temp_alert_config;
+	u32 emif_l3_err_log;
+	u32 emif_rd_wr_lvl_rmp_win;
+	u32 emif_rd_wr_lvl_rmp_ctl;
+	u32 emif_rd_wr_lvl_ctl;
+	u32 padding6[1];
+	u32 emif_ddr_phy_ctrl_1;
+	u32 emif_ddr_phy_ctrl_1_shdw;
+	u32 emif_ddr_phy_ctrl_2;
+	u32 padding7[12];
+	u32 emif_rd_wr_exec_thresh;
+	u32 padding8[7];
+	u32 emif_ddr_phy_status[21];
+	u32 padding9[27];
+	u32 emif_ddr_ext_phy_ctrl_1;
+	u32 emif_ddr_ext_phy_ctrl_1_shdw;
+	u32 emif_ddr_ext_phy_ctrl_2;
+	u32 emif_ddr_ext_phy_ctrl_2_shdw;
+	u32 emif_ddr_ext_phy_ctrl_3;
+	u32 emif_ddr_ext_phy_ctrl_3_shdw;
+	u32 emif_ddr_ext_phy_ctrl_4;
+	u32 emif_ddr_ext_phy_ctrl_4_shdw;
+	u32 emif_ddr_ext_phy_ctrl_5;
+	u32 emif_ddr_ext_phy_ctrl_5_shdw;
+	u32 emif_ddr_ext_phy_ctrl_6;
+	u32 emif_ddr_ext_phy_ctrl_6_shdw;
+	u32 emif_ddr_ext_phy_ctrl_7;
+	u32 emif_ddr_ext_phy_ctrl_7_shdw;
+	u32 emif_ddr_ext_phy_ctrl_8;
+	u32 emif_ddr_ext_phy_ctrl_8_shdw;
+	u32 emif_ddr_ext_phy_ctrl_9;
+	u32 emif_ddr_ext_phy_ctrl_9_shdw;
+	u32 emif_ddr_ext_phy_ctrl_10;
+	u32 emif_ddr_ext_phy_ctrl_10_shdw;
+	u32 emif_ddr_ext_phy_ctrl_11;
+	u32 emif_ddr_ext_phy_ctrl_11_shdw;
+	u32 emif_ddr_ext_phy_ctrl_12;
+	u32 emif_ddr_ext_phy_ctrl_12_shdw;
+	u32 emif_ddr_ext_phy_ctrl_13;
+	u32 emif_ddr_ext_phy_ctrl_13_shdw;
+	u32 emif_ddr_ext_phy_ctrl_14;
+	u32 emif_ddr_ext_phy_ctrl_14_shdw;
+	u32 emif_ddr_ext_phy_ctrl_15;
+	u32 emif_ddr_ext_phy_ctrl_15_shdw;
+	u32 emif_ddr_ext_phy_ctrl_16;
+	u32 emif_ddr_ext_phy_ctrl_16_shdw;
+	u32 emif_ddr_ext_phy_ctrl_17;
+	u32 emif_ddr_ext_phy_ctrl_17_shdw;
+	u32 emif_ddr_ext_phy_ctrl_18;
+	u32 emif_ddr_ext_phy_ctrl_18_shdw;
+	u32 emif_ddr_ext_phy_ctrl_19;
+	u32 emif_ddr_ext_phy_ctrl_19_shdw;
+	u32 emif_ddr_ext_phy_ctrl_20;
+	u32 emif_ddr_ext_phy_ctrl_20_shdw;
+	u32 emif_ddr_ext_phy_ctrl_21;
+	u32 emif_ddr_ext_phy_ctrl_21_shdw;
+	u32 emif_ddr_ext_phy_ctrl_22;
+	u32 emif_ddr_ext_phy_ctrl_22_shdw;
+	u32 emif_ddr_ext_phy_ctrl_23;
+	u32 emif_ddr_ext_phy_ctrl_23_shdw;
+	u32 emif_ddr_ext_phy_ctrl_24;
+	u32 emif_ddr_ext_phy_ctrl_24_shdw;
+	u32 padding[22];
+	u32 emif_ddr_fifo_misaligned_clear_1;
+	u32 emif_ddr_fifo_misaligned_clear_2;
+};
+
+struct dmm_lisa_map_regs {
+	u32 dmm_lisa_map_0;
+	u32 dmm_lisa_map_1;
+	u32 dmm_lisa_map_2;
+	u32 dmm_lisa_map_3;
+	u8 is_ma_present;
+};
+
+#define CS0	0
+#define CS1	1
+/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
+#define MAX_LPDDR2_FREQ	400000000	/* 400 MHz */
+
+/*
+ * The period of DDR clk is represented as numerator and denominator for
+ * better accuracy in integer based calculations. However, if the numerator
+ * and denominator are very huge there may be chances of overflow in
+ * calculations. So, as a trade-off keep denominator(and consequently
+ * numerator) within a limit sacrificing some accuracy - but not much
+ * If denominator and numerator are already small (such as at 400 MHz)
+ * no adjustment is needed
+ */
+#define EMIF_PERIOD_DEN_LIMIT	1000
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES	6
+/*
+ * Indices into the Addressing Table array.
+ * One entry each for all the different types of devices with different
+ * addressing schemes
+ */
+#define ADDR_TABLE_INDEX64M	0
+#define ADDR_TABLE_INDEX128M	1
+#define ADDR_TABLE_INDEX256M	2
+#define ADDR_TABLE_INDEX512M	3
+#define ADDR_TABLE_INDEX1GS4	4
+#define ADDR_TABLE_INDEX2GS4	5
+#define ADDR_TABLE_INDEX4G	6
+#define ADDR_TABLE_INDEX8G	7
+#define ADDR_TABLE_INDEX1GS2	8
+#define ADDR_TABLE_INDEX2GS2	9
+#define ADDR_TABLE_INDEXMAX	10
+
+/* Number of Row bits */
+#define ROW_9  0
+#define ROW_10 1
+#define ROW_11 2
+#define ROW_12 3
+#define ROW_13 4
+#define ROW_14 5
+#define ROW_15 6
+#define ROW_16 7
+
+/* Number of Column bits */
+#define COL_8   0
+#define COL_9   1
+#define COL_10  2
+#define COL_11  3
+#define COL_7   4 /*Not supported by OMAP included for completeness */
+
+/* Number of Banks*/
+#define BANKS1 0
+#define BANKS2 1
+#define BANKS4 2
+#define BANKS8 3
+
+/* Refresh rate in micro seconds x 10 */
+#define T_REFI_15_6	156
+#define T_REFI_7_8	78
+#define T_REFI_3_9	39
+
+#define EBANK_CS1_DIS	0
+#define EBANK_CS1_EN	1
+
+/* Read Latency used by the device at reset */
+#define RL_BOOT		3
+/* Read Latency for the highest frequency you want to use */
+#ifdef CONFIG_OMAP54XX
+#define RL_FINAL	8
+#else
+#define RL_FINAL	6
+#endif
+
+
+/* Interleaving policies at EMIF level- between banks and Chip Selects */
+#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING	0
+#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING	3
+
+/*
+ * Interleaving policy to be used
+ * Currently set to MAX interleaving for better performance
+ */
+#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
+
+/* State of the core voltage:
+ * This is important for some parameters such as read idle control and
+ * ZQ calibration timings. Timings are much stricter when voltage ramp
+ * is happening compared to when the voltage is stable.
+ * We need to calculate two sets of values for these parameters and use
+ * them accordingly
+ */
+#define LPDDR2_VOLTAGE_STABLE	0
+#define LPDDR2_VOLTAGE_RAMPING	1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_REG_READ_IDLE_LEN_VAL	5
+
+/* Interval between forced 'read idles' */
+/* To be used when voltage is changed for DPS/DVFS - 1us */
+#define READ_IDLE_INTERVAL_DVFS		(1*1000)
+/*
+ * To be used when voltage is not scaled except by Smart Reflex
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL	(50*1000)
+
+
+/*
+ * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
+ * be enough. This shoule be enough also in the case when voltage is changing
+ * due to smart-reflex.
+ */
+#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US	(50*1000)
+/*
+ * If voltage is changing due to DVFS ZQCS should be performed more
+ * often(every 50us)
+ */
+#define EMIF_ZQCS_INTERVAL_DVFS_IN_US	50
+
+/* The interval between ZQCL commands as a multiple of ZQCS interval */
+#define REG_ZQ_ZQCL_MULT		4
+/* The interval between ZQINIT commands as a multiple of ZQCL interval */
+#define REG_ZQ_ZQINIT_MULT		3
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define REG_ZQ_SFEXITEN_ENABLE		1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ * None of the boards that we know of have this capability
+ * So disabled by default
+ */
+#define REG_ZQ_DUALCALEN_DISABLE	0
+/*
+ * Enable ZQ Calibration by default on CS0. If we are asked to program
+ * the EMIF there will be something connected to CS0 for sure
+ */
+#define REG_ZQ_CS0EN_ENABLE		1
+
+/* EMIF_PWR_MGMT_CTRL register */
+/* Low power modes */
+#define LP_MODE_DISABLE		0
+#define LP_MODE_CLOCK_STOP	1
+#define LP_MODE_SELF_REFRESH	2
+#define LP_MODE_PWR_DN		3
+
+/* REG_DPD_EN */
+#define DPD_DISABLE	0
+#define DPD_ENABLE	1
+
+/* Maximum delay before Low Power Modes */
+#define REG_CS_TIM		0x0
+#define REG_SR_TIM		0x0
+#define REG_PD_TIM		0x0
+
+
+/* EMIF_PWR_MGMT_CTRL register */
+#define EMIF_PWR_MGMT_CTRL (\
+	((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
+	((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
+	((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
+	((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
+	((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
+			& EMIF_REG_LP_MODE_MASK) |\
+	((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
+			& EMIF_REG_DPD_EN_MASK))\
+
+#define EMIF_PWR_MGMT_CTRL_SHDW (\
+	((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\
+			& EMIF_REG_CS_TIM_SHDW_MASK) |\
+	((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
+			& EMIF_REG_SR_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
+			& EMIF_REG_PD_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
+			& EMIF_REG_PD_TIM_SHDW_MASK))
+
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0	0x0A0000FF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0	0x0A500000
+
+/*
+ * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
+ * All these fields have magic values dependent on frequency and
+ * determined by PHY and DLL integration with EMIF. Setting the magic
+ * values suggested by hw team.
+ */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL			0x049FF
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ			0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ			0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS	0xFF
+
+/*
+* MR1 value:
+* Burst length	: 8
+* Burst type	: sequential
+* Wrap		: enabled
+* nWR		: 3(default). EMIF does not do pre-charge.
+*		: So nWR is don't care
+*/
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3	0x23
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8	0xc3
+
+/* MR2 */
+#define MR2_RL3_WL1			1
+#define MR2_RL4_WL2			2
+#define MR2_RL5_WL2			3
+#define MR2_RL6_WL3			4
+
+/* MR10: ZQ calibration codes */
+#define MR10_ZQ_ZQCS		0x56
+#define MR10_ZQ_ZQCL		0xAB
+#define MR10_ZQ_ZQINIT		0xFF
+#define MR10_ZQ_ZQRESET		0xC3
+
+/* TEMP_ALERT_CONFIG */
+#define TEMP_ALERT_POLL_INTERVAL_MS	360 /* for temp gradient - 5 C/s */
+#define TEMP_ALERT_CONFIG_DEVCT_1	0
+#define TEMP_ALERT_CONFIG_DEVWDT_32	2
+
+/* MR16 value: refresh full array(no partial array self refresh) */
+#define MR16_REF_FULL_ARRAY	0
+
+/*
+ * Maximum number of entries we keep in our array of timing tables
+ * We need not keep all the speed bins supported by the device
+ * We need to keep timing tables for only the speed bins that we
+ * are interested in
+ */
+#define MAX_NUM_SPEEDBINS	4
+
+/* LPDDR2 Densities */
+#define LPDDR2_DENSITY_64Mb	0
+#define LPDDR2_DENSITY_128Mb	1
+#define LPDDR2_DENSITY_256Mb	2
+#define LPDDR2_DENSITY_512Mb	3
+#define LPDDR2_DENSITY_1Gb	4
+#define LPDDR2_DENSITY_2Gb	5
+#define LPDDR2_DENSITY_4Gb	6
+#define LPDDR2_DENSITY_8Gb	7
+#define LPDDR2_DENSITY_16Gb	8
+#define LPDDR2_DENSITY_32Gb	9
+
+/* LPDDR2 type */
+#define	LPDDR2_TYPE_S4	0
+#define	LPDDR2_TYPE_S2	1
+#define	LPDDR2_TYPE_NVM	2
+
+/* LPDDR2 IO width */
+#define	LPDDR2_IO_WIDTH_32	0
+#define	LPDDR2_IO_WIDTH_16	1
+#define	LPDDR2_IO_WIDTH_8	2
+
+/* Mode register numbers */
+#define LPDDR2_MR0	0
+#define LPDDR2_MR1	1
+#define LPDDR2_MR2	2
+#define LPDDR2_MR3	3
+#define LPDDR2_MR4	4
+#define LPDDR2_MR5	5
+#define LPDDR2_MR6	6
+#define LPDDR2_MR7	7
+#define LPDDR2_MR8	8
+#define LPDDR2_MR9	9
+#define LPDDR2_MR10	10
+#define LPDDR2_MR11	11
+#define LPDDR2_MR16	16
+#define LPDDR2_MR17	17
+#define LPDDR2_MR18	18
+
+/* MR0 */
+#define LPDDR2_MR0_DAI_SHIFT	0
+#define LPDDR2_MR0_DAI_MASK	1
+#define LPDDR2_MR0_DI_SHIFT	1
+#define LPDDR2_MR0_DI_MASK	(1 << 1)
+#define LPDDR2_MR0_DNVI_SHIFT	2
+#define LPDDR2_MR0_DNVI_MASK	(1 << 2)
+
+/* MR4 */
+#define MR4_SDRAM_REF_RATE_SHIFT	0
+#define MR4_SDRAM_REF_RATE_MASK		7
+#define MR4_TUF_SHIFT			7
+#define MR4_TUF_MASK			(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_LESS_LOW_SHUTDOWN			0x0
+#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS		0x1
+#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS		0x2
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define LPDDR2_MANUFACTURER_SAMSUNG	1
+#define LPDDR2_MANUFACTURER_QIMONDA	2
+#define LPDDR2_MANUFACTURER_ELPIDA	3
+#define LPDDR2_MANUFACTURER_ETRON	4
+#define LPDDR2_MANUFACTURER_NANYA	5
+#define LPDDR2_MANUFACTURER_HYNIX	6
+#define LPDDR2_MANUFACTURER_MOSEL	7
+#define LPDDR2_MANUFACTURER_WINBOND	8
+#define LPDDR2_MANUFACTURER_ESMT	9
+#define LPDDR2_MANUFACTURER_SPANSION 11
+#define LPDDR2_MANUFACTURER_SST		12
+#define LPDDR2_MANUFACTURER_ZMOS	13
+#define LPDDR2_MANUFACTURER_INTEL	14
+#define LPDDR2_MANUFACTURER_NUMONYX	254
+#define LPDDR2_MANUFACTURER_MICRON	255
+
+/* MR8 register fields */
+#define MR8_TYPE_SHIFT		0x0
+#define MR8_TYPE_MASK		0x3
+#define MR8_DENSITY_SHIFT	0x2
+#define MR8_DENSITY_MASK	(0xF << 0x2)
+#define MR8_IO_WIDTH_SHIFT	0x6
+#define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
+
+/* SDRAM TYPE */
+#define EMIF_SDRAM_TYPE_DDR2	0x2
+#define EMIF_SDRAM_TYPE_DDR3	0x3
+#define EMIF_SDRAM_TYPE_LPDDR2	0x4
+
+struct lpddr2_addressing {
+	u8	num_banks;
+	u8	t_REFI_us_x10;
+	u8	row_sz[2]; /* One entry each for x32 and x16 */
+	u8	col_sz[2]; /* One entry each for x32 and x16 */
+};
+
+/* Structure for timings from the DDR datasheet */
+struct lpddr2_ac_timings {
+	u32 max_freq;
+	u8 RL;
+	u8 tRPab;
+	u8 tRCD;
+	u8 tWR;
+	u8 tRASmin;
+	u8 tRRD;
+	u8 tWTRx2;
+	u8 tXSR;
+	u8 tXPx2;
+	u8 tRFCab;
+	u8 tRTPx2;
+	u8 tCKE;
+	u8 tCKESR;
+	u8 tZQCS;
+	u32 tZQCL;
+	u32 tZQINIT;
+	u8 tDQSCKMAXx2;
+	u8 tRASmax;
+	u8 tFAW;
+
+};
+
+/*
+ * Min tCK values for some of the parameters:
+ * If the calculated clock cycles for the respective parameter is
+ * less than the corresponding min tCK value, we need to set the min
+ * tCK value. This may happen at lower frequencies.
+ */
+struct lpddr2_min_tck {
+	u32 tRL;
+	u32 tRP_AB;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_MIN;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u8  tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+struct lpddr2_device_details {
+	u8	type;
+	u8	density;
+	u8	io_width;
+	u8	manufacturer;
+};
+
+struct lpddr2_device_timings {
+	const struct lpddr2_ac_timings **ac_timings;
+	const struct lpddr2_min_tck *min_tck;
+};
+
+/* Details of the devices connected to each chip-select of an EMIF instance */
+struct emif_device_details {
+	const struct lpddr2_device_details *cs0_device_details;
+	const struct lpddr2_device_details *cs1_device_details;
+	const struct lpddr2_device_timings *cs0_device_timings;
+	const struct lpddr2_device_timings *cs1_device_timings;
+};
+
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialization and DVFS
+ */
+struct emif_regs {
+	u32 freq;
+	u32 sdram_config_init;
+	u32 sdram_config;
+	u32 sdram_config2;
+	u32 ref_ctrl;
+	u32 sdram_tim1;
+	u32 sdram_tim2;
+	u32 sdram_tim3;
+	u32 read_idle_ctrl;
+	u32 zq_config;
+	u32 temp_alert_config;
+	u32 emif_ddr_phy_ctlr_1_init;
+	u32 emif_ddr_phy_ctlr_1;
+	u32 emif_ddr_ext_phy_ctrl_1;
+	u32 emif_ddr_ext_phy_ctrl_2;
+	u32 emif_ddr_ext_phy_ctrl_3;
+	u32 emif_ddr_ext_phy_ctrl_4;
+	u32 emif_ddr_ext_phy_ctrl_5;
+	u32 emif_rd_wr_lvl_rmp_win;
+	u32 emif_rd_wr_lvl_rmp_ctl;
+	u32 emif_rd_wr_lvl_ctl;
+	u32 emif_rd_wr_exec_thresh;
+};
+
+struct lpddr2_mr_regs {
+	s8 mr1;
+	s8 mr2;
+	s8 mr3;
+	s8 mr10;
+	s8 mr16;
+};
+
+struct read_write_regs {
+	u32 read_reg;
+	u32 write_reg;
+};
+
+static inline u32 get_emif_rev(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
+		>> EMIF_REG_MAJOR_REVISION_SHIFT;
+}
+
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+static inline u32 emif_sdram_type(void)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+	return (readl(&emif->emif_sdram_config) &
+		EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
+
+/* assert macros */
+#if defined(DEBUG)
+#define emif_assert(c)	({ if (!(c)) for (;;); })
+#else
+#define emif_assert(c)	({ if (0) hang(); })
+#endif
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+#else
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details);
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings);
+#endif
+
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
+
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+extern u32 *const T_num;
+extern u32 *const T_den;
+#endif
+
+void config_data_eye_leveling_samples(u32 emif_base);
+u32 emif_sdram_type(void);
+const struct read_write_regs *get_bug_regs(u32 *iterations);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/errno.h b/qemu/roms/u-boot/arch/arm/include/asm/errno.h
new file mode 100644
index 000000000..4c82b503d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/errno.h
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/gic.h b/qemu/roms/u-boot/arch/arm/include/asm/gic.h
new file mode 100644
index 000000000..bd3a80cdf
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/gic.h
@@ -0,0 +1,110 @@
+#ifndef __GIC_H__
+#define __GIC_H__
+
+/* Register offsets for the ARM generic interrupt controller (GIC) */
+
+#define GIC_DIST_OFFSET		0x1000
+#define GIC_CPU_OFFSET_A9	0x0100
+#define GIC_CPU_OFFSET_A15	0x2000
+
+/* Distributor Registers */
+#define GICD_CTLR		0x0000
+#define GICD_TYPER		0x0004
+#define GICD_IIDR		0x0008
+#define GICD_STATUSR		0x0010
+#define GICD_SETSPI_NSR		0x0040
+#define GICD_CLRSPI_NSR		0x0048
+#define GICD_SETSPI_SR		0x0050
+#define GICD_CLRSPI_SR		0x0058
+#define GICD_SEIR		0x0068
+#define GICD_IGROUPRn		0x0080
+#define GICD_ISENABLERn		0x0100
+#define GICD_ICENABLERn		0x0180
+#define GICD_ISPENDRn		0x0200
+#define GICD_ICPENDRn		0x0280
+#define GICD_ISACTIVERn		0x0300
+#define GICD_ICACTIVERn		0x0380
+#define GICD_IPRIORITYRn	0x0400
+#define GICD_ITARGETSRn		0x0800
+#define GICD_ICFGR		0x0c00
+#define GICD_IGROUPMODRn	0x0d00
+#define GICD_NSACRn		0x0e00
+#define GICD_SGIR		0x0f00
+#define GICD_CPENDSGIRn		0x0f10
+#define GICD_SPENDSGIRn		0x0f20
+#define GICD_IROUTERn		0x6000
+
+/* Cpu Interface Memory Mapped Registers */
+#define GICC_CTLR		0x0000
+#define GICC_PMR		0x0004
+#define GICC_BPR		0x0008
+#define GICC_IAR		0x000C
+#define GICC_EOIR		0x0010
+#define GICC_RPR		0x0014
+#define GICC_HPPIR		0x0018
+#define GICC_ABPR		0x001c
+#define GICC_AIAR		0x0020
+#define GICC_AEOIR		0x0024
+#define GICC_AHPPIR		0x0028
+#define GICC_APRn		0x00d0
+#define GICC_NSAPRn		0x00e0
+#define GICC_IIDR		0x00fc
+#define GICC_DIR		0x1000
+
+/* ReDistributor Registers for Control and Physical LPIs */
+#define GICR_CTLR		0x0000
+#define GICR_IIDR		0x0004
+#define GICR_TYPER		0x0008
+#define GICR_STATUSR		0x0010
+#define GICR_WAKER		0x0014
+#define GICR_SETLPIR		0x0040
+#define GICR_CLRLPIR		0x0048
+#define GICR_SEIR		0x0068
+#define GICR_PROPBASER		0x0070
+#define GICR_PENDBASER		0x0078
+#define GICR_INVLPIR		0x00a0
+#define GICR_INVALLR		0x00b0
+#define GICR_SYNCR		0x00c0
+#define GICR_MOVLPIR		0x0100
+#define GICR_MOVALLR		0x0110
+
+/* ReDistributor Registers for SGIs and PPIs */
+#define GICR_IGROUPRn		0x0080
+#define GICR_ISENABLERn		0x0100
+#define GICR_ICENABLERn		0x0180
+#define GICR_ISPENDRn		0x0200
+#define GICR_ICPENDRn		0x0280
+#define GICR_ISACTIVERn		0x0300
+#define GICR_ICACTIVERn		0x0380
+#define GICR_IPRIORITYRn	0x0400
+#define GICR_ICFGR0		0x0c00
+#define GICR_ICFGR1		0x0c04
+#define GICR_IGROUPMODRn	0x0d00
+#define GICR_NSACRn		0x0e00
+
+/* Cpu Interface System Registers */
+#define ICC_IAR0_EL1		S3_0_C12_C8_0
+#define ICC_IAR1_EL1		S3_0_C12_C12_0
+#define ICC_EOIR0_EL1		S3_0_C12_C8_1
+#define ICC_EOIR1_EL1		S3_0_C12_C12_1
+#define ICC_HPPIR0_EL1		S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1		S3_0_C12_C12_2
+#define ICC_BPR0_EL1		S3_0_C12_C8_3
+#define ICC_BPR1_EL1		S3_0_C12_C12_3
+#define ICC_DIR_EL1		S3_0_C12_C11_1
+#define ICC_PMR_EL1		S3_0_C4_C6_0
+#define ICC_RPR_EL1		S3_0_C12_C11_3
+#define ICC_CTLR_EL1		S3_0_C12_C12_4
+#define ICC_CTLR_EL3		S3_6_C12_C12_4
+#define ICC_SRE_EL1		S3_0_C12_C12_5
+#define ICC_SRE_EL2		S3_4_C12_C9_5
+#define ICC_SRE_EL3		S3_6_C12_C12_5
+#define ICC_IGRPEN0_EL1		S3_0_C12_C12_6
+#define ICC_IGRPEN1_EL1		S3_0_C12_C12_7
+#define ICC_IGRPEN1_EL3		S3_6_C12_C12_7
+#define ICC_SEIEN_EL1		S3_0_C12_C13_0
+#define ICC_SGI0R_EL1		S3_0_C12_C11_7
+#define ICC_SGI1R_EL1		S3_0_C12_C11_5
+#define ICC_ASGI1R_EL1		S3_0_C12_C11_6
+
+#endif /* __GIC_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/global_data.h b/qemu/roms/u-boot/arch/arm/include/asm/global_data.h
new file mode 100644
index 000000000..63e4ad5a6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/global_data.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#ifdef CONFIG_OMAP
+#include <asm/omap_boot.h>
+#endif
+
+/* Architecture-specific global data */
+struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC)
+	u32 sdhc_clk;
+#endif
+#ifdef CONFIG_AT91FAMILY
+	/* "static data" needed by at91's clock.c */
+	unsigned long	cpu_clk_rate_hz;
+	unsigned long	main_clk_rate_hz;
+	unsigned long	mck_rate_hz;
+	unsigned long	plla_rate_hz;
+	unsigned long	pllb_rate_hz;
+	unsigned long	at91_pllb_usb_init;
+#endif
+	/* "static data" needed by most of timer.c on ARM platforms */
+	unsigned long timer_rate_hz;
+	unsigned long tbu;
+	unsigned long tbl;
+	unsigned long lastinc;
+	unsigned long long timer_reset_value;
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	unsigned long tlb_addr;
+	unsigned long tlb_size;
+#endif
+
+#ifdef CONFIG_OMAP
+	struct omap_boot_parameters omap_boot_params;
+#endif
+};
+
+#include <asm-generic/global_data.h>
+
+#ifdef CONFIG_ARM64
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("x18")
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("r9")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/gpio.h
new file mode 100644
index 000000000..d49ad080e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/gpio.h
@@ -0,0 +1,2 @@
+#include <asm/arch/gpio.h>
+#include <asm-generic/gpio.h>
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/hardware.h b/qemu/roms/u-boot/arch/arm/include/asm/hardware.h
new file mode 100644
index 000000000..1fd1a5b65
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/hardware.h
@@ -0,0 +1,18 @@
+/*
+ *  linux/include/asm-arm/hardware.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Common hardware definitions
+ */
+
+#ifndef __ASM_HARDWARE_H
+#define __ASM_HARDWARE_H
+
+#include <asm/arch/hardware.h>
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/boot_mode.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/boot_mode.h
new file mode 100644
index 000000000..de0205c11
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/boot_mode.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_BOOT_MODE_H
+#define _ASM_BOOT_MODE_H
+#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
+	((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
+
+struct boot_mode {
+	const char *name;
+	unsigned cfg_val;
+};
+
+void add_board_boot_modes(const struct boot_mode *p);
+void boot_mode_apply(unsigned cfg_val);
+extern const struct boot_mode soc_boot_modes[];
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/dma.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/dma.h
new file mode 100644
index 000000000..d5c1f7f25
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/dma.h
@@ -0,0 +1,166 @@
+/*
+ * Freescale i.MX28 APBH DMA
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#include <linux/list.h>
+#include <linux/compiler.h>
+
+#ifndef	CONFIG_ARCH_DMA_PIO_WORDS
+#define	DMA_PIO_WORDS		15
+#else
+#define	DMA_PIO_WORDS		CONFIG_ARCH_DMA_PIO_WORDS
+#endif
+
+#define MXS_DMA_ALIGNMENT	32
+
+/*
+ * MXS DMA channels
+ */
+#if defined(CONFIG_MX23)
+enum {
+	MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP0,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+	MXS_MAX_DMA_CHANNELS,
+};
+#elif defined(CONFIG_MX28)
+enum {
+	MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP2,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP3,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+	MXS_DMA_CHANNEL_AHB_APBH_HSADC,
+	MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
+	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+	MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
+	MXS_MAX_DMA_CHANNELS,
+};
+#elif defined(CONFIG_MX6)
+enum {
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+	MXS_MAX_DMA_CHANNELS,
+};
+#endif
+
+/*
+ * MXS DMA hardware command.
+ *
+ * This structure describes the in-memory layout of an entire DMA command,
+ * including space for the maximum number of PIO accesses. See the appropriate
+ * reference manual for a detailed description of what these fields mean to the
+ * DMA hardware.
+ */
+#define	MXS_DMA_DESC_COMMAND_MASK	0x3
+#define	MXS_DMA_DESC_COMMAND_OFFSET	0
+#define	MXS_DMA_DESC_COMMAND_NO_DMAXFER	0x0
+#define	MXS_DMA_DESC_COMMAND_DMA_WRITE	0x1
+#define	MXS_DMA_DESC_COMMAND_DMA_READ	0x2
+#define	MXS_DMA_DESC_COMMAND_DMA_SENSE	0x3
+#define	MXS_DMA_DESC_CHAIN		(1 << 2)
+#define	MXS_DMA_DESC_IRQ		(1 << 3)
+#define	MXS_DMA_DESC_NAND_LOCK		(1 << 4)
+#define	MXS_DMA_DESC_NAND_WAIT_4_READY	(1 << 5)
+#define	MXS_DMA_DESC_DEC_SEM		(1 << 6)
+#define	MXS_DMA_DESC_WAIT4END		(1 << 7)
+#define	MXS_DMA_DESC_HALT_ON_TERMINATE	(1 << 8)
+#define	MXS_DMA_DESC_TERMINATE_FLUSH	(1 << 9)
+#define	MXS_DMA_DESC_PIO_WORDS_MASK	(0xf << 12)
+#define	MXS_DMA_DESC_PIO_WORDS_OFFSET	12
+#define	MXS_DMA_DESC_BYTES_MASK		(0xffff << 16)
+#define	MXS_DMA_DESC_BYTES_OFFSET	16
+
+struct mxs_dma_cmd {
+	unsigned long		next;
+	unsigned long		data;
+	union {
+		dma_addr_t	address;
+		unsigned long	alternate;
+	};
+	unsigned long		pio_words[DMA_PIO_WORDS];
+};
+
+/*
+ * MXS DMA command descriptor.
+ *
+ * This structure incorporates an MXS DMA hardware command structure, along
+ * with metadata.
+ */
+#define	MXS_DMA_DESC_FIRST	(1 << 0)
+#define	MXS_DMA_DESC_LAST	(1 << 1)
+#define	MXS_DMA_DESC_READY	(1 << 31)
+
+struct mxs_dma_desc {
+	struct mxs_dma_cmd	cmd;
+	unsigned int		flags;
+	dma_addr_t		address;
+	void			*buffer;
+	struct list_head	node;
+} __aligned(MXS_DMA_ALIGNMENT);
+
+/**
+ * MXS DMA channel
+ *
+ * This structure represents a single DMA channel. The MXS platform code
+ * maintains an array of these structures to represent every DMA channel in the
+ * system (see mxs_dma_channels).
+ */
+#define	MXS_DMA_FLAGS_IDLE	0
+#define	MXS_DMA_FLAGS_BUSY	(1 << 0)
+#define	MXS_DMA_FLAGS_FREE	0
+#define	MXS_DMA_FLAGS_ALLOCATED	(1 << 16)
+#define	MXS_DMA_FLAGS_VALID	(1 << 31)
+
+struct mxs_dma_chan {
+	const char *name;
+	unsigned long dev;
+	struct mxs_dma_device *dma;
+	unsigned int flags;
+	unsigned int active_num;
+	unsigned int pending_num;
+	struct list_head active;
+	struct list_head done;
+};
+
+struct mxs_dma_desc *mxs_dma_desc_alloc(void);
+void mxs_dma_desc_free(struct mxs_dma_desc *);
+int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
+
+int mxs_dma_go(int chan);
+void mxs_dma_init(void);
+int mxs_dma_init_channel(int chan);
+int mxs_dma_release(int chan);
+
+void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
+
+#endif	/* __DMA_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/gpio.h
new file mode 100644
index 000000000..26b296b21
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/gpio.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __ASM_ARCH_IMX_GPIO_H
+#define __ASM_ARCH_IMX_GPIO_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+	u32 gpio_dr;	/* data */
+	u32 gpio_dir;	/* direction */
+	u32 gpio_psr;	/* pad satus */
+};
+#endif
+
+#define IMX_GPIO_NR(port, index)		((((port)-1)*32)+((index)&31))
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/imximage.cfg b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/imximage.cfg
new file mode 100644
index 000000000..d62166fd0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/imximage.cfg
@@ -0,0 +1,24 @@
+/*
+ * i.MX image header offset values
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * NOTE: This file must be kept in sync with tools/imximage.h because
+ *       tools/imximage.c can not cross-include headers from arch/arm/
+ *       and vice-versa.
+ */
+
+#ifndef __ASM_IMX_COMMON_IMXIMAGE_CFG__
+#define __ASM_IMX_COMMON_IMXIMAGE_CFG__
+
+/* Standard image header offset for NAND, SATA, SD, SPI flash. */
+#define FLASH_OFFSET_STANDARD	0x400
+/* Specific image header offset for booting from OneNAND. */
+#define FLASH_OFFSET_ONENAND	0x100
+/* Specific image header offset for booting from memory-mapped NOR. */
+#define FLASH_OFFSET_NOR	0x1000
+
+#endif  /* __ASM_IMX_COMMON_IMXIMAGE_CFG__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/iomux-v3.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/iomux-v3.h
new file mode 100644
index 000000000..dec11a133
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -0,0 +1,173 @@
+/*
+ * Based on Linux i.MX iomux-v3.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *			<armlinux@phytec.de>
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MACH_IOMUX_V3_H__
+#define __MACH_IOMUX_V3_H__
+
+#include <common.h>
+
+/*
+ *	build IOMUX_PAD structure
+ *
+ * This iomux scheme is based around pads, which are the physical balls
+ * on the processor.
+ *
+ * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
+ *   things like driving strength and pullup/pulldown.
+ * - Each pad can have but not necessarily does have an output routing register
+ *   (IOMUXC_SW_MUX_CTL_PAD_x).
+ * - Each pad can have but not necessarily does have an input routing register
+ *   (IOMUXC_x_SELECT_INPUT)
+ *
+ * The three register sets do not have a fixed offset to each other,
+ * hence we order this table by pad control registers (which all pads
+ * have) and put the optional i/o routing registers into additional
+ * fields.
+ *
+ * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ *
+ * IOMUX/PAD Bit field definitions
+ *
+ * MUX_CTRL_OFS:	    0..11 (12)
+ * PAD_CTRL_OFS:	   12..23 (12)
+ * SEL_INPUT_OFS:	   24..35 (12)
+ * MUX_MODE + SION:	   36..40  (5)
+ * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
+ * SEL_INP:		   59..62  (4)
+ * reserved:		     63    (1)
+*/
+
+typedef u64 iomux_v3_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT	0
+#define MUX_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
+#define MUX_PAD_CTRL_OFS_SHIFT	12
+#define MUX_PAD_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << \
+	MUX_PAD_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT	24
+#define MUX_SEL_INPUT_OFS_MASK	((iomux_v3_cfg_t)0xfff << \
+	MUX_SEL_INPUT_OFS_SHIFT)
+
+#define MUX_MODE_SHIFT		36
+#define MUX_MODE_MASK		((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL_SHIFT	41
+#define MUX_PAD_CTRL_MASK	((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
+#define MUX_SEL_INPUT_SHIFT	59
+#define MUX_SEL_INPUT_MASK	((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+
+#define MUX_MODE_SION		((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
+	MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL(x)		((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,	\
+		sel_input, pad_ctrl)					\
+	(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT)     |	\
+	((iomux_v3_cfg_t)(mux_mode)      << MUX_MODE_SHIFT)         |	\
+	((iomux_v3_cfg_t)(pad_ctrl_ofs)  << MUX_PAD_CTRL_OFS_SHIFT) |	\
+	((iomux_v3_cfg_t)(pad_ctrl)      << MUX_PAD_CTRL_SHIFT)     |	\
+	((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|	\
+	((iomux_v3_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))
+
+#define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | \
+					MUX_PAD_CTRL(pad))
+
+#define __NA_			0x000
+#define NO_MUX_I		0
+#define NO_PAD_I		0
+
+#define NO_PAD_CTRL		(1 << 17)
+
+#ifdef CONFIG_MX6
+
+#define PAD_CTL_HYS		(1 << 16)
+
+#define PAD_CTL_PUS_100K_DOWN	(0 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP	(1 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP	(2 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP	(3 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUE		(1 << 13 | PAD_CTL_PKE)
+#define PAD_CTL_PKE		(1 << 12)
+
+#define PAD_CTL_ODE		(1 << 11)
+
+#define PAD_CTL_SPEED_LOW	(1 << 6)
+#define PAD_CTL_SPEED_MED	(2 << 6)
+#define PAD_CTL_SPEED_HIGH	(3 << 6)
+
+#define PAD_CTL_DSE_DISABLE	(0 << 3)
+#define PAD_CTL_DSE_240ohm	(1 << 3)
+#define PAD_CTL_DSE_120ohm	(2 << 3)
+#define PAD_CTL_DSE_80ohm	(3 << 3)
+#define PAD_CTL_DSE_60ohm	(4 << 3)
+#define PAD_CTL_DSE_48ohm	(5 << 3)
+#define PAD_CTL_DSE_40ohm	(6 << 3)
+#define PAD_CTL_DSE_34ohm	(7 << 3)
+
+#elif defined(CONFIG_VF610)
+
+#define PAD_MUX_MODE_SHIFT	20
+
+#define PAD_CTL_SPEED_MED	(1 << 12)
+#define PAD_CTL_SPEED_HIGH	(3 << 12)
+
+#define PAD_CTL_DSE_50ohm	(3 << 6)
+#define PAD_CTL_DSE_25ohm	(6 << 6)
+#define PAD_CTL_DSE_20ohm	(7 << 6)
+
+#define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PKE		(1 << 3)
+#define PAD_CTL_PUE		(1 << 2 | PAD_CTL_PKE)
+
+#define PAD_CTL_OBE_IBE_ENABLE	(3 << 0)
+
+#else
+
+#define PAD_CTL_DVS		(1 << 13)
+#define PAD_CTL_INPUT_DDR	(1 << 9)
+#define PAD_CTL_HYS		(1 << 8)
+
+#define PAD_CTL_PKE		(1 << 7)
+#define PAD_CTL_PUE		(1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN	(0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP	(3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE		(1 << 3)
+
+#define PAD_CTL_DSE_LOW		(0 << 1)
+#define PAD_CTL_DSE_MED		(1 << 1)
+#define PAD_CTL_DSE_HIGH	(2 << 1)
+#define PAD_CTL_DSE_MAX		(3 << 1)
+
+#endif
+
+#define PAD_CTL_SRE_SLOW	(0 << 0)
+#define PAD_CTL_SRE_FAST	(1 << 0)
+
+#define IOMUX_CONFIG_SION	0x10
+
+#define GPIO_PIN_MASK		0x1f
+#define GPIO_PORT_SHIFT		5
+#define GPIO_PORT_MASK		(0x7 << GPIO_PORT_SHIFT)
+#define GPIO_PORTA		(0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB		(1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC		(2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD		(3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE		(4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF		(5 << GPIO_PORT_SHIFT)
+
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+				     unsigned count);
+
+#endif	/* __MACH_IOMUX_V3_H__*/
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mx5_video.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mx5_video.h
new file mode 100644
index 000000000..ccaf010b7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mx5_video.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2012
+ * Anatolij Gustschin, DENX Software Engineering, <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __MX5_VIDEO_H
+#define __MX5_VIDEO_H
+
+#ifdef CONFIG_VIDEO
+void lcd_enable(void);
+void setup_iomux_lcd(void);
+#else
+static inline void lcd_enable(void) { }
+static inline void setup_iomux_lcd(void) { }
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mxc_i2c.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mxc_i2c.h
new file mode 100644
index 000000000..47a9edc81
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/mxc_i2c.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARCH_MXC_MXC_I2C_H__
+#define __ASM_ARCH_MXC_MXC_I2C_H__
+#include <asm/imx-common/iomux-v3.h>
+
+struct i2c_pin_ctrl {
+	iomux_v3_cfg_t i2c_mode;
+	iomux_v3_cfg_t gpio_mode;
+	unsigned char gp;
+	unsigned char spare;
+};
+
+struct i2c_pads_info {
+	struct i2c_pin_ctrl scl;
+	struct i2c_pin_ctrl sda;
+};
+
+void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+		struct i2c_pads_info *p);
+void bus_i2c_init(void *base, int speed, int slave_addr,
+		int (*idle_bus_fn)(void *p), void *p);
+int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
+		int len);
+int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
+		const uchar *buf, int len);
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-apbh.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-apbh.h
new file mode 100644
index 000000000..ca7743600
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-apbh.h
@@ -0,0 +1,589 @@
+/*
+ * Freescale i.MX28 APBH Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __REGS_APBH_H__
+#define __REGS_APBH_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+
+#if defined(CONFIG_MX23)
+struct mxs_apbh_regs {
+	mxs_reg_32(hw_apbh_ctrl0)
+	mxs_reg_32(hw_apbh_ctrl1)
+	mxs_reg_32(hw_apbh_ctrl2)
+	mxs_reg_32(hw_apbh_channel_ctrl)
+
+	union {
+	struct {
+		mxs_reg_32(hw_apbh_ch_curcmdar)
+		mxs_reg_32(hw_apbh_ch_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch_cmd)
+		mxs_reg_32(hw_apbh_ch_bar)
+		mxs_reg_32(hw_apbh_ch_sema)
+		mxs_reg_32(hw_apbh_ch_debug1)
+		mxs_reg_32(hw_apbh_ch_debug2)
+	} ch[8];
+	struct {
+		mxs_reg_32(hw_apbh_ch0_curcmdar)
+		mxs_reg_32(hw_apbh_ch0_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch0_cmd)
+		mxs_reg_32(hw_apbh_ch0_bar)
+		mxs_reg_32(hw_apbh_ch0_sema)
+		mxs_reg_32(hw_apbh_ch0_debug1)
+		mxs_reg_32(hw_apbh_ch0_debug2)
+		mxs_reg_32(hw_apbh_ch1_curcmdar)
+		mxs_reg_32(hw_apbh_ch1_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch1_cmd)
+		mxs_reg_32(hw_apbh_ch1_bar)
+		mxs_reg_32(hw_apbh_ch1_sema)
+		mxs_reg_32(hw_apbh_ch1_debug1)
+		mxs_reg_32(hw_apbh_ch1_debug2)
+		mxs_reg_32(hw_apbh_ch2_curcmdar)
+		mxs_reg_32(hw_apbh_ch2_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch2_cmd)
+		mxs_reg_32(hw_apbh_ch2_bar)
+		mxs_reg_32(hw_apbh_ch2_sema)
+		mxs_reg_32(hw_apbh_ch2_debug1)
+		mxs_reg_32(hw_apbh_ch2_debug2)
+		mxs_reg_32(hw_apbh_ch3_curcmdar)
+		mxs_reg_32(hw_apbh_ch3_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch3_cmd)
+		mxs_reg_32(hw_apbh_ch3_bar)
+		mxs_reg_32(hw_apbh_ch3_sema)
+		mxs_reg_32(hw_apbh_ch3_debug1)
+		mxs_reg_32(hw_apbh_ch3_debug2)
+		mxs_reg_32(hw_apbh_ch4_curcmdar)
+		mxs_reg_32(hw_apbh_ch4_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch4_cmd)
+		mxs_reg_32(hw_apbh_ch4_bar)
+		mxs_reg_32(hw_apbh_ch4_sema)
+		mxs_reg_32(hw_apbh_ch4_debug1)
+		mxs_reg_32(hw_apbh_ch4_debug2)
+		mxs_reg_32(hw_apbh_ch5_curcmdar)
+		mxs_reg_32(hw_apbh_ch5_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch5_cmd)
+		mxs_reg_32(hw_apbh_ch5_bar)
+		mxs_reg_32(hw_apbh_ch5_sema)
+		mxs_reg_32(hw_apbh_ch5_debug1)
+		mxs_reg_32(hw_apbh_ch5_debug2)
+		mxs_reg_32(hw_apbh_ch6_curcmdar)
+		mxs_reg_32(hw_apbh_ch6_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch6_cmd)
+		mxs_reg_32(hw_apbh_ch6_bar)
+		mxs_reg_32(hw_apbh_ch6_sema)
+		mxs_reg_32(hw_apbh_ch6_debug1)
+		mxs_reg_32(hw_apbh_ch6_debug2)
+		mxs_reg_32(hw_apbh_ch7_curcmdar)
+		mxs_reg_32(hw_apbh_ch7_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch7_cmd)
+		mxs_reg_32(hw_apbh_ch7_bar)
+		mxs_reg_32(hw_apbh_ch7_sema)
+		mxs_reg_32(hw_apbh_ch7_debug1)
+		mxs_reg_32(hw_apbh_ch7_debug2)
+	};
+	};
+	mxs_reg_32(hw_apbh_version)
+};
+
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
+struct mxs_apbh_regs {
+	mxs_reg_32(hw_apbh_ctrl0)
+	mxs_reg_32(hw_apbh_ctrl1)
+	mxs_reg_32(hw_apbh_ctrl2)
+	mxs_reg_32(hw_apbh_channel_ctrl)
+	mxs_reg_32(hw_apbh_devsel)
+	mxs_reg_32(hw_apbh_dma_burst_size)
+	mxs_reg_32(hw_apbh_debug)
+
+	uint32_t	reserved[36];
+
+	union {
+	struct {
+		mxs_reg_32(hw_apbh_ch_curcmdar)
+		mxs_reg_32(hw_apbh_ch_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch_cmd)
+		mxs_reg_32(hw_apbh_ch_bar)
+		mxs_reg_32(hw_apbh_ch_sema)
+		mxs_reg_32(hw_apbh_ch_debug1)
+		mxs_reg_32(hw_apbh_ch_debug2)
+	} ch[16];
+	struct {
+		mxs_reg_32(hw_apbh_ch0_curcmdar)
+		mxs_reg_32(hw_apbh_ch0_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch0_cmd)
+		mxs_reg_32(hw_apbh_ch0_bar)
+		mxs_reg_32(hw_apbh_ch0_sema)
+		mxs_reg_32(hw_apbh_ch0_debug1)
+		mxs_reg_32(hw_apbh_ch0_debug2)
+		mxs_reg_32(hw_apbh_ch1_curcmdar)
+		mxs_reg_32(hw_apbh_ch1_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch1_cmd)
+		mxs_reg_32(hw_apbh_ch1_bar)
+		mxs_reg_32(hw_apbh_ch1_sema)
+		mxs_reg_32(hw_apbh_ch1_debug1)
+		mxs_reg_32(hw_apbh_ch1_debug2)
+		mxs_reg_32(hw_apbh_ch2_curcmdar)
+		mxs_reg_32(hw_apbh_ch2_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch2_cmd)
+		mxs_reg_32(hw_apbh_ch2_bar)
+		mxs_reg_32(hw_apbh_ch2_sema)
+		mxs_reg_32(hw_apbh_ch2_debug1)
+		mxs_reg_32(hw_apbh_ch2_debug2)
+		mxs_reg_32(hw_apbh_ch3_curcmdar)
+		mxs_reg_32(hw_apbh_ch3_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch3_cmd)
+		mxs_reg_32(hw_apbh_ch3_bar)
+		mxs_reg_32(hw_apbh_ch3_sema)
+		mxs_reg_32(hw_apbh_ch3_debug1)
+		mxs_reg_32(hw_apbh_ch3_debug2)
+		mxs_reg_32(hw_apbh_ch4_curcmdar)
+		mxs_reg_32(hw_apbh_ch4_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch4_cmd)
+		mxs_reg_32(hw_apbh_ch4_bar)
+		mxs_reg_32(hw_apbh_ch4_sema)
+		mxs_reg_32(hw_apbh_ch4_debug1)
+		mxs_reg_32(hw_apbh_ch4_debug2)
+		mxs_reg_32(hw_apbh_ch5_curcmdar)
+		mxs_reg_32(hw_apbh_ch5_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch5_cmd)
+		mxs_reg_32(hw_apbh_ch5_bar)
+		mxs_reg_32(hw_apbh_ch5_sema)
+		mxs_reg_32(hw_apbh_ch5_debug1)
+		mxs_reg_32(hw_apbh_ch5_debug2)
+		mxs_reg_32(hw_apbh_ch6_curcmdar)
+		mxs_reg_32(hw_apbh_ch6_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch6_cmd)
+		mxs_reg_32(hw_apbh_ch6_bar)
+		mxs_reg_32(hw_apbh_ch6_sema)
+		mxs_reg_32(hw_apbh_ch6_debug1)
+		mxs_reg_32(hw_apbh_ch6_debug2)
+		mxs_reg_32(hw_apbh_ch7_curcmdar)
+		mxs_reg_32(hw_apbh_ch7_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch7_cmd)
+		mxs_reg_32(hw_apbh_ch7_bar)
+		mxs_reg_32(hw_apbh_ch7_sema)
+		mxs_reg_32(hw_apbh_ch7_debug1)
+		mxs_reg_32(hw_apbh_ch7_debug2)
+		mxs_reg_32(hw_apbh_ch8_curcmdar)
+		mxs_reg_32(hw_apbh_ch8_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch8_cmd)
+		mxs_reg_32(hw_apbh_ch8_bar)
+		mxs_reg_32(hw_apbh_ch8_sema)
+		mxs_reg_32(hw_apbh_ch8_debug1)
+		mxs_reg_32(hw_apbh_ch8_debug2)
+		mxs_reg_32(hw_apbh_ch9_curcmdar)
+		mxs_reg_32(hw_apbh_ch9_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch9_cmd)
+		mxs_reg_32(hw_apbh_ch9_bar)
+		mxs_reg_32(hw_apbh_ch9_sema)
+		mxs_reg_32(hw_apbh_ch9_debug1)
+		mxs_reg_32(hw_apbh_ch9_debug2)
+		mxs_reg_32(hw_apbh_ch10_curcmdar)
+		mxs_reg_32(hw_apbh_ch10_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch10_cmd)
+		mxs_reg_32(hw_apbh_ch10_bar)
+		mxs_reg_32(hw_apbh_ch10_sema)
+		mxs_reg_32(hw_apbh_ch10_debug1)
+		mxs_reg_32(hw_apbh_ch10_debug2)
+		mxs_reg_32(hw_apbh_ch11_curcmdar)
+		mxs_reg_32(hw_apbh_ch11_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch11_cmd)
+		mxs_reg_32(hw_apbh_ch11_bar)
+		mxs_reg_32(hw_apbh_ch11_sema)
+		mxs_reg_32(hw_apbh_ch11_debug1)
+		mxs_reg_32(hw_apbh_ch11_debug2)
+		mxs_reg_32(hw_apbh_ch12_curcmdar)
+		mxs_reg_32(hw_apbh_ch12_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch12_cmd)
+		mxs_reg_32(hw_apbh_ch12_bar)
+		mxs_reg_32(hw_apbh_ch12_sema)
+		mxs_reg_32(hw_apbh_ch12_debug1)
+		mxs_reg_32(hw_apbh_ch12_debug2)
+		mxs_reg_32(hw_apbh_ch13_curcmdar)
+		mxs_reg_32(hw_apbh_ch13_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch13_cmd)
+		mxs_reg_32(hw_apbh_ch13_bar)
+		mxs_reg_32(hw_apbh_ch13_sema)
+		mxs_reg_32(hw_apbh_ch13_debug1)
+		mxs_reg_32(hw_apbh_ch13_debug2)
+		mxs_reg_32(hw_apbh_ch14_curcmdar)
+		mxs_reg_32(hw_apbh_ch14_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch14_cmd)
+		mxs_reg_32(hw_apbh_ch14_bar)
+		mxs_reg_32(hw_apbh_ch14_sema)
+		mxs_reg_32(hw_apbh_ch14_debug1)
+		mxs_reg_32(hw_apbh_ch14_debug2)
+		mxs_reg_32(hw_apbh_ch15_curcmdar)
+		mxs_reg_32(hw_apbh_ch15_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch15_cmd)
+		mxs_reg_32(hw_apbh_ch15_bar)
+		mxs_reg_32(hw_apbh_ch15_sema)
+		mxs_reg_32(hw_apbh_ch15_debug1)
+		mxs_reg_32(hw_apbh_ch15_debug2)
+	};
+	};
+	mxs_reg_32(hw_apbh_version)
+};
+#endif
+
+#endif
+
+#define	APBH_CTRL0_SFTRST				(1 << 31)
+#define	APBH_CTRL0_CLKGATE				(1 << 30)
+#define	APBH_CTRL0_AHB_BURST8_EN			(1 << 29)
+#define	APBH_CTRL0_APB_BURST_EN				(1 << 28)
+#if defined(CONFIG_MX23)
+#define	APBH_CTRL0_RSVD0_MASK				(0xf << 24)
+#define	APBH_CTRL0_RSVD0_OFFSET				24
+#define	APBH_CTRL0_RESET_CHANNEL_MASK			(0xff << 16)
+#define	APBH_CTRL0_RESET_CHANNEL_OFFSET			16
+#define	APBH_CTRL0_CLKGATE_CHANNEL_MASK			(0xff << 8)
+#define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		8
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP0			0x02
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP1			0x04
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x10
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x20
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND2		0x40
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND3		0x80
+#elif defined(CONFIG_MX28)
+#define	APBH_CTRL0_RSVD0_MASK				(0xfff << 16)
+#define	APBH_CTRL0_RSVD0_OFFSET				16
+#define	APBH_CTRL0_CLKGATE_CHANNEL_MASK			0xffff
+#define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		0
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP0			0x0001
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP1			0x0002
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP2			0x0004
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP3			0x0008
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x0010
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x0020
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND2		0x0040
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND3		0x0080
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND4		0x0100
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND5		0x0200
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND6		0x0400
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND7		0x0800
+#define	APBH_CTRL0_CLKGATE_CHANNEL_HSADC		0x1000
+#define	APBH_CTRL0_CLKGATE_CHANNEL_LCDIF		0x2000
+#elif defined(CONFIG_MX6)
+#define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		0
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x0001
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x0002
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND2		0x0004
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND3		0x0008
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND4		0x0010
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND5		0x0020
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND6		0x0040
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND7		0x0080
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP			0x0100
+#endif
+
+#define	APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN			(1 << 31)
+#define	APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN			(1 << 30)
+#define	APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN			(1 << 29)
+#define	APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN			(1 << 28)
+#define	APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN			(1 << 27)
+#define	APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN			(1 << 26)
+#define	APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN			(1 << 25)
+#define	APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN			(1 << 24)
+#define	APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN			(1 << 23)
+#define	APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN			(1 << 22)
+#define	APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN			(1 << 21)
+#define	APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN			(1 << 20)
+#define	APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN			(1 << 19)
+#define	APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN			(1 << 18)
+#define	APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN			(1 << 17)
+#define	APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN			(1 << 16)
+#define	APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET		16
+#define	APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK		(0xffff << 16)
+#define	APBH_CTRL1_CH15_CMDCMPLT_IRQ			(1 << 15)
+#define	APBH_CTRL1_CH14_CMDCMPLT_IRQ			(1 << 14)
+#define	APBH_CTRL1_CH13_CMDCMPLT_IRQ			(1 << 13)
+#define	APBH_CTRL1_CH12_CMDCMPLT_IRQ			(1 << 12)
+#define	APBH_CTRL1_CH11_CMDCMPLT_IRQ			(1 << 11)
+#define	APBH_CTRL1_CH10_CMDCMPLT_IRQ			(1 << 10)
+#define	APBH_CTRL1_CH9_CMDCMPLT_IRQ			(1 << 9)
+#define	APBH_CTRL1_CH8_CMDCMPLT_IRQ			(1 << 8)
+#define	APBH_CTRL1_CH7_CMDCMPLT_IRQ			(1 << 7)
+#define	APBH_CTRL1_CH6_CMDCMPLT_IRQ			(1 << 6)
+#define	APBH_CTRL1_CH5_CMDCMPLT_IRQ			(1 << 5)
+#define	APBH_CTRL1_CH4_CMDCMPLT_IRQ			(1 << 4)
+#define	APBH_CTRL1_CH3_CMDCMPLT_IRQ			(1 << 3)
+#define	APBH_CTRL1_CH2_CMDCMPLT_IRQ			(1 << 2)
+#define	APBH_CTRL1_CH1_CMDCMPLT_IRQ			(1 << 1)
+#define	APBH_CTRL1_CH0_CMDCMPLT_IRQ			(1 << 0)
+
+#define	APBH_CTRL2_CH15_ERROR_STATUS			(1 << 31)
+#define	APBH_CTRL2_CH14_ERROR_STATUS			(1 << 30)
+#define	APBH_CTRL2_CH13_ERROR_STATUS			(1 << 29)
+#define	APBH_CTRL2_CH12_ERROR_STATUS			(1 << 28)
+#define	APBH_CTRL2_CH11_ERROR_STATUS			(1 << 27)
+#define	APBH_CTRL2_CH10_ERROR_STATUS			(1 << 26)
+#define	APBH_CTRL2_CH9_ERROR_STATUS			(1 << 25)
+#define	APBH_CTRL2_CH8_ERROR_STATUS			(1 << 24)
+#define	APBH_CTRL2_CH7_ERROR_STATUS			(1 << 23)
+#define	APBH_CTRL2_CH6_ERROR_STATUS			(1 << 22)
+#define	APBH_CTRL2_CH5_ERROR_STATUS			(1 << 21)
+#define	APBH_CTRL2_CH4_ERROR_STATUS			(1 << 20)
+#define	APBH_CTRL2_CH3_ERROR_STATUS			(1 << 19)
+#define	APBH_CTRL2_CH2_ERROR_STATUS			(1 << 18)
+#define	APBH_CTRL2_CH1_ERROR_STATUS			(1 << 17)
+#define	APBH_CTRL2_CH0_ERROR_STATUS			(1 << 16)
+#define	APBH_CTRL2_CH15_ERROR_IRQ			(1 << 15)
+#define	APBH_CTRL2_CH14_ERROR_IRQ			(1 << 14)
+#define	APBH_CTRL2_CH13_ERROR_IRQ			(1 << 13)
+#define	APBH_CTRL2_CH12_ERROR_IRQ			(1 << 12)
+#define	APBH_CTRL2_CH11_ERROR_IRQ			(1 << 11)
+#define	APBH_CTRL2_CH10_ERROR_IRQ			(1 << 10)
+#define	APBH_CTRL2_CH9_ERROR_IRQ			(1 << 9)
+#define	APBH_CTRL2_CH8_ERROR_IRQ			(1 << 8)
+#define	APBH_CTRL2_CH7_ERROR_IRQ			(1 << 7)
+#define	APBH_CTRL2_CH6_ERROR_IRQ			(1 << 6)
+#define	APBH_CTRL2_CH5_ERROR_IRQ			(1 << 5)
+#define	APBH_CTRL2_CH4_ERROR_IRQ			(1 << 4)
+#define	APBH_CTRL2_CH3_ERROR_IRQ			(1 << 3)
+#define	APBH_CTRL2_CH2_ERROR_IRQ			(1 << 2)
+#define	APBH_CTRL2_CH1_ERROR_IRQ			(1 << 1)
+#define	APBH_CTRL2_CH0_ERROR_IRQ			(1 << 0)
+
+#if defined(CONFIG_MX28)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK		(0xffff << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET		16
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0		(0x0001 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1		(0x0002 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2		(0x0004 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3		(0x0008 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0		(0x0010 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1		(0x0020 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2		(0x0040 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3		(0x0080 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4		(0x0100 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5		(0x0200 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6		(0x0400 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7		(0x0800 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC		(0x1000 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF		(0x2000 << 16)
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK		0xffff
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET		0
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0		0x0001
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1		0x0002
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2		0x0004
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3		0x0008
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0		0x0010
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1		0x0020
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2		0x0040
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3		0x0080
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4		0x0100
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5		0x0200
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6		0x0400
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7		0x0800
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC		0x1000
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF		0x2000
+#endif
+
+#if defined(CONFIG_MX6)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET		16
+#endif
+
+#if defined(CONFIG_MX23)
+#define	APBH_DEVSEL_CH7_MASK				(0xf << 28)
+#define	APBH_DEVSEL_CH7_OFFSET				28
+#define	APBH_DEVSEL_CH6_MASK				(0xf << 24)
+#define	APBH_DEVSEL_CH6_OFFSET				24
+#define	APBH_DEVSEL_CH5_MASK				(0xf << 20)
+#define	APBH_DEVSEL_CH5_OFFSET				20
+#define	APBH_DEVSEL_CH4_MASK				(0xf << 16)
+#define	APBH_DEVSEL_CH4_OFFSET				16
+#define	APBH_DEVSEL_CH3_MASK				(0xf << 12)
+#define	APBH_DEVSEL_CH3_OFFSET				12
+#define	APBH_DEVSEL_CH2_MASK				(0xf << 8)
+#define	APBH_DEVSEL_CH2_OFFSET				8
+#define	APBH_DEVSEL_CH1_MASK				(0xf << 4)
+#define	APBH_DEVSEL_CH1_OFFSET				4
+#define	APBH_DEVSEL_CH0_MASK				(0xf << 0)
+#define	APBH_DEVSEL_CH0_OFFSET				0
+#elif defined(CONFIG_MX28)
+#define	APBH_DEVSEL_CH15_MASK				(0x3 << 30)
+#define	APBH_DEVSEL_CH15_OFFSET				30
+#define	APBH_DEVSEL_CH14_MASK				(0x3 << 28)
+#define	APBH_DEVSEL_CH14_OFFSET				28
+#define	APBH_DEVSEL_CH13_MASK				(0x3 << 26)
+#define	APBH_DEVSEL_CH13_OFFSET				26
+#define	APBH_DEVSEL_CH12_MASK				(0x3 << 24)
+#define	APBH_DEVSEL_CH12_OFFSET				24
+#define	APBH_DEVSEL_CH11_MASK				(0x3 << 22)
+#define	APBH_DEVSEL_CH11_OFFSET				22
+#define	APBH_DEVSEL_CH10_MASK				(0x3 << 20)
+#define	APBH_DEVSEL_CH10_OFFSET				20
+#define	APBH_DEVSEL_CH9_MASK				(0x3 << 18)
+#define	APBH_DEVSEL_CH9_OFFSET				18
+#define	APBH_DEVSEL_CH8_MASK				(0x3 << 16)
+#define	APBH_DEVSEL_CH8_OFFSET				16
+#define	APBH_DEVSEL_CH7_MASK				(0x3 << 14)
+#define	APBH_DEVSEL_CH7_OFFSET				14
+#define	APBH_DEVSEL_CH6_MASK				(0x3 << 12)
+#define	APBH_DEVSEL_CH6_OFFSET				12
+#define	APBH_DEVSEL_CH5_MASK				(0x3 << 10)
+#define	APBH_DEVSEL_CH5_OFFSET				10
+#define	APBH_DEVSEL_CH4_MASK				(0x3 << 8)
+#define	APBH_DEVSEL_CH4_OFFSET				8
+#define	APBH_DEVSEL_CH3_MASK				(0x3 << 6)
+#define	APBH_DEVSEL_CH3_OFFSET				6
+#define	APBH_DEVSEL_CH2_MASK				(0x3 << 4)
+#define	APBH_DEVSEL_CH2_OFFSET				4
+#define	APBH_DEVSEL_CH1_MASK				(0x3 << 2)
+#define	APBH_DEVSEL_CH1_OFFSET				2
+#define	APBH_DEVSEL_CH0_MASK				(0x3 << 0)
+#define	APBH_DEVSEL_CH0_OFFSET				0
+#endif
+
+#if defined(CONFIG_MX28)
+#define	APBH_DMA_BURST_SIZE_CH15_MASK			(0x3 << 30)
+#define	APBH_DMA_BURST_SIZE_CH15_OFFSET			30
+#define	APBH_DMA_BURST_SIZE_CH14_MASK			(0x3 << 28)
+#define	APBH_DMA_BURST_SIZE_CH14_OFFSET			28
+#define	APBH_DMA_BURST_SIZE_CH13_MASK			(0x3 << 26)
+#define	APBH_DMA_BURST_SIZE_CH13_OFFSET			26
+#define	APBH_DMA_BURST_SIZE_CH12_MASK			(0x3 << 24)
+#define	APBH_DMA_BURST_SIZE_CH12_OFFSET			24
+#define	APBH_DMA_BURST_SIZE_CH11_MASK			(0x3 << 22)
+#define	APBH_DMA_BURST_SIZE_CH11_OFFSET			22
+#define	APBH_DMA_BURST_SIZE_CH10_MASK			(0x3 << 20)
+#define	APBH_DMA_BURST_SIZE_CH10_OFFSET			20
+#define	APBH_DMA_BURST_SIZE_CH9_MASK			(0x3 << 18)
+#define	APBH_DMA_BURST_SIZE_CH9_OFFSET			18
+#define	APBH_DMA_BURST_SIZE_CH8_MASK			(0x3 << 16)
+#define	APBH_DMA_BURST_SIZE_CH8_OFFSET			16
+#define	APBH_DMA_BURST_SIZE_CH8_BURST0			(0x0 << 16)
+#define	APBH_DMA_BURST_SIZE_CH8_BURST4			(0x1 << 16)
+#define	APBH_DMA_BURST_SIZE_CH8_BURST8			(0x2 << 16)
+#define	APBH_DMA_BURST_SIZE_CH7_MASK			(0x3 << 14)
+#define	APBH_DMA_BURST_SIZE_CH7_OFFSET			14
+#define	APBH_DMA_BURST_SIZE_CH6_MASK			(0x3 << 12)
+#define	APBH_DMA_BURST_SIZE_CH6_OFFSET			12
+#define	APBH_DMA_BURST_SIZE_CH5_MASK			(0x3 << 10)
+#define	APBH_DMA_BURST_SIZE_CH5_OFFSET			10
+#define	APBH_DMA_BURST_SIZE_CH4_MASK			(0x3 << 8)
+#define	APBH_DMA_BURST_SIZE_CH4_OFFSET			8
+#define	APBH_DMA_BURST_SIZE_CH3_MASK			(0x3 << 6)
+#define	APBH_DMA_BURST_SIZE_CH3_OFFSET			6
+#define	APBH_DMA_BURST_SIZE_CH3_BURST0			(0x0 << 6)
+#define	APBH_DMA_BURST_SIZE_CH3_BURST4			(0x1 << 6)
+#define	APBH_DMA_BURST_SIZE_CH3_BURST8			(0x2 << 6)
+
+#define	APBH_DMA_BURST_SIZE_CH2_MASK			(0x3 << 4)
+#define	APBH_DMA_BURST_SIZE_CH2_OFFSET			4
+#define	APBH_DMA_BURST_SIZE_CH2_BURST0			(0x0 << 4)
+#define	APBH_DMA_BURST_SIZE_CH2_BURST4			(0x1 << 4)
+#define	APBH_DMA_BURST_SIZE_CH2_BURST8			(0x2 << 4)
+#define	APBH_DMA_BURST_SIZE_CH1_MASK			(0x3 << 2)
+#define	APBH_DMA_BURST_SIZE_CH1_OFFSET			2
+#define	APBH_DMA_BURST_SIZE_CH1_BURST0			(0x0 << 2)
+#define	APBH_DMA_BURST_SIZE_CH1_BURST4			(0x1 << 2)
+#define	APBH_DMA_BURST_SIZE_CH1_BURST8			(0x2 << 2)
+
+#define	APBH_DMA_BURST_SIZE_CH0_MASK			0x3
+#define	APBH_DMA_BURST_SIZE_CH0_OFFSET			0
+#define	APBH_DMA_BURST_SIZE_CH0_BURST0			0x0
+#define	APBH_DMA_BURST_SIZE_CH0_BURST4			0x1
+#define	APBH_DMA_BURST_SIZE_CH0_BURST8			0x2
+
+#define	APBH_DEBUG_GPMI_ONE_FIFO			(1 << 0)
+#endif
+
+#define	APBH_CHn_CURCMDAR_CMD_ADDR_MASK			0xffffffff
+#define	APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET		0
+
+#define	APBH_CHn_NXTCMDAR_CMD_ADDR_MASK			0xffffffff
+#define	APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET		0
+
+#define	APBH_CHn_CMD_XFER_COUNT_MASK			(0xffff << 16)
+#define	APBH_CHn_CMD_XFER_COUNT_OFFSET			16
+#define	APBH_CHn_CMD_CMDWORDS_MASK			(0xf << 12)
+#define	APBH_CHn_CMD_CMDWORDS_OFFSET			12
+#define	APBH_CHn_CMD_HALTONTERMINATE			(1 << 8)
+#define	APBH_CHn_CMD_WAIT4ENDCMD			(1 << 7)
+#define	APBH_CHn_CMD_SEMAPHORE				(1 << 6)
+#define	APBH_CHn_CMD_NANDWAIT4READY			(1 << 5)
+#define	APBH_CHn_CMD_NANDLOCK				(1 << 4)
+#define	APBH_CHn_CMD_IRQONCMPLT				(1 << 3)
+#define	APBH_CHn_CMD_CHAIN				(1 << 2)
+#define	APBH_CHn_CMD_COMMAND_MASK			0x3
+#define	APBH_CHn_CMD_COMMAND_OFFSET			0
+#define	APBH_CHn_CMD_COMMAND_NO_DMA_XFER		0x0
+#define	APBH_CHn_CMD_COMMAND_DMA_WRITE			0x1
+#define	APBH_CHn_CMD_COMMAND_DMA_READ			0x2
+#define	APBH_CHn_CMD_COMMAND_DMA_SENSE			0x3
+
+#define	APBH_CHn_BAR_ADDRESS_MASK			0xffffffff
+#define	APBH_CHn_BAR_ADDRESS_OFFSET			0
+
+#define	APBH_CHn_SEMA_RSVD2_MASK			(0xff << 24)
+#define	APBH_CHn_SEMA_RSVD2_OFFSET			24
+#define	APBH_CHn_SEMA_PHORE_MASK			(0xff << 16)
+#define	APBH_CHn_SEMA_PHORE_OFFSET			16
+#define	APBH_CHn_SEMA_RSVD1_MASK			(0xff << 8)
+#define	APBH_CHn_SEMA_RSVD1_OFFSET			8
+#define	APBH_CHn_SEMA_INCREMENT_SEMA_MASK		(0xff << 0)
+#define	APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET		0
+
+#define	APBH_CHn_DEBUG1_REQ				(1 << 31)
+#define	APBH_CHn_DEBUG1_BURST				(1 << 30)
+#define	APBH_CHn_DEBUG1_KICK				(1 << 29)
+#define	APBH_CHn_DEBUG1_END				(1 << 28)
+#define	APBH_CHn_DEBUG1_SENSE				(1 << 27)
+#define	APBH_CHn_DEBUG1_READY				(1 << 26)
+#define	APBH_CHn_DEBUG1_LOCK				(1 << 25)
+#define	APBH_CHn_DEBUG1_NEXTCMDADDRVALID		(1 << 24)
+#define	APBH_CHn_DEBUG1_RD_FIFO_EMPTY			(1 << 23)
+#define	APBH_CHn_DEBUG1_RD_FIFO_FULL			(1 << 22)
+#define	APBH_CHn_DEBUG1_WR_FIFO_EMPTY			(1 << 21)
+#define	APBH_CHn_DEBUG1_WR_FIFO_FULL			(1 << 20)
+#define	APBH_CHn_DEBUG1_RSVD1_MASK			(0x7fff << 5)
+#define	APBH_CHn_DEBUG1_RSVD1_OFFSET			5
+#define	APBH_CHn_DEBUG1_STATEMACHINE_MASK		0x1f
+#define	APBH_CHn_DEBUG1_STATEMACHINE_OFFSET		0
+#define	APBH_CHn_DEBUG1_STATEMACHINE_IDLE		0x00
+#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1		0x01
+#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3		0x02
+#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2		0x03
+#define	APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE	0x04
+#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT		0x05
+#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4		0x06
+#define	APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ		0x07
+#define	APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH		0x08
+#define	APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT		0x09
+#define	APBH_CHn_DEBUG1_STATEMACHINE_WRITE		0x0c
+#define	APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ		0x0d
+#define	APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN	0x0e
+#define	APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE	0x0f
+#define	APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE		0x14
+#define	APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END		0x15
+#define	APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT		0x1c
+#define	APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM	0x1d
+#define	APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT		0x1e
+#define	APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY		0x1f
+
+#define	APBH_CHn_DEBUG2_APB_BYTES_MASK			(0xffff << 16)
+#define	APBH_CHn_DEBUG2_APB_BYTES_OFFSET		16
+#define	APBH_CHn_DEBUG2_AHB_BYTES_MASK			0xffff
+#define	APBH_CHn_DEBUG2_AHB_BYTES_OFFSET		0
+
+#define	APBH_VERSION_MAJOR_MASK				(0xff << 24)
+#define	APBH_VERSION_MAJOR_OFFSET			24
+#define	APBH_VERSION_MINOR_MASK				(0xff << 16)
+#define	APBH_VERSION_MINOR_OFFSET			16
+#define	APBH_VERSION_STEP_MASK				0xffff
+#define	APBH_VERSION_STEP_OFFSET			0
+
+#endif	/* __REGS_APBH_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-bch.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-bch.h
new file mode 100644
index 000000000..a33d3419b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-bch.h
@@ -0,0 +1,227 @@
+/*
+ * Freescale i.MX28 BCH Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_BCH_H__
+#define __MX28_REGS_BCH_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_bch_regs {
+	mxs_reg_32(hw_bch_ctrl)
+	mxs_reg_32(hw_bch_status0)
+	mxs_reg_32(hw_bch_mode)
+	mxs_reg_32(hw_bch_encodeptr)
+	mxs_reg_32(hw_bch_dataptr)
+	mxs_reg_32(hw_bch_metaptr)
+
+	uint32_t	reserved[4];
+
+	mxs_reg_32(hw_bch_layoutselect)
+	mxs_reg_32(hw_bch_flash0layout0)
+	mxs_reg_32(hw_bch_flash0layout1)
+	mxs_reg_32(hw_bch_flash1layout0)
+	mxs_reg_32(hw_bch_flash1layout1)
+	mxs_reg_32(hw_bch_flash2layout0)
+	mxs_reg_32(hw_bch_flash2layout1)
+	mxs_reg_32(hw_bch_flash3layout0)
+	mxs_reg_32(hw_bch_flash3layout1)
+	mxs_reg_32(hw_bch_dbgkesread)
+	mxs_reg_32(hw_bch_dbgcsferead)
+	mxs_reg_32(hw_bch_dbgsyndegread)
+	mxs_reg_32(hw_bch_dbgahbmread)
+	mxs_reg_32(hw_bch_blockname)
+	mxs_reg_32(hw_bch_version)
+};
+#endif
+
+#define	BCH_CTRL_SFTRST					(1 << 31)
+#define	BCH_CTRL_CLKGATE				(1 << 30)
+#define	BCH_CTRL_DEBUGSYNDROME				(1 << 22)
+#define	BCH_CTRL_M2M_LAYOUT_MASK			(0x3 << 18)
+#define	BCH_CTRL_M2M_LAYOUT_OFFSET			18
+#define	BCH_CTRL_M2M_ENCODE				(1 << 17)
+#define	BCH_CTRL_M2M_ENABLE				(1 << 16)
+#define	BCH_CTRL_DEBUG_STALL_IRQ_EN			(1 << 10)
+#define	BCH_CTRL_COMPLETE_IRQ_EN			(1 << 8)
+#define	BCH_CTRL_BM_ERROR_IRQ				(1 << 3)
+#define	BCH_CTRL_DEBUG_STALL_IRQ			(1 << 2)
+#define	BCH_CTRL_COMPLETE_IRQ				(1 << 0)
+
+#define	BCH_STATUS0_HANDLE_MASK				(0xfff << 20)
+#define	BCH_STATUS0_HANDLE_OFFSET			20
+#define	BCH_STATUS0_COMPLETED_CE_MASK			(0xf << 16)
+#define	BCH_STATUS0_COMPLETED_CE_OFFSET			16
+#define	BCH_STATUS0_STATUS_BLK0_MASK			(0xff << 8)
+#define	BCH_STATUS0_STATUS_BLK0_OFFSET			8
+#define	BCH_STATUS0_STATUS_BLK0_ZERO			(0x00 << 8)
+#define	BCH_STATUS0_STATUS_BLK0_ERROR1			(0x01 << 8)
+#define	BCH_STATUS0_STATUS_BLK0_ERROR2			(0x02 << 8)
+#define	BCH_STATUS0_STATUS_BLK0_ERROR3			(0x03 << 8)
+#define	BCH_STATUS0_STATUS_BLK0_ERROR4			(0x04 << 8)
+#define	BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE		(0xfe << 8)
+#define	BCH_STATUS0_STATUS_BLK0_ERASED			(0xff << 8)
+#define	BCH_STATUS0_ALLONES				(1 << 4)
+#define	BCH_STATUS0_CORRECTED				(1 << 3)
+#define	BCH_STATUS0_UNCORRECTABLE			(1 << 2)
+
+#define	BCH_MODE_ERASE_THRESHOLD_MASK			0xff
+#define	BCH_MODE_ERASE_THRESHOLD_OFFSET			0
+
+#define	BCH_ENCODEPTR_ADDR_MASK				0xffffffff
+#define	BCH_ENCODEPTR_ADDR_OFFSET			0
+
+#define	BCH_DATAPTR_ADDR_MASK				0xffffffff
+#define	BCH_DATAPTR_ADDR_OFFSET				0
+
+#define	BCH_METAPTR_ADDR_MASK				0xffffffff
+#define	BCH_METAPTR_ADDR_OFFSET				0
+
+#define	BCH_LAYOUTSELECT_CS15_SELECT_MASK		(0x3 << 30)
+#define	BCH_LAYOUTSELECT_CS15_SELECT_OFFSET		30
+#define	BCH_LAYOUTSELECT_CS14_SELECT_MASK		(0x3 << 28)
+#define	BCH_LAYOUTSELECT_CS14_SELECT_OFFSET		28
+#define	BCH_LAYOUTSELECT_CS13_SELECT_MASK		(0x3 << 26)
+#define	BCH_LAYOUTSELECT_CS13_SELECT_OFFSET		26
+#define	BCH_LAYOUTSELECT_CS12_SELECT_MASK		(0x3 << 24)
+#define	BCH_LAYOUTSELECT_CS12_SELECT_OFFSET		24
+#define	BCH_LAYOUTSELECT_CS11_SELECT_MASK		(0x3 << 22)
+#define	BCH_LAYOUTSELECT_CS11_SELECT_OFFSET		22
+#define	BCH_LAYOUTSELECT_CS10_SELECT_MASK		(0x3 << 20)
+#define	BCH_LAYOUTSELECT_CS10_SELECT_OFFSET		20
+#define	BCH_LAYOUTSELECT_CS9_SELECT_MASK		(0x3 << 18)
+#define	BCH_LAYOUTSELECT_CS9_SELECT_OFFSET		18
+#define	BCH_LAYOUTSELECT_CS8_SELECT_MASK		(0x3 << 16)
+#define	BCH_LAYOUTSELECT_CS8_SELECT_OFFSET		16
+#define	BCH_LAYOUTSELECT_CS7_SELECT_MASK		(0x3 << 14)
+#define	BCH_LAYOUTSELECT_CS7_SELECT_OFFSET		14
+#define	BCH_LAYOUTSELECT_CS6_SELECT_MASK		(0x3 << 12)
+#define	BCH_LAYOUTSELECT_CS6_SELECT_OFFSET		12
+#define	BCH_LAYOUTSELECT_CS5_SELECT_MASK		(0x3 << 10)
+#define	BCH_LAYOUTSELECT_CS5_SELECT_OFFSET		10
+#define	BCH_LAYOUTSELECT_CS4_SELECT_MASK		(0x3 << 8)
+#define	BCH_LAYOUTSELECT_CS4_SELECT_OFFSET		8
+#define	BCH_LAYOUTSELECT_CS3_SELECT_MASK		(0x3 << 6)
+#define	BCH_LAYOUTSELECT_CS3_SELECT_OFFSET		6
+#define	BCH_LAYOUTSELECT_CS2_SELECT_MASK		(0x3 << 4)
+#define	BCH_LAYOUTSELECT_CS2_SELECT_OFFSET		4
+#define	BCH_LAYOUTSELECT_CS1_SELECT_MASK		(0x3 << 2)
+#define	BCH_LAYOUTSELECT_CS1_SELECT_OFFSET		2
+#define	BCH_LAYOUTSELECT_CS0_SELECT_MASK		(0x3 << 0)
+#define	BCH_LAYOUTSELECT_CS0_SELECT_OFFSET		0
+
+#define	BCH_FLASHLAYOUT0_NBLOCKS_MASK			(0xff << 24)
+#define	BCH_FLASHLAYOUT0_NBLOCKS_OFFSET			24
+#define	BCH_FLASHLAYOUT0_META_SIZE_MASK			(0xff << 16)
+#define	BCH_FLASHLAYOUT0_META_SIZE_OFFSET		16
+#if defined(CONFIG_MX6)
+#define	BCH_FLASHLAYOUT0_ECC0_MASK			(0x1f << 11)
+#define	BCH_FLASHLAYOUT0_ECC0_OFFSET			11
+#else
+#define	BCH_FLASHLAYOUT0_ECC0_MASK			(0xf << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_OFFSET			12
+#endif
+#define	BCH_FLASHLAYOUT0_ECC0_NONE			(0x0 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC2			(0x1 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC4			(0x2 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC6			(0x3 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC8			(0x4 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC10			(0x5 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC12			(0x6 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC14			(0x7 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC16			(0x8 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC18			(0x9 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC20			(0xa << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC22			(0xb << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC24			(0xc << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC26			(0xd << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC28			(0xe << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC30			(0xf << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC32			(0x10 << 12)
+#define	BCH_FLASHLAYOUT0_GF13_0_GF14_1			(1 << 10)
+#define	BCH_FLASHLAYOUT0_DATA0_SIZE_MASK		0xfff
+#define	BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET		0
+
+#define	BCH_FLASHLAYOUT1_PAGE_SIZE_MASK			(0xffff << 16)
+#define	BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET		16
+#if defined(CONFIG_MX6)
+#define	BCH_FLASHLAYOUT1_ECCN_MASK			(0x1f << 11)
+#define	BCH_FLASHLAYOUT1_ECCN_OFFSET			11
+#else
+#define	BCH_FLASHLAYOUT1_ECCN_MASK			(0xf << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_OFFSET			12
+#endif
+#define	BCH_FLASHLAYOUT1_ECCN_NONE			(0x0 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC2			(0x1 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC4			(0x2 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC6			(0x3 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC8			(0x4 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC10			(0x5 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC12			(0x6 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC14			(0x7 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC16			(0x8 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC18			(0x9 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC20			(0xa << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC22			(0xb << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC24			(0xc << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC26			(0xd << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC28			(0xe << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC30			(0xf << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC32			(0x10 << 12)
+#define	BCH_FLASHLAYOUT1_GF13_0_GF14_1			(1 << 10)
+#define	BCH_FLASHLAYOUT1_DATAN_SIZE_MASK		0xfff
+#define	BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET		0
+
+#define	BCH_DEBUG0_RSVD1_MASK				(0x1f << 27)
+#define	BCH_DEBUG0_RSVD1_OFFSET				27
+#define	BCH_DEBUG0_ROM_BIST_ENABLE			(1 << 26)
+#define	BCH_DEBUG0_ROM_BIST_COMPLETE			(1 << 25)
+#define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK	(0x1ff << 16)
+#define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET	16
+#define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL	(0x0 << 16)
+#define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE	(0x1 << 16)
+#define	BCH_DEBUG0_KES_DEBUG_SHIFT_SYND			(1 << 15)
+#define	BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG		(1 << 14)
+#define	BCH_DEBUG0_KES_DEBUG_MODE4K			(1 << 13)
+#define	BCH_DEBUG0_KES_DEBUG_KICK			(1 << 12)
+#define	BCH_DEBUG0_KES_STANDALONE			(1 << 11)
+#define	BCH_DEBUG0_KES_DEBUG_STEP			(1 << 10)
+#define	BCH_DEBUG0_KES_DEBUG_STALL			(1 << 9)
+#define	BCH_DEBUG0_BM_KES_TEST_BYPASS			(1 << 8)
+#define	BCH_DEBUG0_RSVD0_MASK				(0x3 << 6)
+#define	BCH_DEBUG0_RSVD0_OFFSET				6
+#define	BCH_DEBUG0_DEBUG_REG_SELECT_MASK		0x3f
+#define	BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET		0
+
+#define	BCH_DBGKESREAD_VALUES_MASK			0xffffffff
+#define	BCH_DBGKESREAD_VALUES_OFFSET			0
+
+#define	BCH_DBGCSFEREAD_VALUES_MASK			0xffffffff
+#define	BCH_DBGCSFEREAD_VALUES_OFFSET			0
+
+#define	BCH_DBGSYNDGENREAD_VALUES_MASK			0xffffffff
+#define	BCH_DBGSYNDGENREAD_VALUES_OFFSET		0
+
+#define	BCH_DBGAHBMREAD_VALUES_MASK			0xffffffff
+#define	BCH_DBGAHBMREAD_VALUES_OFFSET			0
+
+#define	BCH_BLOCKNAME_NAME_MASK				0xffffffff
+#define	BCH_BLOCKNAME_NAME_OFFSET			0
+
+#define	BCH_VERSION_MAJOR_MASK				(0xff << 24)
+#define	BCH_VERSION_MAJOR_OFFSET			24
+#define	BCH_VERSION_MINOR_MASK				(0xff << 16)
+#define	BCH_VERSION_MINOR_OFFSET			16
+#define	BCH_VERSION_STEP_MASK				0xffff
+#define	BCH_VERSION_STEP_OFFSET				0
+
+#endif	/* __MX28_REGS_BCH_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-common.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-common.h
new file mode 100644
index 000000000..e54a220fa
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-common.h
@@ -0,0 +1,69 @@
+/*
+ * Freescale i.MXS Register Accessors
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MXS_REGS_COMMON_H__
+#define __MXS_REGS_COMMON_H__
+
+/*
+ * The i.MXS has interesting feature when it comes to register access. There
+ * are four kinds of access to one particular register. Those are:
+ *
+ * 1) Common read/write access. To use this mode, just write to the address of
+ *    the register.
+ * 2) Set bits only access. To set bits, write which bits you want to set to the
+ *    address of the register + 0x4.
+ * 3) Clear bits only access. To clear bits, write which bits you want to clear
+ *    to the address of the register + 0x8.
+ * 4) Toggle bits only access. To toggle bits, write which bits you want to
+ *    toggle to the address of the register + 0xc.
+ *
+ * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
+ * can be set/cleared by pure write as in access type 1, some need to be
+ * explicitly set/cleared by using access type 2-3.
+ *
+ * The following macros and structures allow the user to either access the
+ * register in all aforementioned modes (by accessing reg_name, reg_name_set,
+ * reg_name_clr, reg_name_tog) or pass the register structure further into
+ * various functions with correct type information (by accessing reg_name_reg).
+ *
+ */
+
+#define	__mxs_reg_8(name)		\
+	uint8_t	name[4];		\
+	uint8_t	name##_set[4];		\
+	uint8_t	name##_clr[4];		\
+	uint8_t	name##_tog[4];		\
+
+#define	__mxs_reg_32(name)		\
+	uint32_t name;			\
+	uint32_t name##_set;		\
+	uint32_t name##_clr;		\
+	uint32_t name##_tog;
+
+struct mxs_register_8 {
+	__mxs_reg_8(reg)
+};
+
+struct mxs_register_32 {
+	__mxs_reg_32(reg)
+};
+
+#define	mxs_reg_8(name)				\
+	union {						\
+		struct { __mxs_reg_8(name) };		\
+		struct mxs_register_8 name##_reg;	\
+	};
+
+#define	mxs_reg_32(name)				\
+	union {						\
+		struct { __mxs_reg_32(name) };		\
+		struct mxs_register_32 name##_reg;	\
+	};
+
+#endif	/* __MXS_REGS_COMMON_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-gpmi.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-gpmi.h
new file mode 100644
index 000000000..b93bfe55c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/regs-gpmi.h
@@ -0,0 +1,209 @@
+/*
+ * Freescale i.MX28 GPMI Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX28_REGS_GPMI_H__
+#define __MX28_REGS_GPMI_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_gpmi_regs {
+	mxs_reg_32(hw_gpmi_ctrl0)
+	mxs_reg_32(hw_gpmi_compare)
+	mxs_reg_32(hw_gpmi_eccctrl)
+	mxs_reg_32(hw_gpmi_ecccount)
+	mxs_reg_32(hw_gpmi_payload)
+	mxs_reg_32(hw_gpmi_auxiliary)
+	mxs_reg_32(hw_gpmi_ctrl1)
+	mxs_reg_32(hw_gpmi_timing0)
+	mxs_reg_32(hw_gpmi_timing1)
+
+	uint32_t	reserved[4];
+
+	mxs_reg_32(hw_gpmi_data)
+	mxs_reg_32(hw_gpmi_stat)
+	mxs_reg_32(hw_gpmi_debug)
+	mxs_reg_32(hw_gpmi_version)
+};
+#endif
+
+#define	GPMI_CTRL0_SFTRST				(1 << 31)
+#define	GPMI_CTRL0_CLKGATE				(1 << 30)
+#define	GPMI_CTRL0_RUN					(1 << 29)
+#define	GPMI_CTRL0_DEV_IRQ_EN				(1 << 28)
+#define	GPMI_CTRL0_LOCK_CS				(1 << 27)
+#define	GPMI_CTRL0_UDMA					(1 << 26)
+#define	GPMI_CTRL0_COMMAND_MODE_MASK			(0x3 << 24)
+#define	GPMI_CTRL0_COMMAND_MODE_OFFSET			24
+#define	GPMI_CTRL0_COMMAND_MODE_WRITE			(0x0 << 24)
+#define	GPMI_CTRL0_COMMAND_MODE_READ			(0x1 << 24)
+#define	GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE	(0x2 << 24)
+#define	GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY		(0x3 << 24)
+#define	GPMI_CTRL0_WORD_LENGTH				(1 << 23)
+#define	GPMI_CTRL0_CS_MASK				(0x7 << 20)
+#define	GPMI_CTRL0_CS_OFFSET				20
+#define	GPMI_CTRL0_ADDRESS_MASK				(0x7 << 17)
+#define	GPMI_CTRL0_ADDRESS_OFFSET			17
+#define	GPMI_CTRL0_ADDRESS_NAND_DATA			(0x0 << 17)
+#define	GPMI_CTRL0_ADDRESS_NAND_CLE			(0x1 << 17)
+#define	GPMI_CTRL0_ADDRESS_NAND_ALE			(0x2 << 17)
+#define	GPMI_CTRL0_ADDRESS_INCREMENT			(1 << 16)
+#define	GPMI_CTRL0_XFER_COUNT_MASK			0xffff
+#define	GPMI_CTRL0_XFER_COUNT_OFFSET			0
+
+#define	GPMI_COMPARE_MASK_MASK				(0xffff << 16)
+#define	GPMI_COMPARE_MASK_OFFSET			16
+#define	GPMI_COMPARE_REFERENCE_MASK			0xffff
+#define	GPMI_COMPARE_REFERENCE_OFFSET			0
+
+#define	GPMI_ECCCTRL_HANDLE_MASK			(0xffff << 16)
+#define	GPMI_ECCCTRL_HANDLE_OFFSET			16
+#define	GPMI_ECCCTRL_ECC_CMD_MASK			(0x3 << 13)
+#define	GPMI_ECCCTRL_ECC_CMD_OFFSET			13
+#define	GPMI_ECCCTRL_ECC_CMD_DECODE			(0x0 << 13)
+#define	GPMI_ECCCTRL_ECC_CMD_ENCODE			(0x1 << 13)
+#define	GPMI_ECCCTRL_ENABLE_ECC				(1 << 12)
+#define	GPMI_ECCCTRL_BUFFER_MASK_MASK			0x1ff
+#define	GPMI_ECCCTRL_BUFFER_MASK_OFFSET			0
+#define	GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY		0x100
+#define	GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE		0x1ff
+
+#define	GPMI_ECCCOUNT_COUNT_MASK			0xffff
+#define	GPMI_ECCCOUNT_COUNT_OFFSET			0
+
+#define	GPMI_PAYLOAD_ADDRESS_MASK			(0x3fffffff << 2)
+#define	GPMI_PAYLOAD_ADDRESS_OFFSET			2
+
+#define	GPMI_AUXILIARY_ADDRESS_MASK			(0x3fffffff << 2)
+#define	GPMI_AUXILIARY_ADDRESS_OFFSET			2
+
+#define	GPMI_CTRL1_DECOUPLE_CS				(1 << 24)
+#define	GPMI_CTRL1_WRN_DLY_SEL_MASK			(0x3 << 22)
+#define	GPMI_CTRL1_WRN_DLY_SEL_OFFSET			22
+#define	GPMI_CTRL1_TIMEOUT_IRQ_EN			(1 << 20)
+#define	GPMI_CTRL1_GANGED_RDYBUSY			(1 << 19)
+#define	GPMI_CTRL1_BCH_MODE				(1 << 18)
+#define	GPMI_CTRL1_DLL_ENABLE				(1 << 17)
+#define	GPMI_CTRL1_HALF_PERIOD				(1 << 16)
+#define	GPMI_CTRL1_RDN_DELAY_MASK			(0xf << 12)
+#define	GPMI_CTRL1_RDN_DELAY_OFFSET			12
+#define	GPMI_CTRL1_DMA2ECC_MODE				(1 << 11)
+#define	GPMI_CTRL1_DEV_IRQ				(1 << 10)
+#define	GPMI_CTRL1_TIMEOUT_IRQ				(1 << 9)
+#define	GPMI_CTRL1_BURST_EN				(1 << 8)
+#define	GPMI_CTRL1_ABORT_WAIT_REQUEST			(1 << 7)
+#define	GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK	(0x7 << 4)
+#define	GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET	4
+#define	GPMI_CTRL1_DEV_RESET				(1 << 3)
+#define	GPMI_CTRL1_ATA_IRQRDY_POLARITY			(1 << 2)
+#define	GPMI_CTRL1_CAMERA_MODE				(1 << 1)
+#define	GPMI_CTRL1_GPMI_MODE				(1 << 0)
+
+#define	GPMI_TIMING0_ADDRESS_SETUP_MASK			(0xff << 16)
+#define	GPMI_TIMING0_ADDRESS_SETUP_OFFSET		16
+#define	GPMI_TIMING0_DATA_HOLD_MASK			(0xff << 8)
+#define	GPMI_TIMING0_DATA_HOLD_OFFSET			8
+#define	GPMI_TIMING0_DATA_SETUP_MASK			0xff
+#define	GPMI_TIMING0_DATA_SETUP_OFFSET			0
+
+#define	GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK		(0xffff << 16)
+#define	GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET		16
+
+#define	GPMI_TIMING2_UDMA_TRP_MASK			(0xff << 24)
+#define	GPMI_TIMING2_UDMA_TRP_OFFSET			24
+#define	GPMI_TIMING2_UDMA_ENV_MASK			(0xff << 16)
+#define	GPMI_TIMING2_UDMA_ENV_OFFSET			16
+#define	GPMI_TIMING2_UDMA_HOLD_MASK			(0xff << 8)
+#define	GPMI_TIMING2_UDMA_HOLD_OFFSET			8
+#define	GPMI_TIMING2_UDMA_SETUP_MASK			0xff
+#define	GPMI_TIMING2_UDMA_SETUP_OFFSET			0
+
+#define	GPMI_DATA_DATA_MASK				0xffffffff
+#define	GPMI_DATA_DATA_OFFSET				0
+
+#define	GPMI_STAT_READY_BUSY_MASK			(0xff << 24)
+#define	GPMI_STAT_READY_BUSY_OFFSET			24
+#define	GPMI_STAT_RDY_TIMEOUT_MASK			(0xff << 16)
+#define	GPMI_STAT_RDY_TIMEOUT_OFFSET			16
+#define	GPMI_STAT_DEV7_ERROR				(1 << 15)
+#define	GPMI_STAT_DEV6_ERROR				(1 << 14)
+#define	GPMI_STAT_DEV5_ERROR				(1 << 13)
+#define	GPMI_STAT_DEV4_ERROR				(1 << 12)
+#define	GPMI_STAT_DEV3_ERROR				(1 << 11)
+#define	GPMI_STAT_DEV2_ERROR				(1 << 10)
+#define	GPMI_STAT_DEV1_ERROR				(1 << 9)
+#define	GPMI_STAT_DEV0_ERROR				(1 << 8)
+#define	GPMI_STAT_ATA_IRQ				(1 << 4)
+#define	GPMI_STAT_INVALID_BUFFER_MASK			(1 << 3)
+#define	GPMI_STAT_FIFO_EMPTY				(1 << 2)
+#define	GPMI_STAT_FIFO_FULL				(1 << 1)
+#define	GPMI_STAT_PRESENT				(1 << 0)
+
+#define	GPMI_DEBUG_WAIT_FOR_READY_END_MASK		(0xff << 24)
+#define	GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET		24
+#define	GPMI_DEBUG_DMA_SENSE_MASK			(0xff << 16)
+#define	GPMI_DEBUG_DMA_SENSE_OFFSET			16
+#define	GPMI_DEBUG_DMAREQ_MASK				(0xff << 8)
+#define	GPMI_DEBUG_DMAREQ_OFFSET			8
+#define	GPMI_DEBUG_CMD_END_MASK				0xff
+#define	GPMI_DEBUG_CMD_END_OFFSET			0
+
+#define	GPMI_VERSION_MAJOR_MASK				(0xff << 24)
+#define	GPMI_VERSION_MAJOR_OFFSET			24
+#define	GPMI_VERSION_MINOR_MASK				(0xff << 16)
+#define	GPMI_VERSION_MINOR_OFFSET			16
+#define	GPMI_VERSION_STEP_MASK				0xffff
+#define	GPMI_VERSION_STEP_OFFSET			0
+
+#define	GPMI_DEBUG2_UDMA_STATE_MASK			(0xf << 24)
+#define	GPMI_DEBUG2_UDMA_STATE_OFFSET			24
+#define	GPMI_DEBUG2_BUSY				(1 << 23)
+#define	GPMI_DEBUG2_PIN_STATE_MASK			(0x7 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_OFFSET			20
+#define	GPMI_DEBUG2_PIN_STATE_PSM_IDLE			(0x0 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT		(0x1 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_ADDR			(0x2 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_STALL			(0x3 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_STROBE		(0x4 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_ATARDY		(0x5 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_DHOLD			(0x6 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_DONE			(0x7 << 20)
+#define	GPMI_DEBUG2_MAIN_STATE_MASK			(0xf << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_OFFSET			16
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_IDLE			(0x0 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT		(0x1 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE		(0x2 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR		(0x3 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ		(0x4 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK		(0x5 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF		(0x6 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO		(0x7 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR		(0x8 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP		(0x9 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_DONE			(0xa << 16)
+#define	GPMI_DEBUG2_SYND2GPMI_BE_MASK			(0xf << 12)
+#define	GPMI_DEBUG2_SYND2GPMI_BE_OFFSET			12
+#define	GPMI_DEBUG2_GPMI2SYND_VALID			(1 << 11)
+#define	GPMI_DEBUG2_GPMI2SYND_READY			(1 << 10)
+#define	GPMI_DEBUG2_SYND2GPMI_VALID			(1 << 9)
+#define	GPMI_DEBUG2_SYND2GPMI_READY			(1 << 8)
+#define	GPMI_DEBUG2_VIEW_DELAYED_RDN			(1 << 7)
+#define	GPMI_DEBUG2_UPDATE_WINDOW			(1 << 6)
+#define	GPMI_DEBUG2_RDN_TAP_MASK			0x3f
+#define	GPMI_DEBUG2_RDN_TAP_OFFSET			0
+
+#define	GPMI_DEBUG3_APB_WORD_CNTR_MASK			(0xffff << 16)
+#define	GPMI_DEBUG3_APB_WORD_CNTR_OFFSET		16
+#define	GPMI_DEBUG3_DEV_WORD_CNTR_MASK			0xffff
+#define	GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET		0
+
+#endif	/* __MX28_REGS_GPMI_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/imx-common/sata.h b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/sata.h
new file mode 100644
index 000000000..6b864cbd1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/imx-common/sata.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX_SATA_H_
+#define __IMX_SATA_H_
+
+/*
+ * SATA setup for i.mx6 quad based platform
+ */
+
+int setup_sata(void);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/io.h b/qemu/roms/u-boot/arch/arm/include/asm/io.h
new file mode 100644
index 000000000..6a1f05ac3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/io.h
@@ -0,0 +1,440 @@
+/*
+ *  linux/include/asm-arm/io.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_ARM_IO_H
+#define __ASM_ARM_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <asm/memory.h>
+#if 0	/* XXX###XXX */
+#include <asm/arch/hardware.h>
+#endif	/* XXX###XXX */
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
+
+extern inline void __raw_writesb(unsigned long addr, const void *data,
+				 int bytelen)
+{
+	uint8_t *buf = (uint8_t *)data;
+	while(bytelen--)
+		__arch_putb(*buf++, addr);
+}
+
+extern inline void __raw_writesw(unsigned long addr, const void *data,
+				 int wordlen)
+{
+	uint16_t *buf = (uint16_t *)data;
+	while(wordlen--)
+		__arch_putw(*buf++, addr);
+}
+
+extern inline void __raw_writesl(unsigned long addr, const void *data,
+				 int longlen)
+{
+	uint32_t *buf = (uint32_t *)data;
+	while(longlen--)
+		__arch_putl(*buf++, addr);
+}
+
+extern inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
+{
+	uint8_t *buf = (uint8_t *)data;
+	while(bytelen--)
+		*buf++ = __arch_getb(addr);
+}
+
+extern inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
+{
+	uint16_t *buf = (uint16_t *)data;
+	while(wordlen--)
+		*buf++ = __arch_getw(addr);
+}
+
+extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
+{
+	uint32_t *buf = (uint32_t *)data;
+	while(longlen--)
+		*buf++ = __arch_getl(addr);
+}
+
+#define __raw_writeb(v,a)	__arch_putb(v,a)
+#define __raw_writew(v,a)	__arch_putw(v,a)
+#define __raw_writel(v,a)	__arch_putl(v,a)
+
+#define __raw_readb(a)		__arch_getb(a)
+#define __raw_readw(a)		__arch_getw(a)
+#define __raw_readl(a)		__arch_getl(a)
+
+/*
+ * TODO: The kernel offers some more advanced versions of barriers, it might
+ * have some advantages to use them instead of the simple one here.
+ */
+#define dmb()		__asm__ __volatile__ ("" : : : "memory")
+#define __iormb()	dmb()
+#define __iowmb()	dmb()
+
+#define writeb(v,c)	({ u8  __v = v; __iowmb(); __arch_putb(__v,c); __v; })
+#define writew(v,c)	({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
+#define writel(v,c)	({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
+
+#define readb(c)	({ u8  __v = __arch_getb(c); __iormb(); __v; })
+#define readw(c)	({ u16 __v = __arch_getw(c); __iormb(); __v; })
+#define readl(c)	({ u32 __v = __arch_getl(c); __iormb(); __v; })
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val,base,off)	__arch_base_putb(val,base,off)
+#define __raw_base_writew(val,base,off)	__arch_base_putw(val,base,off)
+#define __raw_base_writel(val,base,off)	__arch_base_putl(val,base,off)
+
+#define __raw_base_readb(base,off)	__arch_base_getb(base,off)
+#define __raw_base_readw(base,off)	__arch_base_getw(base,off)
+#define __raw_base_readl(base,off)	__arch_base_getl(base,off)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define out_arch(type,endian,a,v)	__raw_write##type(cpu_to_##endian(v),a)
+#define in_arch(type,endian,a)		endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a,v)	out_arch(l,le32,a,v)
+#define out_le16(a,v)	out_arch(w,le16,a,v)
+
+#define in_le32(a)	in_arch(l,le32,a)
+#define in_le16(a)	in_arch(w,le16,a)
+
+#define out_be32(a,v)	out_arch(l,be32,a,v)
+#define out_be16(a,v)	out_arch(w,be16,a,v)
+
+#define in_be32(a)	in_arch(l,be32,a)
+#define in_be16(a)	in_arch(w,be16,a)
+
+#define out_8(a,v)	__raw_writeb(v,a)
+#define in_8(a)		__raw_readb(a)
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ */
+#if 0	/* XXX###XXX */
+#include <asm/arch/io.h>
+#endif	/* XXX###XXX */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The ARM doesn't have special IO access instructions; all IO is memory
+ * mapped.  Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerous
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v,p)			__raw_writeb(v,__io(p))
+#define outw(v,p)			__raw_writew(cpu_to_le16(v),__io(p))
+#define outl(v,p)			__raw_writel(cpu_to_le32(v),__io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p,d,l)			__raw_writesb(__io(p),d,l)
+#define outsw(p,d,l)			__raw_writesw(__io(p),d,l)
+#define outsl(p,d,l)			__raw_writesl(__io(p),d,l)
+
+#define insb(p,d,l)			__raw_readsb(__io(p),d,l)
+#define insw(p,d,l)			__raw_readsw(__io(p),d,l)
+#define insl(p,d,l)			__raw_readsl(__io(p),d,l)
+#endif
+
+#define outb_p(val,port)		outb((val),(port))
+#define outw_p(val,port)		outw((val),(port))
+#define outl_p(val,port)		outl((val),(port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port,from,len)		outsb(port,from,len)
+#define outsw_p(port,from,len)		outsw(port,from,len)
+#define outsl_p(port,from,len)		outsl(port,from,len)
+#define insb_p(port,to,len)		insb(port,to,len)
+#define insw_p(port,to,len)		insw(port,to,len)
+#define insl_p(port,to,len)		insl(port,to,len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off,sz,nocache)					\
+ ({									\
+	unsigned long _off = (off), _size = (sz);			\
+	void *_ret = (void *)0;						\
+	if (iomem_valid_addr(_off, _size))				\
+		_ret = __ioremap(iomem_to_phys(_off),_size,nocache);	\
+	_ret;								\
+ })
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off,sz)			__arch_ioremap((off),(sz),0)
+#define ioremap_nocache(off,sz)		__arch_ioremap((off),(sz),1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
+#define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
+#define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))
+
+#define memset_io(c,v,l)		_memset_io(__mem_pci(c),(v),(l))
+#define memcpy_fromio(a,c,l)		_memcpy_fromio((a),__mem_pci(c),(l))
+#define memcpy_toio(c,a,l)		_memcpy_toio(__mem_pci(c),(a),(l))
+
+#define eth_io_copy_and_sum(s,c,l,b) \
+				eth_copy_and_sum((s),__mem_pci(c),(l),(b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"),0)
+#define readw(addr)			(__readwrite_bug("readw"),0)
+#define readl(addr)			(__readwrite_bug("readl"),0)
+#define writeb(v,addr)			__readwrite_bug("writeb")
+#define writew(v,addr)			__readwrite_bug("writew")
+#define writel(v,addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a,b,c,d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io,sig,len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val,addr)		__raw_writeb(val,__mem_isa(addr))
+#define isa_writew(val,addr)		__raw_writew(val,__mem_isa(addr))
+#define isa_writel(val,addr)		__raw_writel(val,__mem_isa(addr))
+#define isa_memset_io(a,b,c)		_memset_io(__mem_isa(a),(b),(c))
+#define isa_memcpy_fromio(a,b,c)	_memcpy_fromio((a),__mem_isa(b),(c))
+#define isa_memcpy_toio(a,b,c)		_memcpy_toio(__mem_isa((a)),(b),(c))
+
+#define isa_eth_io_copy_and_sum(a,b,c,d) \
+				eth_copy_and_sum((a),__mem_isa(b),(c),(d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+		    int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"),0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"),0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"),0)
+#define isa_writeb(val,addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val,addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val,addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a,b,c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a,b,c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a,b,c)		__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a,b,c,d) \
+				__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io,sig,len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_ARM_IO_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/kona-common/clk.h b/qemu/roms/u-boot/arch/arm/include/asm/kona-common/clk.h
new file mode 100644
index 000000000..2c7e82999
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/kona-common/clk.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+/* This API file is loosely based on u-boot/drivers/video/ipu.h and linux */
+
+#ifndef __KONA_COMMON_CLK_H
+#define __KONA_COMMON_CLK_H
+
+#include <linux/types.h>
+
+struct clk;
+
+/* Only implement required functions for your specific architecture */
+int clk_init(void);
+struct clk *clk_get(const char *id);
+int clk_enable(struct clk *clk);
+void clk_disable(struct clk *clk);
+unsigned long clk_get_rate(struct clk *clk);
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
+int clk_bsc_enable(void *base);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/kona-common/kona_sdhci.h b/qemu/roms/u-boot/arch/arm/include/asm/kona-common/kona_sdhci.h
new file mode 100644
index 000000000..1ff0e55d1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/kona-common/kona_sdhci.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __KONA_SDHCI_H
+#define __KONA_SDHCI_H
+
+int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/linkage.h b/qemu/roms/u-boot/arch/arm/include/asm/linkage.h
new file mode 100644
index 000000000..dbe4b4e31
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/linkage.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .align 0
+#define __ALIGN_STR ".align 0"
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/mach-types.h b/qemu/roms/u-boot/arch/arm/include/asm/mach-types.h
new file mode 100644
index 000000000..440b041a1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/mach-types.h
@@ -0,0 +1,14246 @@
+/*
+ * This was automagically generated from arch/arm/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_ARM_MACH_TYPE_H
+#define __ASM_ARM_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_EBSA110              0
+#define MACH_TYPE_RISCPC               1
+#define MACH_TYPE_EBSA285              4
+#define MACH_TYPE_NETWINDER            5
+#define MACH_TYPE_CATS                 6
+#define MACH_TYPE_SHARK                15
+#define MACH_TYPE_BRUTUS               16
+#define MACH_TYPE_PERSONAL_SERVER      17
+#define MACH_TYPE_L7200                19
+#define MACH_TYPE_PLEB                 20
+#define MACH_TYPE_INTEGRATOR           21
+#define MACH_TYPE_H3600                22
+#define MACH_TYPE_P720T                24
+#define MACH_TYPE_ASSABET              25
+#define MACH_TYPE_LART                 27
+#define MACH_TYPE_GRAPHICSCLIENT       29
+#define MACH_TYPE_XP860                30
+#define MACH_TYPE_CERF                 31
+#define MACH_TYPE_NANOENGINE           32
+#define MACH_TYPE_JORNADA720           48
+#define MACH_TYPE_EDB7211              50
+#define MACH_TYPE_PFS168               52
+#define MACH_TYPE_FLEXANET             54
+#define MACH_TYPE_SIMPAD               87
+#define MACH_TYPE_LUBBOCK              89
+#define MACH_TYPE_CLEP7212             91
+#define MACH_TYPE_SHANNON              97
+#define MACH_TYPE_CONSUS               105
+#define MACH_TYPE_AAED2000             106
+#define MACH_TYPE_CDB89712             107
+#define MACH_TYPE_GRAPHICSMASTER       108
+#define MACH_TYPE_ADSBITSY             109
+#define MACH_TYPE_PXA_IDP              110
+#define MACH_TYPE_PT_SYSTEM3           112
+#define MACH_TYPE_AUTCPU12             118
+#define MACH_TYPE_H3100                136
+#define MACH_TYPE_COLLIE               146
+#define MACH_TYPE_BADGE4               148
+#define MACH_TYPE_FORTUNET             152
+#define MACH_TYPE_MX1ADS               160
+#define MACH_TYPE_H7201                161
+#define MACH_TYPE_H7202                162
+#define MACH_TYPE_IQ80321              169
+#define MACH_TYPE_KS8695               180
+#define MACH_TYPE_SMDK2410             193
+#define MACH_TYPE_CEIVA                200
+#define MACH_TYPE_VOICEBLUE            218
+#define MACH_TYPE_H5400                220
+#define MACH_TYPE_OMAP_INNOVATOR       234
+#define MACH_TYPE_IXDP2400             242
+#define MACH_TYPE_IXDP2800             243
+#define MACH_TYPE_IXDP425              245
+#define MACH_TYPE_HACKKIT              254
+#define MACH_TYPE_IXCDP1100            260
+#define MACH_TYPE_AT91RM9200DK         262
+#define MACH_TYPE_CINTEGRATOR          275
+#define MACH_TYPE_VIPER                283
+#define MACH_TYPE_ADI_COYOTE           290
+#define MACH_TYPE_IXDP2401             299
+#define MACH_TYPE_IXDP2801             300
+#define MACH_TYPE_IQ31244              327
+#define MACH_TYPE_BAST                 331
+#define MACH_TYPE_H1940                347
+#define MACH_TYPE_ENP2611              356
+#define MACH_TYPE_S3C2440              362
+#define MACH_TYPE_GUMSTIX              373
+#define MACH_TYPE_OMAP_H2              382
+#define MACH_TYPE_E740                 384
+#define MACH_TYPE_IQ80331              385
+#define MACH_TYPE_VERSATILE_PB         387
+#define MACH_TYPE_KEV7A400             388
+#define MACH_TYPE_LPD7A400             389
+#define MACH_TYPE_LPD7A404             390
+#define MACH_TYPE_CSB337               399
+#define MACH_TYPE_MAINSTONE            406
+#define MACH_TYPE_XCEP                 413
+#define MACH_TYPE_ARCOM_VULCAN         414
+#define MACH_TYPE_NOMADIK              420
+#define MACH_TYPE_CORGI                423
+#define MACH_TYPE_POODLE               424
+#define MACH_TYPE_ARMCORE              438
+#define MACH_TYPE_MX31ADS              447
+#define MACH_TYPE_HIMALAYA             448
+#define MACH_TYPE_EDB9312              451
+#define MACH_TYPE_OMAP_GENERIC         452
+#define MACH_TYPE_EDB9301              462
+#define MACH_TYPE_EDB9315              463
+#define MACH_TYPE_VR1000               475
+#define MACH_TYPE_OMAP_PERSEUS2        491
+#define MACH_TYPE_E800                 496
+#define MACH_TYPE_E750                 497
+#define MACH_TYPE_SCB9328              508
+#define MACH_TYPE_OMAP_H3              509
+#define MACH_TYPE_OMAP_H4              510
+#define MACH_TYPE_OMAP_OSK             515
+#define MACH_TYPE_TOSA                 520
+#define MACH_TYPE_AVILA                526
+#define MACH_TYPE_EDB9302              538
+#define MACH_TYPE_HUSKY                543
+#define MACH_TYPE_SHEPHERD             545
+#define MACH_TYPE_H4700                562
+#define MACH_TYPE_RX3715               592
+#define MACH_TYPE_NSLU2                597
+#define MACH_TYPE_E400                 598
+#define MACH_TYPE_IXDPG425             604
+#define MACH_TYPE_VERSATILE_AB         606
+#define MACH_TYPE_EDB9307              607
+#define MACH_TYPE_KB9200               612
+#define MACH_TYPE_SX1                  613
+#define MACH_TYPE_IXDP465              618
+#define MACH_TYPE_IXDP2351             619
+#define MACH_TYPE_IQ80332              629
+#define MACH_TYPE_GTWX5715             641
+#define MACH_TYPE_CSB637               648
+#define MACH_TYPE_N30                  656
+#define MACH_TYPE_NEC_MP900            659
+#define MACH_TYPE_KAFA                 662
+#define MACH_TYPE_TS72XX               673
+#define MACH_TYPE_OTOM                 680
+#define MACH_TYPE_NEXCODER_2440        681
+#define MACH_TYPE_ECO920               702
+#define MACH_TYPE_ROADRUNNER           704
+#define MACH_TYPE_AT91RM9200EK         705
+#define MACH_TYPE_SPITZ                713
+#define MACH_TYPE_ADSSPHERE            723
+#define MACH_TYPE_COLIBRI              729
+#define MACH_TYPE_GATEWAY7001          731
+#define MACH_TYPE_PCM027               732
+#define MACH_TYPE_ANUBIS               734
+#define MACH_TYPE_AKITA                744
+#define MACH_TYPE_E330                 753
+#define MACH_TYPE_NOKIA770             755
+#define MACH_TYPE_CARMEVA              769
+#define MACH_TYPE_EDB9315A             772
+#define MACH_TYPE_STARGATE2            774
+#define MACH_TYPE_INTELMOTE2           775
+#define MACH_TYPE_TRIZEPS4             776
+#define MACH_TYPE_PNX4008              782
+#define MACH_TYPE_CPUAT91              787
+#define MACH_TYPE_IQ81340SC            799
+#define MACH_TYPE_IQ81340MC            801
+#define MACH_TYPE_MICRO9               811
+#define MACH_TYPE_MICRO9L              812
+#define MACH_TYPE_OMAP_PALMTE          817
+#define MACH_TYPE_REALVIEW_EB          827
+#define MACH_TYPE_BORZOI               831
+#define MACH_TYPE_PALMLD               835
+#define MACH_TYPE_IXDP28X5             838
+#define MACH_TYPE_OMAP_PALMTT          839
+#define MACH_TYPE_ARCOM_ZEUS           841
+#define MACH_TYPE_OSIRIS               842
+#define MACH_TYPE_PALMTE2              844
+#define MACH_TYPE_MX27ADS              846
+#define MACH_TYPE_AT91SAM9261EK        848
+#define MACH_TYPE_LOFT                 849
+#define MACH_TYPE_MX21ADS              851
+#define MACH_TYPE_AMS_DELTA            862
+#define MACH_TYPE_NAS100D              865
+#define MACH_TYPE_MAGICIAN             875
+#define MACH_TYPE_NXDKN                880
+#define MACH_TYPE_PALMTX               885
+#define MACH_TYPE_S3C2413              887
+#define MACH_TYPE_WG302V2              890
+#define MACH_TYPE_OMAP_2430SDP         900
+#define MACH_TYPE_DAVINCI_EVM          901
+#define MACH_TYPE_PALMZ72              904
+#define MACH_TYPE_NXDB500              905
+#define MACH_TYPE_PALMT5               917
+#define MACH_TYPE_PALMTC               918
+#define MACH_TYPE_OMAP_APOLLON         919
+#define MACH_TYPE_ATEB9200             923
+#define MACH_TYPE_N35                  927
+#define MACH_TYPE_LOGICPD_PXA270       930
+#define MACH_TYPE_NXEB500HMI           941
+#define MACH_TYPE_ESPRESSO             949
+#define MACH_TYPE_RX1950               952
+#define MACH_TYPE_GESBC9312            958
+#define MACH_TYPE_PICOTUX2XX           963
+#define MACH_TYPE_DSMG600              964
+#define MACH_TYPE_OMAP_FSAMPLE         970
+#define MACH_TYPE_SNAPPER_CL15         986
+#define MACH_TYPE_OMAP_PALMZ71         993
+#define MACH_TYPE_SMDK2412             1009
+#define MACH_TYPE_SMDK2413             1022
+#define MACH_TYPE_AML_M5900            1024
+#define MACH_TYPE_BALLOON3             1029
+#define MACH_TYPE_ECBAT91              1072
+#define MACH_TYPE_ONEARM               1075
+#define MACH_TYPE_SMDK2443             1084
+#define MACH_TYPE_FSG                  1091
+#define MACH_TYPE_AT91SAM9260EK        1099
+#define MACH_TYPE_GLANTANK             1100
+#define MACH_TYPE_N2100                1101
+#define MACH_TYPE_QT2410               1108
+#define MACH_TYPE_KIXRP435             1109
+#define MACH_TYPE_CC9P9360DEV          1114
+#define MACH_TYPE_EDB9302A             1127
+#define MACH_TYPE_EDB9307A             1128
+#define MACH_TYPE_OMAP_3430SDP         1138
+#define MACH_TYPE_VSTMS                1140
+#define MACH_TYPE_MICRO9M              1169
+#define MACH_TYPE_BUG                  1179
+#define MACH_TYPE_AT91SAM9263EK        1202
+#define MACH_TYPE_EM7210               1212
+#define MACH_TYPE_VPAC270              1227
+#define MACH_TYPE_TREO680              1230
+#define MACH_TYPE_ZYLONITE             1233
+#define MACH_TYPE_MX31LITE             1236
+#define MACH_TYPE_MIOA701              1257
+#define MACH_TYPE_ARMADILLO5X0         1260
+#define MACH_TYPE_CC9P9360JS           1264
+#define MACH_TYPE_NOKIA_N800           1271
+#define MACH_TYPE_EP80219              1281
+#define MACH_TYPE_GORAMO_MLR           1292
+#define MACH_TYPE_EM_X270              1297
+#define MACH_TYPE_NEO1973_GTA02        1304
+#define MACH_TYPE_AT91SAM9RLEK         1326
+#define MACH_TYPE_COLIBRI320           1340
+#define MACH_TYPE_CAM60                1351
+#define MACH_TYPE_AT91EB01             1354
+#define MACH_TYPE_DB88F5281            1358
+#define MACH_TYPE_CSB726               1359
+#define MACH_TYPE_DAVINCI_DM6467_EVM   1380
+#define MACH_TYPE_DAVINCI_DM355_EVM    1381
+#define MACH_TYPE_LITTLETON            1388
+#define MACH_TYPE_REALVIEW_PB11MP      1407
+#define MACH_TYPE_MX27_3DS             1430
+#define MACH_TYPE_HALIBUT              1439
+#define MACH_TYPE_TROUT                1440
+#define MACH_TYPE_TCT_HAMMER           1460
+#define MACH_TYPE_HERALD               1461
+#define MACH_TYPE_SIM_ONE              1476
+#define MACH_TYPE_JIVE                 1490
+#define MACH_TYPE_SAM9_L9260           1501
+#define MACH_TYPE_REALVIEW_PB1176      1504
+#define MACH_TYPE_YL9200               1507
+#define MACH_TYPE_RD88F5182            1508
+#define MACH_TYPE_KUROBOX_PRO          1509
+#define MACH_TYPE_MX31_3DS             1511
+#define MACH_TYPE_QONG                 1524
+#define MACH_TYPE_OMAP2EVM             1534
+#define MACH_TYPE_OMAP3EVM             1535
+#define MACH_TYPE_DNS323               1542
+#define MACH_TYPE_OMAP3_BEAGLE         1546
+#define MACH_TYPE_NOKIA_N810           1548
+#define MACH_TYPE_PCM038               1551
+#define MACH_TYPE_TS209                1565
+#define MACH_TYPE_AT91CAP9ADK          1566
+#define MACH_TYPE_MX31MOBOARD          1574
+#define MACH_TYPE_TERASTATION_PRO2     1584
+#define MACH_TYPE_LINKSTATION_PRO      1585
+#define MACH_TYPE_E350                 1596
+#define MACH_TYPE_TS409                1601
+#define MACH_TYPE_CM_X300              1616
+#define MACH_TYPE_AT91SAM9G20EK        1624
+#define MACH_TYPE_SMDK6410             1626
+#define MACH_TYPE_U300                 1627
+#define MACH_TYPE_WRT350N_V2           1633
+#define MACH_TYPE_OMAP_LDP             1639
+#define MACH_TYPE_MX35_3DS             1645
+#define MACH_TYPE_NEUROS_OSD2          1647
+#define MACH_TYPE_TRIZEPS4WL           1649
+#define MACH_TYPE_TS78XX               1652
+#define MACH_TYPE_SFFSDR               1657
+#define MACH_TYPE_PCM037               1673
+#define MACH_TYPE_DB88F6281_BP         1680
+#define MACH_TYPE_RD88F6192_NAS        1681
+#define MACH_TYPE_RD88F6281            1682
+#define MACH_TYPE_DB78X00_BP           1683
+#define MACH_TYPE_SMDK2416             1685
+#define MACH_TYPE_WBD111               1690
+#define MACH_TYPE_MV2120               1693
+#define MACH_TYPE_MX51_3DS             1696
+#define MACH_TYPE_IMX27LITE            1701
+#define MACH_TYPE_USB_A9260            1709
+#define MACH_TYPE_USB_A9263            1710
+#define MACH_TYPE_QIL_A9260            1711
+#define MACH_TYPE_KZM_ARM11_01         1722
+#define MACH_TYPE_NOKIA_N810_WIMAX     1727
+#define MACH_TYPE_SAPPHIRE             1729
+#define MACH_TYPE_STMP37XX             1732
+#define MACH_TYPE_STMP378X             1733
+#define MACH_TYPE_EZX_A780             1740
+#define MACH_TYPE_EZX_E680             1741
+#define MACH_TYPE_EZX_A1200            1742
+#define MACH_TYPE_EZX_E6               1743
+#define MACH_TYPE_EZX_E2               1744
+#define MACH_TYPE_EZX_A910             1745
+#define MACH_TYPE_EDMINI_V2            1756
+#define MACH_TYPE_ZIPIT2               1757
+#define MACH_TYPE_OMAP3_PANDORA        1761
+#define MACH_TYPE_MSS2                 1766
+#define MACH_TYPE_LB88RC8480           1769
+#define MACH_TYPE_MX25_3DS             1771
+#define MACH_TYPE_OMAP3530_LV_SOM      1773
+#define MACH_TYPE_DAVINCI_DA830_EVM    1781
+#define MACH_TYPE_AT572D940HFEB        1783
+#define MACH_TYPE_DOVE_DB              1788
+#define MACH_TYPE_OVERO                1798
+#define MACH_TYPE_AT2440EVB            1799
+#define MACH_TYPE_NEOCORE926           1800
+#define MACH_TYPE_WNR854T              1801
+#define MACH_TYPE_RD88F5181L_GE        1812
+#define MACH_TYPE_RD88F5181L_FXO       1818
+#define MACH_TYPE_STAMP9G20            1824
+#define MACH_TYPE_SMDKC100             1826
+#define MACH_TYPE_TAVOREVB             1827
+#define MACH_TYPE_SAAR                 1828
+#define MACH_TYPE_AT91SAM9M10G45EK     1830
+#define MACH_TYPE_MXLADS               1851
+#define MACH_TYPE_LINKSTATION_MINI     1858
+#define MACH_TYPE_AFEB9260             1859
+#define MACH_TYPE_IMX27IPCAM           1871
+#define MACH_TYPE_RD88F6183AP_GE       1894
+#define MACH_TYPE_REALVIEW_PBA8        1897
+#define MACH_TYPE_REALVIEW_PBX         1901
+#define MACH_TYPE_MICRO9S              1902
+#define MACH_TYPE_RUT100               1908
+#define MACH_TYPE_G3EVM                1919
+#define MACH_TYPE_W90P910EVB           1921
+#define MACH_TYPE_W90P950EVB           1923
+#define MACH_TYPE_W90N960EVB           1924
+#define MACH_TYPE_MV88F6281GTW_GE      1932
+#define MACH_TYPE_NCP                  1933
+#define MACH_TYPE_DAVINCI_DM365_EVM    1939
+#define MACH_TYPE_CENTRO               1944
+#define MACH_TYPE_NOKIA_RX51           1955
+#define MACH_TYPE_OMAP_ZOOM2           1967
+#define MACH_TYPE_CPUAT9260            1973
+#define MACH_TYPE_EUKREA_CPUIMX27      1975
+#define MACH_TYPE_ACS5K                1982
+#define MACH_TYPE_SNAPPER_9260         1987
+#define MACH_TYPE_DSM320               1988
+#define MACH_TYPE_EXEDA                1994
+#define MACH_TYPE_MINI2440             1999
+#define MACH_TYPE_COLIBRI300           2000
+#define MACH_TYPE_LINKSTATION_LS_HGL   2005
+#define MACH_TYPE_CPUAT9G20            2031
+#define MACH_TYPE_SMDK6440             2032
+#define MACH_TYPE_NAS4220B             2038
+#define MACH_TYPE_ZYLONITE2            2042
+#define MACH_TYPE_ASPENITE             2043
+#define MACH_TYPE_TTC_DKB              2045
+#define MACH_TYPE_PCM043               2072
+#define MACH_TYPE_SHEEVAPLUG           2097
+#define MACH_TYPE_AVENGERS_LITE        2104
+#define MACH_TYPE_MX51_BABBAGE         2125
+#define MACH_TYPE_RD78X00_MASA         2135
+#define MACH_TYPE_DM355_LEOPARD        2138
+#define MACH_TYPE_TS219                2139
+#define MACH_TYPE_PCA100               2149
+#define MACH_TYPE_DAVINCI_DA850_EVM    2157
+#define MACH_TYPE_AT91SAM9G10EK        2159
+#define MACH_TYPE_OMAP_4430SDP         2160
+#define MACH_TYPE_MAGX_ZN5             2162
+#define MACH_TYPE_BTMAVB101            2172
+#define MACH_TYPE_BTMAWB101            2173
+#define MACH_TYPE_OMAP3_TORPEDO        2178
+#define MACH_TYPE_ANW6410              2183
+#define MACH_TYPE_IMX27_VISSTRIM_M10   2187
+#define MACH_TYPE_PORTUXG20            2191
+#define MACH_TYPE_SMDKC110             2193
+#define MACH_TYPE_OMAP3517EVM          2200
+#define MACH_TYPE_NETSPACE_V2          2201
+#define MACH_TYPE_NETSPACE_MAX_V2      2202
+#define MACH_TYPE_D2NET_V2             2203
+#define MACH_TYPE_NET2BIG_V2           2204
+#define MACH_TYPE_NET5BIG_V2           2206
+#define MACH_TYPE_INETSPACE_V2         2208
+#define MACH_TYPE_AT91SAM9G45EKES      2212
+#define MACH_TYPE_PC7302               2220
+#define MACH_TYPE_SPEAR600             2236
+#define MACH_TYPE_SPEAR300             2237
+#define MACH_TYPE_LILLY1131            2239
+#define MACH_TYPE_HMT                  2254
+#define MACH_TYPE_VEXPRESS             2272
+#define MACH_TYPE_D2NET                2282
+#define MACH_TYPE_BIGDISK              2283
+#define MACH_TYPE_AT91SAM9G20EK_2MMC   2288
+#define MACH_TYPE_BCMRING              2289
+#define MACH_TYPE_DP6XX                2302
+#define MACH_TYPE_MAHIMAHI             2304
+#define MACH_TYPE_SMDK6442             2324
+#define MACH_TYPE_OPENRD_BASE          2325
+#define MACH_TYPE_DEVKIT8000           2330
+#define MACH_TYPE_MX51_EFIKAMX         2336
+#define MACH_TYPE_CM_T35               2341
+#define MACH_TYPE_NET2BIG              2342
+#define MACH_TYPE_IGEP0020             2344
+#define MACH_TYPE_NUC932EVB            2356
+#define MACH_TYPE_OPENRD_CLIENT        2361
+#define MACH_TYPE_U8500                2368
+#define MACH_TYPE_MX51_EFIKASB         2370
+#define MACH_TYPE_MARVELL_JASPER       2382
+#define MACH_TYPE_FLINT                2383
+#define MACH_TYPE_TAVOREVB3            2384
+#define MACH_TYPE_TOUCHBOOK            2393
+#define MACH_TYPE_RAUMFELD_RC          2413
+#define MACH_TYPE_RAUMFELD_CONNECTOR   2414
+#define MACH_TYPE_RAUMFELD_SPEAKER     2415
+#define MACH_TYPE_TNETV107X            2418
+#define MACH_TYPE_SMDKV210             2456
+#define MACH_TYPE_OMAP_ZOOM3           2464
+#define MACH_TYPE_OMAP_3630SDP         2465
+#define MACH_TYPE_SMARTQ7              2479
+#define MACH_TYPE_WATSON_EFM_PLUGIN    2491
+#define MACH_TYPE_G4EVM                2493
+#define MACH_TYPE_OMAPL138_HAWKBOARD   2495
+#define MACH_TYPE_TS41X                2502
+#define MACH_TYPE_PHY3250              2511
+#define MACH_TYPE_MINI6410             2520
+#define MACH_TYPE_MX28EVK              2531
+#define MACH_TYPE_SMARTQ5              2534
+#define MACH_TYPE_DAVINCI_DM6467TEVM   2548
+#define MACH_TYPE_MXT_TD60             2550
+#define MACH_TYPE_RIOT_BEI2            2576
+#define MACH_TYPE_RIOT_X37             2578
+#define MACH_TYPE_CAPC7117             2612
+#define MACH_TYPE_ICONTROL             2624
+#define MACH_TYPE_QSD8X50A_ST1_5       2627
+#define MACH_TYPE_MX23EVK              2629
+#define MACH_TYPE_AP4EVB               2630
+#define MACH_TYPE_MITYOMAPL138         2650
+#define MACH_TYPE_GURUPLUG             2659
+#define MACH_TYPE_SPEAR310             2660
+#define MACH_TYPE_SPEAR320             2661
+#define MACH_TYPE_AQUILA               2676
+#define MACH_TYPE_ESATA_SHEEVAPLUG     2678
+#define MACH_TYPE_MSM7X30_SURF         2679
+#define MACH_TYPE_EA2478DEVKIT         2683
+#define MACH_TYPE_TERASTATION_WXL      2697
+#define MACH_TYPE_MSM7X25_SURF         2703
+#define MACH_TYPE_MSM7X25_FFA          2704
+#define MACH_TYPE_MSM7X27_SURF         2705
+#define MACH_TYPE_MSM7X27_FFA          2706
+#define MACH_TYPE_MSM7X30_FFA          2707
+#define MACH_TYPE_QSD8X50_SURF         2708
+#define MACH_TYPE_MX53_EVK             2716
+#define MACH_TYPE_IGEP0030             2717
+#define MACH_TYPE_SBC3530              2722
+#define MACH_TYPE_SAARB                2727
+#define MACH_TYPE_HARMONY              2731
+#define MACH_TYPE_MSM7X30_FLUID        2741
+#define MACH_TYPE_CM_T3517             2750
+#define MACH_TYPE_WBD222               2753
+#define MACH_TYPE_MSM8X60_SURF         2755
+#define MACH_TYPE_MSM8X60_SIM          2756
+#define MACH_TYPE_TCC8000_SDK          2758
+#define MACH_TYPE_NANOS                2759
+#define MACH_TYPE_STAMP9G45            2761
+#define MACH_TYPE_CNS3420VB            2776
+#define MACH_TYPE_OMAP4_PANDA          2791
+#define MACH_TYPE_TI8168EVM            2800
+#define MACH_TYPE_TETON_BGA            2816
+#define MACH_TYPE_EUKREA_CPUIMX25SD    2820
+#define MACH_TYPE_EUKREA_CPUIMX35SD    2821
+#define MACH_TYPE_EUKREA_CPUIMX51SD    2822
+#define MACH_TYPE_EUKREA_CPUIMX51      2823
+#define MACH_TYPE_SMDKC210             2838
+#define MACH_TYPE_OMAP3_BRAILLO        2839
+#define MACH_TYPE_SPYPLUG              2840
+#define MACH_TYPE_GINGER               2841
+#define MACH_TYPE_TNY_T3530            2842
+#define MACH_TYPE_PCA102               2843
+#define MACH_TYPE_SPADE                2844
+#define MACH_TYPE_MXC25_TOPAZ          2845
+#define MACH_TYPE_T5325                2846
+#define MACH_TYPE_GW2361               2847
+#define MACH_TYPE_ELOG                 2848
+#define MACH_TYPE_INCOME               2849
+#define MACH_TYPE_BCM589X              2850
+#define MACH_TYPE_ETNA                 2851
+#define MACH_TYPE_HAWKS                2852
+#define MACH_TYPE_MESON                2853
+#define MACH_TYPE_XSBASE255            2854
+#define MACH_TYPE_PVM2030              2855
+#define MACH_TYPE_MIOA502              2856
+#define MACH_TYPE_VVBOX_SDORIG2        2857
+#define MACH_TYPE_VVBOX_SDLITE2        2858
+#define MACH_TYPE_VVBOX_SDPRO4         2859
+#define MACH_TYPE_HTC_SPV_M700         2860
+#define MACH_TYPE_MX257SX              2861
+#define MACH_TYPE_GONI                 2862
+#define MACH_TYPE_MSM8X55_SVLTE_FFA    2863
+#define MACH_TYPE_MSM8X55_SVLTE_SURF   2864
+#define MACH_TYPE_QUICKSTEP            2865
+#define MACH_TYPE_DMW96                2866
+#define MACH_TYPE_HAMMERHEAD           2867
+#define MACH_TYPE_TRIDENT              2868
+#define MACH_TYPE_LIGHTNING            2869
+#define MACH_TYPE_ICONNECT             2870
+#define MACH_TYPE_AUTOBOT              2871
+#define MACH_TYPE_COCONUT              2872
+#define MACH_TYPE_DURIAN               2873
+#define MACH_TYPE_CAYENNE              2874
+#define MACH_TYPE_FUJI                 2875
+#define MACH_TYPE_SYNOLOGY_6282        2876
+#define MACH_TYPE_EM1SY                2877
+#define MACH_TYPE_M502                 2878
+#define MACH_TYPE_MATRIX518            2879
+#define MACH_TYPE_TINY_GURNARD         2880
+#define MACH_TYPE_SPEAR1310            2881
+#define MACH_TYPE_BV07                 2882
+#define MACH_TYPE_MXT_TD61             2883
+#define MACH_TYPE_OPENRD_ULTIMATE      2884
+#define MACH_TYPE_DEVIXP               2885
+#define MACH_TYPE_MICCPT               2886
+#define MACH_TYPE_MIC256               2887
+#define MACH_TYPE_AS1167               2888
+#define MACH_TYPE_OMAP3_IBIZA          2889
+#define MACH_TYPE_U5500                2890
+#define MACH_TYPE_DAVINCI_PICTO        2891
+#define MACH_TYPE_MECHA                2892
+#define MACH_TYPE_BUBBA3               2893
+#define MACH_TYPE_PUPITRE              2894
+#define MACH_TYPE_TEGRA_VOGUE          2896
+#define MACH_TYPE_TEGRA_E1165          2897
+#define MACH_TYPE_SIMPLENET            2898
+#define MACH_TYPE_EC4350TBM            2899
+#define MACH_TYPE_PEC_TC               2900
+#define MACH_TYPE_PEC_HC2              2901
+#define MACH_TYPE_ESL_MOBILIS_A        2902
+#define MACH_TYPE_ESL_MOBILIS_B        2903
+#define MACH_TYPE_ESL_WAVE_A           2904
+#define MACH_TYPE_ESL_WAVE_B           2905
+#define MACH_TYPE_UNISENSE_MMM         2906
+#define MACH_TYPE_BLUESHARK            2907
+#define MACH_TYPE_E10                  2908
+#define MACH_TYPE_APP3K_ROBIN          2909
+#define MACH_TYPE_POV15HD              2910
+#define MACH_TYPE_STELLA               2911
+#define MACH_TYPE_LINKSTATION_LSCHL    2913
+#define MACH_TYPE_NETWALKER            2914
+#define MACH_TYPE_ACSX106              2915
+#define MACH_TYPE_ATLAS5_C1            2916
+#define MACH_TYPE_NSB3AST              2917
+#define MACH_TYPE_GNET_SLC             2918
+#define MACH_TYPE_AF4000               2919
+#define MACH_TYPE_ARK9431              2920
+#define MACH_TYPE_FS_S5PC100           2921
+#define MACH_TYPE_OMAP3505NOVA8        2922
+#define MACH_TYPE_OMAP3621_EDP1        2923
+#define MACH_TYPE_ORATISAES            2924
+#define MACH_TYPE_SMDKV310             2925
+#define MACH_TYPE_SIEMENS_L0           2926
+#define MACH_TYPE_VENTANA              2927
+#define MACH_TYPE_WM8505_7IN_NETBOOK   2928
+#define MACH_TYPE_EC4350SDB            2929
+#define MACH_TYPE_MIMAS                2930
+#define MACH_TYPE_TITAN                2931
+#define MACH_TYPE_CRANEBOARD           2932
+#define MACH_TYPE_ES2440               2933
+#define MACH_TYPE_NAJAY_A9263          2934
+#define MACH_TYPE_HTCTORNADO           2935
+#define MACH_TYPE_DIMM_MX257           2936
+#define MACH_TYPE_JIGEN                2937
+#define MACH_TYPE_SMDK6450             2938
+#define MACH_TYPE_MENO_QNG             2939
+#define MACH_TYPE_NS2416               2940
+#define MACH_TYPE_RPC353               2941
+#define MACH_TYPE_TQ6410               2942
+#define MACH_TYPE_SKY6410              2943
+#define MACH_TYPE_DYNASTY              2944
+#define MACH_TYPE_VIVO                 2945
+#define MACH_TYPE_BURY_BL7582          2946
+#define MACH_TYPE_BURY_BPS5270         2947
+#define MACH_TYPE_BASI                 2948
+#define MACH_TYPE_TN200                2949
+#define MACH_TYPE_C2MMI                2950
+#define MACH_TYPE_MESON_6236M          2951
+#define MACH_TYPE_MESON_8626M          2952
+#define MACH_TYPE_TUBE                 2953
+#define MACH_TYPE_MESSINA              2954
+#define MACH_TYPE_MX50_ARM2            2955
+#define MACH_TYPE_CETUS9263            2956
+#define MACH_TYPE_BROWNSTONE           2957
+#define MACH_TYPE_VMX25                2958
+#define MACH_TYPE_VMX51                2959
+#define MACH_TYPE_ABACUS               2960
+#define MACH_TYPE_CM4745               2961
+#define MACH_TYPE_ORATISLINK           2962
+#define MACH_TYPE_DAVINCI_DM365_DVR    2963
+#define MACH_TYPE_NETVIZ               2964
+#define MACH_TYPE_FLEXIBITY            2965
+#define MACH_TYPE_WLAN_COMPUTER        2966
+#define MACH_TYPE_LPC24XX              2967
+#define MACH_TYPE_SPICA                2968
+#define MACH_TYPE_GPSDISPLAY           2969
+#define MACH_TYPE_BIPNET               2970
+#define MACH_TYPE_OVERO_CTU_INERTIAL   2971
+#define MACH_TYPE_DAVINCI_DM355_MMM    2972
+#define MACH_TYPE_PC9260_V2            2973
+#define MACH_TYPE_PTX7545              2974
+#define MACH_TYPE_TM_EFDC              2975
+#define MACH_TYPE_OMAP3_WALDO1         2977
+#define MACH_TYPE_FLYER                2978
+#define MACH_TYPE_TORNADO3240          2979
+#define MACH_TYPE_SOLI_01              2980
+#define MACH_TYPE_OMAPL138_EUROPALC    2981
+#define MACH_TYPE_HELIOS_V1            2982
+#define MACH_TYPE_NETSPACE_LITE_V2     2983
+#define MACH_TYPE_SSC                  2984
+#define MACH_TYPE_PREMIERWAVE_EN       2985
+#define MACH_TYPE_WASABI               2986
+#define MACH_TYPE_MX50_RDP             2988
+#define MACH_TYPE_UNIVERSAL_C210       2989
+#define MACH_TYPE_REAL6410             2990
+#define MACH_TYPE_SPX_SAKURA           2991
+#define MACH_TYPE_IJ3K_2440            2992
+#define MACH_TYPE_OMAP3_BC10           2993
+#define MACH_TYPE_THEBE                2994
+#define MACH_TYPE_RV082                2995
+#define MACH_TYPE_ARMLGUEST            2996
+#define MACH_TYPE_TJINC1000            2997
+#define MACH_TYPE_DOCKSTAR             2998
+#define MACH_TYPE_AX8008               2999
+#define MACH_TYPE_GNET_SGCE            3000
+#define MACH_TYPE_PXWNAS_500_1000      3001
+#define MACH_TYPE_EA20                 3002
+#define MACH_TYPE_AWM2                 3003
+#define MACH_TYPE_TI8148EVM            3004
+#define MACH_TYPE_SEABOARD             3005
+#define MACH_TYPE_LINKSTATION_CHLV2    3006
+#define MACH_TYPE_TERA_PRO2_RACK       3007
+#define MACH_TYPE_RUBYS                3008
+#define MACH_TYPE_AQUARIUS             3009
+#define MACH_TYPE_MX53_ARD             3010
+#define MACH_TYPE_MX53_SMD             3011
+#define MACH_TYPE_LSWXL                3012
+#define MACH_TYPE_DOVE_AVNG_V3         3013
+#define MACH_TYPE_SDI_ESS_9263         3014
+#define MACH_TYPE_JOCPU550             3015
+#define MACH_TYPE_MSM8X60_RUMI3        3016
+#define MACH_TYPE_MSM8X60_FFA          3017
+#define MACH_TYPE_YANOMAMI             3018
+#define MACH_TYPE_GTA04                3019
+#define MACH_TYPE_CM_A510              3020
+#define MACH_TYPE_OMAP3_RFS200         3021
+#define MACH_TYPE_KX33XX               3022
+#define MACH_TYPE_PTX7510              3023
+#define MACH_TYPE_TOP9000              3024
+#define MACH_TYPE_TEENOTE              3025
+#define MACH_TYPE_TS3                  3026
+#define MACH_TYPE_A0                   3027
+#define MACH_TYPE_FSM9XXX_SURF         3028
+#define MACH_TYPE_FSM9XXX_FFA          3029
+#define MACH_TYPE_FRRHWCDMA60W         3030
+#define MACH_TYPE_REMUS                3031
+#define MACH_TYPE_AT91CAP7XDK          3032
+#define MACH_TYPE_AT91CAP7STK          3033
+#define MACH_TYPE_KT_SBC_SAM9_1        3034
+#define MACH_TYPE_ARMADA_XP_DB         3036
+#define MACH_TYPE_SPDM                 3037
+#define MACH_TYPE_GTIB                 3038
+#define MACH_TYPE_DGM3240              3039
+#define MACH_TYPE_HTCMEGA              3041
+#define MACH_TYPE_TRICORDER            3042
+#define MACH_TYPE_TX28                 3043
+#define MACH_TYPE_BSTBRD               3044
+#define MACH_TYPE_PWB3090              3045
+#define MACH_TYPE_IDEA6410             3046
+#define MACH_TYPE_QBC9263              3047
+#define MACH_TYPE_BORABORA             3048
+#define MACH_TYPE_VALDEZ               3049
+#define MACH_TYPE_LS9G20               3050
+#define MACH_TYPE_MIOS_V1              3051
+#define MACH_TYPE_S5PC110_CRESPO       3052
+#define MACH_TYPE_CONTROLTEK9G20       3053
+#define MACH_TYPE_TIN307               3054
+#define MACH_TYPE_TIN510               3055
+#define MACH_TYPE_BLUECHEESE           3057
+#define MACH_TYPE_TEM3X30              3058
+#define MACH_TYPE_HARVEST_DESOTO       3059
+#define MACH_TYPE_MSM8X60_QRDC         3060
+#define MACH_TYPE_SPEAR900             3061
+#define MACH_TYPE_PCONTROL_G20         3062
+#define MACH_TYPE_RDSTOR               3063
+#define MACH_TYPE_USDLOADER            3064
+#define MACH_TYPE_TSOPLOADER           3065
+#define MACH_TYPE_KRONOS               3066
+#define MACH_TYPE_FFCORE               3067
+#define MACH_TYPE_MONE                 3068
+#define MACH_TYPE_UNIT2S               3069
+#define MACH_TYPE_ACER_A5              3070
+#define MACH_TYPE_ETHERPRO_ISP         3071
+#define MACH_TYPE_STRETCHS7000         3072
+#define MACH_TYPE_P87_SMARTSIM         3073
+#define MACH_TYPE_TULIP                3074
+#define MACH_TYPE_SUNFLOWER            3075
+#define MACH_TYPE_RIB                  3076
+#define MACH_TYPE_CLOD                 3077
+#define MACH_TYPE_RUMP                 3078
+#define MACH_TYPE_TENDERLOIN           3079
+#define MACH_TYPE_SHORTLOIN            3080
+#define MACH_TYPE_ANTARES              3082
+#define MACH_TYPE_WB40N                3083
+#define MACH_TYPE_HERRING              3084
+#define MACH_TYPE_NAXY400              3085
+#define MACH_TYPE_NAXY1200             3086
+#define MACH_TYPE_VPR200               3087
+#define MACH_TYPE_BUG20                3088
+#define MACH_TYPE_GOFLEXNET            3089
+#define MACH_TYPE_TORBRECK             3090
+#define MACH_TYPE_SAARB_MG1            3091
+#define MACH_TYPE_CALLISTO             3092
+#define MACH_TYPE_MULTHSU              3093
+#define MACH_TYPE_SALUDA               3094
+#define MACH_TYPE_PEMP_OMAP3_APOLLO    3095
+#define MACH_TYPE_VC0718               3096
+#define MACH_TYPE_MVBLX                3097
+#define MACH_TYPE_INHAND_APEIRON       3098
+#define MACH_TYPE_INHAND_FURY          3099
+#define MACH_TYPE_INHAND_SIREN         3100
+#define MACH_TYPE_HDNVP                3101
+#define MACH_TYPE_SOFTWINNER           3102
+#define MACH_TYPE_PRIMA2_EVB           3103
+#define MACH_TYPE_NAS6210              3104
+#define MACH_TYPE_UNISDEV              3105
+#define MACH_TYPE_SBCA11               3106
+#define MACH_TYPE_SAGA                 3107
+#define MACH_TYPE_NS_K330              3108
+#define MACH_TYPE_TANNA                3109
+#define MACH_TYPE_IMATE8502            3110
+#define MACH_TYPE_ASPEN                3111
+#define MACH_TYPE_DAINTREE_CWAC        3112
+#define MACH_TYPE_ZMX25                3113
+#define MACH_TYPE_MAPLE1               3114
+#define MACH_TYPE_QSD8X72_SURF         3115
+#define MACH_TYPE_QSD8X72_FFA          3116
+#define MACH_TYPE_ABILENE              3117
+#define MACH_TYPE_EIGEN_TTR            3118
+#define MACH_TYPE_IOMEGA_IX2_200       3119
+#define MACH_TYPE_CORETEC_VCX7400      3120
+#define MACH_TYPE_SANTIAGO             3121
+#define MACH_TYPE_MX257SOL             3122
+#define MACH_TYPE_STRASBOURG           3123
+#define MACH_TYPE_MSM8X60_FLUID        3124
+#define MACH_TYPE_SMARTQV5             3125
+#define MACH_TYPE_SMARTQV3             3126
+#define MACH_TYPE_SMARTQV7             3127
+#define MACH_TYPE_PAZ00                3128
+#define MACH_TYPE_ACMENETUSFOXG20      3129
+#define MACH_TYPE_FWBD_0404            3131
+#define MACH_TYPE_HDGU                 3132
+#define MACH_TYPE_PYRAMID              3133
+#define MACH_TYPE_EPIPHAN              3134
+#define MACH_TYPE_OMAP_BENDER          3135
+#define MACH_TYPE_GURNARD              3136
+#define MACH_TYPE_GTL_IT5100           3137
+#define MACH_TYPE_BCM2708              3138
+#define MACH_TYPE_MX51_GGC             3139
+#define MACH_TYPE_SHARESPACE           3140
+#define MACH_TYPE_HABA_KNX_EXPLORER    3141
+#define MACH_TYPE_SIMTEC_KIRKMOD       3142
+#define MACH_TYPE_CRUX                 3143
+#define MACH_TYPE_MX51_BRAVO           3144
+#define MACH_TYPE_CHARON               3145
+#define MACH_TYPE_PICOCOM3             3146
+#define MACH_TYPE_PICOCOM4             3147
+#define MACH_TYPE_SERRANO              3148
+#define MACH_TYPE_DOUBLESHOT           3149
+#define MACH_TYPE_EVSY                 3150
+#define MACH_TYPE_HUASHAN              3151
+#define MACH_TYPE_LAUSANNE             3152
+#define MACH_TYPE_EMERALD              3153
+#define MACH_TYPE_TQMA35               3154
+#define MACH_TYPE_MARVEL               3155
+#define MACH_TYPE_MANUAE               3156
+#define MACH_TYPE_CHACHA               3157
+#define MACH_TYPE_LEMON                3158
+#define MACH_TYPE_CSC                  3159
+#define MACH_TYPE_GIRA_KNXIP_ROUTER    3160
+#define MACH_TYPE_T20                  3161
+#define MACH_TYPE_HDMINI               3162
+#define MACH_TYPE_SCIPHONE_G2          3163
+#define MACH_TYPE_EXPRESS              3164
+#define MACH_TYPE_EXPRESS_KT           3165
+#define MACH_TYPE_MAXIMASP             3166
+#define MACH_TYPE_NITROGEN_IMX51       3167
+#define MACH_TYPE_NITROGEN_IMX53       3168
+#define MACH_TYPE_SUNFIRE              3169
+#define MACH_TYPE_AROWANA              3170
+#define MACH_TYPE_TEGRA_DAYTONA        3171
+#define MACH_TYPE_TEGRA_SWORDFISH      3172
+#define MACH_TYPE_EDISON               3173
+#define MACH_TYPE_SVP8500V1            3174
+#define MACH_TYPE_SVP8500V2            3175
+#define MACH_TYPE_SVP5500              3176
+#define MACH_TYPE_B5500                3177
+#define MACH_TYPE_S5500                3178
+#define MACH_TYPE_ICON                 3179
+#define MACH_TYPE_ELEPHANT             3180
+#define MACH_TYPE_SHOOTER              3182
+#define MACH_TYPE_SPADE_LTE            3183
+#define MACH_TYPE_PHILHWANI            3184
+#define MACH_TYPE_GSNCOMM              3185
+#define MACH_TYPE_STRASBOURG_A2        3186
+#define MACH_TYPE_MMM                  3187
+#define MACH_TYPE_DAVINCI_DM365_BV     3188
+#define MACH_TYPE_AG5EVM               3189
+#define MACH_TYPE_SC575PLC             3190
+#define MACH_TYPE_SC575IPC             3191
+#define MACH_TYPE_OMAP3_TDM3730        3192
+#define MACH_TYPE_TOP9000_EVAL         3194
+#define MACH_TYPE_TOP9000_SU           3195
+#define MACH_TYPE_UTM300               3196
+#define MACH_TYPE_TSUNAGI              3197
+#define MACH_TYPE_TS75XX               3198
+#define MACH_TYPE_TS47XX               3200
+#define MACH_TYPE_DA850_K5             3201
+#define MACH_TYPE_AX502                3202
+#define MACH_TYPE_IGEP0032             3203
+#define MACH_TYPE_ANTERO               3204
+#define MACH_TYPE_SYNERGY              3205
+#define MACH_TYPE_ICS_IF_VOIP          3206
+#define MACH_TYPE_WLF_CRAGG_6410       3207
+#define MACH_TYPE_PUNICA               3208
+#define MACH_TYPE_TRIMSLICE            3209
+#define MACH_TYPE_MX27_WMULTRA         3210
+#define MACH_TYPE_MACKEREL             3211
+#define MACH_TYPE_FA9X27               3213
+#define MACH_TYPE_NS2816TB             3214
+#define MACH_TYPE_NS2816_NTPAD         3215
+#define MACH_TYPE_NS2816_NTNB          3216
+#define MACH_TYPE_KAEN                 3217
+#define MACH_TYPE_NV1000               3218
+#define MACH_TYPE_NUC950TS             3219
+#define MACH_TYPE_NOKIA_RM680          3220
+#define MACH_TYPE_AST2200              3221
+#define MACH_TYPE_LEAD                 3222
+#define MACH_TYPE_UNINO1               3223
+#define MACH_TYPE_GREECO               3224
+#define MACH_TYPE_VERDI                3225
+#define MACH_TYPE_DM6446_ADBOX         3226
+#define MACH_TYPE_QUAD_SALSA           3227
+#define MACH_TYPE_ABB_GMA_1_1          3228
+#define MACH_TYPE_SVCID                3229
+#define MACH_TYPE_MSM8960_SIM          3230
+#define MACH_TYPE_MSM8960_RUMI3        3231
+#define MACH_TYPE_ICON_G               3232
+#define MACH_TYPE_MB3                  3233
+#define MACH_TYPE_GSIA18S              3234
+#define MACH_TYPE_PIVICC               3235
+#define MACH_TYPE_PCM048               3236
+#define MACH_TYPE_DDS                  3237
+#define MACH_TYPE_CHALTEN_XA1          3238
+#define MACH_TYPE_TS48XX               3239
+#define MACH_TYPE_TONGA2_TFTTIMER      3240
+#define MACH_TYPE_WHISTLER             3241
+#define MACH_TYPE_ASL_PHOENIX          3242
+#define MACH_TYPE_AT91SAM9263OTLITE    3243
+#define MACH_TYPE_DDPLUG               3244
+#define MACH_TYPE_D2PLUG               3245
+#define MACH_TYPE_KZM9D                3246
+#define MACH_TYPE_VERDI_LTE            3247
+#define MACH_TYPE_NANOZOOM             3248
+#define MACH_TYPE_DM3730_SOM_LV        3249
+#define MACH_TYPE_DM3730_TORPEDO       3250
+#define MACH_TYPE_ANCHOVY              3251
+#define MACH_TYPE_RE2REV20             3253
+#define MACH_TYPE_RE2REV21             3254
+#define MACH_TYPE_CNS21XX              3255
+#define MACH_TYPE_RIDER                3257
+#define MACH_TYPE_NSK330               3258
+#define MACH_TYPE_CNS2133EVB           3259
+#define MACH_TYPE_Z3_816X_MOD          3260
+#define MACH_TYPE_Z3_814X_MOD          3261
+#define MACH_TYPE_BEECT                3262
+#define MACH_TYPE_DMA_THUNDERBUG       3263
+#define MACH_TYPE_OMN_AT91SAM9G20      3264
+#define MACH_TYPE_MX25_E2S_UC          3265
+#define MACH_TYPE_MIONE                3266
+#define MACH_TYPE_TOP9000_TCU          3267
+#define MACH_TYPE_TOP9000_BSL          3268
+#define MACH_TYPE_KINGDOM              3269
+#define MACH_TYPE_ARMADILLO460         3270
+#define MACH_TYPE_LQ2                  3271
+#define MACH_TYPE_SWEDA_TMS2           3272
+#define MACH_TYPE_MX53_LOCO            3273
+#define MACH_TYPE_ACER_A8              3275
+#define MACH_TYPE_ACER_GAUGUIN         3276
+#define MACH_TYPE_GUPPY                3277
+#define MACH_TYPE_MX61_ARD             3278
+#define MACH_TYPE_TX53                 3279
+#define MACH_TYPE_OMAPL138_CASE_A3     3280
+#define MACH_TYPE_UEMD                 3281
+#define MACH_TYPE_CCWMX51MUT           3282
+#define MACH_TYPE_ROCKHOPPER           3283
+#define MACH_TYPE_ENCORE               3284
+#define MACH_TYPE_HKDKC100             3285
+#define MACH_TYPE_TS42XX               3286
+#define MACH_TYPE_AEBL                 3287
+#define MACH_TYPE_WARIO                3288
+#define MACH_TYPE_GFS_SPM              3289
+#define MACH_TYPE_CM_T3730             3290
+#define MACH_TYPE_ISC3                 3291
+#define MACH_TYPE_RASCAL               3292
+#define MACH_TYPE_HREFV60              3293
+#define MACH_TYPE_TPT_2_0              3294
+#define MACH_TYPE_SPLENDOR             3296
+#define MACH_TYPE_MSM8X60_QT           3298
+#define MACH_TYPE_HTC_HD_MINI          3299
+#define MACH_TYPE_ATHENE               3300
+#define MACH_TYPE_DEEP_R_EK_1          3301
+#define MACH_TYPE_VIVOW_CT             3302
+#define MACH_TYPE_NERY_1000            3303
+#define MACH_TYPE_RFL109145_SSRV       3304
+#define MACH_TYPE_NMH                  3305
+#define MACH_TYPE_WN802T               3306
+#define MACH_TYPE_DRAGONET             3307
+#define MACH_TYPE_AT91SAM9263DESK16L   3309
+#define MACH_TYPE_BCMHANA_SV           3310
+#define MACH_TYPE_BCMHANA_TABLET       3311
+#define MACH_TYPE_KOI                  3312
+#define MACH_TYPE_TS4800               3313
+#define MACH_TYPE_TQMA9263             3314
+#define MACH_TYPE_HOLIDAY              3315
+#define MACH_TYPE_DMA6410              3316
+#define MACH_TYPE_PCATS_OVERLAY        3317
+#define MACH_TYPE_HWGW6410             3318
+#define MACH_TYPE_SHENZHOU             3319
+#define MACH_TYPE_CWME9210             3320
+#define MACH_TYPE_CWME9210JS           3321
+#define MACH_TYPE_PGS_SITARA           3322
+#define MACH_TYPE_COLIBRI_TEGRA2       3323
+#define MACH_TYPE_W21                  3324
+#define MACH_TYPE_POLYSAT1             3325
+#define MACH_TYPE_DATAWAY              3326
+#define MACH_TYPE_COBRAL138            3327
+#define MACH_TYPE_ROVERPCS8            3328
+#define MACH_TYPE_MARVELC              3329
+#define MACH_TYPE_NAVEFIHID            3330
+#define MACH_TYPE_DM365_CV100          3331
+#define MACH_TYPE_ABLE                 3332
+#define MACH_TYPE_LEGACY               3333
+#define MACH_TYPE_ICONG                3334
+#define MACH_TYPE_ROVER_G8             3335
+#define MACH_TYPE_T5388P               3336
+#define MACH_TYPE_DINGO                3337
+#define MACH_TYPE_GOFLEXHOME           3338
+#define MACH_TYPE_LANREADYFN511        3340
+#define MACH_TYPE_OMAP3_BAIA           3341
+#define MACH_TYPE_OMAP3SMARTDISPLAY    3342
+#define MACH_TYPE_XILINX               3343
+#define MACH_TYPE_A2F                  3344
+#define MACH_TYPE_SKY25                3345
+#define MACH_TYPE_CCMX53               3346
+#define MACH_TYPE_CCMX53JS             3347
+#define MACH_TYPE_CCWMX53              3348
+#define MACH_TYPE_CCWMX53JS            3349
+#define MACH_TYPE_FRISMS               3350
+#define MACH_TYPE_MSM7X27A_FFA         3351
+#define MACH_TYPE_MSM7X27A_SURF        3352
+#define MACH_TYPE_MSM7X27A_RUMI3       3353
+#define MACH_TYPE_DIMMSAM9G20          3354
+#define MACH_TYPE_DIMM_IMX28           3355
+#define MACH_TYPE_AMK_A4               3356
+#define MACH_TYPE_GNET_SGME            3357
+#define MACH_TYPE_SHOOTER_U            3358
+#define MACH_TYPE_VMX53                3359
+#define MACH_TYPE_RHINO                3360
+#define MACH_TYPE_ARMLEX4210           3361
+#define MACH_TYPE_SWARCOEXTMODEM       3362
+#define MACH_TYPE_SNOWBALL             3363
+#define MACH_TYPE_PCM049               3364
+#define MACH_TYPE_VIGOR                3365
+#define MACH_TYPE_OSLO_AMUNDSEN        3366
+#define MACH_TYPE_GSL_DIAMOND          3367
+#define MACH_TYPE_CV2201               3368
+#define MACH_TYPE_CV2202               3369
+#define MACH_TYPE_CV2203               3370
+#define MACH_TYPE_VIT_IBOX             3371
+#define MACH_TYPE_DM6441_ESP           3372
+#define MACH_TYPE_AT91SAM9X5EK         3373
+#define MACH_TYPE_LIBRA                3374
+#define MACH_TYPE_EASYCRRH             3375
+#define MACH_TYPE_TRIPEL               3376
+#define MACH_TYPE_ENDIAN_MINI          3377
+#define MACH_TYPE_XILINX_EP107         3378
+#define MACH_TYPE_NURI                 3379
+#define MACH_TYPE_JANUS                3380
+#define MACH_TYPE_DDNAS                3381
+#define MACH_TYPE_TAG                  3382
+#define MACH_TYPE_TAGW                 3383
+#define MACH_TYPE_NITROGEN_VM_IMX51    3384
+#define MACH_TYPE_VIPRINET             3385
+#define MACH_TYPE_BOCKW                3386
+#define MACH_TYPE_EVA2000              3387
+#define MACH_TYPE_STEELYARD            3388
+#define MACH_TYPE_MACH_SDH001          3390
+#define MACH_TYPE_NSSLSBOARD           3392
+#define MACH_TYPE_GENEVA_B5            3393
+#define MACH_TYPE_SPEAR1340            3394
+#define MACH_TYPE_REXMAS               3395
+#define MACH_TYPE_MSM8960_CDP          3396
+#define MACH_TYPE_MSM8960_MDP          3397
+#define MACH_TYPE_MSM8960_FLUID        3398
+#define MACH_TYPE_MSM8960_APQ          3399
+#define MACH_TYPE_HELIOS_V2            3400
+#define MACH_TYPE_MIF10P               3401
+#define MACH_TYPE_IAM28                3402
+#define MACH_TYPE_PICASSO              3403
+#define MACH_TYPE_MR301A               3404
+#define MACH_TYPE_NOTLE                3405
+#define MACH_TYPE_EELX2                3406
+#define MACH_TYPE_MOON                 3407
+#define MACH_TYPE_RUBY                 3408
+#define MACH_TYPE_GOLDENGATE           3409
+#define MACH_TYPE_CTBU_GEN2            3410
+#define MACH_TYPE_KMP_AM17_01          3411
+#define MACH_TYPE_WTPLUG               3412
+#define MACH_TYPE_MX27SU2              3413
+#define MACH_TYPE_NB31                 3414
+#define MACH_TYPE_HJSDU                3415
+#define MACH_TYPE_TD3_REV1             3416
+#define MACH_TYPE_EAG_CI4000           3417
+#define MACH_TYPE_NET5BIG_NAND_V2      3418
+#define MACH_TYPE_CPX2                 3419
+#define MACH_TYPE_NET2BIG_NAND_V2      3420
+#define MACH_TYPE_ECUV5                3421
+#define MACH_TYPE_HSGX6D               3422
+#define MACH_TYPE_DAWAD7               3423
+#define MACH_TYPE_SAM9REPEATER         3424
+#define MACH_TYPE_GT_I5700             3425
+#define MACH_TYPE_CTERA_PLUG_C2        3426
+#define MACH_TYPE_MARVELCT             3427
+#define MACH_TYPE_AG11005              3428
+#define MACH_TYPE_VANGOGH              3430
+#define MACH_TYPE_MATRIX505            3431
+#define MACH_TYPE_OCE_NIGMA            3432
+#define MACH_TYPE_T55                  3433
+#define MACH_TYPE_BIO3K                3434
+#define MACH_TYPE_EXPRESSCT            3435
+#define MACH_TYPE_CARDHU               3436
+#define MACH_TYPE_ARUBA                3437
+#define MACH_TYPE_BONAIRE              3438
+#define MACH_TYPE_NUC700EVB            3439
+#define MACH_TYPE_NUC710EVB            3440
+#define MACH_TYPE_NUC740EVB            3441
+#define MACH_TYPE_NUC745EVB            3442
+#define MACH_TYPE_TRANSCEDE            3443
+#define MACH_TYPE_MORA                 3444
+#define MACH_TYPE_NDA_EVM              3445
+#define MACH_TYPE_TIMU                 3446
+#define MACH_TYPE_EXPRESSH             3447
+#define MACH_TYPE_VERIDIS_A300         3448
+#define MACH_TYPE_DM368_LEOPARD        3449
+#define MACH_TYPE_OMAP_MCOP            3450
+#define MACH_TYPE_TRITIP               3451
+#define MACH_TYPE_SM1K                 3452
+#define MACH_TYPE_MONCH                3453
+#define MACH_TYPE_CURACAO              3454
+#define MACH_TYPE_ORIGEN               3455
+#define MACH_TYPE_EPC10                3456
+#define MACH_TYPE_SGH_I740             3457
+#define MACH_TYPE_TUNA                 3458
+#define MACH_TYPE_MX51_TULIP           3459
+#define MACH_TYPE_MX51_ASTER7          3460
+#define MACH_TYPE_ACRO37XBRD           3461
+#define MACH_TYPE_ELKE                 3462
+#define MACH_TYPE_SBC6000X             3463
+#define MACH_TYPE_R1801E               3464
+#define MACH_TYPE_H1600                3465
+#define MACH_TYPE_MINI210              3466
+#define MACH_TYPE_MINI8168             3467
+#define MACH_TYPE_PC7308               3468
+#define MACH_TYPE_KMM2M01              3470
+#define MACH_TYPE_MX51EREBUS           3471
+#define MACH_TYPE_WM8650REFBOARD       3472
+#define MACH_TYPE_TUXRAIL              3473
+#define MACH_TYPE_ARTHUR               3474
+#define MACH_TYPE_DOORBOY              3475
+#define MACH_TYPE_XARINA               3476
+#define MACH_TYPE_ROVERX7              3477
+#define MACH_TYPE_SDVR                 3478
+#define MACH_TYPE_ACER_MAYA            3479
+#define MACH_TYPE_PICO                 3480
+#define MACH_TYPE_CWMX233              3481
+#define MACH_TYPE_CWAM1808             3482
+#define MACH_TYPE_CWDM365              3483
+#define MACH_TYPE_MX51_MORAY           3484
+#define MACH_TYPE_THALES_CBC           3485
+#define MACH_TYPE_BLUEPOINT            3486
+#define MACH_TYPE_DIR665               3487
+#define MACH_TYPE_ACMEROVER1           3488
+#define MACH_TYPE_SHOOTER_CT           3489
+#define MACH_TYPE_BLISS                3490
+#define MACH_TYPE_BLISSC               3491
+#define MACH_TYPE_THALES_ADC           3492
+#define MACH_TYPE_UBISYS_P9D_EVP       3493
+#define MACH_TYPE_ATDGP318             3494
+#define MACH_TYPE_OMAP5_SEVM           3777
+#define MACH_TYPE_ARMADILLO_800EVA     3863
+#define MACH_TYPE_KZM9G                4140
+
+#ifdef CONFIG_ARCH_EBSA110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EBSA110
+# endif
+# define machine_is_ebsa110()	(machine_arch_type == MACH_TYPE_EBSA110)
+#else
+# define machine_is_ebsa110()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_RPC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RISCPC
+# endif
+# define machine_is_riscpc()	(machine_arch_type == MACH_TYPE_RISCPC)
+#else
+# define machine_is_riscpc()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_EBSA285
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EBSA285
+# endif
+# define machine_is_ebsa285()	(machine_arch_type == MACH_TYPE_EBSA285)
+#else
+# define machine_is_ebsa285()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NETWINDER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETWINDER
+# endif
+# define machine_is_netwinder()	(machine_arch_type == MACH_TYPE_NETWINDER)
+#else
+# define machine_is_netwinder()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CATS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CATS
+# endif
+# define machine_is_cats()	(machine_arch_type == MACH_TYPE_CATS)
+#else
+# define machine_is_cats()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SHARK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHARK
+# endif
+# define machine_is_shark()	(machine_arch_type == MACH_TYPE_SHARK)
+#else
+# define machine_is_shark()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BRUTUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BRUTUS
+# endif
+# define machine_is_brutus()	(machine_arch_type == MACH_TYPE_BRUTUS)
+#else
+# define machine_is_brutus()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PERSONAL_SERVER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PERSONAL_SERVER
+# endif
+# define machine_is_personal_server()	(machine_arch_type == MACH_TYPE_PERSONAL_SERVER)
+#else
+# define machine_is_personal_server()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_L7200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_L7200
+# endif
+# define machine_is_l7200()	(machine_arch_type == MACH_TYPE_L7200)
+#else
+# define machine_is_l7200()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_PLEB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PLEB
+# endif
+# define machine_is_pleb()	(machine_arch_type == MACH_TYPE_PLEB)
+#else
+# define machine_is_pleb()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_INTEGRATOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INTEGRATOR
+# endif
+# define machine_is_integrator()	(machine_arch_type == MACH_TYPE_INTEGRATOR)
+#else
+# define machine_is_integrator()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_H3600
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H3600
+# endif
+# define machine_is_h3600()	(machine_arch_type == MACH_TYPE_H3600)
+#else
+# define machine_is_h3600()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_P720T
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_P720T
+# endif
+# define machine_is_p720t()	(machine_arch_type == MACH_TYPE_P720T)
+#else
+# define machine_is_p720t()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ASSABET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASSABET
+# endif
+# define machine_is_assabet()	(machine_arch_type == MACH_TYPE_ASSABET)
+#else
+# define machine_is_assabet()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_LART
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LART
+# endif
+# define machine_is_lart()	(machine_arch_type == MACH_TYPE_LART)
+#else
+# define machine_is_lart()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_GRAPHICSCLIENT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GRAPHICSCLIENT
+# endif
+# define machine_is_graphicsclient()	(machine_arch_type == MACH_TYPE_GRAPHICSCLIENT)
+#else
+# define machine_is_graphicsclient()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_XP860
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XP860
+# endif
+# define machine_is_xp860()	(machine_arch_type == MACH_TYPE_XP860)
+#else
+# define machine_is_xp860()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_CERF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CERF
+# endif
+# define machine_is_cerf()	(machine_arch_type == MACH_TYPE_CERF)
+#else
+# define machine_is_cerf()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_NANOENGINE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NANOENGINE
+# endif
+# define machine_is_nanoengine()	(machine_arch_type == MACH_TYPE_NANOENGINE)
+#else
+# define machine_is_nanoengine()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_JORNADA720
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JORNADA720
+# endif
+# define machine_is_jornada720()	(machine_arch_type == MACH_TYPE_JORNADA720)
+#else
+# define machine_is_jornada720()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_EDB7211
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB7211
+# endif
+# define machine_is_edb7211()	(machine_arch_type == MACH_TYPE_EDB7211)
+#else
+# define machine_is_edb7211()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_PFS168
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PFS168
+# endif
+# define machine_is_pfs168()	(machine_arch_type == MACH_TYPE_PFS168)
+#else
+# define machine_is_pfs168()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_FLEXANET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FLEXANET
+# endif
+# define machine_is_flexanet()	(machine_arch_type == MACH_TYPE_FLEXANET)
+#else
+# define machine_is_flexanet()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SIMPAD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIMPAD
+# endif
+# define machine_is_simpad()	(machine_arch_type == MACH_TYPE_SIMPAD)
+#else
+# define machine_is_simpad()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_LUBBOCK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LUBBOCK
+# endif
+# define machine_is_lubbock()	(machine_arch_type == MACH_TYPE_LUBBOCK)
+#else
+# define machine_is_lubbock()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CLEP7212
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CLEP7212
+# endif
+# define machine_is_clep7212()	(machine_arch_type == MACH_TYPE_CLEP7212)
+#else
+# define machine_is_clep7212()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SHANNON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHANNON
+# endif
+# define machine_is_shannon()	(machine_arch_type == MACH_TYPE_SHANNON)
+#else
+# define machine_is_shannon()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_CONSUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CONSUS
+# endif
+# define machine_is_consus()	(machine_arch_type == MACH_TYPE_CONSUS)
+#else
+# define machine_is_consus()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AAED2000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AAED2000
+# endif
+# define machine_is_aaed2000()	(machine_arch_type == MACH_TYPE_AAED2000)
+#else
+# define machine_is_aaed2000()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CDB89712
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CDB89712
+# endif
+# define machine_is_cdb89712()	(machine_arch_type == MACH_TYPE_CDB89712)
+#else
+# define machine_is_cdb89712()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_GRAPHICSMASTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GRAPHICSMASTER
+# endif
+# define machine_is_graphicsmaster()	(machine_arch_type == MACH_TYPE_GRAPHICSMASTER)
+#else
+# define machine_is_graphicsmaster()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ADSBITSY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSBITSY
+# endif
+# define machine_is_adsbitsy()	(machine_arch_type == MACH_TYPE_ADSBITSY)
+#else
+# define machine_is_adsbitsy()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_IDP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_IDP
+# endif
+# define machine_is_pxa_idp()	(machine_arch_type == MACH_TYPE_PXA_IDP)
+#else
+# define machine_is_pxa_idp()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_PT_SYSTEM3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PT_SYSTEM3
+# endif
+# define machine_is_pt_system3()	(machine_arch_type == MACH_TYPE_PT_SYSTEM3)
+#else
+# define machine_is_pt_system3()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AUTCPU12
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AUTCPU12
+# endif
+# define machine_is_autcpu12()	(machine_arch_type == MACH_TYPE_AUTCPU12)
+#else
+# define machine_is_autcpu12()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_H3100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H3100
+# endif
+# define machine_is_h3100()	(machine_arch_type == MACH_TYPE_H3100)
+#else
+# define machine_is_h3100()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_COLLIE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COLLIE
+# endif
+# define machine_is_collie()	(machine_arch_type == MACH_TYPE_COLLIE)
+#else
+# define machine_is_collie()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BADGE4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BADGE4
+# endif
+# define machine_is_badge4()	(machine_arch_type == MACH_TYPE_BADGE4)
+#else
+# define machine_is_badge4()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_FORTUNET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FORTUNET
+# endif
+# define machine_is_fortunet()	(machine_arch_type == MACH_TYPE_FORTUNET)
+#else
+# define machine_is_fortunet()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_MX1ADS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX1ADS
+# endif
+# define machine_is_mx1ads()	(machine_arch_type == MACH_TYPE_MX1ADS)
+#else
+# define machine_is_mx1ads()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H7201
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H7201
+# endif
+# define machine_is_h7201()	(machine_arch_type == MACH_TYPE_H7201)
+#else
+# define machine_is_h7201()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H7202
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H7202
+# endif
+# define machine_is_h7202()	(machine_arch_type == MACH_TYPE_H7202)
+#else
+# define machine_is_h7202()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IQ80321
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ80321
+# endif
+# define machine_is_iq80321()	(machine_arch_type == MACH_TYPE_IQ80321)
+#else
+# define machine_is_iq80321()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_KS8695
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KS8695
+# endif
+# define machine_is_ks8695()	(machine_arch_type == MACH_TYPE_KS8695)
+#else
+# define machine_is_ks8695()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SMDK2410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK2410
+# endif
+# define machine_is_smdk2410()	(machine_arch_type == MACH_TYPE_SMDK2410)
+#else
+# define machine_is_smdk2410()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CEIVA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CEIVA
+# endif
+# define machine_is_ceiva()	(machine_arch_type == MACH_TYPE_CEIVA)
+#else
+# define machine_is_ceiva()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VOICEBLUE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VOICEBLUE
+# endif
+# define machine_is_voiceblue()	(machine_arch_type == MACH_TYPE_VOICEBLUE)
+#else
+# define machine_is_voiceblue()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H5400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H5400
+# endif
+# define machine_is_h5400()	(machine_arch_type == MACH_TYPE_H5400)
+#else
+# define machine_is_h5400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_INNOVATOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_INNOVATOR
+# endif
+# define machine_is_omap_innovator()	(machine_arch_type == MACH_TYPE_OMAP_INNOVATOR)
+#else
+# define machine_is_omap_innovator()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXDP2400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP2400
+# endif
+# define machine_is_ixdp2400()	(machine_arch_type == MACH_TYPE_IXDP2400)
+#else
+# define machine_is_ixdp2400()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXDP2800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP2800
+# endif
+# define machine_is_ixdp2800()	(machine_arch_type == MACH_TYPE_IXDP2800)
+#else
+# define machine_is_ixdp2800()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXDP425
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP425
+# endif
+# define machine_is_ixdp425()	(machine_arch_type == MACH_TYPE_IXDP425)
+#else
+# define machine_is_ixdp425()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_HACKKIT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HACKKIT
+# endif
+# define machine_is_hackkit()	(machine_arch_type == MACH_TYPE_HACKKIT)
+#else
+# define machine_is_hackkit()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXCDP1100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXCDP1100
+# endif
+# define machine_is_ixcdp1100()	(machine_arch_type == MACH_TYPE_IXCDP1100)
+#else
+# define machine_is_ixcdp1100()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91RM9200DK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91RM9200DK
+# endif
+# define machine_is_at91rm9200dk()	(machine_arch_type == MACH_TYPE_AT91RM9200DK)
+#else
+# define machine_is_at91rm9200dk()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CINTEGRATOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CINTEGRATOR
+# endif
+# define machine_is_cintegrator()	(machine_arch_type == MACH_TYPE_CINTEGRATOR)
+#else
+# define machine_is_cintegrator()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_VIPER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VIPER
+# endif
+# define machine_is_viper()	(machine_arch_type == MACH_TYPE_VIPER)
+#else
+# define machine_is_viper()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ADI_COYOTE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADI_COYOTE
+# endif
+# define machine_is_adi_coyote()	(machine_arch_type == MACH_TYPE_ADI_COYOTE)
+#else
+# define machine_is_adi_coyote()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXDP2401
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP2401
+# endif
+# define machine_is_ixdp2401()	(machine_arch_type == MACH_TYPE_IXDP2401)
+#else
+# define machine_is_ixdp2401()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXDP2801
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP2801
+# endif
+# define machine_is_ixdp2801()	(machine_arch_type == MACH_TYPE_IXDP2801)
+#else
+# define machine_is_ixdp2801()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IQ31244
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ31244
+# endif
+# define machine_is_iq31244()	(machine_arch_type == MACH_TYPE_IQ31244)
+#else
+# define machine_is_iq31244()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_BAST
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BAST
+# endif
+# define machine_is_bast()	(machine_arch_type == MACH_TYPE_BAST)
+#else
+# define machine_is_bast()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H1940
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H1940
+# endif
+# define machine_is_h1940()	(machine_arch_type == MACH_TYPE_H1940)
+#else
+# define machine_is_h1940()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ENP2611
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ENP2611
+# endif
+# define machine_is_enp2611()	(machine_arch_type == MACH_TYPE_ENP2611)
+#else
+# define machine_is_enp2611()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_S3C2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C2440
+# endif
+# define machine_is_s3c2440()	(machine_arch_type == MACH_TYPE_S3C2440)
+#else
+# define machine_is_s3c2440()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_GUMSTIX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GUMSTIX
+# endif
+# define machine_is_gumstix()	(machine_arch_type == MACH_TYPE_GUMSTIX)
+#else
+# define machine_is_gumstix()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_H2
+# endif
+# define machine_is_omap_h2()	(machine_arch_type == MACH_TYPE_OMAP_H2)
+#else
+# define machine_is_omap_h2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E740
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E740
+# endif
+# define machine_is_e740()	(machine_arch_type == MACH_TYPE_E740)
+#else
+# define machine_is_e740()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IQ80331
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ80331
+# endif
+# define machine_is_iq80331()	(machine_arch_type == MACH_TYPE_IQ80331)
+#else
+# define machine_is_iq80331()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_VERSATILE_PB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VERSATILE_PB
+# endif
+# define machine_is_versatile_pb()	(machine_arch_type == MACH_TYPE_VERSATILE_PB)
+#else
+# define machine_is_versatile_pb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KEV7A400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KEV7A400
+# endif
+# define machine_is_kev7a400()	(machine_arch_type == MACH_TYPE_KEV7A400)
+#else
+# define machine_is_kev7a400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPD7A400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPD7A400
+# endif
+# define machine_is_lpd7a400()	(machine_arch_type == MACH_TYPE_LPD7A400)
+#else
+# define machine_is_lpd7a400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPD7A404
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPD7A404
+# endif
+# define machine_is_lpd7a404()	(machine_arch_type == MACH_TYPE_LPD7A404)
+#else
+# define machine_is_lpd7a404()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB337
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB337
+# endif
+# define machine_is_csb337()	(machine_arch_type == MACH_TYPE_CSB337)
+#else
+# define machine_is_csb337()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MAINSTONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MAINSTONE
+# endif
+# define machine_is_mainstone()	(machine_arch_type == MACH_TYPE_MAINSTONE)
+#else
+# define machine_is_mainstone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XCEP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XCEP
+# endif
+# define machine_is_xcep()	(machine_arch_type == MACH_TYPE_XCEP)
+#else
+# define machine_is_xcep()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARCOM_VULCAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARCOM_VULCAN
+# endif
+# define machine_is_arcom_vulcan()	(machine_arch_type == MACH_TYPE_ARCOM_VULCAN)
+#else
+# define machine_is_arcom_vulcan()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOMADIK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOMADIK
+# endif
+# define machine_is_nomadik()	(machine_arch_type == MACH_TYPE_NOMADIK)
+#else
+# define machine_is_nomadik()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CORGI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CORGI
+# endif
+# define machine_is_corgi()	(machine_arch_type == MACH_TYPE_CORGI)
+#else
+# define machine_is_corgi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_POODLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_POODLE
+# endif
+# define machine_is_poodle()	(machine_arch_type == MACH_TYPE_POODLE)
+#else
+# define machine_is_poodle()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMCORE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMCORE
+# endif
+# define machine_is_armcore()	(machine_arch_type == MACH_TYPE_ARMCORE)
+#else
+# define machine_is_armcore()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX31ADS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX31ADS
+# endif
+# define machine_is_mx31ads()	(machine_arch_type == MACH_TYPE_MX31ADS)
+#else
+# define machine_is_mx31ads()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HIMALAYA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HIMALAYA
+# endif
+# define machine_is_himalaya()	(machine_arch_type == MACH_TYPE_HIMALAYA)
+#else
+# define machine_is_himalaya()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9312
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9312
+# endif
+# define machine_is_edb9312()	(machine_arch_type == MACH_TYPE_EDB9312)
+#else
+# define machine_is_edb9312()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_GENERIC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_GENERIC
+# endif
+# define machine_is_omap_generic()	(machine_arch_type == MACH_TYPE_OMAP_GENERIC)
+#else
+# define machine_is_omap_generic()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9301
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9301
+# endif
+# define machine_is_edb9301()	(machine_arch_type == MACH_TYPE_EDB9301)
+#else
+# define machine_is_edb9301()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9315
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9315
+# endif
+# define machine_is_edb9315()	(machine_arch_type == MACH_TYPE_EDB9315)
+#else
+# define machine_is_edb9315()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VR1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VR1000
+# endif
+# define machine_is_vr1000()	(machine_arch_type == MACH_TYPE_VR1000)
+#else
+# define machine_is_vr1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_PERSEUS2
+# endif
+# define machine_is_omap_perseus2()	(machine_arch_type == MACH_TYPE_OMAP_PERSEUS2)
+#else
+# define machine_is_omap_perseus2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E800
+# endif
+# define machine_is_e800()	(machine_arch_type == MACH_TYPE_E800)
+#else
+# define machine_is_e800()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E750
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E750
+# endif
+# define machine_is_e750()	(machine_arch_type == MACH_TYPE_E750)
+#else
+# define machine_is_e750()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SCB9328
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCB9328
+# endif
+# define machine_is_scb9328()	(machine_arch_type == MACH_TYPE_SCB9328)
+#else
+# define machine_is_scb9328()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_H3
+# endif
+# define machine_is_omap_h3()	(machine_arch_type == MACH_TYPE_OMAP_H3)
+#else
+# define machine_is_omap_h3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_H4
+# endif
+# define machine_is_omap_h4()	(machine_arch_type == MACH_TYPE_OMAP_H4)
+#else
+# define machine_is_omap_h4()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_OSK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_OSK
+# endif
+# define machine_is_omap_osk()	(machine_arch_type == MACH_TYPE_OMAP_OSK)
+#else
+# define machine_is_omap_osk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOSA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOSA
+# endif
+# define machine_is_tosa()	(machine_arch_type == MACH_TYPE_TOSA)
+#else
+# define machine_is_tosa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AVILA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AVILA
+# endif
+# define machine_is_avila()	(machine_arch_type == MACH_TYPE_AVILA)
+#else
+# define machine_is_avila()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9302
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9302
+# endif
+# define machine_is_edb9302()	(machine_arch_type == MACH_TYPE_EDB9302)
+#else
+# define machine_is_edb9302()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HUSKY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HUSKY
+# endif
+# define machine_is_husky()	(machine_arch_type == MACH_TYPE_HUSKY)
+#else
+# define machine_is_husky()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHEPHERD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHEPHERD
+# endif
+# define machine_is_shepherd()	(machine_arch_type == MACH_TYPE_SHEPHERD)
+#else
+# define machine_is_shepherd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_H4700
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H4700
+# endif
+# define machine_is_h4700()	(machine_arch_type == MACH_TYPE_H4700)
+#else
+# define machine_is_h4700()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RX3715
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RX3715
+# endif
+# define machine_is_rx3715()	(machine_arch_type == MACH_TYPE_RX3715)
+#else
+# define machine_is_rx3715()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NSLU2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NSLU2
+# endif
+# define machine_is_nslu2()	(machine_arch_type == MACH_TYPE_NSLU2)
+#else
+# define machine_is_nslu2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E400
+# endif
+# define machine_is_e400()	(machine_arch_type == MACH_TYPE_E400)
+#else
+# define machine_is_e400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IXDPG425
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDPG425
+# endif
+# define machine_is_ixdpg425()	(machine_arch_type == MACH_TYPE_IXDPG425)
+#else
+# define machine_is_ixdpg425()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VERSATILE_AB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VERSATILE_AB
+# endif
+# define machine_is_versatile_ab()	(machine_arch_type == MACH_TYPE_VERSATILE_AB)
+#else
+# define machine_is_versatile_ab()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9307
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9307
+# endif
+# define machine_is_edb9307()	(machine_arch_type == MACH_TYPE_EDB9307)
+#else
+# define machine_is_edb9307()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KB9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KB9200
+# endif
+# define machine_is_kb9200()	(machine_arch_type == MACH_TYPE_KB9200)
+#else
+# define machine_is_kb9200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SX1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SX1
+# endif
+# define machine_is_sx1()	(machine_arch_type == MACH_TYPE_SX1)
+#else
+# define machine_is_sx1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IXDP465
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP465
+# endif
+# define machine_is_ixdp465()	(machine_arch_type == MACH_TYPE_IXDP465)
+#else
+# define machine_is_ixdp465()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IXDP2351
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP2351
+# endif
+# define machine_is_ixdp2351()	(machine_arch_type == MACH_TYPE_IXDP2351)
+#else
+# define machine_is_ixdp2351()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IQ80332
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ80332
+# endif
+# define machine_is_iq80332()	(machine_arch_type == MACH_TYPE_IQ80332)
+#else
+# define machine_is_iq80332()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GTWX5715
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GTWX5715
+# endif
+# define machine_is_gtwx5715()	(machine_arch_type == MACH_TYPE_GTWX5715)
+#else
+# define machine_is_gtwx5715()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB637
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB637
+# endif
+# define machine_is_csb637()	(machine_arch_type == MACH_TYPE_CSB637)
+#else
+# define machine_is_csb637()	(0)
+#endif
+
+#ifdef CONFIG_MACH_N30
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_N30
+# endif
+# define machine_is_n30()	(machine_arch_type == MACH_TYPE_N30)
+#else
+# define machine_is_n30()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NEC_MP900
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEC_MP900
+# endif
+# define machine_is_nec_mp900()	(machine_arch_type == MACH_TYPE_NEC_MP900)
+#else
+# define machine_is_nec_mp900()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KAFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KAFA
+# endif
+# define machine_is_kafa()	(machine_arch_type == MACH_TYPE_KAFA)
+#else
+# define machine_is_kafa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS72XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS72XX
+# endif
+# define machine_is_ts72xx()	(machine_arch_type == MACH_TYPE_TS72XX)
+#else
+# define machine_is_ts72xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OTOM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OTOM
+# endif
+# define machine_is_otom()	(machine_arch_type == MACH_TYPE_OTOM)
+#else
+# define machine_is_otom()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NEXCODER_2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEXCODER_2440
+# endif
+# define machine_is_nexcoder_2440()	(machine_arch_type == MACH_TYPE_NEXCODER_2440)
+#else
+# define machine_is_nexcoder_2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ECO920
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ECO920
+# endif
+# define machine_is_eco920()	(machine_arch_type == MACH_TYPE_ECO920)
+#else
+# define machine_is_eco920()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROADRUNNER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROADRUNNER
+# endif
+# define machine_is_roadrunner()	(machine_arch_type == MACH_TYPE_ROADRUNNER)
+#else
+# define machine_is_roadrunner()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91RM9200EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91RM9200EK
+# endif
+# define machine_is_at91rm9200ek()	(machine_arch_type == MACH_TYPE_AT91RM9200EK)
+#else
+# define machine_is_at91rm9200ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPITZ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPITZ
+# endif
+# define machine_is_spitz()	(machine_arch_type == MACH_TYPE_SPITZ)
+#else
+# define machine_is_spitz()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ADSSPHERE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSSPHERE
+# endif
+# define machine_is_adssphere()	(machine_arch_type == MACH_TYPE_ADSSPHERE)
+#else
+# define machine_is_adssphere()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COLIBRI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COLIBRI
+# endif
+# define machine_is_colibri()	(machine_arch_type == MACH_TYPE_COLIBRI)
+#else
+# define machine_is_colibri()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GATEWAY7001
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GATEWAY7001
+# endif
+# define machine_is_gateway7001()	(machine_arch_type == MACH_TYPE_GATEWAY7001)
+#else
+# define machine_is_gateway7001()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM027
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM027
+# endif
+# define machine_is_pcm027()	(machine_arch_type == MACH_TYPE_PCM027)
+#else
+# define machine_is_pcm027()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ANUBIS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ANUBIS
+# endif
+# define machine_is_anubis()	(machine_arch_type == MACH_TYPE_ANUBIS)
+#else
+# define machine_is_anubis()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AKITA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AKITA
+# endif
+# define machine_is_akita()	(machine_arch_type == MACH_TYPE_AKITA)
+#else
+# define machine_is_akita()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E330
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E330
+# endif
+# define machine_is_e330()	(machine_arch_type == MACH_TYPE_E330)
+#else
+# define machine_is_e330()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOKIA770
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOKIA770
+# endif
+# define machine_is_nokia770()	(machine_arch_type == MACH_TYPE_NOKIA770)
+#else
+# define machine_is_nokia770()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CARMEVA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CARMEVA
+# endif
+# define machine_is_carmeva()	(machine_arch_type == MACH_TYPE_CARMEVA)
+#else
+# define machine_is_carmeva()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9315A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9315A
+# endif
+# define machine_is_edb9315a()	(machine_arch_type == MACH_TYPE_EDB9315A)
+#else
+# define machine_is_edb9315a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STARGATE2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STARGATE2
+# endif
+# define machine_is_stargate2()	(machine_arch_type == MACH_TYPE_STARGATE2)
+#else
+# define machine_is_stargate2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_INTELMOTE2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INTELMOTE2
+# endif
+# define machine_is_intelmote2()	(machine_arch_type == MACH_TYPE_INTELMOTE2)
+#else
+# define machine_is_intelmote2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRIZEPS4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRIZEPS4
+# endif
+# define machine_is_trizeps4()	(machine_arch_type == MACH_TYPE_TRIZEPS4)
+#else
+# define machine_is_trizeps4()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PNX4008
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PNX4008
+# endif
+# define machine_is_pnx4008()	(machine_arch_type == MACH_TYPE_PNX4008)
+#else
+# define machine_is_pnx4008()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPUAT91
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPUAT91
+# endif
+# define machine_is_cpuat91()	(machine_arch_type == MACH_TYPE_CPUAT91)
+#else
+# define machine_is_cpuat91()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IQ81340SC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ81340SC
+# endif
+# define machine_is_iq81340sc()	(machine_arch_type == MACH_TYPE_IQ81340SC)
+#else
+# define machine_is_iq81340sc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IQ81340MC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ81340MC
+# endif
+# define machine_is_iq81340mc()	(machine_arch_type == MACH_TYPE_IQ81340MC)
+#else
+# define machine_is_iq81340mc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MICRO9
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MICRO9
+# endif
+# define machine_is_micro9()	(machine_arch_type == MACH_TYPE_MICRO9)
+#else
+# define machine_is_micro9()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MICRO9L
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MICRO9L
+# endif
+# define machine_is_micro9l()	(machine_arch_type == MACH_TYPE_MICRO9L)
+#else
+# define machine_is_micro9l()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PALMTE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_PALMTE
+# endif
+# define machine_is_omap_palmte()	(machine_arch_type == MACH_TYPE_OMAP_PALMTE)
+#else
+# define machine_is_omap_palmte()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REALVIEW_EB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REALVIEW_EB
+# endif
+# define machine_is_realview_eb()	(machine_arch_type == MACH_TYPE_REALVIEW_EB)
+#else
+# define machine_is_realview_eb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BORZOI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BORZOI
+# endif
+# define machine_is_borzoi()	(machine_arch_type == MACH_TYPE_BORZOI)
+#else
+# define machine_is_borzoi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PALMLD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PALMLD
+# endif
+# define machine_is_palmld()	(machine_arch_type == MACH_TYPE_PALMLD)
+#else
+# define machine_is_palmld()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IXDP28X5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP28X5
+# endif
+# define machine_is_ixdp28x5()	(machine_arch_type == MACH_TYPE_IXDP28X5)
+#else
+# define machine_is_ixdp28x5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PALMTT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_PALMTT
+# endif
+# define machine_is_omap_palmtt()	(machine_arch_type == MACH_TYPE_OMAP_PALMTT)
+#else
+# define machine_is_omap_palmtt()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARCOM_ZEUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARCOM_ZEUS
+# endif
+# define machine_is_arcom_zeus()	(machine_arch_type == MACH_TYPE_ARCOM_ZEUS)
+#else
+# define machine_is_arcom_zeus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OSIRIS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OSIRIS
+# endif
+# define machine_is_osiris()	(machine_arch_type == MACH_TYPE_OSIRIS)
+#else
+# define machine_is_osiris()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PALMTE2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PALMTE2
+# endif
+# define machine_is_palmte2()	(machine_arch_type == MACH_TYPE_PALMTE2)
+#else
+# define machine_is_palmte2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX27ADS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX27ADS
+# endif
+# define machine_is_mx27ads()	(machine_arch_type == MACH_TYPE_MX27ADS)
+#else
+# define machine_is_mx27ads()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9261EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9261EK
+# endif
+# define machine_is_at91sam9261ek()	(machine_arch_type == MACH_TYPE_AT91SAM9261EK)
+#else
+# define machine_is_at91sam9261ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LOFT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LOFT
+# endif
+# define machine_is_loft()	(machine_arch_type == MACH_TYPE_LOFT)
+#else
+# define machine_is_loft()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX21ADS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX21ADS
+# endif
+# define machine_is_mx21ads()	(machine_arch_type == MACH_TYPE_MX21ADS)
+#else
+# define machine_is_mx21ads()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AMS_DELTA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AMS_DELTA
+# endif
+# define machine_is_ams_delta()	(machine_arch_type == MACH_TYPE_AMS_DELTA)
+#else
+# define machine_is_ams_delta()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NAS100D
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NAS100D
+# endif
+# define machine_is_nas100d()	(machine_arch_type == MACH_TYPE_NAS100D)
+#else
+# define machine_is_nas100d()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MAGICIAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MAGICIAN
+# endif
+# define machine_is_magician()	(machine_arch_type == MACH_TYPE_MAGICIAN)
+#else
+# define machine_is_magician()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NXDKN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NXDKN
+# endif
+# define machine_is_nxdkn()	(machine_arch_type == MACH_TYPE_NXDKN)
+#else
+# define machine_is_nxdkn()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PALMTX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PALMTX
+# endif
+# define machine_is_palmtx()	(machine_arch_type == MACH_TYPE_PALMTX)
+#else
+# define machine_is_palmtx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S3C2413
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C2413
+# endif
+# define machine_is_s3c2413()	(machine_arch_type == MACH_TYPE_S3C2413)
+#else
+# define machine_is_s3c2413()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WG302V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WG302V2
+# endif
+# define machine_is_wg302v2()	(machine_arch_type == MACH_TYPE_WG302V2)
+#else
+# define machine_is_wg302v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_2430SDP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_2430SDP
+# endif
+# define machine_is_omap_2430sdp()	(machine_arch_type == MACH_TYPE_OMAP_2430SDP)
+#else
+# define machine_is_omap_2430sdp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_EVM
+# endif
+# define machine_is_davinci_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_EVM)
+#else
+# define machine_is_davinci_evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PALMZ72
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PALMZ72
+# endif
+# define machine_is_palmz72()	(machine_arch_type == MACH_TYPE_PALMZ72)
+#else
+# define machine_is_palmz72()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NXDB500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NXDB500
+# endif
+# define machine_is_nxdb500()	(machine_arch_type == MACH_TYPE_NXDB500)
+#else
+# define machine_is_nxdb500()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PALMT5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PALMT5
+# endif
+# define machine_is_palmt5()	(machine_arch_type == MACH_TYPE_PALMT5)
+#else
+# define machine_is_palmt5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PALMTC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PALMTC
+# endif
+# define machine_is_palmtc()	(machine_arch_type == MACH_TYPE_PALMTC)
+#else
+# define machine_is_palmtc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_APOLLON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_APOLLON
+# endif
+# define machine_is_omap_apollon()	(machine_arch_type == MACH_TYPE_OMAP_APOLLON)
+#else
+# define machine_is_omap_apollon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ATEB9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ATEB9200
+# endif
+# define machine_is_ateb9200()	(machine_arch_type == MACH_TYPE_ATEB9200)
+#else
+# define machine_is_ateb9200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_N35
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_N35
+# endif
+# define machine_is_n35()	(machine_arch_type == MACH_TYPE_N35)
+#else
+# define machine_is_n35()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LOGICPD_PXA270
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LOGICPD_PXA270
+# endif
+# define machine_is_logicpd_pxa270()	(machine_arch_type == MACH_TYPE_LOGICPD_PXA270)
+#else
+# define machine_is_logicpd_pxa270()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NXEB500HMI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NXEB500HMI
+# endif
+# define machine_is_nxeb500hmi()	(machine_arch_type == MACH_TYPE_NXEB500HMI)
+#else
+# define machine_is_nxeb500hmi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESPRESSO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESPRESSO
+# endif
+# define machine_is_espresso()	(machine_arch_type == MACH_TYPE_ESPRESSO)
+#else
+# define machine_is_espresso()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RX1950
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RX1950
+# endif
+# define machine_is_rx1950()	(machine_arch_type == MACH_TYPE_RX1950)
+#else
+# define machine_is_rx1950()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GESBC9312
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GESBC9312
+# endif
+# define machine_is_gesbc9312()	(machine_arch_type == MACH_TYPE_GESBC9312)
+#else
+# define machine_is_gesbc9312()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PICOTUX2XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PICOTUX2XX
+# endif
+# define machine_is_picotux2xx()	(machine_arch_type == MACH_TYPE_PICOTUX2XX)
+#else
+# define machine_is_picotux2xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DSMG600
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DSMG600
+# endif
+# define machine_is_dsmg600()	(machine_arch_type == MACH_TYPE_DSMG600)
+#else
+# define machine_is_dsmg600()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_FSAMPLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_FSAMPLE
+# endif
+# define machine_is_omap_fsample()	(machine_arch_type == MACH_TYPE_OMAP_FSAMPLE)
+#else
+# define machine_is_omap_fsample()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SNAPPER_CL15
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SNAPPER_CL15
+# endif
+# define machine_is_snapper_cl15()	(machine_arch_type == MACH_TYPE_SNAPPER_CL15)
+#else
+# define machine_is_snapper_cl15()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PALMZ71
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_PALMZ71
+# endif
+# define machine_is_omap_palmz71()	(machine_arch_type == MACH_TYPE_OMAP_PALMZ71)
+#else
+# define machine_is_omap_palmz71()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK2412
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK2412
+# endif
+# define machine_is_smdk2412()	(machine_arch_type == MACH_TYPE_SMDK2412)
+#else
+# define machine_is_smdk2412()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK2413
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK2413
+# endif
+# define machine_is_smdk2413()	(machine_arch_type == MACH_TYPE_SMDK2413)
+#else
+# define machine_is_smdk2413()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AML_M5900
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AML_M5900
+# endif
+# define machine_is_aml_m5900()	(machine_arch_type == MACH_TYPE_AML_M5900)
+#else
+# define machine_is_aml_m5900()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BALLOON3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BALLOON3
+# endif
+# define machine_is_balloon3()	(machine_arch_type == MACH_TYPE_BALLOON3)
+#else
+# define machine_is_balloon3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ECBAT91
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ECBAT91
+# endif
+# define machine_is_ecbat91()	(machine_arch_type == MACH_TYPE_ECBAT91)
+#else
+# define machine_is_ecbat91()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ONEARM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ONEARM
+# endif
+# define machine_is_onearm()	(machine_arch_type == MACH_TYPE_ONEARM)
+#else
+# define machine_is_onearm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK2443
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK2443
+# endif
+# define machine_is_smdk2443()	(machine_arch_type == MACH_TYPE_SMDK2443)
+#else
+# define machine_is_smdk2443()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FSG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FSG
+# endif
+# define machine_is_fsg()	(machine_arch_type == MACH_TYPE_FSG)
+#else
+# define machine_is_fsg()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9260EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9260EK
+# endif
+# define machine_is_at91sam9260ek()	(machine_arch_type == MACH_TYPE_AT91SAM9260EK)
+#else
+# define machine_is_at91sam9260ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GLANTANK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GLANTANK
+# endif
+# define machine_is_glantank()	(machine_arch_type == MACH_TYPE_GLANTANK)
+#else
+# define machine_is_glantank()	(0)
+#endif
+
+#ifdef CONFIG_MACH_N2100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_N2100
+# endif
+# define machine_is_n2100()	(machine_arch_type == MACH_TYPE_N2100)
+#else
+# define machine_is_n2100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QT2410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QT2410
+# endif
+# define machine_is_qt2410()	(machine_arch_type == MACH_TYPE_QT2410)
+#else
+# define machine_is_qt2410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KIXRP435
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KIXRP435
+# endif
+# define machine_is_kixrp435()	(machine_arch_type == MACH_TYPE_KIXRP435)
+#else
+# define machine_is_kixrp435()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CC9P9360DEV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CC9P9360DEV
+# endif
+# define machine_is_cc9p9360dev()	(machine_arch_type == MACH_TYPE_CC9P9360DEV)
+#else
+# define machine_is_cc9p9360dev()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9302A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9302A
+# endif
+# define machine_is_edb9302a()	(machine_arch_type == MACH_TYPE_EDB9302A)
+#else
+# define machine_is_edb9302a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9307A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9307A
+# endif
+# define machine_is_edb9307a()	(machine_arch_type == MACH_TYPE_EDB9307A)
+#else
+# define machine_is_edb9307a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_3430SDP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_3430SDP
+# endif
+# define machine_is_omap_3430sdp()	(machine_arch_type == MACH_TYPE_OMAP_3430SDP)
+#else
+# define machine_is_omap_3430sdp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VSTMS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VSTMS
+# endif
+# define machine_is_vstms()	(machine_arch_type == MACH_TYPE_VSTMS)
+#else
+# define machine_is_vstms()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MICRO9M
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MICRO9M
+# endif
+# define machine_is_micro9m()	(machine_arch_type == MACH_TYPE_MICRO9M)
+#else
+# define machine_is_micro9m()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BUG
+# endif
+# define machine_is_bug()	(machine_arch_type == MACH_TYPE_BUG)
+#else
+# define machine_is_bug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9263EK
+# endif
+# define machine_is_at91sam9263ek()	(machine_arch_type == MACH_TYPE_AT91SAM9263EK)
+#else
+# define machine_is_at91sam9263ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EM7210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EM7210
+# endif
+# define machine_is_em7210()	(machine_arch_type == MACH_TYPE_EM7210)
+#else
+# define machine_is_em7210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VPAC270
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VPAC270
+# endif
+# define machine_is_vpac270()	(machine_arch_type == MACH_TYPE_VPAC270)
+#else
+# define machine_is_vpac270()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TREO680
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TREO680
+# endif
+# define machine_is_treo680()	(machine_arch_type == MACH_TYPE_TREO680)
+#else
+# define machine_is_treo680()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZYLONITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZYLONITE
+# endif
+# define machine_is_zylonite()	(machine_arch_type == MACH_TYPE_ZYLONITE)
+#else
+# define machine_is_zylonite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX31LITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX31LITE
+# endif
+# define machine_is_mx31lite()	(machine_arch_type == MACH_TYPE_MX31LITE)
+#else
+# define machine_is_mx31lite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MIOA701
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MIOA701
+# endif
+# define machine_is_mioa701()	(machine_arch_type == MACH_TYPE_MIOA701)
+#else
+# define machine_is_mioa701()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADILLO5X0
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMADILLO5X0
+# endif
+# define machine_is_armadillo5x0()	(machine_arch_type == MACH_TYPE_ARMADILLO5X0)
+#else
+# define machine_is_armadillo5x0()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CC9P9360JS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CC9P9360JS
+# endif
+# define machine_is_cc9p9360js()	(machine_arch_type == MACH_TYPE_CC9P9360JS)
+#else
+# define machine_is_cc9p9360js()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOKIA_N800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOKIA_N800
+# endif
+# define machine_is_nokia_n800()	(machine_arch_type == MACH_TYPE_NOKIA_N800)
+#else
+# define machine_is_nokia_n800()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EP80219
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EP80219
+# endif
+# define machine_is_ep80219()	(machine_arch_type == MACH_TYPE_EP80219)
+#else
+# define machine_is_ep80219()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GORAMO_MLR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GORAMO_MLR
+# endif
+# define machine_is_goramo_mlr()	(machine_arch_type == MACH_TYPE_GORAMO_MLR)
+#else
+# define machine_is_goramo_mlr()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EM_X270
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EM_X270
+# endif
+# define machine_is_em_x270()	(machine_arch_type == MACH_TYPE_EM_X270)
+#else
+# define machine_is_em_x270()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEO1973_GTA02
+# endif
+# define machine_is_neo1973_gta02()	(machine_arch_type == MACH_TYPE_NEO1973_GTA02)
+#else
+# define machine_is_neo1973_gta02()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9RLEK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9RLEK
+# endif
+# define machine_is_at91sam9rlek()	(machine_arch_type == MACH_TYPE_AT91SAM9RLEK)
+#else
+# define machine_is_at91sam9rlek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COLIBRI320
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COLIBRI320
+# endif
+# define machine_is_colibri320()	(machine_arch_type == MACH_TYPE_COLIBRI320)
+#else
+# define machine_is_colibri320()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CAM60
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CAM60
+# endif
+# define machine_is_cam60()	(machine_arch_type == MACH_TYPE_CAM60)
+#else
+# define machine_is_cam60()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91EB01
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91EB01
+# endif
+# define machine_is_at91eb01()	(machine_arch_type == MACH_TYPE_AT91EB01)
+#else
+# define machine_is_at91eb01()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DB88F5281
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DB88F5281
+# endif
+# define machine_is_db88f5281()	(machine_arch_type == MACH_TYPE_DB88F5281)
+#else
+# define machine_is_db88f5281()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB726
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB726
+# endif
+# define machine_is_csb726()	(machine_arch_type == MACH_TYPE_CSB726)
+#else
+# define machine_is_csb726()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM6467_EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM6467_EVM
+# endif
+# define machine_is_davinci_dm6467_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM6467_EVM)
+#else
+# define machine_is_davinci_dm6467_evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM355_EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM355_EVM
+# endif
+# define machine_is_davinci_dm355_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM)
+#else
+# define machine_is_davinci_dm355_evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LITTLETON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LITTLETON
+# endif
+# define machine_is_littleton()	(machine_arch_type == MACH_TYPE_LITTLETON)
+#else
+# define machine_is_littleton()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REALVIEW_PB11MP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REALVIEW_PB11MP
+# endif
+# define machine_is_realview_pb11mp()	(machine_arch_type == MACH_TYPE_REALVIEW_PB11MP)
+#else
+# define machine_is_realview_pb11mp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX27_3DS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX27_3DS
+# endif
+# define machine_is_mx27_3ds()	(machine_arch_type == MACH_TYPE_MX27_3DS)
+#else
+# define machine_is_mx27_3ds()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HALIBUT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HALIBUT
+# endif
+# define machine_is_halibut()	(machine_arch_type == MACH_TYPE_HALIBUT)
+#else
+# define machine_is_halibut()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TROUT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TROUT
+# endif
+# define machine_is_trout()	(machine_arch_type == MACH_TYPE_TROUT)
+#else
+# define machine_is_trout()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TCT_HAMMER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TCT_HAMMER
+# endif
+# define machine_is_tct_hammer()	(machine_arch_type == MACH_TYPE_TCT_HAMMER)
+#else
+# define machine_is_tct_hammer()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HERALD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HERALD
+# endif
+# define machine_is_herald()	(machine_arch_type == MACH_TYPE_HERALD)
+#else
+# define machine_is_herald()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SIM_ONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIM_ONE
+# endif
+# define machine_is_sim_one()	(machine_arch_type == MACH_TYPE_SIM_ONE)
+#else
+# define machine_is_sim_one()	(0)
+#endif
+
+#ifdef CONFIG_MACH_JIVE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JIVE
+# endif
+# define machine_is_jive()	(machine_arch_type == MACH_TYPE_JIVE)
+#else
+# define machine_is_jive()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SAM9_L9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SAM9_L9260
+# endif
+# define machine_is_sam9_l9260()	(machine_arch_type == MACH_TYPE_SAM9_L9260)
+#else
+# define machine_is_sam9_l9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REALVIEW_PB1176
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REALVIEW_PB1176
+# endif
+# define machine_is_realview_pb1176()	(machine_arch_type == MACH_TYPE_REALVIEW_PB1176)
+#else
+# define machine_is_realview_pb1176()	(0)
+#endif
+
+#ifdef CONFIG_MACH_YL9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_YL9200
+# endif
+# define machine_is_yl9200()	(machine_arch_type == MACH_TYPE_YL9200)
+#else
+# define machine_is_yl9200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RD88F5182
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RD88F5182
+# endif
+# define machine_is_rd88f5182()	(machine_arch_type == MACH_TYPE_RD88F5182)
+#else
+# define machine_is_rd88f5182()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KUROBOX_PRO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KUROBOX_PRO
+# endif
+# define machine_is_kurobox_pro()	(machine_arch_type == MACH_TYPE_KUROBOX_PRO)
+#else
+# define machine_is_kurobox_pro()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX31_3DS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX31_3DS
+# endif
+# define machine_is_mx31_3ds()	(machine_arch_type == MACH_TYPE_MX31_3DS)
+#else
+# define machine_is_mx31_3ds()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QONG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QONG
+# endif
+# define machine_is_qong()	(machine_arch_type == MACH_TYPE_QONG)
+#else
+# define machine_is_qong()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP2EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP2EVM
+# endif
+# define machine_is_omap2evm()	(machine_arch_type == MACH_TYPE_OMAP2EVM)
+#else
+# define machine_is_omap2evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3EVM
+# endif
+# define machine_is_omap3evm()	(machine_arch_type == MACH_TYPE_OMAP3EVM)
+#else
+# define machine_is_omap3evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DNS323
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DNS323
+# endif
+# define machine_is_dns323()	(machine_arch_type == MACH_TYPE_DNS323)
+#else
+# define machine_is_dns323()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_BEAGLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_BEAGLE
+# endif
+# define machine_is_omap3_beagle()	(machine_arch_type == MACH_TYPE_OMAP3_BEAGLE)
+#else
+# define machine_is_omap3_beagle()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOKIA_N810
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOKIA_N810
+# endif
+# define machine_is_nokia_n810()	(machine_arch_type == MACH_TYPE_NOKIA_N810)
+#else
+# define machine_is_nokia_n810()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM038
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM038
+# endif
+# define machine_is_pcm038()	(machine_arch_type == MACH_TYPE_PCM038)
+#else
+# define machine_is_pcm038()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS209
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS209
+# endif
+# define machine_is_ts_x09()	(machine_arch_type == MACH_TYPE_TS209)
+#else
+# define machine_is_ts_x09()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91CAP9ADK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91CAP9ADK
+# endif
+# define machine_is_at91cap9adk()	(machine_arch_type == MACH_TYPE_AT91CAP9ADK)
+#else
+# define machine_is_at91cap9adk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX31MOBOARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX31MOBOARD
+# endif
+# define machine_is_mx31moboard()	(machine_arch_type == MACH_TYPE_MX31MOBOARD)
+#else
+# define machine_is_mx31moboard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TERASTATION_PRO2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TERASTATION_PRO2
+# endif
+# define machine_is_terastation_pro2()	(machine_arch_type == MACH_TYPE_TERASTATION_PRO2)
+#else
+# define machine_is_terastation_pro2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LINKSTATION_PRO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LINKSTATION_PRO
+# endif
+# define machine_is_linkstation_pro()	(machine_arch_type == MACH_TYPE_LINKSTATION_PRO)
+#else
+# define machine_is_linkstation_pro()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E350
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E350
+# endif
+# define machine_is_e350()	(machine_arch_type == MACH_TYPE_E350)
+#else
+# define machine_is_e350()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS409
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS409
+# endif
+# define machine_is_ts409()	(machine_arch_type == MACH_TYPE_TS409)
+#else
+# define machine_is_ts409()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CM_X300
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CM_X300
+# endif
+# define machine_is_cm_x300()	(machine_arch_type == MACH_TYPE_CM_X300)
+#else
+# define machine_is_cm_x300()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G20EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9G20EK
+# endif
+# define machine_is_at91sam9g20ek()	(machine_arch_type == MACH_TYPE_AT91SAM9G20EK)
+#else
+# define machine_is_at91sam9g20ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK6410
+# endif
+# define machine_is_smdk6410()	(machine_arch_type == MACH_TYPE_SMDK6410)
+#else
+# define machine_is_smdk6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_U300
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_U300
+# endif
+# define machine_is_u300()	(machine_arch_type == MACH_TYPE_U300)
+#else
+# define machine_is_u300()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WRT350N_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WRT350N_V2
+# endif
+# define machine_is_wrt350n_v2()	(machine_arch_type == MACH_TYPE_WRT350N_V2)
+#else
+# define machine_is_wrt350n_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_LDP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_LDP
+# endif
+# define machine_is_omap_ldp()	(machine_arch_type == MACH_TYPE_OMAP_LDP)
+#else
+# define machine_is_omap_ldp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX35_3DS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX35_3DS
+# endif
+# define machine_is_mx35_3ds()	(machine_arch_type == MACH_TYPE_MX35_3DS)
+#else
+# define machine_is_mx35_3ds()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NEUROS_OSD2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEUROS_OSD2
+# endif
+# define machine_is_neuros_osd2()	(machine_arch_type == MACH_TYPE_NEUROS_OSD2)
+#else
+# define machine_is_neuros_osd2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRIZEPS4WL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRIZEPS4WL
+# endif
+# define machine_is_trizeps4wl()	(machine_arch_type == MACH_TYPE_TRIZEPS4WL)
+#else
+# define machine_is_trizeps4wl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS78XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS78XX
+# endif
+# define machine_is_ts78xx()	(machine_arch_type == MACH_TYPE_TS78XX)
+#else
+# define machine_is_ts78xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SFFSDR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SFFSDR
+# endif
+# define machine_is_sffsdr()	(machine_arch_type == MACH_TYPE_SFFSDR)
+#else
+# define machine_is_sffsdr()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM037
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM037
+# endif
+# define machine_is_pcm037()	(machine_arch_type == MACH_TYPE_PCM037)
+#else
+# define machine_is_pcm037()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DB88F6281_BP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DB88F6281_BP
+# endif
+# define machine_is_db88f6281_bp()	(machine_arch_type == MACH_TYPE_DB88F6281_BP)
+#else
+# define machine_is_db88f6281_bp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RD88F6192_NAS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RD88F6192_NAS
+# endif
+# define machine_is_rd88f6192_nas()	(machine_arch_type == MACH_TYPE_RD88F6192_NAS)
+#else
+# define machine_is_rd88f6192_nas()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RD88F6281
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RD88F6281
+# endif
+# define machine_is_rd88f6281()	(machine_arch_type == MACH_TYPE_RD88F6281)
+#else
+# define machine_is_rd88f6281()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DB78X00_BP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DB78X00_BP
+# endif
+# define machine_is_db78x00_bp()	(machine_arch_type == MACH_TYPE_DB78X00_BP)
+#else
+# define machine_is_db78x00_bp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK2416
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK2416
+# endif
+# define machine_is_smdk2416()	(machine_arch_type == MACH_TYPE_SMDK2416)
+#else
+# define machine_is_smdk2416()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WBD111
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WBD111
+# endif
+# define machine_is_wbd111()	(machine_arch_type == MACH_TYPE_WBD111)
+#else
+# define machine_is_wbd111()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MV2120
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MV2120
+# endif
+# define machine_is_mv2120()	(machine_arch_type == MACH_TYPE_MV2120)
+#else
+# define machine_is_mv2120()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_3DS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_3DS
+# endif
+# define machine_is_mx51_3ds()	(machine_arch_type == MACH_TYPE_MX51_3DS)
+#else
+# define machine_is_mx51_3ds()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IMX27LITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IMX27LITE
+# endif
+# define machine_is_imx27lite()	(machine_arch_type == MACH_TYPE_IMX27LITE)
+#else
+# define machine_is_imx27lite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_USB_A9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_USB_A9260
+# endif
+# define machine_is_usb_a9260()	(machine_arch_type == MACH_TYPE_USB_A9260)
+#else
+# define machine_is_usb_a9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_USB_A9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_USB_A9263
+# endif
+# define machine_is_usb_a9263()	(machine_arch_type == MACH_TYPE_USB_A9263)
+#else
+# define machine_is_usb_a9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QIL_A9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QIL_A9260
+# endif
+# define machine_is_qil_a9260()	(machine_arch_type == MACH_TYPE_QIL_A9260)
+#else
+# define machine_is_qil_a9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KZM_ARM11_01
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KZM_ARM11_01
+# endif
+# define machine_is_kzm_arm11_01()	(machine_arch_type == MACH_TYPE_KZM_ARM11_01)
+#else
+# define machine_is_kzm_arm11_01()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOKIA_N810_WIMAX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOKIA_N810_WIMAX
+# endif
+# define machine_is_nokia_n810_wimax()	(machine_arch_type == MACH_TYPE_NOKIA_N810_WIMAX)
+#else
+# define machine_is_nokia_n810_wimax()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SAPPHIRE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SAPPHIRE
+# endif
+# define machine_is_sapphire()	(machine_arch_type == MACH_TYPE_SAPPHIRE)
+#else
+# define machine_is_sapphire()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STMP37XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STMP37XX
+# endif
+# define machine_is_stmp37xx()	(machine_arch_type == MACH_TYPE_STMP37XX)
+#else
+# define machine_is_stmp37xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STMP378X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STMP378X
+# endif
+# define machine_is_stmp378x()	(machine_arch_type == MACH_TYPE_STMP378X)
+#else
+# define machine_is_stmp378x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EZX_A780
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EZX_A780
+# endif
+# define machine_is_ezx_a780()	(machine_arch_type == MACH_TYPE_EZX_A780)
+#else
+# define machine_is_ezx_a780()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EZX_E680
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EZX_E680
+# endif
+# define machine_is_ezx_e680()	(machine_arch_type == MACH_TYPE_EZX_E680)
+#else
+# define machine_is_ezx_e680()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EZX_A1200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EZX_A1200
+# endif
+# define machine_is_ezx_a1200()	(machine_arch_type == MACH_TYPE_EZX_A1200)
+#else
+# define machine_is_ezx_a1200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EZX_E6
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EZX_E6
+# endif
+# define machine_is_ezx_e6()	(machine_arch_type == MACH_TYPE_EZX_E6)
+#else
+# define machine_is_ezx_e6()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EZX_E2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EZX_E2
+# endif
+# define machine_is_ezx_e2()	(machine_arch_type == MACH_TYPE_EZX_E2)
+#else
+# define machine_is_ezx_e2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EZX_A910
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EZX_A910
+# endif
+# define machine_is_ezx_a910()	(machine_arch_type == MACH_TYPE_EZX_A910)
+#else
+# define machine_is_ezx_a910()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDMINI_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDMINI_V2
+# endif
+# define machine_is_edmini_v2()	(machine_arch_type == MACH_TYPE_EDMINI_V2)
+#else
+# define machine_is_edmini_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZIPIT2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZIPIT2
+# endif
+# define machine_is_zipit2()	(machine_arch_type == MACH_TYPE_ZIPIT2)
+#else
+# define machine_is_zipit2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_PANDORA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_PANDORA
+# endif
+# define machine_is_omap3_pandora()	(machine_arch_type == MACH_TYPE_OMAP3_PANDORA)
+#else
+# define machine_is_omap3_pandora()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSS2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSS2
+# endif
+# define machine_is_mss2()	(machine_arch_type == MACH_TYPE_MSS2)
+#else
+# define machine_is_mss2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LB88RC8480
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LB88RC8480
+# endif
+# define machine_is_lb88rc8480()	(machine_arch_type == MACH_TYPE_LB88RC8480)
+#else
+# define machine_is_lb88rc8480()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX25_3DS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX25_3DS
+# endif
+# define machine_is_mx25_3ds()	(machine_arch_type == MACH_TYPE_MX25_3DS)
+#else
+# define machine_is_mx25_3ds()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3530_LV_SOM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3530_LV_SOM
+# endif
+# define machine_is_omap3530_lv_som()	(machine_arch_type == MACH_TYPE_OMAP3530_LV_SOM)
+#else
+# define machine_is_omap3530_lv_som()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DA830_EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DA830_EVM
+# endif
+# define machine_is_davinci_da830_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM)
+#else
+# define machine_is_davinci_da830_evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT572D940HFEB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT572D940HFEB
+# endif
+# define machine_is_at572d940hfek()	(machine_arch_type == MACH_TYPE_AT572D940HFEB)
+#else
+# define machine_is_at572d940hfek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DOVE_DB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DOVE_DB
+# endif
+# define machine_is_dove_db()	(machine_arch_type == MACH_TYPE_DOVE_DB)
+#else
+# define machine_is_dove_db()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OVERO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OVERO
+# endif
+# define machine_is_overo()	(machine_arch_type == MACH_TYPE_OVERO)
+#else
+# define machine_is_overo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT2440EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT2440EVB
+# endif
+# define machine_is_at2440evb()	(machine_arch_type == MACH_TYPE_AT2440EVB)
+#else
+# define machine_is_at2440evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NEOCORE926
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEOCORE926
+# endif
+# define machine_is_neocore926()	(machine_arch_type == MACH_TYPE_NEOCORE926)
+#else
+# define machine_is_neocore926()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WNR854T
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WNR854T
+# endif
+# define machine_is_wnr854t()	(machine_arch_type == MACH_TYPE_WNR854T)
+#else
+# define machine_is_wnr854t()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RD88F5181L_GE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RD88F5181L_GE
+# endif
+# define machine_is_rd88f5181l_ge()	(machine_arch_type == MACH_TYPE_RD88F5181L_GE)
+#else
+# define machine_is_rd88f5181l_ge()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RD88F5181L_FXO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RD88F5181L_FXO
+# endif
+# define machine_is_rd88f5181l_fxo()	(machine_arch_type == MACH_TYPE_RD88F5181L_FXO)
+#else
+# define machine_is_rd88f5181l_fxo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STAMP9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STAMP9G20
+# endif
+# define machine_is_stamp9g20()	(machine_arch_type == MACH_TYPE_STAMP9G20)
+#else
+# define machine_is_stamp9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKC100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDKC100
+# endif
+# define machine_is_smdkc100()	(machine_arch_type == MACH_TYPE_SMDKC100)
+#else
+# define machine_is_smdkc100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TAVOREVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAVOREVB
+# endif
+# define machine_is_tavorevb()	(machine_arch_type == MACH_TYPE_TAVOREVB)
+#else
+# define machine_is_tavorevb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SAAR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SAAR
+# endif
+# define machine_is_saar()	(machine_arch_type == MACH_TYPE_SAAR)
+#else
+# define machine_is_saar()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9M10G45EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9M10G45EK
+# endif
+# define machine_is_at91sam9m10g45ek()	(machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK)
+#else
+# define machine_is_at91sam9m10g45ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MXLADS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MXLADS
+# endif
+# define machine_is_mxlads()	(machine_arch_type == MACH_TYPE_MXLADS)
+#else
+# define machine_is_mxlads()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LINKSTATION_MINI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LINKSTATION_MINI
+# endif
+# define machine_is_linkstation_mini()	(machine_arch_type == MACH_TYPE_LINKSTATION_MINI)
+#else
+# define machine_is_linkstation_mini()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AFEB9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AFEB9260
+# endif
+# define machine_is_afeb9260()	(machine_arch_type == MACH_TYPE_AFEB9260)
+#else
+# define machine_is_afeb9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IMX27IPCAM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IMX27IPCAM
+# endif
+# define machine_is_imx27ipcam()	(machine_arch_type == MACH_TYPE_IMX27IPCAM)
+#else
+# define machine_is_imx27ipcam()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RD88F6183AP_GE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RD88F6183AP_GE
+# endif
+# define machine_is_rd88f6183ap_ge()	(machine_arch_type == MACH_TYPE_RD88F6183AP_GE)
+#else
+# define machine_is_rd88f6183ap_ge()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REALVIEW_PBA8
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REALVIEW_PBA8
+# endif
+# define machine_is_realview_pba8()	(machine_arch_type == MACH_TYPE_REALVIEW_PBA8)
+#else
+# define machine_is_realview_pba8()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REALVIEW_PBX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REALVIEW_PBX
+# endif
+# define machine_is_realview_pbx()	(machine_arch_type == MACH_TYPE_REALVIEW_PBX)
+#else
+# define machine_is_realview_pbx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MICRO9S
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MICRO9S
+# endif
+# define machine_is_micro9s()	(machine_arch_type == MACH_TYPE_MICRO9S)
+#else
+# define machine_is_micro9s()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RUT100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RUT100
+# endif
+# define machine_is_rut100()	(machine_arch_type == MACH_TYPE_RUT100)
+#else
+# define machine_is_rut100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_G3EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_G3EVM
+# endif
+# define machine_is_g3evm()	(machine_arch_type == MACH_TYPE_G3EVM)
+#else
+# define machine_is_g3evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_W90P910EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_W90P910EVB
+# endif
+# define machine_is_w90p910evb()	(machine_arch_type == MACH_TYPE_W90P910EVB)
+#else
+# define machine_is_w90p910evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_W90P950EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_W90P950EVB
+# endif
+# define machine_is_w90p950evb()	(machine_arch_type == MACH_TYPE_W90P950EVB)
+#else
+# define machine_is_w90p950evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_W90N960EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_W90N960EVB
+# endif
+# define machine_is_w90n960evb()	(machine_arch_type == MACH_TYPE_W90N960EVB)
+#else
+# define machine_is_w90n960evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MV88F6281GTW_GE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MV88F6281GTW_GE
+# endif
+# define machine_is_mv88f6281gtw_ge()	(machine_arch_type == MACH_TYPE_MV88F6281GTW_GE)
+#else
+# define machine_is_mv88f6281gtw_ge()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NCP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NCP
+# endif
+# define machine_is_ncp()	(machine_arch_type == MACH_TYPE_NCP)
+#else
+# define machine_is_ncp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM365_EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM365_EVM
+# endif
+# define machine_is_davinci_dm365_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM)
+#else
+# define machine_is_davinci_dm365_evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CENTRO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CENTRO
+# endif
+# define machine_is_centro()	(machine_arch_type == MACH_TYPE_CENTRO)
+#else
+# define machine_is_centro()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOKIA_RX51
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOKIA_RX51
+# endif
+# define machine_is_nokia_rx51()	(machine_arch_type == MACH_TYPE_NOKIA_RX51)
+#else
+# define machine_is_nokia_rx51()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_ZOOM2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_ZOOM2
+# endif
+# define machine_is_omap_zoom2()	(machine_arch_type == MACH_TYPE_OMAP_ZOOM2)
+#else
+# define machine_is_omap_zoom2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPUAT9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPUAT9260
+# endif
+# define machine_is_cpuat9260()	(machine_arch_type == MACH_TYPE_CPUAT9260)
+#else
+# define machine_is_cpuat9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX27
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX27
+# endif
+# define machine_is_eukrea_cpuimx27()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX27)
+#else
+# define machine_is_eukrea_cpuimx27()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACS5K
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACS5K
+# endif
+# define machine_is_acs5k()	(machine_arch_type == MACH_TYPE_ACS5K)
+#else
+# define machine_is_acs5k()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SNAPPER_9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SNAPPER_9260
+# endif
+# define machine_is_snapper_9260()	(machine_arch_type == MACH_TYPE_SNAPPER_9260)
+#else
+# define machine_is_snapper_9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DSM320
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DSM320
+# endif
+# define machine_is_dsm320()	(machine_arch_type == MACH_TYPE_DSM320)
+#else
+# define machine_is_dsm320()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EXEDA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EXEDA
+# endif
+# define machine_is_exeda()	(machine_arch_type == MACH_TYPE_EXEDA)
+#else
+# define machine_is_exeda()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MINI2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MINI2440
+# endif
+# define machine_is_mini2440()	(machine_arch_type == MACH_TYPE_MINI2440)
+#else
+# define machine_is_mini2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COLIBRI300
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COLIBRI300
+# endif
+# define machine_is_colibri300()	(machine_arch_type == MACH_TYPE_COLIBRI300)
+#else
+# define machine_is_colibri300()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LINKSTATION_LS_HGL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LINKSTATION_LS_HGL
+# endif
+# define machine_is_linkstation_ls_hgl()	(machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL)
+#else
+# define machine_is_linkstation_ls_hgl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPUAT9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPUAT9G20
+# endif
+# define machine_is_cpuat9g20()	(machine_arch_type == MACH_TYPE_CPUAT9G20)
+#else
+# define machine_is_cpuat9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK6440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK6440
+# endif
+# define machine_is_smdk6440()	(machine_arch_type == MACH_TYPE_SMDK6440)
+#else
+# define machine_is_smdk6440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NAS4220B
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NAS4220B
+# endif
+# define machine_is_nas4220b()	(machine_arch_type == MACH_TYPE_NAS4220B)
+#else
+# define machine_is_nas4220b()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZYLONITE2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZYLONITE2
+# endif
+# define machine_is_zylonite2()	(machine_arch_type == MACH_TYPE_ZYLONITE2)
+#else
+# define machine_is_zylonite2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ASPENITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASPENITE
+# endif
+# define machine_is_aspenite()	(machine_arch_type == MACH_TYPE_ASPENITE)
+#else
+# define machine_is_aspenite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TTC_DKB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TTC_DKB
+# endif
+# define machine_is_ttc_dkb()	(machine_arch_type == MACH_TYPE_TTC_DKB)
+#else
+# define machine_is_ttc_dkb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM043
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM043
+# endif
+# define machine_is_pcm043()	(machine_arch_type == MACH_TYPE_PCM043)
+#else
+# define machine_is_pcm043()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHEEVAPLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHEEVAPLUG
+# endif
+# define machine_is_sheevaplug()	(machine_arch_type == MACH_TYPE_SHEEVAPLUG)
+#else
+# define machine_is_sheevaplug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AVENGERS_LITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AVENGERS_LITE
+# endif
+# define machine_is_avengers_lite()	(machine_arch_type == MACH_TYPE_AVENGERS_LITE)
+#else
+# define machine_is_avengers_lite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_BABBAGE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_BABBAGE
+# endif
+# define machine_is_mx51_babbage()	(machine_arch_type == MACH_TYPE_MX51_BABBAGE)
+#else
+# define machine_is_mx51_babbage()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RD78X00_MASA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RD78X00_MASA
+# endif
+# define machine_is_rd78x00_masa()	(machine_arch_type == MACH_TYPE_RD78X00_MASA)
+#else
+# define machine_is_rd78x00_masa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DM355_LEOPARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM355_LEOPARD
+# endif
+# define machine_is_dm355_leopard()	(machine_arch_type == MACH_TYPE_DM355_LEOPARD)
+#else
+# define machine_is_dm355_leopard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS219
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS219
+# endif
+# define machine_is_ts219()	(machine_arch_type == MACH_TYPE_TS219)
+#else
+# define machine_is_ts219()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCA100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCA100
+# endif
+# define machine_is_pca100()	(machine_arch_type == MACH_TYPE_PCA100)
+#else
+# define machine_is_pca100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DA850_EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DA850_EVM
+# endif
+# define machine_is_davinci_da850_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
+#else
+# define machine_is_davinci_da850_evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G10EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9G10EK
+# endif
+# define machine_is_at91sam9g10ek()	(machine_arch_type == MACH_TYPE_AT91SAM9G10EK)
+#else
+# define machine_is_at91sam9g10ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_4430SDP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_4430SDP
+# endif
+# define machine_is_omap_4430sdp()	(machine_arch_type == MACH_TYPE_OMAP_4430SDP)
+#else
+# define machine_is_omap_4430sdp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MAGX_ZN5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MAGX_ZN5
+# endif
+# define machine_is_magx_zn5()	(machine_arch_type == MACH_TYPE_MAGX_ZN5)
+#else
+# define machine_is_magx_zn5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BTMAVB101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BTMAVB101
+# endif
+# define machine_is_btmavb101()	(machine_arch_type == MACH_TYPE_BTMAVB101)
+#else
+# define machine_is_btmavb101()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BTMAWB101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BTMAWB101
+# endif
+# define machine_is_btmawb101()	(machine_arch_type == MACH_TYPE_BTMAWB101)
+#else
+# define machine_is_btmawb101()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_TORPEDO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_TORPEDO
+# endif
+# define machine_is_omap3_torpedo()	(machine_arch_type == MACH_TYPE_OMAP3_TORPEDO)
+#else
+# define machine_is_omap3_torpedo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ANW6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ANW6410
+# endif
+# define machine_is_anw6410()	(machine_arch_type == MACH_TYPE_ANW6410)
+#else
+# define machine_is_anw6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IMX27_VISSTRIM_M10
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IMX27_VISSTRIM_M10
+# endif
+# define machine_is_imx27_visstrim_m10()	(machine_arch_type == MACH_TYPE_IMX27_VISSTRIM_M10)
+#else
+# define machine_is_imx27_visstrim_m10()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PORTUXG20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PORTUXG20
+# endif
+# define machine_is_portuxg20()	(machine_arch_type == MACH_TYPE_PORTUXG20)
+#else
+# define machine_is_portuxg20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKC110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDKC110
+# endif
+# define machine_is_smdkc110()	(machine_arch_type == MACH_TYPE_SMDKC110)
+#else
+# define machine_is_smdkc110()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3517EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3517EVM
+# endif
+# define machine_is_omap3517evm()	(machine_arch_type == MACH_TYPE_OMAP3517EVM)
+#else
+# define machine_is_omap3517evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NETSPACE_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETSPACE_V2
+# endif
+# define machine_is_netspace_v2()	(machine_arch_type == MACH_TYPE_NETSPACE_V2)
+#else
+# define machine_is_netspace_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NETSPACE_MAX_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETSPACE_MAX_V2
+# endif
+# define machine_is_netspace_max_v2()	(machine_arch_type == MACH_TYPE_NETSPACE_MAX_V2)
+#else
+# define machine_is_netspace_max_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_D2NET_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_D2NET_V2
+# endif
+# define machine_is_d2net_v2()	(machine_arch_type == MACH_TYPE_D2NET_V2)
+#else
+# define machine_is_d2net_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NET2BIG_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NET2BIG_V2
+# endif
+# define machine_is_net2big_v2()	(machine_arch_type == MACH_TYPE_NET2BIG_V2)
+#else
+# define machine_is_net2big_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NET5BIG_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NET5BIG_V2
+# endif
+# define machine_is_net5big_v2()	(machine_arch_type == MACH_TYPE_NET5BIG_V2)
+#else
+# define machine_is_net5big_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_INETSPACE_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INETSPACE_V2
+# endif
+# define machine_is_inetspace_v2()	(machine_arch_type == MACH_TYPE_INETSPACE_V2)
+#else
+# define machine_is_inetspace_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G45EKES
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9G45EKES
+# endif
+# define machine_is_at91sam9g45ekes()	(machine_arch_type == MACH_TYPE_AT91SAM9G45EKES)
+#else
+# define machine_is_at91sam9g45ekes()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PC7302
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PC7302
+# endif
+# define machine_is_pc7302()	(machine_arch_type == MACH_TYPE_PC7302)
+#else
+# define machine_is_pc7302()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR600
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEAR600
+# endif
+# define machine_is_spear600()	(machine_arch_type == MACH_TYPE_SPEAR600)
+#else
+# define machine_is_spear600()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR300
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEAR300
+# endif
+# define machine_is_spear300()	(machine_arch_type == MACH_TYPE_SPEAR300)
+#else
+# define machine_is_spear300()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LILLY1131
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LILLY1131
+# endif
+# define machine_is_lilly1131()	(machine_arch_type == MACH_TYPE_LILLY1131)
+#else
+# define machine_is_lilly1131()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HMT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HMT
+# endif
+# define machine_is_hmt()	(machine_arch_type == MACH_TYPE_HMT)
+#else
+# define machine_is_hmt()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VEXPRESS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VEXPRESS
+# endif
+# define machine_is_vexpress()	(machine_arch_type == MACH_TYPE_VEXPRESS)
+#else
+# define machine_is_vexpress()	(0)
+#endif
+
+#ifdef CONFIG_MACH_D2NET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_D2NET
+# endif
+# define machine_is_d2net()	(machine_arch_type == MACH_TYPE_D2NET)
+#else
+# define machine_is_d2net()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BIGDISK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BIGDISK
+# endif
+# define machine_is_bigdisk()	(machine_arch_type == MACH_TYPE_BIGDISK)
+#else
+# define machine_is_bigdisk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9G20EK_2MMC
+# endif
+# define machine_is_at91sam9g20ek_2mmc()	(machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC)
+#else
+# define machine_is_at91sam9g20ek_2mmc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BCMRING
+# endif
+# define machine_is_bcmring()	(machine_arch_type == MACH_TYPE_BCMRING)
+#else
+# define machine_is_bcmring()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DP6XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DP6XX
+# endif
+# define machine_is_dp6xx()	(machine_arch_type == MACH_TYPE_DP6XX)
+#else
+# define machine_is_dp6xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MAHIMAHI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MAHIMAHI
+# endif
+# define machine_is_mahimahi()	(machine_arch_type == MACH_TYPE_MAHIMAHI)
+#else
+# define machine_is_mahimahi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK6442
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK6442
+# endif
+# define machine_is_smdk6442()	(machine_arch_type == MACH_TYPE_SMDK6442)
+#else
+# define machine_is_smdk6442()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OPENRD_BASE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPENRD_BASE
+# endif
+# define machine_is_openrd_base()	(machine_arch_type == MACH_TYPE_OPENRD_BASE)
+#else
+# define machine_is_openrd_base()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DEVKIT8000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DEVKIT8000
+# endif
+# define machine_is_devkit8000()	(machine_arch_type == MACH_TYPE_DEVKIT8000)
+#else
+# define machine_is_devkit8000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_EFIKAMX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_EFIKAMX
+# endif
+# define machine_is_mx51_efikamx()	(machine_arch_type == MACH_TYPE_MX51_EFIKAMX)
+#else
+# define machine_is_mx51_efikamx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CM_T35
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CM_T35
+# endif
+# define machine_is_cm_t35()	(machine_arch_type == MACH_TYPE_CM_T35)
+#else
+# define machine_is_cm_t35()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NET2BIG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NET2BIG
+# endif
+# define machine_is_net2big()	(machine_arch_type == MACH_TYPE_NET2BIG)
+#else
+# define machine_is_net2big()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IGEP0020
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IGEP0020
+# endif
+# define machine_is_igep0020()	(machine_arch_type == MACH_TYPE_IGEP0020)
+#else
+# define machine_is_igep0020()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC932EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC932EVB
+# endif
+# define machine_is_nuc932evb()	(machine_arch_type == MACH_TYPE_NUC932EVB)
+#else
+# define machine_is_nuc932evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OPENRD_CLIENT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPENRD_CLIENT
+# endif
+# define machine_is_openrd_client()	(machine_arch_type == MACH_TYPE_OPENRD_CLIENT)
+#else
+# define machine_is_openrd_client()	(0)
+#endif
+
+#ifdef CONFIG_MACH_U8500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_U8500
+# endif
+# define machine_is_u8500()	(machine_arch_type == MACH_TYPE_U8500)
+#else
+# define machine_is_u8500()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_EFIKASB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_EFIKASB
+# endif
+# define machine_is_mx51_efikasb()	(machine_arch_type == MACH_TYPE_MX51_EFIKASB)
+#else
+# define machine_is_mx51_efikasb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MARVELL_JASPER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MARVELL_JASPER
+# endif
+# define machine_is_marvell_jasper()	(machine_arch_type == MACH_TYPE_MARVELL_JASPER)
+#else
+# define machine_is_marvell_jasper()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FLINT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FLINT
+# endif
+# define machine_is_flint()	(machine_arch_type == MACH_TYPE_FLINT)
+#else
+# define machine_is_flint()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TAVOREVB3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAVOREVB3
+# endif
+# define machine_is_tavorevb3()	(machine_arch_type == MACH_TYPE_TAVOREVB3)
+#else
+# define machine_is_tavorevb3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOUCHBOOK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOUCHBOOK
+# endif
+# define machine_is_touchbook()	(machine_arch_type == MACH_TYPE_TOUCHBOOK)
+#else
+# define machine_is_touchbook()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RAUMFELD_RC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RAUMFELD_RC
+# endif
+# define machine_is_raumfeld_rc()	(machine_arch_type == MACH_TYPE_RAUMFELD_RC)
+#else
+# define machine_is_raumfeld_rc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RAUMFELD_CONNECTOR
+# endif
+# define machine_is_raumfeld_connector()	(machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR)
+#else
+# define machine_is_raumfeld_connector()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RAUMFELD_SPEAKER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RAUMFELD_SPEAKER
+# endif
+# define machine_is_raumfeld_speaker()	(machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER)
+#else
+# define machine_is_raumfeld_speaker()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TNETV107X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TNETV107X
+# endif
+# define machine_is_tnetv107x()	(machine_arch_type == MACH_TYPE_TNETV107X)
+#else
+# define machine_is_tnetv107x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKV210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDKV210
+# endif
+# define machine_is_smdkv210()	(machine_arch_type == MACH_TYPE_SMDKV210)
+#else
+# define machine_is_smdkv210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_ZOOM3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_ZOOM3
+# endif
+# define machine_is_omap_zoom3()	(machine_arch_type == MACH_TYPE_OMAP_ZOOM3)
+#else
+# define machine_is_omap_zoom3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_3630SDP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_3630SDP
+# endif
+# define machine_is_omap_3630sdp()	(machine_arch_type == MACH_TYPE_OMAP_3630SDP)
+#else
+# define machine_is_omap_3630sdp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQ7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMARTQ7
+# endif
+# define machine_is_smartq7()	(machine_arch_type == MACH_TYPE_SMARTQ7)
+#else
+# define machine_is_smartq7()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WATSON_EFM_PLUGIN
+# endif
+# define machine_is_watson_efm_plugin()	(machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN)
+#else
+# define machine_is_watson_efm_plugin()	(0)
+#endif
+
+#ifdef CONFIG_MACH_G4EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_G4EVM
+# endif
+# define machine_is_g4evm()	(machine_arch_type == MACH_TYPE_G4EVM)
+#else
+# define machine_is_g4evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAPL138_HAWKBOARD
+# endif
+# define machine_is_omapl138_hawkboard()	(machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD)
+#else
+# define machine_is_omapl138_hawkboard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS41X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS41X
+# endif
+# define machine_is_ts41x()	(machine_arch_type == MACH_TYPE_TS41X)
+#else
+# define machine_is_ts41x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PHY3250
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PHY3250
+# endif
+# define machine_is_phy3250()	(machine_arch_type == MACH_TYPE_PHY3250)
+#else
+# define machine_is_phy3250()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MINI6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MINI6410
+# endif
+# define machine_is_mini6410()	(machine_arch_type == MACH_TYPE_MINI6410)
+#else
+# define machine_is_mini6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX28EVK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX28EVK
+# endif
+# define machine_is_mx28evk()	(machine_arch_type == MACH_TYPE_MX28EVK)
+#else
+# define machine_is_mx28evk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQ5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMARTQ5
+# endif
+# define machine_is_smartq5()	(machine_arch_type == MACH_TYPE_SMARTQ5)
+#else
+# define machine_is_smartq5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM6467TEVM
+# endif
+# define machine_is_davinci_dm6467tevm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM)
+#else
+# define machine_is_davinci_dm6467tevm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MXT_TD60
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MXT_TD60
+# endif
+# define machine_is_mxt_td60()	(machine_arch_type == MACH_TYPE_MXT_TD60)
+#else
+# define machine_is_mxt_td60()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RIOT_BEI2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RIOT_BEI2
+# endif
+# define machine_is_riot_bei2()	(machine_arch_type == MACH_TYPE_RIOT_BEI2)
+#else
+# define machine_is_riot_bei2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RIOT_X37
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RIOT_X37
+# endif
+# define machine_is_riot_x37()	(machine_arch_type == MACH_TYPE_RIOT_X37)
+#else
+# define machine_is_riot_x37()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CAPC7117
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CAPC7117
+# endif
+# define machine_is_capc7117()	(machine_arch_type == MACH_TYPE_CAPC7117)
+#else
+# define machine_is_capc7117()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ICONTROL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ICONTROL
+# endif
+# define machine_is_icontrol()	(machine_arch_type == MACH_TYPE_ICONTROL)
+#else
+# define machine_is_icontrol()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50A_ST1_5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X50A_ST1_5
+# endif
+# define machine_is_qsd8x50a_st1_5()	(machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5)
+#else
+# define machine_is_qsd8x50a_st1_5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX23EVK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX23EVK
+# endif
+# define machine_is_mx23evk()	(machine_arch_type == MACH_TYPE_MX23EVK)
+#else
+# define machine_is_mx23evk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AP4EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AP4EVB
+# endif
+# define machine_is_ap4evb()	(machine_arch_type == MACH_TYPE_AP4EVB)
+#else
+# define machine_is_ap4evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MITYOMAPL138
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MITYOMAPL138
+# endif
+# define machine_is_mityomapl138()	(machine_arch_type == MACH_TYPE_MITYOMAPL138)
+#else
+# define machine_is_mityomapl138()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GURUPLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GURUPLUG
+# endif
+# define machine_is_guruplug()	(machine_arch_type == MACH_TYPE_GURUPLUG)
+#else
+# define machine_is_guruplug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR310
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEAR310
+# endif
+# define machine_is_spear310()	(machine_arch_type == MACH_TYPE_SPEAR310)
+#else
+# define machine_is_spear310()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR320
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEAR320
+# endif
+# define machine_is_spear320()	(machine_arch_type == MACH_TYPE_SPEAR320)
+#else
+# define machine_is_spear320()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AQUILA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AQUILA
+# endif
+# define machine_is_aquila()	(machine_arch_type == MACH_TYPE_AQUILA)
+#else
+# define machine_is_aquila()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESATA_SHEEVAPLUG
+# endif
+# define machine_is_sheeva_esata()	(machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG)
+#else
+# define machine_is_sheeva_esata()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X30_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X30_SURF
+# endif
+# define machine_is_msm7x30_surf()	(machine_arch_type == MACH_TYPE_MSM7X30_SURF)
+#else
+# define machine_is_msm7x30_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EA2478DEVKIT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EA2478DEVKIT
+# endif
+# define machine_is_ea2478devkit()	(machine_arch_type == MACH_TYPE_EA2478DEVKIT)
+#else
+# define machine_is_ea2478devkit()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TERASTATION_WXL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TERASTATION_WXL
+# endif
+# define machine_is_terastation_wxl()	(machine_arch_type == MACH_TYPE_TERASTATION_WXL)
+#else
+# define machine_is_terastation_wxl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X25_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X25_SURF
+# endif
+# define machine_is_msm7x25_surf()	(machine_arch_type == MACH_TYPE_MSM7X25_SURF)
+#else
+# define machine_is_msm7x25_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X25_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X25_FFA
+# endif
+# define machine_is_msm7x25_ffa()	(machine_arch_type == MACH_TYPE_MSM7X25_FFA)
+#else
+# define machine_is_msm7x25_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X27_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X27_SURF
+# endif
+# define machine_is_msm7x27_surf()	(machine_arch_type == MACH_TYPE_MSM7X27_SURF)
+#else
+# define machine_is_msm7x27_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X27_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X27_FFA
+# endif
+# define machine_is_msm7x27_ffa()	(machine_arch_type == MACH_TYPE_MSM7X27_FFA)
+#else
+# define machine_is_msm7x27_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X30_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X30_FFA
+# endif
+# define machine_is_msm7x30_ffa()	(machine_arch_type == MACH_TYPE_MSM7X30_FFA)
+#else
+# define machine_is_msm7x30_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X50_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X50_SURF
+# endif
+# define machine_is_qsd8x50_surf()	(machine_arch_type == MACH_TYPE_QSD8X50_SURF)
+#else
+# define machine_is_qsd8x50_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX53_EVK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX53_EVK
+# endif
+# define machine_is_mx53_evk()	(machine_arch_type == MACH_TYPE_MX53_EVK)
+#else
+# define machine_is_mx53_evk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IGEP0030
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IGEP0030
+# endif
+# define machine_is_igep0030()	(machine_arch_type == MACH_TYPE_IGEP0030)
+#else
+# define machine_is_igep0030()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SBC3530
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SBC3530
+# endif
+# define machine_is_sbc3530()	(machine_arch_type == MACH_TYPE_SBC3530)
+#else
+# define machine_is_sbc3530()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SAARB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SAARB
+# endif
+# define machine_is_saarb()	(machine_arch_type == MACH_TYPE_SAARB)
+#else
+# define machine_is_saarb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HARMONY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HARMONY
+# endif
+# define machine_is_harmony()	(machine_arch_type == MACH_TYPE_HARMONY)
+#else
+# define machine_is_harmony()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X30_FLUID
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X30_FLUID
+# endif
+# define machine_is_msm7x30_fluid()	(machine_arch_type == MACH_TYPE_MSM7X30_FLUID)
+#else
+# define machine_is_msm7x30_fluid()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CM_T3517
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CM_T3517
+# endif
+# define machine_is_cm_t3517()	(machine_arch_type == MACH_TYPE_CM_T3517)
+#else
+# define machine_is_cm_t3517()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WBD222
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WBD222
+# endif
+# define machine_is_wbd222()	(machine_arch_type == MACH_TYPE_WBD222)
+#else
+# define machine_is_wbd222()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8X60_SURF
+# endif
+# define machine_is_msm8x60_surf()	(machine_arch_type == MACH_TYPE_MSM8X60_SURF)
+#else
+# define machine_is_msm8x60_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_SIM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8X60_SIM
+# endif
+# define machine_is_msm8x60_sim()	(machine_arch_type == MACH_TYPE_MSM8X60_SIM)
+#else
+# define machine_is_msm8x60_sim()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TCC8000_SDK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TCC8000_SDK
+# endif
+# define machine_is_tcc8000_sdk()	(machine_arch_type == MACH_TYPE_TCC8000_SDK)
+#else
+# define machine_is_tcc8000_sdk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NANOS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NANOS
+# endif
+# define machine_is_nanos()	(machine_arch_type == MACH_TYPE_NANOS)
+#else
+# define machine_is_nanos()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STAMP9G45
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STAMP9G45
+# endif
+# define machine_is_stamp9g45()	(machine_arch_type == MACH_TYPE_STAMP9G45)
+#else
+# define machine_is_stamp9g45()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CNS3420VB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CNS3420VB
+# endif
+# define machine_is_cns3420vb()	(machine_arch_type == MACH_TYPE_CNS3420VB)
+#else
+# define machine_is_cns3420vb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP4_PANDA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP4_PANDA
+# endif
+# define machine_is_omap4_panda()	(machine_arch_type == MACH_TYPE_OMAP4_PANDA)
+#else
+# define machine_is_omap4_panda()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TI8168EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TI8168EVM
+# endif
+# define machine_is_ti8168evm()	(machine_arch_type == MACH_TYPE_TI8168EVM)
+#else
+# define machine_is_ti8168evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TETON_BGA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TETON_BGA
+# endif
+# define machine_is_teton_bga()	(machine_arch_type == MACH_TYPE_TETON_BGA)
+#else
+# define machine_is_teton_bga()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX25SD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX25SD
+# endif
+# define machine_is_eukrea_cpuimx25sd()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX25SD)
+#else
+# define machine_is_eukrea_cpuimx25sd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX35SD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX35SD
+# endif
+# define machine_is_eukrea_cpuimx35sd()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX35SD)
+#else
+# define machine_is_eukrea_cpuimx35sd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX51SD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX51SD
+# endif
+# define machine_is_eukrea_cpuimx51sd()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51SD)
+#else
+# define machine_is_eukrea_cpuimx51sd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX51
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX51
+# endif
+# define machine_is_eukrea_cpuimx51()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51)
+#else
+# define machine_is_eukrea_cpuimx51()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKC210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDKC210
+# endif
+# define machine_is_smdkc210()	(machine_arch_type == MACH_TYPE_SMDKC210)
+#else
+# define machine_is_smdkc210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_BRAILLO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_BRAILLO
+# endif
+# define machine_is_omap3_braillo()	(machine_arch_type == MACH_TYPE_OMAP3_BRAILLO)
+#else
+# define machine_is_omap3_braillo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPYPLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPYPLUG
+# endif
+# define machine_is_spyplug()	(machine_arch_type == MACH_TYPE_SPYPLUG)
+#else
+# define machine_is_spyplug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GINGER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GINGER
+# endif
+# define machine_is_ginger()	(machine_arch_type == MACH_TYPE_GINGER)
+#else
+# define machine_is_ginger()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TNY_T3530
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TNY_T3530
+# endif
+# define machine_is_tny_t3530()	(machine_arch_type == MACH_TYPE_TNY_T3530)
+#else
+# define machine_is_tny_t3530()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCA102
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCA102
+# endif
+# define machine_is_pca102()	(machine_arch_type == MACH_TYPE_PCA102)
+#else
+# define machine_is_pca102()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPADE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPADE
+# endif
+# define machine_is_spade()	(machine_arch_type == MACH_TYPE_SPADE)
+#else
+# define machine_is_spade()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MXC25_TOPAZ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MXC25_TOPAZ
+# endif
+# define machine_is_mxc25_topaz()	(machine_arch_type == MACH_TYPE_MXC25_TOPAZ)
+#else
+# define machine_is_mxc25_topaz()	(0)
+#endif
+
+#ifdef CONFIG_MACH_T5325
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_T5325
+# endif
+# define machine_is_t5325()	(machine_arch_type == MACH_TYPE_T5325)
+#else
+# define machine_is_t5325()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GW2361
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GW2361
+# endif
+# define machine_is_gw2361()	(machine_arch_type == MACH_TYPE_GW2361)
+#else
+# define machine_is_gw2361()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ELOG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ELOG
+# endif
+# define machine_is_elog()	(machine_arch_type == MACH_TYPE_ELOG)
+#else
+# define machine_is_elog()	(0)
+#endif
+
+#ifdef CONFIG_MACH_INCOME
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INCOME
+# endif
+# define machine_is_income()	(machine_arch_type == MACH_TYPE_INCOME)
+#else
+# define machine_is_income()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BCM589X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BCM589X
+# endif
+# define machine_is_bcm589x()	(machine_arch_type == MACH_TYPE_BCM589X)
+#else
+# define machine_is_bcm589x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ETNA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ETNA
+# endif
+# define machine_is_etna()	(machine_arch_type == MACH_TYPE_ETNA)
+#else
+# define machine_is_etna()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HAWKS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HAWKS
+# endif
+# define machine_is_hawks()	(machine_arch_type == MACH_TYPE_HAWKS)
+#else
+# define machine_is_hawks()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MESON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MESON
+# endif
+# define machine_is_meson()	(machine_arch_type == MACH_TYPE_MESON)
+#else
+# define machine_is_meson()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XSBASE255
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XSBASE255
+# endif
+# define machine_is_xsbase255()	(machine_arch_type == MACH_TYPE_XSBASE255)
+#else
+# define machine_is_xsbase255()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PVM2030
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PVM2030
+# endif
+# define machine_is_pvm2030()	(machine_arch_type == MACH_TYPE_PVM2030)
+#else
+# define machine_is_pvm2030()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MIOA502
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MIOA502
+# endif
+# define machine_is_mioa502()	(machine_arch_type == MACH_TYPE_MIOA502)
+#else
+# define machine_is_mioa502()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VVBOX_SDORIG2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VVBOX_SDORIG2
+# endif
+# define machine_is_vvbox_sdorig2()	(machine_arch_type == MACH_TYPE_VVBOX_SDORIG2)
+#else
+# define machine_is_vvbox_sdorig2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VVBOX_SDLITE2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VVBOX_SDLITE2
+# endif
+# define machine_is_vvbox_sdlite2()	(machine_arch_type == MACH_TYPE_VVBOX_SDLITE2)
+#else
+# define machine_is_vvbox_sdlite2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VVBOX_SDPRO4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VVBOX_SDPRO4
+# endif
+# define machine_is_vvbox_sdpro4()	(machine_arch_type == MACH_TYPE_VVBOX_SDPRO4)
+#else
+# define machine_is_vvbox_sdpro4()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTC_SPV_M700
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTC_SPV_M700
+# endif
+# define machine_is_htc_spv_m700()	(machine_arch_type == MACH_TYPE_HTC_SPV_M700)
+#else
+# define machine_is_htc_spv_m700()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX257SX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX257SX
+# endif
+# define machine_is_mx257sx()	(machine_arch_type == MACH_TYPE_MX257SX)
+#else
+# define machine_is_mx257sx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GONI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GONI
+# endif
+# define machine_is_goni()	(machine_arch_type == MACH_TYPE_GONI)
+#else
+# define machine_is_goni()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X55_SVLTE_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8X55_SVLTE_FFA
+# endif
+# define machine_is_msm8x55_svlte_ffa()	(machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_FFA)
+#else
+# define machine_is_msm8x55_svlte_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X55_SVLTE_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8X55_SVLTE_SURF
+# endif
+# define machine_is_msm8x55_svlte_surf()	(machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_SURF)
+#else
+# define machine_is_msm8x55_svlte_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QUICKSTEP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QUICKSTEP
+# endif
+# define machine_is_quickstep()	(machine_arch_type == MACH_TYPE_QUICKSTEP)
+#else
+# define machine_is_quickstep()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DMW96
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DMW96
+# endif
+# define machine_is_dmw96()	(machine_arch_type == MACH_TYPE_DMW96)
+#else
+# define machine_is_dmw96()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HAMMERHEAD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HAMMERHEAD
+# endif
+# define machine_is_hammerhead()	(machine_arch_type == MACH_TYPE_HAMMERHEAD)
+#else
+# define machine_is_hammerhead()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRIDENT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRIDENT
+# endif
+# define machine_is_trident()	(machine_arch_type == MACH_TYPE_TRIDENT)
+#else
+# define machine_is_trident()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LIGHTNING
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LIGHTNING
+# endif
+# define machine_is_lightning()	(machine_arch_type == MACH_TYPE_LIGHTNING)
+#else
+# define machine_is_lightning()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ICONNECT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ICONNECT
+# endif
+# define machine_is_iconnect()	(machine_arch_type == MACH_TYPE_ICONNECT)
+#else
+# define machine_is_iconnect()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AUTOBOT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AUTOBOT
+# endif
+# define machine_is_autobot()	(machine_arch_type == MACH_TYPE_AUTOBOT)
+#else
+# define machine_is_autobot()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COCONUT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COCONUT
+# endif
+# define machine_is_coconut()	(machine_arch_type == MACH_TYPE_COCONUT)
+#else
+# define machine_is_coconut()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DURIAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DURIAN
+# endif
+# define machine_is_durian()	(machine_arch_type == MACH_TYPE_DURIAN)
+#else
+# define machine_is_durian()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CAYENNE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CAYENNE
+# endif
+# define machine_is_cayenne()	(machine_arch_type == MACH_TYPE_CAYENNE)
+#else
+# define machine_is_cayenne()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FUJI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FUJI
+# endif
+# define machine_is_fuji()	(machine_arch_type == MACH_TYPE_FUJI)
+#else
+# define machine_is_fuji()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SYNOLOGY_6282
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SYNOLOGY_6282
+# endif
+# define machine_is_synology_6282()	(machine_arch_type == MACH_TYPE_SYNOLOGY_6282)
+#else
+# define machine_is_synology_6282()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EM1SY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EM1SY
+# endif
+# define machine_is_em1sy()	(machine_arch_type == MACH_TYPE_EM1SY)
+#else
+# define machine_is_em1sy()	(0)
+#endif
+
+#ifdef CONFIG_MACH_M502
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_M502
+# endif
+# define machine_is_m502()	(machine_arch_type == MACH_TYPE_M502)
+#else
+# define machine_is_m502()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MATRIX518
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MATRIX518
+# endif
+# define machine_is_matrix518()	(machine_arch_type == MACH_TYPE_MATRIX518)
+#else
+# define machine_is_matrix518()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TINY_GURNARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TINY_GURNARD
+# endif
+# define machine_is_tiny_gurnard()	(machine_arch_type == MACH_TYPE_TINY_GURNARD)
+#else
+# define machine_is_tiny_gurnard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR1310
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEAR1310
+# endif
+# define machine_is_spear1310()	(machine_arch_type == MACH_TYPE_SPEAR1310)
+#else
+# define machine_is_spear1310()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BV07
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BV07
+# endif
+# define machine_is_bv07()	(machine_arch_type == MACH_TYPE_BV07)
+#else
+# define machine_is_bv07()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MXT_TD61
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MXT_TD61
+# endif
+# define machine_is_mxt_td61()	(machine_arch_type == MACH_TYPE_MXT_TD61)
+#else
+# define machine_is_mxt_td61()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OPENRD_ULTIMATE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPENRD_ULTIMATE
+# endif
+# define machine_is_openrd_ultimate()	(machine_arch_type == MACH_TYPE_OPENRD_ULTIMATE)
+#else
+# define machine_is_openrd_ultimate()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DEVIXP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DEVIXP
+# endif
+# define machine_is_devixp()	(machine_arch_type == MACH_TYPE_DEVIXP)
+#else
+# define machine_is_devixp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MICCPT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MICCPT
+# endif
+# define machine_is_miccpt()	(machine_arch_type == MACH_TYPE_MICCPT)
+#else
+# define machine_is_miccpt()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MIC256
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MIC256
+# endif
+# define machine_is_mic256()	(machine_arch_type == MACH_TYPE_MIC256)
+#else
+# define machine_is_mic256()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AS1167
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AS1167
+# endif
+# define machine_is_as1167()	(machine_arch_type == MACH_TYPE_AS1167)
+#else
+# define machine_is_as1167()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_IBIZA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_IBIZA
+# endif
+# define machine_is_omap3_ibiza()	(machine_arch_type == MACH_TYPE_OMAP3_IBIZA)
+#else
+# define machine_is_omap3_ibiza()	(0)
+#endif
+
+#ifdef CONFIG_MACH_U5500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_U5500
+# endif
+# define machine_is_u5500()	(machine_arch_type == MACH_TYPE_U5500)
+#else
+# define machine_is_u5500()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_PICTO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_PICTO
+# endif
+# define machine_is_davinci_picto()	(machine_arch_type == MACH_TYPE_DAVINCI_PICTO)
+#else
+# define machine_is_davinci_picto()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MECHA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MECHA
+# endif
+# define machine_is_mecha()	(machine_arch_type == MACH_TYPE_MECHA)
+#else
+# define machine_is_mecha()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BUBBA3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BUBBA3
+# endif
+# define machine_is_bubba3()	(machine_arch_type == MACH_TYPE_BUBBA3)
+#else
+# define machine_is_bubba3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PUPITRE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PUPITRE
+# endif
+# define machine_is_pupitre()	(machine_arch_type == MACH_TYPE_PUPITRE)
+#else
+# define machine_is_pupitre()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TEGRA_VOGUE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TEGRA_VOGUE
+# endif
+# define machine_is_tegra_vogue()	(machine_arch_type == MACH_TYPE_TEGRA_VOGUE)
+#else
+# define machine_is_tegra_vogue()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TEGRA_E1165
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TEGRA_E1165
+# endif
+# define machine_is_tegra_e1165()	(machine_arch_type == MACH_TYPE_TEGRA_E1165)
+#else
+# define machine_is_tegra_e1165()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SIMPLENET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIMPLENET
+# endif
+# define machine_is_simplenet()	(machine_arch_type == MACH_TYPE_SIMPLENET)
+#else
+# define machine_is_simplenet()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EC4350TBM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EC4350TBM
+# endif
+# define machine_is_ec4350tbm()	(machine_arch_type == MACH_TYPE_EC4350TBM)
+#else
+# define machine_is_ec4350tbm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PEC_TC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PEC_TC
+# endif
+# define machine_is_pec_tc()	(machine_arch_type == MACH_TYPE_PEC_TC)
+#else
+# define machine_is_pec_tc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PEC_HC2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PEC_HC2
+# endif
+# define machine_is_pec_hc2()	(machine_arch_type == MACH_TYPE_PEC_HC2)
+#else
+# define machine_is_pec_hc2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_MOBILIS_A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_MOBILIS_A
+# endif
+# define machine_is_esl_mobilis_a()	(machine_arch_type == MACH_TYPE_ESL_MOBILIS_A)
+#else
+# define machine_is_esl_mobilis_a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_MOBILIS_B
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_MOBILIS_B
+# endif
+# define machine_is_esl_mobilis_b()	(machine_arch_type == MACH_TYPE_ESL_MOBILIS_B)
+#else
+# define machine_is_esl_mobilis_b()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_WAVE_A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_WAVE_A
+# endif
+# define machine_is_esl_wave_a()	(machine_arch_type == MACH_TYPE_ESL_WAVE_A)
+#else
+# define machine_is_esl_wave_a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_WAVE_B
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_WAVE_B
+# endif
+# define machine_is_esl_wave_b()	(machine_arch_type == MACH_TYPE_ESL_WAVE_B)
+#else
+# define machine_is_esl_wave_b()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UNISENSE_MMM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UNISENSE_MMM
+# endif
+# define machine_is_unisense_mmm()	(machine_arch_type == MACH_TYPE_UNISENSE_MMM)
+#else
+# define machine_is_unisense_mmm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BLUESHARK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLUESHARK
+# endif
+# define machine_is_blueshark()	(machine_arch_type == MACH_TYPE_BLUESHARK)
+#else
+# define machine_is_blueshark()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E10
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E10
+# endif
+# define machine_is_e10()	(machine_arch_type == MACH_TYPE_E10)
+#else
+# define machine_is_e10()	(0)
+#endif
+
+#ifdef CONFIG_MACH_APP3K_ROBIN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_APP3K_ROBIN
+# endif
+# define machine_is_app3k_robin()	(machine_arch_type == MACH_TYPE_APP3K_ROBIN)
+#else
+# define machine_is_app3k_robin()	(0)
+#endif
+
+#ifdef CONFIG_MACH_POV15HD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_POV15HD
+# endif
+# define machine_is_pov15hd()	(machine_arch_type == MACH_TYPE_POV15HD)
+#else
+# define machine_is_pov15hd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STELLA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STELLA
+# endif
+# define machine_is_stella()	(machine_arch_type == MACH_TYPE_STELLA)
+#else
+# define machine_is_stella()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LINKSTATION_LSCHL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LINKSTATION_LSCHL
+# endif
+# define machine_is_linkstation_lschl()	(machine_arch_type == MACH_TYPE_LINKSTATION_LSCHL)
+#else
+# define machine_is_linkstation_lschl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NETWALKER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETWALKER
+# endif
+# define machine_is_netwalker()	(machine_arch_type == MACH_TYPE_NETWALKER)
+#else
+# define machine_is_netwalker()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACSX106
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACSX106
+# endif
+# define machine_is_acsx106()	(machine_arch_type == MACH_TYPE_ACSX106)
+#else
+# define machine_is_acsx106()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ATLAS5_C1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ATLAS5_C1
+# endif
+# define machine_is_atlas5_c1()	(machine_arch_type == MACH_TYPE_ATLAS5_C1)
+#else
+# define machine_is_atlas5_c1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NSB3AST
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NSB3AST
+# endif
+# define machine_is_nsb3ast()	(machine_arch_type == MACH_TYPE_NSB3AST)
+#else
+# define machine_is_nsb3ast()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GNET_SLC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GNET_SLC
+# endif
+# define machine_is_gnet_slc()	(machine_arch_type == MACH_TYPE_GNET_SLC)
+#else
+# define machine_is_gnet_slc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AF4000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AF4000
+# endif
+# define machine_is_af4000()	(machine_arch_type == MACH_TYPE_AF4000)
+#else
+# define machine_is_af4000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARK9431
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARK9431
+# endif
+# define machine_is_ark9431()	(machine_arch_type == MACH_TYPE_ARK9431)
+#else
+# define machine_is_ark9431()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FS_S5PC100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FS_S5PC100
+# endif
+# define machine_is_fs_s5pc100()	(machine_arch_type == MACH_TYPE_FS_S5PC100)
+#else
+# define machine_is_fs_s5pc100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3505NOVA8
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3505NOVA8
+# endif
+# define machine_is_omap3505nova8()	(machine_arch_type == MACH_TYPE_OMAP3505NOVA8)
+#else
+# define machine_is_omap3505nova8()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3621_EDP1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3621_EDP1
+# endif
+# define machine_is_omap3621_edp1()	(machine_arch_type == MACH_TYPE_OMAP3621_EDP1)
+#else
+# define machine_is_omap3621_edp1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ORATISAES
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORATISAES
+# endif
+# define machine_is_oratisaes()	(machine_arch_type == MACH_TYPE_ORATISAES)
+#else
+# define machine_is_oratisaes()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKV310
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDKV310
+# endif
+# define machine_is_smdkv310()	(machine_arch_type == MACH_TYPE_SMDKV310)
+#else
+# define machine_is_smdkv310()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SIEMENS_L0
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIEMENS_L0
+# endif
+# define machine_is_siemens_l0()	(machine_arch_type == MACH_TYPE_SIEMENS_L0)
+#else
+# define machine_is_siemens_l0()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VENTANA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VENTANA
+# endif
+# define machine_is_ventana()	(machine_arch_type == MACH_TYPE_VENTANA)
+#else
+# define machine_is_ventana()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WM8505_7IN_NETBOOK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WM8505_7IN_NETBOOK
+# endif
+# define machine_is_wm8505_7in_netbook()	(machine_arch_type == MACH_TYPE_WM8505_7IN_NETBOOK)
+#else
+# define machine_is_wm8505_7in_netbook()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EC4350SDB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EC4350SDB
+# endif
+# define machine_is_ec4350sdb()	(machine_arch_type == MACH_TYPE_EC4350SDB)
+#else
+# define machine_is_ec4350sdb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MIMAS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MIMAS
+# endif
+# define machine_is_mimas()	(machine_arch_type == MACH_TYPE_MIMAS)
+#else
+# define machine_is_mimas()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TITAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TITAN
+# endif
+# define machine_is_titan()	(machine_arch_type == MACH_TYPE_TITAN)
+#else
+# define machine_is_titan()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CRANEBOARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CRANEBOARD
+# endif
+# define machine_is_craneboard()	(machine_arch_type == MACH_TYPE_CRANEBOARD)
+#else
+# define machine_is_craneboard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ES2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ES2440
+# endif
+# define machine_is_es2440()	(machine_arch_type == MACH_TYPE_ES2440)
+#else
+# define machine_is_es2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NAJAY_A9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NAJAY_A9263
+# endif
+# define machine_is_najay_a9263()	(machine_arch_type == MACH_TYPE_NAJAY_A9263)
+#else
+# define machine_is_najay_a9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCTORNADO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCTORNADO
+# endif
+# define machine_is_htctornado()	(machine_arch_type == MACH_TYPE_HTCTORNADO)
+#else
+# define machine_is_htctornado()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DIMM_MX257
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DIMM_MX257
+# endif
+# define machine_is_dimm_mx257()	(machine_arch_type == MACH_TYPE_DIMM_MX257)
+#else
+# define machine_is_dimm_mx257()	(0)
+#endif
+
+#ifdef CONFIG_MACH_JIGEN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JIGEN
+# endif
+# define machine_is_jigen301()	(machine_arch_type == MACH_TYPE_JIGEN)
+#else
+# define machine_is_jigen301()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK6450
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK6450
+# endif
+# define machine_is_smdk6450()	(machine_arch_type == MACH_TYPE_SMDK6450)
+#else
+# define machine_is_smdk6450()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MENO_QNG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MENO_QNG
+# endif
+# define machine_is_meno_qng()	(machine_arch_type == MACH_TYPE_MENO_QNG)
+#else
+# define machine_is_meno_qng()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NS2416
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NS2416
+# endif
+# define machine_is_ns2416()	(machine_arch_type == MACH_TYPE_NS2416)
+#else
+# define machine_is_ns2416()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RPC353
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RPC353
+# endif
+# define machine_is_rpc353()	(machine_arch_type == MACH_TYPE_RPC353)
+#else
+# define machine_is_rpc353()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TQ6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TQ6410
+# endif
+# define machine_is_tq6410()	(machine_arch_type == MACH_TYPE_TQ6410)
+#else
+# define machine_is_tq6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SKY6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SKY6410
+# endif
+# define machine_is_sky6410()	(machine_arch_type == MACH_TYPE_SKY6410)
+#else
+# define machine_is_sky6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DYNASTY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DYNASTY
+# endif
+# define machine_is_dynasty()	(machine_arch_type == MACH_TYPE_DYNASTY)
+#else
+# define machine_is_dynasty()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VIVO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VIVO
+# endif
+# define machine_is_vivo()	(machine_arch_type == MACH_TYPE_VIVO)
+#else
+# define machine_is_vivo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BURY_BL7582
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BURY_BL7582
+# endif
+# define machine_is_bury_bl7582()	(machine_arch_type == MACH_TYPE_BURY_BL7582)
+#else
+# define machine_is_bury_bl7582()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BURY_BPS5270
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BURY_BPS5270
+# endif
+# define machine_is_bury_bps5270()	(machine_arch_type == MACH_TYPE_BURY_BPS5270)
+#else
+# define machine_is_bury_bps5270()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BASI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BASI
+# endif
+# define machine_is_basi()	(machine_arch_type == MACH_TYPE_BASI)
+#else
+# define machine_is_basi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TN200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TN200
+# endif
+# define machine_is_tn200()	(machine_arch_type == MACH_TYPE_TN200)
+#else
+# define machine_is_tn200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_C2MMI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_C2MMI
+# endif
+# define machine_is_c2mmi()	(machine_arch_type == MACH_TYPE_C2MMI)
+#else
+# define machine_is_c2mmi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MESON_6236M
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MESON_6236M
+# endif
+# define machine_is_meson_6236m()	(machine_arch_type == MACH_TYPE_MESON_6236M)
+#else
+# define machine_is_meson_6236m()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MESON_8626M
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MESON_8626M
+# endif
+# define machine_is_meson_8626m()	(machine_arch_type == MACH_TYPE_MESON_8626M)
+#else
+# define machine_is_meson_8626m()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TUBE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TUBE
+# endif
+# define machine_is_tube()	(machine_arch_type == MACH_TYPE_TUBE)
+#else
+# define machine_is_tube()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MESSINA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MESSINA
+# endif
+# define machine_is_messina()	(machine_arch_type == MACH_TYPE_MESSINA)
+#else
+# define machine_is_messina()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX50_ARM2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX50_ARM2
+# endif
+# define machine_is_mx50_arm2()	(machine_arch_type == MACH_TYPE_MX50_ARM2)
+#else
+# define machine_is_mx50_arm2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CETUS9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CETUS9263
+# endif
+# define machine_is_cetus9263()	(machine_arch_type == MACH_TYPE_CETUS9263)
+#else
+# define machine_is_cetus9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BROWNSTONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BROWNSTONE
+# endif
+# define machine_is_brownstone()	(machine_arch_type == MACH_TYPE_BROWNSTONE)
+#else
+# define machine_is_brownstone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VMX25
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VMX25
+# endif
+# define machine_is_vmx25()	(machine_arch_type == MACH_TYPE_VMX25)
+#else
+# define machine_is_vmx25()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VMX51
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VMX51
+# endif
+# define machine_is_vmx51()	(machine_arch_type == MACH_TYPE_VMX51)
+#else
+# define machine_is_vmx51()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ABACUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ABACUS
+# endif
+# define machine_is_abacus()	(machine_arch_type == MACH_TYPE_ABACUS)
+#else
+# define machine_is_abacus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CM4745
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CM4745
+# endif
+# define machine_is_cm4745()	(machine_arch_type == MACH_TYPE_CM4745)
+#else
+# define machine_is_cm4745()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ORATISLINK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORATISLINK
+# endif
+# define machine_is_oratislink()	(machine_arch_type == MACH_TYPE_ORATISLINK)
+#else
+# define machine_is_oratislink()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM365_DVR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM365_DVR
+# endif
+# define machine_is_davinci_dm365_dvr()	(machine_arch_type == MACH_TYPE_DAVINCI_DM365_DVR)
+#else
+# define machine_is_davinci_dm365_dvr()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NETVIZ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETVIZ
+# endif
+# define machine_is_netviz()	(machine_arch_type == MACH_TYPE_NETVIZ)
+#else
+# define machine_is_netviz()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FLEXIBITY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FLEXIBITY
+# endif
+# define machine_is_flexibity()	(machine_arch_type == MACH_TYPE_FLEXIBITY)
+#else
+# define machine_is_flexibity()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WLAN_COMPUTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WLAN_COMPUTER
+# endif
+# define machine_is_wlan_computer()	(machine_arch_type == MACH_TYPE_WLAN_COMPUTER)
+#else
+# define machine_is_wlan_computer()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPC24XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPC24XX
+# endif
+# define machine_is_lpc24xx()	(machine_arch_type == MACH_TYPE_LPC24XX)
+#else
+# define machine_is_lpc24xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPICA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPICA
+# endif
+# define machine_is_spica()	(machine_arch_type == MACH_TYPE_SPICA)
+#else
+# define machine_is_spica()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GPSDISPLAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GPSDISPLAY
+# endif
+# define machine_is_gpsdisplay()	(machine_arch_type == MACH_TYPE_GPSDISPLAY)
+#else
+# define machine_is_gpsdisplay()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BIPNET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BIPNET
+# endif
+# define machine_is_bipnet()	(machine_arch_type == MACH_TYPE_BIPNET)
+#else
+# define machine_is_bipnet()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OVERO_CTU_INERTIAL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OVERO_CTU_INERTIAL
+# endif
+# define machine_is_overo_ctu_inertial()	(machine_arch_type == MACH_TYPE_OVERO_CTU_INERTIAL)
+#else
+# define machine_is_overo_ctu_inertial()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM355_MMM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM355_MMM
+# endif
+# define machine_is_davinci_dm355_mmm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM355_MMM)
+#else
+# define machine_is_davinci_dm355_mmm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PC9260_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PC9260_V2
+# endif
+# define machine_is_pc9260_v2()	(machine_arch_type == MACH_TYPE_PC9260_V2)
+#else
+# define machine_is_pc9260_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PTX7545
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PTX7545
+# endif
+# define machine_is_ptx7545()	(machine_arch_type == MACH_TYPE_PTX7545)
+#else
+# define machine_is_ptx7545()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TM_EFDC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TM_EFDC
+# endif
+# define machine_is_tm_efdc()	(machine_arch_type == MACH_TYPE_TM_EFDC)
+#else
+# define machine_is_tm_efdc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_WALDO1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_WALDO1
+# endif
+# define machine_is_omap3_waldo1()	(machine_arch_type == MACH_TYPE_OMAP3_WALDO1)
+#else
+# define machine_is_omap3_waldo1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FLYER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FLYER
+# endif
+# define machine_is_flyer()	(machine_arch_type == MACH_TYPE_FLYER)
+#else
+# define machine_is_flyer()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TORNADO3240
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TORNADO3240
+# endif
+# define machine_is_tornado3240()	(machine_arch_type == MACH_TYPE_TORNADO3240)
+#else
+# define machine_is_tornado3240()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SOLI_01
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SOLI_01
+# endif
+# define machine_is_soli_01()	(machine_arch_type == MACH_TYPE_SOLI_01)
+#else
+# define machine_is_soli_01()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAPL138_EUROPALC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAPL138_EUROPALC
+# endif
+# define machine_is_omapl138_europalc()	(machine_arch_type == MACH_TYPE_OMAPL138_EUROPALC)
+#else
+# define machine_is_omapl138_europalc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HELIOS_V1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HELIOS_V1
+# endif
+# define machine_is_helios_v1()	(machine_arch_type == MACH_TYPE_HELIOS_V1)
+#else
+# define machine_is_helios_v1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NETSPACE_LITE_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETSPACE_LITE_V2
+# endif
+# define machine_is_netspace_lite_v2()	(machine_arch_type == MACH_TYPE_NETSPACE_LITE_V2)
+#else
+# define machine_is_netspace_lite_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SSC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SSC
+# endif
+# define machine_is_ssc()	(machine_arch_type == MACH_TYPE_SSC)
+#else
+# define machine_is_ssc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PREMIERWAVE_EN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PREMIERWAVE_EN
+# endif
+# define machine_is_premierwave_en()	(machine_arch_type == MACH_TYPE_PREMIERWAVE_EN)
+#else
+# define machine_is_premierwave_en()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WASABI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WASABI
+# endif
+# define machine_is_wasabi()	(machine_arch_type == MACH_TYPE_WASABI)
+#else
+# define machine_is_wasabi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX50_RDP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX50_RDP
+# endif
+# define machine_is_mx50_rdp()	(machine_arch_type == MACH_TYPE_MX50_RDP)
+#else
+# define machine_is_mx50_rdp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UNIVERSAL_C210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UNIVERSAL_C210
+# endif
+# define machine_is_universal_c210()	(machine_arch_type == MACH_TYPE_UNIVERSAL_C210)
+#else
+# define machine_is_universal_c210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REAL6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REAL6410
+# endif
+# define machine_is_real6410()	(machine_arch_type == MACH_TYPE_REAL6410)
+#else
+# define machine_is_real6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPX_SAKURA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPX_SAKURA
+# endif
+# define machine_is_spx_sakura()	(machine_arch_type == MACH_TYPE_SPX_SAKURA)
+#else
+# define machine_is_spx_sakura()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IJ3K_2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IJ3K_2440
+# endif
+# define machine_is_ij3k_2440()	(machine_arch_type == MACH_TYPE_IJ3K_2440)
+#else
+# define machine_is_ij3k_2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_BC10
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_BC10
+# endif
+# define machine_is_omap3_bc10()	(machine_arch_type == MACH_TYPE_OMAP3_BC10)
+#else
+# define machine_is_omap3_bc10()	(0)
+#endif
+
+#ifdef CONFIG_MACH_THEBE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_THEBE
+# endif
+# define machine_is_thebe()	(machine_arch_type == MACH_TYPE_THEBE)
+#else
+# define machine_is_thebe()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RV082
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RV082
+# endif
+# define machine_is_rv082()	(machine_arch_type == MACH_TYPE_RV082)
+#else
+# define machine_is_rv082()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMLGUEST
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMLGUEST
+# endif
+# define machine_is_armlguest()	(machine_arch_type == MACH_TYPE_ARMLGUEST)
+#else
+# define machine_is_armlguest()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TJINC1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TJINC1000
+# endif
+# define machine_is_tjinc1000()	(machine_arch_type == MACH_TYPE_TJINC1000)
+#else
+# define machine_is_tjinc1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DOCKSTAR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DOCKSTAR
+# endif
+# define machine_is_dockstar()	(machine_arch_type == MACH_TYPE_DOCKSTAR)
+#else
+# define machine_is_dockstar()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AX8008
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AX8008
+# endif
+# define machine_is_ax8008()	(machine_arch_type == MACH_TYPE_AX8008)
+#else
+# define machine_is_ax8008()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GNET_SGCE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GNET_SGCE
+# endif
+# define machine_is_gnet_sgce()	(machine_arch_type == MACH_TYPE_GNET_SGCE)
+#else
+# define machine_is_gnet_sgce()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PXWNAS_500_1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXWNAS_500_1000
+# endif
+# define machine_is_pxwnas_500_1000()	(machine_arch_type == MACH_TYPE_PXWNAS_500_1000)
+#else
+# define machine_is_pxwnas_500_1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EA20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EA20
+# endif
+# define machine_is_ea20()	(machine_arch_type == MACH_TYPE_EA20)
+#else
+# define machine_is_ea20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AWM2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AWM2
+# endif
+# define machine_is_awm2()	(machine_arch_type == MACH_TYPE_AWM2)
+#else
+# define machine_is_awm2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TI8148EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TI8148EVM
+# endif
+# define machine_is_ti8148evm()	(machine_arch_type == MACH_TYPE_TI8148EVM)
+#else
+# define machine_is_ti8148evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SEABOARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SEABOARD
+# endif
+# define machine_is_seaboard()	(machine_arch_type == MACH_TYPE_SEABOARD)
+#else
+# define machine_is_seaboard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LINKSTATION_CHLV2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LINKSTATION_CHLV2
+# endif
+# define machine_is_linkstation_chlv2()	(machine_arch_type == MACH_TYPE_LINKSTATION_CHLV2)
+#else
+# define machine_is_linkstation_chlv2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TERA_PRO2_RACK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TERA_PRO2_RACK
+# endif
+# define machine_is_tera_pro2_rack()	(machine_arch_type == MACH_TYPE_TERA_PRO2_RACK)
+#else
+# define machine_is_tera_pro2_rack()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RUBYS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RUBYS
+# endif
+# define machine_is_rubys()	(machine_arch_type == MACH_TYPE_RUBYS)
+#else
+# define machine_is_rubys()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AQUARIUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AQUARIUS
+# endif
+# define machine_is_aquarius()	(machine_arch_type == MACH_TYPE_AQUARIUS)
+#else
+# define machine_is_aquarius()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX53_ARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX53_ARD
+# endif
+# define machine_is_mx53_ard()	(machine_arch_type == MACH_TYPE_MX53_ARD)
+#else
+# define machine_is_mx53_ard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX53_SMD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX53_SMD
+# endif
+# define machine_is_mx53_smd()	(machine_arch_type == MACH_TYPE_MX53_SMD)
+#else
+# define machine_is_mx53_smd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LSWXL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LSWXL
+# endif
+# define machine_is_lswxl()	(machine_arch_type == MACH_TYPE_LSWXL)
+#else
+# define machine_is_lswxl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DOVE_AVNG_V3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DOVE_AVNG_V3
+# endif
+# define machine_is_dove_avng_v3()	(machine_arch_type == MACH_TYPE_DOVE_AVNG_V3)
+#else
+# define machine_is_dove_avng_v3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SDI_ESS_9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SDI_ESS_9263
+# endif
+# define machine_is_sdi_ess_9263()	(machine_arch_type == MACH_TYPE_SDI_ESS_9263)
+#else
+# define machine_is_sdi_ess_9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_JOCPU550
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JOCPU550
+# endif
+# define machine_is_jocpu550()	(machine_arch_type == MACH_TYPE_JOCPU550)
+#else
+# define machine_is_jocpu550()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_RUMI3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8X60_RUMI3
+# endif
+# define machine_is_msm8x60_rumi3()	(machine_arch_type == MACH_TYPE_MSM8X60_RUMI3)
+#else
+# define machine_is_msm8x60_rumi3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8X60_FFA
+# endif
+# define machine_is_msm8x60_ffa()	(machine_arch_type == MACH_TYPE_MSM8X60_FFA)
+#else
+# define machine_is_msm8x60_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_YANOMAMI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_YANOMAMI
+# endif
+# define machine_is_yanomami()	(machine_arch_type == MACH_TYPE_YANOMAMI)
+#else
+# define machine_is_yanomami()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GTA04
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GTA04
+# endif
+# define machine_is_gta04()	(machine_arch_type == MACH_TYPE_GTA04)
+#else
+# define machine_is_gta04()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CM_A510
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CM_A510
+# endif
+# define machine_is_cm_a510()	(machine_arch_type == MACH_TYPE_CM_A510)
+#else
+# define machine_is_cm_a510()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_RFS200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_RFS200
+# endif
+# define machine_is_omap3_rfs200()	(machine_arch_type == MACH_TYPE_OMAP3_RFS200)
+#else
+# define machine_is_omap3_rfs200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KX33XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KX33XX
+# endif
+# define machine_is_kx33xx()	(machine_arch_type == MACH_TYPE_KX33XX)
+#else
+# define machine_is_kx33xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PTX7510
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PTX7510
+# endif
+# define machine_is_ptx7510()	(machine_arch_type == MACH_TYPE_PTX7510)
+#else
+# define machine_is_ptx7510()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOP9000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOP9000
+# endif
+# define machine_is_top9000()	(machine_arch_type == MACH_TYPE_TOP9000)
+#else
+# define machine_is_top9000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TEENOTE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TEENOTE
+# endif
+# define machine_is_teenote()	(machine_arch_type == MACH_TYPE_TEENOTE)
+#else
+# define machine_is_teenote()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS3
+# endif
+# define machine_is_ts3()	(machine_arch_type == MACH_TYPE_TS3)
+#else
+# define machine_is_ts3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A0
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A0
+# endif
+# define machine_is_a0()	(machine_arch_type == MACH_TYPE_A0)
+#else
+# define machine_is_a0()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FSM9XXX_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FSM9XXX_SURF
+# endif
+# define machine_is_fsm9xxx_surf()	(machine_arch_type == MACH_TYPE_FSM9XXX_SURF)
+#else
+# define machine_is_fsm9xxx_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FSM9XXX_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FSM9XXX_FFA
+# endif
+# define machine_is_fsm9xxx_ffa()	(machine_arch_type == MACH_TYPE_FSM9XXX_FFA)
+#else
+# define machine_is_fsm9xxx_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FRRHWCDMA60W
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FRRHWCDMA60W
+# endif
+# define machine_is_frrhwcdma60w()	(machine_arch_type == MACH_TYPE_FRRHWCDMA60W)
+#else
+# define machine_is_frrhwcdma60w()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REMUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REMUS
+# endif
+# define machine_is_remus()	(machine_arch_type == MACH_TYPE_REMUS)
+#else
+# define machine_is_remus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91CAP7XDK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91CAP7XDK
+# endif
+# define machine_is_at91cap7xdk()	(machine_arch_type == MACH_TYPE_AT91CAP7XDK)
+#else
+# define machine_is_at91cap7xdk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91CAP7STK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91CAP7STK
+# endif
+# define machine_is_at91cap7stk()	(machine_arch_type == MACH_TYPE_AT91CAP7STK)
+#else
+# define machine_is_at91cap7stk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KT_SBC_SAM9_1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KT_SBC_SAM9_1
+# endif
+# define machine_is_kt_sbc_sam9_1()	(machine_arch_type == MACH_TYPE_KT_SBC_SAM9_1)
+#else
+# define machine_is_kt_sbc_sam9_1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADA_XP_DB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMADA_XP_DB
+# endif
+# define machine_is_armada_xp_db()	(machine_arch_type == MACH_TYPE_ARMADA_XP_DB)
+#else
+# define machine_is_armada_xp_db()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPDM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPDM
+# endif
+# define machine_is_spdm()	(machine_arch_type == MACH_TYPE_SPDM)
+#else
+# define machine_is_spdm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GTIB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GTIB
+# endif
+# define machine_is_gtib()	(machine_arch_type == MACH_TYPE_GTIB)
+#else
+# define machine_is_gtib()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DGM3240
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DGM3240
+# endif
+# define machine_is_dgm3240()	(machine_arch_type == MACH_TYPE_DGM3240)
+#else
+# define machine_is_dgm3240()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCMEGA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCMEGA
+# endif
+# define machine_is_htcmega()	(machine_arch_type == MACH_TYPE_HTCMEGA)
+#else
+# define machine_is_htcmega()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRICORDER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRICORDER
+# endif
+# define machine_is_tricorder()	(machine_arch_type == MACH_TYPE_TRICORDER)
+#else
+# define machine_is_tricorder()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TX28
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TX28
+# endif
+# define machine_is_tx28()	(machine_arch_type == MACH_TYPE_TX28)
+#else
+# define machine_is_tx28()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BSTBRD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BSTBRD
+# endif
+# define machine_is_bstbrd()	(machine_arch_type == MACH_TYPE_BSTBRD)
+#else
+# define machine_is_bstbrd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PWB3090
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PWB3090
+# endif
+# define machine_is_pwb3090()	(machine_arch_type == MACH_TYPE_PWB3090)
+#else
+# define machine_is_pwb3090()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IDEA6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IDEA6410
+# endif
+# define machine_is_idea6410()	(machine_arch_type == MACH_TYPE_IDEA6410)
+#else
+# define machine_is_idea6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QBC9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QBC9263
+# endif
+# define machine_is_qbc9263()	(machine_arch_type == MACH_TYPE_QBC9263)
+#else
+# define machine_is_qbc9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BORABORA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BORABORA
+# endif
+# define machine_is_borabora()	(machine_arch_type == MACH_TYPE_BORABORA)
+#else
+# define machine_is_borabora()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VALDEZ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VALDEZ
+# endif
+# define machine_is_valdez()	(machine_arch_type == MACH_TYPE_VALDEZ)
+#else
+# define machine_is_valdez()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LS9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LS9G20
+# endif
+# define machine_is_ls9g20()	(machine_arch_type == MACH_TYPE_LS9G20)
+#else
+# define machine_is_ls9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MIOS_V1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MIOS_V1
+# endif
+# define machine_is_mios_v1()	(machine_arch_type == MACH_TYPE_MIOS_V1)
+#else
+# define machine_is_mios_v1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S5PC110_CRESPO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S5PC110_CRESPO
+# endif
+# define machine_is_s5pc110_crespo()	(machine_arch_type == MACH_TYPE_S5PC110_CRESPO)
+#else
+# define machine_is_s5pc110_crespo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CONTROLTEK9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CONTROLTEK9G20
+# endif
+# define machine_is_controltek9g20()	(machine_arch_type == MACH_TYPE_CONTROLTEK9G20)
+#else
+# define machine_is_controltek9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TIN307
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TIN307
+# endif
+# define machine_is_tin307()	(machine_arch_type == MACH_TYPE_TIN307)
+#else
+# define machine_is_tin307()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TIN510
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TIN510
+# endif
+# define machine_is_tin510()	(machine_arch_type == MACH_TYPE_TIN510)
+#else
+# define machine_is_tin510()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BLUECHEESE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLUECHEESE
+# endif
+# define machine_is_bluecheese()	(machine_arch_type == MACH_TYPE_BLUECHEESE)
+#else
+# define machine_is_bluecheese()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TEM3X30
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TEM3X30
+# endif
+# define machine_is_tem3x30()	(machine_arch_type == MACH_TYPE_TEM3X30)
+#else
+# define machine_is_tem3x30()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HARVEST_DESOTO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HARVEST_DESOTO
+# endif
+# define machine_is_harvest_desoto()	(machine_arch_type == MACH_TYPE_HARVEST_DESOTO)
+#else
+# define machine_is_harvest_desoto()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_QRDC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8X60_QRDC
+# endif
+# define machine_is_msm8x60_qrdc()	(machine_arch_type == MACH_TYPE_MSM8X60_QRDC)
+#else
+# define machine_is_msm8x60_qrdc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR900
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEAR900
+# endif
+# define machine_is_spear900()	(machine_arch_type == MACH_TYPE_SPEAR900)
+#else
+# define machine_is_spear900()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCONTROL_G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCONTROL_G20
+# endif
+# define machine_is_pcontrol_g20()	(machine_arch_type == MACH_TYPE_PCONTROL_G20)
+#else
+# define machine_is_pcontrol_g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RDSTOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RDSTOR
+# endif
+# define machine_is_rdstor()	(machine_arch_type == MACH_TYPE_RDSTOR)
+#else
+# define machine_is_rdstor()	(0)
+#endif
+
+#ifdef CONFIG_MACH_USDLOADER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_USDLOADER
+# endif
+# define machine_is_usdloader()	(machine_arch_type == MACH_TYPE_USDLOADER)
+#else
+# define machine_is_usdloader()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TSOPLOADER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TSOPLOADER
+# endif
+# define machine_is_tsoploader()	(machine_arch_type == MACH_TYPE_TSOPLOADER)
+#else
+# define machine_is_tsoploader()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KRONOS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KRONOS
+# endif
+# define machine_is_kronos()	(machine_arch_type == MACH_TYPE_KRONOS)
+#else
+# define machine_is_kronos()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FFCORE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FFCORE
+# endif
+# define machine_is_ffcore()	(machine_arch_type == MACH_TYPE_FFCORE)
+#else
+# define machine_is_ffcore()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MONE
+# endif
+# define machine_is_mone()	(machine_arch_type == MACH_TYPE_MONE)
+#else
+# define machine_is_mone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UNIT2S
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UNIT2S
+# endif
+# define machine_is_unit2s()	(machine_arch_type == MACH_TYPE_UNIT2S)
+#else
+# define machine_is_unit2s()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_A5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACER_A5
+# endif
+# define machine_is_acer_a5()	(machine_arch_type == MACH_TYPE_ACER_A5)
+#else
+# define machine_is_acer_a5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ETHERPRO_ISP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ETHERPRO_ISP
+# endif
+# define machine_is_etherpro_isp()	(machine_arch_type == MACH_TYPE_ETHERPRO_ISP)
+#else
+# define machine_is_etherpro_isp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STRETCHS7000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STRETCHS7000
+# endif
+# define machine_is_stretchs7000()	(machine_arch_type == MACH_TYPE_STRETCHS7000)
+#else
+# define machine_is_stretchs7000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_P87_SMARTSIM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_P87_SMARTSIM
+# endif
+# define machine_is_p87_smartsim()	(machine_arch_type == MACH_TYPE_P87_SMARTSIM)
+#else
+# define machine_is_p87_smartsim()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TULIP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TULIP
+# endif
+# define machine_is_tulip()	(machine_arch_type == MACH_TYPE_TULIP)
+#else
+# define machine_is_tulip()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SUNFLOWER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SUNFLOWER
+# endif
+# define machine_is_sunflower()	(machine_arch_type == MACH_TYPE_SUNFLOWER)
+#else
+# define machine_is_sunflower()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RIB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RIB
+# endif
+# define machine_is_rib()	(machine_arch_type == MACH_TYPE_RIB)
+#else
+# define machine_is_rib()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CLOD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CLOD
+# endif
+# define machine_is_clod()	(machine_arch_type == MACH_TYPE_CLOD)
+#else
+# define machine_is_clod()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RUMP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RUMP
+# endif
+# define machine_is_rump()	(machine_arch_type == MACH_TYPE_RUMP)
+#else
+# define machine_is_rump()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TENDERLOIN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TENDERLOIN
+# endif
+# define machine_is_tenderloin()	(machine_arch_type == MACH_TYPE_TENDERLOIN)
+#else
+# define machine_is_tenderloin()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHORTLOIN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHORTLOIN
+# endif
+# define machine_is_shortloin()	(machine_arch_type == MACH_TYPE_SHORTLOIN)
+#else
+# define machine_is_shortloin()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ANTARES
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ANTARES
+# endif
+# define machine_is_antares()	(machine_arch_type == MACH_TYPE_ANTARES)
+#else
+# define machine_is_antares()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WB40N
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WB40N
+# endif
+# define machine_is_wb40n()	(machine_arch_type == MACH_TYPE_WB40N)
+#else
+# define machine_is_wb40n()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HERRING
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HERRING
+# endif
+# define machine_is_herring()	(machine_arch_type == MACH_TYPE_HERRING)
+#else
+# define machine_is_herring()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NAXY400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NAXY400
+# endif
+# define machine_is_naxy400()	(machine_arch_type == MACH_TYPE_NAXY400)
+#else
+# define machine_is_naxy400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NAXY1200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NAXY1200
+# endif
+# define machine_is_naxy1200()	(machine_arch_type == MACH_TYPE_NAXY1200)
+#else
+# define machine_is_naxy1200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VPR200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VPR200
+# endif
+# define machine_is_vpr200()	(machine_arch_type == MACH_TYPE_VPR200)
+#else
+# define machine_is_vpr200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BUG20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BUG20
+# endif
+# define machine_is_bug20()	(machine_arch_type == MACH_TYPE_BUG20)
+#else
+# define machine_is_bug20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GOFLEXNET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GOFLEXNET
+# endif
+# define machine_is_goflexnet()	(machine_arch_type == MACH_TYPE_GOFLEXNET)
+#else
+# define machine_is_goflexnet()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TORBRECK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TORBRECK
+# endif
+# define machine_is_torbreck()	(machine_arch_type == MACH_TYPE_TORBRECK)
+#else
+# define machine_is_torbreck()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SAARB_MG1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SAARB_MG1
+# endif
+# define machine_is_saarb_mg1()	(machine_arch_type == MACH_TYPE_SAARB_MG1)
+#else
+# define machine_is_saarb_mg1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CALLISTO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CALLISTO
+# endif
+# define machine_is_callisto()	(machine_arch_type == MACH_TYPE_CALLISTO)
+#else
+# define machine_is_callisto()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MULTHSU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MULTHSU
+# endif
+# define machine_is_multhsu()	(machine_arch_type == MACH_TYPE_MULTHSU)
+#else
+# define machine_is_multhsu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SALUDA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SALUDA
+# endif
+# define machine_is_saluda()	(machine_arch_type == MACH_TYPE_SALUDA)
+#else
+# define machine_is_saluda()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PEMP_OMAP3_APOLLO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PEMP_OMAP3_APOLLO
+# endif
+# define machine_is_pemp_omap3_apollo()	(machine_arch_type == MACH_TYPE_PEMP_OMAP3_APOLLO)
+#else
+# define machine_is_pemp_omap3_apollo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VC0718
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VC0718
+# endif
+# define machine_is_vc0718()	(machine_arch_type == MACH_TYPE_VC0718)
+#else
+# define machine_is_vc0718()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MVBLX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MVBLX
+# endif
+# define machine_is_mvblx()	(machine_arch_type == MACH_TYPE_MVBLX)
+#else
+# define machine_is_mvblx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_INHAND_APEIRON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INHAND_APEIRON
+# endif
+# define machine_is_inhand_apeiron()	(machine_arch_type == MACH_TYPE_INHAND_APEIRON)
+#else
+# define machine_is_inhand_apeiron()	(0)
+#endif
+
+#ifdef CONFIG_MACH_INHAND_FURY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INHAND_FURY
+# endif
+# define machine_is_inhand_fury()	(machine_arch_type == MACH_TYPE_INHAND_FURY)
+#else
+# define machine_is_inhand_fury()	(0)
+#endif
+
+#ifdef CONFIG_MACH_INHAND_SIREN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INHAND_SIREN
+# endif
+# define machine_is_inhand_siren()	(machine_arch_type == MACH_TYPE_INHAND_SIREN)
+#else
+# define machine_is_inhand_siren()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HDNVP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HDNVP
+# endif
+# define machine_is_hdnvp()	(machine_arch_type == MACH_TYPE_HDNVP)
+#else
+# define machine_is_hdnvp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SOFTWINNER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SOFTWINNER
+# endif
+# define machine_is_softwinner()	(machine_arch_type == MACH_TYPE_SOFTWINNER)
+#else
+# define machine_is_softwinner()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PRIMA2_EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PRIMA2_EVB
+# endif
+# define machine_is_prima2_evb()	(machine_arch_type == MACH_TYPE_PRIMA2_EVB)
+#else
+# define machine_is_prima2_evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NAS6210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NAS6210
+# endif
+# define machine_is_nas6210()	(machine_arch_type == MACH_TYPE_NAS6210)
+#else
+# define machine_is_nas6210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UNISDEV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UNISDEV
+# endif
+# define machine_is_unisdev()	(machine_arch_type == MACH_TYPE_UNISDEV)
+#else
+# define machine_is_unisdev()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SBCA11
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SBCA11
+# endif
+# define machine_is_sbca11()	(machine_arch_type == MACH_TYPE_SBCA11)
+#else
+# define machine_is_sbca11()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SAGA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SAGA
+# endif
+# define machine_is_saga()	(machine_arch_type == MACH_TYPE_SAGA)
+#else
+# define machine_is_saga()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NS_K330
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NS_K330
+# endif
+# define machine_is_ns_k330()	(machine_arch_type == MACH_TYPE_NS_K330)
+#else
+# define machine_is_ns_k330()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TANNA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TANNA
+# endif
+# define machine_is_tanna()	(machine_arch_type == MACH_TYPE_TANNA)
+#else
+# define machine_is_tanna()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IMATE8502
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IMATE8502
+# endif
+# define machine_is_imate8502()	(machine_arch_type == MACH_TYPE_IMATE8502)
+#else
+# define machine_is_imate8502()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ASPEN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASPEN
+# endif
+# define machine_is_aspen()	(machine_arch_type == MACH_TYPE_ASPEN)
+#else
+# define machine_is_aspen()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAINTREE_CWAC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAINTREE_CWAC
+# endif
+# define machine_is_daintree_cwac()	(machine_arch_type == MACH_TYPE_DAINTREE_CWAC)
+#else
+# define machine_is_daintree_cwac()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZMX25
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZMX25
+# endif
+# define machine_is_zmx25()	(machine_arch_type == MACH_TYPE_ZMX25)
+#else
+# define machine_is_zmx25()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MAPLE1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MAPLE1
+# endif
+# define machine_is_maple1()	(machine_arch_type == MACH_TYPE_MAPLE1)
+#else
+# define machine_is_maple1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X72_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X72_SURF
+# endif
+# define machine_is_qsd8x72_surf()	(machine_arch_type == MACH_TYPE_QSD8X72_SURF)
+#else
+# define machine_is_qsd8x72_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QSD8X72_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QSD8X72_FFA
+# endif
+# define machine_is_qsd8x72_ffa()	(machine_arch_type == MACH_TYPE_QSD8X72_FFA)
+#else
+# define machine_is_qsd8x72_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ABILENE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ABILENE
+# endif
+# define machine_is_abilene()	(machine_arch_type == MACH_TYPE_ABILENE)
+#else
+# define machine_is_abilene()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EIGEN_TTR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EIGEN_TTR
+# endif
+# define machine_is_eigen_ttr()	(machine_arch_type == MACH_TYPE_EIGEN_TTR)
+#else
+# define machine_is_eigen_ttr()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IOMEGA_IX2_200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IOMEGA_IX2_200
+# endif
+# define machine_is_iomega_ix2_200()	(machine_arch_type == MACH_TYPE_IOMEGA_IX2_200)
+#else
+# define machine_is_iomega_ix2_200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CORETEC_VCX7400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CORETEC_VCX7400
+# endif
+# define machine_is_coretec_vcx7400()	(machine_arch_type == MACH_TYPE_CORETEC_VCX7400)
+#else
+# define machine_is_coretec_vcx7400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SANTIAGO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SANTIAGO
+# endif
+# define machine_is_santiago()	(machine_arch_type == MACH_TYPE_SANTIAGO)
+#else
+# define machine_is_santiago()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX257SOL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX257SOL
+# endif
+# define machine_is_mx257sol()	(machine_arch_type == MACH_TYPE_MX257SOL)
+#else
+# define machine_is_mx257sol()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STRASBOURG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STRASBOURG
+# endif
+# define machine_is_strasbourg()	(machine_arch_type == MACH_TYPE_STRASBOURG)
+#else
+# define machine_is_strasbourg()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_FLUID
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8X60_FLUID
+# endif
+# define machine_is_msm8x60_fluid()	(machine_arch_type == MACH_TYPE_MSM8X60_FLUID)
+#else
+# define machine_is_msm8x60_fluid()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQV5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMARTQV5
+# endif
+# define machine_is_smartqv5()	(machine_arch_type == MACH_TYPE_SMARTQV5)
+#else
+# define machine_is_smartqv5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQV3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMARTQV3
+# endif
+# define machine_is_smartqv3()	(machine_arch_type == MACH_TYPE_SMARTQV3)
+#else
+# define machine_is_smartqv3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMARTQV7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMARTQV7
+# endif
+# define machine_is_smartqv7()	(machine_arch_type == MACH_TYPE_SMARTQV7)
+#else
+# define machine_is_smartqv7()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PAZ00
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PAZ00
+# endif
+# define machine_is_paz00()	(machine_arch_type == MACH_TYPE_PAZ00)
+#else
+# define machine_is_paz00()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACMENETUSFOXG20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACMENETUSFOXG20
+# endif
+# define machine_is_acmenetusfoxg20()	(machine_arch_type == MACH_TYPE_ACMENETUSFOXG20)
+#else
+# define machine_is_acmenetusfoxg20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FWBD_0404
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FWBD_0404
+# endif
+# define machine_is_fwbd_0404()	(machine_arch_type == MACH_TYPE_FWBD_0404)
+#else
+# define machine_is_fwbd_0404()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HDGU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HDGU
+# endif
+# define machine_is_hdgu()	(machine_arch_type == MACH_TYPE_HDGU)
+#else
+# define machine_is_hdgu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PYRAMID
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PYRAMID
+# endif
+# define machine_is_pyramid()	(machine_arch_type == MACH_TYPE_PYRAMID)
+#else
+# define machine_is_pyramid()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EPIPHAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EPIPHAN
+# endif
+# define machine_is_epiphan()	(machine_arch_type == MACH_TYPE_EPIPHAN)
+#else
+# define machine_is_epiphan()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_BENDER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_BENDER
+# endif
+# define machine_is_omap_bender()	(machine_arch_type == MACH_TYPE_OMAP_BENDER)
+#else
+# define machine_is_omap_bender()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GURNARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GURNARD
+# endif
+# define machine_is_gurnard()	(machine_arch_type == MACH_TYPE_GURNARD)
+#else
+# define machine_is_gurnard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GTL_IT5100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GTL_IT5100
+# endif
+# define machine_is_gtl_it5100()	(machine_arch_type == MACH_TYPE_GTL_IT5100)
+#else
+# define machine_is_gtl_it5100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BCM2708
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BCM2708
+# endif
+# define machine_is_bcm2708()	(machine_arch_type == MACH_TYPE_BCM2708)
+#else
+# define machine_is_bcm2708()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_GGC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_GGC
+# endif
+# define machine_is_mx51_ggc()	(machine_arch_type == MACH_TYPE_MX51_GGC)
+#else
+# define machine_is_mx51_ggc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHARESPACE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHARESPACE
+# endif
+# define machine_is_sharespace()	(machine_arch_type == MACH_TYPE_SHARESPACE)
+#else
+# define machine_is_sharespace()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HABA_KNX_EXPLORER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HABA_KNX_EXPLORER
+# endif
+# define machine_is_haba_knx_explorer()	(machine_arch_type == MACH_TYPE_HABA_KNX_EXPLORER)
+#else
+# define machine_is_haba_knx_explorer()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SIMTEC_KIRKMOD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIMTEC_KIRKMOD
+# endif
+# define machine_is_simtec_kirkmod()	(machine_arch_type == MACH_TYPE_SIMTEC_KIRKMOD)
+#else
+# define machine_is_simtec_kirkmod()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CRUX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CRUX
+# endif
+# define machine_is_crux()	(machine_arch_type == MACH_TYPE_CRUX)
+#else
+# define machine_is_crux()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_BRAVO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_BRAVO
+# endif
+# define machine_is_mx51_bravo()	(machine_arch_type == MACH_TYPE_MX51_BRAVO)
+#else
+# define machine_is_mx51_bravo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CHARON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHARON
+# endif
+# define machine_is_charon()	(machine_arch_type == MACH_TYPE_CHARON)
+#else
+# define machine_is_charon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PICOCOM3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PICOCOM3
+# endif
+# define machine_is_picocom3()	(machine_arch_type == MACH_TYPE_PICOCOM3)
+#else
+# define machine_is_picocom3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PICOCOM4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PICOCOM4
+# endif
+# define machine_is_picocom4()	(machine_arch_type == MACH_TYPE_PICOCOM4)
+#else
+# define machine_is_picocom4()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SERRANO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SERRANO
+# endif
+# define machine_is_serrano()	(machine_arch_type == MACH_TYPE_SERRANO)
+#else
+# define machine_is_serrano()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DOUBLESHOT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DOUBLESHOT
+# endif
+# define machine_is_doubleshot()	(machine_arch_type == MACH_TYPE_DOUBLESHOT)
+#else
+# define machine_is_doubleshot()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EVSY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EVSY
+# endif
+# define machine_is_evsy()	(machine_arch_type == MACH_TYPE_EVSY)
+#else
+# define machine_is_evsy()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HUASHAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HUASHAN
+# endif
+# define machine_is_huashan()	(machine_arch_type == MACH_TYPE_HUASHAN)
+#else
+# define machine_is_huashan()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LAUSANNE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LAUSANNE
+# endif
+# define machine_is_lausanne()	(machine_arch_type == MACH_TYPE_LAUSANNE)
+#else
+# define machine_is_lausanne()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EMERALD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EMERALD
+# endif
+# define machine_is_emerald()	(machine_arch_type == MACH_TYPE_EMERALD)
+#else
+# define machine_is_emerald()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TQMA35
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TQMA35
+# endif
+# define machine_is_tqma35()	(machine_arch_type == MACH_TYPE_TQMA35)
+#else
+# define machine_is_tqma35()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MARVEL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MARVEL
+# endif
+# define machine_is_marvel()	(machine_arch_type == MACH_TYPE_MARVEL)
+#else
+# define machine_is_marvel()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MANUAE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MANUAE
+# endif
+# define machine_is_manuae()	(machine_arch_type == MACH_TYPE_MANUAE)
+#else
+# define machine_is_manuae()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CHACHA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHACHA
+# endif
+# define machine_is_chacha()	(machine_arch_type == MACH_TYPE_CHACHA)
+#else
+# define machine_is_chacha()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LEMON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LEMON
+# endif
+# define machine_is_lemon()	(machine_arch_type == MACH_TYPE_LEMON)
+#else
+# define machine_is_lemon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSC
+# endif
+# define machine_is_csc()	(machine_arch_type == MACH_TYPE_CSC)
+#else
+# define machine_is_csc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GIRA_KNXIP_ROUTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GIRA_KNXIP_ROUTER
+# endif
+# define machine_is_gira_knxip_router()	(machine_arch_type == MACH_TYPE_GIRA_KNXIP_ROUTER)
+#else
+# define machine_is_gira_knxip_router()	(0)
+#endif
+
+#ifdef CONFIG_MACH_T20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_T20
+# endif
+# define machine_is_t20()	(machine_arch_type == MACH_TYPE_T20)
+#else
+# define machine_is_t20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HDMINI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HDMINI
+# endif
+# define machine_is_hdmini()	(machine_arch_type == MACH_TYPE_HDMINI)
+#else
+# define machine_is_hdmini()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SCIPHONE_G2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCIPHONE_G2
+# endif
+# define machine_is_sciphone_g2()	(machine_arch_type == MACH_TYPE_SCIPHONE_G2)
+#else
+# define machine_is_sciphone_g2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EXPRESS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EXPRESS
+# endif
+# define machine_is_express()	(machine_arch_type == MACH_TYPE_EXPRESS)
+#else
+# define machine_is_express()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EXPRESS_KT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EXPRESS_KT
+# endif
+# define machine_is_express_kt()	(machine_arch_type == MACH_TYPE_EXPRESS_KT)
+#else
+# define machine_is_express_kt()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MAXIMASP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MAXIMASP
+# endif
+# define machine_is_maximasp()	(machine_arch_type == MACH_TYPE_MAXIMASP)
+#else
+# define machine_is_maximasp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NITROGEN_IMX51
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NITROGEN_IMX51
+# endif
+# define machine_is_nitrogen_imx51()	(machine_arch_type == MACH_TYPE_NITROGEN_IMX51)
+#else
+# define machine_is_nitrogen_imx51()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NITROGEN_IMX53
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NITROGEN_IMX53
+# endif
+# define machine_is_nitrogen_imx53()	(machine_arch_type == MACH_TYPE_NITROGEN_IMX53)
+#else
+# define machine_is_nitrogen_imx53()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SUNFIRE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SUNFIRE
+# endif
+# define machine_is_sunfire()	(machine_arch_type == MACH_TYPE_SUNFIRE)
+#else
+# define machine_is_sunfire()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AROWANA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AROWANA
+# endif
+# define machine_is_arowana()	(machine_arch_type == MACH_TYPE_AROWANA)
+#else
+# define machine_is_arowana()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TEGRA_DAYTONA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TEGRA_DAYTONA
+# endif
+# define machine_is_tegra_daytona()	(machine_arch_type == MACH_TYPE_TEGRA_DAYTONA)
+#else
+# define machine_is_tegra_daytona()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TEGRA_SWORDFISH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TEGRA_SWORDFISH
+# endif
+# define machine_is_tegra_swordfish()	(machine_arch_type == MACH_TYPE_TEGRA_SWORDFISH)
+#else
+# define machine_is_tegra_swordfish()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDISON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDISON
+# endif
+# define machine_is_edison()	(machine_arch_type == MACH_TYPE_EDISON)
+#else
+# define machine_is_edison()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SVP8500V1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SVP8500V1
+# endif
+# define machine_is_svp8500v1()	(machine_arch_type == MACH_TYPE_SVP8500V1)
+#else
+# define machine_is_svp8500v1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SVP8500V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SVP8500V2
+# endif
+# define machine_is_svp8500v2()	(machine_arch_type == MACH_TYPE_SVP8500V2)
+#else
+# define machine_is_svp8500v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SVP5500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SVP5500
+# endif
+# define machine_is_svp5500()	(machine_arch_type == MACH_TYPE_SVP5500)
+#else
+# define machine_is_svp5500()	(0)
+#endif
+
+#ifdef CONFIG_MACH_B5500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_B5500
+# endif
+# define machine_is_b5500()	(machine_arch_type == MACH_TYPE_B5500)
+#else
+# define machine_is_b5500()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S5500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S5500
+# endif
+# define machine_is_s5500()	(machine_arch_type == MACH_TYPE_S5500)
+#else
+# define machine_is_s5500()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ICON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ICON
+# endif
+# define machine_is_icon()	(machine_arch_type == MACH_TYPE_ICON)
+#else
+# define machine_is_icon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ELEPHANT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ELEPHANT
+# endif
+# define machine_is_elephant()	(machine_arch_type == MACH_TYPE_ELEPHANT)
+#else
+# define machine_is_elephant()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHOOTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHOOTER
+# endif
+# define machine_is_shooter()	(machine_arch_type == MACH_TYPE_SHOOTER)
+#else
+# define machine_is_shooter()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPADE_LTE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPADE_LTE
+# endif
+# define machine_is_spade_lte()	(machine_arch_type == MACH_TYPE_SPADE_LTE)
+#else
+# define machine_is_spade_lte()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PHILHWANI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PHILHWANI
+# endif
+# define machine_is_philhwani()	(machine_arch_type == MACH_TYPE_PHILHWANI)
+#else
+# define machine_is_philhwani()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GSNCOMM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GSNCOMM
+# endif
+# define machine_is_gsncomm()	(machine_arch_type == MACH_TYPE_GSNCOMM)
+#else
+# define machine_is_gsncomm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STRASBOURG_A2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STRASBOURG_A2
+# endif
+# define machine_is_strasbourg_a2()	(machine_arch_type == MACH_TYPE_STRASBOURG_A2)
+#else
+# define machine_is_strasbourg_a2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MMM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MMM
+# endif
+# define machine_is_mmm()	(machine_arch_type == MACH_TYPE_MMM)
+#else
+# define machine_is_mmm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM365_BV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM365_BV
+# endif
+# define machine_is_davinci_dm365_bv()	(machine_arch_type == MACH_TYPE_DAVINCI_DM365_BV)
+#else
+# define machine_is_davinci_dm365_bv()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AG5EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AG5EVM
+# endif
+# define machine_is_ag5evm()	(machine_arch_type == MACH_TYPE_AG5EVM)
+#else
+# define machine_is_ag5evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SC575PLC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SC575PLC
+# endif
+# define machine_is_sc575plc()	(machine_arch_type == MACH_TYPE_SC575PLC)
+#else
+# define machine_is_sc575plc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SC575IPC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SC575IPC
+# endif
+# define machine_is_sc575hmi()	(machine_arch_type == MACH_TYPE_SC575IPC)
+#else
+# define machine_is_sc575hmi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_TDM3730
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_TDM3730
+# endif
+# define machine_is_omap3_tdm3730()	(machine_arch_type == MACH_TYPE_OMAP3_TDM3730)
+#else
+# define machine_is_omap3_tdm3730()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOP9000_EVAL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOP9000_EVAL
+# endif
+# define machine_is_top9000_eval()	(machine_arch_type == MACH_TYPE_TOP9000_EVAL)
+#else
+# define machine_is_top9000_eval()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOP9000_SU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOP9000_SU
+# endif
+# define machine_is_top9000_su()	(machine_arch_type == MACH_TYPE_TOP9000_SU)
+#else
+# define machine_is_top9000_su()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UTM300
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UTM300
+# endif
+# define machine_is_utm300()	(machine_arch_type == MACH_TYPE_UTM300)
+#else
+# define machine_is_utm300()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TSUNAGI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TSUNAGI
+# endif
+# define machine_is_tsunagi()	(machine_arch_type == MACH_TYPE_TSUNAGI)
+#else
+# define machine_is_tsunagi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS75XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS75XX
+# endif
+# define machine_is_ts75xx()	(machine_arch_type == MACH_TYPE_TS75XX)
+#else
+# define machine_is_ts75xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS47XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS47XX
+# endif
+# define machine_is_ts47xx()	(machine_arch_type == MACH_TYPE_TS47XX)
+#else
+# define machine_is_ts47xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DA850_K5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DA850_K5
+# endif
+# define machine_is_da850_k5()	(machine_arch_type == MACH_TYPE_DA850_K5)
+#else
+# define machine_is_da850_k5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AX502
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AX502
+# endif
+# define machine_is_ax502()	(machine_arch_type == MACH_TYPE_AX502)
+#else
+# define machine_is_ax502()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IGEP0032
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IGEP0032
+# endif
+# define machine_is_igep0032()	(machine_arch_type == MACH_TYPE_IGEP0032)
+#else
+# define machine_is_igep0032()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ANTERO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ANTERO
+# endif
+# define machine_is_antero()	(machine_arch_type == MACH_TYPE_ANTERO)
+#else
+# define machine_is_antero()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SYNERGY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SYNERGY
+# endif
+# define machine_is_synergy()	(machine_arch_type == MACH_TYPE_SYNERGY)
+#else
+# define machine_is_synergy()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ICS_IF_VOIP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ICS_IF_VOIP
+# endif
+# define machine_is_ics_if_voip()	(machine_arch_type == MACH_TYPE_ICS_IF_VOIP)
+#else
+# define machine_is_ics_if_voip()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WLF_CRAGG_6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WLF_CRAGG_6410
+# endif
+# define machine_is_wlf_cragg_6410()	(machine_arch_type == MACH_TYPE_WLF_CRAGG_6410)
+#else
+# define machine_is_wlf_cragg_6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PUNICA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PUNICA
+# endif
+# define machine_is_punica()	(machine_arch_type == MACH_TYPE_PUNICA)
+#else
+# define machine_is_punica()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRIMSLICE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRIMSLICE
+# endif
+# define machine_is_trimslice()	(machine_arch_type == MACH_TYPE_TRIMSLICE)
+#else
+# define machine_is_trimslice()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX27_WMULTRA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX27_WMULTRA
+# endif
+# define machine_is_mx27_wmultra()	(machine_arch_type == MACH_TYPE_MX27_WMULTRA)
+#else
+# define machine_is_mx27_wmultra()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MACKEREL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MACKEREL
+# endif
+# define machine_is_mackerel()	(machine_arch_type == MACH_TYPE_MACKEREL)
+#else
+# define machine_is_mackerel()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FA9X27
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FA9X27
+# endif
+# define machine_is_fa9x27()	(machine_arch_type == MACH_TYPE_FA9X27)
+#else
+# define machine_is_fa9x27()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NS2816TB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NS2816TB
+# endif
+# define machine_is_ns2816tb()	(machine_arch_type == MACH_TYPE_NS2816TB)
+#else
+# define machine_is_ns2816tb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NS2816_NTPAD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NS2816_NTPAD
+# endif
+# define machine_is_ns2816_ntpad()	(machine_arch_type == MACH_TYPE_NS2816_NTPAD)
+#else
+# define machine_is_ns2816_ntpad()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NS2816_NTNB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NS2816_NTNB
+# endif
+# define machine_is_ns2816_ntnb()	(machine_arch_type == MACH_TYPE_NS2816_NTNB)
+#else
+# define machine_is_ns2816_ntnb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KAEN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KAEN
+# endif
+# define machine_is_kaen()	(machine_arch_type == MACH_TYPE_KAEN)
+#else
+# define machine_is_kaen()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NV1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NV1000
+# endif
+# define machine_is_nv1000()	(machine_arch_type == MACH_TYPE_NV1000)
+#else
+# define machine_is_nv1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC950TS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC950TS
+# endif
+# define machine_is_nuc950ts()	(machine_arch_type == MACH_TYPE_NUC950TS)
+#else
+# define machine_is_nuc950ts()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOKIA_RM680
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOKIA_RM680
+# endif
+# define machine_is_nokia_rm680()	(machine_arch_type == MACH_TYPE_NOKIA_RM680)
+#else
+# define machine_is_nokia_rm680()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AST2200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AST2200
+# endif
+# define machine_is_ast2200()	(machine_arch_type == MACH_TYPE_AST2200)
+#else
+# define machine_is_ast2200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LEAD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LEAD
+# endif
+# define machine_is_lead()	(machine_arch_type == MACH_TYPE_LEAD)
+#else
+# define machine_is_lead()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UNINO1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UNINO1
+# endif
+# define machine_is_unino1()	(machine_arch_type == MACH_TYPE_UNINO1)
+#else
+# define machine_is_unino1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GREECO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GREECO
+# endif
+# define machine_is_greeco()	(machine_arch_type == MACH_TYPE_GREECO)
+#else
+# define machine_is_greeco()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VERDI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VERDI
+# endif
+# define machine_is_verdi()	(machine_arch_type == MACH_TYPE_VERDI)
+#else
+# define machine_is_verdi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DM6446_ADBOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM6446_ADBOX
+# endif
+# define machine_is_dm6446_adbox()	(machine_arch_type == MACH_TYPE_DM6446_ADBOX)
+#else
+# define machine_is_dm6446_adbox()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QUAD_SALSA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QUAD_SALSA
+# endif
+# define machine_is_quad_salsa()	(machine_arch_type == MACH_TYPE_QUAD_SALSA)
+#else
+# define machine_is_quad_salsa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ABB_GMA_1_1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ABB_GMA_1_1
+# endif
+# define machine_is_abb_gma_1_1()	(machine_arch_type == MACH_TYPE_ABB_GMA_1_1)
+#else
+# define machine_is_abb_gma_1_1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SVCID
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SVCID
+# endif
+# define machine_is_svcid()	(machine_arch_type == MACH_TYPE_SVCID)
+#else
+# define machine_is_svcid()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8960_SIM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8960_SIM
+# endif
+# define machine_is_msm8960_sim()	(machine_arch_type == MACH_TYPE_MSM8960_SIM)
+#else
+# define machine_is_msm8960_sim()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8960_RUMI3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8960_RUMI3
+# endif
+# define machine_is_msm8960_rumi3()	(machine_arch_type == MACH_TYPE_MSM8960_RUMI3)
+#else
+# define machine_is_msm8960_rumi3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ICON_G
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ICON_G
+# endif
+# define machine_is_icon_g()	(machine_arch_type == MACH_TYPE_ICON_G)
+#else
+# define machine_is_icon_g()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MB3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MB3
+# endif
+# define machine_is_mb3()	(machine_arch_type == MACH_TYPE_MB3)
+#else
+# define machine_is_mb3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GSIA18S
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GSIA18S
+# endif
+# define machine_is_gsia18s()	(machine_arch_type == MACH_TYPE_GSIA18S)
+#else
+# define machine_is_gsia18s()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PIVICC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PIVICC
+# endif
+# define machine_is_pivicc()	(machine_arch_type == MACH_TYPE_PIVICC)
+#else
+# define machine_is_pivicc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM048
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM048
+# endif
+# define machine_is_pcm048()	(machine_arch_type == MACH_TYPE_PCM048)
+#else
+# define machine_is_pcm048()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DDS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DDS
+# endif
+# define machine_is_dds()	(machine_arch_type == MACH_TYPE_DDS)
+#else
+# define machine_is_dds()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CHALTEN_XA1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHALTEN_XA1
+# endif
+# define machine_is_chalten_xa1()	(machine_arch_type == MACH_TYPE_CHALTEN_XA1)
+#else
+# define machine_is_chalten_xa1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS48XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS48XX
+# endif
+# define machine_is_ts48xx()	(machine_arch_type == MACH_TYPE_TS48XX)
+#else
+# define machine_is_ts48xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TONGA2_TFTTIMER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TONGA2_TFTTIMER
+# endif
+# define machine_is_tonga2_tfttimer()	(machine_arch_type == MACH_TYPE_TONGA2_TFTTIMER)
+#else
+# define machine_is_tonga2_tfttimer()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WHISTLER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WHISTLER
+# endif
+# define machine_is_whistler()	(machine_arch_type == MACH_TYPE_WHISTLER)
+#else
+# define machine_is_whistler()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ASL_PHOENIX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASL_PHOENIX
+# endif
+# define machine_is_asl_phoenix()	(machine_arch_type == MACH_TYPE_ASL_PHOENIX)
+#else
+# define machine_is_asl_phoenix()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263OTLITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9263OTLITE
+# endif
+# define machine_is_at91sam9263otlite()	(machine_arch_type == MACH_TYPE_AT91SAM9263OTLITE)
+#else
+# define machine_is_at91sam9263otlite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DDPLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DDPLUG
+# endif
+# define machine_is_ddplug()	(machine_arch_type == MACH_TYPE_DDPLUG)
+#else
+# define machine_is_ddplug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_D2PLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_D2PLUG
+# endif
+# define machine_is_d2plug()	(machine_arch_type == MACH_TYPE_D2PLUG)
+#else
+# define machine_is_d2plug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KZM9D
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KZM9D
+# endif
+# define machine_is_kzm9d()	(machine_arch_type == MACH_TYPE_KZM9D)
+#else
+# define machine_is_kzm9d()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VERDI_LTE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VERDI_LTE
+# endif
+# define machine_is_verdi_lte()	(machine_arch_type == MACH_TYPE_VERDI_LTE)
+#else
+# define machine_is_verdi_lte()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NANOZOOM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NANOZOOM
+# endif
+# define machine_is_nanozoom()	(machine_arch_type == MACH_TYPE_NANOZOOM)
+#else
+# define machine_is_nanozoom()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DM3730_SOM_LV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM3730_SOM_LV
+# endif
+# define machine_is_dm3730_som_lv()	(machine_arch_type == MACH_TYPE_DM3730_SOM_LV)
+#else
+# define machine_is_dm3730_som_lv()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DM3730_TORPEDO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM3730_TORPEDO
+# endif
+# define machine_is_dm3730_torpedo()	(machine_arch_type == MACH_TYPE_DM3730_TORPEDO)
+#else
+# define machine_is_dm3730_torpedo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ANCHOVY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ANCHOVY
+# endif
+# define machine_is_anchovy()	(machine_arch_type == MACH_TYPE_ANCHOVY)
+#else
+# define machine_is_anchovy()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RE2REV20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RE2REV20
+# endif
+# define machine_is_re2rev20()	(machine_arch_type == MACH_TYPE_RE2REV20)
+#else
+# define machine_is_re2rev20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RE2REV21
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RE2REV21
+# endif
+# define machine_is_re2rev21()	(machine_arch_type == MACH_TYPE_RE2REV21)
+#else
+# define machine_is_re2rev21()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CNS21XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CNS21XX
+# endif
+# define machine_is_cns21xx()	(machine_arch_type == MACH_TYPE_CNS21XX)
+#else
+# define machine_is_cns21xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RIDER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RIDER
+# endif
+# define machine_is_rider()	(machine_arch_type == MACH_TYPE_RIDER)
+#else
+# define machine_is_rider()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NSK330
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NSK330
+# endif
+# define machine_is_nsk330()	(machine_arch_type == MACH_TYPE_NSK330)
+#else
+# define machine_is_nsk330()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CNS2133EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CNS2133EVB
+# endif
+# define machine_is_cns2133evb()	(machine_arch_type == MACH_TYPE_CNS2133EVB)
+#else
+# define machine_is_cns2133evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_Z3_816X_MOD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_Z3_816X_MOD
+# endif
+# define machine_is_z3_816x_mod()	(machine_arch_type == MACH_TYPE_Z3_816X_MOD)
+#else
+# define machine_is_z3_816x_mod()	(0)
+#endif
+
+#ifdef CONFIG_MACH_Z3_814X_MOD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_Z3_814X_MOD
+# endif
+# define machine_is_z3_814x_mod()	(machine_arch_type == MACH_TYPE_Z3_814X_MOD)
+#else
+# define machine_is_z3_814x_mod()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BEECT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BEECT
+# endif
+# define machine_is_beect()	(machine_arch_type == MACH_TYPE_BEECT)
+#else
+# define machine_is_beect()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DMA_THUNDERBUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DMA_THUNDERBUG
+# endif
+# define machine_is_dma_thunderbug()	(machine_arch_type == MACH_TYPE_DMA_THUNDERBUG)
+#else
+# define machine_is_dma_thunderbug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMN_AT91SAM9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMN_AT91SAM9G20
+# endif
+# define machine_is_omn_at91sam9g20()	(machine_arch_type == MACH_TYPE_OMN_AT91SAM9G20)
+#else
+# define machine_is_omn_at91sam9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX25_E2S_UC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX25_E2S_UC
+# endif
+# define machine_is_mx25_e2s_uc()	(machine_arch_type == MACH_TYPE_MX25_E2S_UC)
+#else
+# define machine_is_mx25_e2s_uc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MIONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MIONE
+# endif
+# define machine_is_mione()	(machine_arch_type == MACH_TYPE_MIONE)
+#else
+# define machine_is_mione()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOP9000_TCU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOP9000_TCU
+# endif
+# define machine_is_top9000_tcu()	(machine_arch_type == MACH_TYPE_TOP9000_TCU)
+#else
+# define machine_is_top9000_tcu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOP9000_BSL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOP9000_BSL
+# endif
+# define machine_is_top9000_bsl()	(machine_arch_type == MACH_TYPE_TOP9000_BSL)
+#else
+# define machine_is_top9000_bsl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KINGDOM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KINGDOM
+# endif
+# define machine_is_kingdom()	(machine_arch_type == MACH_TYPE_KINGDOM)
+#else
+# define machine_is_kingdom()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADILLO460
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMADILLO460
+# endif
+# define machine_is_armadillo460()	(machine_arch_type == MACH_TYPE_ARMADILLO460)
+#else
+# define machine_is_armadillo460()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LQ2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LQ2
+# endif
+# define machine_is_lq2()	(machine_arch_type == MACH_TYPE_LQ2)
+#else
+# define machine_is_lq2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SWEDA_TMS2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SWEDA_TMS2
+# endif
+# define machine_is_sweda_tms2()	(machine_arch_type == MACH_TYPE_SWEDA_TMS2)
+#else
+# define machine_is_sweda_tms2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX53_LOCO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX53_LOCO
+# endif
+# define machine_is_mx53_loco()	(machine_arch_type == MACH_TYPE_MX53_LOCO)
+#else
+# define machine_is_mx53_loco()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_A8
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACER_A8
+# endif
+# define machine_is_acer_a8()	(machine_arch_type == MACH_TYPE_ACER_A8)
+#else
+# define machine_is_acer_a8()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_GAUGUIN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACER_GAUGUIN
+# endif
+# define machine_is_acer_gauguin()	(machine_arch_type == MACH_TYPE_ACER_GAUGUIN)
+#else
+# define machine_is_acer_gauguin()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GUPPY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GUPPY
+# endif
+# define machine_is_guppy()	(machine_arch_type == MACH_TYPE_GUPPY)
+#else
+# define machine_is_guppy()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX61_ARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX61_ARD
+# endif
+# define machine_is_mx61_ard()	(machine_arch_type == MACH_TYPE_MX61_ARD)
+#else
+# define machine_is_mx61_ard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TX53
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TX53
+# endif
+# define machine_is_tx53()	(machine_arch_type == MACH_TYPE_TX53)
+#else
+# define machine_is_tx53()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAPL138_CASE_A3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAPL138_CASE_A3
+# endif
+# define machine_is_omapl138_case_a3()	(machine_arch_type == MACH_TYPE_OMAPL138_CASE_A3)
+#else
+# define machine_is_omapl138_case_a3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UEMD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UEMD
+# endif
+# define machine_is_uemd()	(machine_arch_type == MACH_TYPE_UEMD)
+#else
+# define machine_is_uemd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX51MUT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CCWMX51MUT
+# endif
+# define machine_is_ccwmx51mut()	(machine_arch_type == MACH_TYPE_CCWMX51MUT)
+#else
+# define machine_is_ccwmx51mut()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROCKHOPPER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROCKHOPPER
+# endif
+# define machine_is_rockhopper()	(machine_arch_type == MACH_TYPE_ROCKHOPPER)
+#else
+# define machine_is_rockhopper()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ENCORE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ENCORE
+# endif
+# define machine_is_encore()	(machine_arch_type == MACH_TYPE_ENCORE)
+#else
+# define machine_is_encore()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HKDKC100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HKDKC100
+# endif
+# define machine_is_hkdkc100()	(machine_arch_type == MACH_TYPE_HKDKC100)
+#else
+# define machine_is_hkdkc100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS42XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS42XX
+# endif
+# define machine_is_ts42xx()	(machine_arch_type == MACH_TYPE_TS42XX)
+#else
+# define machine_is_ts42xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AEBL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AEBL
+# endif
+# define machine_is_aebl()	(machine_arch_type == MACH_TYPE_AEBL)
+#else
+# define machine_is_aebl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WARIO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WARIO
+# endif
+# define machine_is_wario()	(machine_arch_type == MACH_TYPE_WARIO)
+#else
+# define machine_is_wario()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GFS_SPM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GFS_SPM
+# endif
+# define machine_is_gfs_spm()	(machine_arch_type == MACH_TYPE_GFS_SPM)
+#else
+# define machine_is_gfs_spm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CM_T3730
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CM_T3730
+# endif
+# define machine_is_cm_t3730()	(machine_arch_type == MACH_TYPE_CM_T3730)
+#else
+# define machine_is_cm_t3730()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ISC3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ISC3
+# endif
+# define machine_is_isc3()	(machine_arch_type == MACH_TYPE_ISC3)
+#else
+# define machine_is_isc3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RASCAL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RASCAL
+# endif
+# define machine_is_rascal()	(machine_arch_type == MACH_TYPE_RASCAL)
+#else
+# define machine_is_rascal()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HREFV60
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HREFV60
+# endif
+# define machine_is_hrefv60()	(machine_arch_type == MACH_TYPE_HREFV60)
+#else
+# define machine_is_hrefv60()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TPT_2_0
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TPT_2_0
+# endif
+# define machine_is_tpt_2_0()	(machine_arch_type == MACH_TYPE_TPT_2_0)
+#else
+# define machine_is_tpt_2_0()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPLENDOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPLENDOR
+# endif
+# define machine_is_splendor()	(machine_arch_type == MACH_TYPE_SPLENDOR)
+#else
+# define machine_is_splendor()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8X60_QT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8X60_QT
+# endif
+# define machine_is_msm8x60_qt()	(machine_arch_type == MACH_TYPE_MSM8X60_QT)
+#else
+# define machine_is_msm8x60_qt()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTC_HD_MINI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTC_HD_MINI
+# endif
+# define machine_is_htc_hd_mini()	(machine_arch_type == MACH_TYPE_HTC_HD_MINI)
+#else
+# define machine_is_htc_hd_mini()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ATHENE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ATHENE
+# endif
+# define machine_is_athene()	(machine_arch_type == MACH_TYPE_ATHENE)
+#else
+# define machine_is_athene()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DEEP_R_EK_1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DEEP_R_EK_1
+# endif
+# define machine_is_deep_r_ek_1()	(machine_arch_type == MACH_TYPE_DEEP_R_EK_1)
+#else
+# define machine_is_deep_r_ek_1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VIVOW_CT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VIVOW_CT
+# endif
+# define machine_is_vivow_ct()	(machine_arch_type == MACH_TYPE_VIVOW_CT)
+#else
+# define machine_is_vivow_ct()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NERY_1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NERY_1000
+# endif
+# define machine_is_nery_1000()	(machine_arch_type == MACH_TYPE_NERY_1000)
+#else
+# define machine_is_nery_1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RFL109145_SSRV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RFL109145_SSRV
+# endif
+# define machine_is_rfl109145_ssrv()	(machine_arch_type == MACH_TYPE_RFL109145_SSRV)
+#else
+# define machine_is_rfl109145_ssrv()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NMH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NMH
+# endif
+# define machine_is_nmh()	(machine_arch_type == MACH_TYPE_NMH)
+#else
+# define machine_is_nmh()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WN802T
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WN802T
+# endif
+# define machine_is_wn802t()	(machine_arch_type == MACH_TYPE_WN802T)
+#else
+# define machine_is_wn802t()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DRAGONET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DRAGONET
+# endif
+# define machine_is_dragonet()	(machine_arch_type == MACH_TYPE_DRAGONET)
+#else
+# define machine_is_dragonet()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263DESK16L
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9263DESK16L
+# endif
+# define machine_is_at91sam9263desk16l()	(machine_arch_type == MACH_TYPE_AT91SAM9263DESK16L)
+#else
+# define machine_is_at91sam9263desk16l()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BCMHANA_SV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BCMHANA_SV
+# endif
+# define machine_is_bcmhana_sv()	(machine_arch_type == MACH_TYPE_BCMHANA_SV)
+#else
+# define machine_is_bcmhana_sv()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BCMHANA_TABLET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BCMHANA_TABLET
+# endif
+# define machine_is_bcmhana_tablet()	(machine_arch_type == MACH_TYPE_BCMHANA_TABLET)
+#else
+# define machine_is_bcmhana_tablet()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KOI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KOI
+# endif
+# define machine_is_koi()	(machine_arch_type == MACH_TYPE_KOI)
+#else
+# define machine_is_koi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS4800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS4800
+# endif
+# define machine_is_ts4800()	(machine_arch_type == MACH_TYPE_TS4800)
+#else
+# define machine_is_ts4800()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TQMA9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TQMA9263
+# endif
+# define machine_is_tqma9263()	(machine_arch_type == MACH_TYPE_TQMA9263)
+#else
+# define machine_is_tqma9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HOLIDAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HOLIDAY
+# endif
+# define machine_is_holiday()	(machine_arch_type == MACH_TYPE_HOLIDAY)
+#else
+# define machine_is_holiday()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DMA6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DMA6410
+# endif
+# define machine_is_dma_6410()	(machine_arch_type == MACH_TYPE_DMA6410)
+#else
+# define machine_is_dma_6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCATS_OVERLAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCATS_OVERLAY
+# endif
+# define machine_is_pcats_overlay()	(machine_arch_type == MACH_TYPE_PCATS_OVERLAY)
+#else
+# define machine_is_pcats_overlay()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HWGW6410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HWGW6410
+# endif
+# define machine_is_hwgw6410()	(machine_arch_type == MACH_TYPE_HWGW6410)
+#else
+# define machine_is_hwgw6410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHENZHOU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHENZHOU
+# endif
+# define machine_is_shenzhou()	(machine_arch_type == MACH_TYPE_SHENZHOU)
+#else
+# define machine_is_shenzhou()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CWME9210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CWME9210
+# endif
+# define machine_is_cwme9210()	(machine_arch_type == MACH_TYPE_CWME9210)
+#else
+# define machine_is_cwme9210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CWME9210JS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CWME9210JS
+# endif
+# define machine_is_cwme9210js()	(machine_arch_type == MACH_TYPE_CWME9210JS)
+#else
+# define machine_is_cwme9210js()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PGS_SITARA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PGS_SITARA
+# endif
+# define machine_is_pgs_v1()	(machine_arch_type == MACH_TYPE_PGS_SITARA)
+#else
+# define machine_is_pgs_v1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COLIBRI_TEGRA2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COLIBRI_TEGRA2
+# endif
+# define machine_is_colibri_tegra2()	(machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2)
+#else
+# define machine_is_colibri_tegra2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_W21
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_W21
+# endif
+# define machine_is_w21()	(machine_arch_type == MACH_TYPE_W21)
+#else
+# define machine_is_w21()	(0)
+#endif
+
+#ifdef CONFIG_MACH_POLYSAT1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_POLYSAT1
+# endif
+# define machine_is_polysat1()	(machine_arch_type == MACH_TYPE_POLYSAT1)
+#else
+# define machine_is_polysat1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DATAWAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DATAWAY
+# endif
+# define machine_is_dataway()	(machine_arch_type == MACH_TYPE_DATAWAY)
+#else
+# define machine_is_dataway()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COBRAL138
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COBRAL138
+# endif
+# define machine_is_cobral138()	(machine_arch_type == MACH_TYPE_COBRAL138)
+#else
+# define machine_is_cobral138()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROVERPCS8
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROVERPCS8
+# endif
+# define machine_is_roverpcs8()	(machine_arch_type == MACH_TYPE_ROVERPCS8)
+#else
+# define machine_is_roverpcs8()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MARVELC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MARVELC
+# endif
+# define machine_is_marvelc()	(machine_arch_type == MACH_TYPE_MARVELC)
+#else
+# define machine_is_marvelc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NAVEFIHID
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NAVEFIHID
+# endif
+# define machine_is_navefihid()	(machine_arch_type == MACH_TYPE_NAVEFIHID)
+#else
+# define machine_is_navefihid()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DM365_CV100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM365_CV100
+# endif
+# define machine_is_dm365_cv100()	(machine_arch_type == MACH_TYPE_DM365_CV100)
+#else
+# define machine_is_dm365_cv100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ABLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ABLE
+# endif
+# define machine_is_able()	(machine_arch_type == MACH_TYPE_ABLE)
+#else
+# define machine_is_able()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LEGACY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LEGACY
+# endif
+# define machine_is_legacy()	(machine_arch_type == MACH_TYPE_LEGACY)
+#else
+# define machine_is_legacy()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ICONG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ICONG
+# endif
+# define machine_is_icong()	(machine_arch_type == MACH_TYPE_ICONG)
+#else
+# define machine_is_icong()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROVER_G8
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROVER_G8
+# endif
+# define machine_is_rover_g8()	(machine_arch_type == MACH_TYPE_ROVER_G8)
+#else
+# define machine_is_rover_g8()	(0)
+#endif
+
+#ifdef CONFIG_MACH_T5388P
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_T5388P
+# endif
+# define machine_is_t5388p()	(machine_arch_type == MACH_TYPE_T5388P)
+#else
+# define machine_is_t5388p()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DINGO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DINGO
+# endif
+# define machine_is_dingo()	(machine_arch_type == MACH_TYPE_DINGO)
+#else
+# define machine_is_dingo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GOFLEXHOME
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GOFLEXHOME
+# endif
+# define machine_is_goflexhome()	(machine_arch_type == MACH_TYPE_GOFLEXHOME)
+#else
+# define machine_is_goflexhome()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LANREADYFN511
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LANREADYFN511
+# endif
+# define machine_is_lanreadyfn511()	(machine_arch_type == MACH_TYPE_LANREADYFN511)
+#else
+# define machine_is_lanreadyfn511()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_BAIA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_BAIA
+# endif
+# define machine_is_omap3_baia()	(machine_arch_type == MACH_TYPE_OMAP3_BAIA)
+#else
+# define machine_is_omap3_baia()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3SMARTDISPLAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3SMARTDISPLAY
+# endif
+# define machine_is_omap3smartdisplay()	(machine_arch_type == MACH_TYPE_OMAP3SMARTDISPLAY)
+#else
+# define machine_is_omap3smartdisplay()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XILINX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XILINX
+# endif
+# define machine_is_xilinx()	(machine_arch_type == MACH_TYPE_XILINX)
+#else
+# define machine_is_xilinx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A2F
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A2F
+# endif
+# define machine_is_a2f()	(machine_arch_type == MACH_TYPE_A2F)
+#else
+# define machine_is_a2f()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SKY25
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SKY25
+# endif
+# define machine_is_sky25()	(machine_arch_type == MACH_TYPE_SKY25)
+#else
+# define machine_is_sky25()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CCMX53
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CCMX53
+# endif
+# define machine_is_ccmx53()	(machine_arch_type == MACH_TYPE_CCMX53)
+#else
+# define machine_is_ccmx53()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CCMX53JS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CCMX53JS
+# endif
+# define machine_is_ccmx53js()	(machine_arch_type == MACH_TYPE_CCMX53JS)
+#else
+# define machine_is_ccmx53js()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX53
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CCWMX53
+# endif
+# define machine_is_ccwmx53()	(machine_arch_type == MACH_TYPE_CCWMX53)
+#else
+# define machine_is_ccwmx53()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CCWMX53JS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CCWMX53JS
+# endif
+# define machine_is_ccwmx53js()	(machine_arch_type == MACH_TYPE_CCWMX53JS)
+#else
+# define machine_is_ccwmx53js()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FRISMS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FRISMS
+# endif
+# define machine_is_frisms()	(machine_arch_type == MACH_TYPE_FRISMS)
+#else
+# define machine_is_frisms()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X27A_FFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X27A_FFA
+# endif
+# define machine_is_msm7x27a_ffa()	(machine_arch_type == MACH_TYPE_MSM7X27A_FFA)
+#else
+# define machine_is_msm7x27a_ffa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X27A_SURF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X27A_SURF
+# endif
+# define machine_is_msm7x27a_surf()	(machine_arch_type == MACH_TYPE_MSM7X27A_SURF)
+#else
+# define machine_is_msm7x27a_surf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM7X27A_RUMI3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM7X27A_RUMI3
+# endif
+# define machine_is_msm7x27a_rumi3()	(machine_arch_type == MACH_TYPE_MSM7X27A_RUMI3)
+#else
+# define machine_is_msm7x27a_rumi3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DIMMSAM9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DIMMSAM9G20
+# endif
+# define machine_is_dimmsam9g20()	(machine_arch_type == MACH_TYPE_DIMMSAM9G20)
+#else
+# define machine_is_dimmsam9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DIMM_IMX28
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DIMM_IMX28
+# endif
+# define machine_is_dimm_imx28()	(machine_arch_type == MACH_TYPE_DIMM_IMX28)
+#else
+# define machine_is_dimm_imx28()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AMK_A4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AMK_A4
+# endif
+# define machine_is_amk_a4()	(machine_arch_type == MACH_TYPE_AMK_A4)
+#else
+# define machine_is_amk_a4()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GNET_SGME
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GNET_SGME
+# endif
+# define machine_is_gnet_sgme()	(machine_arch_type == MACH_TYPE_GNET_SGME)
+#else
+# define machine_is_gnet_sgme()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHOOTER_U
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHOOTER_U
+# endif
+# define machine_is_shooter_u()	(machine_arch_type == MACH_TYPE_SHOOTER_U)
+#else
+# define machine_is_shooter_u()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VMX53
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VMX53
+# endif
+# define machine_is_vmx53()	(machine_arch_type == MACH_TYPE_VMX53)
+#else
+# define machine_is_vmx53()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RHINO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RHINO
+# endif
+# define machine_is_rhino()	(machine_arch_type == MACH_TYPE_RHINO)
+#else
+# define machine_is_rhino()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMLEX4210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMLEX4210
+# endif
+# define machine_is_armlex4210()	(machine_arch_type == MACH_TYPE_ARMLEX4210)
+#else
+# define machine_is_armlex4210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SWARCOEXTMODEM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SWARCOEXTMODEM
+# endif
+# define machine_is_swarcoextmodem()	(machine_arch_type == MACH_TYPE_SWARCOEXTMODEM)
+#else
+# define machine_is_swarcoextmodem()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SNOWBALL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SNOWBALL
+# endif
+# define machine_is_snowball()	(machine_arch_type == MACH_TYPE_SNOWBALL)
+#else
+# define machine_is_snowball()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM049
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM049
+# endif
+# define machine_is_pcm049()	(machine_arch_type == MACH_TYPE_PCM049)
+#else
+# define machine_is_pcm049()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VIGOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VIGOR
+# endif
+# define machine_is_vigor()	(machine_arch_type == MACH_TYPE_VIGOR)
+#else
+# define machine_is_vigor()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OSLO_AMUNDSEN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OSLO_AMUNDSEN
+# endif
+# define machine_is_oslo_amundsen()	(machine_arch_type == MACH_TYPE_OSLO_AMUNDSEN)
+#else
+# define machine_is_oslo_amundsen()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GSL_DIAMOND
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GSL_DIAMOND
+# endif
+# define machine_is_gsl_diamond()	(machine_arch_type == MACH_TYPE_GSL_DIAMOND)
+#else
+# define machine_is_gsl_diamond()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CV2201
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CV2201
+# endif
+# define machine_is_cv2201()	(machine_arch_type == MACH_TYPE_CV2201)
+#else
+# define machine_is_cv2201()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CV2202
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CV2202
+# endif
+# define machine_is_cv2202()	(machine_arch_type == MACH_TYPE_CV2202)
+#else
+# define machine_is_cv2202()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CV2203
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CV2203
+# endif
+# define machine_is_cv2203()	(machine_arch_type == MACH_TYPE_CV2203)
+#else
+# define machine_is_cv2203()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VIT_IBOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VIT_IBOX
+# endif
+# define machine_is_vit_ibox()	(machine_arch_type == MACH_TYPE_VIT_IBOX)
+#else
+# define machine_is_vit_ibox()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DM6441_ESP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM6441_ESP
+# endif
+# define machine_is_dm6441_esp()	(machine_arch_type == MACH_TYPE_DM6441_ESP)
+#else
+# define machine_is_dm6441_esp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9X5EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9X5EK
+# endif
+# define machine_is_at91sam9x5ek()	(machine_arch_type == MACH_TYPE_AT91SAM9X5EK)
+#else
+# define machine_is_at91sam9x5ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LIBRA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LIBRA
+# endif
+# define machine_is_libra()	(machine_arch_type == MACH_TYPE_LIBRA)
+#else
+# define machine_is_libra()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EASYCRRH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EASYCRRH
+# endif
+# define machine_is_easycrrh()	(machine_arch_type == MACH_TYPE_EASYCRRH)
+#else
+# define machine_is_easycrrh()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRIPEL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRIPEL
+# endif
+# define machine_is_tripel()	(machine_arch_type == MACH_TYPE_TRIPEL)
+#else
+# define machine_is_tripel()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ENDIAN_MINI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ENDIAN_MINI
+# endif
+# define machine_is_endian_mini()	(machine_arch_type == MACH_TYPE_ENDIAN_MINI)
+#else
+# define machine_is_endian_mini()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XILINX_EP107
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XILINX_EP107
+# endif
+# define machine_is_xilinx_ep107()	(machine_arch_type == MACH_TYPE_XILINX_EP107)
+#else
+# define machine_is_xilinx_ep107()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NURI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NURI
+# endif
+# define machine_is_nuri()	(machine_arch_type == MACH_TYPE_NURI)
+#else
+# define machine_is_nuri()	(0)
+#endif
+
+#ifdef CONFIG_MACH_JANUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JANUS
+# endif
+# define machine_is_janus()	(machine_arch_type == MACH_TYPE_JANUS)
+#else
+# define machine_is_janus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DDNAS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DDNAS
+# endif
+# define machine_is_ddnas()	(machine_arch_type == MACH_TYPE_DDNAS)
+#else
+# define machine_is_ddnas()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TAG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAG
+# endif
+# define machine_is_tag()	(machine_arch_type == MACH_TYPE_TAG)
+#else
+# define machine_is_tag()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TAGW
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAGW
+# endif
+# define machine_is_tagw()	(machine_arch_type == MACH_TYPE_TAGW)
+#else
+# define machine_is_tagw()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NITROGEN_VM_IMX51
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NITROGEN_VM_IMX51
+# endif
+# define machine_is_nitrogen_vm_imx51()	(machine_arch_type == MACH_TYPE_NITROGEN_VM_IMX51)
+#else
+# define machine_is_nitrogen_vm_imx51()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VIPRINET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VIPRINET
+# endif
+# define machine_is_viprinet()	(machine_arch_type == MACH_TYPE_VIPRINET)
+#else
+# define machine_is_viprinet()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BOCKW
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BOCKW
+# endif
+# define machine_is_bockw()	(machine_arch_type == MACH_TYPE_BOCKW)
+#else
+# define machine_is_bockw()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EVA2000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EVA2000
+# endif
+# define machine_is_eva2000()	(machine_arch_type == MACH_TYPE_EVA2000)
+#else
+# define machine_is_eva2000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STEELYARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STEELYARD
+# endif
+# define machine_is_steelyard()	(machine_arch_type == MACH_TYPE_STEELYARD)
+#else
+# define machine_is_steelyard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MACH_SDH001
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MACH_SDH001
+# endif
+# define machine_is_sdh001()	(machine_arch_type == MACH_TYPE_MACH_SDH001)
+#else
+# define machine_is_sdh001()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NSSLSBOARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NSSLSBOARD
+# endif
+# define machine_is_nsslsboard()	(machine_arch_type == MACH_TYPE_NSSLSBOARD)
+#else
+# define machine_is_nsslsboard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GENEVA_B5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GENEVA_B5
+# endif
+# define machine_is_geneva_b5()	(machine_arch_type == MACH_TYPE_GENEVA_B5)
+#else
+# define machine_is_geneva_b5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPEAR1340
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEAR1340
+# endif
+# define machine_is_spear1340()	(machine_arch_type == MACH_TYPE_SPEAR1340)
+#else
+# define machine_is_spear1340()	(0)
+#endif
+
+#ifdef CONFIG_MACH_REXMAS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REXMAS
+# endif
+# define machine_is_rexmas()	(machine_arch_type == MACH_TYPE_REXMAS)
+#else
+# define machine_is_rexmas()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8960_CDP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8960_CDP
+# endif
+# define machine_is_msm8960_cdp()	(machine_arch_type == MACH_TYPE_MSM8960_CDP)
+#else
+# define machine_is_msm8960_cdp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8960_MDP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8960_MDP
+# endif
+# define machine_is_msm8960_mdp()	(machine_arch_type == MACH_TYPE_MSM8960_MDP)
+#else
+# define machine_is_msm8960_mdp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8960_FLUID
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8960_FLUID
+# endif
+# define machine_is_msm8960_fluid()	(machine_arch_type == MACH_TYPE_MSM8960_FLUID)
+#else
+# define machine_is_msm8960_fluid()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MSM8960_APQ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MSM8960_APQ
+# endif
+# define machine_is_msm8960_apq()	(machine_arch_type == MACH_TYPE_MSM8960_APQ)
+#else
+# define machine_is_msm8960_apq()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HELIOS_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HELIOS_V2
+# endif
+# define machine_is_helios_v2()	(machine_arch_type == MACH_TYPE_HELIOS_V2)
+#else
+# define machine_is_helios_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MIF10P
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MIF10P
+# endif
+# define machine_is_mif10p()	(machine_arch_type == MACH_TYPE_MIF10P)
+#else
+# define machine_is_mif10p()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IAM28
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IAM28
+# endif
+# define machine_is_iam28()	(machine_arch_type == MACH_TYPE_IAM28)
+#else
+# define machine_is_iam28()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PICASSO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PICASSO
+# endif
+# define machine_is_picasso()	(machine_arch_type == MACH_TYPE_PICASSO)
+#else
+# define machine_is_picasso()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MR301A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MR301A
+# endif
+# define machine_is_mr301a()	(machine_arch_type == MACH_TYPE_MR301A)
+#else
+# define machine_is_mr301a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOTLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOTLE
+# endif
+# define machine_is_notle()	(machine_arch_type == MACH_TYPE_NOTLE)
+#else
+# define machine_is_notle()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EELX2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EELX2
+# endif
+# define machine_is_eelx2()	(machine_arch_type == MACH_TYPE_EELX2)
+#else
+# define machine_is_eelx2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MOON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MOON
+# endif
+# define machine_is_moon()	(machine_arch_type == MACH_TYPE_MOON)
+#else
+# define machine_is_moon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RUBY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RUBY
+# endif
+# define machine_is_ruby()	(machine_arch_type == MACH_TYPE_RUBY)
+#else
+# define machine_is_ruby()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GOLDENGATE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GOLDENGATE
+# endif
+# define machine_is_goldengate()	(machine_arch_type == MACH_TYPE_GOLDENGATE)
+#else
+# define machine_is_goldengate()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CTBU_GEN2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CTBU_GEN2
+# endif
+# define machine_is_ctbu_gen2()	(machine_arch_type == MACH_TYPE_CTBU_GEN2)
+#else
+# define machine_is_ctbu_gen2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KMP_AM17_01
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KMP_AM17_01
+# endif
+# define machine_is_kmp_am17_01()	(machine_arch_type == MACH_TYPE_KMP_AM17_01)
+#else
+# define machine_is_kmp_am17_01()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WTPLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WTPLUG
+# endif
+# define machine_is_wtplug()	(machine_arch_type == MACH_TYPE_WTPLUG)
+#else
+# define machine_is_wtplug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX27SU2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX27SU2
+# endif
+# define machine_is_mx27su2()	(machine_arch_type == MACH_TYPE_MX27SU2)
+#else
+# define machine_is_mx27su2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NB31
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NB31
+# endif
+# define machine_is_nb31()	(machine_arch_type == MACH_TYPE_NB31)
+#else
+# define machine_is_nb31()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HJSDU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HJSDU
+# endif
+# define machine_is_hjsdu()	(machine_arch_type == MACH_TYPE_HJSDU)
+#else
+# define machine_is_hjsdu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TD3_REV1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TD3_REV1
+# endif
+# define machine_is_td3_rev1()	(machine_arch_type == MACH_TYPE_TD3_REV1)
+#else
+# define machine_is_td3_rev1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EAG_CI4000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EAG_CI4000
+# endif
+# define machine_is_eag_ci4000()	(machine_arch_type == MACH_TYPE_EAG_CI4000)
+#else
+# define machine_is_eag_ci4000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NET5BIG_NAND_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NET5BIG_NAND_V2
+# endif
+# define machine_is_net5big_nand_v2()	(machine_arch_type == MACH_TYPE_NET5BIG_NAND_V2)
+#else
+# define machine_is_net5big_nand_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPX2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPX2
+# endif
+# define machine_is_cpx2()	(machine_arch_type == MACH_TYPE_CPX2)
+#else
+# define machine_is_cpx2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NET2BIG_NAND_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NET2BIG_NAND_V2
+# endif
+# define machine_is_net2big_nand_v2()	(machine_arch_type == MACH_TYPE_NET2BIG_NAND_V2)
+#else
+# define machine_is_net2big_nand_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ECUV5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ECUV5
+# endif
+# define machine_is_ecuv5()	(machine_arch_type == MACH_TYPE_ECUV5)
+#else
+# define machine_is_ecuv5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HSGX6D
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HSGX6D
+# endif
+# define machine_is_hsgx6d()	(machine_arch_type == MACH_TYPE_HSGX6D)
+#else
+# define machine_is_hsgx6d()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAWAD7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAWAD7
+# endif
+# define machine_is_dawad7()	(machine_arch_type == MACH_TYPE_DAWAD7)
+#else
+# define machine_is_dawad7()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SAM9REPEATER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SAM9REPEATER
+# endif
+# define machine_is_sam9repeater()	(machine_arch_type == MACH_TYPE_SAM9REPEATER)
+#else
+# define machine_is_sam9repeater()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GT_I5700
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GT_I5700
+# endif
+# define machine_is_gt_i5700()	(machine_arch_type == MACH_TYPE_GT_I5700)
+#else
+# define machine_is_gt_i5700()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_PLUG_C2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CTERA_PLUG_C2
+# endif
+# define machine_is_ctera_plug_c2()	(machine_arch_type == MACH_TYPE_CTERA_PLUG_C2)
+#else
+# define machine_is_ctera_plug_c2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MARVELCT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MARVELCT
+# endif
+# define machine_is_marvelct()	(machine_arch_type == MACH_TYPE_MARVELCT)
+#else
+# define machine_is_marvelct()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AG11005
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AG11005
+# endif
+# define machine_is_ag11005()	(machine_arch_type == MACH_TYPE_AG11005)
+#else
+# define machine_is_ag11005()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VANGOGH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VANGOGH
+# endif
+# define machine_is_vangogh()	(machine_arch_type == MACH_TYPE_VANGOGH)
+#else
+# define machine_is_vangogh()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MATRIX505
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MATRIX505
+# endif
+# define machine_is_matrix505()	(machine_arch_type == MACH_TYPE_MATRIX505)
+#else
+# define machine_is_matrix505()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OCE_NIGMA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OCE_NIGMA
+# endif
+# define machine_is_oce_nigma()	(machine_arch_type == MACH_TYPE_OCE_NIGMA)
+#else
+# define machine_is_oce_nigma()	(0)
+#endif
+
+#ifdef CONFIG_MACH_T55
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_T55
+# endif
+# define machine_is_t55()	(machine_arch_type == MACH_TYPE_T55)
+#else
+# define machine_is_t55()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BIO3K
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BIO3K
+# endif
+# define machine_is_bio3k()	(machine_arch_type == MACH_TYPE_BIO3K)
+#else
+# define machine_is_bio3k()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EXPRESSCT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EXPRESSCT
+# endif
+# define machine_is_expressct()	(machine_arch_type == MACH_TYPE_EXPRESSCT)
+#else
+# define machine_is_expressct()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CARDHU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CARDHU
+# endif
+# define machine_is_cardhu()	(machine_arch_type == MACH_TYPE_CARDHU)
+#else
+# define machine_is_cardhu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARUBA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARUBA
+# endif
+# define machine_is_aruba()	(machine_arch_type == MACH_TYPE_ARUBA)
+#else
+# define machine_is_aruba()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BONAIRE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BONAIRE
+# endif
+# define machine_is_bonaire()	(machine_arch_type == MACH_TYPE_BONAIRE)
+#else
+# define machine_is_bonaire()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC700EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC700EVB
+# endif
+# define machine_is_nuc700evb()	(machine_arch_type == MACH_TYPE_NUC700EVB)
+#else
+# define machine_is_nuc700evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC710EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC710EVB
+# endif
+# define machine_is_nuc710evb()	(machine_arch_type == MACH_TYPE_NUC710EVB)
+#else
+# define machine_is_nuc710evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC740EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC740EVB
+# endif
+# define machine_is_nuc740evb()	(machine_arch_type == MACH_TYPE_NUC740EVB)
+#else
+# define machine_is_nuc740evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC745EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC745EVB
+# endif
+# define machine_is_nuc745evb()	(machine_arch_type == MACH_TYPE_NUC745EVB)
+#else
+# define machine_is_nuc745evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRANSCEDE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRANSCEDE
+# endif
+# define machine_is_transcede()	(machine_arch_type == MACH_TYPE_TRANSCEDE)
+#else
+# define machine_is_transcede()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MORA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MORA
+# endif
+# define machine_is_mora()	(machine_arch_type == MACH_TYPE_MORA)
+#else
+# define machine_is_mora()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NDA_EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NDA_EVM
+# endif
+# define machine_is_nda_evm()	(machine_arch_type == MACH_TYPE_NDA_EVM)
+#else
+# define machine_is_nda_evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TIMU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TIMU
+# endif
+# define machine_is_timu()	(machine_arch_type == MACH_TYPE_TIMU)
+#else
+# define machine_is_timu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EXPRESSH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EXPRESSH
+# endif
+# define machine_is_expressh()	(machine_arch_type == MACH_TYPE_EXPRESSH)
+#else
+# define machine_is_expressh()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VERIDIS_A300
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VERIDIS_A300
+# endif
+# define machine_is_veridis_a300()	(machine_arch_type == MACH_TYPE_VERIDIS_A300)
+#else
+# define machine_is_veridis_a300()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DM368_LEOPARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM368_LEOPARD
+# endif
+# define machine_is_dm368_leopard()	(machine_arch_type == MACH_TYPE_DM368_LEOPARD)
+#else
+# define machine_is_dm368_leopard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_MCOP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_MCOP
+# endif
+# define machine_is_omap_mcop()	(machine_arch_type == MACH_TYPE_OMAP_MCOP)
+#else
+# define machine_is_omap_mcop()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRITIP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRITIP
+# endif
+# define machine_is_tritip()	(machine_arch_type == MACH_TYPE_TRITIP)
+#else
+# define machine_is_tritip()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SM1K
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SM1K
+# endif
+# define machine_is_sm1k()	(machine_arch_type == MACH_TYPE_SM1K)
+#else
+# define machine_is_sm1k()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MONCH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MONCH
+# endif
+# define machine_is_monch()	(machine_arch_type == MACH_TYPE_MONCH)
+#else
+# define machine_is_monch()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CURACAO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CURACAO
+# endif
+# define machine_is_curacao()	(machine_arch_type == MACH_TYPE_CURACAO)
+#else
+# define machine_is_curacao()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ORIGEN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORIGEN
+# endif
+# define machine_is_origen()	(machine_arch_type == MACH_TYPE_ORIGEN)
+#else
+# define machine_is_origen()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EPC10
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EPC10
+# endif
+# define machine_is_epc10()	(machine_arch_type == MACH_TYPE_EPC10)
+#else
+# define machine_is_epc10()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SGH_I740
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SGH_I740
+# endif
+# define machine_is_sgh_i740()	(machine_arch_type == MACH_TYPE_SGH_I740)
+#else
+# define machine_is_sgh_i740()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TUNA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TUNA
+# endif
+# define machine_is_tuna()	(machine_arch_type == MACH_TYPE_TUNA)
+#else
+# define machine_is_tuna()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_TULIP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_TULIP
+# endif
+# define machine_is_mx51_tulip()	(machine_arch_type == MACH_TYPE_MX51_TULIP)
+#else
+# define machine_is_mx51_tulip()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_ASTER7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_ASTER7
+# endif
+# define machine_is_mx51_aster7()	(machine_arch_type == MACH_TYPE_MX51_ASTER7)
+#else
+# define machine_is_mx51_aster7()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACRO37XBRD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACRO37XBRD
+# endif
+# define machine_is_acro37xbrd()	(machine_arch_type == MACH_TYPE_ACRO37XBRD)
+#else
+# define machine_is_acro37xbrd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ELKE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ELKE
+# endif
+# define machine_is_elke()	(machine_arch_type == MACH_TYPE_ELKE)
+#else
+# define machine_is_elke()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SBC6000X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SBC6000X
+# endif
+# define machine_is_sbc6000x()	(machine_arch_type == MACH_TYPE_SBC6000X)
+#else
+# define machine_is_sbc6000x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_R1801E
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_R1801E
+# endif
+# define machine_is_r1801e()	(machine_arch_type == MACH_TYPE_R1801E)
+#else
+# define machine_is_r1801e()	(0)
+#endif
+
+#ifdef CONFIG_MACH_H1600
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H1600
+# endif
+# define machine_is_h1600()	(machine_arch_type == MACH_TYPE_H1600)
+#else
+# define machine_is_h1600()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MINI210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MINI210
+# endif
+# define machine_is_mini210()	(machine_arch_type == MACH_TYPE_MINI210)
+#else
+# define machine_is_mini210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MINI8168
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MINI8168
+# endif
+# define machine_is_mini8168()	(machine_arch_type == MACH_TYPE_MINI8168)
+#else
+# define machine_is_mini8168()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PC7308
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PC7308
+# endif
+# define machine_is_pc7308()	(machine_arch_type == MACH_TYPE_PC7308)
+#else
+# define machine_is_pc7308()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KMM2M01
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KMM2M01
+# endif
+# define machine_is_kmm2m01()	(machine_arch_type == MACH_TYPE_KMM2M01)
+#else
+# define machine_is_kmm2m01()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51EREBUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51EREBUS
+# endif
+# define machine_is_mx51erebus()	(machine_arch_type == MACH_TYPE_MX51EREBUS)
+#else
+# define machine_is_mx51erebus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WM8650REFBOARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WM8650REFBOARD
+# endif
+# define machine_is_wm8650refboard()	(machine_arch_type == MACH_TYPE_WM8650REFBOARD)
+#else
+# define machine_is_wm8650refboard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TUXRAIL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TUXRAIL
+# endif
+# define machine_is_tuxrail()	(machine_arch_type == MACH_TYPE_TUXRAIL)
+#else
+# define machine_is_tuxrail()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARTHUR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARTHUR
+# endif
+# define machine_is_arthur()	(machine_arch_type == MACH_TYPE_ARTHUR)
+#else
+# define machine_is_arthur()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DOORBOY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DOORBOY
+# endif
+# define machine_is_doorboy()	(machine_arch_type == MACH_TYPE_DOORBOY)
+#else
+# define machine_is_doorboy()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XARINA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XARINA
+# endif
+# define machine_is_xarina()	(machine_arch_type == MACH_TYPE_XARINA)
+#else
+# define machine_is_xarina()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROVERX7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROVERX7
+# endif
+# define machine_is_roverx7()	(machine_arch_type == MACH_TYPE_ROVERX7)
+#else
+# define machine_is_roverx7()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SDVR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SDVR
+# endif
+# define machine_is_sdvr()	(machine_arch_type == MACH_TYPE_SDVR)
+#else
+# define machine_is_sdvr()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_MAYA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACER_MAYA
+# endif
+# define machine_is_acer_maya()	(machine_arch_type == MACH_TYPE_ACER_MAYA)
+#else
+# define machine_is_acer_maya()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PICO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PICO
+# endif
+# define machine_is_pico()	(machine_arch_type == MACH_TYPE_PICO)
+#else
+# define machine_is_pico()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CWMX233
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CWMX233
+# endif
+# define machine_is_cwmx233()	(machine_arch_type == MACH_TYPE_CWMX233)
+#else
+# define machine_is_cwmx233()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CWAM1808
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CWAM1808
+# endif
+# define machine_is_cwam1808()	(machine_arch_type == MACH_TYPE_CWAM1808)
+#else
+# define machine_is_cwam1808()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CWDM365
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CWDM365
+# endif
+# define machine_is_cwdm365()	(machine_arch_type == MACH_TYPE_CWDM365)
+#else
+# define machine_is_cwdm365()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_MORAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_MORAY
+# endif
+# define machine_is_mx51_moray()	(machine_arch_type == MACH_TYPE_MX51_MORAY)
+#else
+# define machine_is_mx51_moray()	(0)
+#endif
+
+#ifdef CONFIG_MACH_THALES_CBC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_THALES_CBC
+# endif
+# define machine_is_thales_cbc()	(machine_arch_type == MACH_TYPE_THALES_CBC)
+#else
+# define machine_is_thales_cbc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BLUEPOINT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLUEPOINT
+# endif
+# define machine_is_bluepoint()	(machine_arch_type == MACH_TYPE_BLUEPOINT)
+#else
+# define machine_is_bluepoint()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DIR665
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DIR665
+# endif
+# define machine_is_dir665()	(machine_arch_type == MACH_TYPE_DIR665)
+#else
+# define machine_is_dir665()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACMEROVER1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACMEROVER1
+# endif
+# define machine_is_acmerover1()	(machine_arch_type == MACH_TYPE_ACMEROVER1)
+#else
+# define machine_is_acmerover1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHOOTER_CT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHOOTER_CT
+# endif
+# define machine_is_shooter_ct()	(machine_arch_type == MACH_TYPE_SHOOTER_CT)
+#else
+# define machine_is_shooter_ct()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BLISS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLISS
+# endif
+# define machine_is_bliss()	(machine_arch_type == MACH_TYPE_BLISS)
+#else
+# define machine_is_bliss()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BLISSC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLISSC
+# endif
+# define machine_is_blissc()	(machine_arch_type == MACH_TYPE_BLISSC)
+#else
+# define machine_is_blissc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_THALES_ADC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_THALES_ADC
+# endif
+# define machine_is_thales_adc()	(machine_arch_type == MACH_TYPE_THALES_ADC)
+#else
+# define machine_is_thales_adc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UBISYS_P9D_EVP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UBISYS_P9D_EVP
+# endif
+# define machine_is_ubisys_p9d_evp()	(machine_arch_type == MACH_TYPE_UBISYS_P9D_EVP)
+#else
+# define machine_is_ubisys_p9d_evp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ATDGP318
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ATDGP318
+# endif
+# define machine_is_atdgp318()	(machine_arch_type == MACH_TYPE_ATDGP318)
+#else
+# define machine_is_atdgp318()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP5_SEVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type     __machine_arch_type
+# else
+#  define machine_arch_type     MACH_TYPE_OMAP5_SEVM
+# endif
+# define machine_is_omap5_sevm()      (machine_arch_type == MACH_TYPE_OMAP5_SEVM)
+#else
+# define machine_is_omap5_sevm()      (0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADILLO800EVA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type __machine_arch_type
+# else
+#  define machine_arch_type MACH_TYPE_ARMADILLO800EVA
+# endif
+# define machine_is_armadillo800eva()	(machine_arch_type == MACH_TYPE_ARMADILLO800EVA)
+#else
+# define machine_is_armadillo800eva()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KZM9G
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type __machine_arch_type
+# else
+#  define machine_arch_type MACH_TYPE_KZM9G
+# endif
+# define machine_is_kzm9g()	(machine_arch_type == MACH_TYPE_KZM9G)
+#else
+# define machine_is_kzm9g()	(0)
+#endif
+
+/*
+ * These have not yet been registered
+ */
+
+#ifndef machine_arch_type
+#define machine_arch_type	__machine_arch_type
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/macro.h b/qemu/roms/u-boot/arch/arm/include/asm/macro.h
new file mode 100644
index 000000000..f77e4b880
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/macro.h
@@ -0,0 +1,111 @@
+/*
+ * include/asm-arm/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_MACRO_H__
+#define __ASM_ARM_MACRO_H__
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to any address.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any ARM architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	ldr	r4, =\addr
+	ldr	r5, =\data
+	str	r5, [r4]
+.endm
+
+.macro	write16, addr, data
+	ldr	r4, =\addr
+	ldrh	r5, =\data
+	strh	r5, [r4]
+.endm
+
+.macro	write8, addr, data
+	ldr	r4, =\addr
+	ldrb	r5, =\data
+	strb	r5, [r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any ARM architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	ldr	r4, =\time
+1:
+	nop
+	subs	r4, r4, #1
+	bcs	1b
+.endm
+
+#ifdef CONFIG_ARM64
+/*
+ * Register aliases.
+ */
+lr	.req	x30
+
+/*
+ * Branch according to exception level
+ */
+.macro	switch_el, xreg, el3_label, el2_label, el1_label
+	mrs	\xreg, CurrentEL
+	cmp	\xreg, 0xc
+	b.eq	\el3_label
+	cmp	\xreg, 0x8
+	b.eq	\el2_label
+	cmp	\xreg, 0x4
+	b.eq	\el1_label
+.endm
+
+/*
+ * Branch if current processor is a slave,
+ * choose processor with all zero affinity value as the master.
+ */
+.macro	branch_if_slave, xreg, slave_label
+	mrs	\xreg, mpidr_el1
+	tst	\xreg, #0xff		/* Test Affinity 0 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #8
+	tst	\xreg, #0xff		/* Test Affinity 1 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #8
+	tst	\xreg, #0xff		/* Test Affinity 2 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #16
+	tst	\xreg, #0xff		/* Test Affinity 3 */
+	b.ne	\slave_label
+.endm
+
+/*
+ * Branch if current processor is a master,
+ * choose processor with all zero affinity value as the master.
+ */
+.macro	branch_if_master, xreg1, xreg2, master_label
+	mrs	\xreg1, mpidr_el1
+	lsr	\xreg2, \xreg1, #32
+	lsl	\xreg1, \xreg1, #40
+	lsr	\xreg1, \xreg1, #40
+	orr	\xreg1, \xreg1, \xreg2
+	cbz	\xreg1, \master_label
+.endm
+
+#endif /* CONFIG_ARM64 */
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H__ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/memory.h b/qemu/roms/u-boot/arch/arm/include/asm/memory.h
new file mode 100644
index 000000000..1864ab9fb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/memory.h
@@ -0,0 +1,136 @@
+/*
+ *  linux/include/asm-arm/memory.h
+ *
+ *  Copyright (C) 2000-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Note: this file should not be included by non-asm/.h files
+ */
+#ifndef __ASM_ARM_MEMORY_H
+#define __ASM_ARM_MEMORY_H
+
+#if 0	/* XXX###XXX */
+
+#include <asm/arch/memory.h>
+
+/*
+ * PFNs are used to describe any physical page; this means
+ * PFN 0 == physical address 0.
+ *
+ * This is the PFN of the first RAM page in the kernel
+ * direct-mapped view.  We assume this is the first page
+ * of RAM in the mem_map as well.
+ */
+#define PHYS_PFN_OFFSET	(PHYS_OFFSET >> PAGE_SHIFT)
+
+/*
+ * These are *only* valid on the kernel direct mapped RAM memory.
+ */
+static inline unsigned long virt_to_phys(void *x)
+{
+	return __virt_to_phys((unsigned long)(x));
+}
+
+static inline void *phys_to_virt(unsigned long x)
+{
+	return (void *)(__phys_to_virt((unsigned long)(x)));
+}
+
+#define __pa(x)			__virt_to_phys((unsigned long)(x))
+#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
+
+/*
+ * Virtual <-> DMA view memory address translations
+ * Again, these are *only* valid on the kernel direct mapped RAM
+ * memory.  Use of these is *depreciated*.
+ */
+#define virt_to_bus(x)		(__virt_to_bus((unsigned long)(x)))
+#define bus_to_virt(x)		((void *)(__bus_to_virt((unsigned long)(x))))
+
+/*
+ * Conversion between a struct page and a physical address.
+ *
+ * Note: when converting an unknown physical address to a
+ * struct page, the resulting pointer must be validated
+ * using VALID_PAGE().  It must return an invalid struct page
+ * for any physical address not corresponding to a system
+ * RAM address.
+ *
+ *  page_to_pfn(page)	convert a struct page * to a PFN number
+ *  pfn_to_page(pfn)	convert a _valid_ PFN number to struct page *
+ *  pfn_valid(pfn)	indicates whether a PFN number is valid
+ *
+ *  virt_to_page(k)	convert a _valid_ virtual address to struct page *
+ *  virt_addr_valid(k)	indicates whether a virtual address is valid
+ */
+#ifndef CONFIG_DISCONTIGMEM
+
+#define page_to_pfn(page)	(((page) - mem_map) + PHYS_PFN_OFFSET)
+#define pfn_to_page(pfn)	((mem_map + (pfn)) - PHYS_PFN_OFFSET)
+#define pfn_valid(pfn)		((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
+
+#define virt_to_page(kaddr)	(pfn_to_page(__pa(kaddr) >> PAGE_SHIFT))
+#define virt_addr_valid(kaddr)	((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory)
+
+#define PHYS_TO_NID(addr)	(0)
+
+#define VALID_PAGE(page)	((page - mem_map) < max_mapnr)
+
+#else
+
+/*
+ * This is more complex.  We have a set of mem_map arrays spread
+ * around in memory.
+ */
+#define page_to_pfn(page)					\
+	(((page) - page_zone(page)->zone_mem_map)		\
+	  + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT))
+
+#define pfn_to_page(pfn)					\
+	(PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT))
+
+#define pfn_valid(pfn)						\
+  ({								\
+	unsigned int node = PFN_TO_NID(pfn);			\
+	struct pglist_data *nd = NODE_DATA(node);		\
+	((node < NR_NODES) &&					\
+	 ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\
+   })
+
+#define virt_to_page(kaddr)					\
+	(ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
+
+#define virt_addr_valid(kaddr)	(KVADDR_TO_NID(kaddr) < NR_NODES)
+
+/*
+ * Common discontigmem stuff.
+ *  PHYS_TO_NID is used by the ARM kernel/setup.c
+ */
+#define PHYS_TO_NID(addr)	PFN_TO_NID((addr) >> PAGE_SHIFT)
+
+/*
+ * 2.4 compatibility
+ *
+ * VALID_PAGE returns a non-zero value if given page pointer is valid.
+ * This assumes all node's mem_maps are stored within the node they
+ * refer to.  This is actually inherently buggy.
+ */
+#define VALID_PAGE(page) \
+({ unsigned int node = KVADDR_TO_NID(page); \
+   ((node < NR_NODES) && \
+     ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \
+})
+
+#endif
+
+/*
+ * We should really eliminate virt_to_bus() here - it's depreciated.
+ */
+#define page_to_bus(page)	(virt_to_bus(page_address(page)))
+
+#endif	/* XXX###XXX */
+
+#endif	/* __ASM_ARM_MEMORY_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/omap_boot.h b/qemu/roms/u-boot/arch/arm/include/asm/omap_boot.h
new file mode 100644
index 000000000..f77f9d6b7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/omap_boot.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK	0xFF
+#define BOOT_DEVICE_OFFSET	0x8
+#define DEV_DESC_PTR_OFFSET	0x4
+#define DEV_DATA_PTR_OFFSET	0x18
+#define BOOT_MODE_OFFSET	0x8
+#define RESET_REASON_OFFSET	0x9
+#define CH_FLAGS_OFFSET		0xA
+
+#define CH_FLAGS_CHSETTINGS	(0x1 << 0)
+#define CH_FLAGS_CHRAM		(0x1 << 1)
+#define CH_FLAGS_CHFLASH	(0x1 << 2)
+#define CH_FLAGS_CHMMCSD	(0x1 << 3)
+
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+	char *boot_message;
+	unsigned int mem_boot_descriptor;
+	unsigned char omap_bootdevice;
+	unsigned char reset_reason;
+	unsigned char ch_flags;
+	unsigned long omap_bootmode;
+};
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/omap_common.h b/qemu/roms/u-boot/arch/arm/include/asm/omap_common.h
new file mode 100644
index 000000000..729723afe
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/omap_common.h
@@ -0,0 +1,663 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_OMAP_COMMON_H_
+#define	_OMAP_COMMON_H_
+
+#ifndef __ASSEMBLY__
+
+#include <common.h>
+
+#define NUM_SYS_CLKS	7
+
+struct prcm_regs {
+	/* cm1.ckgen */
+	u32 cm_clksel_core;
+	u32 cm_clksel_abe;
+	u32 cm_dll_ctrl;
+	u32 cm_clkmode_dpll_core;
+	u32 cm_idlest_dpll_core;
+	u32 cm_autoidle_dpll_core;
+	u32 cm_clksel_dpll_core;
+	u32 cm_div_m2_dpll_core;
+	u32 cm_div_m3_dpll_core;
+	u32 cm_div_h11_dpll_core;
+	u32 cm_div_h12_dpll_core;
+	u32 cm_div_h13_dpll_core;
+	u32 cm_div_h14_dpll_core;
+	u32 cm_div_h21_dpll_core;
+	u32 cm_div_h24_dpll_core;
+	u32 cm_ssc_deltamstep_dpll_core;
+	u32 cm_ssc_modfreqdiv_dpll_core;
+	u32 cm_emu_override_dpll_core;
+	u32 cm_div_h22_dpllcore;
+	u32 cm_div_h23_dpll_core;
+	u32 cm_clkmode_dpll_mpu;
+	u32 cm_idlest_dpll_mpu;
+	u32 cm_autoidle_dpll_mpu;
+	u32 cm_clksel_dpll_mpu;
+	u32 cm_div_m2_dpll_mpu;
+	u32 cm_ssc_deltamstep_dpll_mpu;
+	u32 cm_ssc_modfreqdiv_dpll_mpu;
+	u32 cm_bypclk_dpll_mpu;
+	u32 cm_clkmode_dpll_iva;
+	u32 cm_idlest_dpll_iva;
+	u32 cm_autoidle_dpll_iva;
+	u32 cm_clksel_dpll_iva;
+	u32 cm_div_h11_dpll_iva;
+	u32 cm_div_h12_dpll_iva;
+	u32 cm_ssc_deltamstep_dpll_iva;
+	u32 cm_ssc_modfreqdiv_dpll_iva;
+	u32 cm_bypclk_dpll_iva;
+	u32 cm_clkmode_dpll_abe;
+	u32 cm_idlest_dpll_abe;
+	u32 cm_autoidle_dpll_abe;
+	u32 cm_clksel_dpll_abe;
+	u32 cm_div_m2_dpll_abe;
+	u32 cm_div_m3_dpll_abe;
+	u32 cm_ssc_deltamstep_dpll_abe;
+	u32 cm_ssc_modfreqdiv_dpll_abe;
+	u32 cm_clkmode_dpll_ddrphy;
+	u32 cm_idlest_dpll_ddrphy;
+	u32 cm_autoidle_dpll_ddrphy;
+	u32 cm_clksel_dpll_ddrphy;
+	u32 cm_div_m2_dpll_ddrphy;
+	u32 cm_div_h11_dpll_ddrphy;
+	u32 cm_div_h12_dpll_ddrphy;
+	u32 cm_div_h13_dpll_ddrphy;
+	u32 cm_ssc_deltamstep_dpll_ddrphy;
+	u32 cm_clkmode_dpll_dsp;
+	u32 cm_shadow_freq_config1;
+	u32 cm_clkmode_dpll_gmac;
+	u32 cm_mpu_mpu_clkctrl;
+
+	/* cm1.dsp */
+	u32 cm_dsp_clkstctrl;
+	u32 cm_dsp_dsp_clkctrl;
+
+	/* cm1.abe */
+	u32 cm1_abe_clkstctrl;
+	u32 cm1_abe_l4abe_clkctrl;
+	u32 cm1_abe_aess_clkctrl;
+	u32 cm1_abe_pdm_clkctrl;
+	u32 cm1_abe_dmic_clkctrl;
+	u32 cm1_abe_mcasp_clkctrl;
+	u32 cm1_abe_mcbsp1_clkctrl;
+	u32 cm1_abe_mcbsp2_clkctrl;
+	u32 cm1_abe_mcbsp3_clkctrl;
+	u32 cm1_abe_slimbus_clkctrl;
+	u32 cm1_abe_timer5_clkctrl;
+	u32 cm1_abe_timer6_clkctrl;
+	u32 cm1_abe_timer7_clkctrl;
+	u32 cm1_abe_timer8_clkctrl;
+	u32 cm1_abe_wdt3_clkctrl;
+
+	/* cm2.ckgen */
+	u32 cm_clksel_mpu_m3_iss_root;
+	u32 cm_clksel_usb_60mhz;
+	u32 cm_scale_fclk;
+	u32 cm_core_dvfs_perf1;
+	u32 cm_core_dvfs_perf2;
+	u32 cm_core_dvfs_perf3;
+	u32 cm_core_dvfs_perf4;
+	u32 cm_core_dvfs_current;
+	u32 cm_iva_dvfs_perf_tesla;
+	u32 cm_iva_dvfs_perf_ivahd;
+	u32 cm_iva_dvfs_perf_abe;
+	u32 cm_iva_dvfs_current;
+	u32 cm_clkmode_dpll_per;
+	u32 cm_idlest_dpll_per;
+	u32 cm_autoidle_dpll_per;
+	u32 cm_clksel_dpll_per;
+	u32 cm_div_m2_dpll_per;
+	u32 cm_div_m3_dpll_per;
+	u32 cm_div_h11_dpll_per;
+	u32 cm_div_h12_dpll_per;
+	u32 cm_div_h13_dpll_per;
+	u32 cm_div_h14_dpll_per;
+	u32 cm_ssc_deltamstep_dpll_per;
+	u32 cm_ssc_modfreqdiv_dpll_per;
+	u32 cm_emu_override_dpll_per;
+	u32 cm_clkmode_dpll_usb;
+	u32 cm_idlest_dpll_usb;
+	u32 cm_autoidle_dpll_usb;
+	u32 cm_clksel_dpll_usb;
+	u32 cm_div_m2_dpll_usb;
+	u32 cm_ssc_deltamstep_dpll_usb;
+	u32 cm_ssc_modfreqdiv_dpll_usb;
+	u32 cm_clkdcoldo_dpll_usb;
+	u32 cm_clkmode_dpll_pcie_ref;
+	u32 cm_clkmode_apll_pcie;
+	u32 cm_idlest_apll_pcie;
+	u32 cm_div_m2_apll_pcie;
+	u32 cm_clkvcoldo_apll_pcie;
+	u32 cm_clkmode_dpll_unipro;
+	u32 cm_idlest_dpll_unipro;
+	u32 cm_autoidle_dpll_unipro;
+	u32 cm_clksel_dpll_unipro;
+	u32 cm_div_m2_dpll_unipro;
+	u32 cm_ssc_deltamstep_dpll_unipro;
+	u32 cm_ssc_modfreqdiv_dpll_unipro;
+	u32 cm_coreaon_usb_phy_core_clkctrl;
+	u32 cm_coreaon_usb_phy2_core_clkctrl;
+
+	/* cm2.core */
+	u32 cm_coreaon_bandgap_clkctrl;
+	u32 cm_coreaon_io_srcomp_clkctrl;
+	u32 cm_l3_1_clkstctrl;
+	u32 cm_l3_1_dynamicdep;
+	u32 cm_l3_1_l3_1_clkctrl;
+	u32 cm_l3_2_clkstctrl;
+	u32 cm_l3_2_dynamicdep;
+	u32 cm_l3_2_l3_2_clkctrl;
+	u32 cm_l3_gpmc_clkctrl;
+	u32 cm_l3_2_ocmc_ram_clkctrl;
+	u32 cm_mpu_m3_clkstctrl;
+	u32 cm_mpu_m3_staticdep;
+	u32 cm_mpu_m3_dynamicdep;
+	u32 cm_mpu_m3_mpu_m3_clkctrl;
+	u32 cm_sdma_clkstctrl;
+	u32 cm_sdma_staticdep;
+	u32 cm_sdma_dynamicdep;
+	u32 cm_sdma_sdma_clkctrl;
+	u32 cm_memif_clkstctrl;
+	u32 cm_memif_dmm_clkctrl;
+	u32 cm_memif_emif_fw_clkctrl;
+	u32 cm_memif_emif_1_clkctrl;
+	u32 cm_memif_emif_2_clkctrl;
+	u32 cm_memif_dll_clkctrl;
+	u32 cm_memif_emif_h1_clkctrl;
+	u32 cm_memif_emif_h2_clkctrl;
+	u32 cm_memif_dll_h_clkctrl;
+	u32 cm_c2c_clkstctrl;
+	u32 cm_c2c_staticdep;
+	u32 cm_c2c_dynamicdep;
+	u32 cm_c2c_sad2d_clkctrl;
+	u32 cm_c2c_modem_icr_clkctrl;
+	u32 cm_c2c_sad2d_fw_clkctrl;
+	u32 cm_l4cfg_clkstctrl;
+	u32 cm_l4cfg_dynamicdep;
+	u32 cm_l4cfg_l4_cfg_clkctrl;
+	u32 cm_l4cfg_hw_sem_clkctrl;
+	u32 cm_l4cfg_mailbox_clkctrl;
+	u32 cm_l4cfg_sar_rom_clkctrl;
+	u32 cm_l3instr_clkstctrl;
+	u32 cm_l3instr_l3_3_clkctrl;
+	u32 cm_l3instr_l3_instr_clkctrl;
+	u32 cm_l3instr_intrconn_wp1_clkctrl;
+
+	/* cm2.ivahd */
+	u32 cm_ivahd_clkstctrl;
+	u32 cm_ivahd_ivahd_clkctrl;
+	u32 cm_ivahd_sl2_clkctrl;
+
+	/* cm2.cam */
+	u32 cm_cam_clkstctrl;
+	u32 cm_cam_iss_clkctrl;
+	u32 cm_cam_fdif_clkctrl;
+	u32 cm_cam_vip1_clkctrl;
+	u32 cm_cam_vip2_clkctrl;
+	u32 cm_cam_vip3_clkctrl;
+	u32 cm_cam_lvdsrx_clkctrl;
+	u32 cm_cam_csi1_clkctrl;
+	u32 cm_cam_csi2_clkctrl;
+
+	/* cm2.dss */
+	u32 cm_dss_clkstctrl;
+	u32 cm_dss_dss_clkctrl;
+
+	/* cm2.sgx */
+	u32 cm_sgx_clkstctrl;
+	u32 cm_sgx_sgx_clkctrl;
+
+	/* cm2.l3init */
+	u32 cm_l3init_clkstctrl;
+
+	/* cm2.l3init */
+	u32 cm_l3init_hsmmc1_clkctrl;
+	u32 cm_l3init_hsmmc2_clkctrl;
+	u32 cm_l3init_hsi_clkctrl;
+	u32 cm_l3init_hsusbhost_clkctrl;
+	u32 cm_l3init_hsusbotg_clkctrl;
+	u32 cm_l3init_hsusbtll_clkctrl;
+	u32 cm_l3init_p1500_clkctrl;
+	u32 cm_l3init_sata_clkctrl;
+	u32 cm_l3init_fsusb_clkctrl;
+	u32 cm_l3init_ocp2scp1_clkctrl;
+	u32 cm_l3init_ocp2scp3_clkctrl;
+	u32 cm_l3init_usb_otg_ss_clkctrl;
+
+	u32 prm_irqstatus_mpu_2;
+
+	/* cm2.l4per */
+	u32 cm_l4per_clkstctrl;
+	u32 cm_l4per_dynamicdep;
+	u32 cm_l4per_adc_clkctrl;
+	u32 cm_l4per_gptimer10_clkctrl;
+	u32 cm_l4per_gptimer11_clkctrl;
+	u32 cm_l4per_gptimer2_clkctrl;
+	u32 cm_l4per_gptimer3_clkctrl;
+	u32 cm_l4per_gptimer4_clkctrl;
+	u32 cm_l4per_gptimer9_clkctrl;
+	u32 cm_l4per_elm_clkctrl;
+	u32 cm_l4per_gpio2_clkctrl;
+	u32 cm_l4per_gpio3_clkctrl;
+	u32 cm_l4per_gpio4_clkctrl;
+	u32 cm_l4per_gpio5_clkctrl;
+	u32 cm_l4per_gpio6_clkctrl;
+	u32 cm_l4per_hdq1w_clkctrl;
+	u32 cm_l4per_hecc1_clkctrl;
+	u32 cm_l4per_hecc2_clkctrl;
+	u32 cm_l4per_i2c1_clkctrl;
+	u32 cm_l4per_i2c2_clkctrl;
+	u32 cm_l4per_i2c3_clkctrl;
+	u32 cm_l4per_i2c4_clkctrl;
+	u32 cm_l4per_l4per_clkctrl;
+	u32 cm_l4per_mcasp2_clkctrl;
+	u32 cm_l4per_mcasp3_clkctrl;
+	u32 cm_l4per_mgate_clkctrl;
+	u32 cm_l4per_mcspi1_clkctrl;
+	u32 cm_l4per_mcspi2_clkctrl;
+	u32 cm_l4per_mcspi3_clkctrl;
+	u32 cm_l4per_mcspi4_clkctrl;
+	u32 cm_l4per_gpio7_clkctrl;
+	u32 cm_l4per_gpio8_clkctrl;
+	u32 cm_l4per_mmcsd3_clkctrl;
+	u32 cm_l4per_mmcsd4_clkctrl;
+	u32 cm_l4per_msprohg_clkctrl;
+	u32 cm_l4per_slimbus2_clkctrl;
+	u32 cm_l4per_qspi_clkctrl;
+	u32 cm_l4per_uart1_clkctrl;
+	u32 cm_l4per_uart2_clkctrl;
+	u32 cm_l4per_uart3_clkctrl;
+	u32 cm_l4per_uart4_clkctrl;
+	u32 cm_l4per_mmcsd5_clkctrl;
+	u32 cm_l4per_i2c5_clkctrl;
+	u32 cm_l4per_uart5_clkctrl;
+	u32 cm_l4per_uart6_clkctrl;
+	u32 cm_l4sec_clkstctrl;
+	u32 cm_l4sec_staticdep;
+	u32 cm_l4sec_dynamicdep;
+	u32 cm_l4sec_aes1_clkctrl;
+	u32 cm_l4sec_aes2_clkctrl;
+	u32 cm_l4sec_des3des_clkctrl;
+	u32 cm_l4sec_pkaeip29_clkctrl;
+	u32 cm_l4sec_rng_clkctrl;
+	u32 cm_l4sec_sha2md51_clkctrl;
+	u32 cm_l4sec_cryptodma_clkctrl;
+
+	/* l4 wkup regs */
+	u32 cm_abe_pll_ref_clksel;
+	u32 cm_sys_clksel;
+	u32 cm_abe_pll_sys_clksel;
+	u32 cm_wkup_clkstctrl;
+	u32 cm_wkup_l4wkup_clkctrl;
+	u32 cm_wkup_wdtimer1_clkctrl;
+	u32 cm_wkup_wdtimer2_clkctrl;
+	u32 cm_wkup_gpio1_clkctrl;
+	u32 cm_wkup_gptimer1_clkctrl;
+	u32 cm_wkup_gptimer12_clkctrl;
+	u32 cm_wkup_synctimer_clkctrl;
+	u32 cm_wkup_usim_clkctrl;
+	u32 cm_wkup_sarram_clkctrl;
+	u32 cm_wkup_keyboard_clkctrl;
+	u32 cm_wkup_rtc_clkctrl;
+	u32 cm_wkup_bandgap_clkctrl;
+	u32 cm_wkupaon_scrm_clkctrl;
+	u32 cm_wkupaon_io_srcomp_clkctrl;
+	u32 prm_rstctrl;
+	u32 prm_rstst;
+	u32 prm_rsttime;
+	u32 prm_vc_val_bypass;
+	u32 prm_vc_cfg_i2c_mode;
+	u32 prm_vc_cfg_i2c_clk;
+	u32 prm_abbldo_mpu_setup;
+	u32 prm_abbldo_mpu_ctrl;
+
+	u32 cm_div_m4_dpll_core;
+	u32 cm_div_m5_dpll_core;
+	u32 cm_div_m6_dpll_core;
+	u32 cm_div_m7_dpll_core;
+	u32 cm_div_m4_dpll_iva;
+	u32 cm_div_m5_dpll_iva;
+	u32 cm_div_m4_dpll_ddrphy;
+	u32 cm_div_m5_dpll_ddrphy;
+	u32 cm_div_m6_dpll_ddrphy;
+	u32 cm_div_m4_dpll_per;
+	u32 cm_div_m5_dpll_per;
+	u32 cm_div_m6_dpll_per;
+	u32 cm_div_m7_dpll_per;
+	u32 cm_l3instr_intrconn_wp1_clkct;
+	u32 cm_l3init_usbphy_clkctrl;
+	u32 cm_l4per_mcbsp4_clkctrl;
+	u32 prm_vc_cfg_channel;
+
+	/* SCRM stuff, used by some boards */
+	u32 scrm_auxclk0;
+	u32 scrm_auxclk1;
+
+	/* GMAC Clk Ctrl */
+	u32 cm_gmac_gmac_clkctrl;
+	u32 cm_gmac_clkstctrl;
+};
+
+struct omap_sys_ctrl_regs {
+	u32 control_status;
+	u32 control_core_mac_id_0_lo;
+	u32 control_core_mac_id_0_hi;
+	u32 control_core_mac_id_1_lo;
+	u32 control_core_mac_id_1_hi;
+	u32 control_std_fuse_opp_vdd_mpu_2;
+	u32 control_phy_power_usb;
+	u32 control_core_mmr_lock1;
+	u32 control_core_mmr_lock2;
+	u32 control_core_mmr_lock3;
+	u32 control_core_mmr_lock4;
+	u32 control_core_mmr_lock5;
+	u32 control_core_control_io1;
+	u32 control_core_control_io2;
+	u32 control_id_code;
+	u32 control_std_fuse_opp_bgap;
+	u32 control_ldosram_iva_voltage_ctrl;
+	u32 control_ldosram_mpu_voltage_ctrl;
+	u32 control_ldosram_core_voltage_ctrl;
+	u32 control_usbotghs_ctrl;
+	u32 control_phy_power_sata;
+	u32 control_padconf_core_base;
+	u32 control_paconf_global;
+	u32 control_paconf_mode;
+	u32 control_smart1io_padconf_0;
+	u32 control_smart1io_padconf_1;
+	u32 control_smart1io_padconf_2;
+	u32 control_smart2io_padconf_0;
+	u32 control_smart2io_padconf_1;
+	u32 control_smart2io_padconf_2;
+	u32 control_smart3io_padconf_0;
+	u32 control_smart3io_padconf_1;
+	u32 control_pbias;
+	u32 control_i2c_0;
+	u32 control_camera_rx;
+	u32 control_hdmi_tx_phy;
+	u32 control_uniportm;
+	u32 control_dsiphy;
+	u32 control_mcbsplp;
+	u32 control_usb2phycore;
+	u32 control_hdmi_1;
+	u32 control_hsi;
+	u32 control_ddr3ch1_0;
+	u32 control_ddr3ch2_0;
+	u32 control_ddrch1_0;
+	u32 control_ddrch1_1;
+	u32 control_ddrch2_0;
+	u32 control_ddrch2_1;
+	u32 control_lpddr2ch1_0;
+	u32 control_lpddr2ch1_1;
+	u32 control_ddrio_0;
+	u32 control_ddrio_1;
+	u32 control_ddrio_2;
+	u32 control_ddr_control_ext_0;
+	u32 control_lpddr2io1_0;
+	u32 control_lpddr2io1_1;
+	u32 control_lpddr2io1_2;
+	u32 control_lpddr2io1_3;
+	u32 control_lpddr2io2_0;
+	u32 control_lpddr2io2_1;
+	u32 control_lpddr2io2_2;
+	u32 control_lpddr2io2_3;
+	u32 control_hyst_1;
+	u32 control_usbb_hsic_control;
+	u32 control_c2c;
+	u32 control_core_control_spare_rw;
+	u32 control_core_control_spare_r;
+	u32 control_core_control_spare_r_c0;
+	u32 control_srcomp_north_side;
+	u32 control_srcomp_south_side;
+	u32 control_srcomp_east_side;
+	u32 control_srcomp_west_side;
+	u32 control_srcomp_code_latch;
+	u32 control_pbiaslite;
+	u32 control_port_emif1_sdram_config;
+	u32 control_port_emif1_lpddr2_nvm_config;
+	u32 control_port_emif2_sdram_config;
+	u32 control_emif1_sdram_config_ext;
+	u32 control_emif2_sdram_config_ext;
+	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
+	u32 control_smart1nopmio_padconf_0;
+	u32 control_smart1nopmio_padconf_1;
+	u32 control_padconf_mode;
+	u32 control_xtal_oscillator;
+	u32 control_i2c_2;
+	u32 control_ckobuffer;
+	u32 control_wkup_control_spare_rw;
+	u32 control_wkup_control_spare_r;
+	u32 control_wkup_control_spare_r_c0;
+	u32 control_srcomp_east_side_wkup;
+	u32 control_efuse_1;
+	u32 control_efuse_2;
+	u32 control_efuse_3;
+	u32 control_efuse_4;
+	u32 control_efuse_5;
+	u32 control_efuse_6;
+	u32 control_efuse_7;
+	u32 control_efuse_8;
+	u32 control_efuse_9;
+	u32 control_efuse_10;
+	u32 control_efuse_11;
+	u32 control_efuse_12;
+	u32 control_efuse_13;
+	u32 control_padconf_wkup_base;
+};
+
+struct dpll_params {
+	u32 m;
+	u32 n;
+	s8 m2;
+	s8 m3;
+	s8 m4_h11;
+	s8 m5_h12;
+	s8 m6_h13;
+	s8 m7_h14;
+	s8 h21;
+	s8 h22;
+	s8 h23;
+	s8 h24;
+};
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_h11_dpll;
+	u32 cm_div_m5_h12_dpll;
+	u32 cm_div_m6_h13_dpll;
+	u32 cm_div_m7_h14_dpll;
+	u32 reserved[2];
+	u32 cm_div_h21_dpll;
+	u32 cm_div_h22_dpll;
+	u32 cm_div_h23_dpll;
+	u32 cm_div_h24_dpll;
+};
+
+struct dplls {
+	const struct dpll_params *mpu;
+	const struct dpll_params *core;
+	const struct dpll_params *per;
+	const struct dpll_params *abe;
+	const struct dpll_params *iva;
+	const struct dpll_params *usb;
+	const struct dpll_params *ddr;
+	const struct dpll_params *gmac;
+};
+
+struct pmic_data {
+	u32 base_offset;
+	u32 step;
+	u32 start_code;
+	unsigned gpio;
+	int gpio_en;
+	u32 i2c_slave_addr;
+	void (*pmic_bus_init)(void);
+	int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
+};
+
+/**
+ * struct volts_efuse_data - efuse definition for voltage
+ * @reg:	register address for efuse
+ * @reg_bits:	Number of bits in a register address, mandatory.
+ */
+struct volts_efuse_data {
+	u32 reg;
+	u8 reg_bits;
+};
+
+struct volts {
+	u32 value;
+	u32 addr;
+	struct volts_efuse_data efuse;
+	struct pmic_data *pmic;
+};
+
+struct vcores_data {
+	struct volts mpu;
+	struct volts core;
+	struct volts mm;
+	struct volts gpu;
+	struct volts eve;
+	struct volts iva;
+};
+
+extern struct prcm_regs const **prcm;
+extern struct prcm_regs const omap5_es1_prcm;
+extern struct prcm_regs const omap5_es2_prcm;
+extern struct prcm_regs const omap4_prcm;
+extern struct prcm_regs const dra7xx_prcm;
+extern struct dplls const **dplls_data;
+extern struct vcores_data const **omap_vcores;
+extern const u32 sys_clk_array[8];
+extern struct omap_sys_ctrl_regs const **ctrl;
+extern struct omap_sys_ctrl_regs const omap4_ctrl;
+extern struct omap_sys_ctrl_regs const omap5_ctrl;
+extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
+
+void hw_data_init(void);
+
+const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
+const struct dpll_params *get_core_dpll_params(struct dplls const *);
+const struct dpll_params *get_per_dpll_params(struct dplls const *);
+const struct dpll_params *get_iva_dpll_params(struct dplls const *);
+const struct dpll_params *get_usb_dpll_params(struct dplls const *);
+const struct dpll_params *get_abe_dpll_params(struct dplls const *);
+
+void do_enable_clocks(u32 const *clk_domains,
+		      u32 const *clk_modules_hw_auto,
+		      u32 const *clk_modules_explicit_en,
+		      u8 wait_for_enable);
+
+void setup_post_dividers(u32 const base,
+			const struct dpll_params *params);
+u32 omap_ddr_clk(void);
+u32 get_sys_clk_index(void);
+void enable_basic_clocks(void);
+void enable_basic_uboot_clocks(void);
+void scale_vcores(struct vcores_data const *);
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
+void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
+	       u32 txdone, u32 txdone_mask, u32 opp);
+s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
+
+void usb_fake_mac_from_die_id(u32 *id);
+
+/* HW Init Context */
+#define OMAP_INIT_CONTEXT_SPL			0
+#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
+
+/* ABB */
+#define OMAP_ABB_NOMINAL_OPP		0
+#define OMAP_ABB_FAST_OPP		1
+#define OMAP_ABB_SLOW_OPP		3
+#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK		(0x1 << 0)
+#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK		(0x1 << 1)
+#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK		(0x1 << 2)
+#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK		(0x1 << 6)
+#define OMAP_ABB_SETUP_SR2EN_MASK			(0x1 << 0)
+#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK		(0x1 << 2)
+#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK		(0x1 << 1)
+#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK		(0xff << 8)
+
+static inline u32 omap_revision(void)
+{
+	extern u32 *const omap_si_rev;
+	return *omap_si_rev;
+}
+
+#define OMAP54xx	0x54000000
+
+static inline u8 is_omap54xx(void)
+{
+	extern u32 *const omap_si_rev;
+	return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
+}
+
+#define DRA7XX		0x07000000
+
+static inline u8 is_dra7xx(void)
+{
+	extern u32 *const omap_si_rev;
+	return ((*omap_si_rev & 0xFF000000) == DRA7XX);
+}
+#endif
+
+/*
+ * silicon revisions.
+ * Moving this to common, so that most of code can be moved to common,
+ * directories.
+ */
+
+/* omap4 */
+#define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
+#define OMAP4430_ES1_0	0x44300100
+#define OMAP4430_ES2_0	0x44300200
+#define OMAP4430_ES2_1	0x44300210
+#define OMAP4430_ES2_2	0x44300220
+#define OMAP4430_ES2_3	0x44300230
+#define OMAP4460_ES1_0	0x44600100
+#define OMAP4460_ES1_1	0x44600110
+#define OMAP4470_ES1_0	0x44700100
+
+/* omap5 */
+#define OMAP5430_SILICON_ID_INVALID	0
+#define OMAP5430_ES1_0	0x54300100
+#define OMAP5432_ES1_0	0x54320100
+#define OMAP5430_ES2_0  0x54300200
+#define OMAP5432_ES2_0  0x54320200
+
+/* DRA7XX */
+#define DRA752_ES1_0	0x07520100
+#define DRA752_ES1_1	0x07520110
+
+/*
+ * SRAM scratch space entries
+ */
+#define OMAP_SRAM_SCRATCH_OMAP_REV	SRAM_SCRATCH_SPACE_ADDR
+#define OMAP_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP_SRAM_SCRATCH_BOOT_PARAMS	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
+#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x28)
+
+#endif /* _OMAP_COMMON_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/omap_gpio.h b/qemu/roms/u-boot/arch/arm/include/asm/omap_gpio.h
new file mode 100644
index 000000000..5d25d04c3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/omap_gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+#ifndef _GPIO_H
+#define _GPIO_H
+
+#include <asm/arch/cpu.h>
+
+struct gpio_bank {
+	void *base;
+	int method;
+};
+
+extern const struct gpio_bank *const omap_gpio_bank;
+
+#define METHOD_GPIO_24XX	4
+
+/**
+ * Check if gpio is valid.
+ *
+ * @param gpio	GPIO number
+ * @return 1 if ok, 0 on error
+ */
+int gpio_is_valid(int gpio);
+#endif /* _GPIO_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/omap_mmc.h b/qemu/roms/u-boot/arch/arm/include/asm/omap_mmc.h
new file mode 100644
index 000000000..617e22fa5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/omap_mmc.h
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef OMAP_MMC_H_
+#define OMAP_MMC_H_
+
+struct hsmmc {
+	unsigned char res1[0x10];
+	unsigned int sysconfig;		/* 0x10 */
+	unsigned int sysstatus;		/* 0x14 */
+	unsigned char res2[0x14];
+	unsigned int con;		/* 0x2C */
+	unsigned char res3[0xD4];
+	unsigned int blk;		/* 0x104 */
+	unsigned int arg;		/* 0x108 */
+	unsigned int cmd;		/* 0x10C */
+	unsigned int rsp10;		/* 0x110 */
+	unsigned int rsp32;		/* 0x114 */
+	unsigned int rsp54;		/* 0x118 */
+	unsigned int rsp76;		/* 0x11C */
+	unsigned int data;		/* 0x120 */
+	unsigned int pstate;		/* 0x124 */
+	unsigned int hctl;		/* 0x128 */
+	unsigned int sysctl;		/* 0x12C */
+	unsigned int stat;		/* 0x130 */
+	unsigned int ie;		/* 0x134 */
+	unsigned char res4[0x8];
+	unsigned int capa;		/* 0x140 */
+};
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET			(0x1 << 1)
+#define RESETDONE			(0x1 << 0)
+#define NOOPENDRAIN			(0x0 << 0)
+#define OPENDRAIN			(0x1 << 0)
+#define OD				(0x1 << 0)
+#define INIT_NOINIT			(0x0 << 1)
+#define INIT_INITSTREAM			(0x1 << 1)
+#define HR_NOHOSTRESP			(0x0 << 2)
+#define STR_BLOCK			(0x0 << 3)
+#define MODE_FUNC			(0x0 << 4)
+#define DW8_1_4BITMODE			(0x0 << 5)
+#define MIT_CTO				(0x0 << 6)
+#define CDP_ACTIVEHIGH			(0x0 << 7)
+#define WPP_ACTIVEHIGH			(0x0 << 8)
+#define RESERVED_MASK			(0x3 << 9)
+#define CTPL_MMC_SD			(0x0 << 11)
+#define BLEN_512BYTESLEN		(0x200 << 0)
+#define NBLK_STPCNT			(0x0 << 16)
+#define DE_DISABLE			(0x0 << 0)
+#define BCE_DISABLE			(0x0 << 1)
+#define BCE_ENABLE			(0x1 << 1)
+#define ACEN_DISABLE			(0x0 << 2)
+#define DDIR_OFFSET			(4)
+#define DDIR_MASK			(0x1 << 4)
+#define DDIR_WRITE			(0x0 << 4)
+#define DDIR_READ			(0x1 << 4)
+#define MSBS_SGLEBLK			(0x0 << 5)
+#define MSBS_MULTIBLK			(0x1 << 5)
+#define RSP_TYPE_OFFSET			(16)
+#define RSP_TYPE_MASK			(0x3 << 16)
+#define RSP_TYPE_NORSP			(0x0 << 16)
+#define RSP_TYPE_LGHT136		(0x1 << 16)
+#define RSP_TYPE_LGHT48			(0x2 << 16)
+#define RSP_TYPE_LGHT48B		(0x3 << 16)
+#define CCCE_NOCHECK			(0x0 << 19)
+#define CCCE_CHECK			(0x1 << 19)
+#define CICE_NOCHECK			(0x0 << 20)
+#define CICE_CHECK			(0x1 << 20)
+#define DP_OFFSET			(21)
+#define DP_MASK				(0x1 << 21)
+#define DP_NO_DATA			(0x0 << 21)
+#define DP_DATA				(0x1 << 21)
+#define CMD_TYPE_NORMAL			(0x0 << 22)
+#define INDEX_OFFSET			(24)
+#define INDEX_MASK			(0x3f << 24)
+#define INDEX(i)			(i << 24)
+#define DATI_MASK			(0x1 << 1)
+#define CMDI_MASK			(0x1 << 0)
+#define DTW_1_BITMODE			(0x0 << 1)
+#define DTW_4_BITMODE			(0x1 << 1)
+#define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
+#define SDBP_PWROFF			(0x0 << 8)
+#define SDBP_PWRON			(0x1 << 8)
+#define SDVS_1V8			(0x5 << 9)
+#define SDVS_3V0			(0x6 << 9)
+#define ICE_MASK			(0x1 << 0)
+#define ICE_STOP			(0x0 << 0)
+#define ICS_MASK			(0x1 << 1)
+#define ICS_NOTREADY			(0x0 << 1)
+#define ICE_OSCILLATE			(0x1 << 0)
+#define CEN_MASK			(0x1 << 2)
+#define CEN_DISABLE			(0x0 << 2)
+#define CEN_ENABLE			(0x1 << 2)
+#define CLKD_OFFSET			(6)
+#define CLKD_MASK			(0x3FF << 6)
+#define DTO_MASK			(0xF << 16)
+#define DTO_15THDTO			(0xE << 16)
+#define SOFTRESETALL			(0x1 << 24)
+#define CC_MASK				(0x1 << 0)
+#define TC_MASK				(0x1 << 1)
+#define BWR_MASK			(0x1 << 4)
+#define BRR_MASK			(0x1 << 5)
+#define ERRI_MASK			(0x1 << 15)
+#define IE_CC				(0x01 << 0)
+#define IE_TC				(0x01 << 1)
+#define IE_BWR				(0x01 << 4)
+#define IE_BRR				(0x01 << 5)
+#define IE_CTO				(0x01 << 16)
+#define IE_CCRC				(0x01 << 17)
+#define IE_CEB				(0x01 << 18)
+#define IE_CIE				(0x01 << 19)
+#define IE_DTO				(0x01 << 20)
+#define IE_DCRC				(0x01 << 21)
+#define IE_DEB				(0x01 << 22)
+#define IE_CERR				(0x01 << 28)
+#define IE_BADA				(0x01 << 29)
+
+#define VS30_3V0SUP			(1 << 25)
+#define VS18_1V8SUP			(1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE		512
+#define MMC_CARD			0
+#define SD_CARD				1
+#define BYTE_MODE			0
+#define SECTOR_MODE			1
+#define CLK_INITSEQ			0
+#define CLK_400KHZ			1
+#define CLK_MISC			2
+
+#define RSP_TYPE_NONE	(RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0	(INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE	96 /* MHz */
+
+#define mmc_reg_out(addr, mask, val)\
+	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
+		int wp_gpio);
+
+
+#endif /* OMAP_MMC_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/omap_musb.h b/qemu/roms/u-boot/arch/arm/include/asm/omap_musb.h
new file mode 100644
index 000000000..8b9cb0eb8
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/omap_musb.h
@@ -0,0 +1,24 @@
+/*
+ * Board data structure for musb gadget on OMAPs
+ *
+ * Copyright (C) 2012, Ilya Yanok <ilya.yanok@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_OMAP_MUSB_H
+#define __ASM_ARM_OMAP_MUSB_H
+
+extern struct musb_platform_ops musb_dsps_ops;
+extern const struct musb_platform_ops am35x_ops;
+extern const struct musb_platform_ops omap2430_ops;
+
+struct omap_musb_board_data {
+	u8 interface_type;
+	void (*set_phy_power)(u8 on);
+	void (*clear_irq)(void);
+	void (*reset)(void);
+};
+
+enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
+#endif /* __ASM_ARM_OMAP_MUSB_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/pl310.h b/qemu/roms/u-boot/arch/arm/include/asm/pl310.h
new file mode 100644
index 000000000..ddc245bfd
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/pl310.h
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _PL310_H_
+#define _PL310_H_
+
+#include <linux/types.h>
+
+/* Register bit fields */
+#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK	(1 << 16)
+#define L2X0_DYNAMIC_CLK_GATING_EN		(1 << 1)
+#define L2X0_STNDBY_MODE_EN			(1 << 0)
+#define L2X0_CTRL_EN				1
+
+struct pl310_regs {
+	u32 pl310_cache_id;
+	u32 pl310_cache_type;
+	u32 pad1[62];
+	u32 pl310_ctrl;
+	u32 pl310_aux_ctrl;
+	u32 pl310_tag_latency_ctrl;
+	u32 pl310_data_latency_ctrl;
+	u32 pad2[60];
+	u32 pl310_event_cnt_ctrl;
+	u32 pl310_event_cnt1_cfg;
+	u32 pl310_event_cnt0_cfg;
+	u32 pl310_event_cnt1_val;
+	u32 pl310_event_cnt0_val;
+	u32 pl310_intr_mask;
+	u32 pl310_masked_intr_stat;
+	u32 pl310_raw_intr_stat;
+	u32 pl310_intr_clear;
+	u32 pad3[323];
+	u32 pl310_cache_sync;
+	u32 pad4[15];
+	u32 pl310_inv_line_pa;
+	u32 pad5[2];
+	u32 pl310_inv_way;
+	u32 pad6[12];
+	u32 pl310_clean_line_pa;
+	u32 pad7[1];
+	u32 pl310_clean_line_idx;
+	u32 pl310_clean_way;
+	u32 pad8[12];
+	u32 pl310_clean_inv_line_pa;
+	u32 pad9[1];
+	u32 pl310_clean_inv_line_idx;
+	u32 pl310_clean_inv_way;
+	u32 pad10[64];
+	u32 pl310_lockdown_dbase;
+	u32 pl310_lockdown_ibase;
+	u32 pad11[190];
+	u32 pl310_addr_filter_start;
+	u32 pl310_addr_filter_end;
+	u32 pad12[190];
+	u32 pl310_test_operation;
+	u32 pad13[3];
+	u32 pl310_line_data;
+	u32 pad14[7];
+	u32 pl310_line_tag;
+	u32 pad15[3];
+	u32 pl310_debug_ctrl;
+	u32 pad16[7];
+	u32 pl310_prefetch_ctrl;
+	u32 pad17[7];
+	u32 pl310_power_ctrl;
+};
+
+void pl310_inval_all(void);
+void pl310_clean_inval_all(void);
+void pl310_inval_range(u32 start, u32 end);
+void pl310_clean_inval_range(u32 start, u32 end);
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/posix_types.h b/qemu/roms/u-boot/arch/arm/include/asm/posix_types.h
new file mode 100644
index 000000000..d254b95b2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/posix_types.h
@@ -0,0 +1,87 @@
+/*
+ *  linux/include/asm-arm/posix_types.h
+ *
+ *  Copyright (C) 1996-1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ */
+#ifndef __ARCH_ARM_POSIX_TYPES_H
+#define __ARCH_ARM_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+
+#ifdef	__aarch64__
+typedef unsigned long		__kernel_size_t;
+typedef long			__kernel_ssize_t;
+typedef long			__kernel_ptrdiff_t;
+#else
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+#endif
+
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char *			__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp)))
+
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/domain.h b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/domain.h
new file mode 100644
index 000000000..aadc83187
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/domain.h
@@ -0,0 +1,50 @@
+/*
+ *  linux/include/asm-arm/proc-armv/domain.h
+ *
+ *  Copyright (C) 1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_DOMAIN_H
+#define __ASM_PROC_DOMAIN_H
+
+/*
+ * Domain numbers
+ *
+ *  DOMAIN_IO     - domain 2 includes all IO only
+ *  DOMAIN_KERNEL - domain 1 includes all kernel memory only
+ *  DOMAIN_USER   - domain 0 includes all user memory only
+ */
+#define DOMAIN_USER	0
+#define DOMAIN_KERNEL	1
+#define DOMAIN_TABLE	1
+#define DOMAIN_IO	2
+
+/*
+ * Domain types
+ */
+#define DOMAIN_NOACCESS	0
+#define DOMAIN_CLIENT	1
+#define DOMAIN_MANAGER	3
+
+#define domain_val(dom,type)	((type) << 2*(dom))
+
+#define set_domain(x)					\
+	do {						\
+	__asm__ __volatile__(				\
+	"mcr	p15, 0, %0, c3, c0	@ set domain"	\
+	  : : "r" (x));					\
+	} while (0)
+
+#define modify_domain(dom,type)				\
+	do {						\
+	unsigned int domain = current->thread.domain;	\
+	domain &= ~domain_val(dom, DOMAIN_MANAGER);	\
+	domain |= domain_val(dom, type);		\
+	current->thread.domain = domain;		\
+	set_domain(current->thread.domain);		\
+	} while (0)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/processor.h b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/processor.h
new file mode 100644
index 000000000..5bfab7fb9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/processor.h
@@ -0,0 +1,74 @@
+/*
+ *  linux/include/asm-arm/proc-armv/processor.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-09-1996	RMK	Created
+ *   26-09-1996	RMK	Added 'EXTRA_THREAD_STRUCT*'
+ *   28-09-1996	RMK	Moved start_thread into the processor dependencies
+ *   09-09-1998	PJB	Delete redundant `wp_works_ok'
+ *   30-05-1999	PJB	Save sl across context switches
+ *   31-07-1999	RMK	Added 'domain' stuff
+ */
+#ifndef __ASM_PROC_PROCESSOR_H
+#define __ASM_PROC_PROCESSOR_H
+
+#include <asm/proc/domain.h>
+
+#define KERNEL_STACK_SIZE	PAGE_SIZE
+
+struct context_save_struct {
+	unsigned long cpsr;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long sl;
+	unsigned long fp;
+	unsigned long pc;
+};
+
+#define INIT_CSS (struct context_save_struct){ SVC_MODE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+
+#define EXTRA_THREAD_STRUCT						\
+	unsigned int	domain;
+
+#define EXTRA_THREAD_STRUCT_INIT					\
+	domain:	  domain_val(DOMAIN_USER, DOMAIN_CLIENT) |		\
+		  domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) |		\
+		  domain_val(DOMAIN_IO, DOMAIN_CLIENT)
+
+#define start_thread(regs,pc,sp)					\
+({									\
+	unsigned long *stack = (unsigned long *)sp;			\
+	set_fs(USER_DS);						\
+	memzero(regs->uregs, sizeof(regs->uregs));			\
+	if (current->personality & ADDR_LIMIT_32BIT)			\
+		regs->ARM_cpsr = USR_MODE;				\
+	else								\
+		regs->ARM_cpsr = USR26_MODE;				\
+	regs->ARM_pc = pc;		/* pc */			\
+	regs->ARM_sp = sp;		/* sp */			\
+	regs->ARM_r2 = stack[2];	/* r2 (envp) */			\
+	regs->ARM_r1 = stack[1];	/* r1 (argv) */			\
+	regs->ARM_r0 = stack[0];	/* r0 (argc) */			\
+})
+
+#define KSTK_EIP(tsk)	(((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
+#define KSTK_ESP(tsk)	(((unsigned long *)(4096+(unsigned long)(tsk)))[1017])
+
+/* Allocation and freeing of basic task resources. */
+/*
+ * NOTE! The task struct and the stack go together
+ */
+#define ll_alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
+#define ll_free_task_struct(p) free_pages((unsigned long)(p),1)
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h
new file mode 100644
index 000000000..21aef58b7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/ptrace.h
@@ -0,0 +1,128 @@
+/*
+ *  linux/include/asm-arm/proc-armv/ptrace.h
+ *
+ *  Copyright (C) 1996-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_PTRACE_H
+#define __ASM_PROC_PTRACE_H
+
+#ifdef CONFIG_ARM64
+
+#define PCMASK		0
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored
+ * on the stack during an exception.
+ */
+struct pt_regs {
+	unsigned long elr;
+	unsigned long regs[31];
+};
+
+#endif	/* __ASSEMBLY__ */
+
+#else	/* CONFIG_ARM64 */
+
+#define USR26_MODE	0x00
+#define FIQ26_MODE	0x01
+#define IRQ26_MODE	0x02
+#define SVC26_MODE	0x03
+#define USR_MODE	0x10
+#define FIQ_MODE	0x11
+#define IRQ_MODE	0x12
+#define SVC_MODE	0x13
+#define ABT_MODE	0x17
+#define UND_MODE	0x1b
+#define SYSTEM_MODE	0x1f
+#define MODE_MASK	0x1f
+#define T_BIT		0x20
+#define F_BIT		0x40
+#define I_BIT		0x80
+#define CC_V_BIT	(1 << 28)
+#define CC_C_BIT	(1 << 29)
+#define CC_Z_BIT	(1 << 30)
+#define CC_N_BIT	(1 << 31)
+#define PCMASK		0
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+struct pt_regs {
+	long uregs[18];
+};
+
+#define ARM_cpsr	uregs[16]
+#define ARM_pc		uregs[15]
+#define ARM_lr		uregs[14]
+#define ARM_sp		uregs[13]
+#define ARM_ip		uregs[12]
+#define ARM_fp		uregs[11]
+#define ARM_r10		uregs[10]
+#define ARM_r9		uregs[9]
+#define ARM_r8		uregs[8]
+#define ARM_r7		uregs[7]
+#define ARM_r6		uregs[6]
+#define ARM_r5		uregs[5]
+#define ARM_r4		uregs[4]
+#define ARM_r3		uregs[3]
+#define ARM_r2		uregs[2]
+#define ARM_r1		uregs[1]
+#define ARM_r0		uregs[0]
+#define ARM_ORIG_r0	uregs[17]
+
+#ifdef __KERNEL__
+
+#define user_mode(regs)	\
+	(((regs)->ARM_cpsr & 0xf) == 0)
+
+#ifdef CONFIG_ARM_THUMB
+#define thumb_mode(regs) \
+	(((regs)->ARM_cpsr & T_BIT))
+#else
+#define thumb_mode(regs) (0)
+#endif
+
+#define processor_mode(regs) \
+	((regs)->ARM_cpsr & MODE_MASK)
+
+#define interrupts_enabled(regs) \
+	(!((regs)->ARM_cpsr & I_BIT))
+
+#define fast_interrupts_enabled(regs) \
+	(!((regs)->ARM_cpsr & F_BIT))
+
+#define condition_codes(regs) \
+	((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
+
+/* Are the current registers suitable for user mode?
+ * (used to maintain security in signal handlers)
+ */
+static inline int valid_user_regs(struct pt_regs *regs)
+{
+	if ((regs->ARM_cpsr & 0xf) == 0 &&
+	    (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
+		return 1;
+
+	/*
+	 * Force CPSR to something logical...
+	 */
+	regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
+
+	return 0;
+}
+
+#endif	/* __KERNEL__ */
+
+#endif	/* __ASSEMBLY__ */
+
+#endif	/* CONFIG_ARM64 */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/system.h b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/system.h
new file mode 100644
index 000000000..693d1f492
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/proc-armv/system.h
@@ -0,0 +1,224 @@
+/*
+ *  linux/include/asm-arm/proc-armv/system.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_SYSTEM_H
+#define __ASM_PROC_SYSTEM_H
+
+/*
+ * Save the current interrupt enable state & disable IRQs
+ */
+#ifdef CONFIG_ARM64
+
+/*
+ * Save the current interrupt enable state
+ * and disable IRQs/FIQs
+ */
+#define local_irq_save(flags)					\
+	({							\
+	asm volatile(						\
+	"mrs	%0, daif"					\
+	"msr	daifset, #3"					\
+	: "=r" (flags)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define local_irq_restore(flags)				\
+	({							\
+	asm volatile(						\
+	"msr	daif, %0"					\
+	:							\
+	: "r" (flags)						\
+	: "memory");						\
+	})
+
+/*
+ * Enable IRQs/FIQs
+ */
+#define local_irq_enable()					\
+	({							\
+	asm volatile(						\
+	"msr	daifclr, #3"					\
+	:							\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Disable IRQs/FIQs
+ */
+#define local_irq_disable()					\
+	({							\
+	asm volatile(						\
+	"msr	daifset, #3"					\
+	:							\
+	:							\
+	: "memory");						\
+	})
+
+#else	/* CONFIG_ARM64 */
+
+#define local_irq_save(x)					\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_irq_save\n"	\
+"	orr	%1, %0, #128\n"					\
+"	msr	cpsr_c, %1"					\
+	: "=r" (x), "=r" (temp)					\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Enable IRQs
+ */
+#define local_irq_enable()					\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_irq_enable\n"	\
+"	bic	%0, %0, #128\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Disable IRQs
+ */
+#define local_irq_disable()					\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_irq_disable\n"	\
+"	orr	%0, %0, #128\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Enable FIQs
+ */
+#define __stf()							\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ stf\n"		\
+"	bic	%0, %0, #64\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Disable FIQs
+ */
+#define __clf()							\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ clf\n"		\
+"	orr	%0, %0, #64\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Save the current interrupt enable state.
+ */
+#define local_save_flags(x)					\
+	({							\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_save_flags\n"	\
+	  : "=r" (x)						\
+	  :							\
+	  : "memory");						\
+	})
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define local_irq_restore(x)					\
+	__asm__ __volatile__(					\
+	"msr	cpsr_c, %0		@ local_irq_restore\n"	\
+	:							\
+	: "r" (x)						\
+	: "memory")
+
+#endif	/* CONFIG_ARM64 */
+
+#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \
+	defined(CONFIG_ARM64)
+/*
+ * On the StrongARM, "swp" is terminally broken since it bypasses the
+ * cache totally.  This means that the cache becomes inconsistent, and,
+ * since we use normal loads/stores as well, this is really bad.
+ * Typically, this causes oopsen in filp_close, but could have other,
+ * more disasterous effects.  There are two work-arounds:
+ *  1. Disable interrupts and emulate the atomic swap
+ *  2. Clean the cache, perform atomic swap, flush the cache
+ *
+ * We choose (1) since its the "easiest" to achieve here and is not
+ * dependent on the processor type.
+ */
+#define swp_is_buggy
+#endif
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+{
+	extern void __bad_xchg(volatile void *, int);
+	unsigned long ret;
+#ifdef swp_is_buggy
+	unsigned long flags;
+#endif
+
+	switch (size) {
+#ifdef swp_is_buggy
+		case 1:
+			local_irq_save(flags);
+			ret = *(volatile unsigned char *)ptr;
+			*(volatile unsigned char *)ptr = x;
+			local_irq_restore(flags);
+			break;
+
+		case 4:
+			local_irq_save(flags);
+			ret = *(volatile unsigned long *)ptr;
+			*(volatile unsigned long *)ptr = x;
+			local_irq_restore(flags);
+			break;
+#else
+		case 1:	__asm__ __volatile__ ("swpb %0, %1, [%2]"
+					: "=&r" (ret)
+					: "r" (x), "r" (ptr)
+					: "memory");
+			break;
+		case 4:	__asm__ __volatile__ ("swp %0, %1, [%2]"
+					: "=&r" (ret)
+					: "r" (x), "r" (ptr)
+					: "memory");
+			break;
+#endif
+		default: __bad_xchg(ptr, size), ret = 0;
+	}
+
+	return ret;
+}
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/processor.h b/qemu/roms/u-boot/arch/arm/include/asm/processor.h
new file mode 100644
index 000000000..445d4495b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/processor.h
@@ -0,0 +1,134 @@
+/*
+ *  linux/include/asm-arm/processor.h
+ *
+ *  Copyright (C) 1995-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_PROCESSOR_H
+#define __ASM_ARM_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#define FP_SIZE 35
+
+struct fp_hard_struct {
+	unsigned int save[FP_SIZE];		/* as yet undefined */
+};
+
+struct fp_soft_struct {
+	unsigned int save[FP_SIZE];		/* undefined information */
+};
+
+union fp_state {
+	struct fp_hard_struct	hard;
+	struct fp_soft_struct	soft;
+};
+
+typedef unsigned long mm_segment_t;		/* domain register	*/
+
+#ifdef __KERNEL__
+
+#define EISA_bus 0
+#define MCA_bus 0
+#define MCA_bus__is_a_macro
+
+#include <asm/atomic.h>
+#include <asm/ptrace.h>
+#if 0	/* XXX###XXX */
+#include <asm/arch/memory.h>
+#endif	/* XXX###XXX */
+#include <asm/proc/processor.h>
+#include <asm/types.h>
+
+union debug_insn {
+	u32	arm;
+	u16	thumb;
+};
+
+struct debug_entry {
+	u32			address;
+	union debug_insn	insn;
+};
+
+struct debug_info {
+	int			nsaved;
+	struct debug_entry	bp[2];
+};
+
+struct thread_struct {
+	atomic_t			refcount;
+							/* fault info	  */
+	unsigned long			address;
+	unsigned long			trap_no;
+	unsigned long			error_code;
+							/* floating point */
+	union fp_state			fpstate;
+							/* debugging	  */
+	struct debug_info		debug;
+							/* context info	  */
+	struct context_save_struct	*save;
+	EXTRA_THREAD_STRUCT
+};
+
+#define INIT_THREAD  {					\
+	refcount:	ATOMIC_INIT(1),			\
+	EXTRA_THREAD_STRUCT_INIT			\
+}
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+static inline unsigned long thread_saved_pc(struct thread_struct *t)
+{
+	return t->save ? pc_pointer(t->save->pc) : 0;
+}
+
+static inline unsigned long thread_saved_fp(struct thread_struct *t)
+{
+	return t->save ? t->save->fp : 0;
+}
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+
+/* Copy and release all segment info associated with a VM */
+#define copy_segments(tsk, mm)		do { } while (0)
+#define release_segments(mm)		do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define THREAD_SIZE	(8192)
+
+extern struct task_struct *alloc_task_struct(void);
+extern void __free_task_struct(struct task_struct *);
+#define get_task_struct(p)	atomic_inc(&(p)->thread.refcount)
+#define free_task_struct(p)					\
+ do {								\
+	if (atomic_dec_and_test(&(p)->thread.refcount))		\
+		__free_task_struct((p));			\
+ } while (0)
+
+#define init_task	(init_task_union.task)
+#define init_stack	(init_task_union.stack)
+
+#define cpu_relax()	barrier()
+
+/*
+ * Create a new kernel thread
+ */
+extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+#endif
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/ptrace.h b/qemu/roms/u-boot/arch/arm/include/asm/ptrace.h
new file mode 100644
index 000000000..73c9087b5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/ptrace.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_ARM_PTRACE_H
+#define __ASM_ARM_PTRACE_H
+
+#define PTRACE_GETREGS		12
+#define PTRACE_SETREGS		13
+#define PTRACE_GETFPREGS	14
+#define PTRACE_SETFPREGS	15
+
+#define PTRACE_SETOPTIONS	21
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD	0x00000001
+
+#include <asm/proc/ptrace.h>
+
+#ifndef __ASSEMBLY__
+#define pc_pointer(v) \
+	((v) & ~PCMASK)
+
+#define instruction_pointer(regs) \
+	(pc_pointer((regs)->ARM_pc))
+
+#ifdef __KERNEL__
+extern void show_regs(struct pt_regs *);
+
+#define predicate(x)	(x & 0xf0000000)
+#define PREDICATE_ALWAYS	0xe0000000
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/sections.h b/qemu/roms/u-boot/arch/arm/include/asm/sections.h
new file mode 100644
index 000000000..f7a7f4c41
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/sections.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_SECTIONS_H
+#define __ASM_ARM_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/setup.h b/qemu/roms/u-boot/arch/arm/include/asm/setup.h
new file mode 100644
index 000000000..78a7facfc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/setup.h
@@ -0,0 +1,274 @@
+/*
+ *  linux/include/asm/setup.h
+ *
+ *  Copyright (C) 1997-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Structure passed to kernel to tell it about the
+ *  hardware it's running on.  See linux/Documentation/arm/Setup
+ *  for more info.
+ *
+ * NOTE:
+ *  This file contains two ways to pass information from the boot
+ *  loader to the kernel. The old struct param_struct is deprecated,
+ *  but it will be kept in the kernel for 5 years from now
+ *  (2001). This will allow boot loaders to convert to the new struct
+ *  tag way.
+ */
+#ifndef __ASMARM_SETUP_H
+#define __ASMARM_SETUP_H
+
+/*
+ * Usage:
+ *  - do not go blindly adding fields, add them at the end
+ *  - when adding fields, don't rely on the address until
+ *    a patch from me has been released
+ *  - unused fields should be zero (for future expansion)
+ *  - this structure is relatively short-lived - only
+ *    guaranteed to contain useful data in setup_arch()
+ */
+#define COMMAND_LINE_SIZE 1024
+
+/* This is the old deprecated way to pass parameters to the kernel */
+struct param_struct {
+    union {
+	struct {
+	    unsigned long page_size;		/*  0 */
+	    unsigned long nr_pages;		/*  4 */
+	    unsigned long ramdisk_size;		/*  8 */
+	    unsigned long flags;		/* 12 */
+#define FLAG_READONLY	1
+#define FLAG_RDLOAD	4
+#define FLAG_RDPROMPT	8
+	    unsigned long rootdev;		/* 16 */
+	    unsigned long video_num_cols;	/* 20 */
+	    unsigned long video_num_rows;	/* 24 */
+	    unsigned long video_x;		/* 28 */
+	    unsigned long video_y;		/* 32 */
+	    unsigned long memc_control_reg;	/* 36 */
+	    unsigned char sounddefault;		/* 40 */
+	    unsigned char adfsdrives;		/* 41 */
+	    unsigned char bytes_per_char_h;	/* 42 */
+	    unsigned char bytes_per_char_v;	/* 43 */
+	    unsigned long pages_in_bank[4];	/* 44 */
+	    unsigned long pages_in_vram;	/* 60 */
+	    unsigned long initrd_start;		/* 64 */
+	    unsigned long initrd_size;		/* 68 */
+	    unsigned long rd_start;		/* 72 */
+	    unsigned long system_rev;		/* 76 */
+	    unsigned long system_serial_low;	/* 80 */
+	    unsigned long system_serial_high;	/* 84 */
+	    unsigned long mem_fclk_21285;       /* 88 */
+	} s;
+	char unused[256];
+    } u1;
+    union {
+	char paths[8][128];
+	struct {
+	    unsigned long magic;
+	    char n[1024 - sizeof(unsigned long)];
+	} s;
+    } u2;
+    char commandline[COMMAND_LINE_SIZE];
+};
+
+
+/*
+ * The new way of passing information: a list of tagged entries
+ */
+
+/* The list ends with an ATAG_NONE node. */
+#define ATAG_NONE	0x00000000
+
+struct tag_header {
+	u32 size;
+	u32 tag;
+};
+
+/* The list must start with an ATAG_CORE node */
+#define ATAG_CORE	0x54410001
+
+struct tag_core {
+	u32 flags;		/* bit 0 = read-only */
+	u32 pagesize;
+	u32 rootdev;
+};
+
+/* it is allowed to have multiple ATAG_MEM nodes */
+#define ATAG_MEM	0x54410002
+
+struct tag_mem32 {
+	u32	size;
+	u32	start;	/* physical start address */
+};
+
+/* VGA text type displays */
+#define ATAG_VIDEOTEXT	0x54410003
+
+struct tag_videotext {
+	u8		x;
+	u8		y;
+	u16		video_page;
+	u8		video_mode;
+	u8		video_cols;
+	u16		video_ega_bx;
+	u8		video_lines;
+	u8		video_isvga;
+	u16		video_points;
+};
+
+/* describes how the ramdisk will be used in kernel */
+#define ATAG_RAMDISK	0x54410004
+
+struct tag_ramdisk {
+	u32 flags;	/* bit 0 = load, bit 1 = prompt */
+	u32 size;	/* decompressed ramdisk size in _kilo_ bytes */
+	u32 start;	/* starting block of floppy-based RAM disk image */
+};
+
+/* describes where the compressed ramdisk image lives (virtual address) */
+/*
+ * this one accidentally used virtual addresses - as such,
+ * its depreciated.
+ */
+#define ATAG_INITRD	0x54410005
+
+/* describes where the compressed ramdisk image lives (physical address) */
+#define ATAG_INITRD2	0x54420005
+
+struct tag_initrd {
+	u32 start;	/* physical start address */
+	u32 size;	/* size of compressed ramdisk image in bytes */
+};
+
+/* board serial number. "64 bits should be enough for everybody" */
+#define ATAG_SERIAL	0x54410006
+
+struct tag_serialnr {
+	u32 low;
+	u32 high;
+};
+
+/* board revision */
+#define ATAG_REVISION	0x54410007
+
+struct tag_revision {
+	u32 rev;
+};
+
+/* initial values for vesafb-type framebuffers. see struct screen_info
+ * in include/linux/tty.h
+ */
+#define ATAG_VIDEOLFB	0x54410008
+
+struct tag_videolfb {
+	u16		lfb_width;
+	u16		lfb_height;
+	u16		lfb_depth;
+	u16		lfb_linelength;
+	u32		lfb_base;
+	u32		lfb_size;
+	u8		red_size;
+	u8		red_pos;
+	u8		green_size;
+	u8		green_pos;
+	u8		blue_size;
+	u8		blue_pos;
+	u8		rsvd_size;
+	u8		rsvd_pos;
+};
+
+/* command line: \0 terminated string */
+#define ATAG_CMDLINE	0x54410009
+
+struct tag_cmdline {
+	char	cmdline[1];	/* this is the minimum size */
+};
+
+/* acorn RiscPC specific information */
+#define ATAG_ACORN	0x41000101
+
+struct tag_acorn {
+	u32 memc_control_reg;
+	u32 vram_pages;
+	u8 sounddefault;
+	u8 adfsdrives;
+};
+
+/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
+#define ATAG_MEMCLK	0x41000402
+
+struct tag_memclk {
+	u32 fmemclk;
+};
+
+struct tag {
+	struct tag_header hdr;
+	union {
+		struct tag_core		core;
+		struct tag_mem32	mem;
+		struct tag_videotext	videotext;
+		struct tag_ramdisk	ramdisk;
+		struct tag_initrd	initrd;
+		struct tag_serialnr	serialnr;
+		struct tag_revision	revision;
+		struct tag_videolfb	videolfb;
+		struct tag_cmdline	cmdline;
+
+		/*
+		 * Acorn specific
+		 */
+		struct tag_acorn	acorn;
+
+		/*
+		 * DC21285 specific
+		 */
+		struct tag_memclk	memclk;
+	} u;
+};
+
+struct tagtable {
+	u32 tag;
+	int (*parse)(const struct tag *);
+};
+
+#define __tag __attribute__((unused, __section__(".taglist")))
+#define __tagtable(tag, fn) \
+static struct tagtable __tagtable_##fn __tag = { tag, fn }
+
+#define tag_member_present(tag,member)				\
+	((unsigned long)(&((struct tag *)0L)->member + 1)	\
+		<= (tag)->hdr.size * 4)
+
+#define tag_next(t)	((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_size(type)	((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
+
+#define for_each_tag(t,base)		\
+	for (t = base; t->hdr.size; t = tag_next(t))
+
+/*
+ * Memory map description
+ */
+#define NR_BANKS 8
+
+struct meminfo {
+	int nr_banks;
+	unsigned long end;
+	struct {
+		unsigned long start;
+		unsigned long size;
+		int           node;
+	} bank[NR_BANKS];
+};
+
+extern struct meminfo meminfo;
+
+#endif
+
+/*
+ * Board specified tags
+ */
+void setup_board_tags(struct tag **in_params);
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/spl.h b/qemu/roms/u-boot/arch/arm/include/asm/spl.h
new file mode 100644
index 000000000..90e5a9dde
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/spl.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_SPL_H_
+#define	_ASM_SPL_H_
+
+/* Platform-specific defines */
+#include <asm/arch/spl.h>
+
+/* Linker symbols. */
+extern char __bss_start[], __bss_end[];
+
+extern gd_t gdata;
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/string.h b/qemu/roms/u-boot/arch/arm/include/asm/string.h
new file mode 100644
index 000000000..c6dfb254b
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/string.h
@@ -0,0 +1,53 @@
+#ifndef __ASM_ARM_STRING_H
+#define __ASM_ARM_STRING_H
+
+#include <config.h>
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char * s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char * strchr(const char * s, int c);
+
+#ifdef CONFIG_USE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMCPY
+#endif
+extern void * memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#ifdef CONFIG_USE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMSET
+#endif
+extern void * memset(void *, int, __kernel_size_t);
+
+#if 0
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p,v,n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p),(n));			\
+			else						\
+				memset((p),(v),(n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/system.h b/qemu/roms/u-boot/arch/arm/include/asm/system.h
new file mode 100644
index 000000000..74ee9a4df
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/system.h
@@ -0,0 +1,220 @@
+#ifndef __ASM_ARM_SYSTEM_H
+#define __ASM_ARM_SYSTEM_H
+
+#ifdef CONFIG_ARM64
+
+/*
+ * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
+ */
+#define CR_M		(1 << 0)	/* MMU enable			*/
+#define CR_A		(1 << 1)	/* Alignment abort enable	*/
+#define CR_C		(1 << 2)	/* Dcache enable		*/
+#define CR_SA		(1 << 3)	/* Stack Alignment Check Enable	*/
+#define CR_I		(1 << 12)	/* Icache enable		*/
+#define CR_WXN		(1 << 19)	/* Write Permision Imply XN	*/
+#define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/
+
+#define PGTABLE_SIZE	(0x10000)
+
+#ifndef __ASSEMBLY__
+
+#define isb()				\
+	({asm volatile(			\
+	"isb" : : : "memory");		\
+	})
+
+#define wfi()				\
+	({asm volatile(			\
+	"wfi" : : : "memory");		\
+	})
+
+static inline unsigned int current_el(void)
+{
+	unsigned int el;
+	asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
+	return el >> 2;
+}
+
+static inline unsigned int get_sctlr(void)
+{
+	unsigned int el, val;
+
+	el = current_el();
+	if (el == 1)
+		asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
+	else if (el == 2)
+		asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
+	else
+		asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
+
+	return val;
+}
+
+static inline void set_sctlr(unsigned int val)
+{
+	unsigned int el;
+
+	el = current_el();
+	if (el == 1)
+		asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
+	else if (el == 2)
+		asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
+	else
+		asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
+
+	asm volatile("isb");
+}
+
+void __asm_flush_dcache_all(void);
+void __asm_invalidate_dcache_all(void);
+void __asm_flush_dcache_range(u64 start, u64 end);
+void __asm_invalidate_tlb_all(void);
+void __asm_invalidate_icache_all(void);
+
+void armv8_switch_to_el2(void);
+void armv8_switch_to_el1(void);
+void gic_init(void);
+void gic_send_sgi(unsigned long sgino);
+void wait_for_wakeup(void);
+void smp_kick_all_cpus(void);
+
+#endif	/* __ASSEMBLY__ */
+
+#else /* CONFIG_ARM64 */
+
+#ifdef __KERNEL__
+
+#define CPU_ARCH_UNKNOWN	0
+#define CPU_ARCH_ARMv3		1
+#define CPU_ARCH_ARMv4		2
+#define CPU_ARCH_ARMv4T		3
+#define CPU_ARCH_ARMv5		4
+#define CPU_ARCH_ARMv5T		5
+#define CPU_ARCH_ARMv5TE	6
+#define CPU_ARCH_ARMv5TEJ	7
+#define CPU_ARCH_ARMv6		8
+#define CPU_ARCH_ARMv7		9
+
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M	(1 << 0)	/* MMU enable				*/
+#define CR_A	(1 << 1)	/* Alignment abort enable		*/
+#define CR_C	(1 << 2)	/* Dcache enable			*/
+#define CR_W	(1 << 3)	/* Write buffer enable			*/
+#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
+#define CR_D	(1 << 5)	/* 32-bit data address range		*/
+#define CR_L	(1 << 6)	/* Implementation defined		*/
+#define CR_B	(1 << 7)	/* Big endian				*/
+#define CR_S	(1 << 8)	/* System MMU protection		*/
+#define CR_R	(1 << 9)	/* ROM MMU protection			*/
+#define CR_F	(1 << 10)	/* Implementation defined		*/
+#define CR_Z	(1 << 11)	/* Implementation defined		*/
+#define CR_I	(1 << 12)	/* Icache enable			*/
+#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
+#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
+#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
+#define CR_DT	(1 << 16)
+#define CR_IT	(1 << 18)
+#define CR_ST	(1 << 19)
+#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
+#define CR_U	(1 << 22)	/* Unaligned access operation		*/
+#define CR_XP	(1 << 23)	/* Extended page tables			*/
+#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
+#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
+#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
+#define CR_AFE	(1 << 29)	/* Access flag enable			*/
+#define CR_TE	(1 << 30)	/* Thumb exception enable		*/
+
+#define PGTABLE_SIZE		(4096 * 4)
+
+/*
+ * This is used to ensure the compiler did actually allocate the register we
+ * asked it for some inline assembly sequences.  Apparently we can't trust
+ * the compiler from one version to another so a bit of paranoia won't hurt.
+ * This string is meant to be concatenated with the inline asm string and
+ * will cause compilation to stop on mismatch.
+ * (for details, see gcc PR 15089)
+ */
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+#ifndef __ASSEMBLY__
+
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
+
+#ifdef __ARM_ARCH_7A__
+#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
+#else
+#define wfi()
+#endif
+
+static inline unsigned int get_cr(void)
+{
+	unsigned int val;
+	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
+	return val;
+}
+
+static inline void set_cr(unsigned int val)
+{
+	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
+	  : : "r" (val) : "cc");
+	isb();
+}
+
+static inline unsigned int get_dacr(void)
+{
+	unsigned int val;
+	asm("mrc p15, 0, %0, c3, c0, 0	@ get DACR" : "=r" (val) : : "cc");
+	return val;
+}
+
+static inline void set_dacr(unsigned int val)
+{
+	asm volatile("mcr p15, 0, %0, c3, c0, 0	@ set DACR"
+	  : : "r" (val) : "cc");
+	isb();
+}
+
+/* options available for data cache on each page */
+enum dcache_option {
+	DCACHE_OFF = 0x12,
+	DCACHE_WRITETHROUGH = 0x1a,
+	DCACHE_WRITEBACK = 0x1e,
+};
+
+/* Size of an MMU section */
+enum {
+	MMU_SECTION_SHIFT	= 20,
+	MMU_SECTION_SIZE	= 1 << MMU_SECTION_SHIFT,
+};
+
+/**
+ * Change the cache settings for a region.
+ *
+ * \param start		start address of memory region to change
+ * \param size		size of memory region to change
+ * \param option	dcache option to select
+ */
+void mmu_set_region_dcache_behaviour(u32 start, int size,
+				     enum dcache_option option);
+
+/**
+ * Register an update to the page tables, and flush the TLB
+ *
+ * \param start		start address of update in page table
+ * \param stop		stop address of update in page table
+ */
+void mmu_page_table_flush(unsigned long start, unsigned long stop);
+
+#endif /* __ASSEMBLY__ */
+
+#define arch_align_stack(x) (x)
+
+#endif /* __KERNEL__ */
+
+#endif /* CONFIG_ARM64 */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/types.h b/qemu/roms/u-boot/arch/arm/include/asm/types.h
new file mode 100644
index 000000000..2326420a7
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/types.h
@@ -0,0 +1,57 @@
+#ifndef __ASM_ARM_TYPES_H
+#define __ASM_ARM_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#ifdef	CONFIG_ARM64
+#define BITS_PER_LONG 64
+#else	/* CONFIG_ARM64 */
+#define BITS_PER_LONG 32
+#endif	/* CONFIG_ARM64 */
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/u-boot-arm.h b/qemu/roms/u-boot/arch/arm/include/asm/u-boot-arm.h
new file mode 100644
index 000000000..b16694c72
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/u-boot-arm.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _U_BOOT_ARM_H_
+#define _U_BOOT_ARM_H_	1
+
+/* for the following variables, see start.S */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+extern ulong _datarel_start_ofs;
+extern ulong _datarelrolocal_start_ofs;
+extern ulong _datarellocal_start_ofs;
+extern ulong _datarelro_start_ofs;
+extern ulong IRQ_STACK_START_IN;	/* 8 bytes in IRQ stack */
+
+/* cpu/.../cpu.c */
+int	cpu_init(void);
+int	cleanup_before_linux(void);
+
+/* Set up ARMv7 MMU, caches and TLBs */
+void	cpu_init_cp15(void);
+
+/* cpu/.../arch/cpu.c */
+int	arch_cpu_init(void);
+int	arch_misc_init(void);
+int	arch_early_init_r(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init (void);
+void	dram_init_banksize (void);
+
+/* cpu/.../interrupt.c */
+int	arch_interrupt_init	(void);
+void	reset_timer_masked	(void);
+ulong	get_timer_masked	(void);
+void	udelay_masked		(unsigned long usec);
+
+#endif	/* _U_BOOT_ARM_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/u-boot.h b/qemu/roms/u-boot/arch/arm/include/asm/u-boot.h
new file mode 100644
index 000000000..43cc49468
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/u-boot.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#ifdef CONFIG_SYS_GENERIC_BOARD
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#else
+
+#ifndef __ASSEMBLY__
+typedef struct bd_info {
+    ulong	        bi_arch_number;	/* unique id for this board */
+    ulong	        bi_boot_params;	/* where this board expects params */
+	unsigned long	bi_arm_freq; /* arm frequency */
+	unsigned long	bi_dsp_freq; /* dsp core frequency */
+	unsigned long	bi_ddr_freq; /* ddr frequency */
+    struct				/* RAM configuration */
+    {
+	ulong start;
+	ulong size;
+    }			bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+#endif
+
+#endif /* !CONFIG_SYS_GENERIC_BOARD */
+
+/* For image.h:image_check_target_arch() */
+#ifndef CONFIG_ARM64
+#define IH_ARCH_DEFAULT IH_ARCH_ARM
+#else
+#define IH_ARCH_DEFAULT IH_ARCH_ARM64
+#endif
+
+#endif	/* _U_BOOT_H_ */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/unaligned.h b/qemu/roms/u-boot/arch/arm/include/asm/unaligned.h
new file mode 100644
index 000000000..0a228fb8e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/unaligned.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_UNALIGNED_H
+#define _ASM_ARM_UNALIGNED_H
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+/*
+ * Select endianness
+ */
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define get_unaligned	__get_unaligned_le
+#define put_unaligned	__put_unaligned_le
+#else
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+#endif
+
+#endif /* _ASM_ARM_UNALIGNED_H */
diff --git a/qemu/roms/u-boot/arch/arm/include/asm/utils.h b/qemu/roms/u-boot/arch/arm/include/asm/utils.h
new file mode 100644
index 000000000..1b3f1a0c2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/include/asm/utils.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _UTILS_H_
+#define _UTILS_H_
+
+static inline s32 log_2_n_round_up(u32 n)
+{
+	s32 log2n = -1;
+	u32 temp = n;
+
+	while (temp) {
+		log2n++;
+		temp >>= 1;
+	}
+
+	if (n & (n - 1))
+		return log2n + 1; /* not power of 2 - round up */
+	else
+		return log2n; /* power of 2 */
+}
+
+static inline s32 log_2_n_round_down(u32 n)
+{
+	s32 log2n = -1;
+	u32 temp = n;
+
+	while (temp) {
+		log2n++;
+		temp >>= 1;
+	}
+
+	return log2n;
+}
+
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/lib/Makefile b/qemu/roms/u-boot/arch/arm/lib/Makefile
new file mode 100644
index 000000000..e035d6acc
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
+			_lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o
+
+ifdef CONFIG_ARM64
+obj-y	+= crt0_64.o
+else
+obj-y	+= crt0.o
+endif
+
+ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_ARM64
+obj-y	+= relocate_64.o
+else
+obj-y	+= relocate.o
+endif
+ifndef CONFIG_SYS_GENERIC_BOARD
+obj-y	+= board.o
+endif
+
+obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
+obj-$(CONFIG_USE_ARCH_MEMSET) += memset.o
+obj-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
+else
+obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
+endif
+
+obj-y	+= sections.o
+ifdef CONFIG_ARM64
+obj-y	+= gic_64.o
+obj-y	+= interrupts_64.o
+else
+obj-y	+= interrupts.o
+endif
+obj-y	+= reset.o
+
+obj-y	+= cache.o
+ifndef CONFIG_ARM64
+obj-y	+= cache-cp15.o
+endif
+
+# For EABI conformant tool chains, provide eabi_compat()
+ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
+extra-y	+= eabi_compat.o
+endif
diff --git a/qemu/roms/u-boot/arch/arm/lib/_ashldi3.S b/qemu/roms/u-boot/arch/arm/lib/_ashldi3.S
new file mode 100644
index 000000000..2c26f84ac
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/_ashldi3.S
@@ -0,0 +1,26 @@
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+.globl __ashldi3
+.globl	__aeabi_llsl
+__ashldi3:
+__aeabi_llsl:
+
+	subs	r3, r2, #32
+	rsb	ip, r2, #32
+	movmi	ah, ah, lsl r2
+	movpl	ah, al, lsl r3
+	orrmi	ah, ah, al, lsr ip
+	mov	al, al, lsl r2
+	mov	pc, lr
diff --git a/qemu/roms/u-boot/arch/arm/lib/_ashrdi3.S b/qemu/roms/u-boot/arch/arm/lib/_ashrdi3.S
new file mode 100644
index 000000000..4d93c8a5e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/_ashrdi3.S
@@ -0,0 +1,26 @@
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+.globl __ashrdi3
+.globl __aeabi_lasr
+__ashrdi3:
+__aeabi_lasr:
+
+	subs	r3, r2, #32
+	rsb	ip, r2, #32
+	movmi	al, al, lsr r2
+	movpl	al, ah, asr r3
+	orrmi	al, al, ah, lsl ip
+	mov	ah, ah, asr r2
+	mov	pc, lr
diff --git a/qemu/roms/u-boot/arch/arm/lib/_divsi3.S b/qemu/roms/u-boot/arch/arm/lib/_divsi3.S
new file mode 100644
index 000000000..601549304
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/_divsi3.S
@@ -0,0 +1,141 @@
+.macro ARM_DIV_BODY dividend, divisor, result, curbit
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\curbit, \divisor
+	clz	\result, \dividend
+	sub	\result, \curbit, \result
+	mov	\curbit, #1
+	mov	\divisor, \divisor, lsl \result
+	mov	\curbit, \curbit, lsl \result
+	mov	\result, #0
+
+#else
+
+	@ Initially shift the divisor left 3 bits if possible,
+	@ set curbit accordingly.  This allows for curbit to be located
+	@ at the left end of each 4 bit nibbles in the division loop
+	@ to save one loop in most cases.
+	tst	\divisor, #0xe0000000
+	moveq	\divisor, \divisor, lsl #3
+	moveq	\curbit, #8
+	movne	\curbit, #1
+
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is
+	@ larger than the dividend.
+1:	cmp	\divisor, #0x10000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #4
+	movlo	\curbit, \curbit, lsl #4
+	blo	1b
+
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+1:	cmp	\divisor, #0x80000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #1
+	movlo	\curbit, \curbit, lsl #1
+	blo	1b
+
+	mov	\result, #0
+
+#endif
+
+	@ Division loop
+1:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	orrhs	\result,   \result,   \curbit
+	cmp	\dividend, \divisor,  lsr #1
+	subhs	\dividend, \dividend, \divisor, lsr #1
+	orrhs	\result,   \result,   \curbit,  lsr #1
+	cmp	\dividend, \divisor,  lsr #2
+	subhs	\dividend, \dividend, \divisor, lsr #2
+	orrhs	\result,   \result,   \curbit,  lsr #2
+	cmp	\dividend, \divisor,  lsr #3
+	subhs	\dividend, \dividend, \divisor, lsr #3
+	orrhs	\result,   \result,   \curbit,  lsr #3
+	cmp	\dividend, #0			@ Early termination?
+	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
+	movne	\divisor,  \divisor, lsr #4
+	bne	1b
+
+.endm
+
+.macro ARM_DIV2_ORDER divisor, order
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\order, \divisor
+	rsb	\order, \order, #31
+
+#else
+
+	cmp	\divisor, #(1 << 16)
+	movhs	\divisor, \divisor, lsr #16
+	movhs	\order, #16
+	movlo	\order, #0
+
+	cmp	\divisor, #(1 << 8)
+	movhs	\divisor, \divisor, lsr #8
+	addhs	\order, \order, #8
+
+	cmp	\divisor, #(1 << 4)
+	movhs	\divisor, \divisor, lsr #4
+	addhs	\order, \order, #4
+
+	cmp	\divisor, #(1 << 2)
+	addhi	\order, \order, #3
+	addls	\order, \order, \divisor, lsr #1
+
+#endif
+
+.endm
+
+	.align	5
+.globl __divsi3
+.globl __aeabi_idiv
+__divsi3:
+__aeabi_idiv:
+	cmp	r1, #0
+	eor	ip, r0, r1			@ save the sign of the result.
+	beq	Ldiv0
+	rsbmi	r1, r1, #0			@ loops below use unsigned.
+	subs	r2, r1, #1			@ division by 1 or -1 ?
+	beq	10f
+	movs	r3, r0
+	rsbmi	r3, r0, #0			@ positive dividend value
+	cmp	r3, r1
+	bls	11f
+	tst	r1, r2				@ divisor is power of 2 ?
+	beq	12f
+
+	ARM_DIV_BODY r3, r1, r0, r2
+
+	cmp	ip, #0
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+10:	teq	ip, r0				@ same sign ?
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+11:	movlo	r0, #0
+	moveq	r0, ip, asr #31
+	orreq	r0, r0, #1
+	mov	pc, lr
+
+12:	ARM_DIV2_ORDER r1, r2
+
+	cmp	ip, #0
+	mov	r0, r3, lsr r2
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+Ldiv0:
+
+	str	lr, [sp, #-4]!
+	bl	__div0
+	mov	r0, #0			@ About as wrong as it could be.
+	ldr	pc, [sp], #4
diff --git a/qemu/roms/u-boot/arch/arm/lib/_lshrdi3.S b/qemu/roms/u-boot/arch/arm/lib/_lshrdi3.S
new file mode 100644
index 000000000..33296a0a9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/_lshrdi3.S
@@ -0,0 +1,26 @@
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifdef __ARMEB__
+#define al r1
+#define ah r0
+#else
+#define al r0
+#define ah r1
+#endif
+
+.globl __lshrdi3
+.globl __aeabi_llsr
+__lshrdi3:
+__aeabi_llsr:
+
+	subs	r3, r2, #32
+	rsb	ip, r2, #32
+	movmi	al, al, lsr r2
+	movpl	al, ah, lsr r3
+	orrmi	al, al, ah, lsl ip
+	mov	ah, ah, lsr r2
+	mov	pc, lr
diff --git a/qemu/roms/u-boot/arch/arm/lib/_modsi3.S b/qemu/roms/u-boot/arch/arm/lib/_modsi3.S
new file mode 100644
index 000000000..3d31a559f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/_modsi3.S
@@ -0,0 +1,98 @@
+.macro ARM_MOD_BODY dividend, divisor, order, spare
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\order, \divisor
+	clz	\spare, \dividend
+	sub	\order, \order, \spare
+	mov	\divisor, \divisor, lsl \order
+
+#else
+
+	mov	\order, #0
+
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is
+	@ larger than the dividend.
+1:	cmp	\divisor, #0x10000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #4
+	addlo	\order, \order, #4
+	blo	1b
+
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+1:	cmp	\divisor, #0x80000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #1
+	addlo	\order, \order, #1
+	blo	1b
+
+#endif
+
+	@ Perform all needed substractions to keep only the reminder.
+	@ Do comparisons in batch of 4 first.
+	subs	\order, \order, #3		@ yes, 3 is intended here
+	blt	2f
+
+1:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	cmp	\dividend, \divisor,  lsr #1
+	subhs	\dividend, \dividend, \divisor, lsr #1
+	cmp	\dividend, \divisor,  lsr #2
+	subhs	\dividend, \dividend, \divisor, lsr #2
+	cmp	\dividend, \divisor,  lsr #3
+	subhs	\dividend, \dividend, \divisor, lsr #3
+	cmp	\dividend, #1
+	mov	\divisor, \divisor, lsr #4
+	subges	\order, \order, #4
+	bge	1b
+
+	tst	\order, #3
+	teqne	\dividend, #0
+	beq	5f
+
+	@ Either 1, 2 or 3 comparison/substractions are left.
+2:	cmn	\order, #2
+	blt	4f
+	beq	3f
+	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	mov	\divisor,  \divisor,  lsr #1
+3:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	mov	\divisor,  \divisor,  lsr #1
+4:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+5:
+.endm
+
+	.align	5
+.globl __modsi3
+__modsi3:
+	cmp	r1, #0
+	beq	Ldiv0
+	rsbmi	r1, r1, #0			@ loops below use unsigned.
+	movs	ip, r0				@ preserve sign of dividend
+	rsbmi	r0, r0, #0			@ if negative make positive
+	subs	r2, r1, #1			@ compare divisor with 1
+	cmpne	r0, r1				@ compare dividend with divisor
+	moveq	r0, #0
+	tsthi	r1, r2				@ see if divisor is power of 2
+	andeq	r0, r0, r2
+	bls	10f
+
+	ARM_MOD_BODY r0, r1, r2, r3
+
+10:	cmp	ip, #0
+	rsbmi	r0, r0, #0
+	mov	pc, lr
+
+
+Ldiv0:
+
+	str	lr, [sp, #-4]!
+	bl	__div0
+	mov	r0, #0			@ About as wrong as it could be.
+	ldr	pc, [sp], #4
diff --git a/qemu/roms/u-boot/arch/arm/lib/_udivsi3.S b/qemu/roms/u-boot/arch/arm/lib/_udivsi3.S
new file mode 100644
index 000000000..130980261
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/_udivsi3.S
@@ -0,0 +1,93 @@
+/* # 1 "libgcc1.S" */
+@ libgcc1 routines for ARM cpu.
+@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
+dividend	.req	r0
+divisor		.req	r1
+result		.req	r2
+curbit		.req	r3
+/* ip		.req	r12	*/
+/* sp		.req	r13	*/
+/* lr		.req	r14	*/
+/* pc		.req	r15	*/
+	.text
+	.globl	 __udivsi3
+	.type	__udivsi3 ,function
+	.globl	__aeabi_uidiv
+	.type	__aeabi_uidiv ,function
+	.align	0
+ __udivsi3:
+ __aeabi_uidiv:
+	cmp	divisor, #0
+	beq	Ldiv0
+	mov	curbit, #1
+	mov	result, #0
+	cmp	dividend, divisor
+	bcc	Lgot_result
+Loop1:
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is
+	@ larger than the dividend.
+	cmp	divisor, #0x10000000
+	cmpcc	divisor, dividend
+	movcc	divisor, divisor, lsl #4
+	movcc	curbit, curbit, lsl #4
+	bcc	Loop1
+Lbignum:
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+	cmp	divisor, #0x80000000
+	cmpcc	divisor, dividend
+	movcc	divisor, divisor, lsl #1
+	movcc	curbit, curbit, lsl #1
+	bcc	Lbignum
+Loop3:
+	@ Test for possible subtractions, and note which bits
+	@ are done in the result.  On the final pass, this may subtract
+	@ too much from the dividend, but the result will be ok, since the
+	@ "bit" will have been shifted out at the bottom.
+	cmp	dividend, divisor
+	subcs	dividend, dividend, divisor
+	orrcs	result, result, curbit
+	cmp	dividend, divisor, lsr #1
+	subcs	dividend, dividend, divisor, lsr #1
+	orrcs	result, result, curbit, lsr #1
+	cmp	dividend, divisor, lsr #2
+	subcs	dividend, dividend, divisor, lsr #2
+	orrcs	result, result, curbit, lsr #2
+	cmp	dividend, divisor, lsr #3
+	subcs	dividend, dividend, divisor, lsr #3
+	orrcs	result, result, curbit, lsr #3
+	cmp	dividend, #0			@ Early termination?
+	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
+	movne	divisor, divisor, lsr #4
+	bne	Loop3
+Lgot_result:
+	mov	r0, result
+	mov	pc, lr
+Ldiv0:
+	str	lr, [sp, #-4]!
+	bl	 __div0       (PLT)
+	mov	r0, #0			@ about as wrong as it could be
+	ldmia	sp!, {pc}
+	.size  __udivsi3       , . -  __udivsi3
+
+.globl __aeabi_uidivmod
+__aeabi_uidivmod:
+
+	stmfd	sp!, {r0, r1, ip, lr}
+	bl	__aeabi_uidiv
+	ldmfd	sp!, {r1, r2, ip, lr}
+	mul	r3, r0, r2
+	sub	r1, r1, r3
+	mov	pc, lr
+
+.globl __aeabi_idivmod
+__aeabi_idivmod:
+
+	stmfd	sp!, {r0, r1, ip, lr}
+	bl	__aeabi_idiv
+	ldmfd	sp!, {r1, r2, ip, lr}
+	mul	r3, r0, r2
+	sub	r1, r1, r3
+	mov	pc, lr
diff --git a/qemu/roms/u-boot/arch/arm/lib/_umodsi3.S b/qemu/roms/u-boot/arch/arm/lib/_umodsi3.S
new file mode 100644
index 000000000..8465ef09d
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/_umodsi3.S
@@ -0,0 +1,88 @@
+/* # 1 "libgcc1.S" */
+@ libgcc1 routines for ARM cpu.
+@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
+/* # 145 "libgcc1.S" */
+dividend	.req	r0
+divisor		.req	r1
+overdone	.req	r2
+curbit		.req	r3
+/* ip		.req	r12	*/
+/* sp		.req	r13	*/
+/* lr		.req	r14	*/
+/* pc		.req	r15	*/
+	.text
+	.globl	 __umodsi3
+	.type  __umodsi3       ,function
+	.align 0
+ __umodsi3      :
+	cmp	divisor, #0
+	beq	Ldiv0
+	mov	curbit, #1
+	cmp	dividend, divisor
+	movcc	pc, lr
+Loop1:
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is
+	@ larger than the dividend.
+	cmp	divisor, #0x10000000
+	cmpcc	divisor, dividend
+	movcc	divisor, divisor, lsl #4
+	movcc	curbit, curbit, lsl #4
+	bcc	Loop1
+Lbignum:
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+	cmp	divisor, #0x80000000
+	cmpcc	divisor, dividend
+	movcc	divisor, divisor, lsl #1
+	movcc	curbit, curbit, lsl #1
+	bcc	Lbignum
+Loop3:
+	@ Test for possible subtractions.  On the final pass, this may
+	@ subtract too much from the dividend, so keep track of which
+	@ subtractions are done, we can fix them up afterwards...
+	mov	overdone, #0
+	cmp	dividend, divisor
+	subcs	dividend, dividend, divisor
+	cmp	dividend, divisor, lsr #1
+	subcs	dividend, dividend, divisor, lsr #1
+	orrcs	overdone, overdone, curbit, ror #1
+	cmp	dividend, divisor, lsr #2
+	subcs	dividend, dividend, divisor, lsr #2
+	orrcs	overdone, overdone, curbit, ror #2
+	cmp	dividend, divisor, lsr #3
+	subcs	dividend, dividend, divisor, lsr #3
+	orrcs	overdone, overdone, curbit, ror #3
+	mov	ip, curbit
+	cmp	dividend, #0			@ Early termination?
+	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
+	movne	divisor, divisor, lsr #4
+	bne	Loop3
+	@ Any subtractions that we should not have done will be recorded in
+	@ the top three bits of "overdone".  Exactly which were not needed
+	@ are governed by the position of the bit, stored in ip.
+	@ If we terminated early, because dividend became zero,
+	@ then none of the below will match, since the bit in ip will not be
+	@ in the bottom nibble.
+	ands	overdone, overdone, #0xe0000000
+	moveq	pc, lr				@ No fixups needed
+	tst	overdone, ip, ror #3
+	addne	dividend, dividend, divisor, lsr #3
+	tst	overdone, ip, ror #2
+	addne	dividend, dividend, divisor, lsr #2
+	tst	overdone, ip, ror #1
+	addne	dividend, dividend, divisor, lsr #1
+	mov	pc, lr
+Ldiv0:
+	str	lr, [sp, #-4]!
+	bl	 __div0       (PLT)
+	mov	r0, #0			@ about as wrong as it could be
+	ldmia	sp!, {pc}
+	.size  __umodsi3       , . -  __umodsi3
+/* # 320 "libgcc1.S" */
+/* # 421 "libgcc1.S" */
+/* # 433 "libgcc1.S" */
+/* # 456 "libgcc1.S" */
+/* # 500 "libgcc1.S" */
+/* # 580 "libgcc1.S" */
diff --git a/qemu/roms/u-boot/arch/arm/lib/asm-offsets.c b/qemu/roms/u-boot/arch/arm/lib/asm-offsets.c
new file mode 100644
index 000000000..b0c26e5d6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/asm-offsets.c
@@ -0,0 +1,248 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/kbuild.h>
+
+#if defined(CONFIG_MB86R0x)
+#include <asm/arch/mb86r0x.h>
+#endif
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
+	|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#include <asm/arch/imx-regs.h>
+#endif
+
+int main(void)
+{
+	/*
+	 * TODO : Check if each entry in this file is really necessary.
+	 *   - struct mb86r0x_ddr2
+	 *   - struct mb86r0x_memc
+	 *   - struct esdramc_regs
+	 *   - struct max_regs
+	 *   - struct aips_regs
+	 *   - struct aipi_regs
+	 *   - struct clkctl
+	 *   - struct dpll
+	 * are used only for generating asm-offsets.h.
+	 * It means their offset addresses are referenced only from assembly
+	 * code. Is it better to define the macros directly in headers?
+	 */
+
+#if defined(CONFIG_MB86R0x)
+	/* ddr2 controller */
+	DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
+	DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
+	DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
+	DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
+	DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
+	DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
+	DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
+	DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
+	DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
+	DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
+	DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
+	DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
+	DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
+	DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
+	DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
+
+	/* clock reset generator */
+	DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
+	DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
+	DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
+	DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
+	DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
+	DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
+
+	/* chip control module */
+	DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
+
+	/* external bus interface */
+	DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
+	DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
+	DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
+	DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
+	DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
+	DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
+	DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
+	DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
+	DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
+#endif
+
+#if defined(CONFIG_MX25)
+	/* Clock Control Module */
+	DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
+	DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
+	DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
+	DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
+	DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
+	DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
+
+	/* Enhanced SDRAM Controller */
+	DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
+	DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
+	DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
+
+	/* Multi-Layer AHB Crossbar Switch */
+	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+
+	/* AHB <-> IP-Bus Interface */
+	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+#endif
+
+#if defined(CONFIG_MX27)
+	DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
+	DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
+	DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
+	DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
+
+	DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
+	DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
+	DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
+	DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
+	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
+
+	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+	DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
+	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+
+	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
+		offsetof(struct system_control_regs, gpcr));
+	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
+		offsetof(struct system_control_regs, fmcr));
+#endif
+
+#if defined(CONFIG_MX35)
+	/* Round up to make sure size gives nice stack alignment */
+	DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
+	DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
+	DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
+	DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
+	DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
+	DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
+	DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
+	DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
+	DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
+	DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
+	DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
+	DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
+	DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
+	DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
+	DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
+
+	/* Multi-Layer AHB Crossbar Switch */
+	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+	DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
+
+	/* AHB <-> IP-Bus Interface */
+	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+	DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
+	DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
+	DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
+	DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
+	DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
+	DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
+	DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
+	DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
+	DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+	/* Round up to make sure size gives nice stack alignment */
+	DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
+	DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
+	DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
+	DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
+	DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
+	DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
+	DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
+	DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
+	DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
+	DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
+	DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
+	DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
+	DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
+	DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
+	DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
+	DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
+	DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
+	DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
+	DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
+	DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
+	DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
+	DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
+	DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
+	DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
+	DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
+	DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
+	DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
+	DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
+	DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
+	DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
+	DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
+	DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
+	DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
+	DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
+#if defined(CONFIG_MX53)
+	DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
+#endif
+
+	/* DPLL */
+	DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
+	DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
+	DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
+	DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
+	DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
+	DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
+	DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
+	DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
+#endif
+
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/lib/board.c b/qemu/roms/u-boot/arch/arm/lib/board.c
new file mode 100644
index 000000000..9b473b5ea
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/board.c
@@ -0,0 +1,702 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * To match the U-Boot user interface on ARM platforms to the U-Boot
+ * standard (as on PPC platforms), some messages with debug character
+ * are removed from the default U-Boot build.
+ *
+ * Define DEBUG here if you want additional info as shown below
+ * printed upon startup:
+ *
+ * U-Boot code: 00F00000 -> 00F3C774  BSS: -> 00FC3274
+ * IRQ Stack: 00ebff7c
+ * FIQ Stack: 00ebef7c
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <libfdt.h>
+#include <fdtdec.h>
+#include <post.h>
+#include <logbuff.h>
+#include <asm/sections.h>
+
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ulong monitor_flash_len;
+
+#ifdef CONFIG_HAS_DATAFLASH
+extern int  AT91F_DataflashInit(void);
+extern void dataflash_print_info(void);
+#endif
+
+#if defined(CONFIG_HARD_I2C) || \
+	defined(CONFIG_SYS_I2C)
+#include <i2c.h>
+#endif
+
+/************************************************************************
+ * Coloured LED functionality
+ ************************************************************************
+ * May be supplied by boards if desired
+ */
+inline void __coloured_LED_init(void) {}
+void coloured_LED_init(void)
+	__attribute__((weak, alias("__coloured_LED_init")));
+inline void __red_led_on(void) {}
+void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
+inline void __red_led_off(void) {}
+void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
+inline void __green_led_on(void) {}
+void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
+inline void __green_led_off(void) {}
+void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
+inline void __yellow_led_on(void) {}
+void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
+inline void __yellow_led_off(void) {}
+void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
+inline void __blue_led_on(void) {}
+void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
+inline void __blue_led_off(void) {}
+void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
+
+/*
+ ************************************************************************
+ * Init Utilities							*
+ ************************************************************************
+ * Some of this code should be moved into the core functions,
+ * or dropped completely,
+ * but let's get it working (again) first...
+ */
+
+#if defined(CONFIG_ARM_DCC) && !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 115200
+#endif
+
+static int init_baudrate(void)
+{
+	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
+	return 0;
+}
+
+static int display_banner(void)
+{
+	printf("\n\n%s\n\n", version_string);
+	debug("U-Boot code: %08lX -> %08lX  BSS: -> %08lX\n",
+	       (ulong)&_start,
+	       (ulong)&__bss_start, (ulong)&__bss_end);
+#ifdef CONFIG_MODEM_SUPPORT
+	debug("Modem Support enabled\n");
+#endif
+#ifdef CONFIG_USE_IRQ
+	debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
+	debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
+#endif
+
+	return (0);
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+	int i;
+
+#ifdef DEBUG
+	puts("RAM Configuration:\n");
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+		print_size(gd->bd->bi_dram[i].size, "\n");
+	}
+#else
+	ulong size = 0;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		size += gd->bd->bi_dram[i].size;
+
+	puts("DRAM:  ");
+	print_size(size, "\n");
+#endif
+
+	return (0);
+}
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
+static int init_func_i2c(void)
+{
+	puts("I2C:   ");
+#ifdef CONFIG_SYS_I2C
+	i2c_init_all();
+#else
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+	puts("ready\n");
+	return (0);
+}
+#endif
+
+#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
+#include <pci.h>
+static int arm_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t) (void);
+
+void __dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size =  gd->ram_size;
+}
+void dram_init_banksize(void)
+	__attribute__((weak, alias("__dram_init_banksize")));
+
+int __arch_cpu_init(void)
+{
+	return 0;
+}
+int arch_cpu_init(void)
+	__attribute__((weak, alias("__arch_cpu_init")));
+
+int __power_init_board(void)
+{
+	return 0;
+}
+int power_init_board(void)
+	__attribute__((weak, alias("__power_init_board")));
+
+	/* Record the board_init_f() bootstage (after arch_cpu_init()) */
+static int mark_bootstage(void)
+{
+	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
+
+	return 0;
+}
+
+init_fnc_t *init_sequence[] = {
+	arch_cpu_init,		/* basic arch cpu dependent setup */
+	mark_bootstage,
+#ifdef CONFIG_OF_CONTROL
+	fdtdec_check_fdt,
+#endif
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+	board_early_init_f,
+#endif
+	timer_init,		/* initialize timer */
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+	board_postclk_init,
+#endif
+#ifdef CONFIG_FSL_ESDHC
+	get_clocks,
+#endif
+	env_init,		/* initialize environment */
+	init_baudrate,		/* initialze baudrate settings */
+	serial_init,		/* serial communications setup */
+	console_init_f,		/* stage 1 init of console */
+	display_banner,		/* say that we are here */
+	print_cpuinfo,		/* display cpu info (and speed) */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+	checkboard,		/* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
+	init_func_i2c,
+#endif
+	dram_init,		/* configure available RAM banks */
+	NULL,
+};
+
+void board_init_f(ulong bootflag)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+	gd_t *id;
+	ulong addr, addr_sp;
+#ifdef CONFIG_PRAM
+	ulong reg;
+#endif
+	void *new_fdt = NULL;
+	size_t fdt_size = 0;
+
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	gd->mon_len = (ulong)&__bss_end - (ulong)_start;
+#ifdef CONFIG_OF_EMBED
+	/* Get a pointer to the FDT */
+	gd->fdt_blob = __dtb_db_begin;
+#elif defined CONFIG_OF_SEPARATE
+	/* FDT is at end of image */
+	gd->fdt_blob = &_end;
+#endif
+	/* Allow the early environment to override the fdt address */
+	gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
+						(uintptr_t)gd->fdt_blob);
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		if ((*init_fnc_ptr)() != 0) {
+			hang ();
+		}
+	}
+
+#ifdef CONFIG_OF_CONTROL
+	/* For now, put this check after the console is ready */
+	if (fdtdec_prepare_fdt()) {
+		panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+			"doc/README.fdt-control");
+	}
+#endif
+
+	debug("monitor len: %08lX\n", gd->mon_len);
+	/*
+	 * Ram is setup, size stored in gd !!
+	 */
+	debug("ramsize: %08lX\n", gd->ram_size);
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+	/*
+	 * Subtract specified amount of memory to hide so that it won't
+	 * get "touched" at all by U-Boot. By fixing up gd->ram_size
+	 * the Linux kernel should now get passed the now "corrected"
+	 * memory size and won't touch it either. This should work
+	 * for arch/ppc and arch/powerpc. Only Linux board ports in
+	 * arch/powerpc with bootwrapper support, that recalculate the
+	 * memory size from the SDRAM controller setup will have to
+	 * get fixed.
+	 */
+	gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+
+	addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
+
+#ifdef CONFIG_LOGBUFFER
+#ifndef CONFIG_ALT_LB_ADDR
+	/* reserve kernel log buffer */
+	addr -= (LOGBUFF_RESERVE);
+	debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
+		addr);
+#endif
+#endif
+
+#ifdef CONFIG_PRAM
+	/*
+	 * reserve protected RAM
+	 */
+	reg = getenv_ulong("pram", 10, CONFIG_PRAM);
+	addr -= (reg << 10);		/* size is in kB */
+	debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
+#endif /* CONFIG_PRAM */
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+	/* reserve TLB table */
+	gd->arch.tlb_size = PGTABLE_SIZE;
+	addr -= gd->arch.tlb_size;
+
+	/* round down to next 64 kB limit */
+	addr &= ~(0x10000 - 1);
+
+	gd->arch.tlb_addr = addr;
+	debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);
+#endif
+
+	/* round down to next 4 kB limit */
+	addr &= ~(4096 - 1);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+#ifdef CONFIG_LCD
+#ifdef CONFIG_FB_ADDR
+	gd->fb_base = CONFIG_FB_ADDR;
+#else
+	/* reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem(addr);
+	gd->fb_base = addr;
+#endif /* CONFIG_FB_ADDR */
+#endif /* CONFIG_LCD */
+
+	/*
+	 * reserve memory for U-Boot code, data & bss
+	 * round down to next 4 kB limit
+	 */
+	addr -= gd->mon_len;
+	addr &= ~(4096 - 1);
+
+	debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
+
+#ifndef CONFIG_SPL_BUILD
+	/*
+	 * reserve memory for malloc() arena
+	 */
+	addr_sp = addr - TOTAL_MALLOC_LEN;
+	debug("Reserving %dk for malloc() at: %08lx\n",
+			TOTAL_MALLOC_LEN >> 10, addr_sp);
+	/*
+	 * (permanently) allocate a Board Info struct
+	 * and a permanent copy of the "global" data
+	 */
+	addr_sp -= sizeof (bd_t);
+	bd = (bd_t *) addr_sp;
+	gd->bd = bd;
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
+			sizeof (bd_t), addr_sp);
+
+#ifdef CONFIG_MACH_TYPE
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
+#endif
+
+	addr_sp -= sizeof (gd_t);
+	id = (gd_t *) addr_sp;
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			sizeof (gd_t), addr_sp);
+
+#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
+	/*
+	 * If the device tree is sitting immediate above our image then we
+	 * must relocate it. If it is embedded in the data section, then it
+	 * will be relocated with other data.
+	 */
+	if (gd->fdt_blob) {
+		fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+
+		addr_sp -= fdt_size;
+		new_fdt = (void *)addr_sp;
+		debug("Reserving %zu Bytes for FDT at: %08lx\n",
+		      fdt_size, addr_sp);
+	}
+#endif
+
+#ifndef CONFIG_ARM64
+	/* setup stackpointer for exeptions */
+	gd->irq_sp = addr_sp;
+#ifdef CONFIG_USE_IRQ
+	addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ);
+	debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
+		CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
+#endif
+	/* leave 3 words for abort-stack    */
+	addr_sp -= 12;
+
+	/* 8-byte alignment for ABI compliance */
+	addr_sp &= ~0x07;
+#else	/* CONFIG_ARM64 */
+	/* 16-byte alignment for ABI compliance */
+	addr_sp &= ~0x0f;
+#endif	/* CONFIG_ARM64 */
+#else
+	addr_sp += 128;	/* leave 32 words for abort-stack   */
+	gd->irq_sp = addr_sp;
+#endif
+
+	debug("New Stack Pointer is: %08lx\n", addr_sp);
+
+#ifdef CONFIG_POST
+	post_bootmode_init();
+	post_run(NULL, POST_ROM | post_bootmode_get(0));
+#endif
+
+	/* Ram ist board specific, so move it to board code ... */
+	dram_init_banksize();
+	display_dram_config();	/* and display it */
+
+	gd->relocaddr = addr;
+	gd->start_addr_sp = addr_sp;
+	gd->reloc_off = addr - (ulong)&_start;
+	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	if (new_fdt) {
+		memcpy(new_fdt, gd->fdt_blob, fdt_size);
+		gd->fdt_blob = new_fdt;
+	}
+	memcpy(id, (void *)gd, sizeof(gd_t));
+}
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+static char *failed = "*** failed ***\n";
+#endif
+
+/*
+ * Tell if it's OK to load the environment early in boot.
+ *
+ * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see
+ * if this is OK (defaulting to saying it's not OK).
+ *
+ * NOTE: Loading the environment early can be a bad idea if security is
+ *       important, since no verification is done on the environment.
+ *
+ * @return 0 if environment should not be loaded, !=0 if it is ok to load
+ */
+static int should_load_env(void)
+{
+#ifdef CONFIG_OF_CONTROL
+	return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
+#elif defined CONFIG_DELAY_ENVIRONMENT
+	return 0;
+#else
+	return 1;
+#endif
+}
+
+#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) && defined(CONFIG_OF_CONTROL)
+static void display_fdt_model(const void *blob)
+{
+	const char *model;
+
+	model = (char *)fdt_getprop(blob, 0, "model", NULL);
+	printf("Model: %s\n", model ? model : "<unknown>");
+}
+#endif
+
+/************************************************************************
+ *
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ *
+ ************************************************************************
+ */
+
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+	ulong malloc_start;
+#if !defined(CONFIG_SYS_NO_FLASH)
+	ulong flash_size;
+#endif
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
+
+	monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start;
+
+	/* Enable caches */
+	enable_caches();
+
+	debug("monitor flash len: %08lX\n", monitor_flash_len);
+	board_init();	/* Setup chipselects */
+	/*
+	 * TODO: printing of the clock inforamtion of the board is now
+	 * implemented as part of bdinfo command. Currently only support for
+	 * davinci SOC's is added. Remove this check once all the board
+	 * implement this.
+	 */
+#ifdef CONFIG_CLOCKS
+	set_cpu_clk_info(); /* Setup clock information */
+#endif
+	serial_initialize();
+
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+
+#ifdef CONFIG_LOGBUFFER
+	logbuff_init_ptrs();
+#endif
+#ifdef CONFIG_POST
+	post_output_backlog();
+#endif
+
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+	mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
+
+#ifdef CONFIG_ARCH_EARLY_INIT_R
+	arch_early_init_r();
+#endif
+	power_init_board();
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+	puts("Flash: ");
+
+	flash_size = flash_init();
+	if (flash_size > 0) {
+# ifdef CONFIG_SYS_FLASH_CHECKSUM
+		print_size(flash_size, "");
+		/*
+		 * Compute and print flash CRC if flashchecksum is set to 'y'
+		 *
+		 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
+		 */
+		if (getenv_yesno("flashchecksum") == 1) {
+			printf("  CRC: %08X", crc32(0,
+				(const unsigned char *) CONFIG_SYS_FLASH_BASE,
+				flash_size));
+		}
+		putc('\n');
+# else	/* !CONFIG_SYS_FLASH_CHECKSUM */
+		print_size(flash_size, "\n");
+# endif /* CONFIG_SYS_FLASH_CHECKSUM */
+	} else {
+		puts(failed);
+		hang();
+	}
+#endif
+
+#if defined(CONFIG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+	onenand_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+#endif
+
+#ifdef CONFIG_CMD_SCSI
+	puts("SCSI:  ");
+	scsi_init();
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+	AT91F_DataflashInit();
+	dataflash_print_info();
+#endif
+
+	/* initialize environment */
+	if (should_load_env())
+		env_relocate();
+	else
+		set_default_env(NULL);
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	arm_pci_init();
+#endif
+
+	stdio_init();	/* get the devices list going. */
+
+	jumptable_init();
+
+#if defined(CONFIG_API)
+	/* Initialize API */
+	api_init();
+#endif
+
+	console_init_r();	/* fully init console as a device */
+
+#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
+# ifdef CONFIG_OF_CONTROL
+	/* Put this here so it appears on the LCD, now it is ready */
+	display_fdt_model(gd->fdt_blob);
+# else
+	checkboard();
+# endif
+#endif
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+	 /* set up exceptions */
+	interrupt_init();
+	/* enable exceptions */
+	enable_interrupts();
+
+	/* Initialize from environment */
+	load_addr = getenv_ulong("loadaddr", 16, load_addr);
+
+#ifdef CONFIG_BOARD_LATE_INIT
+	board_late_init();
+#endif
+
+#ifdef CONFIG_BITBANGMII
+	bb_miiphy_init();
+#endif
+#if defined(CONFIG_CMD_NET)
+	puts("Net:   ");
+	eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+	debug("Reset Ethernet PHY\n");
+	reset_phy();
+#endif
+#endif
+
+#ifdef CONFIG_POST
+	post_run(NULL, POST_RAM | post_bootmode_get(0));
+#endif
+
+#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
+	/*
+	 * Export available size of memory for Linux,
+	 * taking into account the protected RAM at top of memory
+	 */
+	{
+		ulong pram = 0;
+		uchar memsz[32];
+
+#ifdef CONFIG_PRAM
+		pram = getenv_ulong("pram", 10, CONFIG_PRAM);
+#endif
+#ifdef CONFIG_LOGBUFFER
+#ifndef CONFIG_ALT_LB_ADDR
+		/* Also take the logbuffer into account (pram is in kB) */
+		pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
+#endif
+#endif
+		sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
+		setenv("mem", (char *)memsz);
+	}
+#endif
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;) {
+		main_loop();
+	}
+
+	/* NOTREACHED - no way out of command loop except booting */
+}
diff --git a/qemu/roms/u-boot/arch/arm/lib/bootm-fdt.c b/qemu/roms/u-boot/arch/arm/lib/bootm-fdt.c
new file mode 100644
index 000000000..e40691d15
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/bootm-fdt.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *  - Added prep subcommand support
+ *  - Reorganized source - modeled after powerpc version
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2001  Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_fixup_memory_node(void *blob)
+{
+	bd_t *bd = gd->bd;
+	int bank;
+	u64 start[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start[bank] = bd->bi_dram[bank].start;
+		size[bank] = bd->bi_dram[bank].size;
+	}
+
+	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+}
diff --git a/qemu/roms/u-boot/arch/arm/lib/bootm.c b/qemu/roms/u-boot/arch/arm/lib/bootm.c
new file mode 100644
index 000000000..47ee07059
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/bootm.c
@@ -0,0 +1,375 @@
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *  - Added prep subcommand support
+ *  - Reorganized source - modeled after powerpc version
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2001  Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/bootm.h>
+#include <linux/compiler.h>
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#include <asm/armv7.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct tag *params;
+
+static ulong get_sp(void)
+{
+	ulong ret;
+
+	asm("mov %0, sp" : "=r"(ret) : );
+	return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+	ulong sp;
+
+	/*
+	 * Booting a (Linux) kernel image
+	 *
+	 * Allocate space for command line and board info - the
+	 * address should be as high as possible within the reach of
+	 * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+	 * memory, which means far enough below the current stack
+	 * pointer.
+	 */
+	sp = get_sp();
+	debug("## Current stack ends at 0x%08lx ", sp);
+
+	/* adjust sp by 4K to be safe */
+	sp -= 4096;
+	lmb_reserve(lmb, sp,
+		    gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
+}
+
+/**
+ * announce_and_cleanup() - Print message and prepare for kernel boot
+ *
+ * @fake: non-zero to do everything except actually boot
+ */
+static void announce_and_cleanup(int fake)
+{
+	printf("\nStarting kernel ...%s\n\n", fake ?
+		"(fake run for tracing)" : "");
+	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+#ifdef CONFIG_BOOTSTAGE_FDT
+	bootstage_fdt_add_report();
+#endif
+#ifdef CONFIG_BOOTSTAGE_REPORT
+	bootstage_report();
+#endif
+
+#ifdef CONFIG_USB_DEVICE
+	udc_disconnect();
+#endif
+	cleanup_before_linux();
+}
+
+static void setup_start_tag (bd_t *bd)
+{
+	params = (struct tag *)bd->bi_boot_params;
+
+	params->hdr.tag = ATAG_CORE;
+	params->hdr.size = tag_size (tag_core);
+
+	params->u.core.flags = 0;
+	params->u.core.pagesize = 0;
+	params->u.core.rootdev = 0;
+
+	params = tag_next (params);
+}
+
+static void setup_memory_tags(bd_t *bd)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		params->hdr.tag = ATAG_MEM;
+		params->hdr.size = tag_size (tag_mem32);
+
+		params->u.mem.start = bd->bi_dram[i].start;
+		params->u.mem.size = bd->bi_dram[i].size;
+
+		params = tag_next (params);
+	}
+}
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+	char *p;
+
+	if (!commandline)
+		return;
+
+	/* eat leading white space */
+	for (p = commandline; *p == ' '; p++);
+
+	/* skip non-existent command lines so the kernel will still
+	 * use its default command line.
+	 */
+	if (*p == '\0')
+		return;
+
+	params->hdr.tag = ATAG_CMDLINE;
+	params->hdr.size =
+		(sizeof (struct tag_header) + strlen (p) + 1 + 4) >> 2;
+
+	strcpy (params->u.cmdline.cmdline, p);
+
+	params = tag_next (params);
+}
+
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+	/* an ATAG_INITRD node tells the kernel where the compressed
+	 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+	 */
+	params->hdr.tag = ATAG_INITRD2;
+	params->hdr.size = tag_size (tag_initrd);
+
+	params->u.initrd.start = initrd_start;
+	params->u.initrd.size = initrd_end - initrd_start;
+
+	params = tag_next (params);
+}
+
+static void setup_serial_tag(struct tag **tmp)
+{
+	struct tag *params = *tmp;
+	struct tag_serialnr serialnr;
+
+	get_board_serial(&serialnr);
+	params->hdr.tag = ATAG_SERIAL;
+	params->hdr.size = tag_size (tag_serialnr);
+	params->u.serialnr.low = serialnr.low;
+	params->u.serialnr.high= serialnr.high;
+	params = tag_next (params);
+	*tmp = params;
+}
+
+static void setup_revision_tag(struct tag **in_params)
+{
+	u32 rev = 0;
+
+	rev = get_board_rev();
+	params->hdr.tag = ATAG_REVISION;
+	params->hdr.size = tag_size (tag_revision);
+	params->u.revision.rev = rev;
+	params = tag_next (params);
+}
+
+static void setup_end_tag(bd_t *bd)
+{
+	params->hdr.tag = ATAG_NONE;
+	params->hdr.size = 0;
+}
+
+__weak void setup_board_tags(struct tag **in_params) {}
+
+static void do_nonsec_virt_switch(void)
+{
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+	if (armv7_switch_nonsec() == 0)
+#ifdef CONFIG_ARMV7_VIRT
+		if (armv7_switch_hyp() == 0)
+			debug("entered HYP mode\n");
+#else
+		debug("entered non-secure state\n");
+#endif
+#endif
+
+#ifdef CONFIG_ARM64
+	smp_kick_all_cpus();
+	flush_dcache_all();	/* flush cache before swtiching to EL2 */
+	armv8_switch_to_el2();
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	armv8_switch_to_el1();
+#endif
+#endif
+}
+
+/* Subcommand: PREP */
+static void boot_prep_linux(bootm_headers_t *images)
+{
+	char *commandline = getenv("bootargs");
+
+	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+#ifdef CONFIG_OF_LIBFDT
+		debug("using: FDT\n");
+		if (image_setup_linux(images)) {
+			printf("FDT creation failed! hanging...");
+			hang();
+		}
+#endif
+	} else if (BOOTM_ENABLE_TAGS) {
+		debug("using: ATAGS\n");
+		setup_start_tag(gd->bd);
+		if (BOOTM_ENABLE_SERIAL_TAG)
+			setup_serial_tag(&params);
+		if (BOOTM_ENABLE_CMDLINE_TAG)
+			setup_commandline_tag(gd->bd, commandline);
+		if (BOOTM_ENABLE_REVISION_TAG)
+			setup_revision_tag(&params);
+		if (BOOTM_ENABLE_MEMORY_TAGS)
+			setup_memory_tags(gd->bd);
+		if (BOOTM_ENABLE_INITRD_TAG) {
+			if (images->rd_start && images->rd_end) {
+				setup_initrd_tag(gd->bd, images->rd_start,
+						 images->rd_end);
+			}
+		}
+		setup_board_tags(&params);
+		setup_end_tag(gd->bd);
+	} else {
+		printf("FDT and ATAGS support not compiled in - hanging\n");
+		hang();
+	}
+	do_nonsec_virt_switch();
+}
+
+/* Subcommand: GO */
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+#ifdef CONFIG_ARM64
+	void (*kernel_entry)(void *fdt_addr);
+	int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
+	kernel_entry = (void (*)(void *fdt_addr))images->ep;
+
+	debug("## Transferring control to Linux (at address %lx)...\n",
+		(ulong) kernel_entry);
+	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+	announce_and_cleanup(fake);
+
+	if (!fake)
+		kernel_entry(images->ft_addr);
+#else
+	unsigned long machid = gd->bd->bi_arch_number;
+	char *s;
+	void (*kernel_entry)(int zero, int arch, uint params);
+	unsigned long r2;
+	int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
+	kernel_entry = (void (*)(int, int, uint))images->ep;
+
+	s = getenv("machid");
+	if (s) {
+		strict_strtoul(s, 16, &machid);
+		printf("Using machid 0x%lx from environment\n", machid);
+	}
+
+	debug("## Transferring control to Linux (at address %08lx)" \
+		"...\n", (ulong) kernel_entry);
+	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+	announce_and_cleanup(fake);
+
+	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+		r2 = (unsigned long)images->ft_addr;
+	else
+		r2 = gd->bd->bi_boot_params;
+
+	if (!fake)
+		kernel_entry(0, machid, r2);
+#endif
+}
+
+/* Main Entry point for arm bootm implementation
+ *
+ * Modeled after the powerpc implementation
+ * DIFFERENCE: Instead of calling prep and go at the end
+ * they are called if subcommand is equal 0.
+ */
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	/* No need for those on ARM */
+	if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+		return -1;
+
+	if (flag & BOOTM_STATE_OS_PREP) {
+		boot_prep_linux(images);
+		return 0;
+	}
+
+	if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+		boot_jump_linux(images, flag);
+		return 0;
+	}
+
+	boot_prep_linux(images);
+	boot_jump_linux(images, flag);
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BOOTZ
+
+struct zimage_header {
+	uint32_t	code[9];
+	uint32_t	zi_magic;
+	uint32_t	zi_start;
+	uint32_t	zi_end;
+};
+
+#define	LINUX_ARM_ZIMAGE_MAGIC	0x016f2818
+
+int bootz_setup(ulong image, ulong *start, ulong *end)
+{
+	struct zimage_header *zi;
+
+	zi = (struct zimage_header *)map_sysmem(image, 0);
+	if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) {
+		puts("Bad Linux ARM zImage magic!\n");
+		return 1;
+	}
+
+	*start = zi->zi_start;
+	*end = zi->zi_end;
+
+	printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", image, *start,
+	      *end);
+
+	return 0;
+}
+
+#endif	/* CONFIG_CMD_BOOTZ */
+
+#if defined(CONFIG_BOOTM_VXWORKS)
+void boot_prep_vxworks(bootm_headers_t *images)
+{
+#if defined(CONFIG_OF_LIBFDT)
+	int off;
+
+	if (images->ft_addr) {
+		off = fdt_path_offset(images->ft_addr, "/memory");
+		if (off < 0) {
+			if (arch_fixup_memory_node(images->ft_addr))
+				puts("## WARNING: fixup memory failed!\n");
+		}
+	}
+#endif
+	cleanup_before_linux();
+}
+void boot_jump_vxworks(bootm_headers_t *images)
+{
+	/* ARM VxWorks requires device tree physical address to be passed */
+	((void (*)(void *))images->ep)(images->ft_addr);
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/lib/cache-cp15.c b/qemu/roms/u-boot/arch/arm/lib/cache-cp15.c
new file mode 100644
index 000000000..8642010a1
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/cache-cp15.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <linux/compiler.h>
+
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __arm_init_before_mmu(void)
+{
+}
+void arm_init_before_mmu(void)
+	__attribute__((weak, alias("__arm_init_before_mmu")));
+
+__weak void arm_init_domains(void)
+{
+}
+
+static void cp_delay (void)
+{
+	volatile int i;
+
+	/* copro seems to need some delay between reading and writing */
+	for (i = 0; i < 100; i++)
+		nop();
+	asm volatile("" : : : "memory");
+}
+
+void set_section_dcache(int section, enum dcache_option option)
+{
+	u32 *page_table = (u32 *)gd->arch.tlb_addr;
+	u32 value;
+
+	value = (section << MMU_SECTION_SHIFT) | (3 << 10);
+	value |= option;
+	page_table[section] = value;
+}
+
+void __mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+	debug("%s: Warning: not implemented\n", __func__);
+}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+	__attribute__((weak, alias("__mmu_page_table_flush")));
+
+void mmu_set_region_dcache_behaviour(u32 start, int size,
+				     enum dcache_option option)
+{
+	u32 *page_table = (u32 *)gd->arch.tlb_addr;
+	u32 upto, end;
+
+	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
+	start = start >> MMU_SECTION_SHIFT;
+	debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
+	      option);
+	for (upto = start; upto < end; upto++)
+		set_section_dcache(upto, option);
+	mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+}
+
+__weak void dram_bank_mmu_setup(int bank)
+{
+	bd_t *bd = gd->bd;
+	int	i;
+
+	debug("%s: bank: %d\n", __func__, bank);
+	for (i = bd->bi_dram[bank].start >> 20;
+	     i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
+	     i++) {
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+		set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+		set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+	}
+}
+
+/* to activate the MMU we need to set up virtual memory: use 1M areas */
+static inline void mmu_setup(void)
+{
+	int i;
+	u32 reg;
+
+	arm_init_before_mmu();
+	/* Set up an identity-mapping for all 4GB, rw for everyone */
+	for (i = 0; i < 4096; i++)
+		set_section_dcache(i, DCACHE_OFF);
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		dram_bank_mmu_setup(i);
+	}
+
+	/* Copy the page table address to cp15 */
+	asm volatile("mcr p15, 0, %0, c2, c0, 0"
+		     : : "r" (gd->arch.tlb_addr) : "memory");
+	/* Set the access control to all-supervisor */
+	asm volatile("mcr p15, 0, %0, c3, c0, 0"
+		     : : "r" (~0));
+
+	arm_init_domains();
+
+	/* and enable the mmu */
+	reg = get_cr();	/* get control reg. */
+	cp_delay();
+	set_cr(reg | CR_M);
+}
+
+static int mmu_enabled(void)
+{
+	return get_cr() & CR_M;
+}
+
+/* cache_bit must be either CR_I or CR_C */
+static void cache_enable(uint32_t cache_bit)
+{
+	uint32_t reg;
+
+	/* The data cache is not active unless the mmu is enabled too */
+	if ((cache_bit == CR_C) && !mmu_enabled())
+		mmu_setup();
+	reg = get_cr();	/* get control reg. */
+	cp_delay();
+	set_cr(reg | cache_bit);
+}
+
+/* cache_bit must be either CR_I or CR_C */
+static void cache_disable(uint32_t cache_bit)
+{
+	uint32_t reg;
+
+	reg = get_cr();
+	cp_delay();
+
+	if (cache_bit == CR_C) {
+		/* if cache isn;t enabled no need to disable */
+		if ((reg & CR_C) != CR_C)
+			return;
+		/* if disabling data cache, disable mmu too */
+		cache_bit |= CR_M;
+	}
+	reg = get_cr();
+	cp_delay();
+	if (cache_bit == (CR_C | CR_M))
+		flush_dcache_all();
+	set_cr(reg & ~cache_bit);
+}
+#endif
+
+#ifdef CONFIG_SYS_ICACHE_OFF
+void icache_enable (void)
+{
+	return;
+}
+
+void icache_disable (void)
+{
+	return;
+}
+
+int icache_status (void)
+{
+	return 0;					/* always off */
+}
+#else
+void icache_enable(void)
+{
+	cache_enable(CR_I);
+}
+
+void icache_disable(void)
+{
+	cache_disable(CR_I);
+}
+
+int icache_status(void)
+{
+	return (get_cr() & CR_I) != 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_DCACHE_OFF
+void dcache_enable (void)
+{
+	return;
+}
+
+void dcache_disable (void)
+{
+	return;
+}
+
+int dcache_status (void)
+{
+	return 0;					/* always off */
+}
+#else
+void dcache_enable(void)
+{
+	cache_enable(CR_C);
+}
+
+void dcache_disable(void)
+{
+	cache_disable(CR_C);
+}
+
+int dcache_status(void)
+{
+	return (get_cr() & CR_C) != 0;
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/lib/cache-pl310.c b/qemu/roms/u-boot/arch/arm/lib/cache-pl310.c
new file mode 100644
index 000000000..1ad1f8aea
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/cache-pl310.c
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
+#include <config.h>
+#include <common.h>
+
+struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+static void pl310_cache_sync(void)
+{
+	writel(0, &pl310->pl310_cache_sync);
+}
+
+static void pl310_background_op_all_ways(u32 *op_reg)
+{
+	u32 assoc_16, associativity, way_mask;
+
+	assoc_16 = readl(&pl310->pl310_aux_ctrl) &
+			PL310_AUX_CTRL_ASSOCIATIVITY_MASK;
+	if (assoc_16)
+		associativity = 16;
+	else
+		associativity = 8;
+
+	way_mask = (1 << associativity) - 1;
+	/* Invalidate all ways */
+	writel(way_mask, op_reg);
+	/* Wait for all ways to be invalidated */
+	while (readl(op_reg) && way_mask)
+		;
+	pl310_cache_sync();
+}
+
+void v7_outer_cache_inval_all(void)
+{
+	pl310_background_op_all_ways(&pl310->pl310_inv_way);
+}
+
+void v7_outer_cache_flush_all(void)
+{
+	pl310_background_op_all_ways(&pl310->pl310_clean_inv_way);
+}
+
+/* Flush(clean invalidate) memory from start to stop-1 */
+void v7_outer_cache_flush_range(u32 start, u32 stop)
+{
+	/* PL310 currently supports only 32 bytes cache line */
+	u32 pa, line_size = 32;
+
+	/*
+	 * Align to the beginning of cache-line - this ensures that
+	 * the first 5 bits are 0 as required by PL310 TRM
+	 */
+	start &= ~(line_size - 1);
+
+	for (pa = start; pa < stop; pa = pa + line_size)
+		writel(pa, &pl310->pl310_clean_inv_line_pa);
+
+	pl310_cache_sync();
+}
+
+/* invalidate memory from start to stop-1 */
+void v7_outer_cache_inval_range(u32 start, u32 stop)
+{
+	/* PL310 currently supports only 32 bytes cache line */
+	u32 pa, line_size = 32;
+
+	/*
+	 * If start address is not aligned to cache-line do not
+	 * invalidate the first cache-line
+	 */
+	if (start & (line_size - 1)) {
+		printf("ERROR: %s - start address is not aligned - 0x%08x\n",
+			__func__, start);
+		/* move to next cache line */
+		start = (start + line_size - 1) & ~(line_size - 1);
+	}
+
+	/*
+	 * If stop address is not aligned to cache-line do not
+	 * invalidate the last cache-line
+	 */
+	if (stop & (line_size - 1)) {
+		printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
+			__func__, stop);
+		/* align to the beginning of this cache line */
+		stop &= ~(line_size - 1);
+	}
+
+	for (pa = start; pa < stop; pa = pa + line_size)
+		writel(pa, &pl310->pl310_inv_line_pa);
+
+	pl310_cache_sync();
+}
diff --git a/qemu/roms/u-boot/arch/arm/lib/cache.c b/qemu/roms/u-boot/arch/arm/lib/cache.c
new file mode 100644
index 000000000..6cc136aa3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/cache.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* for now: just dummy functions to satisfy the linker */
+
+#include <common.h>
+
+void  __flush_cache(unsigned long start, unsigned long size)
+{
+#if defined(CONFIG_ARM1136)
+	void arm1136_cache_flush(void);
+
+	arm1136_cache_flush();
+#endif
+#ifdef CONFIG_ARM926EJS
+	/* test and clean, page 2-23 of arm926ejs manual */
+	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
+	/* disable write buffer as well (page 2-22) */
+	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+#endif
+	return;
+}
+void  flush_cache(unsigned long start, unsigned long size)
+	__attribute__((weak, alias("__flush_cache")));
+
+/*
+ * Default implementation:
+ * do a range flush for the entire range
+ */
+void	__flush_dcache_all(void)
+{
+	flush_cache(0, ~0);
+}
+void	flush_dcache_all(void)
+	__attribute__((weak, alias("__flush_dcache_all")));
+
+
+/*
+ * Default implementation of enable_caches()
+ * Real implementation should be in platform code
+ */
+void __enable_caches(void)
+{
+	puts("WARNING: Caches not enabled\n");
+}
+void enable_caches(void)
+	__attribute__((weak, alias("__enable_caches")));
diff --git a/qemu/roms/u-boot/arch/arm/lib/crt0.S b/qemu/roms/u-boot/arch/arm/lib/crt0.S
new file mode 100644
index 000000000..dfc2de9a6
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/crt0.S
@@ -0,0 +1,123 @@
+/*
+ *  crt0 - C-runtime startup Code for ARM U-Boot
+ *
+ *  Copyright (c) 2012  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <linux/linkage.h>
+
+/*
+ * This file handles the target-independent stages of the U-Boot
+ * start-up where a C runtime environment is needed. Its entry point
+ * is _main and is branched into from the target's start.S file.
+ *
+ * _main execution sequence is:
+ *
+ * 1. Set up initial environment for calling board_init_f().
+ *    This environment only provides a stack and a place to store
+ *    the GD ('global data') structure, both located in some readily
+ *    available RAM (SRAM, locked cache...). In this context, VARIABLE
+ *    global data, initialized or not (BSS), are UNAVAILABLE; only
+ *    CONSTANT initialized data are available.
+ *
+ * 2. Call board_init_f(). This function prepares the hardware for
+ *    execution from system RAM (DRAM, DDR...) As system RAM may not
+ *    be available yet, , board_init_f() must use the current GD to
+ *    store any data which must be passed on to later stages. These
+ *    data include the relocation destination, the future stack, and
+ *    the future GD location.
+ *
+ * (the following applies only to non-SPL builds)
+ *
+ * 3. Set up intermediate environment where the stack and GD are the
+ *    ones allocated by board_init_f() in system RAM, but BSS and
+ *    initialized non-const data are still not available.
+ *
+ * 4. Call relocate_code(). This function relocates U-Boot from its
+ *    current location into the relocation destination computed by
+ *    board_init_f().
+ *
+ * 5. Set up final environment for calling board_init_r(). This
+ *    environment has BSS (initialized to 0), initialized non-const
+ *    data (initialized to their intended value), and stack in system
+ *    RAM. GD has retained values set by board_init_f(). Some CPUs
+ *    have some work left to do at this point regarding memory, so
+ *    call c_runtime_cpu_setup.
+ *
+ * 6. Branch to board_init_r().
+ */
+
+/*
+ * entry point of crt0 sequence
+ */
+
+ENTRY(_main)
+
+/*
+ * Set up initial C runtime environment and call board_init_f(0).
+ */
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+	ldr	sp, =(CONFIG_SPL_STACK)
+#else
+	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
+	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
+	sub	sp, sp, #GD_SIZE	/* allocate one GD above SP */
+	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
+	mov	r9, sp		/* GD is above SP */
+	mov	r0, #0
+	bl	board_init_f
+
+#if ! defined(CONFIG_SPL_BUILD)
+
+/*
+ * Set up intermediate environment (new sp and gd) and call
+ * relocate_code(addr_moni). Trick here is that we'll return
+ * 'here' but relocated.
+ */
+
+	ldr	sp, [r9, #GD_START_ADDR_SP]	/* sp = gd->start_addr_sp */
+	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
+	ldr	r9, [r9, #GD_BD]		/* r9 = gd->bd */
+	sub	r9, r9, #GD_SIZE		/* new GD is below bd */
+
+	adr	lr, here
+	ldr	r0, [r9, #GD_RELOC_OFF]		/* r0 = gd->reloc_off */
+	add	lr, lr, r0
+	ldr	r0, [r9, #GD_RELOCADDR]		/* r0 = gd->relocaddr */
+	b	relocate_code
+here:
+
+/* Set up final (full) environment */
+
+	bl	c_runtime_cpu_setup	/* we still call old routine here */
+
+	ldr	r0, =__bss_start	/* this is auto-relocated! */
+	ldr	r1, =__bss_end		/* this is auto-relocated! */
+
+	mov	r2, #0x00000000		/* prepare zero to clear BSS */
+
+clbss_l:cmp	r0, r1			/* while not at end of BSS */
+	strlo	r2, [r0]		/* clear 32-bit BSS word */
+	addlo	r0, r0, #4		/* move to next */
+	blo	clbss_l
+
+	bl coloured_LED_init
+	bl red_led_on
+
+	/* call board_init_r(gd_t *id, ulong dest_addr) */
+	mov     r0, r9                  /* gd_t */
+	ldr	r1, [r9, #GD_RELOCADDR]	/* dest_addr */
+	/* call board_init_r */
+	ldr	pc, =board_init_r	/* this is auto-relocated! */
+
+	/* we should not return here. */
+
+#endif
+
+ENDPROC(_main)
diff --git a/qemu/roms/u-boot/arch/arm/lib/crt0_64.S b/qemu/roms/u-boot/arch/arm/lib/crt0_64.S
new file mode 100644
index 000000000..77563967e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/crt0_64.S
@@ -0,0 +1,113 @@
+/*
+ * crt0 - C-runtime startup Code for AArch64 U-Boot
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2012
+ * Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/macro.h>
+#include <linux/linkage.h>
+
+/*
+ * This file handles the target-independent stages of the U-Boot
+ * start-up where a C runtime environment is needed. Its entry point
+ * is _main and is branched into from the target's start.S file.
+ *
+ * _main execution sequence is:
+ *
+ * 1. Set up initial environment for calling board_init_f().
+ *    This environment only provides a stack and a place to store
+ *    the GD ('global data') structure, both located in some readily
+ *    available RAM (SRAM, locked cache...). In this context, VARIABLE
+ *    global data, initialized or not (BSS), are UNAVAILABLE; only
+ *    CONSTANT initialized data are available.
+ *
+ * 2. Call board_init_f(). This function prepares the hardware for
+ *    execution from system RAM (DRAM, DDR...) As system RAM may not
+ *    be available yet, , board_init_f() must use the current GD to
+ *    store any data which must be passed on to later stages. These
+ *    data include the relocation destination, the future stack, and
+ *    the future GD location.
+ *
+ * (the following applies only to non-SPL builds)
+ *
+ * 3. Set up intermediate environment where the stack and GD are the
+ *    ones allocated by board_init_f() in system RAM, but BSS and
+ *    initialized non-const data are still not available.
+ *
+ * 4. Call relocate_code(). This function relocates U-Boot from its
+ *    current location into the relocation destination computed by
+ *    board_init_f().
+ *
+ * 5. Set up final environment for calling board_init_r(). This
+ *    environment has BSS (initialized to 0), initialized non-const
+ *    data (initialized to their intended value), and stack in system
+ *    RAM. GD has retained values set by board_init_f(). Some CPUs
+ *    have some work left to do at this point regarding memory, so
+ *    call c_runtime_cpu_setup.
+ *
+ * 6. Branch to board_init_r().
+ */
+
+ENTRY(_main)
+
+/*
+ * Set up initial C runtime environment and call board_init_f(0).
+ */
+	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)
+	sub	x0, x0, #GD_SIZE	/* allocate one GD above SP */
+	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
+	mov	x18, sp			/* GD is above SP */
+	mov	x0, #0
+	bl	board_init_f
+
+/*
+ * Set up intermediate environment (new sp and gd) and call
+ * relocate_code(addr_moni). Trick here is that we'll return
+ * 'here' but relocated.
+ */
+	ldr	x0, [x18, #GD_START_ADDR_SP]	/* x0 <- gd->start_addr_sp */
+	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
+	ldr	x18, [x18, #GD_BD]		/* x18 <- gd->bd */
+	sub	x18, x18, #GD_SIZE		/* new GD is below bd */
+
+	adr	lr, relocation_return
+	ldr	x9, [x18, #GD_RELOC_OFF]	/* x9 <- gd->reloc_off */
+	add	lr, lr, x9	/* new return address after relocation */
+	ldr	x0, [x18, #GD_RELOCADDR]	/* x0 <- gd->relocaddr */
+	b	relocate_code
+
+relocation_return:
+
+/*
+ * Set up final (full) environment
+ */
+	bl	c_runtime_cpu_setup		/* still call old routine */
+
+/*
+ * Clear BSS section
+ */
+	ldr	x0, =__bss_start		/* this is auto-relocated! */
+	ldr	x1, =__bss_end			/* this is auto-relocated! */
+	mov	x2, #0
+clear_loop:
+	str	x2, [x0]
+	add	x0, x0, #8
+	cmp	x0, x1
+	b.lo	clear_loop
+
+	/* call board_init_r(gd_t *id, ulong dest_addr) */
+	mov	x0, x18				/* gd_t */
+	ldr	x1, [x18, #GD_RELOCADDR]	/* dest_addr */
+	b	board_init_r			/* PC relative jump */
+
+	/* NOTREACHED - board_init_r() does not return */
+
+ENDPROC(_main)
diff --git a/qemu/roms/u-boot/arch/arm/lib/div0.c b/qemu/roms/u-boot/arch/arm/lib/div0.c
new file mode 100644
index 000000000..1337ccab0
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/div0.c
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Replacement (=dummy) for GNU/Linux division-by zero handler */
+void __div0 (void)
+{
+	extern void hang (void);
+
+	hang();
+}
diff --git a/qemu/roms/u-boot/arch/arm/lib/eabi_compat.c b/qemu/roms/u-boot/arch/arm/lib/eabi_compat.c
new file mode 100644
index 000000000..10d19333f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/eabi_compat.c
@@ -0,0 +1,27 @@
+/*
+ * Utility functions needed for (some) EABI conformant tool chains.
+ *
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+int raise (int signum)
+{
+	/* Even if printf() is available, it's large. Punt it for SPL builds */
+#if !defined(CONFIG_SPL_BUILD)
+	printf("raise: Signal # %d caught\n", signum);
+#endif
+	return 0;
+}
+
+/* Dummy function to avoid linker complaints */
+void __aeabi_unwind_cpp_pr0(void)
+{
+};
+
+void __aeabi_unwind_cpp_pr1(void)
+{
+};
diff --git a/qemu/roms/u-boot/arch/arm/lib/gic_64.S b/qemu/roms/u-boot/arch/arm/lib/gic_64.S
new file mode 100644
index 000000000..d56396ea2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/gic_64.S
@@ -0,0 +1,194 @@
+/*
+ * GIC Initialization Routines.
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/gic.h>
+
+
+/*************************************************************************
+ *
+ * void gic_init_secure(DistributorBase);
+ *
+ * Initialize secure copy of GIC at EL3.
+ *
+ *************************************************************************/
+ENTRY(gic_init_secure)
+	/*
+	 * Initialize Distributor
+	 * x0: Distributor Base
+	 */
+#if defined(CONFIG_GICV3)
+	mov	w9, #0x37		/* EnableGrp0 | EnableGrp1NS */
+					/* EnableGrp1S | ARE_S | ARE_NS */
+	str	w9, [x0, GICD_CTLR]	/* Secure GICD_CTLR */
+	ldr	w9, [x0, GICD_TYPER]
+	and	w10, w9, #0x1f		/* ITLinesNumber */
+	cbz	w10, 1f			/* No SPIs */
+	add	x11, x0, (GICD_IGROUPRn + 4)
+	add	x12, x0, (GICD_IGROUPMODRn + 4)
+	mov	w9, #~0
+0:	str	w9, [x11], #0x4
+	str	wzr, [x12], #0x4	/* Config SPIs as Group1NS */
+	sub	w10, w10, #0x1
+	cbnz	w10, 0b
+#elif defined(CONFIG_GICV2)
+	mov	w9, #0x3		/* EnableGrp0 | EnableGrp1 */
+	str	w9, [x0, GICD_CTLR]	/* Secure GICD_CTLR */
+	ldr	w9, [x0, GICD_TYPER]
+	and	w10, w9, #0x1f		/* ITLinesNumber */
+	cbz	w10, 1f			/* No SPIs */
+	add	x11, x0, (GICD_IGROUPRn + 4)
+	mov	w9, #~0			/* Config SPIs as Grp1 */
+0:	str	w9, [x11], #0x4
+	sub	w10, w10, #0x1
+	cbnz	w10, 0b
+#endif
+1:
+	ret
+ENDPROC(gic_init_secure)
+
+
+/*************************************************************************
+ * For Gicv2:
+ * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
+ * For Gicv3:
+ * void gic_init_secure_percpu(ReDistributorBase);
+ *
+ * Initialize secure copy of GIC at EL3.
+ *
+ *************************************************************************/
+ENTRY(gic_init_secure_percpu)
+#if defined(CONFIG_GICV3)
+	/*
+	 * Initialize ReDistributor
+	 * x0: ReDistributor Base
+	 */
+	mrs	x10, mpidr_el1
+	lsr	x9, x10, #32
+	bfi	x10, x9, #24, #8	/* w10 is aff3:aff2:aff1:aff0 */
+	mov	x9, x0
+1:	ldr	x11, [x9, GICR_TYPER]
+	lsr	x11, x11, #32		/* w11 is aff3:aff2:aff1:aff0 */
+	cmp	w10, w11
+	b.eq	2f
+	add	x9, x9, #(2 << 16)
+	b	1b
+
+	/* x9: ReDistributor Base Address of Current CPU */
+2:	mov	w10, #~0x2
+	ldr	w11, [x9, GICR_WAKER]
+	and	w11, w11, w10		/* Clear ProcessorSleep */
+	str	w11, [x9, GICR_WAKER]
+	dsb	st
+	isb
+3:	ldr	w10, [x9, GICR_WAKER]
+	tbnz	w10, #2, 3b		/* Wait Children be Alive */
+
+	add	x10, x9, #(1 << 16)	/* SGI_Base */
+	mov	w11, #~0
+	str	w11, [x10, GICR_IGROUPRn]
+	str	wzr, [x10, GICR_IGROUPMODRn]	/* SGIs|PPIs Group1NS */
+	mov	w11, #0x1		/* Enable SGI 0 */
+	str	w11, [x10, GICR_ISENABLERn]
+
+	/* Initialize Cpu Interface */
+	mrs	x10, ICC_SRE_EL3
+	orr	x10, x10, #0xf		/* SRE & Disable IRQ/FIQ Bypass & */
+					/* Allow EL2 access to ICC_SRE_EL2 */
+	msr	ICC_SRE_EL3, x10
+	isb
+
+	mrs	x10, ICC_SRE_EL2
+	orr	x10, x10, #0xf		/* SRE & Disable IRQ/FIQ Bypass & */
+					/* Allow EL1 access to ICC_SRE_EL1 */
+	msr	ICC_SRE_EL2, x10
+	isb
+
+	mov	x10, #0x3		/* EnableGrp1NS | EnableGrp1S */
+	msr	ICC_IGRPEN1_EL3, x10
+	isb
+
+	msr	ICC_CTLR_EL3, xzr
+	isb
+
+	msr	ICC_CTLR_EL1, xzr	/* NonSecure ICC_CTLR_EL1 */
+	isb
+
+	mov	x10, #0x1 << 7		/* Non-Secure access to ICC_PMR_EL1 */
+	msr	ICC_PMR_EL1, x10
+	isb
+#elif defined(CONFIG_GICV2)
+	/*
+	 * Initialize SGIs and PPIs
+	 * x0: Distributor Base
+	 * x1: Cpu Interface Base
+	 */
+	mov	w9, #~0			/* Config SGIs and PPIs as Grp1 */
+	str	w9, [x0, GICD_IGROUPRn]	/* GICD_IGROUPR0 */
+	mov	w9, #0x1		/* Enable SGI 0 */
+	str	w9, [x0, GICD_ISENABLERn]
+
+	/* Initialize Cpu Interface */
+	mov	w9, #0x1e7		/* Disable IRQ/FIQ Bypass & */
+					/* Enable Ack Group1 Interrupt & */
+					/* EnableGrp0 & EnableGrp1 */
+	str	w9, [x1, GICC_CTLR]	/* Secure GICC_CTLR */
+
+	mov	w9, #0x1 << 7		/* Non-Secure access to GICC_PMR */
+	str	w9, [x1, GICC_PMR]
+#endif
+	ret
+ENDPROC(gic_init_secure_percpu)
+
+
+/*************************************************************************
+ * For Gicv2:
+ * void gic_kick_secondary_cpus(DistributorBase);
+ * For Gicv3:
+ * void gic_kick_secondary_cpus(void);
+ *
+ *************************************************************************/
+ENTRY(gic_kick_secondary_cpus)
+#if defined(CONFIG_GICV3)
+	mov	x9, #(1 << 40)
+	msr	ICC_ASGI1R_EL1, x9
+	isb
+#elif defined(CONFIG_GICV2)
+	mov	w9, #0x8000
+	movk	w9, #0x100, lsl #16
+	str	w9, [x0, GICD_SGIR]
+#endif
+	ret
+ENDPROC(gic_kick_secondary_cpus)
+
+
+/*************************************************************************
+ * For Gicv2:
+ * void gic_wait_for_interrupt(CpuInterfaceBase);
+ * For Gicv3:
+ * void gic_wait_for_interrupt(void);
+ *
+ * Wait for SGI 0 from master.
+ *
+ *************************************************************************/
+ENTRY(gic_wait_for_interrupt)
+0:	wfi
+#if defined(CONFIG_GICV3)
+	mrs	x9, ICC_IAR1_EL1
+	msr	ICC_EOIR1_EL1, x9
+#elif defined(CONFIG_GICV2)
+	ldr	w9, [x0, GICC_AIAR]
+	str	w9, [x0, GICC_AEOIR]
+#endif
+	cbnz	w9, 0b
+	ret
+ENDPROC(gic_wait_for_interrupt)
diff --git a/qemu/roms/u-boot/arch/arm/lib/interrupts.c b/qemu/roms/u-boot/arch/arm/lib/interrupts.c
new file mode 100644
index 000000000..758b01371
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/interrupts.c
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USE_IRQ
+int interrupt_init (void)
+{
+	/*
+	 * setup up stacks if necessary
+	 */
+	IRQ_STACK_START = gd->irq_sp - 4;
+	IRQ_STACK_START_IN = gd->irq_sp + 8;
+	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+
+	return arch_interrupt_init();
+}
+
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+	unsigned long temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     "bic %0, %0, #0x80\n"
+			     "msr cpsr_c, %0"
+			     : "=r" (temp)
+			     :
+			     : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+	unsigned long old,temp;
+	__asm__ __volatile__("mrs %0, cpsr\n"
+			     "orr %1, %0, #0xc0\n"
+			     "msr cpsr_c, %1"
+			     : "=r" (old), "=r" (temp)
+			     :
+			     : "memory");
+	return (old & 0x80) == 0;
+}
+#else
+int interrupt_init (void)
+{
+	/*
+	 * setup up stacks if necessary
+	 */
+	IRQ_STACK_START_IN = gd->irq_sp + 8;
+
+	return 0;
+}
+
+void enable_interrupts (void)
+{
+	return;
+}
+int disable_interrupts (void)
+{
+	return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+	panic ("Resetting CPU ...\n");
+	reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+	unsigned long flags;
+	const char *processor_modes[] = {
+	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
+	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
+	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
+	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
+	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
+	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
+	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
+	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
+	};
+
+	flags = condition_codes (regs);
+
+	printf ("pc : [<%08lx>]	   lr : [<%08lx>]\n"
+		"sp : %08lx  ip : %08lx	 fp : %08lx\n",
+		instruction_pointer (regs),
+		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+	printf ("r10: %08lx  r9 : %08lx	 r8 : %08lx\n",
+		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+	printf ("r7 : %08lx  r6 : %08lx	 r5 : %08lx  r4 : %08lx\n",
+		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+	printf ("r3 : %08lx  r2 : %08lx	 r1 : %08lx  r0 : %08lx\n",
+		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+	printf ("Flags: %c%c%c%c",
+		flags & CC_N_BIT ? 'N' : 'n',
+		flags & CC_Z_BIT ? 'Z' : 'z',
+		flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
+		interrupts_enabled (regs) ? "on" : "off",
+		fast_interrupts_enabled (regs) ? "on" : "off",
+		processor_modes[processor_mode (regs)],
+		thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+	printf ("undefined instruction\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+	printf ("software interrupt\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+	printf ("prefetch abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+	printf ("data abort\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+	printf ("not used\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+	printf ("fast interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+
+#ifndef CONFIG_USE_IRQ
+void do_irq (struct pt_regs *pt_regs)
+{
+	printf ("interrupt request\n");
+	show_regs (pt_regs);
+	bad_mode ();
+}
+#endif
diff --git a/qemu/roms/u-boot/arch/arm/lib/interrupts_64.c b/qemu/roms/u-boot/arch/arm/lib/interrupts_64.c
new file mode 100644
index 000000000..b47672255
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/interrupts_64.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+
+
+int interrupt_init(void)
+{
+	return 0;
+}
+
+void enable_interrupts(void)
+{
+	return;
+}
+
+int disable_interrupts(void)
+{
+	return 0;
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	int i;
+
+	printf("ELR:     %lx\n", regs->elr);
+	printf("LR:      %lx\n", regs->regs[30]);
+	for (i = 0; i < 29; i += 2)
+		printf("x%-2d: %016lx x%-2d: %016lx\n",
+		       i, regs->regs[i], i+1, regs->regs[i+1]);
+	printf("\n");
+}
+
+/*
+ * do_bad_sync handles the impossible case in the Synchronous Abort vector.
+ */
+void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_irq handles the impossible case in the Irq vector.
+ */
+void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_fiq handles the impossible case in the Fiq vector.
+ */
+void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_bad_error handles the impossible case in the Error vector.
+ */
+void do_bad_error(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_sync handles the Synchronous Abort exception.
+ */
+void do_sync(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_irq handles the Irq exception.
+ */
+void do_irq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Irq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_fiq handles the Fiq exception.
+ */
+void do_fiq(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Fiq\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
+
+/*
+ * do_error handles the Error exception.
+ * Errors are more likely to be processor specific,
+ * it is defined with weak attribute and can be redefined
+ * in processor specific code.
+ */
+void __weak do_error(struct pt_regs *pt_regs, unsigned int esr)
+{
+	printf("\"Error\" handler, esr 0x%08x\n", esr);
+	show_regs(pt_regs);
+	panic("Resetting CPU ...\n");
+}
diff --git a/qemu/roms/u-boot/arch/arm/lib/memcpy.S b/qemu/roms/u-boot/arch/arm/lib/memcpy.S
new file mode 100644
index 000000000..f655256b5
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/memcpy.S
@@ -0,0 +1,243 @@
+/*
+ *  linux/arch/arm/lib/memcpy.S
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Sep 28, 2005
+ *  Copyright:	MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <asm/assembler.h>
+
+#define W(instr)	instr
+
+#define LDR1W_SHIFT	0
+#define STR1W_SHIFT	0
+
+	.macro ldr1w ptr reg abort
+	W(ldr) \reg, [\ptr], #4
+	.endm
+
+	.macro ldr4w ptr reg1 reg2 reg3 reg4 abort
+	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
+	.endm
+
+	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
+	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+	.endm
+
+	.macro ldr1b ptr reg cond=al abort
+	ldr\cond\()b \reg, [\ptr], #1
+	.endm
+
+	.macro str1w ptr reg abort
+	W(str) \reg, [\ptr], #4
+	.endm
+
+	.macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
+	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+	.endm
+
+	.macro str1b ptr reg cond=al abort
+	str\cond\()b \reg, [\ptr], #1
+	.endm
+
+	.macro enter reg1 reg2
+	stmdb sp!, {r0, \reg1, \reg2}
+	.endm
+
+	.macro exit reg1 reg2
+	ldmfd sp!, {r0, \reg1, \reg2}
+	.endm
+
+	.text
+
+/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
+
+.globl memcpy
+memcpy:
+
+		cmp	r0, r1
+		moveq	pc, lr
+
+		enter	r4, lr
+
+		subs	r2, r2, #4
+		blt	8f
+		ands	ip, r0, #3
+	PLD(	pld	[r1, #0]		)
+		bne	9f
+		ands	ip, r1, #3
+		bne	10f
+
+1:		subs	r2, r2, #(28)
+		stmfd	sp!, {r5 - r8}
+		blt	5f
+
+	CALGN(	ands	ip, r0, #31		)
+	CALGN(	rsb	r3, ip, #32		)
+	CALGN(	sbcnes	r4, r3, r2		)  @ C is always set here
+	CALGN(	bcs	2f			)
+	CALGN(	adr	r4, 6f			)
+	CALGN(	subs	r2, r2, r3		)  @ C gets set
+	CALGN(	add	pc, r4, ip		)
+
+	PLD(	pld	[r1, #0]		)
+2:	PLD(	subs	r2, r2, #96		)
+	PLD(	pld	[r1, #28]		)
+	PLD(	blt	4f			)
+	PLD(	pld	[r1, #60]		)
+	PLD(	pld	[r1, #92]		)
+
+3:	PLD(	pld	[r1, #124]		)
+4:		ldr8w	r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+		subs	r2, r2, #32
+		str8w	r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+		bge	3b
+	PLD(	cmn	r2, #96			)
+	PLD(	bge	4b			)
+
+5:		ands	ip, r2, #28
+		rsb	ip, ip, #32
+#if LDR1W_SHIFT > 0
+		lsl	ip, ip, #LDR1W_SHIFT
+#endif
+		addne	pc, pc, ip		@ C is always clear here
+		b	7f
+6:
+		.rept	(1 << LDR1W_SHIFT)
+		W(nop)
+		.endr
+		ldr1w	r1, r3, abort=20f
+		ldr1w	r1, r4, abort=20f
+		ldr1w	r1, r5, abort=20f
+		ldr1w	r1, r6, abort=20f
+		ldr1w	r1, r7, abort=20f
+		ldr1w	r1, r8, abort=20f
+		ldr1w	r1, lr, abort=20f
+
+#if LDR1W_SHIFT < STR1W_SHIFT
+		lsl	ip, ip, #STR1W_SHIFT - LDR1W_SHIFT
+#elif LDR1W_SHIFT > STR1W_SHIFT
+		lsr	ip, ip, #LDR1W_SHIFT - STR1W_SHIFT
+#endif
+		add	pc, pc, ip
+		nop
+		.rept	(1 << STR1W_SHIFT)
+		W(nop)
+		.endr
+		str1w	r0, r3, abort=20f
+		str1w	r0, r4, abort=20f
+		str1w	r0, r5, abort=20f
+		str1w	r0, r6, abort=20f
+		str1w	r0, r7, abort=20f
+		str1w	r0, r8, abort=20f
+		str1w	r0, lr, abort=20f
+
+	CALGN(	bcs	2b			)
+
+7:		ldmfd	sp!, {r5 - r8}
+
+8:		movs	r2, r2, lsl #31
+		ldr1b	r1, r3, ne, abort=21f
+		ldr1b	r1, r4, cs, abort=21f
+		ldr1b	r1, ip, cs, abort=21f
+		str1b	r0, r3, ne, abort=21f
+		str1b	r0, r4, cs, abort=21f
+		str1b	r0, ip, cs, abort=21f
+
+		exit	r4, pc
+
+9:		rsb	ip, ip, #4
+		cmp	ip, #2
+		ldr1b	r1, r3, gt, abort=21f
+		ldr1b	r1, r4, ge, abort=21f
+		ldr1b	r1, lr, abort=21f
+		str1b	r0, r3, gt, abort=21f
+		str1b	r0, r4, ge, abort=21f
+		subs	r2, r2, ip
+		str1b	r0, lr, abort=21f
+		blt	8b
+		ands	ip, r1, #3
+		beq	1b
+
+10:		bic	r1, r1, #3
+		cmp	ip, #2
+		ldr1w	r1, lr, abort=21f
+		beq	17f
+		bgt	18f
+
+
+		.macro	forward_copy_shift pull push
+
+		subs	r2, r2, #28
+		blt	14f
+
+	CALGN(	ands	ip, r0, #31		)
+	CALGN(	rsb	ip, ip, #32		)
+	CALGN(	sbcnes	r4, ip, r2		)  @ C is always set here
+	CALGN(	subcc	r2, r2, ip		)
+	CALGN(	bcc	15f			)
+
+11:		stmfd	sp!, {r5 - r9}
+
+	PLD(	pld	[r1, #0]		)
+	PLD(	subs	r2, r2, #96		)
+	PLD(	pld	[r1, #28]		)
+	PLD(	blt	13f			)
+	PLD(	pld	[r1, #60]		)
+	PLD(	pld	[r1, #92]		)
+
+12:	PLD(	pld	[r1, #124]		)
+13:		ldr4w	r1, r4, r5, r6, r7, abort=19f
+		mov	r3, lr, pull #\pull
+		subs	r2, r2, #32
+		ldr4w	r1, r8, r9, ip, lr, abort=19f
+		orr	r3, r3, r4, push #\push
+		mov	r4, r4, pull #\pull
+		orr	r4, r4, r5, push #\push
+		mov	r5, r5, pull #\pull
+		orr	r5, r5, r6, push #\push
+		mov	r6, r6, pull #\pull
+		orr	r6, r6, r7, push #\push
+		mov	r7, r7, pull #\pull
+		orr	r7, r7, r8, push #\push
+		mov	r8, r8, pull #\pull
+		orr	r8, r8, r9, push #\push
+		mov	r9, r9, pull #\pull
+		orr	r9, r9, ip, push #\push
+		mov	ip, ip, pull #\pull
+		orr	ip, ip, lr, push #\push
+		str8w	r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
+		bge	12b
+	PLD(	cmn	r2, #96			)
+	PLD(	bge	13b			)
+
+		ldmfd	sp!, {r5 - r9}
+
+14:		ands	ip, r2, #28
+		beq	16f
+
+15:		mov	r3, lr, pull #\pull
+		ldr1w	r1, lr, abort=21f
+		subs	ip, ip, #4
+		orr	r3, r3, lr, push #\push
+		str1w	r0, r3, abort=21f
+		bgt	15b
+	CALGN(	cmp	r2, #0			)
+	CALGN(	bge	11b			)
+
+16:		sub	r1, r1, #(\push / 8)
+		b	8b
+
+		.endm
+
+
+		forward_copy_shift	pull=8	push=24
+
+17:		forward_copy_shift	pull=16	push=16
+
+18:		forward_copy_shift	pull=24	push=8
diff --git a/qemu/roms/u-boot/arch/arm/lib/memset.S b/qemu/roms/u-boot/arch/arm/lib/memset.S
new file mode 100644
index 000000000..0cdf89535
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/memset.S
@@ -0,0 +1,126 @@
+/*
+ *  linux/arch/arm/lib/memset.S
+ *
+ *  Copyright (C) 1995-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  ASM optimised string functions
+ */
+#include <asm/assembler.h>
+
+	.text
+	.align	5
+	.word	0
+
+1:	subs	r2, r2, #4		@ 1 do we have enough
+	blt	5f			@ 1 bytes to align with?
+	cmp	r3, #2			@ 1
+	strltb	r1, [r0], #1		@ 1
+	strleb	r1, [r0], #1		@ 1
+	strb	r1, [r0], #1		@ 1
+	add	r2, r2, r3		@ 1 (r2 = r2 - (4 - r3))
+/*
+ * The pointer is now aligned and the length is adjusted.  Try doing the
+ * memset again.
+ */
+
+.globl memset
+memset:
+	ands	r3, r0, #3		@ 1 unaligned?
+	bne	1b			@ 1
+/*
+ * we know that the pointer in r0 is aligned to a word boundary.
+ */
+	orr	r1, r1, r1, lsl #8
+	orr	r1, r1, r1, lsl #16
+	mov	r3, r1
+	cmp	r2, #16
+	blt	4f
+
+#if ! CALGN(1)+0
+
+/*
+ * We need an extra register for this loop - save the return address and
+ * use the LR
+ */
+	str	lr, [sp, #-4]!
+	mov	ip, r1
+	mov	lr, r1
+
+2:	subs	r2, r2, #64
+	stmgeia	r0!, {r1, r3, ip, lr}	@ 64 bytes at a time.
+	stmgeia	r0!, {r1, r3, ip, lr}
+	stmgeia	r0!, {r1, r3, ip, lr}
+	stmgeia	r0!, {r1, r3, ip, lr}
+	bgt	2b
+	ldmeqfd	sp!, {pc}		@ Now <64 bytes to go.
+/*
+ * No need to correct the count; we're only testing bits from now on
+ */
+	tst	r2, #32
+	stmneia	r0!, {r1, r3, ip, lr}
+	stmneia	r0!, {r1, r3, ip, lr}
+	tst	r2, #16
+	stmneia	r0!, {r1, r3, ip, lr}
+	ldr	lr, [sp], #4
+
+#else
+
+/*
+ * This version aligns the destination pointer in order to write
+ * whole cache lines at once.
+ */
+
+	stmfd	sp!, {r4-r7, lr}
+	mov	r4, r1
+	mov	r5, r1
+	mov	r6, r1
+	mov	r7, r1
+	mov	ip, r1
+	mov	lr, r1
+
+	cmp	r2, #96
+	tstgt	r0, #31
+	ble	3f
+
+	and	ip, r0, #31
+	rsb	ip, ip, #32
+	sub	r2, r2, ip
+	movs	ip, ip, lsl #(32 - 4)
+	stmcsia	r0!, {r4, r5, r6, r7}
+	stmmiia	r0!, {r4, r5}
+	tst	ip, #(1 << 30)
+	mov	ip, r1
+	strne	r1, [r0], #4
+
+3:	subs	r2, r2, #64
+	stmgeia	r0!, {r1, r3-r7, ip, lr}
+	stmgeia	r0!, {r1, r3-r7, ip, lr}
+	bgt	3b
+	ldmeqfd	sp!, {r4-r7, pc}
+
+	tst	r2, #32
+	stmneia	r0!, {r1, r3-r7, ip, lr}
+	tst	r2, #16
+	stmneia	r0!, {r4-r7}
+	ldmfd	sp!, {r4-r7, lr}
+
+#endif
+
+4:	tst	r2, #8
+	stmneia	r0!, {r1, r3}
+	tst	r2, #4
+	strne	r1, [r0], #4
+/*
+ * When we get here, we've got less than 4 bytes to zero.  We
+ * may have an unaligned pointer as well.
+ */
+5:	tst	r2, #2
+	strneb	r1, [r0], #1
+	strneb	r1, [r0], #1
+	tst	r2, #1
+	strneb	r1, [r0], #1
+	mov	pc, lr
diff --git a/qemu/roms/u-boot/arch/arm/lib/relocate.S b/qemu/roms/u-boot/arch/arm/lib/relocate.S
new file mode 100644
index 000000000..803525156
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/relocate.S
@@ -0,0 +1,74 @@
+/*
+ *  relocate - common relocation function for ARM U-Boot
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * void relocate_code(addr_moni)
+ *
+ * This function relocates the monitor code.
+ *
+ * NOTE:
+ * To prevent the code below from containing references with an R_ARM_ABS32
+ * relocation record type, we never refer to linker-defined symbols directly.
+ * Instead, we declare literals which contain their relative location with
+ * respect to relocate_code, and at run time, add relocate_code back to them.
+ */
+
+ENTRY(relocate_code)
+	ldr	r1, =__image_copy_start	/* r1 <- SRC &__image_copy_start */
+	subs	r4, r0, r1		/* r4 <- relocation offset */
+	beq	relocate_done		/* skip relocation */
+	ldr	r2, =__image_copy_end	/* r2 <- SRC &__image_copy_end */
+
+copy_loop:
+	ldmia	r1!, {r10-r11}		/* copy from source address [r1]    */
+	stmia	r0!, {r10-r11}		/* copy to   target address [r0]    */
+	cmp	r1, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r2, =__rel_dyn_start	/* r2 <- SRC &__rel_dyn_start */
+	ldr	r3, =__rel_dyn_end	/* r3 <- SRC &__rel_dyn_end */
+fixloop:
+	ldmia	r2!, {r0-r1}		/* (r0,r1) <- (SRC location,fixup) */
+	and	r1, r1, #0xff
+	cmp	r1, #23			/* relative fixup? */
+	bne	fixnext
+
+	/* relative fix: increase location by offset */
+	add	r0, r0, r4
+	ldr	r1, [r0]
+	add	r1, r1, r4
+	str	r1, [r0]
+fixnext:
+	cmp	r2, r3
+	blo	fixloop
+
+relocate_done:
+
+#ifdef __XSCALE__
+	/*
+	 * On xscale, icache must be invalidated and write buffers drained,
+	 * even with cache disabled - 4.2.7 of xscale core developer's manual
+	 */
+	mcr	p15, 0, r0, c7, c7, 0	/* invalidate icache */
+	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
+#endif
+
+	/* ARMv4- don't know bx lr but the assembler fails to see that */
+
+#ifdef __ARM_ARCH_4__
+	mov        pc, lr
+#else
+	bx        lr
+#endif
+
+ENDPROC(relocate_code)
diff --git a/qemu/roms/u-boot/arch/arm/lib/relocate_64.S b/qemu/roms/u-boot/arch/arm/lib/relocate_64.S
new file mode 100644
index 000000000..5c51cae8a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/relocate_64.S
@@ -0,0 +1,77 @@
+/*
+ * relocate - common relocation function for AArch64 U-Boot
+ *
+ * (C) Copyright 2013
+ * Albert ARIBAUD <albert.u.boot@aribaud.net>
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+/*
+ * void relocate_code (addr_moni)
+ *
+ * This function relocates the monitor code.
+ * x0 holds the destination address.
+ */
+ENTRY(relocate_code)
+	stp	x29, x30, [sp, #-32]!	/* create a stack frame */
+	mov	x29, sp
+	str	x0, [sp, #16]
+	/*
+	 * Copy u-boot from flash to RAM
+	 */
+	ldr	x1, =__image_copy_start	/* x1 <- SRC &__image_copy_start */
+	subs	x9, x0, x1		/* x9 <- relocation offset */
+	b.eq	relocate_done		/* skip relocation */
+	ldr	x2, =__image_copy_end	/* x2 <- SRC &__image_copy_end */
+
+copy_loop:
+	ldp	x10, x11, [x1], #16	/* copy from source address [x1] */
+	stp	x10, x11, [x0], #16	/* copy to   target address [x0] */
+	cmp	x1, x2			/* until source end address [x2] */
+	b.lo	copy_loop
+	str	x0, [sp, #24]
+
+	/*
+	 * Fix .rela.dyn relocations
+	 */
+	ldr	x2, =__rel_dyn_start	/* x2 <- SRC &__rel_dyn_start */
+	ldr	x3, =__rel_dyn_end	/* x3 <- SRC &__rel_dyn_end */
+fixloop:
+	ldp	x0, x1, [x2], #16	/* (x0,x1) <- (SRC location, fixup) */
+	ldr	x4, [x2], #8		/* x4 <- addend */
+	and	x1, x1, #0xffffffff
+	cmp	x1, #1027		/* relative fixup? */
+	bne	fixnext
+
+	/* relative fix: store addend plus offset at dest location */
+	add	x0, x0, x9
+	add	x4, x4, x9
+	str	x4, [x0]
+fixnext:
+	cmp	x2, x3
+	b.lo	fixloop
+
+relocate_done:
+	switch_el x1, 3f, 2f, 1f
+	bl	hang
+3:	mrs	x0, sctlr_el3
+	b	0f
+2:	mrs	x0, sctlr_el2
+	b	0f
+1:	mrs	x0, sctlr_el1
+0:	tbz	w0, #2, 5f	/* skip flushing cache if disabled */
+	tbz	w0, #12, 4f	/* invalide i-cache is enabled */
+	ic	iallu		/* i-cache invalidate all */
+	isb	sy
+4:	ldp	x0, x1, [sp, #16]
+	bl	__asm_flush_dcache_range
+5:	ldp	x29, x30, [sp],#16
+	ret
+ENDPROC(relocate_code)
diff --git a/qemu/roms/u-boot/arch/arm/lib/reset.c b/qemu/roms/u-boot/arch/arm/lib/reset.c
new file mode 100644
index 000000000..7a0358071
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/reset.c
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	puts ("resetting ...\n");
+
+	udelay (50000);				/* wait 50 ms */
+
+	disable_interrupts();
+	reset_cpu(0);
+
+	/*NOTREACHED*/
+	return 0;
+}
diff --git a/qemu/roms/u-boot/arch/arm/lib/sections.c b/qemu/roms/u-boot/arch/arm/lib/sections.c
new file mode 100644
index 000000000..5b30bcb9a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/sections.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/**
+ * These two symbols are declared in a C file so that the linker
+ * uses R_ARM_RELATIVE relocation, rather than the R_ARM_ABS32 one
+ * it would use if the symbols were defined in the linker file.
+ * Using only R_ARM_RELATIVE relocation ensures that references to
+ * the symbols are correct after as well as before relocation.
+ *
+ * We need a 0-byte-size type for these symbols, and the compiler
+ * does not allow defining objects of C type 'void'. Using an empty
+ * struct is allowed by the compiler, but causes gcc versions 4.4 and
+ * below to complain about aliasing. Therefore we use the next best
+ * thing: zero-sized arrays, which are both 0-byte-size and exempt from
+ * aliasing warnings.
+ */
+
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
+char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
+char _end[0] __attribute__((section(".__end")));
diff --git a/qemu/roms/u-boot/arch/arm/lib/spl.c b/qemu/roms/u-boot/arch/arm/lib/spl.c
new file mode 100644
index 000000000..dfcc59681
--- /dev/null
+++ b/qemu/roms/u-boot/arch/arm/lib/spl.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2010-2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Tom Rini <trini@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <spl.h>
+#include <image.h>
+#include <linux/compiler.h>
+
+/* Pointer to as well as the global data structure for SPL */
+DECLARE_GLOBAL_DATA_PTR;
+gd_t gdata __attribute__ ((section(".data")));
+
+/*
+ * In the context of SPL, board_init_f must ensure that any clocks/etc for
+ * DDR are enabled, ensure that the stack pointer is valid, clear the BSS
+ * and call board_init_f.  We provide this version by default but mark it
+ * as __weak to allow for platforms to do this in their own way if needed.
+ */
+void __weak board_init_f(ulong dummy)
+{
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Set global data pointer. */
+	gd = &gdata;
+
+	board_init_r(NULL, 0);
+}
+
+/*
+ * This function jumps to an image with argument. Normally an FDT or ATAGS
+ * image.
+ * arg: Pointer to paramter image in RAM
+ */
+#ifdef CONFIG_SPL_OS_BOOT
+void __noreturn jump_to_image_linux(void *arg)
+{
+	unsigned long machid = 0xffffffff;
+#ifdef CONFIG_MACH_TYPE
+	machid = CONFIG_MACH_TYPE;
+#endif
+
+	debug("Entering kernel arg pointer: 0x%p\n", arg);
+	typedef void (*image_entry_arg_t)(int, int, void *)
+		__attribute__ ((noreturn));
+	image_entry_arg_t image_entry =
+		(image_entry_arg_t) spl_image.entry_point;
+	cleanup_before_linux();
+	image_entry(0, machid, arg);
+}
+#endif